diff --git a/.gitignore b/.gitignore index 1363260..4ec2e96 100644 --- a/.gitignore +++ b/.gitignore @@ -116,3 +116,6 @@ out/ tmp/ *.cbuild.yml *.cbuild-idx.yml +*.cbuild-pack.yml +*.cbuild-set.yml + diff --git a/cmsis-pack-examples/README.md b/cmsis-pack-examples/README.md index 3939840..727740a 100644 --- a/cmsis-pack-examples/README.md +++ b/cmsis-pack-examples/README.md @@ -42,17 +42,19 @@ Currently, the following examples are supported: Target platforms supported: -| Name | Type | IP | Examples | -|-----------------------|---------------------|-----------------------------------------------|----------| -| Arm® Corstone™-300 | Virtual or physical | Arm® Cortex®-M55 CPU | All | -| Arm® Corstone™-300-U55 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U55 | All | -| Arm® Corstone™-300-U65 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U65 | All | -| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU | All | -| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U55 | All | -| Arm® Corstone™-310-U65 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U65 NPU | All | +| Name | Type | IP | Examples | +|------------------------------|---------------------|-----------------------------------------------|----------| +| Arm® Corstone™-300 | Virtual or physical | Arm® Cortex®-M55 CPU | All | +| Arm® Corstone™-300-U55 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U55 | All | +| Arm® Corstone™-300-U65 | Virtual or physical | Arm® Cortex®-M55 CPU with Arm® Ethos™-U65 | All | +| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU | All | +| Arm® Corstone™-310 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U55 | All | +| Arm® Corstone™-310-U65 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U65 NPU | All | +| Arm® Corstone™-315 | Virtual or physical | Arm® Cortex®-M85 CPU | All | +| Arm® Corstone™-315-U65 | Virtual or physical | Arm® Cortex®-M85 CPU with Arm® Ethos™-U65 NPU | All | | Alif™ Ensemble™ E7 AI/ML Kit | Physical board | Arm® Cortex®-M55 CPU with Arm® Ethos™-U55 NPU | All | -| STM32® F746G-Discovery| Physical board | Arm® Cortex®-M7 CPU | KWS | -| NXP® FRDM-K64F | Physical board | Arm® Cortex®-M4 CPU | KWS | +| STM32® F746G-Discovery | Physical board | Arm® Cortex®-M7 CPU | KWS | +| NXP® FRDM-K64F | Physical board | Arm® Cortex®-M4 CPU | KWS | Use this import button to open the solution in Keil Studio Cloud: [![Open in Keil Studio](https://img.shields.io/badge/Keil%20Studio-Import-blue?logo=data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0iMS4wIiBlbmNvZGluZz0idXRmLTgiPz4NCjwhLS0gR2VuZXJhdG9yOiBBZG9iZSBJbGx1c3RyYXRvciAyNS40LjEsIFNWRyBFeHBvcnQgUGx1Zy1JbiAuIFNWRyBWZXJzaW9uOiA2LjAwIEJ1aWxkIDApICAtLT4NCjxzdmcgdmVyc2lvbj0iMS4xIiBpZD0iTGF5ZXJfMSIgeG1sbnM9Imh0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnIiB4bWxuczp4bGluaz0iaHR0cDovL3d3dy53My5vcmcvMTk5OS94bGluayIgeD0iMHB4IiB5PSIwcHgiDQoJIHZpZXdCb3g9IjAgMCA0NyAxNCIgc3R5bGU9ImVuYWJsZS1iYWNrZ3JvdW5kOm5ldyAwIDAgNDcgMTQ7IiB4bWw6c3BhY2U9InByZXNlcnZlIj4NCjxzdHlsZSB0eXBlPSJ0ZXh0L2NzcyI+DQoJLnN0MHtmaWxsOiNGRkZGRkY7fQ0KPC9zdHlsZT4NCjxwYXRoIGNsYXNzPSJzdDAiIGQ9Ik00LjcsN2MwLDIuMiwxLjQsNC4xLDMuNSw0LjFjMS44LDAsMy42LTEuNCwzLjYtNC4xYzAtMi44LTEuNy00LjItMy42LTQuMkM2LjIsMi45LDQuNyw0LjcsNC43LDcgTTExLjYsMC41DQoJaDIuOXYxM2gtMi45di0xLjNjLTAuOSwxLjEtMi4zLDEuNy0zLjcsMS43QzQsMTMuOSwxLjgsMTAuNiwxLjgsN2MwLTQuMywyLjctNi45LDYuMS02LjljMS41LDAsMi44LDAuNywzLjcsMS45VjAuNXoiLz4NCjxwYXRoIGNsYXNzPSJzdDAiIGQ9Ik0xOCwwLjVIMjF2MS4yYzAuMy0wLjQsMC43LTAuOCwxLjItMS4xYzAuNS0wLjMsMS4yLTAuNCwxLjctMC40YzAuOCwwLDEuNiwwLjIsMi4zLDAuNmwtMS4yLDIuOA0KCWMtMC40LTAuMy0xLTAuNC0xLjUtMC40Yy0wLjctMC4xLTEuMywwLjItMS44LDAuN0MyMSw0LjYsMjEsNS45LDIxLDYuOHY2LjdIMThWMC41eiIvPg0KPHBhdGggY2xhc3M9InN0MCIgZD0iTTI4LjIsMC41aDIuOXYxLjJjMC43LTAuOSwxLjktMS42LDMuMS0xLjZjMS4zLDAsMi42LDAuNywzLjIsMS45YzAuOS0xLjIsMi4yLTEuOSwzLjctMS45DQoJQzQyLjcsMCw0NCwwLjksNDQuNywyLjJjMC4yLDAuNCwwLjcsMS40LDAuNywzLjN2OC4xaC0yLjlWNi4zYzAtMS41LTAuMi0yLjEtMC4yLTIuM2MtMC4yLTAuNy0wLjktMS4yLTEuNy0xLjENCgljLTAuNywwLTEuMywwLjMtMS43LDAuOWMtMC41LDAuOC0wLjYsMS45LTAuNiwyLjl2Ni43aC0yLjlWNi4zYzAtMS41LTAuMi0yLjEtMC4yLTIuM2MtMC4yLTAuNy0wLjktMS4yLTEuNy0xLjENCgljLTAuNywwLTEuMywwLjMtMS43LDAuOWMtMC41LDAuOC0wLjYsMS45LTAuNiwyLjl2Ni43aC0yLjlMMjguMiwwLjV6Ii8+DQo8L3N2Zz4NCg==&logoWidth=47)](https://studio.keil.arm.com/?import=https://github.com/Arm-Examples/mlek-cmsis-pack-examples.git) @@ -130,7 +132,7 @@ In addition to the above, the VSI Python scripts depend on `opencv-python` packa a virtual environment and installing this with pip. ```shell -$ pip install opencv-python +$ pip install opencv-python "numpy<2.0.0" ``` **NOTE**: The requirement for Python version is driven by the FVP executable. Versions <= 11.26 require @@ -249,12 +251,14 @@ $ cp ./out/kws/STM32F746-DISCO/Release/kws.Release+STM32F746-DISCO.bin /media/us ### Working with Virtual Streaming Interface -The object detection example for Arm Corstone-300 and Corstone-310 supports Virtual Streaming Interface (VSI). +The object detection example supports the Virtual Streaming Interface (VSI) feature found in the FVPs for Arm Corstone-300, Corstone-310 and Corstone-315. This allows the locally installed FVP application (or an AVH instance) to read images in from a camera connected to your local machine and stream these over to the application running within the FVP. To run the VSI application, append the command line with the v_path argument. For example: +#### Arm Corstone-300 + Arm Corstone-310 + ```shell $ \ -a ./out/object-detection-vsi/AVH-SSE-300-U55/Release/object-detection-vsi.axf \ @@ -262,6 +266,15 @@ To run the VSI application, append the command line with the v_path argument. Fo -C mps3_board.v_path=./device/corstone/vsi/video/python/ ``` +#### Arm Corstone-315 + +```shell + $ \ + -a ./out/object-detection-vsi/AVH-SSE-315-U65/Release/object-detection-vsi.axf \ + -C ethosu.num_macs=256 \ + -C mps4_board.v_path=./device/corstone/vsi/video/python/ +``` + ## Application output Once the project can be built successfully, the execution on target hardware will show output of diff --git a/cmsis-pack-examples/device/corstone/corstone-device.clayer.yml b/cmsis-pack-examples/device/corstone/corstone-device.clayer.yml index 804b633..00f977e 100644 --- a/cmsis-pack-examples/device/corstone/corstone-device.clayer.yml +++ b/cmsis-pack-examples/device/corstone/corstone-device.clayer.yml @@ -25,10 +25,12 @@ layer: for-context: - +AVH-SSE-300 - +AVH-SSE-310 + - +AVH-SSE-315 - +AVH-SSE-300-U55 - +AVH-SSE-310-U55 - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 files: - file: src/retarget.c - file: src/uart_cmsdk_apb.c @@ -51,13 +53,16 @@ layer: for-context: - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - component: tensorflow::Machine Learning:TensorFlow:Kernel&Ethos-U for-context: - +AVH-SSE-300-U55 - +AVH-SSE-310-U55 - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - component: tensorflow::Machine Learning:TensorFlow:Kernel&CMSIS-NN for-context: - +AVH-SSE-300 - - +AVH-SSE-310 \ No newline at end of file + - +AVH-SSE-310 + - +AVH-SSE-315 \ No newline at end of file diff --git a/cmsis-pack-examples/device/corstone/src/BoardInit.cpp b/cmsis-pack-examples/device/corstone/src/BoardInit.cpp index 0923119..5f5ad7f 100644 --- a/cmsis-pack-examples/device/corstone/src/BoardInit.cpp +++ b/cmsis-pack-examples/device/corstone/src/BoardInit.cpp @@ -66,10 +66,10 @@ static void arm_ethosu_npu_irq_handler(void) /** @brief Initialises the NPU IRQ */ static void arm_ethosu_npu_irq_init(void) { - #if defined(CORSTONE310_FVP) - const IRQn_Type ethosu_irqnum = (IRQn_Type)NPU0_IRQn; - #else + #if defined(CORSTONE300_FVP) const IRQn_Type ethosu_irqnum = (IRQn_Type)ETHOS_U55_IRQn; + #else + const IRQn_Type ethosu_irqnum = (IRQn_Type)NPU0_IRQn; #endif /* Register the EthosU IRQ handler in our vector table. @@ -91,10 +91,10 @@ static int arm_ethosu_npu_init(void) arm_ethosu_npu_irq_init(); /* Initialise Ethos-U device */ - #if defined(CORSTONE310_FVP) - void* const ethosu_base_address = (void*)(NPU0_APB_BASE_NS); - #else + #if defined(CORSTONE300_FVP) void* const ethosu_base_address = (void*)(ETHOS_U55_APB_BASE_S); + #else + void* const ethosu_base_address = (void*)(NPU0_APB_BASE_NS); #endif debug("Cache arena: 0x%p\n", get_cache_arena()); diff --git a/cmsis-pack-examples/device/corstone/src/uart_cmsdk_apb.c b/cmsis-pack-examples/device/corstone/src/uart_cmsdk_apb.c index b6f4a02..75c76c8 100644 --- a/cmsis-pack-examples/device/corstone/src/uart_cmsdk_apb.c +++ b/cmsis-pack-examples/device/corstone/src/uart_cmsdk_apb.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its * affiliates * SPDX-License-Identifier: Apache-2.0 * @@ -20,6 +20,11 @@ #include "uart_config.h" #include "uart_stdout.h" + +/* Platform dependent files */ +#include "RTE_Components.h" /* Provides definition for CMSIS_device_header */ +#include CMSIS_device_header /* Gives us IRQ num, base addresses. */ + #include #include @@ -46,7 +51,7 @@ typedef struct { __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ } CMSDK_UART_TypeDef; -#define CMSDK_UART0_BASE UART0_BASE +#define CMSDK_UART0_BASE UART0_BASE_NS #define CMSDK_UART0 ((CMSDK_UART_TypeDef*)CMSDK_UART0_BASE) #define CMSDK_UART0_BAUDRATE UART0_BAUDRATE diff --git a/cmsis-pack-examples/device/corstone/src/uart_config.h b/cmsis-pack-examples/device/corstone/src/uart_config.h index aa43d1e..8d1e8f7 100644 --- a/cmsis-pack-examples/device/corstone/src/uart_config.h +++ b/cmsis-pack-examples/device/corstone/src/uart_config.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its * affiliates * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,6 @@ #ifndef _UART_CONFIG_H_ #define _UART_CONFIG_H_ -#define UART0_BASE (0x49303000) #define UART0_BAUDRATE (115200) #define SYSTEM_CORE_CLOCK (25000000) diff --git a/cmsis-pack-examples/kws/kws.cproject.yml b/cmsis-pack-examples/kws/kws.cproject.yml index be73dbf..91bdc48 100644 --- a/cmsis-pack-examples/kws/kws.cproject.yml +++ b/cmsis-pack-examples/kws/kws.cproject.yml @@ -27,8 +27,10 @@ project: for-context: - +AVH-SSE-300 - +AVH-SSE-310 + - +AVH-SSE-315 - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - +AVH-SSE-300-U55 - +AVH-SSE-310-U55 - +FRDM-K64F @@ -65,6 +67,7 @@ project: for-context: - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - file: src/kws_micronet_m.tflite.cpp for-context: @@ -72,6 +75,7 @@ project: - +STM32F746-DISCO - +AVH-SSE-300 - +AVH-SSE-310 + - +AVH-SSE-315 - group: Device Files files: @@ -85,6 +89,10 @@ project: - +AVH-SSE-310 - +AVH-SSE-310-U55 - +AVH-SSE-310-U65 + - file: linker/mps4-sse-315.sct + for-context: + - +AVH-SSE-315 + - +AVH-SSE-315-U65 - file: linker/frdm-k64f.sct for-context: +FRDM-K64F - file: linker/stm32f746-disco.sct @@ -105,6 +113,8 @@ project: - +AVH-SSE-310 - +AVH-SSE-310-U55 - +AVH-SSE-310-U65 + - +AVH-SSE-315 + - +AVH-SSE-315-U65 - layer: ../device/frdm-k64f/frdm-k64f-device.clayer.yml for-context: diff --git a/cmsis-pack-examples/kws/linker/mps3-sse-300.sct b/cmsis-pack-examples/kws/linker/mps3-sse-300.sct index cf0ab14..a180540 100644 --- a/cmsis-pack-examples/kws/linker/mps3-sse-300.sct +++ b/cmsis-pack-examples/kws/linker/mps3-sse-300.sct @@ -1,4 +1,4 @@ -; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its affiliates ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,8 +16,6 @@ ; ************************************************************* ; *** Scatter-Loading Description File *** ; ************************************************************* -; Please see docs/sections/appendix.md for memory mapping -; information. ; ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR ; sections => activation buffers and the model should diff --git a/cmsis-pack-examples/kws/linker/mps3-sse-310.sct b/cmsis-pack-examples/kws/linker/mps3-sse-310.sct index d9de5d1..6d24e33 100644 --- a/cmsis-pack-examples/kws/linker/mps3-sse-310.sct +++ b/cmsis-pack-examples/kws/linker/mps3-sse-310.sct @@ -1,4 +1,4 @@ -; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its affiliates ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,14 +16,11 @@ ; ************************************************************* ; *** Scatter-Loading Description File *** ; ************************************************************* -; Please see docs/sections/appendix.md for memory mapping -; information. ; ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR ; sections => activation buffers and the model should ; only be placed in those regions. ; - ;--------------------------------------------------------- ; First load region (SRAM/BRAM) 2MiB region ;--------------------------------------------------------- diff --git a/cmsis-pack-examples/kws/linker/mps4-sse-315.sct b/cmsis-pack-examples/kws/linker/mps4-sse-315.sct new file mode 100644 index 0000000..6f22695 --- /dev/null +++ b/cmsis-pack-examples/kws/linker/mps4-sse-315.sct @@ -0,0 +1,151 @@ +; SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; +;--------------------------------------------------------- +; First load region (SRAM) 64KiB boot region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00010000 +{ + ;----------------------------------------------------- + ; 64K boot ROM. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + boot.bin 0x11000000 0x00010000 + { + *.o (RESET, +First) + *(InRoot$$Sections) + } +} + +;--------------------------------------------------------- +; Second load region (FPGA SRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_1 0X12000000 0x00200000 +{ + ;----------------------------------------------------- + ; First 640K of SRAM/BRAM region for RO code, + ; 8 byte aligned. + ;----------------------------------------------------- + bram.bin 0x12000000 ALIGN 8 0x000A0000 + { + ; Essentially only RO (code) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 384K of SRAM/BRAM region for RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x120A0000 ALIGN 8 0x00060000 + { + ; Any RO-DATA + .ANY (+RO-DATA) + + ; Any R/W and/or zero initialised data + .ANY(+RW +ZI) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x12100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + ; Cache area (if used) + *.o (.bss.NoInit.ethos_u_cache) + + ; activation buffers a.k.a tensor arena when + ; memory mode sram only or shared sram + *.o (.bss.NoInit.activation_buf_sram) + } +} + +;--------------------------------------------------------- +; Third load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_2 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + ; nn model's baked in input matrices + *.o (ifm) + + ; nn model's default space + *.o (nn_model) + + ; labels + *.o (labels) + Labels.o (+RO-DATA) + + ; activation buffers a.k.a tensor arena when memory mode dedicated sram + *.o (activation_buf_dram) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} diff --git a/cmsis-pack-examples/mlek.csolution.yml b/cmsis-pack-examples/mlek.csolution.yml index 199f6a3..0651110 100644 --- a/cmsis-pack-examples/mlek.csolution.yml +++ b/cmsis-pack-examples/mlek.csolution.yml @@ -35,6 +35,7 @@ solution: - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 - pack: ARM::V2M_MPS3_SSE_310_BSP@1.4.0 + - pack: ARM::SSE_315_BSP@1.0.0 - pack: NXP::FRDM-K64F_BSP@14.0.0 - pack: NXP::MK64F12_DFP@14.0.0 - pack: Keil::STM32F7xx_DFP@2.15.1 @@ -75,6 +76,10 @@ solution: define: - ETHOSU55 + - type: AVH-SSE-315 + board: ARM::SSE-315 + device: ARM::SSE-315-FVP + - type: FRDM-K64F board: NXP::FRDM-K64F device: MK64FN1M0VLL12 @@ -112,16 +117,24 @@ solution: define: - ETHOSU65 + - type: AVH-SSE-315-U65 + board: ARM::SSE-315 + device: ARM::SSE-315-FVP + define: + - ETHOSU65 + projects: # Object detection use case - project: ./object-detection/object-detection.cproject.yml for-context: - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - +AVH-SSE-300-U55 - +AVH-SSE-310-U55 - +AVH-SSE-300 - +AVH-SSE-310 + - +AVH-SSE-315 - +Alif-E7-M55-HP # Object detection with Virtual Streaming Interface (VSI) support @@ -129,20 +142,24 @@ solution: for-context: - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - +AVH-SSE-300-U55 - +AVH-SSE-310-U55 - +AVH-SSE-300 - +AVH-SSE-310 + - +AVH-SSE-315 # Keyword Spotting (KWS) use case - project: ./kws/kws.cproject.yml for-context: - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - +AVH-SSE-300-U55 - +AVH-SSE-310-U55 - +AVH-SSE-300 - +AVH-SSE-310 + - +AVH-SSE-315 - +FRDM-K64F - +STM32F746-DISCO - +Alif-E7-M55-HE diff --git a/cmsis-pack-examples/object-detection/linker/mps3-sse-300.sct b/cmsis-pack-examples/object-detection/linker/mps3-sse-300.sct index cf0ab14..a180540 100644 --- a/cmsis-pack-examples/object-detection/linker/mps3-sse-300.sct +++ b/cmsis-pack-examples/object-detection/linker/mps3-sse-300.sct @@ -1,4 +1,4 @@ -; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its affiliates ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,8 +16,6 @@ ; ************************************************************* ; *** Scatter-Loading Description File *** ; ************************************************************* -; Please see docs/sections/appendix.md for memory mapping -; information. ; ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR ; sections => activation buffers and the model should diff --git a/cmsis-pack-examples/object-detection/linker/mps3-sse-310.sct b/cmsis-pack-examples/object-detection/linker/mps3-sse-310.sct index d9de5d1..6d24e33 100644 --- a/cmsis-pack-examples/object-detection/linker/mps3-sse-310.sct +++ b/cmsis-pack-examples/object-detection/linker/mps3-sse-310.sct @@ -1,4 +1,4 @@ -; Copyright (c) 2021-2022 Arm Limited. All rights reserved. +; SPDX-FileCopyrightText: Copyright 2021-2022, 2024 Arm Limited and/or its affiliates ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,14 +16,11 @@ ; ************************************************************* ; *** Scatter-Loading Description File *** ; ************************************************************* -; Please see docs/sections/appendix.md for memory mapping -; information. ; ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR ; sections => activation buffers and the model should ; only be placed in those regions. ; - ;--------------------------------------------------------- ; First load region (SRAM/BRAM) 2MiB region ;--------------------------------------------------------- diff --git a/cmsis-pack-examples/object-detection/linker/mps4-sse-315.sct b/cmsis-pack-examples/object-detection/linker/mps4-sse-315.sct new file mode 100644 index 0000000..6f22695 --- /dev/null +++ b/cmsis-pack-examples/object-detection/linker/mps4-sse-315.sct @@ -0,0 +1,151 @@ +; SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should +; only be placed in those regions. +; +;--------------------------------------------------------- +; First load region (SRAM) 64KiB boot region +;--------------------------------------------------------- +LOAD_REGION_0 0x11000000 0x00010000 +{ + ;----------------------------------------------------- + ; 64K boot ROM. Our vector table also + ; resides here as the default INITSVTOR is 0x11000000. + ; We currently do not use the ITCM for any code, but + ; could potentially put some critical code in there + ; if we need to. + ;----------------------------------------------------- + boot.bin 0x11000000 0x00010000 + { + *.o (RESET, +First) + *(InRoot$$Sections) + } +} + +;--------------------------------------------------------- +; Second load region (FPGA SRAM) 2MiB region +;--------------------------------------------------------- +LOAD_REGION_1 0X12000000 0x00200000 +{ + ;----------------------------------------------------- + ; First 640K of SRAM/BRAM region for RO code, + ; 8 byte aligned. + ;----------------------------------------------------- + bram.bin 0x12000000 ALIGN 8 0x000A0000 + { + ; Essentially only RO (code) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Next 384K of SRAM/BRAM region for RW and ZI + ; data, 8 byte aligned. + ;----------------------------------------------------- + data.bin 0x120A0000 ALIGN 8 0x00060000 + { + ; Any RO-DATA + .ANY (+RO-DATA) + + ; Any R/W and/or zero initialised data + .ANY(+RW +ZI) + } + + ;----------------------------------------------------- + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. + ;----------------------------------------------------- + ARM_LIB_HEAP 0x12100000 EMPTY ALIGN 8 0x000C0000 + {} + + ;----------------------------------------------------- + ; 32 kiB of stack space occupying the DTCM region. + ;----------------------------------------------------- + ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000 + {} + + ;----------------------------------------------------- + ; FPGA internal SRAM of 2MiB - reserved for activation + ; buffers. The total memory is 4 MiB (we are choosing + ; to not use the other bank). This region should have + ; 3 cycle read latency from both CPU and Ethos-U NPU. + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 + { + ; Cache area (if used) + *.o (.bss.NoInit.ethos_u_cache) + + ; activation buffers a.k.a tensor arena when + ; memory mode sram only or shared sram + *.o (.bss.NoInit.activation_buf_sram) + } +} + +;--------------------------------------------------------- +; Third load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_2 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DDR space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + ddr.bin 0x70000000 ALIGN 16 0x02000000 + { + ; nn model's baked in input matrices + *.o (ifm) + + ; nn model's default space + *.o (nn_model) + + ; labels + *.o (labels) + Labels.o (+RO-DATA) + + ; activation buffers a.k.a tensor arena when memory mode dedicated sram + *.o (activation_buf_dram) + } + + ;----------------------------------------------------- + ; The following regions are for use by the FVP to + ; allow loading or dumping of dynamic data into or + ; from the memory. These regions are mentioned in + ; the CMake subsystem profile. Do not change the + ; addresses and sizes below in isolation. + ;----------------------------------------------------- + ; 32 MiB of model space for run-time load of model + ;----------------------------------------------------- + runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of IFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 + {} + + ;----------------------------------------------------- + ; 16 MiB of OFM space for run-time loading (FVP only) + ;----------------------------------------------------- + runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 + {} +} diff --git a/cmsis-pack-examples/object-detection/object-detection-vsi.cproject.yml b/cmsis-pack-examples/object-detection/object-detection-vsi.cproject.yml index 30d09fd..5bc7d00 100644 --- a/cmsis-pack-examples/object-detection/object-detection-vsi.cproject.yml +++ b/cmsis-pack-examples/object-detection/object-detection-vsi.cproject.yml @@ -38,4 +38,6 @@ project: - +AVH-SSE-310 - +AVH-SSE-310-U55 - +AVH-SSE-310-U65 + - +AVH-SSE-315 + - +AVH-SSE-315-U65 - layer: ./object-detection.clayer.yml diff --git a/cmsis-pack-examples/object-detection/object-detection.clayer.yml b/cmsis-pack-examples/object-detection/object-detection.clayer.yml index b7673e0..d05cb08 100644 --- a/cmsis-pack-examples/object-detection/object-detection.clayer.yml +++ b/cmsis-pack-examples/object-detection/object-detection.clayer.yml @@ -26,6 +26,7 @@ layer: for-context: - +AVH-SSE-300 - +AVH-SSE-310 + - +AVH-SSE-315 - file: src/yolo-fastest_192_face_v4_vela_H256.tflite.cpp for-context: - +AVH-SSE-300-U55 @@ -35,6 +36,7 @@ layer: for-context: - +AVH-SSE-300-U65 - +AVH-SSE-310-U65 + - +AVH-SSE-315-U65 - group: Device Files files: @@ -48,6 +50,10 @@ layer: - +AVH-SSE-310 - +AVH-SSE-310-U55 - +AVH-SSE-310-U65 + - file: linker/mps4-sse-315.sct + for-context: + - +AVH-SSE-315 + - +AVH-SSE-315-U65 - file: linker/alif-e7-m55-hp.sct for-context: +Alif-E7-M55-HP diff --git a/cmsis-pack-examples/object-detection/object-detection.cproject.yml b/cmsis-pack-examples/object-detection/object-detection.cproject.yml index fb27861..9d5115b 100644 --- a/cmsis-pack-examples/object-detection/object-detection.cproject.yml +++ b/cmsis-pack-examples/object-detection/object-detection.cproject.yml @@ -31,6 +31,8 @@ project: - +AVH-SSE-310 - +AVH-SSE-310-U55 - +AVH-SSE-310-U65 + - +AVH-SSE-315 + - +AVH-SSE-315-U65 files: - file: include/InputFiles.hpp - file: src/InputFiles.cpp @@ -54,9 +56,11 @@ project: - +AVH-SSE-310 - +AVH-SSE-310-U55 - +AVH-SSE-310-U65 + - +AVH-SSE-315 + - +AVH-SSE-315-U65 - layer: ../device/alif-ensemble/alif-ensemble-E7-device.clayer.yml for-context: - +Alif-E7-M55-HP - - layer: ./object-detection.clayer.yml + - layer: ./object-detection.clayer.yml \ No newline at end of file