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[NUC472] Sync SPI mode with NUC472 BSP V3.02.001
1 parent d885de6 commit 6b8724b

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+41
-68
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2 files changed

+41
-68
lines changed

‎targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.c‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/****************************************************************************//**
22
* @file spi.c
33
* @version V0.10
4-
* $Revision: 15 $
5-
* $Date: 14/09/30 1:10p $
4+
* $Revision: 16 $
5+
* $Date: 15/06/18 4:00p $
66
* @brief NUC472/NUC442 SPI driver source file
77
*
88
* @note
@@ -102,7 +102,7 @@ void SPI_ClearTxFIFO(SPI_T *spi)
102102
*/
103103
void SPI_DisableAutoSS(SPI_T *spi)
104104
{
105-
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
105+
spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
106106
}
107107

108108
/**
@@ -118,7 +118,7 @@ void SPI_DisableAutoSS(SPI_T *spi)
118118
*/
119119
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
120120
{
121-
spi->SSCTL |= (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
121+
spi->SSCTL = (spi->SSCTL & ~(SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
122122
}
123123

124124
/**
@@ -153,12 +153,15 @@ uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
153153
u32ClkSrc = CLK_GetPLLClockFreq();
154154
}
155155

156+
if(u32BusClock > u32ClkSrc)
157+
u32BusClock = u32ClkSrc;
156158

157159
if(u32BusClock != 0 ) {
158160
u32Div = (u32ClkSrc / u32BusClock) - 1;
159161
if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
160162
u32Div = SPI_CLKDIV_DIVIDER_Msk;
161-
}
163+
} else
164+
return 0;
162165

163166
spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
164167

‎targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.h‎

Lines changed: 33 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/****************************************************************************//**
22
* @file spi.h
33
* @version V1.00
4-
* $Revision: 18 $
5-
* $Date: 14/10/06 1:36p $
4+
* $Revision: 21 $
5+
* $Date: 15/06/18 4:12p $
66
* @brief NUC472/NUC442 SPI driver header file
77
*
88
* @note
@@ -31,8 +31,8 @@ extern "C"
3131

3232
#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 \hideinitializer */
3333
#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 \hideinitializer */
34-
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 \hideinitializer */
35-
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 \hideinitializer */
34+
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 \hideinitializer */
35+
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 \hideinitializer */
3636

3737
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
3838
#define SPI_MASTER (0x0) /*!< Set as master \hideinitializer */
@@ -70,7 +70,7 @@ extern "C"
7070
* @return none
7171
* \hideinitializer
7272
*/
73-
#define SPI_SET_SLAVE_TIMEOUT_PERIOD(spi, u32TimeoutPeriod) ( (spi)->SSCTL = ((spi)->SSCTL & ~SPI_SSCTL_SLVTOCNT_Msk) | (u32TimeoutPeriod & 0xFFFF) )
73+
#define SPI_SET_SLAVE_TIMEOUT_PERIOD(spi, u32TimeoutPeriod) ( (spi)->SSCTL = ((spi)->SSCTL & ~SPI_SSCTL_SLVTOCNT_Msk) | (((uint32_t)u32TimeoutPeriod & 0xFFFF) << SPI_SSCTL_SLVTOCNT_Pos) )
7474

7575
/**
7676
* @brief Enable time out clear function for FIFO mode.
@@ -194,56 +194,41 @@ extern "C"
194194
#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
195195

196196
/**
197-
* @brief Disable automatic slave select function and set SPI_SS pin to high state.
198-
* @param[in] spi is the base address of SPI module.
199-
* @return none
197+
* @brief Set SPIn_SS0 pin to high state.
198+
* @param[in] spi The pointer of the specified SPI module.
199+
* @return None.
200+
* @details Disable automatic slave selection function and set SPIn_SS0 pin to high state. Only available in Master mode.
200201
* \hideinitializer
201202
*/
202-
static __INLINE void SPI_SET_SS0_HIGH(SPI_T *spi)
203-
{
204-
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
205-
spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
206-
spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS0;
207-
}
203+
#define SPI_SET_SS0_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS0)))
208204

209205
/**
210-
* @brief Disable automatic slave select function and set SPI_SS pin to low state.
211-
* @param[in] spi is the base address of SPI module.
212-
* @return none
206+
* @brief Set SPIn_SS0 pin to low state.
207+
* @param[in] spi The pointer of the specified SPI module.
208+
* @return None.
209+
* @details Disable automatic slave selection function and set SPIn_SS0 pin to low state. Only available in Master mode.
213210
* \hideinitializer
214211
*/
215-
static __INLINE void SPI_SET_SS0_LOW(SPI_T *spi)
216-
{
217-
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
218-
spi->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
219-
spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS0;
220-
}
212+
#define SPI_SET_SS0_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS0)) | SPI_SS0)
221213

222214
/**
223-
* @brief Disable automatic slave select function and set SPI_SS pin to high state.
224-
* @param[in] spi is the base address of SPI module.
225-
* @return none
215+
* @brief Set SPIn_SS1 pin to high state.
216+
* @param[in] spi The pointer of the specified SPI module.
217+
* @return None.
218+
* @details Disable automatic slave selection function and set SPIn_SS1 pin to high state. Only available in Master mode.
226219
* \hideinitializer
227220
*/
228-
static __INLINE void SPI_SET_SS1_HIGH(SPI_T *spi)
229-
{
230-
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
231-
spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
232-
spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS1;
233-
}
221+
#define SPI_SET_SS1_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS1)))
234222

235223
/**
236-
* @brief Disable automatic slave select function and set SPI_SS pin to low state.
237-
* @param[in] spi is the base address of SPI module.
238-
* @return none
224+
* @brief Set SPIn_SS1 pin to low state.
225+
* @param[in] spi The pointer of the specified SPI module.
226+
* @return None.
227+
* @details Disable automatic slave selection function and set SPIn_SS1 pin to low state. Only available in Master mode.
239228
* \hideinitializer
240229
*/
241-
static __INLINE void SPI_SET_SS1_LOW(SPI_T *spi)
242-
{
243-
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
244-
spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
245-
spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS1;
246-
}
230+
#define SPI_SET_SS1_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS1)) | SPI_SS1)
231+
247232

248233
/**
249234
* @brief Enable byte reorder function.
@@ -341,14 +326,6 @@ static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
341326
*/
342327
#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )
343328

344-
/**
345-
* @brief Enable SPI Dual IO function.
346-
* @param[in] spi is the base address of SPI module.
347-
* @return none
348-
* \hideinitializer
349-
*/
350-
#define SPI_ENABLE_DUAL_MODE(spi) ( (spi)->CTL |= SPI_CTL_DUALIOEN_Msk )
351-
352329
/**
353330
* @brief Disable SPI Dual IO function.
354331
* @param[in] spi is the base address of SPI module.
@@ -358,28 +335,20 @@ static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
358335
#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk )
359336

360337
/**
361-
* @brief Set SPI Dual IO direction to input.
338+
* @brief Enable Dual IO function and set SPI Dual IO direction to input.
362339
* @param[in] spi is the base address of SPI module.
363340
* @return none
364341
* \hideinitializer
365342
*/
366-
#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QDIODIR_Msk )
343+
#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_QDIODIR_Msk) | SPI_CTL_DUALIOEN_Msk )
367344

368345
/**
369-
* @brief Set SPI Dual IO direction to output.
346+
* @brief Enable Dual IO function and set SPI Dual IO direction to output.
370347
* @param[in] spi is the base address of SPI module.
371348
* @return none
372349
* \hideinitializer
373350
*/
374-
#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk )
375-
376-
/**
377-
* @brief Enable SPI QUAD IO function.
378-
* @param[in] spi is the base address of SPI module.
379-
* @return none
380-
* \hideinitializer
381-
*/
382-
#define SPI_ENABLE_QUAD_MODE(spi) ( (spi)->CTL |= SPI_CTL_QUADIOEN_Msk )
351+
#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk )
383352

384353
/**
385354
* @brief Disable SPI Dual IO function.
@@ -395,15 +364,15 @@ static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
395364
* @return none
396365
* \hideinitializer
397366
*/
398-
#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QDIODIR_Msk )
367+
#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_QDIODIR_Msk) | SPI_CTL_QUADIOEN_Msk )
399368

400369
/**
401370
* @brief Set SPI Quad IO direction to output.
402371
* @param[in] spi is the base address of SPI module.
403372
* @return none
404373
* \hideinitializer
405374
*/
406-
#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk )
375+
#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk )
407376

408377
/**
409378
* @brief Trigger RX PDMA transfer.
@@ -489,3 +458,4 @@ void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
489458
#endif //__SPI_H__
490459

491460
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
461+

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