From e83a8abdcb844b09f578a6f6b17f0af3b74b0e0b Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Mon, 18 Nov 2019 18:13:09 +0100 Subject: [PATCH 1/6] targets: DISCO_H747I add support of MBED_TICKLESS --- .../TARGET_STM32H747xI/h747i_sleep.c | 23 ------------- targets/TARGET_STM/lp_ticker.c | 18 +++++++++++ targets/TARGET_STM/sleep.c | 32 ++++++++++++++++++- targets/targets.json | 11 +++++-- 4 files changed, 58 insertions(+), 26 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c deleted file mode 100644 index 1f71d754959..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * SPDX-License-Identifier: BSD-3-Clause - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - ******************************************************************************* - */ -#if DEVICE_SLEEP - -/* Deepsleep temporarily not supported on STM32H747I - * wrap it to sleep - */ -void hal_deepsleep(void) -{ - hal_sleep(); -} - -#endif diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index 8844bdac921..eca51b35ef6 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -67,6 +67,13 @@ #define LPTIM_MST_IRQ LPTIM4_IRQn #define LPTIM_MST_RCC __HAL_RCC_LPTIM4_CLK_ENABLE +#define LPTIM_MST_RCC_CLKAM __HAL_RCC_LPTIM4_CLKAM_ENABLE + +/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */ +#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG() {\ + HAL_EXTI_D1_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, ENABLE);\ + HAL_EXTI_D2_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, DISABLE);\ + } #define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM4_FORCE_RESET #define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM4_RELEASE_RESET @@ -85,6 +92,13 @@ #define LPTIM_MST_IRQ LPTIM5_IRQn #define LPTIM_MST_RCC __HAL_RCC_LPTIM5_CLK_ENABLE +#define LPTIM_MST_RCC_CLKAM __HAL_RCC_LPTIM5_CLKAM_ENABLE + +/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */ +#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG() {\ + HAL_EXTI_D2_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, ENABLE);\ + HAL_EXTI_D1_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, DISABLE);\ + } #define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM5_FORCE_RESET #define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM5_RELEASE_RESET #else @@ -209,6 +223,10 @@ void lp_ticker_init(void) LPTIM_MST_RESET_ON(); LPTIM_MST_RESET_OFF(); #if defined(DUAL_CORE) + /* Configure EXTI wakeup and configure autonomous mode */ + LPTIM_MST_RCC_CLKAM(); + LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG(); + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); #endif /* DUAL_CORE */ diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index d1ba586451b..a8c0dcfaa59 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -204,6 +204,25 @@ __WEAK void hal_deepsleep(void) if (!pwrClockEnabled) { __HAL_RCC_PWR_CLK_DISABLE(); } +#elif defined(DUAL_CORE) + int lowPowerModeEnabled = LL_PWR_GetRegulModeDS(); + +#if defined(CORE_CM7) + HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN); + HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D1_DOMAIN); + +#elif defined(CORE_CM4) + HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN); + HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D2_DOMAIN); + +#else +#error "Wrong Core selection" +#endif /* CORE_CM7 */ + + if (lowPowerModeEnabled) { + LL_PWR_SetRegulModeDS(lowPowerModeEnabled); + } + #else /* PWR_CR1_LPMS_STOP2 */ HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); #endif /* PWR_CR1_LPMS_STOP2 */ @@ -220,8 +239,19 @@ __WEAK void hal_deepsleep(void) ForceOscOutofDeepSleep(); ForcePeriphOutofDeepSleep(); - // After wake-up from STOP reconfigure the PLL + /* After wake-up from STOP reconfigure the PLL */ +#if defined(DUAL_CORE) + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { + } + + if ((LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)) { + LL_PWR_ClearFlag_CPU(); + SetSysClock(); + } + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#else SetSysClock(); +#endif /* Wait for clock to be stabilized. * TO DO: a better way of doing this, would be to rely on diff --git a/targets/targets.json b/targets/targets.json index 6c8a4a88a29..7fe6d2e1839 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3303,7 +3303,8 @@ "macros_add": [ "STM32H747xx", "CORE_CM7", - "EXTRA_IDLE_STACK_REQUIRED" + "EXTRA_IDLE_STACK_REQUIRED", + "MBED_TICKLESS" ], "overrides": { "lpticker_delay_ticks": 0 }, "supported_form_factors": [ @@ -3338,6 +3339,11 @@ "mbed_ram_start": "0x10000000", "mbed_ram_size" : "0x48000", "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC", + "macro_name": "CLOCK_SOURCE" + }, "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 @@ -3346,7 +3352,8 @@ "macros_add": [ "STM32H747xx", "CORE_CM4", - "EXTRA_IDLE_STACK_REQUIRED" + "EXTRA_IDLE_STACK_REQUIRED", + "MBED_TICKLESS" ], "overrides": { "lpticker_delay_ticks": 0 }, "supported_form_factors": [ From 41b038a028882172190598c3a41655f3b9e0b929 Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Wed, 27 Nov 2019 14:25:30 +0100 Subject: [PATCH 2/6] TARGET_STM: rework hal_sleep management to be compatible with all STM32 families --- targets/TARGET_STM/TARGET_STM32F0/common_objects.h | 8 ++++++++ targets/TARGET_STM/TARGET_STM32F1/common_objects.h | 1 + targets/TARGET_STM/TARGET_STM32F2/objects.h | 1 + targets/TARGET_STM/TARGET_STM32F3/common_objects.h | 1 + targets/TARGET_STM/TARGET_STM32F4/common_objects.h | 1 + targets/TARGET_STM/TARGET_STM32F7/common_objects.h | 1 + targets/TARGET_STM/TARGET_STM32H7/objects.h | 2 +- targets/TARGET_STM/TARGET_STM32L0/common_objects.h | 1 + targets/TARGET_STM/TARGET_STM32L1/common_objects.h | 1 + targets/TARGET_STM/TARGET_STM32L4/common_objects.h | 1 + targets/TARGET_STM/TARGET_STM32WB/common_objects.h | 1 + targets/TARGET_STM/sleep.c | 11 +++++++++-- 12 files changed, 27 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h index 1aa7002ec21..9b2f8a2c4f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h @@ -36,6 +36,7 @@ #include "PinNames.h" #include "stm32f0xx_ll_usart.h" #include "stm32f0xx_ll_tim.h" +#include "stm32f0xx_ll_pwr.h" #ifdef __cplusplus extern "C" { @@ -119,6 +120,13 @@ struct analogin_s { uint8_t channel; }; + +#ifdef CRC_PROG_POLYNOMIAL_SUPPORT +#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 7 || (width) == 8 || (width) == 16 || (width) == 32) +#else +#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 32 && (polynomial) == 0x04C11DB7) +#endif + #include "gpio_object.h" #if DEVICE_ANALOGOUT diff --git a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h index fa962a47267..b5bdf04f785 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h @@ -36,6 +36,7 @@ #include "PinNames.h" #include "stm32f1xx_ll_usart.h" #include "stm32f1xx_ll_tim.h" +#include "stm32f1xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h index c9d7da1a64b..4a171ac5291 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h @@ -36,6 +36,7 @@ #include "PinNames.h" #include "stm32f2xx_ll_usart.h" #include "stm32f2xx_ll_tim.h" +#include "stm32f2xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h index 7e6d4721547..70b17c4d6ac 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h @@ -36,6 +36,7 @@ #include "PinNames.h" #include "stm32f3xx_ll_usart.h" #include "stm32f3xx_ll_tim.h" +#include "stm32f3xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h index 00129513d57..548d2660d47 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h @@ -36,6 +36,7 @@ #include "PinNames.h" #include "stm32f4xx_ll_usart.h" #include "stm32f4xx_ll_tim.h" +#include "stm32f4xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h index df929361dad..a4e6096cb50 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h @@ -38,6 +38,7 @@ #include "stm32f7xx_ll_tim.h" #include "stm32f7xx_ll_adc.h" #include "stm32f7xx_ll_rtc.h" +#include "stm32f7xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h index 42fa1a1b335..3cfff01b6a4 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -40,9 +40,9 @@ #if defined(DUAL_CORE) #include "stm32h7xx_ll_hsem.h" #include "stm32h7xx_ll_rcc.h" -#include "stm32h7xx_ll_pwr.h" #include "stm32h7xx_ll_cortex.h" #endif /* CONFIG_STM32H7_DUAL_CORE */ +#include "stm32h7xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32L0/common_objects.h b/targets/TARGET_STM/TARGET_STM32L0/common_objects.h index 43c401ac647..96fb7c8f570 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32L0/common_objects.h @@ -36,6 +36,7 @@ #include "PinNames.h" #include "stm32l0xx_ll_usart.h" #include "stm32l0xx_ll_tim.h" +#include "stm32l0xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32L1/common_objects.h b/targets/TARGET_STM/TARGET_STM32L1/common_objects.h index 9334aa7ae4f..49b98e09a65 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32L1/common_objects.h @@ -36,6 +36,7 @@ #include "PinNames.h" #include "stm32l1xx_ll_usart.h" #include "stm32l1xx_ll_tim.h" +#include "stm32l1xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h index be251d8349e..1e9d1028cde 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h @@ -38,6 +38,7 @@ #include "stm32l4xx_ll_lpuart.h" #include "stm32l4xx_ll_tim.h" #include "stm32l4xx_ll_rtc.h" +#include "stm32l4xx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/TARGET_STM32WB/common_objects.h b/targets/TARGET_STM/TARGET_STM32WB/common_objects.h index 6bbfb801641..156caa81565 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32WB/common_objects.h @@ -38,6 +38,7 @@ #include "PinNames.h" #include "stm32wbxx_ll_usart.h" #include "stm32wbxx_ll_tim.h" +#include "stm32wbxx_ll_pwr.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index a8c0dcfaa59..529b1c328ce 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -135,7 +135,7 @@ void hal_sleep(void) core_util_critical_section_enter(); // Request to enter SLEEP mode -#ifdef PWR_CR1_LPR +#if defined(PWR_CR1_LPR) // State Transitions (see 5.3 Low-power modes, Fig. 13): // * (opt): Low Power Run (LPR) Mode -> Run Mode // * Run Mode -> Sleep @@ -145,7 +145,14 @@ void hal_sleep(void) // [5.4.1 Power control register 1 (PWR_CR1)] // LPR: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). - int lowPowerMode = PWR->CR1 & PWR_CR1_LPR; + uint32_t lowPowerMode = LL_PWR_IsEnabledLowPowerRunMode(); + if (lowPowerMode) { + HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); + } else { + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + } +#elif defined(PWR_CR_LPDS) || defined(PWR_CR1_LPDS) + uint32_t lowPowerMode = LL_PWR_GetRegulModeDS(); if (lowPowerMode) { HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); } else { From affe7113effcb0ccaeb412cc396c053656fe7786 Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Tue, 19 Nov 2019 16:16:17 +0100 Subject: [PATCH 3/6] TARGET_STM: Remove timeout on HSEM. With tickless mechanism hsem can be used for quite a long time (time to set up PLL clock). Also, if hsem is held to long, then this is not the current core which is faulty, but probably the other (the one which hold the HSEM) --- .../TARGET_STM/TARGET_STM32L4/aes_alt.c | 3 +-- .../TARGET_STM32H7/analogin_device.c | 3 +-- targets/TARGET_STM/TARGET_STM32H7/flash_api.c | 9 +++------ targets/TARGET_STM/TARGET_STM32H7/pin_device.h | 6 ++---- targets/TARGET_STM/can_api.c | 9 +++------ targets/TARGET_STM/gpio_api.c | 3 +-- targets/TARGET_STM/gpio_object.h | 3 +-- targets/TARGET_STM/i2c_api.c | 6 ++---- targets/TARGET_STM/lp_ticker.c | 3 +-- targets/TARGET_STM/pinmap.c | 8 +++----- targets/TARGET_STM/qspi_api.c | 6 ++---- targets/TARGET_STM/rtc_api.c | 3 +-- targets/TARGET_STM/serial_api.c | 18 ++++++------------ targets/TARGET_STM/sleep.c | 6 ++---- targets/TARGET_STM/stm_spi_api.c | 3 +-- targets/TARGET_STM/trng_api.c | 3 +-- targets/TARGET_STM/us_ticker.c | 6 ++---- 17 files changed, 33 insertions(+), 65 deletions(-) diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c index 768624a7ff7..fcaadb685a4 100644 --- a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c +++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c @@ -93,8 +93,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx) return; } #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ /* Force the CRYP Periheral Clock Reset */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index 5b593736c15..74c2c6c279b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -89,8 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin) PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP; PeriphClkInitStruct.PLL2.PLL2P = 4; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); diff --git a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c index 3917e9309c4..c080d7a34c1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c @@ -28,8 +28,7 @@ static uint32_t GetSectorBase(uint32_t SectorId, uint32_t BanksId); int32_t flash_init(flash_t *obj) { #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) { } #endif /* DUAL_CORE */ /* Clear pending flags (if any) */ @@ -58,8 +57,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) } #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) { } #endif /* DUAL_CORE */ if (HAL_FLASH_Unlock() != HAL_OK) { @@ -121,8 +119,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, } #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) { } #endif /* DUAL_CORE */ if (HAL_FLASH_Unlock() != HAL_OK) { diff --git a/targets/TARGET_STM/TARGET_STM32H7/pin_device.h b/targets/TARGET_STM/TARGET_STM32H7/pin_device.h index eb459d54a6a..4589013e480 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32H7/pin_device.h @@ -45,8 +45,7 @@ static inline void stm_pin_DisconnectDebug(PinName pin) static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config) { #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { } #endif /* DUAL_CORE */ @@ -72,8 +71,7 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { } #endif /* DUAL_CORE */ diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 10fe11517eb..17687222676 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -91,8 +91,7 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80) #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { @@ -190,8 +189,7 @@ void can_irq_free(can_t *obj) void can_free(can_t *obj) { #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ __HAL_RCC_FDCAN_FORCE_RESET(); @@ -638,8 +636,7 @@ void can_free(can_t *obj) { CANName can = (CANName) obj->CanHandle.Instance; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ // Reset CAN and disable clock diff --git a/targets/TARGET_STM/gpio_api.c b/targets/TARGET_STM/gpio_api.c index cfea965ee8b..b7a08428f3e 100644 --- a/targets/TARGET_STM/gpio_api.c +++ b/targets/TARGET_STM/gpio_api.c @@ -156,8 +156,7 @@ void gpio_mode(gpio_t *obj, PinMode mode) inline void gpio_dir(gpio_t *obj, PinDirection direction) { #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { } #endif /* DUAL_CORE */ diff --git a/targets/TARGET_STM/gpio_object.h b/targets/TARGET_STM/gpio_object.h index a9c13b5b0a8..0a3827df2c2 100644 --- a/targets/TARGET_STM/gpio_object.h +++ b/targets/TARGET_STM/gpio_object.h @@ -58,8 +58,7 @@ typedef struct { static inline void gpio_write(gpio_t *obj, int value) { #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { } #endif /* DUAL_CORE */ diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index a693e56a18e..4d78d4a2df6 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -215,8 +215,7 @@ void i2c_hw_reset(i2c_t *obj) timeout = BYTE_TIMEOUT; while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0)); #if defined(DUAL_CORE) - timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ #if defined I2C1_BASE @@ -422,8 +421,7 @@ void i2c_frequency(i2c_t *obj, int hz) /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/ #if defined(DUAL_CORE) - timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG) diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index eca51b35ef6..cec8c74d5d9 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -205,8 +205,7 @@ void lp_ticker_init(void) #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index 336cc133f54..467544c56e7 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -81,8 +81,7 @@ void pin_function(PinName pin, int data) if (mode == STM_PIN_OUTPUT) { #endif #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { } #endif /* DUAL_CORE */ switch (speed) { @@ -126,7 +125,7 @@ void pin_function(PinName pin, int data) } #if defined(DUAL_CORE) - while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { } #endif /* DUAL_CORE */ @@ -172,8 +171,7 @@ void pin_mode(PinName pin, PinMode mode) GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index); #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) { } #endif /* DUAL_CORE */ diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index 90243dbee16..b2f2d079d24 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -499,8 +499,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN // Reset QSPI #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ __HAL_RCC_QSPI_FORCE_RESET(); @@ -607,8 +606,7 @@ qspi_status_t qspi_free(qspi_t *obj) // Reset QSPI #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ __HAL_RCC_QSPI_FORCE_RESET(); diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index a9728b68f41..acb85af6148 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -59,8 +59,7 @@ void rtc_init(void) HAL_PWR_EnableBkUpAccess(); #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ #if MBED_CONF_TARGET_LSE_AVAILABLE diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index fe33165d03d..5e8e40f2bd9 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -211,8 +211,7 @@ void serial_free(serial_t *obj) // Reset UART and disable clock #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ #if defined(USART1_BASE) @@ -365,8 +364,7 @@ void serial_baud(serial_t *obj, int baudrate) RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ HAL_RCC_OscConfig(&RCC_OscInitStruct); @@ -377,8 +375,7 @@ void serial_baud(serial_t *obj, int baudrate) // Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) { #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; @@ -408,8 +405,7 @@ void serial_baud(serial_t *obj, int baudrate) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ HAL_RCC_OscConfig(&RCC_OscInitStruct); @@ -421,8 +417,7 @@ void serial_baud(serial_t *obj, int baudrate) if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) { PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); @@ -437,8 +432,7 @@ void serial_baud(serial_t *obj, int baudrate) // Last chance using SYSCLK PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index 529b1c328ce..655992254c0 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -58,8 +58,7 @@ static void ForcePeriphOutofDeepSleep(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ /* Get the Clocks configuration according to the internal RCC registers */ @@ -100,8 +99,7 @@ static void ForceOscOutofDeepSleep(void) __HAL_RCC_PWR_CLK_ENABLE(); #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ /* Get the Oscillators configuration according to the internal RCC registers */ diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index a62512c5043..9222b2b8259 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -236,8 +236,7 @@ void spi_free(spi_t *obj) HAL_SPI_DeInit(handle); #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ #if defined SPI1_BASE diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c index 348170c12d4..e6ebfe1f783 100644 --- a/targets/TARGET_STM/trng_api.c +++ b/targets/TARGET_STM/trng_api.c @@ -54,8 +54,7 @@ void trng_init(trng_t *obj) PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL; #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { diff --git a/targets/TARGET_STM/us_ticker.c b/targets/TARGET_STM/us_ticker.c index a731383ef59..eb69612e13b 100644 --- a/targets/TARGET_STM/us_ticker.c +++ b/targets/TARGET_STM/us_ticker.c @@ -76,8 +76,7 @@ void init_16bit_timer(void) // Reset timer #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ TIM_MST_RESET_ON; @@ -170,8 +169,7 @@ void init_32bit_timer(void) // Reset timer #if defined(DUAL_CORE) - uint32_t timeout = HSEM_TIMEOUT; - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) { + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ TIM_MST_RESET_ON; From df7431df814c533464d44282d0041447c531410c Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Fri, 22 Nov 2019 16:01:52 +0100 Subject: [PATCH 4/6] TARGET_STM: Improve H747 dual core Deepsleep robustness --- targets/TARGET_STM/TARGET_STM32H7/objects.h | 4 +- targets/TARGET_STM/mbed_overrides.c | 9 ++-- targets/TARGET_STM/sleep.c | 57 +++++++++++---------- 3 files changed, 38 insertions(+), 32 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h index 3cfff01b6a4..5512111cd99 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -151,8 +151,8 @@ struct analogin_s { #if defined(DUAL_CORE) /* HW semaphore Complement ID list defined in hw_conf.h from STM32WB */ /* Index of the semaphore used to manage the entry Stop Mode procedure */ -#define CFG_HW_ENTRY_STOP_MODE_SEMID 4 -#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1 << CFG_HW_ENTRY_STOP_MODE_SEMID) +#define CFG_HW_STOP_MODE_SEMID 4 +#define CFG_HW_STOP_MODE_MASK_SEMID (1 << CFG_HW_STOP_MODE_SEMID) /* Index of the semaphore used to access the RCC */ #define CFG_HW_RCC_SEMID 3 diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 4f0e0bbcab3..a006a7563ce 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -60,7 +60,7 @@ void mbed_sdk_init() /* CM4 boots at the same time than CM7. It is necessary to synchronize with CM7, by mean of HSEM, that CM7 finishes its initialization. */ /* Activate HSEM notification for Cortex-M4*/ - LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID); + LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID); /* * Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for @@ -89,7 +89,8 @@ void mbed_sdk_init() LL_LPM_EnableSleep(); /* Clear HSEM flag */ - LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID); + LL_HSEM_DisableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID); + LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_STOP_MODE_MASK_SEMID); } // Update the SystemCoreClock variable. @@ -109,9 +110,9 @@ void mbed_sdk_init() /* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization. otherwise CM7 should wakeup CM4 when system clocks initialization is done. */ if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) { - LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID); + LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID); /*Release HSEM in order to notify the CPU2(CM4)*/ - LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0); + LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, 0); } else { LL_RCC_ForceCM4Boot(); } diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index 655992254c0..f0656666e48 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -57,10 +57,6 @@ static void ForcePeriphOutofDeepSleep(void) uint32_t pFLatency = 0; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; -#if defined(DUAL_CORE) - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { - } -#endif /* DUAL_CORE */ /* Get the Clocks configuration according to the internal RCC registers */ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency); @@ -85,9 +81,6 @@ static void ForcePeriphOutofDeepSleep(void) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) { error("ForcePeriphOutofDeepSleep clock issue\r\n"); } -#if defined(DUAL_CORE) - LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); -#endif /* DUAL_CORE */ } @@ -98,10 +91,6 @@ static void ForceOscOutofDeepSleep(void) /* Enable Power Control clock */ __HAL_RCC_PWR_CLK_ENABLE(); -#if defined(DUAL_CORE) - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { - } -#endif /* DUAL_CORE */ /* Get the Oscillators configuration according to the internal RCC registers */ HAL_RCC_GetOscConfig(&RCC_OscInitStruct); @@ -121,9 +110,7 @@ static void ForceOscOutofDeepSleep(void) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { error("ForceOscOutofDeepSleep clock issue\r\n"); } -#if defined(DUAL_CORE) - LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); -#endif /* DUAL_CORE */ + } @@ -236,25 +223,43 @@ __WEAK void hal_deepsleep(void) * us_ticker timestamp until the us_ticker context is restored. */ mbed_sdk_inited = 0; - /* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered - * So we need to force clock init out of Deep Sleep. - * This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel. - * This will reduce the maximum stack usage in case on non-optimized / debug compilers settings - */ - ForceOscOutofDeepSleep(); - ForcePeriphOutofDeepSleep(); - /* After wake-up from STOP reconfigure the PLL */ #if defined(DUAL_CORE) - while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { + /* CFG_HW_STOP_MODE_SEMID is used to protect read access to STOP flag, and this avoid both core to configure clocks if both exit from stop at the same time */ + while (LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID)) { } - if ((LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)) { - LL_PWR_ClearFlag_CPU(); + /* Clocks need to be reconfigured only if system has been in stop mode */ + if (LL_PWR_CPU_IsActiveFlag_STOP() && LL_PWR_CPU2_IsActiveFlag_STOP()) { + /* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered + * So we need to force clock init out of Deep Sleep. + * This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel. + * This will reduce the maximum stack usage in case on non-optimized / debug compilers settings + */ + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { + } + ForceOscOutofDeepSleep(); + ForcePeriphOutofDeepSleep(); SetSysClock(); + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); } - LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); +#if defined(CORE_CM7) + LL_PWR_ClearFlag_CPU(); +#elif defined(CORE_CM4) + LL_PWR_ClearFlag_CPU2(); #else +#error "Core not supported" +#endif + + LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, HSEM_CR_COREID_CURRENT); +#else + /* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered + * So we need to force clock init out of Deep Sleep. + * This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel. + * This will reduce the maximum stack usage in case on non-optimized / debug compilers settings + */ + ForceOscOutofDeepSleep(); + ForcePeriphOutofDeepSleep(); SetSysClock(); #endif From f36982cc97c32c630747ffe46d466a72244fbf75 Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Fri, 22 Nov 2019 16:07:50 +0100 Subject: [PATCH 5/6] TARGET_STM: STM32H7 HAL_RCC_OscConfig update in PLL configuration port fix #5896 on STM32H7 Cube HAL ST internal ticket 42806 not yet released for STM32H7 --- .../TARGET_STM32H7/device/stm32h7xx_hal_rcc.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c index ca44d1b87cd..895c9cb8baf 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c @@ -803,7 +803,19 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } else { - return HAL_ERROR; + /* Do not return HAL_ERROR if request repeats the current configuration */ + uint32_t temp1_pllckcfg = RCC->PLLCKSELR; + uint32_t temp2_pllckcfg = RCC->PLL1DIVR; + if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } } } return HAL_OK; From 42a0407a56beb48ef0e623932a32581aa3d62ed3 Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Tue, 26 Nov 2019 10:54:53 +0100 Subject: [PATCH 6/6] export: fix IAR definition for dual core STM32 DISCO_H747I --- targets/targets.json | 1 - tools/export/iar/iar_definitions.json | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 7fe6d2e1839..2069b85ca30 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3369,7 +3369,6 @@ "FLASH", "MPU" ], - "device_name": "STM32H747XIHx", "bootloader_supported": true }, "DISCO_H747I_CM7": { diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index b2d6f25ff28..7fdbc7b1c6d 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -371,7 +371,7 @@ "STM32H743ZI": { "OGChipSelectEditMenu": "STM32H743ZI\tST STM32H743ZI" }, - "DISCO_H747I": { + "STM32H747XIHx": { "OGChipSelectEditMenu": "STM32H747XI_CM7\tST STM32H747XI_CM7" }, "DISCO_H747I_CM4": {