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131 | 131 | */ |
132 | 132 |
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133 | 133 | // Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON) |
134 | | -#define USE_PLL_HSE_EXTC (1) // Use external clock |
| 134 | +#define USE_PLL_HSE_EXTC (0) // Use external clock |
135 | 135 | #define USE_PLL_HSE_XTAL (0) // Use external xtal |
136 | 136 | #define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI) |
137 | 137 | #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) |
@@ -530,40 +530,48 @@ uint8_t SetSysClock_PLL_MSI(void) |
530 | 530 | { |
531 | 531 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
532 | 532 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
533 | | - |
| 533 | + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; |
| 534 | + |
534 | 535 | // Enable LSE Oscillator to automatically calibrate the MSI clock |
535 | 536 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; |
536 | 537 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
537 | 538 | RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT |
538 | 539 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { |
539 | 540 | RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode |
540 | 541 | } |
541 | | - |
542 | | - // Enable MSI oscillator and activate PLL with MSI as source |
543 | | - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| 542 | + |
| 543 | + HAL_RCCEx_DisableLSECSS(); |
| 544 | + /* Enable MSI Oscillator and activate PLL with MSI as source */ |
| 545 | + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
544 | 546 | RCC_OscInitStruct.MSIState = RCC_MSI_ON; |
545 | 547 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
546 | 548 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
547 | | - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; |
548 | | - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; |
549 | | - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
550 | | - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz |
551 | | - RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1) |
552 | | - RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40) |
553 | | - RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7) |
554 | | - RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB |
555 | | - RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) |
| 549 | + |
| 550 | + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; |
| 551 | + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; |
| 552 | + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| 553 | + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; |
| 554 | + RCC_OscInitStruct.PLL.PLLM = 6; |
| 555 | + RCC_OscInitStruct.PLL.PLLN = 40; |
| 556 | + RCC_OscInitStruct.PLL.PLLP = 7; |
| 557 | + RCC_OscInitStruct.PLL.PLLQ = 4; |
| 558 | + RCC_OscInitStruct.PLL.PLLR = 4; |
556 | 559 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
557 | 560 | { |
558 | 561 | return 0; // FAIL |
559 | 562 | } |
560 | | - |
| 563 | + /* Enable MSI Auto-calibration through LSE */ |
| 564 | + HAL_RCCEx_EnableMSIPLLMode(); |
| 565 | + /* Select MSI output as USB clock source */ |
| 566 | + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; |
| 567 | + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; |
| 568 | + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |
561 | 569 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
562 | 570 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
563 | | - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz |
564 | | - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz |
565 | | - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
566 | | - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
| 571 | + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| 572 | + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| 573 | + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; |
| 574 | + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; |
567 | 575 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) |
568 | 576 | { |
569 | 577 | return 0; // FAIL |
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