diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h
index 560a973b7cd..60588932d3e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h
@@ -1,35 +1,41 @@
 /*
 ** ###################################################################
-**     Processor:           MKL46Z128VLK4
+**     Processors:          MKL46Z256VLH4
+**                          MKL46Z128VLH4
+**                          MKL46Z256VLL4
+**                          MKL46Z128VLL4
+**                          MKL46Z256VMC4
+**                          MKL46Z128VMC4
+**
 **     Compilers:           ARM Compiler
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
 **
-**     Reference manual:    KL25RM, Rev.1, Jun 2012
-**     Version:             rev. 1.1, 2012-06-21
+**     Reference manual:    KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+**     Version:             rev. 2.0, 2012-12-12
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MKL46Z4
 **
-**     Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**     Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
 **
 **     http:                 www.freescale.com
 **     mail:                 support@freescale.com
 **
 **     Revisions:
-**     - rev. 1.0 (2012-06-13)
+**     - rev. 1.0 (2012-10-16)
 **         Initial version.
-**     - rev. 1.1 (2012-06-21)
-**         Update according to reference manual rev. 1.
+**     - rev. 2.0 (2012-12-12)
+**         Update to reference manual rev. 1.
 **
 ** ###################################################################
 */
 
 /**
  * @file MKL46Z4.h
- * @version 1.1
- * @date 2012-06-21
+ * @version 2.0
+ * @date 2012-12-12
  * @brief CMSIS Peripheral Access Layer for MKL46Z4
  *
  * CMSIS Peripheral Access Layer for MKL46Z4
@@ -40,9 +46,9 @@
 
 /** Memory map major version (memory maps with equal major version number are
  * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
+#define MCU_MEM_MAP_VERSION 0x0200u
 /** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
 
 
 /* ----------------------------------------------------------------------------
@@ -64,12 +70,12 @@ typedef enum IRQn {
   SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
 
   /* Device specific interrupts */
-  DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete interrupt */
-  DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete interrupt */
-  DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete interrupt */
-  DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete interrupt */
+  DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete/error interrupt */
+  DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete/error interrupt */
+  DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete/error interrupt */
+  DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete/error interrupt */
   Reserved20_IRQn              = 4,                /**< Reserved interrupt 20 */
-  FTFA_IRQn                    = 5,                /**< FTFA interrupt */
+  FTFA_IRQn                    = 5,                /**< FTFA command complete/read collision interrupt */
   LVD_LVW_IRQn                 = 6,                /**< Low Voltage Detect, Low Voltage Warning */
   LLW_IRQn                     = 7,                /**< Low Leakage Wakeup */
   I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
@@ -87,13 +93,13 @@ typedef enum IRQn {
   RTC_IRQn                     = 20,               /**< RTC interrupt */
   RTC_Seconds_IRQn             = 21,               /**< RTC seconds interrupt */
   PIT_IRQn                     = 22,               /**< PIT timer interrupt */
-  Reserved39_IRQn              = 23,               /**< Reserved interrupt 39 */
+  I2S0_IRQn                    = 23,               /**< I2S0 transmit interrupt */
   USB0_IRQn                    = 24,               /**< USB0 interrupt */
-  DAC0_IRQn                    = 25,               /**< DAC interrupt */
+  DAC0_IRQn                    = 25,               /**< DAC0 interrupt */
   TSI0_IRQn                    = 26,               /**< TSI0 interrupt */
   MCG_IRQn                     = 27,               /**< MCG interrupt */
   LPTimer_IRQn                 = 28,               /**< LPTimer interrupt */
-  Reserved45_IRQn              = 29,               /**< Reserved interrupt 45 */
+  LCD_IRQn                     = 29,               /**< Segment LCD Interrupt */
   PORTA_IRQn                   = 30,               /**< Port A interrupt */
   PORTD_IRQn                   = 31                /**< Port D interrupt */
 } IRQn_Type;
@@ -447,8 +453,8 @@ typedef struct {
 #define CMP_MUXCR_PSEL_MASK                      0x38u
 #define CMP_MUXCR_PSEL_SHIFT                     3
 #define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-#define CMP_MUXCR_PSTM_MASK                      0x40u
-#define CMP_MUXCR_PSTM_SHIFT                     6
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
 
 /**
  * @}
@@ -569,10 +575,7 @@ typedef struct {
 
 /** DMA - Register Layout Typedef */
 typedef struct {
-  union {                                          /* offset: 0x0 */
-    __IO uint8_t REQC_ARR[4];                        /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
-  };
-       uint8_t RESERVED_0[252];
+       uint8_t RESERVED_0[256];
   struct {                                         /* offset: 0x100, array step: 0x10 */
     __IO uint32_t SAR;                               /**< Source Address Register, array offset: 0x100, array step: 0x10 */
     __IO uint32_t DAR;                               /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
@@ -596,12 +599,6 @@ typedef struct {
  * @{
  */
 
-/* REQC_ARR Bit Fields */
-#define DMA_REQC_ARR_DMAC_MASK                   0xFu
-#define DMA_REQC_ARR_DMAC_SHIFT                  0
-#define DMA_REQC_ARR_DMAC(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
-#define DMA_REQC_ARR_CFSM_MASK                   0x80u
-#define DMA_REQC_ARR_CFSM_SHIFT                  7
 /* SAR Bit Fields */
 #define DMA_SAR_SAR_MASK                         0xFFFFFFFFu
 #define DMA_SAR_SAR_SHIFT                        0
@@ -1234,6 +1231,1591 @@ typedef struct {
  */ /* end of group I2C_Peripheral_Access_Layer */
 
 
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_1[8];
+  __O  uint32_t TDR[1];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_2[60];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_5[8];
+  __I  uint32_t RDR[1];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_CLKMODE_MASK                    0xC000000u
+#define I2S_TCR2_CLKMODE_SHIFT                   26
+#define I2S_TCR2_CLKMODE(x)                      (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1u
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_TCE_MASK                        0x10000u
+#define I2S_TCR3_TCE_SHIFT                       16
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x10000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0x3u
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_CLKMODE_MASK                    0xC000000u
+#define I2S_RCR2_CLKMODE_SHIFT                   26
+#define I2S_RCR2_CLKMODE(x)                      (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1u
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_RCE_MASK                        0x10000u
+#define I2S_RCR3_RCE_SHIFT                       16
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x10000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0x3u
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASES                                { I2S0 }
+
+/**
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GCR;                               /**< LCD General Control Register, offset: 0x0 */
+  __IO uint32_t AR;                                /**< LCD Auxiliary Register, offset: 0x4 */
+  __IO uint32_t FDCR;                              /**< LCD Fault Detect Control Register, offset: 0x8 */
+  __IO uint32_t FDSR;                              /**< LCD Fault Detect Status Register, offset: 0xC */
+  __IO uint32_t PEN[2];                            /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t BPEN[2];                           /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
+  union {                                          /* offset: 0x20 */
+    __IO uint32_t WF[16];                            /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
+    __IO uint8_t WF8B[64];                           /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
+  };
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/* GCR Bit Fields */
+#define LCD_GCR_DUTY_MASK                        0x7u
+#define LCD_GCR_DUTY_SHIFT                       0
+#define LCD_GCR_DUTY(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
+#define LCD_GCR_LCLK_MASK                        0x38u
+#define LCD_GCR_LCLK_SHIFT                       3
+#define LCD_GCR_LCLK(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
+#define LCD_GCR_SOURCE_MASK                      0x40u
+#define LCD_GCR_SOURCE_SHIFT                     6
+#define LCD_GCR_LCDEN_MASK                       0x80u
+#define LCD_GCR_LCDEN_SHIFT                      7
+#define LCD_GCR_LCDSTP_MASK                      0x100u
+#define LCD_GCR_LCDSTP_SHIFT                     8
+#define LCD_GCR_LCDDOZE_MASK                     0x200u
+#define LCD_GCR_LCDDOZE_SHIFT                    9
+#define LCD_GCR_FFR_MASK                         0x400u
+#define LCD_GCR_FFR_SHIFT                        10
+#define LCD_GCR_ALTSOURCE_MASK                   0x800u
+#define LCD_GCR_ALTSOURCE_SHIFT                  11
+#define LCD_GCR_ALTDIV_MASK                      0x3000u
+#define LCD_GCR_ALTDIV_SHIFT                     12
+#define LCD_GCR_ALTDIV(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
+#define LCD_GCR_FDCIEN_MASK                      0x4000u
+#define LCD_GCR_FDCIEN_SHIFT                     14
+#define LCD_GCR_PADSAFE_MASK                     0x8000u
+#define LCD_GCR_PADSAFE_SHIFT                    15
+#define LCD_GCR_VSUPPLY_MASK                     0x20000u
+#define LCD_GCR_VSUPPLY_SHIFT                    17
+#define LCD_GCR_LADJ_MASK                        0x300000u
+#define LCD_GCR_LADJ_SHIFT                       20
+#define LCD_GCR_LADJ(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
+#define LCD_GCR_CPSEL_MASK                       0x800000u
+#define LCD_GCR_CPSEL_SHIFT                      23
+#define LCD_GCR_RVTRIM_MASK                      0xF000000u
+#define LCD_GCR_RVTRIM_SHIFT                     24
+#define LCD_GCR_RVTRIM(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
+#define LCD_GCR_RVEN_MASK                        0x80000000u
+#define LCD_GCR_RVEN_SHIFT                       31
+/* AR Bit Fields */
+#define LCD_AR_BRATE_MASK                        0x7u
+#define LCD_AR_BRATE_SHIFT                       0
+#define LCD_AR_BRATE(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
+#define LCD_AR_BMODE_MASK                        0x8u
+#define LCD_AR_BMODE_SHIFT                       3
+#define LCD_AR_BLANK_MASK                        0x20u
+#define LCD_AR_BLANK_SHIFT                       5
+#define LCD_AR_ALT_MASK                          0x40u
+#define LCD_AR_ALT_SHIFT                         6
+#define LCD_AR_BLINK_MASK                        0x80u
+#define LCD_AR_BLINK_SHIFT                       7
+/* FDCR Bit Fields */
+#define LCD_FDCR_FDPINID_MASK                    0x3Fu
+#define LCD_FDCR_FDPINID_SHIFT                   0
+#define LCD_FDCR_FDPINID(x)                      (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
+#define LCD_FDCR_FDBPEN_MASK                     0x40u
+#define LCD_FDCR_FDBPEN_SHIFT                    6
+#define LCD_FDCR_FDEN_MASK                       0x80u
+#define LCD_FDCR_FDEN_SHIFT                      7
+#define LCD_FDCR_FDSWW_MASK                      0xE00u
+#define LCD_FDCR_FDSWW_SHIFT                     9
+#define LCD_FDCR_FDSWW(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
+#define LCD_FDCR_FDPRS_MASK                      0x7000u
+#define LCD_FDCR_FDPRS_SHIFT                     12
+#define LCD_FDCR_FDPRS(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
+/* FDSR Bit Fields */
+#define LCD_FDSR_FDCNT_MASK                      0xFFu
+#define LCD_FDSR_FDCNT_SHIFT                     0
+#define LCD_FDSR_FDCNT(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
+#define LCD_FDSR_FDCF_MASK                       0x8000u
+#define LCD_FDSR_FDCF_SHIFT                      15
+/* PEN Bit Fields */
+#define LCD_PEN_PEN_MASK                         0xFFFFFFFFu
+#define LCD_PEN_PEN_SHIFT                        0
+#define LCD_PEN_PEN(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
+/* BPEN Bit Fields */
+#define LCD_BPEN_BPEN_MASK                       0xFFFFFFFFu
+#define LCD_BPEN_BPEN_SHIFT                      0
+#define LCD_BPEN_BPEN(x)                         (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
+/* WF Bit Fields */
+#define LCD_WF_WF0_MASK                          0xFFu
+#define LCD_WF_WF0_SHIFT                         0
+#define LCD_WF_WF0(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
+#define LCD_WF_WF60_MASK                         0xFFu
+#define LCD_WF_WF60_SHIFT                        0
+#define LCD_WF_WF60(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
+#define LCD_WF_WF56_MASK                         0xFFu
+#define LCD_WF_WF56_SHIFT                        0
+#define LCD_WF_WF56(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
+#define LCD_WF_WF52_MASK                         0xFFu
+#define LCD_WF_WF52_SHIFT                        0
+#define LCD_WF_WF52(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
+#define LCD_WF_WF4_MASK                          0xFFu
+#define LCD_WF_WF4_SHIFT                         0
+#define LCD_WF_WF4(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
+#define LCD_WF_WF48_MASK                         0xFFu
+#define LCD_WF_WF48_SHIFT                        0
+#define LCD_WF_WF48(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
+#define LCD_WF_WF44_MASK                         0xFFu
+#define LCD_WF_WF44_SHIFT                        0
+#define LCD_WF_WF44(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
+#define LCD_WF_WF40_MASK                         0xFFu
+#define LCD_WF_WF40_SHIFT                        0
+#define LCD_WF_WF40(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
+#define LCD_WF_WF8_MASK                          0xFFu
+#define LCD_WF_WF8_SHIFT                         0
+#define LCD_WF_WF8(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
+#define LCD_WF_WF36_MASK                         0xFFu
+#define LCD_WF_WF36_SHIFT                        0
+#define LCD_WF_WF36(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
+#define LCD_WF_WF32_MASK                         0xFFu
+#define LCD_WF_WF32_SHIFT                        0
+#define LCD_WF_WF32(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
+#define LCD_WF_WF28_MASK                         0xFFu
+#define LCD_WF_WF28_SHIFT                        0
+#define LCD_WF_WF28(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
+#define LCD_WF_WF12_MASK                         0xFFu
+#define LCD_WF_WF12_SHIFT                        0
+#define LCD_WF_WF12(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
+#define LCD_WF_WF24_MASK                         0xFFu
+#define LCD_WF_WF24_SHIFT                        0
+#define LCD_WF_WF24(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
+#define LCD_WF_WF20_MASK                         0xFFu
+#define LCD_WF_WF20_SHIFT                        0
+#define LCD_WF_WF20(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
+#define LCD_WF_WF16_MASK                         0xFFu
+#define LCD_WF_WF16_SHIFT                        0
+#define LCD_WF_WF16(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
+#define LCD_WF_WF5_MASK                          0xFF00u
+#define LCD_WF_WF5_SHIFT                         8
+#define LCD_WF_WF5(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
+#define LCD_WF_WF49_MASK                         0xFF00u
+#define LCD_WF_WF49_SHIFT                        8
+#define LCD_WF_WF49(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
+#define LCD_WF_WF45_MASK                         0xFF00u
+#define LCD_WF_WF45_SHIFT                        8
+#define LCD_WF_WF45(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
+#define LCD_WF_WF61_MASK                         0xFF00u
+#define LCD_WF_WF61_SHIFT                        8
+#define LCD_WF_WF61(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
+#define LCD_WF_WF25_MASK                         0xFF00u
+#define LCD_WF_WF25_SHIFT                        8
+#define LCD_WF_WF25(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
+#define LCD_WF_WF17_MASK                         0xFF00u
+#define LCD_WF_WF17_SHIFT                        8
+#define LCD_WF_WF17(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
+#define LCD_WF_WF41_MASK                         0xFF00u
+#define LCD_WF_WF41_SHIFT                        8
+#define LCD_WF_WF41(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
+#define LCD_WF_WF13_MASK                         0xFF00u
+#define LCD_WF_WF13_SHIFT                        8
+#define LCD_WF_WF13(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
+#define LCD_WF_WF57_MASK                         0xFF00u
+#define LCD_WF_WF57_SHIFT                        8
+#define LCD_WF_WF57(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
+#define LCD_WF_WF53_MASK                         0xFF00u
+#define LCD_WF_WF53_SHIFT                        8
+#define LCD_WF_WF53(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
+#define LCD_WF_WF37_MASK                         0xFF00u
+#define LCD_WF_WF37_SHIFT                        8
+#define LCD_WF_WF37(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
+#define LCD_WF_WF9_MASK                          0xFF00u
+#define LCD_WF_WF9_SHIFT                         8
+#define LCD_WF_WF9(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
+#define LCD_WF_WF1_MASK                          0xFF00u
+#define LCD_WF_WF1_SHIFT                         8
+#define LCD_WF_WF1(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
+#define LCD_WF_WF29_MASK                         0xFF00u
+#define LCD_WF_WF29_SHIFT                        8
+#define LCD_WF_WF29(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
+#define LCD_WF_WF33_MASK                         0xFF00u
+#define LCD_WF_WF33_SHIFT                        8
+#define LCD_WF_WF33(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
+#define LCD_WF_WF21_MASK                         0xFF00u
+#define LCD_WF_WF21_SHIFT                        8
+#define LCD_WF_WF21(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
+#define LCD_WF_WF26_MASK                         0xFF0000u
+#define LCD_WF_WF26_SHIFT                        16
+#define LCD_WF_WF26(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
+#define LCD_WF_WF46_MASK                         0xFF0000u
+#define LCD_WF_WF46_SHIFT                        16
+#define LCD_WF_WF46(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
+#define LCD_WF_WF6_MASK                          0xFF0000u
+#define LCD_WF_WF6_SHIFT                         16
+#define LCD_WF_WF6(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
+#define LCD_WF_WF42_MASK                         0xFF0000u
+#define LCD_WF_WF42_SHIFT                        16
+#define LCD_WF_WF42(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
+#define LCD_WF_WF18_MASK                         0xFF0000u
+#define LCD_WF_WF18_SHIFT                        16
+#define LCD_WF_WF18(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
+#define LCD_WF_WF38_MASK                         0xFF0000u
+#define LCD_WF_WF38_SHIFT                        16
+#define LCD_WF_WF38(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
+#define LCD_WF_WF22_MASK                         0xFF0000u
+#define LCD_WF_WF22_SHIFT                        16
+#define LCD_WF_WF22(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
+#define LCD_WF_WF34_MASK                         0xFF0000u
+#define LCD_WF_WF34_SHIFT                        16
+#define LCD_WF_WF34(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
+#define LCD_WF_WF50_MASK                         0xFF0000u
+#define LCD_WF_WF50_SHIFT                        16
+#define LCD_WF_WF50(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
+#define LCD_WF_WF14_MASK                         0xFF0000u
+#define LCD_WF_WF14_SHIFT                        16
+#define LCD_WF_WF14(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
+#define LCD_WF_WF54_MASK                         0xFF0000u
+#define LCD_WF_WF54_SHIFT                        16
+#define LCD_WF_WF54(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
+#define LCD_WF_WF2_MASK                          0xFF0000u
+#define LCD_WF_WF2_SHIFT                         16
+#define LCD_WF_WF2(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
+#define LCD_WF_WF58_MASK                         0xFF0000u
+#define LCD_WF_WF58_SHIFT                        16
+#define LCD_WF_WF58(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
+#define LCD_WF_WF30_MASK                         0xFF0000u
+#define LCD_WF_WF30_SHIFT                        16
+#define LCD_WF_WF30(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
+#define LCD_WF_WF62_MASK                         0xFF0000u
+#define LCD_WF_WF62_SHIFT                        16
+#define LCD_WF_WF62(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
+#define LCD_WF_WF10_MASK                         0xFF0000u
+#define LCD_WF_WF10_SHIFT                        16
+#define LCD_WF_WF10(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
+#define LCD_WF_WF63_MASK                         0xFF000000u
+#define LCD_WF_WF63_SHIFT                        24
+#define LCD_WF_WF63(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
+#define LCD_WF_WF59_MASK                         0xFF000000u
+#define LCD_WF_WF59_SHIFT                        24
+#define LCD_WF_WF59(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
+#define LCD_WF_WF55_MASK                         0xFF000000u
+#define LCD_WF_WF55_SHIFT                        24
+#define LCD_WF_WF55(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
+#define LCD_WF_WF3_MASK                          0xFF000000u
+#define LCD_WF_WF3_SHIFT                         24
+#define LCD_WF_WF3(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
+#define LCD_WF_WF51_MASK                         0xFF000000u
+#define LCD_WF_WF51_SHIFT                        24
+#define LCD_WF_WF51(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
+#define LCD_WF_WF47_MASK                         0xFF000000u
+#define LCD_WF_WF47_SHIFT                        24
+#define LCD_WF_WF47(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
+#define LCD_WF_WF43_MASK                         0xFF000000u
+#define LCD_WF_WF43_SHIFT                        24
+#define LCD_WF_WF43(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
+#define LCD_WF_WF7_MASK                          0xFF000000u
+#define LCD_WF_WF7_SHIFT                         24
+#define LCD_WF_WF7(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
+#define LCD_WF_WF39_MASK                         0xFF000000u
+#define LCD_WF_WF39_SHIFT                        24
+#define LCD_WF_WF39(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
+#define LCD_WF_WF35_MASK                         0xFF000000u
+#define LCD_WF_WF35_SHIFT                        24
+#define LCD_WF_WF35(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
+#define LCD_WF_WF31_MASK                         0xFF000000u
+#define LCD_WF_WF31_SHIFT                        24
+#define LCD_WF_WF31(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
+#define LCD_WF_WF11_MASK                         0xFF000000u
+#define LCD_WF_WF11_SHIFT                        24
+#define LCD_WF_WF11(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
+#define LCD_WF_WF27_MASK                         0xFF000000u
+#define LCD_WF_WF27_SHIFT                        24
+#define LCD_WF_WF27(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
+#define LCD_WF_WF23_MASK                         0xFF000000u
+#define LCD_WF_WF23_SHIFT                        24
+#define LCD_WF_WF23(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
+#define LCD_WF_WF19_MASK                         0xFF000000u
+#define LCD_WF_WF19_SHIFT                        24
+#define LCD_WF_WF19(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
+#define LCD_WF_WF15_MASK                         0xFF000000u
+#define LCD_WF_WF15_SHIFT                        24
+#define LCD_WF_WF15(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
+/* WF8B Bit Fields */
+#define LCD_WF8B_BPALCD0_MASK                    0x1u
+#define LCD_WF8B_BPALCD0_SHIFT                   0
+#define LCD_WF8B_BPALCD63_MASK                   0x1u
+#define LCD_WF8B_BPALCD63_SHIFT                  0
+#define LCD_WF8B_BPALCD62_MASK                   0x1u
+#define LCD_WF8B_BPALCD62_SHIFT                  0
+#define LCD_WF8B_BPALCD61_MASK                   0x1u
+#define LCD_WF8B_BPALCD61_SHIFT                  0
+#define LCD_WF8B_BPALCD60_MASK                   0x1u
+#define LCD_WF8B_BPALCD60_SHIFT                  0
+#define LCD_WF8B_BPALCD59_MASK                   0x1u
+#define LCD_WF8B_BPALCD59_SHIFT                  0
+#define LCD_WF8B_BPALCD58_MASK                   0x1u
+#define LCD_WF8B_BPALCD58_SHIFT                  0
+#define LCD_WF8B_BPALCD57_MASK                   0x1u
+#define LCD_WF8B_BPALCD57_SHIFT                  0
+#define LCD_WF8B_BPALCD1_MASK                    0x1u
+#define LCD_WF8B_BPALCD1_SHIFT                   0
+#define LCD_WF8B_BPALCD56_MASK                   0x1u
+#define LCD_WF8B_BPALCD56_SHIFT                  0
+#define LCD_WF8B_BPALCD55_MASK                   0x1u
+#define LCD_WF8B_BPALCD55_SHIFT                  0
+#define LCD_WF8B_BPALCD54_MASK                   0x1u
+#define LCD_WF8B_BPALCD54_SHIFT                  0
+#define LCD_WF8B_BPALCD53_MASK                   0x1u
+#define LCD_WF8B_BPALCD53_SHIFT                  0
+#define LCD_WF8B_BPALCD52_MASK                   0x1u
+#define LCD_WF8B_BPALCD52_SHIFT                  0
+#define LCD_WF8B_BPALCD51_MASK                   0x1u
+#define LCD_WF8B_BPALCD51_SHIFT                  0
+#define LCD_WF8B_BPALCD50_MASK                   0x1u
+#define LCD_WF8B_BPALCD50_SHIFT                  0
+#define LCD_WF8B_BPALCD2_MASK                    0x1u
+#define LCD_WF8B_BPALCD2_SHIFT                   0
+#define LCD_WF8B_BPALCD49_MASK                   0x1u
+#define LCD_WF8B_BPALCD49_SHIFT                  0
+#define LCD_WF8B_BPALCD48_MASK                   0x1u
+#define LCD_WF8B_BPALCD48_SHIFT                  0
+#define LCD_WF8B_BPALCD47_MASK                   0x1u
+#define LCD_WF8B_BPALCD47_SHIFT                  0
+#define LCD_WF8B_BPALCD46_MASK                   0x1u
+#define LCD_WF8B_BPALCD46_SHIFT                  0
+#define LCD_WF8B_BPALCD45_MASK                   0x1u
+#define LCD_WF8B_BPALCD45_SHIFT                  0
+#define LCD_WF8B_BPALCD44_MASK                   0x1u
+#define LCD_WF8B_BPALCD44_SHIFT                  0
+#define LCD_WF8B_BPALCD43_MASK                   0x1u
+#define LCD_WF8B_BPALCD43_SHIFT                  0
+#define LCD_WF8B_BPALCD3_MASK                    0x1u
+#define LCD_WF8B_BPALCD3_SHIFT                   0
+#define LCD_WF8B_BPALCD42_MASK                   0x1u
+#define LCD_WF8B_BPALCD42_SHIFT                  0
+#define LCD_WF8B_BPALCD41_MASK                   0x1u
+#define LCD_WF8B_BPALCD41_SHIFT                  0
+#define LCD_WF8B_BPALCD40_MASK                   0x1u
+#define LCD_WF8B_BPALCD40_SHIFT                  0
+#define LCD_WF8B_BPALCD39_MASK                   0x1u
+#define LCD_WF8B_BPALCD39_SHIFT                  0
+#define LCD_WF8B_BPALCD38_MASK                   0x1u
+#define LCD_WF8B_BPALCD38_SHIFT                  0
+#define LCD_WF8B_BPALCD37_MASK                   0x1u
+#define LCD_WF8B_BPALCD37_SHIFT                  0
+#define LCD_WF8B_BPALCD36_MASK                   0x1u
+#define LCD_WF8B_BPALCD36_SHIFT                  0
+#define LCD_WF8B_BPALCD4_MASK                    0x1u
+#define LCD_WF8B_BPALCD4_SHIFT                   0
+#define LCD_WF8B_BPALCD35_MASK                   0x1u
+#define LCD_WF8B_BPALCD35_SHIFT                  0
+#define LCD_WF8B_BPALCD34_MASK                   0x1u
+#define LCD_WF8B_BPALCD34_SHIFT                  0
+#define LCD_WF8B_BPALCD33_MASK                   0x1u
+#define LCD_WF8B_BPALCD33_SHIFT                  0
+#define LCD_WF8B_BPALCD32_MASK                   0x1u
+#define LCD_WF8B_BPALCD32_SHIFT                  0
+#define LCD_WF8B_BPALCD31_MASK                   0x1u
+#define LCD_WF8B_BPALCD31_SHIFT                  0
+#define LCD_WF8B_BPALCD30_MASK                   0x1u
+#define LCD_WF8B_BPALCD30_SHIFT                  0
+#define LCD_WF8B_BPALCD29_MASK                   0x1u
+#define LCD_WF8B_BPALCD29_SHIFT                  0
+#define LCD_WF8B_BPALCD5_MASK                    0x1u
+#define LCD_WF8B_BPALCD5_SHIFT                   0
+#define LCD_WF8B_BPALCD28_MASK                   0x1u
+#define LCD_WF8B_BPALCD28_SHIFT                  0
+#define LCD_WF8B_BPALCD27_MASK                   0x1u
+#define LCD_WF8B_BPALCD27_SHIFT                  0
+#define LCD_WF8B_BPALCD26_MASK                   0x1u
+#define LCD_WF8B_BPALCD26_SHIFT                  0
+#define LCD_WF8B_BPALCD25_MASK                   0x1u
+#define LCD_WF8B_BPALCD25_SHIFT                  0
+#define LCD_WF8B_BPALCD24_MASK                   0x1u
+#define LCD_WF8B_BPALCD24_SHIFT                  0
+#define LCD_WF8B_BPALCD23_MASK                   0x1u
+#define LCD_WF8B_BPALCD23_SHIFT                  0
+#define LCD_WF8B_BPALCD22_MASK                   0x1u
+#define LCD_WF8B_BPALCD22_SHIFT                  0
+#define LCD_WF8B_BPALCD6_MASK                    0x1u
+#define LCD_WF8B_BPALCD6_SHIFT                   0
+#define LCD_WF8B_BPALCD21_MASK                   0x1u
+#define LCD_WF8B_BPALCD21_SHIFT                  0
+#define LCD_WF8B_BPALCD20_MASK                   0x1u
+#define LCD_WF8B_BPALCD20_SHIFT                  0
+#define LCD_WF8B_BPALCD19_MASK                   0x1u
+#define LCD_WF8B_BPALCD19_SHIFT                  0
+#define LCD_WF8B_BPALCD18_MASK                   0x1u
+#define LCD_WF8B_BPALCD18_SHIFT                  0
+#define LCD_WF8B_BPALCD17_MASK                   0x1u
+#define LCD_WF8B_BPALCD17_SHIFT                  0
+#define LCD_WF8B_BPALCD16_MASK                   0x1u
+#define LCD_WF8B_BPALCD16_SHIFT                  0
+#define LCD_WF8B_BPALCD15_MASK                   0x1u
+#define LCD_WF8B_BPALCD15_SHIFT                  0
+#define LCD_WF8B_BPALCD7_MASK                    0x1u
+#define LCD_WF8B_BPALCD7_SHIFT                   0
+#define LCD_WF8B_BPALCD14_MASK                   0x1u
+#define LCD_WF8B_BPALCD14_SHIFT                  0
+#define LCD_WF8B_BPALCD13_MASK                   0x1u
+#define LCD_WF8B_BPALCD13_SHIFT                  0
+#define LCD_WF8B_BPALCD12_MASK                   0x1u
+#define LCD_WF8B_BPALCD12_SHIFT                  0
+#define LCD_WF8B_BPALCD11_MASK                   0x1u
+#define LCD_WF8B_BPALCD11_SHIFT                  0
+#define LCD_WF8B_BPALCD10_MASK                   0x1u
+#define LCD_WF8B_BPALCD10_SHIFT                  0
+#define LCD_WF8B_BPALCD9_MASK                    0x1u
+#define LCD_WF8B_BPALCD9_SHIFT                   0
+#define LCD_WF8B_BPALCD8_MASK                    0x1u
+#define LCD_WF8B_BPALCD8_SHIFT                   0
+#define LCD_WF8B_BPBLCD1_MASK                    0x2u
+#define LCD_WF8B_BPBLCD1_SHIFT                   1
+#define LCD_WF8B_BPBLCD32_MASK                   0x2u
+#define LCD_WF8B_BPBLCD32_SHIFT                  1
+#define LCD_WF8B_BPBLCD30_MASK                   0x2u
+#define LCD_WF8B_BPBLCD30_SHIFT                  1
+#define LCD_WF8B_BPBLCD60_MASK                   0x2u
+#define LCD_WF8B_BPBLCD60_SHIFT                  1
+#define LCD_WF8B_BPBLCD24_MASK                   0x2u
+#define LCD_WF8B_BPBLCD24_SHIFT                  1
+#define LCD_WF8B_BPBLCD28_MASK                   0x2u
+#define LCD_WF8B_BPBLCD28_SHIFT                  1
+#define LCD_WF8B_BPBLCD23_MASK                   0x2u
+#define LCD_WF8B_BPBLCD23_SHIFT                  1
+#define LCD_WF8B_BPBLCD48_MASK                   0x2u
+#define LCD_WF8B_BPBLCD48_SHIFT                  1
+#define LCD_WF8B_BPBLCD10_MASK                   0x2u
+#define LCD_WF8B_BPBLCD10_SHIFT                  1
+#define LCD_WF8B_BPBLCD15_MASK                   0x2u
+#define LCD_WF8B_BPBLCD15_SHIFT                  1
+#define LCD_WF8B_BPBLCD36_MASK                   0x2u
+#define LCD_WF8B_BPBLCD36_SHIFT                  1
+#define LCD_WF8B_BPBLCD44_MASK                   0x2u
+#define LCD_WF8B_BPBLCD44_SHIFT                  1
+#define LCD_WF8B_BPBLCD62_MASK                   0x2u
+#define LCD_WF8B_BPBLCD62_SHIFT                  1
+#define LCD_WF8B_BPBLCD53_MASK                   0x2u
+#define LCD_WF8B_BPBLCD53_SHIFT                  1
+#define LCD_WF8B_BPBLCD22_MASK                   0x2u
+#define LCD_WF8B_BPBLCD22_SHIFT                  1
+#define LCD_WF8B_BPBLCD47_MASK                   0x2u
+#define LCD_WF8B_BPBLCD47_SHIFT                  1
+#define LCD_WF8B_BPBLCD33_MASK                   0x2u
+#define LCD_WF8B_BPBLCD33_SHIFT                  1
+#define LCD_WF8B_BPBLCD2_MASK                    0x2u
+#define LCD_WF8B_BPBLCD2_SHIFT                   1
+#define LCD_WF8B_BPBLCD49_MASK                   0x2u
+#define LCD_WF8B_BPBLCD49_SHIFT                  1
+#define LCD_WF8B_BPBLCD0_MASK                    0x2u
+#define LCD_WF8B_BPBLCD0_SHIFT                   1
+#define LCD_WF8B_BPBLCD55_MASK                   0x2u
+#define LCD_WF8B_BPBLCD55_SHIFT                  1
+#define LCD_WF8B_BPBLCD56_MASK                   0x2u
+#define LCD_WF8B_BPBLCD56_SHIFT                  1
+#define LCD_WF8B_BPBLCD21_MASK                   0x2u
+#define LCD_WF8B_BPBLCD21_SHIFT                  1
+#define LCD_WF8B_BPBLCD6_MASK                    0x2u
+#define LCD_WF8B_BPBLCD6_SHIFT                   1
+#define LCD_WF8B_BPBLCD29_MASK                   0x2u
+#define LCD_WF8B_BPBLCD29_SHIFT                  1
+#define LCD_WF8B_BPBLCD25_MASK                   0x2u
+#define LCD_WF8B_BPBLCD25_SHIFT                  1
+#define LCD_WF8B_BPBLCD8_MASK                    0x2u
+#define LCD_WF8B_BPBLCD8_SHIFT                   1
+#define LCD_WF8B_BPBLCD54_MASK                   0x2u
+#define LCD_WF8B_BPBLCD54_SHIFT                  1
+#define LCD_WF8B_BPBLCD38_MASK                   0x2u
+#define LCD_WF8B_BPBLCD38_SHIFT                  1
+#define LCD_WF8B_BPBLCD43_MASK                   0x2u
+#define LCD_WF8B_BPBLCD43_SHIFT                  1
+#define LCD_WF8B_BPBLCD20_MASK                   0x2u
+#define LCD_WF8B_BPBLCD20_SHIFT                  1
+#define LCD_WF8B_BPBLCD9_MASK                    0x2u
+#define LCD_WF8B_BPBLCD9_SHIFT                   1
+#define LCD_WF8B_BPBLCD7_MASK                    0x2u
+#define LCD_WF8B_BPBLCD7_SHIFT                   1
+#define LCD_WF8B_BPBLCD50_MASK                   0x2u
+#define LCD_WF8B_BPBLCD50_SHIFT                  1
+#define LCD_WF8B_BPBLCD40_MASK                   0x2u
+#define LCD_WF8B_BPBLCD40_SHIFT                  1
+#define LCD_WF8B_BPBLCD63_MASK                   0x2u
+#define LCD_WF8B_BPBLCD63_SHIFT                  1
+#define LCD_WF8B_BPBLCD26_MASK                   0x2u
+#define LCD_WF8B_BPBLCD26_SHIFT                  1
+#define LCD_WF8B_BPBLCD12_MASK                   0x2u
+#define LCD_WF8B_BPBLCD12_SHIFT                  1
+#define LCD_WF8B_BPBLCD19_MASK                   0x2u
+#define LCD_WF8B_BPBLCD19_SHIFT                  1
+#define LCD_WF8B_BPBLCD34_MASK                   0x2u
+#define LCD_WF8B_BPBLCD34_SHIFT                  1
+#define LCD_WF8B_BPBLCD39_MASK                   0x2u
+#define LCD_WF8B_BPBLCD39_SHIFT                  1
+#define LCD_WF8B_BPBLCD59_MASK                   0x2u
+#define LCD_WF8B_BPBLCD59_SHIFT                  1
+#define LCD_WF8B_BPBLCD61_MASK                   0x2u
+#define LCD_WF8B_BPBLCD61_SHIFT                  1
+#define LCD_WF8B_BPBLCD37_MASK                   0x2u
+#define LCD_WF8B_BPBLCD37_SHIFT                  1
+#define LCD_WF8B_BPBLCD31_MASK                   0x2u
+#define LCD_WF8B_BPBLCD31_SHIFT                  1
+#define LCD_WF8B_BPBLCD58_MASK                   0x2u
+#define LCD_WF8B_BPBLCD58_SHIFT                  1
+#define LCD_WF8B_BPBLCD18_MASK                   0x2u
+#define LCD_WF8B_BPBLCD18_SHIFT                  1
+#define LCD_WF8B_BPBLCD45_MASK                   0x2u
+#define LCD_WF8B_BPBLCD45_SHIFT                  1
+#define LCD_WF8B_BPBLCD27_MASK                   0x2u
+#define LCD_WF8B_BPBLCD27_SHIFT                  1
+#define LCD_WF8B_BPBLCD14_MASK                   0x2u
+#define LCD_WF8B_BPBLCD14_SHIFT                  1
+#define LCD_WF8B_BPBLCD51_MASK                   0x2u
+#define LCD_WF8B_BPBLCD51_SHIFT                  1
+#define LCD_WF8B_BPBLCD52_MASK                   0x2u
+#define LCD_WF8B_BPBLCD52_SHIFT                  1
+#define LCD_WF8B_BPBLCD4_MASK                    0x2u
+#define LCD_WF8B_BPBLCD4_SHIFT                   1
+#define LCD_WF8B_BPBLCD35_MASK                   0x2u
+#define LCD_WF8B_BPBLCD35_SHIFT                  1
+#define LCD_WF8B_BPBLCD17_MASK                   0x2u
+#define LCD_WF8B_BPBLCD17_SHIFT                  1
+#define LCD_WF8B_BPBLCD41_MASK                   0x2u
+#define LCD_WF8B_BPBLCD41_SHIFT                  1
+#define LCD_WF8B_BPBLCD11_MASK                   0x2u
+#define LCD_WF8B_BPBLCD11_SHIFT                  1
+#define LCD_WF8B_BPBLCD46_MASK                   0x2u
+#define LCD_WF8B_BPBLCD46_SHIFT                  1
+#define LCD_WF8B_BPBLCD57_MASK                   0x2u
+#define LCD_WF8B_BPBLCD57_SHIFT                  1
+#define LCD_WF8B_BPBLCD42_MASK                   0x2u
+#define LCD_WF8B_BPBLCD42_SHIFT                  1
+#define LCD_WF8B_BPBLCD5_MASK                    0x2u
+#define LCD_WF8B_BPBLCD5_SHIFT                   1
+#define LCD_WF8B_BPBLCD3_MASK                    0x2u
+#define LCD_WF8B_BPBLCD3_SHIFT                   1
+#define LCD_WF8B_BPBLCD16_MASK                   0x2u
+#define LCD_WF8B_BPBLCD16_SHIFT                  1
+#define LCD_WF8B_BPBLCD13_MASK                   0x2u
+#define LCD_WF8B_BPBLCD13_SHIFT                  1
+#define LCD_WF8B_BPCLCD10_MASK                   0x4u
+#define LCD_WF8B_BPCLCD10_SHIFT                  2
+#define LCD_WF8B_BPCLCD55_MASK                   0x4u
+#define LCD_WF8B_BPCLCD55_SHIFT                  2
+#define LCD_WF8B_BPCLCD2_MASK                    0x4u
+#define LCD_WF8B_BPCLCD2_SHIFT                   2
+#define LCD_WF8B_BPCLCD23_MASK                   0x4u
+#define LCD_WF8B_BPCLCD23_SHIFT                  2
+#define LCD_WF8B_BPCLCD48_MASK                   0x4u
+#define LCD_WF8B_BPCLCD48_SHIFT                  2
+#define LCD_WF8B_BPCLCD24_MASK                   0x4u
+#define LCD_WF8B_BPCLCD24_SHIFT                  2
+#define LCD_WF8B_BPCLCD60_MASK                   0x4u
+#define LCD_WF8B_BPCLCD60_SHIFT                  2
+#define LCD_WF8B_BPCLCD47_MASK                   0x4u
+#define LCD_WF8B_BPCLCD47_SHIFT                  2
+#define LCD_WF8B_BPCLCD22_MASK                   0x4u
+#define LCD_WF8B_BPCLCD22_SHIFT                  2
+#define LCD_WF8B_BPCLCD8_MASK                    0x4u
+#define LCD_WF8B_BPCLCD8_SHIFT                   2
+#define LCD_WF8B_BPCLCD21_MASK                   0x4u
+#define LCD_WF8B_BPCLCD21_SHIFT                  2
+#define LCD_WF8B_BPCLCD49_MASK                   0x4u
+#define LCD_WF8B_BPCLCD49_SHIFT                  2
+#define LCD_WF8B_BPCLCD25_MASK                   0x4u
+#define LCD_WF8B_BPCLCD25_SHIFT                  2
+#define LCD_WF8B_BPCLCD1_MASK                    0x4u
+#define LCD_WF8B_BPCLCD1_SHIFT                   2
+#define LCD_WF8B_BPCLCD20_MASK                   0x4u
+#define LCD_WF8B_BPCLCD20_SHIFT                  2
+#define LCD_WF8B_BPCLCD50_MASK                   0x4u
+#define LCD_WF8B_BPCLCD50_SHIFT                  2
+#define LCD_WF8B_BPCLCD19_MASK                   0x4u
+#define LCD_WF8B_BPCLCD19_SHIFT                  2
+#define LCD_WF8B_BPCLCD26_MASK                   0x4u
+#define LCD_WF8B_BPCLCD26_SHIFT                  2
+#define LCD_WF8B_BPCLCD59_MASK                   0x4u
+#define LCD_WF8B_BPCLCD59_SHIFT                  2
+#define LCD_WF8B_BPCLCD61_MASK                   0x4u
+#define LCD_WF8B_BPCLCD61_SHIFT                  2
+#define LCD_WF8B_BPCLCD46_MASK                   0x4u
+#define LCD_WF8B_BPCLCD46_SHIFT                  2
+#define LCD_WF8B_BPCLCD18_MASK                   0x4u
+#define LCD_WF8B_BPCLCD18_SHIFT                  2
+#define LCD_WF8B_BPCLCD5_MASK                    0x4u
+#define LCD_WF8B_BPCLCD5_SHIFT                   2
+#define LCD_WF8B_BPCLCD63_MASK                   0x4u
+#define LCD_WF8B_BPCLCD63_SHIFT                  2
+#define LCD_WF8B_BPCLCD27_MASK                   0x4u
+#define LCD_WF8B_BPCLCD27_SHIFT                  2
+#define LCD_WF8B_BPCLCD17_MASK                   0x4u
+#define LCD_WF8B_BPCLCD17_SHIFT                  2
+#define LCD_WF8B_BPCLCD51_MASK                   0x4u
+#define LCD_WF8B_BPCLCD51_SHIFT                  2
+#define LCD_WF8B_BPCLCD9_MASK                    0x4u
+#define LCD_WF8B_BPCLCD9_SHIFT                   2
+#define LCD_WF8B_BPCLCD54_MASK                   0x4u
+#define LCD_WF8B_BPCLCD54_SHIFT                  2
+#define LCD_WF8B_BPCLCD15_MASK                   0x4u
+#define LCD_WF8B_BPCLCD15_SHIFT                  2
+#define LCD_WF8B_BPCLCD16_MASK                   0x4u
+#define LCD_WF8B_BPCLCD16_SHIFT                  2
+#define LCD_WF8B_BPCLCD14_MASK                   0x4u
+#define LCD_WF8B_BPCLCD14_SHIFT                  2
+#define LCD_WF8B_BPCLCD32_MASK                   0x4u
+#define LCD_WF8B_BPCLCD32_SHIFT                  2
+#define LCD_WF8B_BPCLCD28_MASK                   0x4u
+#define LCD_WF8B_BPCLCD28_SHIFT                  2
+#define LCD_WF8B_BPCLCD53_MASK                   0x4u
+#define LCD_WF8B_BPCLCD53_SHIFT                  2
+#define LCD_WF8B_BPCLCD33_MASK                   0x4u
+#define LCD_WF8B_BPCLCD33_SHIFT                  2
+#define LCD_WF8B_BPCLCD0_MASK                    0x4u
+#define LCD_WF8B_BPCLCD0_SHIFT                   2
+#define LCD_WF8B_BPCLCD43_MASK                   0x4u
+#define LCD_WF8B_BPCLCD43_SHIFT                  2
+#define LCD_WF8B_BPCLCD7_MASK                    0x4u
+#define LCD_WF8B_BPCLCD7_SHIFT                   2
+#define LCD_WF8B_BPCLCD4_MASK                    0x4u
+#define LCD_WF8B_BPCLCD4_SHIFT                   2
+#define LCD_WF8B_BPCLCD34_MASK                   0x4u
+#define LCD_WF8B_BPCLCD34_SHIFT                  2
+#define LCD_WF8B_BPCLCD29_MASK                   0x4u
+#define LCD_WF8B_BPCLCD29_SHIFT                  2
+#define LCD_WF8B_BPCLCD45_MASK                   0x4u
+#define LCD_WF8B_BPCLCD45_SHIFT                  2
+#define LCD_WF8B_BPCLCD57_MASK                   0x4u
+#define LCD_WF8B_BPCLCD57_SHIFT                  2
+#define LCD_WF8B_BPCLCD42_MASK                   0x4u
+#define LCD_WF8B_BPCLCD42_SHIFT                  2
+#define LCD_WF8B_BPCLCD35_MASK                   0x4u
+#define LCD_WF8B_BPCLCD35_SHIFT                  2
+#define LCD_WF8B_BPCLCD13_MASK                   0x4u
+#define LCD_WF8B_BPCLCD13_SHIFT                  2
+#define LCD_WF8B_BPCLCD36_MASK                   0x4u
+#define LCD_WF8B_BPCLCD36_SHIFT                  2
+#define LCD_WF8B_BPCLCD30_MASK                   0x4u
+#define LCD_WF8B_BPCLCD30_SHIFT                  2
+#define LCD_WF8B_BPCLCD52_MASK                   0x4u
+#define LCD_WF8B_BPCLCD52_SHIFT                  2
+#define LCD_WF8B_BPCLCD58_MASK                   0x4u
+#define LCD_WF8B_BPCLCD58_SHIFT                  2
+#define LCD_WF8B_BPCLCD41_MASK                   0x4u
+#define LCD_WF8B_BPCLCD41_SHIFT                  2
+#define LCD_WF8B_BPCLCD37_MASK                   0x4u
+#define LCD_WF8B_BPCLCD37_SHIFT                  2
+#define LCD_WF8B_BPCLCD3_MASK                    0x4u
+#define LCD_WF8B_BPCLCD3_SHIFT                   2
+#define LCD_WF8B_BPCLCD12_MASK                   0x4u
+#define LCD_WF8B_BPCLCD12_SHIFT                  2
+#define LCD_WF8B_BPCLCD11_MASK                   0x4u
+#define LCD_WF8B_BPCLCD11_SHIFT                  2
+#define LCD_WF8B_BPCLCD38_MASK                   0x4u
+#define LCD_WF8B_BPCLCD38_SHIFT                  2
+#define LCD_WF8B_BPCLCD44_MASK                   0x4u
+#define LCD_WF8B_BPCLCD44_SHIFT                  2
+#define LCD_WF8B_BPCLCD31_MASK                   0x4u
+#define LCD_WF8B_BPCLCD31_SHIFT                  2
+#define LCD_WF8B_BPCLCD40_MASK                   0x4u
+#define LCD_WF8B_BPCLCD40_SHIFT                  2
+#define LCD_WF8B_BPCLCD62_MASK                   0x4u
+#define LCD_WF8B_BPCLCD62_SHIFT                  2
+#define LCD_WF8B_BPCLCD56_MASK                   0x4u
+#define LCD_WF8B_BPCLCD56_SHIFT                  2
+#define LCD_WF8B_BPCLCD39_MASK                   0x4u
+#define LCD_WF8B_BPCLCD39_SHIFT                  2
+#define LCD_WF8B_BPCLCD6_MASK                    0x4u
+#define LCD_WF8B_BPCLCD6_SHIFT                   2
+#define LCD_WF8B_BPDLCD47_MASK                   0x8u
+#define LCD_WF8B_BPDLCD47_SHIFT                  3
+#define LCD_WF8B_BPDLCD23_MASK                   0x8u
+#define LCD_WF8B_BPDLCD23_SHIFT                  3
+#define LCD_WF8B_BPDLCD48_MASK                   0x8u
+#define LCD_WF8B_BPDLCD48_SHIFT                  3
+#define LCD_WF8B_BPDLCD24_MASK                   0x8u
+#define LCD_WF8B_BPDLCD24_SHIFT                  3
+#define LCD_WF8B_BPDLCD15_MASK                   0x8u
+#define LCD_WF8B_BPDLCD15_SHIFT                  3
+#define LCD_WF8B_BPDLCD22_MASK                   0x8u
+#define LCD_WF8B_BPDLCD22_SHIFT                  3
+#define LCD_WF8B_BPDLCD60_MASK                   0x8u
+#define LCD_WF8B_BPDLCD60_SHIFT                  3
+#define LCD_WF8B_BPDLCD10_MASK                   0x8u
+#define LCD_WF8B_BPDLCD10_SHIFT                  3
+#define LCD_WF8B_BPDLCD21_MASK                   0x8u
+#define LCD_WF8B_BPDLCD21_SHIFT                  3
+#define LCD_WF8B_BPDLCD49_MASK                   0x8u
+#define LCD_WF8B_BPDLCD49_SHIFT                  3
+#define LCD_WF8B_BPDLCD1_MASK                    0x8u
+#define LCD_WF8B_BPDLCD1_SHIFT                   3
+#define LCD_WF8B_BPDLCD25_MASK                   0x8u
+#define LCD_WF8B_BPDLCD25_SHIFT                  3
+#define LCD_WF8B_BPDLCD20_MASK                   0x8u
+#define LCD_WF8B_BPDLCD20_SHIFT                  3
+#define LCD_WF8B_BPDLCD2_MASK                    0x8u
+#define LCD_WF8B_BPDLCD2_SHIFT                   3
+#define LCD_WF8B_BPDLCD55_MASK                   0x8u
+#define LCD_WF8B_BPDLCD55_SHIFT                  3
+#define LCD_WF8B_BPDLCD59_MASK                   0x8u
+#define LCD_WF8B_BPDLCD59_SHIFT                  3
+#define LCD_WF8B_BPDLCD5_MASK                    0x8u
+#define LCD_WF8B_BPDLCD5_SHIFT                   3
+#define LCD_WF8B_BPDLCD19_MASK                   0x8u
+#define LCD_WF8B_BPDLCD19_SHIFT                  3
+#define LCD_WF8B_BPDLCD6_MASK                    0x8u
+#define LCD_WF8B_BPDLCD6_SHIFT                   3
+#define LCD_WF8B_BPDLCD26_MASK                   0x8u
+#define LCD_WF8B_BPDLCD26_SHIFT                  3
+#define LCD_WF8B_BPDLCD0_MASK                    0x8u
+#define LCD_WF8B_BPDLCD0_SHIFT                   3
+#define LCD_WF8B_BPDLCD50_MASK                   0x8u
+#define LCD_WF8B_BPDLCD50_SHIFT                  3
+#define LCD_WF8B_BPDLCD46_MASK                   0x8u
+#define LCD_WF8B_BPDLCD46_SHIFT                  3
+#define LCD_WF8B_BPDLCD18_MASK                   0x8u
+#define LCD_WF8B_BPDLCD18_SHIFT                  3
+#define LCD_WF8B_BPDLCD61_MASK                   0x8u
+#define LCD_WF8B_BPDLCD61_SHIFT                  3
+#define LCD_WF8B_BPDLCD9_MASK                    0x8u
+#define LCD_WF8B_BPDLCD9_SHIFT                   3
+#define LCD_WF8B_BPDLCD17_MASK                   0x8u
+#define LCD_WF8B_BPDLCD17_SHIFT                  3
+#define LCD_WF8B_BPDLCD27_MASK                   0x8u
+#define LCD_WF8B_BPDLCD27_SHIFT                  3
+#define LCD_WF8B_BPDLCD53_MASK                   0x8u
+#define LCD_WF8B_BPDLCD53_SHIFT                  3
+#define LCD_WF8B_BPDLCD51_MASK                   0x8u
+#define LCD_WF8B_BPDLCD51_SHIFT                  3
+#define LCD_WF8B_BPDLCD54_MASK                   0x8u
+#define LCD_WF8B_BPDLCD54_SHIFT                  3
+#define LCD_WF8B_BPDLCD13_MASK                   0x8u
+#define LCD_WF8B_BPDLCD13_SHIFT                  3
+#define LCD_WF8B_BPDLCD16_MASK                   0x8u
+#define LCD_WF8B_BPDLCD16_SHIFT                  3
+#define LCD_WF8B_BPDLCD32_MASK                   0x8u
+#define LCD_WF8B_BPDLCD32_SHIFT                  3
+#define LCD_WF8B_BPDLCD14_MASK                   0x8u
+#define LCD_WF8B_BPDLCD14_SHIFT                  3
+#define LCD_WF8B_BPDLCD28_MASK                   0x8u
+#define LCD_WF8B_BPDLCD28_SHIFT                  3
+#define LCD_WF8B_BPDLCD43_MASK                   0x8u
+#define LCD_WF8B_BPDLCD43_SHIFT                  3
+#define LCD_WF8B_BPDLCD4_MASK                    0x8u
+#define LCD_WF8B_BPDLCD4_SHIFT                   3
+#define LCD_WF8B_BPDLCD45_MASK                   0x8u
+#define LCD_WF8B_BPDLCD45_SHIFT                  3
+#define LCD_WF8B_BPDLCD8_MASK                    0x8u
+#define LCD_WF8B_BPDLCD8_SHIFT                   3
+#define LCD_WF8B_BPDLCD62_MASK                   0x8u
+#define LCD_WF8B_BPDLCD62_SHIFT                  3
+#define LCD_WF8B_BPDLCD33_MASK                   0x8u
+#define LCD_WF8B_BPDLCD33_SHIFT                  3
+#define LCD_WF8B_BPDLCD34_MASK                   0x8u
+#define LCD_WF8B_BPDLCD34_SHIFT                  3
+#define LCD_WF8B_BPDLCD29_MASK                   0x8u
+#define LCD_WF8B_BPDLCD29_SHIFT                  3
+#define LCD_WF8B_BPDLCD58_MASK                   0x8u
+#define LCD_WF8B_BPDLCD58_SHIFT                  3
+#define LCD_WF8B_BPDLCD57_MASK                   0x8u
+#define LCD_WF8B_BPDLCD57_SHIFT                  3
+#define LCD_WF8B_BPDLCD42_MASK                   0x8u
+#define LCD_WF8B_BPDLCD42_SHIFT                  3
+#define LCD_WF8B_BPDLCD35_MASK                   0x8u
+#define LCD_WF8B_BPDLCD35_SHIFT                  3
+#define LCD_WF8B_BPDLCD52_MASK                   0x8u
+#define LCD_WF8B_BPDLCD52_SHIFT                  3
+#define LCD_WF8B_BPDLCD7_MASK                    0x8u
+#define LCD_WF8B_BPDLCD7_SHIFT                   3
+#define LCD_WF8B_BPDLCD36_MASK                   0x8u
+#define LCD_WF8B_BPDLCD36_SHIFT                  3
+#define LCD_WF8B_BPDLCD30_MASK                   0x8u
+#define LCD_WF8B_BPDLCD30_SHIFT                  3
+#define LCD_WF8B_BPDLCD41_MASK                   0x8u
+#define LCD_WF8B_BPDLCD41_SHIFT                  3
+#define LCD_WF8B_BPDLCD37_MASK                   0x8u
+#define LCD_WF8B_BPDLCD37_SHIFT                  3
+#define LCD_WF8B_BPDLCD44_MASK                   0x8u
+#define LCD_WF8B_BPDLCD44_SHIFT                  3
+#define LCD_WF8B_BPDLCD63_MASK                   0x8u
+#define LCD_WF8B_BPDLCD63_SHIFT                  3
+#define LCD_WF8B_BPDLCD38_MASK                   0x8u
+#define LCD_WF8B_BPDLCD38_SHIFT                  3
+#define LCD_WF8B_BPDLCD56_MASK                   0x8u
+#define LCD_WF8B_BPDLCD56_SHIFT                  3
+#define LCD_WF8B_BPDLCD40_MASK                   0x8u
+#define LCD_WF8B_BPDLCD40_SHIFT                  3
+#define LCD_WF8B_BPDLCD31_MASK                   0x8u
+#define LCD_WF8B_BPDLCD31_SHIFT                  3
+#define LCD_WF8B_BPDLCD12_MASK                   0x8u
+#define LCD_WF8B_BPDLCD12_SHIFT                  3
+#define LCD_WF8B_BPDLCD39_MASK                   0x8u
+#define LCD_WF8B_BPDLCD39_SHIFT                  3
+#define LCD_WF8B_BPDLCD3_MASK                    0x8u
+#define LCD_WF8B_BPDLCD3_SHIFT                   3
+#define LCD_WF8B_BPDLCD11_MASK                   0x8u
+#define LCD_WF8B_BPDLCD11_SHIFT                  3
+#define LCD_WF8B_BPELCD12_MASK                   0x10u
+#define LCD_WF8B_BPELCD12_SHIFT                  4
+#define LCD_WF8B_BPELCD39_MASK                   0x10u
+#define LCD_WF8B_BPELCD39_SHIFT                  4
+#define LCD_WF8B_BPELCD3_MASK                    0x10u
+#define LCD_WF8B_BPELCD3_SHIFT                   4
+#define LCD_WF8B_BPELCD38_MASK                   0x10u
+#define LCD_WF8B_BPELCD38_SHIFT                  4
+#define LCD_WF8B_BPELCD40_MASK                   0x10u
+#define LCD_WF8B_BPELCD40_SHIFT                  4
+#define LCD_WF8B_BPELCD37_MASK                   0x10u
+#define LCD_WF8B_BPELCD37_SHIFT                  4
+#define LCD_WF8B_BPELCD41_MASK                   0x10u
+#define LCD_WF8B_BPELCD41_SHIFT                  4
+#define LCD_WF8B_BPELCD36_MASK                   0x10u
+#define LCD_WF8B_BPELCD36_SHIFT                  4
+#define LCD_WF8B_BPELCD8_MASK                    0x10u
+#define LCD_WF8B_BPELCD8_SHIFT                   4
+#define LCD_WF8B_BPELCD35_MASK                   0x10u
+#define LCD_WF8B_BPELCD35_SHIFT                  4
+#define LCD_WF8B_BPELCD42_MASK                   0x10u
+#define LCD_WF8B_BPELCD42_SHIFT                  4
+#define LCD_WF8B_BPELCD34_MASK                   0x10u
+#define LCD_WF8B_BPELCD34_SHIFT                  4
+#define LCD_WF8B_BPELCD33_MASK                   0x10u
+#define LCD_WF8B_BPELCD33_SHIFT                  4
+#define LCD_WF8B_BPELCD11_MASK                   0x10u
+#define LCD_WF8B_BPELCD11_SHIFT                  4
+#define LCD_WF8B_BPELCD43_MASK                   0x10u
+#define LCD_WF8B_BPELCD43_SHIFT                  4
+#define LCD_WF8B_BPELCD32_MASK                   0x10u
+#define LCD_WF8B_BPELCD32_SHIFT                  4
+#define LCD_WF8B_BPELCD31_MASK                   0x10u
+#define LCD_WF8B_BPELCD31_SHIFT                  4
+#define LCD_WF8B_BPELCD44_MASK                   0x10u
+#define LCD_WF8B_BPELCD44_SHIFT                  4
+#define LCD_WF8B_BPELCD30_MASK                   0x10u
+#define LCD_WF8B_BPELCD30_SHIFT                  4
+#define LCD_WF8B_BPELCD29_MASK                   0x10u
+#define LCD_WF8B_BPELCD29_SHIFT                  4
+#define LCD_WF8B_BPELCD7_MASK                    0x10u
+#define LCD_WF8B_BPELCD7_SHIFT                   4
+#define LCD_WF8B_BPELCD45_MASK                   0x10u
+#define LCD_WF8B_BPELCD45_SHIFT                  4
+#define LCD_WF8B_BPELCD28_MASK                   0x10u
+#define LCD_WF8B_BPELCD28_SHIFT                  4
+#define LCD_WF8B_BPELCD2_MASK                    0x10u
+#define LCD_WF8B_BPELCD2_SHIFT                   4
+#define LCD_WF8B_BPELCD27_MASK                   0x10u
+#define LCD_WF8B_BPELCD27_SHIFT                  4
+#define LCD_WF8B_BPELCD46_MASK                   0x10u
+#define LCD_WF8B_BPELCD46_SHIFT                  4
+#define LCD_WF8B_BPELCD26_MASK                   0x10u
+#define LCD_WF8B_BPELCD26_SHIFT                  4
+#define LCD_WF8B_BPELCD10_MASK                   0x10u
+#define LCD_WF8B_BPELCD10_SHIFT                  4
+#define LCD_WF8B_BPELCD13_MASK                   0x10u
+#define LCD_WF8B_BPELCD13_SHIFT                  4
+#define LCD_WF8B_BPELCD25_MASK                   0x10u
+#define LCD_WF8B_BPELCD25_SHIFT                  4
+#define LCD_WF8B_BPELCD5_MASK                    0x10u
+#define LCD_WF8B_BPELCD5_SHIFT                   4
+#define LCD_WF8B_BPELCD24_MASK                   0x10u
+#define LCD_WF8B_BPELCD24_SHIFT                  4
+#define LCD_WF8B_BPELCD47_MASK                   0x10u
+#define LCD_WF8B_BPELCD47_SHIFT                  4
+#define LCD_WF8B_BPELCD23_MASK                   0x10u
+#define LCD_WF8B_BPELCD23_SHIFT                  4
+#define LCD_WF8B_BPELCD22_MASK                   0x10u
+#define LCD_WF8B_BPELCD22_SHIFT                  4
+#define LCD_WF8B_BPELCD48_MASK                   0x10u
+#define LCD_WF8B_BPELCD48_SHIFT                  4
+#define LCD_WF8B_BPELCD21_MASK                   0x10u
+#define LCD_WF8B_BPELCD21_SHIFT                  4
+#define LCD_WF8B_BPELCD49_MASK                   0x10u
+#define LCD_WF8B_BPELCD49_SHIFT                  4
+#define LCD_WF8B_BPELCD20_MASK                   0x10u
+#define LCD_WF8B_BPELCD20_SHIFT                  4
+#define LCD_WF8B_BPELCD19_MASK                   0x10u
+#define LCD_WF8B_BPELCD19_SHIFT                  4
+#define LCD_WF8B_BPELCD9_MASK                    0x10u
+#define LCD_WF8B_BPELCD9_SHIFT                   4
+#define LCD_WF8B_BPELCD50_MASK                   0x10u
+#define LCD_WF8B_BPELCD50_SHIFT                  4
+#define LCD_WF8B_BPELCD18_MASK                   0x10u
+#define LCD_WF8B_BPELCD18_SHIFT                  4
+#define LCD_WF8B_BPELCD6_MASK                    0x10u
+#define LCD_WF8B_BPELCD6_SHIFT                   4
+#define LCD_WF8B_BPELCD17_MASK                   0x10u
+#define LCD_WF8B_BPELCD17_SHIFT                  4
+#define LCD_WF8B_BPELCD51_MASK                   0x10u
+#define LCD_WF8B_BPELCD51_SHIFT                  4
+#define LCD_WF8B_BPELCD16_MASK                   0x10u
+#define LCD_WF8B_BPELCD16_SHIFT                  4
+#define LCD_WF8B_BPELCD56_MASK                   0x10u
+#define LCD_WF8B_BPELCD56_SHIFT                  4
+#define LCD_WF8B_BPELCD57_MASK                   0x10u
+#define LCD_WF8B_BPELCD57_SHIFT                  4
+#define LCD_WF8B_BPELCD52_MASK                   0x10u
+#define LCD_WF8B_BPELCD52_SHIFT                  4
+#define LCD_WF8B_BPELCD1_MASK                    0x10u
+#define LCD_WF8B_BPELCD1_SHIFT                   4
+#define LCD_WF8B_BPELCD58_MASK                   0x10u
+#define LCD_WF8B_BPELCD58_SHIFT                  4
+#define LCD_WF8B_BPELCD59_MASK                   0x10u
+#define LCD_WF8B_BPELCD59_SHIFT                  4
+#define LCD_WF8B_BPELCD53_MASK                   0x10u
+#define LCD_WF8B_BPELCD53_SHIFT                  4
+#define LCD_WF8B_BPELCD14_MASK                   0x10u
+#define LCD_WF8B_BPELCD14_SHIFT                  4
+#define LCD_WF8B_BPELCD0_MASK                    0x10u
+#define LCD_WF8B_BPELCD0_SHIFT                   4
+#define LCD_WF8B_BPELCD60_MASK                   0x10u
+#define LCD_WF8B_BPELCD60_SHIFT                  4
+#define LCD_WF8B_BPELCD15_MASK                   0x10u
+#define LCD_WF8B_BPELCD15_SHIFT                  4
+#define LCD_WF8B_BPELCD61_MASK                   0x10u
+#define LCD_WF8B_BPELCD61_SHIFT                  4
+#define LCD_WF8B_BPELCD54_MASK                   0x10u
+#define LCD_WF8B_BPELCD54_SHIFT                  4
+#define LCD_WF8B_BPELCD62_MASK                   0x10u
+#define LCD_WF8B_BPELCD62_SHIFT                  4
+#define LCD_WF8B_BPELCD63_MASK                   0x10u
+#define LCD_WF8B_BPELCD63_SHIFT                  4
+#define LCD_WF8B_BPELCD55_MASK                   0x10u
+#define LCD_WF8B_BPELCD55_SHIFT                  4
+#define LCD_WF8B_BPELCD4_MASK                    0x10u
+#define LCD_WF8B_BPELCD4_SHIFT                   4
+#define LCD_WF8B_BPFLCD13_MASK                   0x20u
+#define LCD_WF8B_BPFLCD13_SHIFT                  5
+#define LCD_WF8B_BPFLCD39_MASK                   0x20u
+#define LCD_WF8B_BPFLCD39_SHIFT                  5
+#define LCD_WF8B_BPFLCD55_MASK                   0x20u
+#define LCD_WF8B_BPFLCD55_SHIFT                  5
+#define LCD_WF8B_BPFLCD47_MASK                   0x20u
+#define LCD_WF8B_BPFLCD47_SHIFT                  5
+#define LCD_WF8B_BPFLCD63_MASK                   0x20u
+#define LCD_WF8B_BPFLCD63_SHIFT                  5
+#define LCD_WF8B_BPFLCD43_MASK                   0x20u
+#define LCD_WF8B_BPFLCD43_SHIFT                  5
+#define LCD_WF8B_BPFLCD5_MASK                    0x20u
+#define LCD_WF8B_BPFLCD5_SHIFT                   5
+#define LCD_WF8B_BPFLCD62_MASK                   0x20u
+#define LCD_WF8B_BPFLCD62_SHIFT                  5
+#define LCD_WF8B_BPFLCD14_MASK                   0x20u
+#define LCD_WF8B_BPFLCD14_SHIFT                  5
+#define LCD_WF8B_BPFLCD24_MASK                   0x20u
+#define LCD_WF8B_BPFLCD24_SHIFT                  5
+#define LCD_WF8B_BPFLCD54_MASK                   0x20u
+#define LCD_WF8B_BPFLCD54_SHIFT                  5
+#define LCD_WF8B_BPFLCD15_MASK                   0x20u
+#define LCD_WF8B_BPFLCD15_SHIFT                  5
+#define LCD_WF8B_BPFLCD32_MASK                   0x20u
+#define LCD_WF8B_BPFLCD32_SHIFT                  5
+#define LCD_WF8B_BPFLCD61_MASK                   0x20u
+#define LCD_WF8B_BPFLCD61_SHIFT                  5
+#define LCD_WF8B_BPFLCD25_MASK                   0x20u
+#define LCD_WF8B_BPFLCD25_SHIFT                  5
+#define LCD_WF8B_BPFLCD60_MASK                   0x20u
+#define LCD_WF8B_BPFLCD60_SHIFT                  5
+#define LCD_WF8B_BPFLCD41_MASK                   0x20u
+#define LCD_WF8B_BPFLCD41_SHIFT                  5
+#define LCD_WF8B_BPFLCD33_MASK                   0x20u
+#define LCD_WF8B_BPFLCD33_SHIFT                  5
+#define LCD_WF8B_BPFLCD53_MASK                   0x20u
+#define LCD_WF8B_BPFLCD53_SHIFT                  5
+#define LCD_WF8B_BPFLCD59_MASK                   0x20u
+#define LCD_WF8B_BPFLCD59_SHIFT                  5
+#define LCD_WF8B_BPFLCD0_MASK                    0x20u
+#define LCD_WF8B_BPFLCD0_SHIFT                   5
+#define LCD_WF8B_BPFLCD46_MASK                   0x20u
+#define LCD_WF8B_BPFLCD46_SHIFT                  5
+#define LCD_WF8B_BPFLCD58_MASK                   0x20u
+#define LCD_WF8B_BPFLCD58_SHIFT                  5
+#define LCD_WF8B_BPFLCD26_MASK                   0x20u
+#define LCD_WF8B_BPFLCD26_SHIFT                  5
+#define LCD_WF8B_BPFLCD36_MASK                   0x20u
+#define LCD_WF8B_BPFLCD36_SHIFT                  5
+#define LCD_WF8B_BPFLCD10_MASK                   0x20u
+#define LCD_WF8B_BPFLCD10_SHIFT                  5
+#define LCD_WF8B_BPFLCD52_MASK                   0x20u
+#define LCD_WF8B_BPFLCD52_SHIFT                  5
+#define LCD_WF8B_BPFLCD57_MASK                   0x20u
+#define LCD_WF8B_BPFLCD57_SHIFT                  5
+#define LCD_WF8B_BPFLCD27_MASK                   0x20u
+#define LCD_WF8B_BPFLCD27_SHIFT                  5
+#define LCD_WF8B_BPFLCD11_MASK                   0x20u
+#define LCD_WF8B_BPFLCD11_SHIFT                  5
+#define LCD_WF8B_BPFLCD56_MASK                   0x20u
+#define LCD_WF8B_BPFLCD56_SHIFT                  5
+#define LCD_WF8B_BPFLCD1_MASK                    0x20u
+#define LCD_WF8B_BPFLCD1_SHIFT                   5
+#define LCD_WF8B_BPFLCD8_MASK                    0x20u
+#define LCD_WF8B_BPFLCD8_SHIFT                   5
+#define LCD_WF8B_BPFLCD40_MASK                   0x20u
+#define LCD_WF8B_BPFLCD40_SHIFT                  5
+#define LCD_WF8B_BPFLCD51_MASK                   0x20u
+#define LCD_WF8B_BPFLCD51_SHIFT                  5
+#define LCD_WF8B_BPFLCD16_MASK                   0x20u
+#define LCD_WF8B_BPFLCD16_SHIFT                  5
+#define LCD_WF8B_BPFLCD45_MASK                   0x20u
+#define LCD_WF8B_BPFLCD45_SHIFT                  5
+#define LCD_WF8B_BPFLCD6_MASK                    0x20u
+#define LCD_WF8B_BPFLCD6_SHIFT                   5
+#define LCD_WF8B_BPFLCD17_MASK                   0x20u
+#define LCD_WF8B_BPFLCD17_SHIFT                  5
+#define LCD_WF8B_BPFLCD28_MASK                   0x20u
+#define LCD_WF8B_BPFLCD28_SHIFT                  5
+#define LCD_WF8B_BPFLCD42_MASK                   0x20u
+#define LCD_WF8B_BPFLCD42_SHIFT                  5
+#define LCD_WF8B_BPFLCD29_MASK                   0x20u
+#define LCD_WF8B_BPFLCD29_SHIFT                  5
+#define LCD_WF8B_BPFLCD50_MASK                   0x20u
+#define LCD_WF8B_BPFLCD50_SHIFT                  5
+#define LCD_WF8B_BPFLCD18_MASK                   0x20u
+#define LCD_WF8B_BPFLCD18_SHIFT                  5
+#define LCD_WF8B_BPFLCD34_MASK                   0x20u
+#define LCD_WF8B_BPFLCD34_SHIFT                  5
+#define LCD_WF8B_BPFLCD19_MASK                   0x20u
+#define LCD_WF8B_BPFLCD19_SHIFT                  5
+#define LCD_WF8B_BPFLCD2_MASK                    0x20u
+#define LCD_WF8B_BPFLCD2_SHIFT                   5
+#define LCD_WF8B_BPFLCD9_MASK                    0x20u
+#define LCD_WF8B_BPFLCD9_SHIFT                   5
+#define LCD_WF8B_BPFLCD3_MASK                    0x20u
+#define LCD_WF8B_BPFLCD3_SHIFT                   5
+#define LCD_WF8B_BPFLCD37_MASK                   0x20u
+#define LCD_WF8B_BPFLCD37_SHIFT                  5
+#define LCD_WF8B_BPFLCD49_MASK                   0x20u
+#define LCD_WF8B_BPFLCD49_SHIFT                  5
+#define LCD_WF8B_BPFLCD20_MASK                   0x20u
+#define LCD_WF8B_BPFLCD20_SHIFT                  5
+#define LCD_WF8B_BPFLCD44_MASK                   0x20u
+#define LCD_WF8B_BPFLCD44_SHIFT                  5
+#define LCD_WF8B_BPFLCD30_MASK                   0x20u
+#define LCD_WF8B_BPFLCD30_SHIFT                  5
+#define LCD_WF8B_BPFLCD21_MASK                   0x20u
+#define LCD_WF8B_BPFLCD21_SHIFT                  5
+#define LCD_WF8B_BPFLCD35_MASK                   0x20u
+#define LCD_WF8B_BPFLCD35_SHIFT                  5
+#define LCD_WF8B_BPFLCD4_MASK                    0x20u
+#define LCD_WF8B_BPFLCD4_SHIFT                   5
+#define LCD_WF8B_BPFLCD31_MASK                   0x20u
+#define LCD_WF8B_BPFLCD31_SHIFT                  5
+#define LCD_WF8B_BPFLCD48_MASK                   0x20u
+#define LCD_WF8B_BPFLCD48_SHIFT                  5
+#define LCD_WF8B_BPFLCD7_MASK                    0x20u
+#define LCD_WF8B_BPFLCD7_SHIFT                   5
+#define LCD_WF8B_BPFLCD22_MASK                   0x20u
+#define LCD_WF8B_BPFLCD22_SHIFT                  5
+#define LCD_WF8B_BPFLCD38_MASK                   0x20u
+#define LCD_WF8B_BPFLCD38_SHIFT                  5
+#define LCD_WF8B_BPFLCD12_MASK                   0x20u
+#define LCD_WF8B_BPFLCD12_SHIFT                  5
+#define LCD_WF8B_BPFLCD23_MASK                   0x20u
+#define LCD_WF8B_BPFLCD23_SHIFT                  5
+#define LCD_WF8B_BPGLCD14_MASK                   0x40u
+#define LCD_WF8B_BPGLCD14_SHIFT                  6
+#define LCD_WF8B_BPGLCD55_MASK                   0x40u
+#define LCD_WF8B_BPGLCD55_SHIFT                  6
+#define LCD_WF8B_BPGLCD63_MASK                   0x40u
+#define LCD_WF8B_BPGLCD63_SHIFT                  6
+#define LCD_WF8B_BPGLCD15_MASK                   0x40u
+#define LCD_WF8B_BPGLCD15_SHIFT                  6
+#define LCD_WF8B_BPGLCD62_MASK                   0x40u
+#define LCD_WF8B_BPGLCD62_SHIFT                  6
+#define LCD_WF8B_BPGLCD54_MASK                   0x40u
+#define LCD_WF8B_BPGLCD54_SHIFT                  6
+#define LCD_WF8B_BPGLCD61_MASK                   0x40u
+#define LCD_WF8B_BPGLCD61_SHIFT                  6
+#define LCD_WF8B_BPGLCD60_MASK                   0x40u
+#define LCD_WF8B_BPGLCD60_SHIFT                  6
+#define LCD_WF8B_BPGLCD59_MASK                   0x40u
+#define LCD_WF8B_BPGLCD59_SHIFT                  6
+#define LCD_WF8B_BPGLCD53_MASK                   0x40u
+#define LCD_WF8B_BPGLCD53_SHIFT                  6
+#define LCD_WF8B_BPGLCD58_MASK                   0x40u
+#define LCD_WF8B_BPGLCD58_SHIFT                  6
+#define LCD_WF8B_BPGLCD0_MASK                    0x40u
+#define LCD_WF8B_BPGLCD0_SHIFT                   6
+#define LCD_WF8B_BPGLCD57_MASK                   0x40u
+#define LCD_WF8B_BPGLCD57_SHIFT                  6
+#define LCD_WF8B_BPGLCD52_MASK                   0x40u
+#define LCD_WF8B_BPGLCD52_SHIFT                  6
+#define LCD_WF8B_BPGLCD7_MASK                    0x40u
+#define LCD_WF8B_BPGLCD7_SHIFT                   6
+#define LCD_WF8B_BPGLCD56_MASK                   0x40u
+#define LCD_WF8B_BPGLCD56_SHIFT                  6
+#define LCD_WF8B_BPGLCD6_MASK                    0x40u
+#define LCD_WF8B_BPGLCD6_SHIFT                   6
+#define LCD_WF8B_BPGLCD51_MASK                   0x40u
+#define LCD_WF8B_BPGLCD51_SHIFT                  6
+#define LCD_WF8B_BPGLCD16_MASK                   0x40u
+#define LCD_WF8B_BPGLCD16_SHIFT                  6
+#define LCD_WF8B_BPGLCD1_MASK                    0x40u
+#define LCD_WF8B_BPGLCD1_SHIFT                   6
+#define LCD_WF8B_BPGLCD17_MASK                   0x40u
+#define LCD_WF8B_BPGLCD17_SHIFT                  6
+#define LCD_WF8B_BPGLCD50_MASK                   0x40u
+#define LCD_WF8B_BPGLCD50_SHIFT                  6
+#define LCD_WF8B_BPGLCD18_MASK                   0x40u
+#define LCD_WF8B_BPGLCD18_SHIFT                  6
+#define LCD_WF8B_BPGLCD19_MASK                   0x40u
+#define LCD_WF8B_BPGLCD19_SHIFT                  6
+#define LCD_WF8B_BPGLCD8_MASK                    0x40u
+#define LCD_WF8B_BPGLCD8_SHIFT                   6
+#define LCD_WF8B_BPGLCD49_MASK                   0x40u
+#define LCD_WF8B_BPGLCD49_SHIFT                  6
+#define LCD_WF8B_BPGLCD20_MASK                   0x40u
+#define LCD_WF8B_BPGLCD20_SHIFT                  6
+#define LCD_WF8B_BPGLCD9_MASK                    0x40u
+#define LCD_WF8B_BPGLCD9_SHIFT                   6
+#define LCD_WF8B_BPGLCD21_MASK                   0x40u
+#define LCD_WF8B_BPGLCD21_SHIFT                  6
+#define LCD_WF8B_BPGLCD13_MASK                   0x40u
+#define LCD_WF8B_BPGLCD13_SHIFT                  6
+#define LCD_WF8B_BPGLCD48_MASK                   0x40u
+#define LCD_WF8B_BPGLCD48_SHIFT                  6
+#define LCD_WF8B_BPGLCD22_MASK                   0x40u
+#define LCD_WF8B_BPGLCD22_SHIFT                  6
+#define LCD_WF8B_BPGLCD5_MASK                    0x40u
+#define LCD_WF8B_BPGLCD5_SHIFT                   6
+#define LCD_WF8B_BPGLCD47_MASK                   0x40u
+#define LCD_WF8B_BPGLCD47_SHIFT                  6
+#define LCD_WF8B_BPGLCD23_MASK                   0x40u
+#define LCD_WF8B_BPGLCD23_SHIFT                  6
+#define LCD_WF8B_BPGLCD24_MASK                   0x40u
+#define LCD_WF8B_BPGLCD24_SHIFT                  6
+#define LCD_WF8B_BPGLCD25_MASK                   0x40u
+#define LCD_WF8B_BPGLCD25_SHIFT                  6
+#define LCD_WF8B_BPGLCD46_MASK                   0x40u
+#define LCD_WF8B_BPGLCD46_SHIFT                  6
+#define LCD_WF8B_BPGLCD26_MASK                   0x40u
+#define LCD_WF8B_BPGLCD26_SHIFT                  6
+#define LCD_WF8B_BPGLCD27_MASK                   0x40u
+#define LCD_WF8B_BPGLCD27_SHIFT                  6
+#define LCD_WF8B_BPGLCD10_MASK                   0x40u
+#define LCD_WF8B_BPGLCD10_SHIFT                  6
+#define LCD_WF8B_BPGLCD45_MASK                   0x40u
+#define LCD_WF8B_BPGLCD45_SHIFT                  6
+#define LCD_WF8B_BPGLCD28_MASK                   0x40u
+#define LCD_WF8B_BPGLCD28_SHIFT                  6
+#define LCD_WF8B_BPGLCD29_MASK                   0x40u
+#define LCD_WF8B_BPGLCD29_SHIFT                  6
+#define LCD_WF8B_BPGLCD4_MASK                    0x40u
+#define LCD_WF8B_BPGLCD4_SHIFT                   6
+#define LCD_WF8B_BPGLCD44_MASK                   0x40u
+#define LCD_WF8B_BPGLCD44_SHIFT                  6
+#define LCD_WF8B_BPGLCD30_MASK                   0x40u
+#define LCD_WF8B_BPGLCD30_SHIFT                  6
+#define LCD_WF8B_BPGLCD2_MASK                    0x40u
+#define LCD_WF8B_BPGLCD2_SHIFT                   6
+#define LCD_WF8B_BPGLCD31_MASK                   0x40u
+#define LCD_WF8B_BPGLCD31_SHIFT                  6
+#define LCD_WF8B_BPGLCD43_MASK                   0x40u
+#define LCD_WF8B_BPGLCD43_SHIFT                  6
+#define LCD_WF8B_BPGLCD32_MASK                   0x40u
+#define LCD_WF8B_BPGLCD32_SHIFT                  6
+#define LCD_WF8B_BPGLCD33_MASK                   0x40u
+#define LCD_WF8B_BPGLCD33_SHIFT                  6
+#define LCD_WF8B_BPGLCD42_MASK                   0x40u
+#define LCD_WF8B_BPGLCD42_SHIFT                  6
+#define LCD_WF8B_BPGLCD34_MASK                   0x40u
+#define LCD_WF8B_BPGLCD34_SHIFT                  6
+#define LCD_WF8B_BPGLCD11_MASK                   0x40u
+#define LCD_WF8B_BPGLCD11_SHIFT                  6
+#define LCD_WF8B_BPGLCD35_MASK                   0x40u
+#define LCD_WF8B_BPGLCD35_SHIFT                  6
+#define LCD_WF8B_BPGLCD12_MASK                   0x40u
+#define LCD_WF8B_BPGLCD12_SHIFT                  6
+#define LCD_WF8B_BPGLCD41_MASK                   0x40u
+#define LCD_WF8B_BPGLCD41_SHIFT                  6
+#define LCD_WF8B_BPGLCD36_MASK                   0x40u
+#define LCD_WF8B_BPGLCD36_SHIFT                  6
+#define LCD_WF8B_BPGLCD3_MASK                    0x40u
+#define LCD_WF8B_BPGLCD3_SHIFT                   6
+#define LCD_WF8B_BPGLCD37_MASK                   0x40u
+#define LCD_WF8B_BPGLCD37_SHIFT                  6
+#define LCD_WF8B_BPGLCD40_MASK                   0x40u
+#define LCD_WF8B_BPGLCD40_SHIFT                  6
+#define LCD_WF8B_BPGLCD38_MASK                   0x40u
+#define LCD_WF8B_BPGLCD38_SHIFT                  6
+#define LCD_WF8B_BPGLCD39_MASK                   0x40u
+#define LCD_WF8B_BPGLCD39_SHIFT                  6
+#define LCD_WF8B_BPHLCD63_MASK                   0x80u
+#define LCD_WF8B_BPHLCD63_SHIFT                  7
+#define LCD_WF8B_BPHLCD62_MASK                   0x80u
+#define LCD_WF8B_BPHLCD62_SHIFT                  7
+#define LCD_WF8B_BPHLCD61_MASK                   0x80u
+#define LCD_WF8B_BPHLCD61_SHIFT                  7
+#define LCD_WF8B_BPHLCD60_MASK                   0x80u
+#define LCD_WF8B_BPHLCD60_SHIFT                  7
+#define LCD_WF8B_BPHLCD59_MASK                   0x80u
+#define LCD_WF8B_BPHLCD59_SHIFT                  7
+#define LCD_WF8B_BPHLCD58_MASK                   0x80u
+#define LCD_WF8B_BPHLCD58_SHIFT                  7
+#define LCD_WF8B_BPHLCD57_MASK                   0x80u
+#define LCD_WF8B_BPHLCD57_SHIFT                  7
+#define LCD_WF8B_BPHLCD0_MASK                    0x80u
+#define LCD_WF8B_BPHLCD0_SHIFT                   7
+#define LCD_WF8B_BPHLCD56_MASK                   0x80u
+#define LCD_WF8B_BPHLCD56_SHIFT                  7
+#define LCD_WF8B_BPHLCD55_MASK                   0x80u
+#define LCD_WF8B_BPHLCD55_SHIFT                  7
+#define LCD_WF8B_BPHLCD54_MASK                   0x80u
+#define LCD_WF8B_BPHLCD54_SHIFT                  7
+#define LCD_WF8B_BPHLCD53_MASK                   0x80u
+#define LCD_WF8B_BPHLCD53_SHIFT                  7
+#define LCD_WF8B_BPHLCD52_MASK                   0x80u
+#define LCD_WF8B_BPHLCD52_SHIFT                  7
+#define LCD_WF8B_BPHLCD51_MASK                   0x80u
+#define LCD_WF8B_BPHLCD51_SHIFT                  7
+#define LCD_WF8B_BPHLCD50_MASK                   0x80u
+#define LCD_WF8B_BPHLCD50_SHIFT                  7
+#define LCD_WF8B_BPHLCD1_MASK                    0x80u
+#define LCD_WF8B_BPHLCD1_SHIFT                   7
+#define LCD_WF8B_BPHLCD49_MASK                   0x80u
+#define LCD_WF8B_BPHLCD49_SHIFT                  7
+#define LCD_WF8B_BPHLCD48_MASK                   0x80u
+#define LCD_WF8B_BPHLCD48_SHIFT                  7
+#define LCD_WF8B_BPHLCD47_MASK                   0x80u
+#define LCD_WF8B_BPHLCD47_SHIFT                  7
+#define LCD_WF8B_BPHLCD46_MASK                   0x80u
+#define LCD_WF8B_BPHLCD46_SHIFT                  7
+#define LCD_WF8B_BPHLCD45_MASK                   0x80u
+#define LCD_WF8B_BPHLCD45_SHIFT                  7
+#define LCD_WF8B_BPHLCD44_MASK                   0x80u
+#define LCD_WF8B_BPHLCD44_SHIFT                  7
+#define LCD_WF8B_BPHLCD43_MASK                   0x80u
+#define LCD_WF8B_BPHLCD43_SHIFT                  7
+#define LCD_WF8B_BPHLCD2_MASK                    0x80u
+#define LCD_WF8B_BPHLCD2_SHIFT                   7
+#define LCD_WF8B_BPHLCD42_MASK                   0x80u
+#define LCD_WF8B_BPHLCD42_SHIFT                  7
+#define LCD_WF8B_BPHLCD41_MASK                   0x80u
+#define LCD_WF8B_BPHLCD41_SHIFT                  7
+#define LCD_WF8B_BPHLCD40_MASK                   0x80u
+#define LCD_WF8B_BPHLCD40_SHIFT                  7
+#define LCD_WF8B_BPHLCD39_MASK                   0x80u
+#define LCD_WF8B_BPHLCD39_SHIFT                  7
+#define LCD_WF8B_BPHLCD38_MASK                   0x80u
+#define LCD_WF8B_BPHLCD38_SHIFT                  7
+#define LCD_WF8B_BPHLCD37_MASK                   0x80u
+#define LCD_WF8B_BPHLCD37_SHIFT                  7
+#define LCD_WF8B_BPHLCD36_MASK                   0x80u
+#define LCD_WF8B_BPHLCD36_SHIFT                  7
+#define LCD_WF8B_BPHLCD3_MASK                    0x80u
+#define LCD_WF8B_BPHLCD3_SHIFT                   7
+#define LCD_WF8B_BPHLCD35_MASK                   0x80u
+#define LCD_WF8B_BPHLCD35_SHIFT                  7
+#define LCD_WF8B_BPHLCD34_MASK                   0x80u
+#define LCD_WF8B_BPHLCD34_SHIFT                  7
+#define LCD_WF8B_BPHLCD33_MASK                   0x80u
+#define LCD_WF8B_BPHLCD33_SHIFT                  7
+#define LCD_WF8B_BPHLCD32_MASK                   0x80u
+#define LCD_WF8B_BPHLCD32_SHIFT                  7
+#define LCD_WF8B_BPHLCD31_MASK                   0x80u
+#define LCD_WF8B_BPHLCD31_SHIFT                  7
+#define LCD_WF8B_BPHLCD30_MASK                   0x80u
+#define LCD_WF8B_BPHLCD30_SHIFT                  7
+#define LCD_WF8B_BPHLCD29_MASK                   0x80u
+#define LCD_WF8B_BPHLCD29_SHIFT                  7
+#define LCD_WF8B_BPHLCD4_MASK                    0x80u
+#define LCD_WF8B_BPHLCD4_SHIFT                   7
+#define LCD_WF8B_BPHLCD28_MASK                   0x80u
+#define LCD_WF8B_BPHLCD28_SHIFT                  7
+#define LCD_WF8B_BPHLCD27_MASK                   0x80u
+#define LCD_WF8B_BPHLCD27_SHIFT                  7
+#define LCD_WF8B_BPHLCD26_MASK                   0x80u
+#define LCD_WF8B_BPHLCD26_SHIFT                  7
+#define LCD_WF8B_BPHLCD25_MASK                   0x80u
+#define LCD_WF8B_BPHLCD25_SHIFT                  7
+#define LCD_WF8B_BPHLCD24_MASK                   0x80u
+#define LCD_WF8B_BPHLCD24_SHIFT                  7
+#define LCD_WF8B_BPHLCD23_MASK                   0x80u
+#define LCD_WF8B_BPHLCD23_SHIFT                  7
+#define LCD_WF8B_BPHLCD22_MASK                   0x80u
+#define LCD_WF8B_BPHLCD22_SHIFT                  7
+#define LCD_WF8B_BPHLCD5_MASK                    0x80u
+#define LCD_WF8B_BPHLCD5_SHIFT                   7
+#define LCD_WF8B_BPHLCD21_MASK                   0x80u
+#define LCD_WF8B_BPHLCD21_SHIFT                  7
+#define LCD_WF8B_BPHLCD20_MASK                   0x80u
+#define LCD_WF8B_BPHLCD20_SHIFT                  7
+#define LCD_WF8B_BPHLCD19_MASK                   0x80u
+#define LCD_WF8B_BPHLCD19_SHIFT                  7
+#define LCD_WF8B_BPHLCD18_MASK                   0x80u
+#define LCD_WF8B_BPHLCD18_SHIFT                  7
+#define LCD_WF8B_BPHLCD17_MASK                   0x80u
+#define LCD_WF8B_BPHLCD17_SHIFT                  7
+#define LCD_WF8B_BPHLCD16_MASK                   0x80u
+#define LCD_WF8B_BPHLCD16_SHIFT                  7
+#define LCD_WF8B_BPHLCD15_MASK                   0x80u
+#define LCD_WF8B_BPHLCD15_SHIFT                  7
+#define LCD_WF8B_BPHLCD6_MASK                    0x80u
+#define LCD_WF8B_BPHLCD6_SHIFT                   7
+#define LCD_WF8B_BPHLCD14_MASK                   0x80u
+#define LCD_WF8B_BPHLCD14_SHIFT                  7
+#define LCD_WF8B_BPHLCD13_MASK                   0x80u
+#define LCD_WF8B_BPHLCD13_SHIFT                  7
+#define LCD_WF8B_BPHLCD12_MASK                   0x80u
+#define LCD_WF8B_BPHLCD12_SHIFT                  7
+#define LCD_WF8B_BPHLCD11_MASK                   0x80u
+#define LCD_WF8B_BPHLCD11_SHIFT                  7
+#define LCD_WF8B_BPHLCD10_MASK                   0x80u
+#define LCD_WF8B_BPHLCD10_SHIFT                  7
+#define LCD_WF8B_BPHLCD9_MASK                    0x80u
+#define LCD_WF8B_BPHLCD9_SHIFT                   7
+#define LCD_WF8B_BPHLCD8_MASK                    0x80u
+#define LCD_WF8B_BPHLCD8_SHIFT                   7
+#define LCD_WF8B_BPHLCD7_MASK                    0x80u
+#define LCD_WF8B_BPHLCD7_SHIFT                   7
+
+/**
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE                                 (0x40053000u)
+/** Peripheral LCD base pointer */
+#define LCD                                      ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASES                                { LCD }
+
+/**
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
 /* ----------------------------------------------------------------------------
    -- LLWU Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -1564,6 +3146,8 @@ typedef struct {
 #define MCG_C2_RANGE0_MASK                       0x30u
 #define MCG_C2_RANGE0_SHIFT                      4
 #define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
 #define MCG_C2_LOCRE0_MASK                       0x80u
 #define MCG_C2_LOCRE0_SHIFT                      7
 /* C3 Bit Fields */
@@ -2818,8 +4402,9 @@ typedef struct {
 #define SIM_SOPT2_UART0SRC_SHIFT                 26
 #define SIM_SOPT2_UART0SRC(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
 /* SOPT4 Bit Fields */
-#define SIM_SOPT4_TPM1CH0SRC_MASK                0x40000u
+#define SIM_SOPT4_TPM1CH0SRC_MASK                0xC0000u
 #define SIM_SOPT4_TPM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
 #define SIM_SOPT4_TPM2CH0SRC_MASK                0x100000u
 #define SIM_SOPT4_TPM2CH0SRC_SHIFT               20
 #define SIM_SOPT4_TPM0CLKSEL_MASK                0x1000000u
@@ -2909,11 +4494,15 @@ typedef struct {
 #define SIM_SCGC5_PORTD_SHIFT                    12
 #define SIM_SCGC5_PORTE_MASK                     0x2000u
 #define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_SLCD_MASK                      0x80000u
+#define SIM_SCGC5_SLCD_SHIFT                     19
 /* SCGC6 Bit Fields */
 #define SIM_SCGC6_FTF_MASK                       0x1u
 #define SIM_SCGC6_FTF_SHIFT                      0
 #define SIM_SCGC6_DMAMUX_MASK                    0x2u
 #define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
 #define SIM_SCGC6_PIT_MASK                       0x800000u
 #define SIM_SCGC6_PIT_SHIFT                      23
 #define SIM_SCGC6_TPM0_MASK                      0x1000000u
@@ -2947,9 +4536,12 @@ typedef struct {
 #define SIM_FCFG1_PFSIZE_SHIFT                   24
 #define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
 /* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR_MASK                   0x7F000000u
-#define SIM_FCFG2_MAXADDR_SHIFT                  24
-#define SIM_FCFG2_MAXADDR(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
 /* UIDMH Bit Fields */
 #define SIM_UIDMH_UID_MASK                       0xFFFFu
 #define SIM_UIDMH_UID_SHIFT                      0
@@ -3078,14 +4670,17 @@ typedef struct {
 
 /** SPI - Register Layout Typedef */
 typedef struct {
-  __IO uint8_t C1;                                 /**< SPI control register 1, offset: 0x0 */
-  __IO uint8_t C2;                                 /**< SPI control register 2, offset: 0x1 */
-  __IO uint8_t BR;                                 /**< SPI baud rate register, offset: 0x2 */
-  __I  uint8_t S;                                  /**< SPI status register, offset: 0x3 */
-       uint8_t RESERVED_0[1];
-  __IO uint8_t D;                                  /**< SPI data register, offset: 0x5 */
-       uint8_t RESERVED_1[1];
-  __IO uint8_t M;                                  /**< SPI match register, offset: 0x7 */
+  __I  uint8_t S;                                  /**< SPI status register, offset: 0x0 */
+  __IO uint8_t BR;                                 /**< SPI baud rate register, offset: 0x1 */
+  __IO uint8_t C2;                                 /**< SPI control register 2, offset: 0x2 */
+  __IO uint8_t C1;                                 /**< SPI control register 1, offset: 0x3 */
+  __IO uint8_t ML;                                 /**< SPI match register low, offset: 0x4 */
+  __IO uint8_t MH;                                 /**< SPI match register high, offset: 0x5 */
+  __IO uint8_t DL;                                 /**< SPI data register low, offset: 0x6 */
+  __IO uint8_t DH;                                 /**< SPI data register high, offset: 0x7 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t CI;                                 /**< SPI clear interrupt register, offset: 0xA */
+  __IO uint8_t C3;                                 /**< SPI control register 3, offset: 0xB */
 } SPI_Type;
 
 /* ----------------------------------------------------------------------------
@@ -3097,6 +4692,47 @@ typedef struct {
  * @{
  */
 
+/* S Bit Fields */
+#define SPI_S_RFIFOEF_MASK                       0x1u
+#define SPI_S_RFIFOEF_SHIFT                      0
+#define SPI_S_TXFULLF_MASK                       0x2u
+#define SPI_S_TXFULLF_SHIFT                      1
+#define SPI_S_TNEAREF_MASK                       0x4u
+#define SPI_S_TNEAREF_SHIFT                      2
+#define SPI_S_RNFULLF_MASK                       0x8u
+#define SPI_S_RNFULLF_SHIFT                      3
+#define SPI_S_MODF_MASK                          0x10u
+#define SPI_S_MODF_SHIFT                         4
+#define SPI_S_SPTEF_MASK                         0x20u
+#define SPI_S_SPTEF_SHIFT                        5
+#define SPI_S_SPMF_MASK                          0x40u
+#define SPI_S_SPMF_SHIFT                         6
+#define SPI_S_SPRF_MASK                          0x80u
+#define SPI_S_SPRF_SHIFT                         7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK                          0xFu
+#define SPI_BR_SPR_SHIFT                         0
+#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK                         0x70u
+#define SPI_BR_SPPR_SHIFT                        4
+#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK                         0x1u
+#define SPI_C2_SPC0_SHIFT                        0
+#define SPI_C2_SPISWAI_MASK                      0x2u
+#define SPI_C2_SPISWAI_SHIFT                     1
+#define SPI_C2_RXDMAE_MASK                       0x4u
+#define SPI_C2_RXDMAE_SHIFT                      2
+#define SPI_C2_BIDIROE_MASK                      0x8u
+#define SPI_C2_BIDIROE_SHIFT                     3
+#define SPI_C2_MODFEN_MASK                       0x10u
+#define SPI_C2_MODFEN_SHIFT                      4
+#define SPI_C2_TXDMAE_MASK                       0x20u
+#define SPI_C2_TXDMAE_SHIFT                      5
+#define SPI_C2_SPIMODE_MASK                      0x40u
+#define SPI_C2_SPIMODE_SHIFT                     6
+#define SPI_C2_SPMIE_MASK                        0x80u
+#define SPI_C2_SPMIE_SHIFT                       7
 /* C1 Bit Fields */
 #define SPI_C1_LSBFE_MASK                        0x1u
 #define SPI_C1_LSBFE_SHIFT                       0
@@ -3114,47 +4750,52 @@ typedef struct {
 #define SPI_C1_SPE_SHIFT                         6
 #define SPI_C1_SPIE_MASK                         0x80u
 #define SPI_C1_SPIE_SHIFT                        7
-/* C2 Bit Fields */
-#define SPI_C2_SPC0_MASK                         0x1u
-#define SPI_C2_SPC0_SHIFT                        0
-#define SPI_C2_SPISWAI_MASK                      0x2u
-#define SPI_C2_SPISWAI_SHIFT                     1
-#define SPI_C2_RXDMAE_MASK                       0x4u
-#define SPI_C2_RXDMAE_SHIFT                      2
-#define SPI_C2_BIDIROE_MASK                      0x8u
-#define SPI_C2_BIDIROE_SHIFT                     3
-#define SPI_C2_MODFEN_MASK                       0x10u
-#define SPI_C2_MODFEN_SHIFT                      4
-#define SPI_C2_TXDMAE_MASK                       0x20u
-#define SPI_C2_TXDMAE_SHIFT                      5
-#define SPI_C2_SPLPIE_MASK                       0x40u
-#define SPI_C2_SPLPIE_SHIFT                      6
-#define SPI_C2_SPMIE_MASK                        0x80u
-#define SPI_C2_SPMIE_SHIFT                       7
-/* BR Bit Fields */
-#define SPI_BR_SPR_MASK                          0xFu
-#define SPI_BR_SPR_SHIFT                         0
-#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
-#define SPI_BR_SPPR_MASK                         0x70u
-#define SPI_BR_SPPR_SHIFT                        4
-#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
-/* S Bit Fields */
-#define SPI_S_MODF_MASK                          0x10u
-#define SPI_S_MODF_SHIFT                         4
-#define SPI_S_SPTEF_MASK                         0x20u
-#define SPI_S_SPTEF_SHIFT                        5
-#define SPI_S_SPMF_MASK                          0x40u
-#define SPI_S_SPMF_SHIFT                         6
-#define SPI_S_SPRF_MASK                          0x80u
-#define SPI_S_SPRF_SHIFT                         7
-/* D Bit Fields */
-#define SPI_D_Bits_MASK                          0xFFu
-#define SPI_D_Bits_SHIFT                         0
-#define SPI_D_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
-/* M Bit Fields */
-#define SPI_M_Bits_MASK                          0xFFu
-#define SPI_M_Bits_SHIFT                         0
-#define SPI_M_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+/* ML Bit Fields */
+#define SPI_ML_Bits_MASK                         0xFFu
+#define SPI_ML_Bits_SHIFT                        0
+#define SPI_ML_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
+/* MH Bit Fields */
+#define SPI_MH_Bits_MASK                         0xFFu
+#define SPI_MH_Bits_SHIFT                        0
+#define SPI_MH_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
+/* DL Bit Fields */
+#define SPI_DL_Bits_MASK                         0xFFu
+#define SPI_DL_Bits_SHIFT                        0
+#define SPI_DL_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
+/* DH Bit Fields */
+#define SPI_DH_Bits_MASK                         0xFFu
+#define SPI_DH_Bits_SHIFT                        0
+#define SPI_DH_Bits(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
+/* CI Bit Fields */
+#define SPI_CI_SPRFCI_MASK                       0x1u
+#define SPI_CI_SPRFCI_SHIFT                      0
+#define SPI_CI_SPTEFCI_MASK                      0x2u
+#define SPI_CI_SPTEFCI_SHIFT                     1
+#define SPI_CI_RNFULLFCI_MASK                    0x4u
+#define SPI_CI_RNFULLFCI_SHIFT                   2
+#define SPI_CI_TNEAREFCI_MASK                    0x8u
+#define SPI_CI_TNEAREFCI_SHIFT                   3
+#define SPI_CI_RXFOF_MASK                        0x10u
+#define SPI_CI_RXFOF_SHIFT                       4
+#define SPI_CI_TXFOF_MASK                        0x20u
+#define SPI_CI_TXFOF_SHIFT                       5
+#define SPI_CI_RXFERR_MASK                       0x40u
+#define SPI_CI_RXFERR_SHIFT                      6
+#define SPI_CI_TXFERR_MASK                       0x80u
+#define SPI_CI_TXFERR_SHIFT                      7
+/* C3 Bit Fields */
+#define SPI_C3_FIFOMODE_MASK                     0x1u
+#define SPI_C3_FIFOMODE_SHIFT                    0
+#define SPI_C3_RNFULLIEN_MASK                    0x2u
+#define SPI_C3_RNFULLIEN_SHIFT                   1
+#define SPI_C3_TNEARIEN_MASK                     0x4u
+#define SPI_C3_TNEARIEN_SHIFT                    2
+#define SPI_C3_INTCLR_MASK                       0x8u
+#define SPI_C3_INTCLR_SHIFT                      3
+#define SPI_C3_RNFULLF_MARK_MASK                 0x10u
+#define SPI_C3_RNFULLF_MARK_SHIFT                4
+#define SPI_C3_TNEAREF_MARK_MASK                 0x20u
+#define SPI_C3_TNEAREF_MARK_SHIFT                5
 
 /**
  * @}
@@ -3557,14 +5198,8 @@ typedef struct {
 #define UART_D_R7T7_MASK                         0x80u
 #define UART_D_R7T7_SHIFT                        7
 /* C4 Bit Fields */
-#define UART_C4_LBKDDMAS_MASK                    0x8u
-#define UART_C4_LBKDDMAS_SHIFT                   3
-#define UART_C4_ILDMAS_MASK                      0x10u
-#define UART_C4_ILDMAS_SHIFT                     4
 #define UART_C4_RDMAS_MASK                       0x20u
 #define UART_C4_RDMAS_SHIFT                      5
-#define UART_C4_TCDMAS_MASK                      0x40u
-#define UART_C4_TCDMAS_SHIFT                     6
 #define UART_C4_TDMAS_MASK                       0x80u
 #define UART_C4_TDMAS_SHIFT                      7
 
@@ -3591,15 +5226,15 @@ typedef struct {
 
 
 /* ----------------------------------------------------------------------------
-   -- UARTLP Peripheral Access Layer
+   -- UART0 Peripheral Access Layer
    ---------------------------------------------------------------------------- */
 
 /**
- * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
+ * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
  * @{
  */
 
-/** UARTLP - Register Layout Typedef */
+/** UART0 - Register Layout Typedef */
 typedef struct {
   __IO uint8_t BDH;                                /**< UART Baud Rate Register High, offset: 0x0 */
   __IO uint8_t BDL;                                /**< UART Baud Rate Register Low, offset: 0x1 */
@@ -3613,177 +5248,177 @@ typedef struct {
   __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
   __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
   __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
-} UARTLP_Type;
+} UART0_Type;
 
 /* ----------------------------------------------------------------------------
-   -- UARTLP Register Masks
+   -- UART0 Register Masks
    ---------------------------------------------------------------------------- */
 
 /**
- * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
+ * @addtogroup UART0_Register_Masks UART0 Register Masks
  * @{
  */
 
 /* BDH Bit Fields */
-#define UARTLP_BDH_SBR_MASK                      0x1Fu
-#define UARTLP_BDH_SBR_SHIFT                     0
-#define UARTLP_BDH_SBR(x)                        (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
-#define UARTLP_BDH_SBNS_MASK                     0x20u
-#define UARTLP_BDH_SBNS_SHIFT                    5
-#define UARTLP_BDH_RXEDGIE_MASK                  0x40u
-#define UARTLP_BDH_RXEDGIE_SHIFT                 6
-#define UARTLP_BDH_LBKDIE_MASK                   0x80u
-#define UARTLP_BDH_LBKDIE_SHIFT                  7
+#define UART0_BDH_SBR_MASK                       0x1Fu
+#define UART0_BDH_SBR_SHIFT                      0
+#define UART0_BDH_SBR(x)                         (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
+#define UART0_BDH_SBNS_MASK                      0x20u
+#define UART0_BDH_SBNS_SHIFT                     5
+#define UART0_BDH_RXEDGIE_MASK                   0x40u
+#define UART0_BDH_RXEDGIE_SHIFT                  6
+#define UART0_BDH_LBKDIE_MASK                    0x80u
+#define UART0_BDH_LBKDIE_SHIFT                   7
 /* BDL Bit Fields */
-#define UARTLP_BDL_SBR_MASK                      0xFFu
-#define UARTLP_BDL_SBR_SHIFT                     0
-#define UARTLP_BDL_SBR(x)                        (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
+#define UART0_BDL_SBR_MASK                       0xFFu
+#define UART0_BDL_SBR_SHIFT                      0
+#define UART0_BDL_SBR(x)                         (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
 /* C1 Bit Fields */
-#define UARTLP_C1_PT_MASK                        0x1u
-#define UARTLP_C1_PT_SHIFT                       0
-#define UARTLP_C1_PE_MASK                        0x2u
-#define UARTLP_C1_PE_SHIFT                       1
-#define UARTLP_C1_ILT_MASK                       0x4u
-#define UARTLP_C1_ILT_SHIFT                      2
-#define UARTLP_C1_WAKE_MASK                      0x8u
-#define UARTLP_C1_WAKE_SHIFT                     3
-#define UARTLP_C1_M_MASK                         0x10u
-#define UARTLP_C1_M_SHIFT                        4
-#define UARTLP_C1_RSRC_MASK                      0x20u
-#define UARTLP_C1_RSRC_SHIFT                     5
-#define UARTLP_C1_DOZEEN_MASK                    0x40u
-#define UARTLP_C1_DOZEEN_SHIFT                   6
-#define UARTLP_C1_LOOPS_MASK                     0x80u
-#define UARTLP_C1_LOOPS_SHIFT                    7
+#define UART0_C1_PT_MASK                         0x1u
+#define UART0_C1_PT_SHIFT                        0
+#define UART0_C1_PE_MASK                         0x2u
+#define UART0_C1_PE_SHIFT                        1
+#define UART0_C1_ILT_MASK                        0x4u
+#define UART0_C1_ILT_SHIFT                       2
+#define UART0_C1_WAKE_MASK                       0x8u
+#define UART0_C1_WAKE_SHIFT                      3
+#define UART0_C1_M_MASK                          0x10u
+#define UART0_C1_M_SHIFT                         4
+#define UART0_C1_RSRC_MASK                       0x20u
+#define UART0_C1_RSRC_SHIFT                      5
+#define UART0_C1_DOZEEN_MASK                     0x40u
+#define UART0_C1_DOZEEN_SHIFT                    6
+#define UART0_C1_LOOPS_MASK                      0x80u
+#define UART0_C1_LOOPS_SHIFT                     7
 /* C2 Bit Fields */
-#define UARTLP_C2_SBK_MASK                       0x1u
-#define UARTLP_C2_SBK_SHIFT                      0
-#define UARTLP_C2_RWU_MASK                       0x2u
-#define UARTLP_C2_RWU_SHIFT                      1
-#define UARTLP_C2_RE_MASK                        0x4u
-#define UARTLP_C2_RE_SHIFT                       2
-#define UARTLP_C2_TE_MASK                        0x8u
-#define UARTLP_C2_TE_SHIFT                       3
-#define UARTLP_C2_ILIE_MASK                      0x10u
-#define UARTLP_C2_ILIE_SHIFT                     4
-#define UARTLP_C2_RIE_MASK                       0x20u
-#define UARTLP_C2_RIE_SHIFT                      5
-#define UARTLP_C2_TCIE_MASK                      0x40u
-#define UARTLP_C2_TCIE_SHIFT                     6
-#define UARTLP_C2_TIE_MASK                       0x80u
-#define UARTLP_C2_TIE_SHIFT                      7
+#define UART0_C2_SBK_MASK                        0x1u
+#define UART0_C2_SBK_SHIFT                       0
+#define UART0_C2_RWU_MASK                        0x2u
+#define UART0_C2_RWU_SHIFT                       1
+#define UART0_C2_RE_MASK                         0x4u
+#define UART0_C2_RE_SHIFT                        2
+#define UART0_C2_TE_MASK                         0x8u
+#define UART0_C2_TE_SHIFT                        3
+#define UART0_C2_ILIE_MASK                       0x10u
+#define UART0_C2_ILIE_SHIFT                      4
+#define UART0_C2_RIE_MASK                        0x20u
+#define UART0_C2_RIE_SHIFT                       5
+#define UART0_C2_TCIE_MASK                       0x40u
+#define UART0_C2_TCIE_SHIFT                      6
+#define UART0_C2_TIE_MASK                        0x80u
+#define UART0_C2_TIE_SHIFT                       7
 /* S1 Bit Fields */
-#define UARTLP_S1_PF_MASK                        0x1u
-#define UARTLP_S1_PF_SHIFT                       0
-#define UARTLP_S1_FE_MASK                        0x2u
-#define UARTLP_S1_FE_SHIFT                       1
-#define UARTLP_S1_NF_MASK                        0x4u
-#define UARTLP_S1_NF_SHIFT                       2
-#define UARTLP_S1_OR_MASK                        0x8u
-#define UARTLP_S1_OR_SHIFT                       3
-#define UARTLP_S1_IDLE_MASK                      0x10u
-#define UARTLP_S1_IDLE_SHIFT                     4
-#define UARTLP_S1_RDRF_MASK                      0x20u
-#define UARTLP_S1_RDRF_SHIFT                     5
-#define UARTLP_S1_TC_MASK                        0x40u
-#define UARTLP_S1_TC_SHIFT                       6
-#define UARTLP_S1_TDRE_MASK                      0x80u
-#define UARTLP_S1_TDRE_SHIFT                     7
+#define UART0_S1_PF_MASK                         0x1u
+#define UART0_S1_PF_SHIFT                        0
+#define UART0_S1_FE_MASK                         0x2u
+#define UART0_S1_FE_SHIFT                        1
+#define UART0_S1_NF_MASK                         0x4u
+#define UART0_S1_NF_SHIFT                        2
+#define UART0_S1_OR_MASK                         0x8u
+#define UART0_S1_OR_SHIFT                        3
+#define UART0_S1_IDLE_MASK                       0x10u
+#define UART0_S1_IDLE_SHIFT                      4
+#define UART0_S1_RDRF_MASK                       0x20u
+#define UART0_S1_RDRF_SHIFT                      5
+#define UART0_S1_TC_MASK                         0x40u
+#define UART0_S1_TC_SHIFT                        6
+#define UART0_S1_TDRE_MASK                       0x80u
+#define UART0_S1_TDRE_SHIFT                      7
 /* S2 Bit Fields */
-#define UARTLP_S2_RAF_MASK                       0x1u
-#define UARTLP_S2_RAF_SHIFT                      0
-#define UARTLP_S2_LBKDE_MASK                     0x2u
-#define UARTLP_S2_LBKDE_SHIFT                    1
-#define UARTLP_S2_BRK13_MASK                     0x4u
-#define UARTLP_S2_BRK13_SHIFT                    2
-#define UARTLP_S2_RWUID_MASK                     0x8u
-#define UARTLP_S2_RWUID_SHIFT                    3
-#define UARTLP_S2_RXINV_MASK                     0x10u
-#define UARTLP_S2_RXINV_SHIFT                    4
-#define UARTLP_S2_MSBF_MASK                      0x20u
-#define UARTLP_S2_MSBF_SHIFT                     5
-#define UARTLP_S2_RXEDGIF_MASK                   0x40u
-#define UARTLP_S2_RXEDGIF_SHIFT                  6
-#define UARTLP_S2_LBKDIF_MASK                    0x80u
-#define UARTLP_S2_LBKDIF_SHIFT                   7
+#define UART0_S2_RAF_MASK                        0x1u
+#define UART0_S2_RAF_SHIFT                       0
+#define UART0_S2_LBKDE_MASK                      0x2u
+#define UART0_S2_LBKDE_SHIFT                     1
+#define UART0_S2_BRK13_MASK                      0x4u
+#define UART0_S2_BRK13_SHIFT                     2
+#define UART0_S2_RWUID_MASK                      0x8u
+#define UART0_S2_RWUID_SHIFT                     3
+#define UART0_S2_RXINV_MASK                      0x10u
+#define UART0_S2_RXINV_SHIFT                     4
+#define UART0_S2_MSBF_MASK                       0x20u
+#define UART0_S2_MSBF_SHIFT                      5
+#define UART0_S2_RXEDGIF_MASK                    0x40u
+#define UART0_S2_RXEDGIF_SHIFT                   6
+#define UART0_S2_LBKDIF_MASK                     0x80u
+#define UART0_S2_LBKDIF_SHIFT                    7
 /* C3 Bit Fields */
-#define UARTLP_C3_PEIE_MASK                      0x1u
-#define UARTLP_C3_PEIE_SHIFT                     0
-#define UARTLP_C3_FEIE_MASK                      0x2u
-#define UARTLP_C3_FEIE_SHIFT                     1
-#define UARTLP_C3_NEIE_MASK                      0x4u
-#define UARTLP_C3_NEIE_SHIFT                     2
-#define UARTLP_C3_ORIE_MASK                      0x8u
-#define UARTLP_C3_ORIE_SHIFT                     3
-#define UARTLP_C3_TXINV_MASK                     0x10u
-#define UARTLP_C3_TXINV_SHIFT                    4
-#define UARTLP_C3_TXDIR_MASK                     0x20u
-#define UARTLP_C3_TXDIR_SHIFT                    5
-#define UARTLP_C3_R9T8_MASK                      0x40u
-#define UARTLP_C3_R9T8_SHIFT                     6
-#define UARTLP_C3_R8T9_MASK                      0x80u
-#define UARTLP_C3_R8T9_SHIFT                     7
+#define UART0_C3_PEIE_MASK                       0x1u
+#define UART0_C3_PEIE_SHIFT                      0
+#define UART0_C3_FEIE_MASK                       0x2u
+#define UART0_C3_FEIE_SHIFT                      1
+#define UART0_C3_NEIE_MASK                       0x4u
+#define UART0_C3_NEIE_SHIFT                      2
+#define UART0_C3_ORIE_MASK                       0x8u
+#define UART0_C3_ORIE_SHIFT                      3
+#define UART0_C3_TXINV_MASK                      0x10u
+#define UART0_C3_TXINV_SHIFT                     4
+#define UART0_C3_TXDIR_MASK                      0x20u
+#define UART0_C3_TXDIR_SHIFT                     5
+#define UART0_C3_R9T8_MASK                       0x40u
+#define UART0_C3_R9T8_SHIFT                      6
+#define UART0_C3_R8T9_MASK                       0x80u
+#define UART0_C3_R8T9_SHIFT                      7
 /* D Bit Fields */
-#define UARTLP_D_R0T0_MASK                       0x1u
-#define UARTLP_D_R0T0_SHIFT                      0
-#define UARTLP_D_R1T1_MASK                       0x2u
-#define UARTLP_D_R1T1_SHIFT                      1
-#define UARTLP_D_R2T2_MASK                       0x4u
-#define UARTLP_D_R2T2_SHIFT                      2
-#define UARTLP_D_R3T3_MASK                       0x8u
-#define UARTLP_D_R3T3_SHIFT                      3
-#define UARTLP_D_R4T4_MASK                       0x10u
-#define UARTLP_D_R4T4_SHIFT                      4
-#define UARTLP_D_R5T5_MASK                       0x20u
-#define UARTLP_D_R5T5_SHIFT                      5
-#define UARTLP_D_R6T6_MASK                       0x40u
-#define UARTLP_D_R6T6_SHIFT                      6
-#define UARTLP_D_R7T7_MASK                       0x80u
-#define UARTLP_D_R7T7_SHIFT                      7
+#define UART0_D_R0T0_MASK                        0x1u
+#define UART0_D_R0T0_SHIFT                       0
+#define UART0_D_R1T1_MASK                        0x2u
+#define UART0_D_R1T1_SHIFT                       1
+#define UART0_D_R2T2_MASK                        0x4u
+#define UART0_D_R2T2_SHIFT                       2
+#define UART0_D_R3T3_MASK                        0x8u
+#define UART0_D_R3T3_SHIFT                       3
+#define UART0_D_R4T4_MASK                        0x10u
+#define UART0_D_R4T4_SHIFT                       4
+#define UART0_D_R5T5_MASK                        0x20u
+#define UART0_D_R5T5_SHIFT                       5
+#define UART0_D_R6T6_MASK                        0x40u
+#define UART0_D_R6T6_SHIFT                       6
+#define UART0_D_R7T7_MASK                        0x80u
+#define UART0_D_R7T7_SHIFT                       7
 /* MA1 Bit Fields */
-#define UARTLP_MA1_MA_MASK                       0xFFu
-#define UARTLP_MA1_MA_SHIFT                      0
-#define UARTLP_MA1_MA(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
+#define UART0_MA1_MA_MASK                        0xFFu
+#define UART0_MA1_MA_SHIFT                       0
+#define UART0_MA1_MA(x)                          (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
 /* MA2 Bit Fields */
-#define UARTLP_MA2_MA_MASK                       0xFFu
-#define UARTLP_MA2_MA_SHIFT                      0
-#define UARTLP_MA2_MA(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
+#define UART0_MA2_MA_MASK                        0xFFu
+#define UART0_MA2_MA_SHIFT                       0
+#define UART0_MA2_MA(x)                          (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
 /* C4 Bit Fields */
-#define UARTLP_C4_OSR_MASK                       0x1Fu
-#define UARTLP_C4_OSR_SHIFT                      0
-#define UARTLP_C4_OSR(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
-#define UARTLP_C4_M10_MASK                       0x20u
-#define UARTLP_C4_M10_SHIFT                      5
-#define UARTLP_C4_MAEN2_MASK                     0x40u
-#define UARTLP_C4_MAEN2_SHIFT                    6
-#define UARTLP_C4_MAEN1_MASK                     0x80u
-#define UARTLP_C4_MAEN1_SHIFT                    7
+#define UART0_C4_OSR_MASK                        0x1Fu
+#define UART0_C4_OSR_SHIFT                       0
+#define UART0_C4_OSR(x)                          (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
+#define UART0_C4_M10_MASK                        0x20u
+#define UART0_C4_M10_SHIFT                       5
+#define UART0_C4_MAEN2_MASK                      0x40u
+#define UART0_C4_MAEN2_SHIFT                     6
+#define UART0_C4_MAEN1_MASK                      0x80u
+#define UART0_C4_MAEN1_SHIFT                     7
 /* C5 Bit Fields */
-#define UARTLP_C5_RESYNCDIS_MASK                 0x1u
-#define UARTLP_C5_RESYNCDIS_SHIFT                0
-#define UARTLP_C5_BOTHEDGE_MASK                  0x2u
-#define UARTLP_C5_BOTHEDGE_SHIFT                 1
-#define UARTLP_C5_RDMAE_MASK                     0x20u
-#define UARTLP_C5_RDMAE_SHIFT                    5
-#define UARTLP_C5_TDMAE_MASK                     0x80u
-#define UARTLP_C5_TDMAE_SHIFT                    7
+#define UART0_C5_RESYNCDIS_MASK                  0x1u
+#define UART0_C5_RESYNCDIS_SHIFT                 0
+#define UART0_C5_BOTHEDGE_MASK                   0x2u
+#define UART0_C5_BOTHEDGE_SHIFT                  1
+#define UART0_C5_RDMAE_MASK                      0x20u
+#define UART0_C5_RDMAE_SHIFT                     5
+#define UART0_C5_TDMAE_MASK                      0x80u
+#define UART0_C5_TDMAE_SHIFT                     7
 
 /**
  * @}
- */ /* end of group UARTLP_Register_Masks */
+ */ /* end of group UART0_Register_Masks */
 
 
-/* UARTLP - Peripheral instance base addresses */
+/* UART0 - Peripheral instance base addresses */
 /** Peripheral UART0 base address */
 #define UART0_BASE                               (0x4006A000u)
 /** Peripheral UART0 base pointer */
-#define UART0                                    ((UARTLP_Type *)UART0_BASE)
-/** Array initializer of UARTLP peripheral base pointers */
-#define UARTLP_BASES                             { UART0 }
+#define UART0                                    ((UART0_Type *)UART0_BASE)
+/** Array initializer of UART0 peripheral base pointers */
+#define UART0_BASES                              { UART0 }
 
 /**
  * @}
- */ /* end of group UARTLP_Peripheral_Access_Layer */
+ */ /* end of group UART0_Peripheral_Access_Layer */
 
 
 /* ----------------------------------------------------------------------------
@@ -3852,6 +5487,8 @@ typedef struct {
   __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
        uint8_t RESERVED_24[3];
   __IO uint8_t USBTRC0;                            /**< USB Transceiver Control Register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
 } USB_Type;
 
 /* ----------------------------------------------------------------------------
@@ -4094,6 +5731,10 @@ typedef struct {
 #define USB_USBTRC0_USBRESMEN_SHIFT              5
 #define USB_USBTRC0_USBRESET_MASK                0x80u
 #define USB_USBTRC0_USBRESET_SHIFT               7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
 
 /**
  * @}
diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c
index 0a3298c69b4..8a15912ac9b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c
+++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.c
@@ -1,37 +1,43 @@
 /*
 ** ###################################################################
-**     Processor:           MKL46Z128VLK4
+**     Processors:          MKL46Z256VLH4
+**                          MKL46Z128VLH4
+**                          MKL46Z256VLL4
+**                          MKL46Z128VLL4
+**                          MKL46Z256VMC4
+**                          MKL46Z128VMC4
+**
 **     Compilers:           ARM Compiler
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
 **
-**     Reference manual:    KL25RM, Rev.1, Jun 2012
-**     Version:             rev. 1.1, 2012-06-21
+**     Reference manual:    KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+**     Version:             rev. 2.0, 2012-12-12
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**     Copyright: 2012 Freescale, Inc. All Rights Reserved.
 **
 **     http:                 www.freescale.com
 **     mail:                 support@freescale.com
 **
 **     Revisions:
-**     - rev. 1.0 (2012-06-13)
+**     - rev. 1.0 (2012-10-16)
 **         Initial version.
-**     - rev. 1.1 (2012-06-21)
-**         Update according to reference manual rev. 1.
+**     - rev. 2.0 (2012-12-12)
+**         Update to reference manual rev. 1.
 **
 ** ###################################################################
 */
 
 /**
  * @file MKL46Z4
- * @version 1.1
- * @date 2012-06-21
+ * @version 2.0
+ * @date 2012-12-12
  * @brief Device specific configuration file for MKL46Z4 (implementation file)
  *
  * Provides a system configuration function and a global variable that contains
@@ -100,8 +106,8 @@ void SystemInit (void) {
   /* Switch to FEI Mode */
   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
   MCG->C1 = (uint8_t)0x06U;
-  /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x00U;
+  /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
   /* MCG->C4: DMX32=0,DRST_DRS=1 */
   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
@@ -124,11 +130,11 @@ void SystemInit (void) {
   /* PORTA->PCR19: ISF=0,MUX=0 */
   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
   /* Switch to FBE Mode */
-  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
-  OSC0->CR = (uint8_t)0x89U;
-  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x24U;
-  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
+  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
+  /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
   MCG->C1 = (uint8_t)0x9AU;
   /* MCG->C4: DMX32=0,DRST_DRS=0 */
   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
@@ -162,10 +168,10 @@ void SystemInit (void) {
   /* PORTA->PCR19: ISF=0,MUX=0 */
   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
   /* Switch to FBE Mode */
-  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
-  OSC0->CR = (uint8_t)0x89U;
   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
   MCG->C2 = (uint8_t)0x24U;
+  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
   MCG->C1 = (uint8_t)0x9AU;
   /* MCG->C4: DMX32=0,DRST_DRS=0 */
@@ -179,8 +185,8 @@ void SystemInit (void) {
   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
   }
   /* Switch to BLPE Mode */
-  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
-  MCG->C2 = (uint8_t)0x26U;
+  /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
+  MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
   }
 #endif /* (CLOCK_SETUP == 2) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.h
index 1f4d8ab644f..e88304711a9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/system_MKL46Z4.h
@@ -1,37 +1,43 @@
 /*
 ** ###################################################################
-**     Processor:           MKL46Z128VLK4
+**     Processors:          MKL46Z256VLH4
+**                          MKL46Z128VLH4
+**                          MKL46Z256VLL4
+**                          MKL46Z128VLL4
+**                          MKL46Z256VMC4
+**                          MKL46Z128VMC4
+**
 **     Compilers:           ARM Compiler
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
 **
-**     Reference manual:    KL25RM, Rev.1, Jun 2012
-**     Version:             rev. 1.1, 2012-06-21
+**     Reference manual:    KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+**     Version:             rev. 2.0, 2012-12-12
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**     Copyright: 2012 Freescale, Inc. All Rights Reserved.
 **
 **     http:                 www.freescale.com
 **     mail:                 support@freescale.com
 **
 **     Revisions:
-**     - rev. 1.0 (2012-06-13)
+**     - rev. 1.0 (2012-10-16)
 **         Initial version.
-**     - rev. 1.1 (2012-06-21)
-**         Update according to reference manual rev. 1.
+**     - rev. 2.0 (2012-12-12)
+**         Update to reference manual rev. 1.
 **
 ** ###################################################################
 */
 
 /**
  * @file MKL46Z4
- * @version 1.1
- * @date 2012-06-21
+ * @version 2.0
+ * @date 2012-12-12
  * @brief Device specific configuration file for MKL46Z4 (header file)
  *
  * Provides a system configuration function and a global variable that contains
diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/objects.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/objects.h
index a5366deaedc..8178967acb3 100644
--- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/objects.h
+++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/objects.h
@@ -46,7 +46,7 @@ struct pwmout_s {
 };
 
 struct serial_s {
-    UARTLP_Type *uart;
+    UART0_Type *uart;
     int index;
 };
 
diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c
index 3414e47ee3d..f978799de24 100644
--- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c
+++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/serial_api.c
@@ -71,7 +71,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
         error("Serial pinout mapping failed");
     }
 
-    obj->uart = (UARTLP_Type *)uart;
+    obj->uart = (UART0_Type *)uart;
     // enable clk
     switch (uart) {
         case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT2_UART0SRC_SHIFT);
@@ -200,8 +200,8 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
 
     // enable 10bit mode if needed
     if (obj->index == 0) {
-        obj->uart->C4 &= ~UARTLP_C4_M10_MASK;
-        obj->uart->C4 |= (m10 << UARTLP_C4_M10_SHIFT);
+        obj->uart->C4 &= ~UART0_C4_M10_MASK;
+        obj->uart->C4 |= (m10 << UART0_C4_M10_SHIFT);
     }
 
     // stop bits
diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/spi_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/spi_api.c
index e76c5aa1371..c717768b0d9 100644
--- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/spi_api.c
+++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KL46Z/spi_api.c
@@ -96,7 +96,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
 
     // enable power and clocking
     switch ((int)obj->spi) {
-        case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
+        case SPI_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 22; break;
         case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
     }
 
@@ -110,6 +110,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
 
     // enable SPI
     obj->spi->C1 |= SPI_C1_SPE_MASK;
+    obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit
 
     // pin out the spi pins
     pinmap_pinout(mosi, PinMap_SPI_MOSI);
@@ -124,8 +125,8 @@ void spi_free(spi_t *obj) {
     // [TODO]
 }
 void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    if (bits != 8) {
-        error("Only 8bits SPI supported");
+    if ((bits != 8) && (bits != 16)) {
+        error("Only 8/16 bits SPI supported");
     }
 
     if ((mode < 0) || (mode > 3)) {
@@ -141,6 +142,11 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
 
     // write new value
     obj->spi->C1 |= c1_data;
+    if (bits == 8) {
+        obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK;
+    } else {
+        obj->spi->C2 |= SPI_C2_SPIMODE_MASK;
+    }
 }
 
 void spi_frequency(spi_t *obj, int hz) {
@@ -184,13 +190,28 @@ static inline int spi_readable(spi_t * obj) {
 }
 
 int spi_master_write(spi_t *obj, int value) {
-    // wait tx buffer empty
-    while(!spi_writeable(obj));
-    obj->spi->D = (value & 0xff);
+    int ret;
+    if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
+        // 16bit
+        while(!spi_writeable(obj));
+        obj->spi->DL = (value & 0xff);
+        obj->spi->DH = ((value >> 8) & 0xff);
+
+        // wait rx buffer full
+        while (!spi_readable(obj));
+        ret = obj->spi->DH;
+        ret = (ret << 8) | obj->spi->DL;
+    } else {
+        //8bit
+        while(!spi_writeable(obj));
+        obj->spi->DL = (value & 0xff);
+
+        // wait rx buffer full
+        while (!spi_readable(obj));
+        ret = (obj->spi->DL & 0xff);
+    }
 
-    // wait rx buffer full
-    while (!spi_readable(obj));
-    return obj->spi->D & 0xff;
+    return ret;
 }
 
 int spi_slave_receive(spi_t *obj) {
@@ -198,10 +219,23 @@ int spi_slave_receive(spi_t *obj) {
 }
 
 int spi_slave_read(spi_t *obj) {
-    return obj->spi->D;
+    int ret;
+    if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
+        ret = obj->spi->DH;
+        ret = ((ret << 8) | obj->spi->DL);
+    } else {
+        ret = obj->spi->DL;
+    }
+    return ret;
 }
 
 void spi_slave_write(spi_t *obj, int value) {
     while (!spi_writeable(obj));
-    obj->spi->D = value;
+    if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
+        obj->spi->DL = (value & 0xff);
+        obj->spi->DH = ((value >> 8) & 0xff);
+    } else {
+        obj->spi->DL = value;
+    }
+
 }