diff --git a/.astyleignore b/.astyleignore index 85d2551aa22..a07fa426189 100644 --- a/.astyleignore +++ b/.astyleignore @@ -1,6 +1,7 @@ ^BUILD ^cmsis ^components/802.15.4_RF +^components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca ^components/TARGET_PSA/services/attestation/attestation.h ^components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl ^components/TARGET_PSA/services/attestation/qcbor diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/QCA400XInterface.cpp b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400XInterface.cpp new file mode 100644 index 00000000000..5d1f2ca8c74 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400XInterface.cpp @@ -0,0 +1,668 @@ +/* QCA4002/4004 implementation of NetworkInterfaceAPI + * Copyright (c) 2019 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "QCA400XInterface.h" +#include "events/EventQueue.h" +#include "events/mbed_shared_queues.h" +#include "features/netsocket/nsapi_types.h" +#include "mbed_trace.h" +#include "platform/Callback.h" +#include "platform/mbed_critical.h" +#include "platform/mbed_debug.h" +#include "platform/mbed_wait_api.h" +#include "platform/mbed_error.h" + +#define TRACE_GROUP "QCAI" // QCA400X Interface + +#define QCA400X_WIFI_IF_NAME "qca0" + +using namespace mbed; +using namespace rtos; + +QCA400XInterface::QCA400XInterface(): + _connect_retval(NSAPI_ERROR_OK), + _ap_sec(NSAPI_SECURITY_NONE), + _channel_num(1), + _if_blocking(true), + _if_connected(_cmutex), + _conn_stat(NSAPI_STATUS_DISCONNECTED), + _conn_stat_cb(NULL), + _global_event_queue(mbed_event_queue()), // Needs to be set before attaching event() to SIGIO + _connect_event_id(0) +{ + memset(_ssid, 0, sizeof(_ssid)); + memset(ap_pass, 0, sizeof(ap_pass)); + + _qca400x.sigio(this, &QCA400XInterface::event); + _qca400x.attach(this, &QCA400XInterface::refresh_conn_state_cb); + + for (int i = 0; i < QCA400X_SOCKET_COUNT; i++) { + _sock_i[i].open = false; + _sock_i[i].sport = 0; + } +} + +QCA400XInterface::~QCA400XInterface() +{ + _cmutex.lock(); + if (_connect_event_id) { + _global_event_queue->cancel(_connect_event_id); + } + _cmutex.unlock(); +} + +int QCA400XInterface::connect(const char *ssid, const char *pass, + nsapi_security_t security, uint8_t channel) +{ + nsapi_error_t ret_code; + + ret_code = set_credentials(ssid, pass, security); + if (ret_code) { + return ret_code; + } + + _channel_num = channel; + + return connect(); +} + +void QCA400XInterface::_connect_async() +{ + _cmutex.lock(); + if (!_connect_event_id) { + _cmutex.unlock(); + return; + } + + _connect_retval = _qca400x.connect(_ssid, ap_pass, _ap_sec, _channel_num); + + _if_connected.notify_all(); + + _connect_event_id = 0; + + _cmutex.unlock(); +} + +int QCA400XInterface::connect() +{ + nsapi_error_t status = _conn_status_to_error(); + if (status != NSAPI_ERROR_NO_CONNECTION) { + return status; + } + + if (strlen(_ssid) == 0) { + return NSAPI_ERROR_NO_SSID; + } + + if (_ap_sec != NSAPI_SECURITY_NONE) { + if (strlen(ap_pass) < QCA400X_PASSPHRASE_MIN_LENGTH) { + return NSAPI_ERROR_PARAMETER; + } + } + + status = _qca400x.initialize(); + if (status != NSAPI_ERROR_OK) { + return status; + } + + _cmutex.lock(); + + _connect_retval = NSAPI_ERROR_NO_CONNECTION; + MBED_ASSERT(!_connect_event_id); + + _connect_event_id = _global_event_queue->call(callback(this, &QCA400XInterface::_connect_async)); + + if (!_connect_event_id) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_ENOMEM), \ + "connect(): unable to add event to queue. Increase \"events.shared-eventsize\"\n"); + } + + while (_if_blocking && (_conn_status_to_error() != NSAPI_ERROR_IS_CONNECTED) + && (_connect_retval == NSAPI_ERROR_NO_CONNECTION)) { + _if_connected.wait(); + } + + _cmutex.unlock(); + + if (!_if_blocking) { + return NSAPI_ERROR_OK; + } else { + return _connect_retval; + } +} + +int QCA400XInterface::set_credentials(const char *ssid, const char *pass, + nsapi_security_t security) +{ + nsapi_error_t status = _conn_status_to_error(); + if (status != NSAPI_ERROR_NO_CONNECTION) { + return NSAPI_ERROR_NO_CONNECTION; + } + + _ap_sec = security; + + if (!ssid) { + return NSAPI_ERROR_PARAMETER; + } + + int ssid_length = strlen(ssid); + + if (ssid_length > 0 && ssid_length <= QCA400X_SSID_MAX_LENGTH) { + memset(_ssid, 0, sizeof(_ssid)); + strncpy(_ssid, ssid, sizeof(_ssid)); + } else { + return NSAPI_ERROR_PARAMETER; + } + + if (_ap_sec != NSAPI_SECURITY_NONE) { + + if (!pass) { + return NSAPI_ERROR_PARAMETER; + } + + int pass_length = strlen(pass); + if (pass_length >= QCA400X_PASSPHRASE_MIN_LENGTH + && pass_length <= QCA400X_PASSPHRASE_MAX_LENGTH) { + memset(ap_pass, 0, sizeof(ap_pass)); + strncpy(ap_pass, pass, sizeof(ap_pass)); + } else { + return NSAPI_ERROR_PARAMETER; + } + } else { + memset(ap_pass, 0, sizeof(ap_pass)); + } + + return NSAPI_ERROR_OK; +} + +int QCA400XInterface::set_channel(uint8_t channel) +{ + return NSAPI_ERROR_UNSUPPORTED; +} + +int QCA400XInterface::disconnect() +{ + _cmutex.lock(); + if (_connect_event_id) { + _global_event_queue->cancel(_connect_event_id); + _connect_event_id = 0; // cancel asynchronous connection attempt if one is ongoing + } + _cmutex.unlock(); + + nsapi_error_t status = _conn_status_to_error(); + if (status == NSAPI_ERROR_NO_CONNECTION) { + return NSAPI_ERROR_NO_CONNECTION; + } + + int ret = _qca400x.disconnect() ? NSAPI_ERROR_OK : NSAPI_ERROR_DEVICE_ERROR; + + return ret; +} + +const char *QCA400XInterface::get_ip_address() +{ + const char *ip_buff = _qca400x.getIPAddress(); + if (!ip_buff || strcmp(ip_buff, "0.0.0.0") == 0) { + return NULL; + } + + return ip_buff; +} + +nsapi_error_t QCA400XInterface::get_ip_address(SocketAddress *address) +{ + const char *ip_buff = _qca400x.getIPAddress(); + if (!ip_buff || strcmp(ip_buff, "0.0.0.0") == 0) { + return NULL; + } + if (ip_buff) { + address->set_ip_address(ip_buff); + return NSAPI_ERROR_OK; + } + return NSAPI_ERROR_NO_ADDRESS; +} + +const char *QCA400XInterface::get_mac_address() +{ + return _qca400x.getMACAddress(); +} + +const char *QCA400XInterface::get_gateway() +{ + return _conn_stat != NSAPI_STATUS_DISCONNECTED ? _qca400x.getGateway() : NULL; +} + +nsapi_error_t QCA400XInterface::get_gateway(SocketAddress *address) +{ + if (address == nullptr) { + return NSAPI_ERROR_PARAMETER; + } + if (_conn_stat == NSAPI_STATUS_DISCONNECTED) { + return NSAPI_ERROR_NO_CONNECTION; + } + + if (!address->set_ip_address(_qca400x.getGateway())) { + return NSAPI_ERROR_NO_ADDRESS; + } + + return NSAPI_ERROR_OK; +} + +const char *QCA400XInterface::get_netmask() +{ + return _conn_stat != NSAPI_STATUS_DISCONNECTED ? _qca400x.getNetmask() : NULL; +} + +nsapi_error_t QCA400XInterface::get_netmask(SocketAddress *address) +{ + if (address == nullptr) { + return NSAPI_ERROR_PARAMETER; + } + if (_conn_stat == NSAPI_STATUS_DISCONNECTED) { + return NSAPI_ERROR_NO_CONNECTION; + } + + if (!address->set_ip_address(_qca400x.getNetmask())) { + return NSAPI_ERROR_NO_ADDRESS; + } + + return NSAPI_ERROR_OK; +} + +char *QCA400XInterface::get_interface_name(char *interface_name) +{ + memcpy(interface_name, QCA400X_WIFI_IF_NAME, sizeof(QCA400X_WIFI_IF_NAME)); + return interface_name; +} + +int8_t QCA400XInterface::get_rssi() +{ + if (_conn_stat == NSAPI_STATUS_DISCONNECTED) { + return 0; + } + + return _qca400x.rssi(); +} + +int QCA400XInterface::scan(WiFiAccessPoint *res, unsigned count) +{ + nsapi_error_t status; + + status = _qca400x.initialize(); + if (status != NSAPI_ERROR_OK) { + return status; + } + + return _qca400x.scan(res, count); +} + +nsapi_error_t QCA400XInterface::socket_open(void **handle, nsapi_protocol_t proto) +{ + // Look for an unused socket + int id = -1; + nsapi_error_t ret; + nsapi_error_t status; + + for (int i = 0; i < QCA400X_SOCKET_COUNT; i++) { + if (!_sock_i[i].open) { + id = i; + _sock_i[i].open = true; + break; + } + } + + if (id == -1) { + return NSAPI_ERROR_NO_SOCKET; + } + + status = _qca400x.initialize(); + if (status != NSAPI_ERROR_OK) { + return status; + } + + ret = _qca400x.open_socket(id, proto); + if (ret != NSAPI_ERROR_OK) { + _sock_i[id].open = false; + return NSAPI_ERROR_NO_SOCKET; + } + + struct qca400x_socket *socket = new struct qca400x_socket; + if (!socket) { + _sock_i[id].open = false; + return NSAPI_ERROR_NO_SOCKET; + } + + socket->id = id; + socket->proto = proto; + socket->connected = false; + *handle = socket; + + return 0; +} + +nsapi_error_t QCA400XInterface::socket_close(void *handle) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + int err = 0; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + if (!_qca400x.close_socket(socket->id)) { + err = NSAPI_ERROR_DEVICE_ERROR; + } + + _cbs[socket->id].callback = NULL; + _cbs[socket->id].data = NULL; + core_util_atomic_store_u8(&_cbs[socket->id].deferred, false); + + socket->connected = false; + _sock_i[socket->id].open = false; + _sock_i[socket->id].sport = 0; + + delete socket; + + return err; +} + +int QCA400XInterface::socket_bind(void *handle, const SocketAddress &address) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + nsapi_error_t ret; + nsapi_addr_t ip_addr; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + if (socket->connected) { + return NSAPI_ERROR_PARAMETER; + } + + if (socket->proto == NSAPI_UDP) { + if (address.get_addr().version != NSAPI_UNSPEC) { + return NSAPI_ERROR_UNSUPPORTED; + } + + for (int id = 0; id < QCA400X_SOCKET_COUNT; id++) { + if (_sock_i[id].sport == address.get_port() && id != socket->id) { // Port already reserved by another socket + return NSAPI_ERROR_PARAMETER; + } + } + + ip_addr = address.get_addr(); + ret = _qca400x.bind_socket(socket->id, ip_addr.bytes, address.get_port()); + if (ret == NSAPI_ERROR_OK) { + _sock_i[socket->id].sport = address.get_port(); + return 0; + } + } + + return NSAPI_ERROR_UNSUPPORTED; +} + +int QCA400XInterface::socket_listen(void *handle, int backlog) +{ + return NSAPI_ERROR_UNSUPPORTED; +} + +int QCA400XInterface::socket_connect(void *handle, const SocketAddress &addr) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + nsapi_error_t ret; + nsapi_addr_t ip_addr; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + ip_addr = addr.get_addr(); + + ret = _qca400x.connect_socket(socket->id, ip_addr.bytes, addr.get_port()); + + socket->connected = (ret == NSAPI_ERROR_OK) ? true : false; + + return ret; + +} + +int QCA400XInterface::socket_accept(void *handle, void **socket, SocketAddress *address) +{ + return NSAPI_ERROR_UNSUPPORTED; +} + +int QCA400XInterface::socket_send(void *handle, const void *data, unsigned size) +{ + nsapi_error_t status; + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + if (!socket->connected) { + return NSAPI_ERROR_CONNECTION_LOST; + } + + if (data == NULL) { + return NSAPI_ERROR_PARAMETER; + } + + status = _qca400x.send(socket->id, data, size); + + return status != NSAPI_ERROR_OK ? status : size; + +} + +int QCA400XInterface::socket_recv(void *handle, void *data, unsigned size) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + if (!_sock_i[socket->id].open) { + return NSAPI_ERROR_CONNECTION_LOST; + } + + int32_t recv; + + recv = _qca400x.recv(socket->id, data, size); + if (recv <= 0 && recv != NSAPI_ERROR_WOULD_BLOCK) { + socket->connected = false; + } + + return recv; +} + +int QCA400XInterface::socket_sendto(void *handle, const SocketAddress &addr, const void *data, unsigned size) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + nsapi_error_t status; + nsapi_addr_t ip_addr; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + if ((strcmp(addr.get_ip_address(), "0.0.0.0") == 0) || !addr.get_port()) { + return NSAPI_ERROR_DNS_FAILURE; + } + + if (data == NULL) { + return NSAPI_ERROR_PARAMETER; + } + + ip_addr = addr.get_addr(); + + status = _qca400x.sendto(socket->id, data, size, ip_addr.bytes, addr.get_port()); + + socket->connected = (status == NSAPI_ERROR_OK) ? true : false; + + return status != NSAPI_ERROR_OK ? status : size; +} + +int QCA400XInterface::socket_recvfrom(void *handle, SocketAddress *addr, void *data, unsigned size) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + int recv = _qca400x.recvfrom(socket, data, size); + if (recv < 0 && recv != NSAPI_ERROR_WOULD_BLOCK) { + socket->connected = false; + } else if (recv >= 0 && addr) { + *addr = socket->addr; + } + + return recv; +} + +void QCA400XInterface::socket_attach(void *handle, void (*attach_callback)(void *), void *data) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + _cbs[socket->id].callback = attach_callback; + _cbs[socket->id].data = data; +} + +nsapi_error_t QCA400XInterface::setsockopt(nsapi_socket_t handle, int level, int optname, + const void *optval, unsigned optlen) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + + if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + return NSAPI_ERROR_UNSUPPORTED; +} + +nsapi_error_t QCA400XInterface::getsockopt(nsapi_socket_t handle, int level, int optname, + void *optval, unsigned *optlen) +{ + struct qca400x_socket *socket = (struct qca400x_socket *)handle; + + if (!optval || !optlen) { + return NSAPI_ERROR_PARAMETER; + } else if (!socket) { + return NSAPI_ERROR_NO_SOCKET; + } + + if (level == NSAPI_SOCKET && socket->proto == NSAPI_TCP) { + if ((optname == NSAPI_KEEPALIVE) || (optname == NSAPI_LINGER)) { + if (*optlen > sizeof(int)) { + *optlen = sizeof(int); + } + return _qca400x.getsockopt(socket->id, optname, optval); + } + } + + return NSAPI_ERROR_UNSUPPORTED; +} + +void QCA400XInterface::event(int sock) +{ + if (_cbs[sock].callback) { + _cbs[sock].callback(_cbs[sock].data); + } +} + +void QCA400XInterface::attach(Callback status_cb) +{ + _conn_stat_cb = status_cb; +} + +nsapi_connection_status_t QCA400XInterface::get_connection_status() const +{ + return _conn_stat; +} + +#if MBED_CONF_QCA400X_PROVIDE_DEFAULT + +WiFiInterface *WiFiInterface::get_default_instance() +{ + static QCA400XInterface wifi; + return &wifi; +} + +#endif + +void QCA400XInterface::refresh_conn_state_cb() +{ + nsapi_connection_status_t prev_stat = _conn_stat; + _conn_stat = _qca400x.connection_status(); + + switch (_conn_stat) { + // Doesn't require changes + case NSAPI_STATUS_CONNECTING: + case NSAPI_STATUS_GLOBAL_UP: + break; + // Start from scratch if connection drops/is dropped + case NSAPI_STATUS_DISCONNECTED: + break; + // Handled on AT layer + case NSAPI_STATUS_LOCAL_UP: + case NSAPI_STATUS_ERROR_UNSUPPORTED: + default: + _conn_stat = NSAPI_STATUS_DISCONNECTED; + for (int i = 0; i < QCA400X_SOCKET_COUNT; i++) { + _sock_i[i].open = false; + _sock_i[i].sport = 0; + } + } + + if (prev_stat == _conn_stat) { + return; + } + + tr_debug("refresh_conn_state_cb(): changed to %d", _conn_stat); + + // Inform upper layers + if (_conn_stat_cb) { + _conn_stat_cb(NSAPI_EVENT_CONNECTION_STATUS_CHANGE, _conn_stat); + } +} + +nsapi_error_t QCA400XInterface::_conn_status_to_error() +{ + nsapi_error_t ret; + + switch (_conn_stat) { + case NSAPI_STATUS_DISCONNECTED: + ret = NSAPI_ERROR_NO_CONNECTION; + break; + case NSAPI_STATUS_CONNECTING: + ret = NSAPI_ERROR_ALREADY; + break; + case NSAPI_STATUS_GLOBAL_UP: + ret = NSAPI_ERROR_IS_CONNECTED; + break; + default: + ret = NSAPI_ERROR_DEVICE_ERROR; + } + + return ret; +} + +nsapi_error_t QCA400XInterface::set_blocking(bool blocking) +{ + return NSAPI_ERROR_UNSUPPORTED; +} + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/QCA400XInterface.h b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400XInterface.h new file mode 100644 index 00000000000..98bf3999a63 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400XInterface.h @@ -0,0 +1,370 @@ +/* QCA4002/4004 implementation of NetworkInterfaceAPI + * Copyright (c) 2019 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef QCA400X_INTERFACE_H +#define QCA400X_INTERFACE_H + +#include "QCA400x.h" +#include "events/EventQueue.h" +#include "events/mbed_shared_queues.h" +#include "features/netsocket/NetworkInterface.h" +#include "features/netsocket/NetworkStack.h" +#include "features/netsocket/nsapi_types.h" +#include "features/netsocket/SocketAddress.h" +#include "features/netsocket/WiFiAccessPoint.h" +#include "features/netsocket/WiFiInterface.h" +#include "platform/Callback.h" +#if MBED_CONF_RTOS_PRESENT +#include "rtos/ConditionVariable.h" +#endif +#include "rtos/Mutex.h" + +#define QCA400X_SOCKET_COUNT 5 + +#define QCA400X_SSID_MAX_LENGTH 32 +#define QCA400X_PASSPHRASE_MAX_LENGTH 63 +#define QCA400X_PASSPHRASE_MIN_LENGTH 8 /* The shortest allowed passphrase */ + +/** QCA400XInterface interface class + * Implementation of the NetworkStack for QCA 4002/4004 + */ +class QCA400XInterface : public NetworkStack, public WiFiInterface { +public: + /** + * @brief QCA400XInterface default constructor + */ + QCA400XInterface(); + + /** + * @brief QCA400XInterface default destructor + */ + virtual ~QCA400XInterface(); + + + /** Start the interface + * + * Attempts to connect to a WiFi network. Requires ssid and passphrase to be set. + * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. + * + * @return 0 on success, negative error code on failure + */ + virtual int connect(); + + /** Start the interface + * + * Attempts to connect to a WiFi network. + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) + * @param channel This parameter is not supported, setting it to anything else than 0 will result in NSAPI_ERROR_UNSUPPORTED + * @return 0 on success, or error code on failure + */ + virtual int connect(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, + uint8_t channel = 0); + + /** Set the WiFi network credentials + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection + * (defaults to NSAPI_SECURITY_NONE) + * @return 0 on success, or error code on failure + */ + virtual int set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); + + /** Set the WiFi network channel - NOT SUPPORTED + * + * This function is not supported and will return NSAPI_ERROR_UNSUPPORTED + * + * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) + * @return Not supported, returns NSAPI_ERROR_UNSUPPORTED + */ + virtual int set_channel(uint8_t channel); + + /** Stop the interface + * @return 0 on success, negative on failure + */ + virtual int disconnect(); + + /** Get the internally stored IP address + * @return IP address of the interface or null if not yet connected + */ + virtual nsapi_error_t get_ip_address(SocketAddress *address); + + MBED_DEPRECATED_SINCE("mbed-os-5.15", "String-based APIs are deprecated") + virtual const char *get_ip_address(); + + /** Get the internally stored MAC address + * @return MAC address of the interface + */ + virtual const char *get_mac_address(); + + /** Get the local gateway + * + * @return Null-terminated representation of the local gateway + * or null if no network mask has been recieved + */ + virtual nsapi_error_t get_gateway(SocketAddress *address); + + MBED_DEPRECATED_SINCE("mbed-os-5.15", "String-based APIs are deprecated") + virtual const char *get_gateway(); + + /** Get the local network mask + * + * @return Null-terminated representation of the local network mask + * or null if no network mask has been recieved + */ + virtual nsapi_error_t get_netmask(SocketAddress *address); + + MBED_DEPRECATED_SINCE("mbed-os-5.15", "String-based APIs are deprecated") + virtual const char *get_netmask(); + + /** Get the network interface name + * + * @return Null-terminated representation of the network interface name + * or null if interface not exists + */ + virtual char *get_interface_name(char *interface_name); + + /** Gets the current radio signal strength for active connection + * + * @return Connection strength in dBm (negative value) + */ + virtual int8_t get_rssi(); + + /** Scan for available networks + * + * This function will block. + * + * @param res Pointer to allocated array to store discovered AP + * @param count Size of allocated @a res array, or 0 to only count available AP + * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error + * see @a nsapi_error + */ + virtual int scan(WiFiAccessPoint *res, unsigned count); + + /** Translates a hostname to an IP address with specific version + * + * The hostname may be either a domain name or an IP address. If the + * hostname is an IP address, no network transactions will be performed. + * + * If no stack-specific DNS resolution is provided, the hostname + * will be resolve using a UDP socket on the stack. + * + * @param address Destination for the host SocketAddress + * @param host Hostname to resolve + * @param version IP version of address to resolve, NSAPI_UNSPEC indicates + * version is chosen by the stack (defaults to NSAPI_UNSPEC) + * @return 0 on success, negative error code on failure + */ + using NetworkInterface::gethostbyname; + + /** Add a domain name server to list of servers to query + * + * @param addr Destination for the host address + * @return 0 on success, negative error code on failure + */ + using NetworkInterface::add_dns_server; + + /** @copydoc NetworkStack::setsockopt + */ + virtual nsapi_error_t setsockopt(nsapi_socket_t handle, int level, + int optname, const void *optval, unsigned optlen); + + /** @copydoc NetworkStack::getsockopt + */ + virtual nsapi_error_t getsockopt(nsapi_socket_t handle, int level, int optname, + void *optval, unsigned *optlen); + + /** Register callback for status reporting + * + * The specified status callback function will be called on status changes + * on the network. The parameters on the callback are the event type and + * event-type dependent reason parameter. + * + * @param status_cb The callback for status changes + */ + virtual void attach(mbed::Callback status_cb); + + /** Get the connection status + * + * @return The connection status according to ConnectionStatusType + */ + virtual nsapi_connection_status_t get_connection_status() const; + +protected: + /** Open a socket + * @param handle Handle in which to store new socket + * @param proto Type of socket to open, NSAPI_TCP or NSAPI_UDP + * @return 0 on success, negative on failure + */ + virtual int socket_open(void **handle, nsapi_protocol_t proto); + + /** Close the socket + * @param handle Socket handle + * @return 0 on success, negative on failure + * @note On failure, any memory associated with the socket must still + * be cleaned up + */ + virtual int socket_close(void *handle); + + /** Bind a server socket to a specific port + * @param handle Socket handle + * @param address Local address to listen for incoming connections on + * @return 0 on success, negative on failure. + */ + virtual int socket_bind(void *handle, const SocketAddress &address); + + /** Start listening for incoming connections + * @param handle Socket handle + * @param backlog Number of pending connections that can be queued up at any + * one time [Default: 1] + * @return 0 on success, negative on failure + */ + virtual int socket_listen(void *handle, int backlog); + + /** Connects this TCP socket to the server + * @param handle Socket handle + * @param address SocketAddress to connect to + * @return 0 on success, negative on failure + */ + virtual int socket_connect(void *handle, const SocketAddress &address); + + /** Accept a new connection. + * @param handle Handle in which to store new socket + * @param server Socket handle to server to accept from + * @return 0 on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_accept(void *handle, void **socket, SocketAddress *address); + + /** Send data to the remote host + * @param handle Socket handle + * @param data The buffer to send to the host + * @param size The length of the buffer to send + * @return Number of written bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_send(void *handle, const void *data, unsigned size); + + /** Receive data from the remote host + * @param handle Socket handle + * @param data The buffer in which to store the data received from the host + * @param size The maximum length of the buffer + * @return Number of received bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_recv(void *handle, void *data, unsigned size); + + /** Send a packet to a remote endpoint + * @param handle Socket handle + * @param address The remote SocketAddress + * @param data The packet to be sent + * @param size The length of the packet to be sent + * @return The number of written bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size); + + /** Receive a packet from a remote endpoint + * @param handle Socket handle + * @param address Destination for the remote SocketAddress or null + * @param data The buffer for storing the incoming packet data + * If a packet is too long to fit in the supplied buffer, + * excess bytes are discarded + * @param size The length of the buffer + * @return The number of received bytes on success, negative on failure + * @note This call is not-blocking, if this call would block, must + * immediately return NSAPI_ERROR_WOULD_WAIT + */ + virtual int socket_recvfrom(void *handle, SocketAddress *address, void *data, unsigned size); + + /** Register a callback on state change of the socket + * @param handle Socket handle + * @param attach_callback Function to call on state change + * @param data Argument to pass to callback + * @note Callback may be called in an interrupt context. + */ + virtual void socket_attach(void *handle, void (*attach_callback)(void *), void *data); + + /** Provide access to the NetworkStack object + * + * @return The underlying NetworkStack object + */ + virtual NetworkStack *get_stack() + { + return this; + } + + /** Set blocking status of connect() which by default should be blocking. + * + * @param blocking Use true to make connect() blocking. + * @return NSAPI_ERROR_OK on success, negative error code on failure. + */ + virtual nsapi_error_t set_blocking(bool blocking); + +private: + + // Drivers's socket info + struct _sock_info { + bool open; + uint16_t sport; + }; + struct _sock_info _sock_i[QCA400X_SOCKET_COUNT]; + + /* Add other private members here */ + nsapi_error_t _connect_retval; + + char _ssid[QCA400X_SSID_MAX_LENGTH + 1]; + char ap_pass[QCA400X_PASSPHRASE_MAX_LENGTH + 1]; /* The longest possible passphrase; +1 for the \0 */ + nsapi_security_t _ap_sec; + uint8_t _channel_num; + + bool _if_blocking; // NetworkInterface, blocking or not + + nsapi_error_t _conn_status_to_error(); + + rtos::ConditionVariable _if_connected; + + QCA400x _qca400x; + void refresh_conn_state_cb(); + + //sigio + struct { + void (*callback)(void *); + void *data; + uint8_t deferred; + } _cbs[QCA400X_SOCKET_COUNT]; + void event(int sock); + + // Connection state reporting to application + nsapi_connection_status_t _conn_stat; + mbed::Callback _conn_stat_cb; + + // Use global EventQueue + events::EventQueue *_global_event_queue; + int _connect_event_id; + void _connect_async(); + rtos::Mutex _cmutex; // Protect asynchronous connection logic +}; + +#endif + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/QCA400x.cpp b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400x.cpp new file mode 100644 index 00000000000..7b59ac921ef --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400x.cpp @@ -0,0 +1,812 @@ +/* QCA400x Class + * Copyright (c) 2019 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "QCA400x.h" +#include "ip4string.h" +#include "atheros_stack_offload.h" + +// Convert an unsigned thirty-two-bit value from host endianness to network +#define CSV_BYTES_TO_UINT32_IPADDR(a0, a1, a2, a3) \ + (((uint32_t)(a0)&0xFF) << 24) | (((uint32_t)(a1)&0xFF) << 16) | (((uint32_t)(a2)&0xFF) << 8) | ((uint32_t)(a3)&0xFF) + +// Connection state reporting +mbed::Callback _conn_stat_cb; // QCA400XInterface registered +nsapi_connection_status_t _conn_status; +static osSemaphoreId_t conn_event; +static nsapi_security_t _security; +static mbed_rtos_storage_semaphore_t event_sem_storage; + +using namespace mbed; + +QCA400x::QCA400x(): + _callback(0), + _initialized(false), + sigioThread(osPriorityNormal, OS_STACK_SIZE, NULL, "QCA400X poll thread") +{ + _conn_status = NSAPI_STATUS_DISCONNECTED; + _security = NSAPI_SECURITY_NONE; + + for (int i = 0; i < SOCKET_COUNT; i++) { + _sock_i[i].open = false; + _sock_i[i].proto = NSAPI_UDP; + _sock_i[i].xSocket = 0; + } + osSemaphoreAttr_t event_sem_attr = { 0 }; + event_sem_attr.cb_mem = &event_sem_storage; + event_sem_attr.cb_size = sizeof(event_sem_storage); + + conn_event = osSemaphoreNew(1, 0, &event_sem_attr); +} + +nsapi_error_t QCA400x::initialize() +{ + int32_t result = 0; + + if (_initialized) { + return NSAPI_ERROR_OK; + } + + _smutex.lock(); + + /* Initialize WIFI shield */ + result = WIFISHIELD_Init(); + if (result != A_OK) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + /* Initialize the WIFI driver (thus starting the driver task) */ + result = wlan_driver_start(); + + if (result != A_OK) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + for (int i = 0; i < SOCKET_COUNT; i++) { + _sock_i[i].open = false; + _sock_i[i].proto = NSAPI_UDP; + _sock_i[i].xSocket = 0; + } + + /* Wait for Wi-Fi */ + wait_us(100 * 1000); + + sigioThread.start(mbed::callback(this, &QCA400x::poll)); + + _smutex.unlock(); + + _initialized = true; + + return NSAPI_ERROR_OK; +} + +static void connect_cb(uint8_t event, uint8_t devId, char *bssid, uint8_t bssConn) +{ + bool release_sem = false; + + if ((_security == NSAPI_SECURITY_WPA) || (_security == NSAPI_SECURITY_WPA2) || + (_security == NSAPI_SECURITY_WPA_WPA2)) { + + switch (event) { + case QCOM_ONCONNECT_EVENT_SUCCESS: + /* Do nothing, wait for 4-way handshake */ + // NOTE that station is not fully connected until PEER_FIRST_NODE_JOIN_EVENT + break; + case INVALID_PROFILE: + // this event is used to indicate RSNA failure + _conn_status = NSAPI_STATUS_DISCONNECTED; + release_sem = true; + break; + case PEER_FIRST_NODE_JOIN_EVENT: + // this event is used to RSNA success + _conn_status = NSAPI_STATUS_CONNECTING; + release_sem = true; + break; + case QCOM_ONCONNECT_EVENT_DISCONNECT: + _conn_status = NSAPI_STATUS_DISCONNECTED; + release_sem = true; + break; + default: + release_sem = true; + break; + } + } else { + switch (event) { + case QCOM_ONCONNECT_EVENT_SUCCESS: + _conn_status = NSAPI_STATUS_CONNECTING; + release_sem = true; + break; + case QCOM_ONCONNECT_EVENT_DISCONNECT: + _conn_status = NSAPI_STATUS_DISCONNECTED; + release_sem = true; + break; + default: + release_sem = true; + break; + } + } + + if (release_sem) { + MBED_ASSERT(_conn_stat_cb); + _conn_stat_cb(); + + osSemaphoreRelease(conn_event); + } +} + +nsapi_error_t QCA400x::connect(const char *ssid, const char *passPhrase, nsapi_security_t security, + uint8_t channel) +{ + WLAN_AUTH_MODE g_auth; + WLAN_CRYPT_TYPE g_cipher; + QCOM_SSID g_ssid; + QCOM_PASSPHRASE g_passphrase; + + switch (security) { + case NSAPI_SECURITY_NONE: + g_auth = WLAN_AUTH_NONE; + g_cipher = WLAN_CRYPT_NONE; + break; + case NSAPI_SECURITY_WEP: + g_auth = WLAN_AUTH_NONE; + g_cipher = WLAN_CRYPT_WEP_CRYPT; + break; + case NSAPI_SECURITY_WPA: + g_auth = WLAN_AUTH_WPA_PSK; + g_cipher = WLAN_CRYPT_TKIP_CRYPT; + break; + case NSAPI_SECURITY_WPA2: + case NSAPI_SECURITY_WPA_WPA2: + g_auth = WLAN_AUTH_WPA2_PSK; + g_cipher = WLAN_CRYPT_AES_CRYPT; + break; + case NSAPI_SECURITY_PAP: + case NSAPI_SECURITY_CHAP: + default: + return NSAPI_ERROR_UNSUPPORTED; + } + + _smutex.lock(); + + /* Set Wi-Fi to device mode */ + if (A_OK != (A_STATUS)qcom_op_set_mode(0, QCOM_WLAN_DEV_MODE_STATION)) { + _smutex.unlock(); + return NSAPI_ERROR_NO_CONNECTION; + } + + /* Set SSID, must be done before auth, cipher and passphrase */ + memset(g_ssid.ssid, 0, sizeof(g_ssid.ssid)); + strncpy(g_ssid.ssid, ssid, sizeof(g_ssid.ssid)); + if (A_OK != (A_STATUS)qcom_set_ssid(0, &g_ssid)) { + _smutex.unlock(); + return NSAPI_ERROR_NO_CONNECTION; + } + + /* Set encyption mode */ + if (A_OK != (A_STATUS)qcom_sec_set_encrypt_mode(0, g_cipher)) { + _smutex.unlock(); + return NSAPI_ERROR_NO_CONNECTION; + } + + /* Set auth mode */ + if (A_OK != qcom_sec_set_auth_mode(0, g_auth)) { + _smutex.unlock(); + return NSAPI_ERROR_NO_CONNECTION; + } + + if (security != NSAPI_SECURITY_NONE) { + /* Set passphrase */ + memset(g_passphrase.passphrase, 0, sizeof(g_passphrase.passphrase)); + strncpy(g_passphrase.passphrase, passPhrase, sizeof(g_passphrase.passphrase)); + if (A_OK != qcom_sec_set_passphrase(0, &g_passphrase)) { + _smutex.unlock(); + return NSAPI_ERROR_NO_CONNECTION; + } + } + + /* Set connect_callback */ + if (A_OK != qcom_set_connect_callback(0, (void *)connect_cb)) { + _smutex.unlock(); + return NSAPI_ERROR_NO_CONNECTION; + } + + /* Set the security type to be used by connect callback */ + _security = security; + + /* Commit settings to Wi-Fi module */ + if (A_OK != qcom_commit(0)) { + _smutex.unlock(); + return NSAPI_ERROR_NO_CONNECTION; + } + + /* Wait for callback to indicate connection is complete */ + /* semaphore is released in callback fn */ + if (osOK != osSemaphoreAcquire(conn_event, QCA400x_CONNECT_TIMEOUT)) { + _smutex.unlock(); + return NSAPI_ERROR_TIMEOUT; + } + + if (_conn_status == NSAPI_STATUS_CONNECTING) { + if (A_OK != getDhcp()) { + _smutex.unlock(); + return NSAPI_ERROR_DHCP_FAILURE; + } + } else { + return NSAPI_ERROR_AUTH_FAILURE; + } + + _smutex.unlock(); + + return NSAPI_ERROR_OK; +} + +bool QCA400x::disconnect() +{ + int32_t result = 0; + + _smutex.lock(); + + result = apDisconnect(); + + if (result != A_OK) { + _smutex.unlock(); + return false; + } + + /* Wait for callback to indicate disconnect is complete */ + /* semaphore is released in callback fn */ + if (osOK != osSemaphoreAcquire(conn_event, QCA400x_CONNECT_TIMEOUT)) { + _smutex.unlock(); + return false; + } + + _smutex.unlock(); + + _conn_status = NSAPI_STATUS_DISCONNECTED; + _security = NSAPI_SECURITY_NONE; + + return true; +} + +const char *QCA400x::getIPAddress() +{ + uint32_t address; + uint8_t bytes[4]; + + _smutex.lock(); + + if (A_OK != qcom_ipconfig(0, QCOM_IPCONFIG_QUERY, &address, NULL, NULL)) { + _smutex.unlock(); + return 0; + } + + _smutex.unlock(); + + for (int i = 0; i < 4; i++) { + bytes[i] = (address >> (8 * (3 - i))) & 0xFF; + } + + memset(_ip_buffer, 0, sizeof(_ip_buffer)); + ip4tos(bytes, _ip_buffer); + + return _ip_buffer; +} + +const char *QCA400x::getMACAddress() +{ + _smutex.lock(); + + memset(_mac_buffer, 0, sizeof(_mac_buffer)); + + if (A_OK != qcom_get_bssid(0, (uint8_t *)_mac_buffer)) { + _smutex.unlock(); + return 0; + } + + _smutex.unlock(); + + return _mac_buffer; +} + +const char *QCA400x::getGateway() +{ + uint32_t address; + uint8_t bytes[4]; + + _smutex.lock(); + + if (A_OK != qcom_ipconfig(0, QCOM_IPCONFIG_QUERY, NULL, NULL, &address)) { + _smutex.unlock(); + return 0; + } + + _smutex.unlock(); + + for (int i = 0; i < 4; i++) { + bytes[i] = (address >> (8 * (3 - i))) & 0xFF; + } + + memset(_gateway_buffer, 0, sizeof(_gateway_buffer)); + ip4tos(bytes, _gateway_buffer); + + return _gateway_buffer; +} + +const char *QCA400x::getNetmask() +{ + uint32_t address; + uint8_t bytes[4]; + + _smutex.lock(); + + if (A_OK != qcom_ipconfig(0, QCOM_IPCONFIG_QUERY, NULL, &address, NULL)) { + _smutex.unlock(); + return 0; + } + + _smutex.unlock(); + + for (int i = 0; i < 4; i++) { + bytes[i] = (address >> (8 * (3 - i))) & 0xFF; + } + + memset(_netmask_buffer, 0, sizeof(_netmask_buffer)); + ip4tos(bytes, _netmask_buffer); + + return _netmask_buffer; +} + +int QCA400x::scan(WiFiAccessPoint *res, unsigned count) +{ + QCOM_BSS_SCAN_INFO *scan_result = NULL; + unsigned int scan_result_num = 0; + nsapi_wifi_ap_t ap; + unsigned int i; + QCOM_SSID g_ssid; + + _smutex.lock(); + + /* Note: won't work if SSID is set already */ + qcom_get_ssid(0, &g_ssid); + if (g_ssid.ssid[0] != '\0') { + /* Empty SSID will only have the termination string */ + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + if (A_OK != qcom_set_scan(0, NULL)) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + if (qcom_get_scan(0, &scan_result, (int16_t *)&scan_result_num)) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + for (i = 0; i < scan_result_num; i++) { + memset(ap.ssid, 0, sizeof(ap.ssid)); + strncpy((char *)ap.ssid, (char const *)scan_result[i].ssid, scan_result[i].ssid_len); + strncpy((char *)ap.bssid, (char const *)scan_result[i].bssid, wificonfigMAX_BSSID_LEN); + ap.rssi = scan_result[i].rssi; + ap.channel = scan_result[i].channel; + + if (!scan_result[i].security_enabled) { + ap.security = NSAPI_SECURITY_NONE; + } else if ((0 == scan_result[i].rsn_cipher) || + (ATH_CIPHER_TYPE_WEP & scan_result[i].rsn_cipher)) { + ap.security = NSAPI_SECURITY_WEP; + } else if (ATH_CIPHER_TYPE_CCMP & scan_result[i].rsn_cipher) { + ap.security = NSAPI_SECURITY_WPA2; + } else { + ap.security = NSAPI_SECURITY_WPA; + } + + if (i < count) { + res[i] = WiFiAccessPoint(ap); + } + + if (count != 0 && i >= count) { + break; + } + } + + _smutex.unlock(); + + return i; +} + +nsapi_error_t QCA400x::dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version) +{ + return NSAPI_ERROR_OK; +} + +int8_t QCA400x::rssi() +{ + uint8_t rssi_val = 0; + + _smutex.lock(); + + if (qcom_sta_get_rssi(0, &rssi_val) != A_OK) { + _smutex.unlock(); + return 0; + } + + _smutex.unlock(); + + return rssi_val; +} + +void QCA400x::poll() +{ + QCA_CONTEXT_STRUCT *enetCtx = wlan_get_context(); + A_STATUS xStatus; + + while (1) { + /* Go through the sockets to see if data is available on any of the open sockets */ + for (int i = 0; i < SOCKET_COUNT; i++) { + /* Check if socket is open */ + if (_sock_i[i].open) { + _smutex.lock(); + /* Check if there is anything to be received on this socket. */ + xStatus = (A_STATUS)t_select(enetCtx, _sock_i[i].xSocket, 5000); + _smutex.unlock(); + + if (xStatus != A_ERROR) { + // notify data is available + if (_callback) { + _callback(i); + } + } + } + } + + /* Sleep for sometime */ + wait_us(50 * 1000); + } +} + +void QCA400x::sigio(Callback func) +{ + _callback = func; +} + +void QCA400x::attach(Callback status_cb) +{ + _conn_stat_cb = status_cb; +} + +nsapi_error_t QCA400x::open_socket(int id, nsapi_protocol_t proto) +{ + if (id >= SOCKET_COUNT) { + return NSAPI_ERROR_PARAMETER; + } + + _smutex.lock(); + + /* Create socket */ + if (proto == NSAPI_TCP) { + _sock_i[id].xSocket = qcom_socket(ATH_AF_INET, SOCK_STREAM_TYPE, 0); + } else { + _sock_i[id].xSocket = qcom_socket(ATH_AF_INET, SOCK_DGRAM_TYPE, 0); + } + + if (-1 == _sock_i[id].xSocket) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + _smutex.unlock(); + + _sock_i[id].proto = proto; + + return NSAPI_ERROR_OK; +} + +nsapi_error_t QCA400x::bind_socket(int id, const uint8_t *addr, uint16_t port) +{ + SOCKADDR_T localAddr = { 0 }; + int status; + + /* Check if socket has been opened */ + if (id >= SOCKET_COUNT || !(_sock_i[id].open)) { + return NSAPI_ERROR_PARAMETER; + } + + memset(&localAddr, 0, sizeof(localAddr)); + localAddr.sin_port = port; + localAddr.sin_family = ATH_AF_INET; + localAddr.sin_addr.s_addr = CSV_BYTES_TO_UINT32_IPADDR(0, 0, 0, 0); + + _smutex.lock(); + + status = qcom_bind(_sock_i[id].xSocket, (struct sockaddr *)(&localAddr), sizeof(localAddr)); + if (status != A_OK) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + _smutex.unlock(); + + return NSAPI_ERROR_OK; +} + +bool QCA400x::close_socket(int id) +{ + int status; + + if (id >= SOCKET_COUNT) { + return false; + } + + _smutex.lock(); + + _sock_i[id].open = false; + + status = qcom_socket_close(_sock_i[id].xSocket); + + if (status == A_ERROR) { + _smutex.unlock(); + return false; + } + + _smutex.unlock(); + + return true; +} + +int QCA400x::connect_socket(int id, const uint8_t *addr, uint16_t port) +{ + SOCKADDR_T localAddr = { 0 }; + int32_t xStatus = 0; + + if (id >= SOCKET_COUNT) { + return NSAPI_ERROR_PARAMETER; + } + + _smutex.lock(); + + memset(&localAddr, 0, sizeof(localAddr)); + localAddr.sin_port = port; + localAddr.sin_family = ATH_AF_INET; + localAddr.sin_addr.s_addr = CSV_BYTES_TO_UINT32_IPADDR(*addr, *(addr + 1), *(addr + 2), *(addr + 3)); + + xStatus = qcom_connect(_sock_i[id].xSocket, (struct sockaddr *)&localAddr, sizeof(localAddr)); + + if (0 != xStatus) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR;; + } + + _sock_i[id].open = true; + + _smutex.unlock(); + + return NSAPI_ERROR_OK; +} + +int32_t QCA400x::send(int id, const void *data, uint32_t size) +{ + char *sendBuf; + + _smutex.lock(); + + sendBuf = (char *)custom_alloc(size); + if (sendBuf == NULL) { + _smutex.unlock(); + return NSAPI_ERROR_NO_MEMORY; + } + + memcpy(sendBuf, data, size); + int ret = qcom_send(_sock_i[id].xSocket, sendBuf, size, 0); + custom_free(sendBuf); + + if (ret < 0) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + _smutex.unlock(); + + return NSAPI_ERROR_OK; +} + +int32_t QCA400x::sendto(int id, const void *data, uint32_t size, const uint8_t *addr, + uint16_t port) +{ + char *sendBuf; + int32_t result = 0; + SOCKADDR_T localAddr = { 0 }; + + _smutex.lock(); + + sendBuf = (char *)custom_alloc(size); + if (sendBuf == NULL) { + _smutex.unlock(); + return NSAPI_ERROR_NO_MEMORY; + } + + localAddr.sin_port = port; + localAddr.sin_addr.s_addr = CSV_BYTES_TO_UINT32_IPADDR(*addr, *(addr + 1), *(addr + 2), *(addr + 3)); + localAddr.sin_family = ATH_AF_INET; + + memcpy(sendBuf, data, size); + + /* Send data over UDP */ + result = qcom_sendto(_sock_i[id].xSocket, sendBuf, size, 0, + (struct sockaddr *)(&localAddr), sizeof(localAddr)); + + custom_free(sendBuf); + + if (result < 0) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + _smutex.unlock(); + + return NSAPI_ERROR_OK; +} + +int32_t QCA400x::recv(int id, void *data, uint32_t size) +{ + int xRetVal = 0; + QCA_CONTEXT_STRUCT *enetCtx = wlan_get_context(); + A_STATUS xStatus; + char *rx_buffer = NULL; + + _smutex.lock(); + + /* Check if there is anything to be received on this socket. */ + xStatus = (A_STATUS)t_select(enetCtx, _sock_i[id].xSocket, 5000); + + if (xStatus != A_ERROR) { + /* Data available. */ + xRetVal = qcom_recv(_sock_i[id].xSocket, &rx_buffer, size, 0); + + if (xRetVal == A_ERROR) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } else if (xRetVal == A_SOCK_INVALID) { + _smutex.unlock(); + return 0; + } + memcpy(data, rx_buffer, xRetVal); + + /* Free RxBuffer */ + if (NULL != rx_buffer) { + zero_copy_free(rx_buffer); + rx_buffer = NULL; + } + } else { + _smutex.unlock(); + return NSAPI_ERROR_WOULD_BLOCK; + } + + _smutex.unlock(); + + return xRetVal; +} + +int32_t QCA400x::recvfrom(struct qca400x_socket *socket, void *data, uint32_t size) +{ + int xRetVal = 0; + QCA_CONTEXT_STRUCT *enetCtx = wlan_get_context(); + A_STATUS xStatus; + SOCKADDR_T local_addr = { 0 }; + uint16_t local_len = sizeof(local_addr); + char *rx_buffer = NULL; + uint8_t ip_bytes[NSAPI_IPv4_BYTES]; + + _smutex.lock(); + + /* Check if there is anything to be received on this socket. */ + xStatus = (A_STATUS)t_select(enetCtx, _sock_i[socket->id].xSocket, 5000); + + if (xStatus != A_ERROR) { + /* Data available. */ + xRetVal = qcom_recvfrom(_sock_i[socket->id].xSocket, &rx_buffer, size, 0, + (struct sockaddr *)&local_addr, &local_len); + + + if (xRetVal < 0) { + _smutex.unlock(); + + return NSAPI_ERROR_DEVICE_ERROR; + } + + memcpy(data, rx_buffer, xRetVal); + + // Convert IP address in uint32_t to comma separated bytes + ip_bytes[0] = (uint8_t)(((local_addr.sin_addr.s_addr) >> 24) & 0xFF); + ip_bytes[1] = (uint8_t)(((local_addr.sin_addr.s_addr) >> 16) & 0xFF); + ip_bytes[2] = (uint8_t)(((local_addr.sin_addr.s_addr) >> 8) & 0xFF); + ip_bytes[3] = (uint8_t)((local_addr.sin_addr.s_addr) & 0xFF); + + socket->addr.set_ip_bytes(ip_bytes, NSAPI_IPv4); + socket->addr.set_port(local_addr.sin_port); + /* Free RxBuffer */ + if (NULL != rx_buffer) { + zero_copy_free(rx_buffer); + rx_buffer = NULL; + } + } else { + _smutex.unlock(); + return NSAPI_ERROR_WOULD_BLOCK; + } + + _smutex.unlock(); + + return xRetVal; +} + +int32_t QCA400x::setsockopt(int id, int optname, const void *optval, unsigned optlen) +{ + int name; + + if (optname == NSAPI_KEEPALIVE) { + name = SO_KEEPALIVE; + } else if (optname == NSAPI_LINGER) { + name = SO_LINGER; + } else { + return NSAPI_ERROR_UNSUPPORTED; + } + + _smutex.lock(); + + int ret = qcom_setsockopt(_sock_i[id].xSocket, SOL_SOCKET, name, (void *)optval, optlen); + + if (ret < 0) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + _smutex.unlock(); + return NSAPI_ERROR_OK; +} + +int32_t QCA400x::getsockopt(int id, int optname, void *optval) +{ + int name; + + if (optname == NSAPI_KEEPALIVE) { + name = SO_KEEPALIVE; + } else if (optname == NSAPI_LINGER) { + name = SO_LINGER; + } else { + return NSAPI_ERROR_UNSUPPORTED; + } + + _smutex.lock(); + + int ret = qcom_getsockopt(_sock_i[id].xSocket, SOL_SOCKET, name, optval, sizeof(int)); + + if (ret < 0) { + _smutex.unlock(); + return NSAPI_ERROR_DEVICE_ERROR; + } + + _smutex.unlock(); + return NSAPI_ERROR_OK; + +} + +nsapi_connection_status_t QCA400x::connection_status() const +{ + return _conn_status; +} + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/QCA400x.h b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400x.h new file mode 100644 index 00000000000..aa4d0de6faf --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/QCA400x.h @@ -0,0 +1,319 @@ + +/* QCA400x Class + * Copyright (c) 2019 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef QCA400x_H +#define QCA400x_H + +#include "rtos/Mutex.h" +#include "rtos/Thread.h" +#include "features/netsocket/nsapi_types.h" +#include "features/netsocket/WiFiAccessPoint.h" +#include "platform/Callback.h" +#include "qcom_api.h" +#include "wlan_qcom.h" +#include "features/netsocket/SocketAddress.h" + +// Various timeouts for different QCA400x operations +#ifndef QCA400x_CONNECT_TIMEOUT +#define QCA400x_CONNECT_TIMEOUT 30000 +#endif +#ifndef QCA400x_SEND_TIMEOUT +#define QCA400x_SEND_TIMEOUT 2000 +#endif +#ifndef QCA400x_RECV_TIMEOUT +#define QCA400x_RECV_TIMEOUT 2000 +#endif +#ifndef QCA400x_MISC_TIMEOUT +#define QCA400x_MISC_TIMEOUT 2000 +#endif + +#define QCA400X_SCAN_TIME_MIN 0 // [ms] +#define QCA400X_SCAN_TIME_MAX 1500 // [ms] +#define QCA400X_SCAN_TIME_MIN_DEFAULT 120 // [ms] +#define QCA400X_SCAN_TIME_MAX_DEFAULT 360 // [ms] + +/** + * @brief Max SSID length. + */ +#define wificonfigMAX_SSID_LEN ( 32 ) + +/** + * @brief Max BSSID length. + */ +#define wificonfigMAX_BSSID_LEN ( 6 ) + +struct qca400x_socket { + int id; + nsapi_protocol_t proto; + bool connected; + SocketAddress addr; +}; + +/** + * This is the interface class to wifi_qca + */ +class QCA400x { +public: + QCA400x(); + + /** + * Initialize QCA400x to default state + */ + nsapi_error_t initialize(); + + /** + * Connect QCA400x to AP + * + * @param ssid the name of the AP + * @param passPhrase the password of AP + * @param security security type + * @param channel channel on which the connection is to be made + * @return NSAPI_ERROR_OK only if QCA400x is connected successfully + */ + nsapi_error_t connect(const char *ssid, const char *passPhrase, nsapi_security_t security, uint8_t channel); + + /** + * Disconnect QCA400x from AP + * + * @return true only if QCA400x is disconnected successfully + */ + bool disconnect(void); + + /** + * Get the IP address of QCA400x + * + * @return null-teriminated IP address or null if no IP address is assigned + */ + const char *getIPAddress(void); + + /** + * Get the MAC address of QCA400x + * + * @return null-terminated MAC address or null if no MAC address is assigned + */ + const char *getMACAddress(void); + + /** Get the local gateway + * + * @return Null-terminated representation of the local gateway + * or null if no network mask has been received + */ + const char *getGateway(); + + /** Get the local network mask + * + * @return Null-terminated representation of the local network mask + * or null if no network mask has been recieved + */ + const char *getNetmask(); + + /** Scan for available networks + * + * @param ap Pointer to allocated array to store discovered AP + * @param limit Size of allocated @a res array, or 0 to only count available AP + * @return Number of entries in @a res, or if @a count was 0 number of available networks, negative on error + * see @a nsapi_error + */ + int scan(WiFiAccessPoint *res, unsigned count); + + /** Perform a dns query + * + * @param name Hostname to resolve + * @param ip Buffer to store IP address + * @return NSAPI error code + */ + nsapi_error_t dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version); + + /** Return RSSI for active connection + * + * @return Measured RSSI + */ + int8_t rssi(); + + /** Check if there is any incoming packet + * + */ + void poll(); + + /** + * Attach a function to call whenever sigio happens + * + * @param func A pointer to a void function, or 0 to set as none + */ + void sigio(mbed::Callback func); + + /** + * Attach a function to call whenever sigio happens + * + * @param obj pointer to the object to call the member function on + * @param method pointer to the member function to call + */ + template + void sigio(T *obj, M method) + { + sigio(mbed::Callback(obj, method)); + } + + /** + * Attach a function to call whenever network state has changed. + * + * @param func A pointer to a void function, or 0 to set as none + */ + void attach(mbed::Callback status_cb); + + template + void attach(T *obj, M method) + { + attach(mbed::Callback(obj, method)); + } + + /** + * Open a socketed connection + * + * @param id id to give the new socket, valid 0-4 + * @param type the type of socket to open "UDP" or "TCP" + * @return NSAPI_ERROR_OK in success, negative error code in failure + */ + nsapi_error_t open_socket(int id, nsapi_protocol_t proto); + + /** + * Bind a specific address to a socket + * + * @param id id to give the new socket, valid 0-4 + * @param address local IP address to bind + * @param port local port number + * @return NSAPI_ERROR_OK in success, negative error code in failure + */ + nsapi_error_t bind_socket(int id, const uint8_t *addr, uint16_t port); + + /** + * Close a socket + * + * @param id id to give the new socket, valid 0-4 + * @return true if socket was closed successfully, false otherwise + */ + bool close_socket(int id); + + /** + * Initiate a connection on a socket (blocking) + * + * @param id id to give the new socket, valid 0-4 + * @param addr IP address of the destination + * @param port port on the destination + * + * @return NSAPI_ERROR_OK in success, negative error code in failure + */ + int connect_socket(int id, const uint8_t *addr, uint16_t port); + + /** + * Sends data to an open socket (nonblocking) + * + * @param id id to give the new socket, valid 0-4 + * @param data data to be sent + * @param size number of bytes to be sent - max 1024 + * @return NSAPI_ERROR_OK in success, negative error code in failure + */ + int32_t send(int id, const void *data, uint32_t size); + + /** + * Send a packet to a remote endpoint + * + * @param id id to give the new socket, valid 0-4 + * @param data data to be sent + * @param size number of bytes to be sent - max 1024 + * @param addr IP address of the destination + * @param port port on the destination + * @return NSAPI_ERROR_OK in success, negative error code in failure + */ + int32_t sendto(int id, const void *data, uint32_t size, const uint8_t *addr, uint16_t port); + + /** + * Receives stream data from an open TCP socket (nonblocking) + * + * @param id id to give the new socket, valid 0-4 + * @param data placeholder for returned information + * @param size number of bytes to be received + * @return the number of bytes received + */ + int32_t recv(int id, void *data, uint32_t size); + + /** + * Receive a packet from a remote endpoint (nonblocking) + * + * @param socket pointer to the qca400x socket + * @param data placeholder for returned information + * @param size number of bytes to be received + * @return the number of bytes received + */ + int32_t recvfrom(struct qca400x_socket *socket, void *data, uint32_t size); + + /** + * Set socket options + * + * @param id id to give the new socket, valid 0-4 + * @param optname Stack-specific option identifier + * @param optval Option value + * @param optlen Length of the option value + * @return NSAPI_ERROR_OK in success, negative error code in failure + */ + int32_t setsockopt(int id, int optname, const void *optval, unsigned optlen); + + /** + * Get socket options + * + * @param id id to give the new socket, valid 0-4 + * @param optname Stack-specific option identifier + * @param optval Option value + * @return NSAPI_ERROR_OK in success, negative error code in failure + */ + int32_t getsockopt(int id, int optname, void *optval); + + /** Get the connection status + * + * @return The connection status according to ConnectionStatusType + */ + nsapi_connection_status_t connection_status() const; + + static const int8_t SOCKET_COUNT = 5; + +private: + + mbed::Callback _callback; + + rtos::Mutex _smutex; // Protect accesses + + // Add private members + int _initialized; + + // Address info + char _ip_buffer[16]; + char _gateway_buffer[16]; + char _netmask_buffer[16]; + char _mac_buffer[ATH_MAC_LEN]; + + // Socket info + struct _sock_info { + bool open; + nsapi_protocol_t proto; + int32_t xSocket; + }; + + struct _sock_info _sock_i[SOCKET_COUNT]; + rtos::Thread sigioThread; +}; +#endif /* QCA400x_H_ */ + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/mbed_lib.json b/components/wifi/COMPONENT_QCA400X_WIFI/mbed_lib.json new file mode 100644 index 00000000000..5c5a148f3a9 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/mbed_lib.json @@ -0,0 +1,20 @@ +{ + "name": "qca400x", + "macros": [ + "A_LITTLE_ENDIAN" + ], + "config": { + "debug": { + "help": "Enable debug logs. [true/false]", + "value": false + }, + "provide-default": { + "help": "Provide default WifiInterface. [true/false]", + "value": false + }, + "connector-type": { + "help": "Configuration for which board is used. [ARDUINO/MIKROE]", + "value": "MIKROE" + } + } +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_stack_offload.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_stack_offload.h new file mode 100644 index 00000000000..3f465dae6b8 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_stack_offload.h @@ -0,0 +1,800 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHEROS_STACK_OFFLOAD_H__ +#define __ATHEROS_STACK_OFFLOAD_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include "atheros_wifi.h" + +//TODO: find more appropriate place +typedef uint16_t socklen_t; + +#if ENABLE_STACK_OFFLOAD + +/**********************Macros and config parameters**********/ +#define MAX_SOCKETS_SUPPORTED (8) +#define SOCKET_NOT_FOUND (-1) +#define EMPTY_SOCKET_CONTEXT (0) +#define SOCKET_HANDLE_PLACEHOLDER (0xFFFFFFFF) +#define ATH_AF_INET (2) +#define ATH_PF_INET (ATH_AF_INET) +#define ATH_AF_INET6 (3) +#define ATH_PF_INET6 (ATH_AF_INET6) +#define IPV4_HEADER_LENGTH (20) +#define IPV6_HEADER_LENGTH (40) +#define TCP_HEADER_LENGTH (20) +#define UDP_HEADER_LENGTH (8) +#define IPV6_FRAGMENTATION_THRESHOLD (1280) +#define IPV4_FRAGMENTATION_THRESHOLD (AR4100_BUFFER_SIZE - TCP6_HEADROOM) +#define MAX_ETHERNET_FRAME_SIZE (1500) + +#define GLOBAL_SOCK_INDEX (MAX_SOCKETS_SUPPORTED) // Index used for global commands e.g. ipconfig, ping + +/*The following macro enables the zero copy feature. In memory-constrained systems, + the application will provide a pointer instead of an allocated buffer. The driver + will return the pointer to received packet instead of copying the packet over. + The application must call zero_copy_free() API after it is done with the buffer + and pass the pointer to buffer.*/ +#define ZERO_COPY 1 +#if !ZERO_COPY +# error "WiFi driver works only with ZERO_COPY enabled ! " +#endif + +/* NON_BLOCKING_TX- Macro used to control SEND behavior. + SECTION 1- Macro is disabled. + If this macro is disabled, application thread will block until a packet is + sent over SPI. This is not desirable in a single buffer scenario as it may + lead to deadlocks. + SECTION 2- Macro is enabled. + If this macro is enabled, the application thread will return after submitting + packet to the driver thread. Under this setting, the application MUST NOT + TRY TO REUSE OR FREE THIS BUFFER. This buffer is now owned by the driver. + The application should call custom_alloc again to get a new buffer. */ +#define NON_BLOCKING_TX 0 + +/* There may be scenarios where application does not wish to block on a receive operation. + This macro will enable non blocking receive behavior. Note that this change is only + limited to the host and does not affect target behavior.*/ +#define NON_BLOCKING_RX 0 + +/* If the host has only 1 RX buffer, receive operation can never be blocking, as + this may lead to deadlocks.*/ +#if WLAN_CONFIG_NUM_PRE_ALLOC_RX_BUFFERS < 2 + +#if NON_BLOCKING_RX == 0 +#error "Blocking receive not permitted with single RX buffer, please enable NON_BLOCKING_RX" +#endif + +#if NON_BLOCKING_TX == 0 +#error "Blocking tranmit not permitted with single RX buffer, please enable NON_BLOCKING_TX" +#endif + +#endif + +/* Generic/TCP socket options */ +#define SOL_SOCKET 1 + +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_MAXMSG 0x1010 /* get TCP_MSS (max segment size) */ +#define SO_LINGER 0x0080 /* linger on close if data present */ + +/* TCP User-settable options (used with setsockopt). */ +#define TCP_MAXSEG 0x2003 /* set maximum segment size */ + +/* RAW socket option */ +#define IP_HDRINCL 2 /* u_char; set/get IP header rcv/send or not */ + +/*Multicast options*/ +#define IP_MULTICAST_IF 9 /* u_char; set/get IP multicast i/f */ +#define IP_MULTICAST_TTL 10 /* u_char; set/get IP multicast ttl */ +#define IP_MULTICAST_LOOP 11 /* u_char; set/get IP multicast loopback */ +#define IP_ADD_MEMBERSHIP 12 /* ip_mreq; add an IP group membership */ +#define IP_DROP_MEMBERSHIP 13 /* ip_mreq; drop an IP group membership */ +#define IP_HDRINCL 2 /* int ; header is included with data */ + +/*IPv6*/ +#define IPV6_MULTICAST_IF 80 /* unisgned int; set IF for outgoing MC pkts */ +#define IPV6_MULTICAST_HOPS 81 /* int; set MC hopcount */ +#define IPV6_MULTICAST_LOOP 82 /* unisgned int; set to 1 to loop back */ +#define IPV6_JOIN_GROUP 83 /* ipv6_mreq; join MC group */ +#define IPV6_LEAVE_GROUP 84 /* ipv6_mreq; leave MC group */ +#define IPV6_V6ONLY 85 /* int; IPv6 only on this socket */ + +#define ATH_IN_MULTICAST(a) (((a)&0xF0000000L) == 0xE0000000L) + +#define CUSTOM_ALLOC(size) custom_alloc(size) + +#define CUSTOM_FREE(buf) custom_free(buf) + +#define ATH_IPPROTO_IP 0 +#define ATH_IPPROTO_ICMP 1 +#define ATH_IPPROTO_IGMP 2 /* added for IP multicasting changes */ +#define ATH_IPPROTO_TCP 6 +#define ATH_IPPROTO_UDP 17 +#define ATH_IPPROTO_RAW 255 +#define ATH_IPPROTO_IPV6 41 /* IPv6 header */ +#define ATH_IPPROTO_ROUTING 43 /* IPv6 Routing header */ +#define ATH_IPPROTO_FRAGMENT 44 /* IPv6 fragmentation header */ + +/* SSL cipher suites. To be used with SSL_configure(). */ +#define TLS_NULL_WITH_NULL_NULL 0x0000 +#define TLS_RSA_WITH_NULL_MD5 0x0001 +#define TLS_RSA_WITH_NULL_SHA 0x0002 +#define TLS_RSA_WITH_RC4_128_MD5 0x0004 +#define TLS_RSA_WITH_RC4_128_SHA 0x0005 +#define TLS_RSA_WITH_DES_CBC_SHA 0x0009 +#define TLS_RSA_WITH_3DES_EDE_CBC_SHA 0x000A +#define TLS_DHE_RSA_WITH_DES_CBC_SHA 0x0015 +#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA 0x0016 +#define TLS_RSA_WITH_AES_128_CBC_SHA 0x002F +#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA 0x0033 +#define TLS_RSA_WITH_AES_256_CBC_SHA 0x0035 +#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA 0x0039 +#define TLS_RSA_WITH_NULL_SHA256 0x003B +#define TLS_RSA_WITH_AES_128_CBC_SHA256 0x003C +#define TLS_RSA_WITH_AES_256_CBC_SHA256 0x003D +#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 0x0067 +#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 0x006B +#define TLS_PSK_WITH_RC4_128_SHA 0x008A +#define TLS_PSK_WITH_3DES_EDE_CBC_SHA 0x008B +#define TLS_PSK_WITH_AES_128_CBC_SHA 0x008C +#define TLS_PSK_WITH_AES_256_CBC_SHA 0x008D +#define TLS_RSA_WITH_AES_128_GCM_SHA256 0x009C +#define TLS_RSA_WITH_AES_256_GCM_SHA384 0x009D +#define TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 0x009E +#define TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 0x009F +#define TLS_ECDH_ECDSA_WITH_NULL_SHA 0xC001 +#define TLS_ECDH_ECDSA_WITH_RC4_128_SHA 0xC002 +#define TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA 0xC003 +#define TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA 0xC004 +#define TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA 0xC005 +#define TLS_ECDHE_ECDSA_WITH_NULL_SHA 0xC006 +#define TLS_ECDHE_ECDSA_WITH_RC4_128_SHA 0xC007 +#define TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA 0xC008 +#define TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA 0xC009 +#define TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA 0xC00A +#define TLS_ECDH_RSA_WITH_NULL_SHA 0xC00B +#define TLS_ECDH_RSA_WITH_RC4_128_SHA 0xC00C +#define TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA 0xC00D +#define TLS_ECDH_RSA_WITH_AES_128_CBC_SHA 0xC00E +#define TLS_ECDH_RSA_WITH_AES_256_CBC_SHA 0xC00F +#define TLS_ECDHE_RSA_WITH_NULL_SHA 0xC010 +#define TLS_ECDHE_RSA_WITH_RC4_128_SHA 0xC011 +#define TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA 0xC012 +#define TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA 0xC013 +#define TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA 0xC014 +#define TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 0xC023 +#define TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 0xC024 +#define TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 0xC025 +#define TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 0xC026 +#define TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 0xC027 +#define TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 0xC028 +#define TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 0xC029 +#define TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 0xC02A +#define TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 0xC02B +#define TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 0xC02C +#define TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 0xC02D +#define TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 0xC02E +#define TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 0xC02F +#define TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 0xC030 +#define TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 0xC031 +#define TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 0xC032 +#define TLS_RSA_WITH_AES_128_CCM 0xC09C +#define TLS_RSA_WITH_AES_256_CCM 0xC09D +#define TLS_DHE_RSA_WITH_AES_128_CCM 0xC09E +#define TLS_DHE_RSA_WITH_AES_256_CCM 0xC09F +#define TLS_RSA_WITH_AES_128_CCM_8 0xC0A0 +#define TLS_RSA_WITH_AES_256_CCM_8 0xC0A1 +#define TLS_DHE_RSA_WITH_AES_128_CCM_8 0xC0A2 +#define TLS_DHE_RSA_WITH_AES_256_CCM_8 0xC0A3 + +#define SSL_PROTOCOL_UNKNOWN 0x00 +#define SSL_PROTOCOL_SSL_3_0 0x30 +#define SSL_PROTOCOL_TLS_1_0 0x31 +#define SSL_PROTOCOL_TLS_1_1 0x32 +#define SSL_PROTOCOL_TLS_1_2 0x33 + +#define ATH_ETH_P_PAE 0x888E + +#define ATH_MAX_ROUTES 3 +/****************************************************************************** + * ***************************** CAUTION ****************************** + * THESE DATA STRUCTURES ARE USED BY FIRMWARE ALSO. MAKE SURE THAT BOTH ARE IN + * SYNCH WHEN YOU MODIFY THESE. + ******************************************************************************/ + +typedef PREPACK struct ip6_addr +{ + uint8_t s6_addr[16]; /* 128 bit IPv6 address */ +} POSTPACK IP6_ADDR_T; + +typedef PREPACK struct ip_addr +{ + uint32_t s_addr; +} POSTPACK IP_ADDR_T; + +typedef PREPACK struct sockaddr_4 +{ /// E.Y. add _4 + uint16_t sin_port FIELD_PACKED; // Port number + uint16_t sin_family FIELD_PACKED; // ATH_AF_INET + IP_ADDR_T sin_addr FIELD_PACKED; // IPv4 Address +} POSTPACK SOCKADDR_T; + +typedef PREPACK struct sockaddr_6 +{ + uint16_t sin6_family FIELD_PACKED; // ATH_AF_INET6 + uint16_t sin6_port FIELD_PACKED; // transport layer port # + uint32_t sin6_flowinfo FIELD_PACKED; // IPv6 flow information + IP6_ADDR_T sin6_addr FIELD_PACKED; // IPv6 address + uint32_t sin6_scope_id FIELD_PACKED; // set of interfaces for a scope +} POSTPACK SOCKADDR_6_T; + +typedef PREPACK struct _ip_mreq +{ + uint32_t imr_multiaddr FIELD_PACKED; // Multicast group address + uint32_t imr_interface FIELD_PACKED; // Interface address +} POSTPACK IP_MREQ_T; + +typedef PREPACK struct _ipv6_mreq +{ + IP6_ADDR_T ipv6mr_multiaddr FIELD_PACKED; /* IPv6 multicast addr */ + IP6_ADDR_T ipv6mr_interface FIELD_PACKED; /* IPv6 interface address */ +} POSTPACK IPV6_MREQ_T; + +enum SOCKET_TYPE +{ + SOCK_STREAM_TYPE = 1, /* TCP */ + SOCK_DGRAM_TYPE, /* UDP */ + SOCK_RAW_TYPE /* IP */ +}; + +enum IPCONFIG_MODE +{ + IPCFG_QUERY = 0, /*Retrieve IP parameters*/ + IPCFG_STATIC, /*Set static IP parameters*/ + IPCFG_DHCP, /*Run DHCP client*/ + IPCFG_AUTO, /*Run AUTO IP*/ +}; + +typedef PREPACK struct +{ + uint32_t length; + uint32_t resp_code; + uint32_t flags; + uint8_t data[1]; +} POSTPACK HTTPC_RESPONSE; + +enum DNSC_CMDS +{ + + GETHOSTBYNAME = 0, + GETHOSTBYNAME2, + RESOLVEHOSTNAME +}; + +/* HTTP Server socket command MACROS*/ +#define HTTP_UNKNOWN -1 +#define HTTP_SERVER_STOP 0 +#define HTTP_SERVER_START 1 +#define HTTPS_SERVER_STOP 2 +#define HTTPS_SERVER_START 3 + +/* HTTP Server Get/Post socket MACROS */ +#define HTTP_GET_METHOD 0 +#define HTTP_POST_METHOD 1 + +enum +{ + /* Host command macros */ + HTTPC_CONNECT_CMD, + HTTPC_GET_CMD, + HTTPC_POST_CMD, + HTTPC_DATA_CMD, + HTTPC_DISCONNECT_CMD, + HTTPC_CONNECT_SSL_CMD +}; + +enum +{ + ROUTE_ADD, + ROUTE_DEL, + ROUTE_SHOW, + ROUTE_MAX +}; + +#define GET_TLV_TYPE(x, y) (A_MEMCPY(&(y), (x), sizeof(uint16_t))) +#define GET_TLV_LENGTH(x, y) (A_MEMCPY(&(y), (x + 2), sizeof(uint16_t))) +#define GET_NEXT_TLV(x, y) ((x) + sizeof(uint16_t) + sizeof(uint16_t) + (y)) +#define GET_TLV_VAL(x) ((x) + sizeof(uint16_t) + sizeof(uint16_t)) + +enum WI_POST_EVENT_TLV_TYPE +{ + POST_TYPE_URI, + POST_TYPE_NAME, + POST_TYPE_VALUE +}; + +typedef struct +{ + uint32_t numTLV; /*Number of TLVs encapsulated in the event*/ + uint8_t data[1]; /*Start of TLV data*/ // TODO: original has size = 0 +} HTTP_POST_EVENT_T; + +#define MAX_DNSADDRS 3 +#define MAX_SNTP_SERVERS 2 +#define DNS_NAME_NOT_SPECIFIED 0 + +typedef PREPACK struct dnccfgcmd +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t mode FIELD_PACKED; // 0-gethostbyname, 1-gethostbyname2, 2-resolvehostname + uint32_t domain FIELD_PACKED; // AF_INET ,AF_INET6 + uint8_t ahostname[255]; + FIELD_PACKED +} POSTPACK DNC_CFG_CMD; + +typedef PREPACK struct dncrespinfo +{ + char dns_names[64] FIELD_PACKED; /* Buffer of names (usually w/domain) */ + int32_t h_length; + FIELD_PACKED /* Length of the address */ + int32_t h_addrtype FIELD_PACKED; // host address type + int32_t ipaddrs FIELD_PACKED; // count of entries in ipaddr_list + uint32_t ipaddrs_list[MAX_DNSADDRS] FIELD_PACKED; // list of ipv4 address + int32_t ip6addrs FIELD_PACKED; // count of ip6 entries in ip6addr_list + IP6_ADDR_T ip6addrs_list[MAX_DNSADDRS] FIELD_PACKED; // list of ip6 address + +} POSTPACK DNC_RESP_INFO; + +typedef PREPACK struct ip46addr +{ + uint8_t type FIELD_PACKED; + uint8_t au1Rsvd[3] FIELD_PACKED; + uint32_t addr4 FIELD_PACKED; + IP6_ADDR_T addr6 FIELD_PACKED; +} POSTPACK IP46ADDR; + +typedef struct sntp_time +{ + int32_t Sec FIELD_PACKED; + int32_t min FIELD_PACKED; + int32_t hour FIELD_PACKED; + int32_t mon FIELD_PACKED; + int32_t year FIELD_PACKED; + int32_t wday FIELD_PACKED; + int32_t yday FIELD_PACKED; +} POSTPACK tSntpTime; + +typedef PREPACK struct sntp_tm +{ + uint32_t tv_sec FIELD_PACKED; /* seconds */ + uint32_t tv_usec FIELD_PACKED; /* and microseconds */ +} POSTPACK tSntpTM; + +typedef PREPACK struct sntp_dns_addr +{ + uint8_t addr[68] FIELD_PACKED; + uint8_t resolve FIELD_PACKED; +} POSTPACK tSntpDnsAddr; + +typedef PREPACK struct IPv4Route +{ + uint32_t reserved FIELD_PACKED; + uint32_t address FIELD_PACKED; + uint32_t mask FIELD_PACKED; + uint32_t gateway FIELD_PACKED; + uint32_t ifIndex FIELD_PACKED; + uint32_t prot FIELD_PACKED; +} POSTPACK IPV4_ROUTE_T; + +typedef PREPACK struct IPv4RouteLists +{ + uint32_t rtcount FIELD_PACKED; + IPV4_ROUTE_T route[ATH_MAX_ROUTES] FIELD_PACKED; +} POSTPACK IPV4_ROUTE_LIST_T; + +typedef PREPACK struct IPv6Route +{ + uint32_t command FIELD_PACKED; + uint8_t address[16] FIELD_PACKED; + int32_t prefixlen FIELD_PACKED; + uint8_t nexthop[16] FIELD_PACKED; + uint32_t ifindex; + uint32_t prot; +} POSTPACK IPV6_ROUTE_T; + +typedef PREPACK struct IPv6RouteLists +{ + uint32_t rtcount FIELD_PACKED; + IPV6_ROUTE_T route[ATH_MAX_ROUTES] FIELD_PACKED; +} POSTPACK IPV6_ROUTE_LIST_T; + +#define MAX_OTA_AREA_READ_SIZE 1024 +typedef struct ota_upgrade_resp +{ + uint32_t resp_code; + uint32_t size; +} tOtaUpgradeResp; + +typedef PREPACK struct ota_info +{ + uint32_t resp_code; + uint32_t size; + uint8_t *data; +} POSTPACK tOtaReadResp; + +typedef PREPACK struct ota_done +{ + uint32_t resp_code; +} POSTPACK tOtaDoneResp; + +typedef struct ota_response_s +{ + uint32_t resp_code; +} POSTPACK tOtaResp; + +typedef struct ota_partition_get_size_response_s +{ + uint32_t resp_code; + uint32_t size; +} POSTPACK tOtaPartitionGetSizeResp; + +typedef struct ota_parse_image_hdr_response_s +{ + uint32_t resp_code; + uint32_t offset; +} POSTPACK tOtaParseImageHdrResp; + +typedef struct ota_partition_write_data_response_s +{ + uint32_t resp_code; + uint32_t size; +} POSTPACK tOtaPartitionWriteDataResp; + +typedef enum OTA_STATUS +{ + QCOM_OTA_OK = 0, + QCOM_OTA_COMPLETED = 1, + QCOM_OTA_FLASH_AUTH_PENDING = 3, + + QCOM_OTA_ERR_UNKOWN_MSG = 1000, + QCOM_OTA_ERR_IMAGE_NOT_FOUND = 1001, + QCOM_OTA_ERR_IMAGE_DOWNLOAD_FAIL = 1002, + QCOM_OTA_ERR_IMAGE_CHECKSUM_INCORRECT = 1003, + QCOM_OTA_ERR_SERVER_RSP_TIMEOUT = 1004, + QCOM_OTA_ERR_INVALID_FILENAME = 1005, + QCOM_OTA_ERR_UNSUPPORT_PROTOCOL = 1006, + QCOM_OTA_ERR_INVALID_PARTITION_INDEX = 1007, + QCOM_OTA_ERR_IMAGE_HDR_INCORRECT = 1008, + QCOM_OTA_ERR_INSUFFICIENT_MEMORY = 1009, + QCOM_OTA_ERR_PRESERVE_LAST_FAILED = 1010, + QCOM_OTA_ERR_NO_ACTIVE_OTA_SESSION = 1011, + QCOM_OTA_ERR_INVALID_PARTITION_ACESS = 1012, + QCOM_OTA_ERR_OTA_SESS_IN_PROGRESS = 1013, + QCOM_OTA_ERR_FLASH_READ_TIMEOUT = 1014, + QCOM_OTA_ERR_FLASH_ERASE_ERROR = 1015, + QCOM_OTA_ERR_IMAGE_OVERFLOW = 1016, + QCOM_OTA_ERR_IMAGE_UNDERFLOW = 1017, + QCOM_OTA_ERR_WRITE_DATA_ERROR = 1018, +} QCOM_OTA_STATUS_CODE_t; + +enum SslErrors +{ + ESSL_OK = 0, // success + ESSL_INVAL = -1, // Invalid argument + ESSL_NOSOCKET = -2, // No more SSL socket descriptors available + ESSL_HSNOTDONE = -3, // Handshake not done + ESSL_HSDONE = -4, // Handshake already done + ESSL_NOMEM = -5, // Out of memory + ESSL_CONN = -6, // SharkSslCon_Error + ESSL_CERT = -7, // SharkSslCon_CertificateError + ESSL_ALERTRECV = -8, // SharkSslCon_AlertRecv + ESSL_ALERTFATAL = -9, // SharkSslCon_AlertSend FATAL received. Connection must be closed. + ESSL_TIMEOUT = -10, // Timeout during handshake + ESSL_OOPS = -29, // Oops (something is terribly wrong) + ESSL_OK_HANDSHAKE = -32, // handshake complete (internal reason code, not an error) + + // Following TRUST reason codes are returned by sslValidate() + + /** The peer's SSL certificate is trusted, CN matches the host name, time is valid */ + ESSL_TRUST_CertCnTime = -32, // Same as ESSL_OK_HANDSHAKE + /** The peer's SSL certificate is trusted, CN matches the host name, time is expired */ + ESSL_TRUST_CertCn = -33, // name OK, time NOTOK + /** The peer's SSL certificate is trusted, CN does NOT match the host name, time is valid */ + ESSL_TRUST_CertTime = -34, // name NOTOK, time OK + /** The peer's SSL certificate is trusted, CN does NOT match host name, time is expired */ + ESSL_TRUST_Cert = -35, // name NOTOK, time NOTOK + /** The peer's SSL certificate is NOT trusted */ + ESSL_TRUST_None = -36, +}; + +typedef void SSL_CTX; +typedef void SSL; +typedef const uint8_t *SslCert; +typedef const uint8_t *SslCAList; + +typedef enum +{ + SSL_SERVER = 1, + SSL_CLIENT = 2 +} SSL_ROLE_T; + +typedef enum +{ + SSL_CERTIFICATE = 1, + SSL_CA_LIST = 2 +} SSL_CERT_TYPE_T; + +typedef PREPACK struct sslVerifyPolicy +{ + /** True to verify certificate commonName against peer's domain name */ + uint8_t domain FIELD_PACKED; + /** True to verify certificate time validity */ + uint8_t timeValidity FIELD_PACKED; + /** True to immediately send a fatal alert on detection of untrusted certificate */ + uint8_t sendAlert FIELD_PACKED; + /** Reserved */ + uint8_t reserved FIELD_PACKED; +} POSTPACK SSL_VERIFY_POLICY; + +#define SSL_CIPHERSUITE_LIST_DEPTH 8 +typedef PREPACK struct SSL_config +{ + uint16_t protocol FIELD_PACKED; + uint16_t cipher[SSL_CIPHERSUITE_LIST_DEPTH] FIELD_PACKED; + SSL_VERIFY_POLICY verify FIELD_PACKED; + char matchName[40] FIELD_PACKED; +} POSTPACK SSL_CONFIG; + +typedef PREPACK struct ssl_file_name_list +{ + uint8_t name[10][20] FIELD_PACKED; // The file names of the certificates or CA lists +} POSTPACK SSL_FILE_NAME_LIST; + +#if defined(__cplusplus) +extern "C" { +#endif + +#if ZERO_COPY +void zero_copy_free(void *buffer); +#endif + +int32_t t_socket(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t domain, uint32_t type, uint32_t protocol); +int32_t t_shutdown(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle); +int32_t t_connect(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, uint16_t length); +int32_t t_bind(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, uint16_t length); +int32_t t_listen(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint32_t backlog); +int32_t t_accept(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, socklen_t length); +int32_t t_sendto(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + uint8_t *buffer, + uint32_t length, + uint32_t flags, + void *name, + uint32_t socklength); +int32_t t_send(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint8_t *buffer, uint32_t length, uint32_t flags); + +#if T_SELECT_VER1 +int32_t t_accept_nb(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, socklen_t length); +#endif +int32_t t_setsockopt(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + uint32_t level, + uint32_t optname, + uint8_t *optval, + uint32_t optlen); +int32_t t_getsockopt(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + uint32_t level, + uint32_t optname, + uint8_t *optval, + uint32_t optlen); + +#if ZERO_COPY +int32_t t_recvfrom(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + void **buffer, + uint32_t length, + uint32_t flags, + void *name, + socklen_t *socklength); +int32_t t_recv(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void **buffer, uint32_t length, uint32_t flags); +#else +int32_t t_recvfrom(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + void *buffer, + uint32_t length, + uint32_t flags, + void *name, + socklen_t *socklength); +int32_t t_recv(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *buffer, uint32_t length, uint32_t flags); +#endif +int32_t t_select(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint32_t tv); + +#if T_SELECT_VER1 +int32_t FD_IsSet(uint32_t handle, uint32_t mask); +int32_t FD_Set(uint32_t handle, uint32_t *mask); +int32_t FD_Clr(uint32_t handle, uint32_t *mask); +int32_t FD_Zero(uint32_t *mask); + +int32_t t_select_ver1( + QCA_CONTEXT_STRUCT_PTR qca_ptr, int32_t num, uint32_t *r_fd, uint32_t *w_fd, uint32_t *e_fd, uint32_t tv); +#endif // T_SELECT_VER1 + +int32_t t_errno(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle); +A_STATUS t_ipconfig(void *handle, + uint32_t mode, + uint32_t *ipv4_addr, + uint32_t *subnetMask, + uint32_t *gateway4, + IP46ADDR *Dnsaddr, + char *hostname); +A_STATUS t_ping(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t ipv4_addr, uint32_t size, uint32_t ms_interval); +A_STATUS t_ping6(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint8_t *ip6addr, uint32_t size, uint32_t ms_interval); +A_STATUS t_ip6config(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t mode, + IP6_ADDR_T *v6Global, + IP6_ADDR_T *v6Local, + IP6_ADDR_T *v6DefGw, + IP6_ADDR_T *v6GlobalExtd, + int32_t *LinkPrefix, + int32_t *GlbPrefix, + int32_t *DefGwPrefix, + int32_t *GlbPrefixExtd); +int32_t t_ipconfig_dhcp_pool(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t *start_ipv4_addr, + uint32_t *end_ipv4_addr, + int32_t leasetime); +int32_t t_ipconfig_dhcps_cb_enable(QCA_CONTEXT_STRUCT_PTR qca_ptr, void *callback); +int32_t t_ipconfig_dhcpc_cb_enable(QCA_CONTEXT_STRUCT_PTR qca_ptr, void *callback); +A_STATUS t_ip6config_router_prefix(QCA_CONTEXT_STRUCT_PTR qca_ptr, + IP6_ADDR_T *v6addr, + int32_t prefixlen, + int32_t prefix_lifetime, + int32_t valid_lifetime); +A_STATUS custom_ipbridgemode(void *handle, uint16_t status); +A_STATUS custom_ipconfig_set_tcp_exponential_backoff_retry(QCA_CONTEXT_STRUCT_PTR qca_ptr, int32_t retry); +int32_t custom_ipconfig_set_ip6_status(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint16_t status); +A_STATUS custom_ipconfig_dhcp_release(QCA_CONTEXT_STRUCT_PTR qca_ptr); +A_STATUS custom_ipconfig_set_tcp_rx_buffer(QCA_CONTEXT_STRUCT_PTR qca_ptr, int32_t rxbuf); +A_STATUS custom_ip_http_server(void *handle, int32_t command); +A_STATUS custom_ip_http_server_method(void *handle, + int32_t command, + uint8_t *pagename, + uint8_t *objname, + int32_t objtype, + int32_t objlen, + uint8_t *value); +int32_t custom_http_set_post_cb(void *handle, void *cxt, void *callback); + +#if ENABLE_DNS_CLIENT +int32_t custom_ip_set_dns_block_time(void *handle, int32_t blockSec); +int32_t custom_ip_resolve_hostname(void *handle, DNC_CFG_CMD *DncCfg, DNC_RESP_INFO *DncRespInfo); +int32_t custom_ip_dns_client(void *handle, int32_t command); +int32_t custom_ip_dns_server_addr(void *handle, IP46ADDR *addr); +#endif +int32_t custom_ip_hostname(void *handle, char *domain_name); +#if ENABLE_DNS_SERVER +int32_t custom_ip_dns_local_domain(void *handle, char *domain_name); +int32_t custom_ipsetdns(void *handle, int32_t command, char *domain_name, IP46ADDR *dnsaddr); +int32_t custom_ip_dns_server(void *handle, uint32_t command); +int32_t custom_ipdns(void *handle, int32_t command, char *domain_name, IP46ADDR *dnsaddr); +#endif +#if ENABLE_SNTP_CLIENT +int32_t custom_ip_sntp_srvr_addr(void *handle, int32_t command, char *sntp_srvr_addr); +int32_t custom_ip_sntp_get_time(void *handle, tSntpTime *SntpTime); +int32_t custom_ip_sntp_get_time_of_day(void *handle, tSntpTM *SntpTm); +int32_t custom_ip_sntp_modify_zone_dse(void *handle, uint8_t hour, uint8_t min, uint8_t add_sub, uint8_t dse); +int32_t custom_ip_sntp_query_srvr_address(void *handle, tSntpDnsAddr SntpDnsAddr[MAX_SNTP_SERVERS]); +int32_t custom_ip_sntp_client(void *handle, int32_t command); +#endif +#if ENABLE_HTTP_CLIENT +A_STATUS custom_httpc_method(void *a_handle, uint32_t command, uint8_t *url, uint8_t *data, uint8_t **output); +#endif /* ENABLE_HTTP_CLIENT */ +void zero_copy_http_free(void *buffer); +#if ENABLE_ROUTING_CMDS +A_STATUS custom_ipv4_route(void *handle, + uint32_t command, + IP_ADDR_T *ipv4_addr, + IP_ADDR_T *subnetMask, + IP_ADDR_T *gateway, + uint32_t *ifIndex, + IPV4_ROUTE_LIST_T *routelist); +A_STATUS custom_ipv6_route(void *handle, + uint32_t command, + IP6_ADDR_T *ipv6_addr, + uint32_t *prefixLen, + IP6_ADDR_T *gateway, + uint32_t *ifIndex, + IPV6_ROUTE_LIST_T *routelist); +#endif +A_STATUS custom_tcp_connection_timeout(void *handle, uint32_t timeout_val); + +int32_t custom_ota_upgrade(void *handle, + uint32_t addr, + char *filename, + uint8_t mode, + uint8_t preserve_last, + uint8_t protocol, + uint32_t *resp_code, + uint32_t *length); +int32_t custom_ota_read_area(void *handle, uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *retlen); +int32_t custom_ota_done(void *handle, boolean good_image); +int32_t custom_ota_session_start(void *handle, uint32_t flags, uint32_t partition_index); +uint32_t custom_ota_partition_get_size(void *handle); +int32_t custom_ota_partition_erase(void *handle); +int32_t custom_ota_partition_verify_checksum(void *handle); +int32_t custom_ota_parse_image_hdr(void *handle, uint8_t *header, uint32_t *offset); +int32_t custom_ota_partition_write_data(void *handle, uint32_t offset, uint8_t *buf, uint32_t size, uint32_t *ret_size); +int32_t custom_ota_set_response_cb(void *handle, void *callback); + +/***************************************************************************************************/ +void *custom_alloc(uint32_t size); +void custom_free(void *buf); + +#if ENABLE_SSL +SSL_CTX *SSL_ctx_new(SSL_ROLE_T role, int32_t inbufSize, int32_t outbufSize, int32_t reserved); +int32_t SSL_ctx_free(SSL_CTX *ctx); +SSL *SSL_new(SSL_CTX *ctx); +int32_t SSL_setCaList(SSL_CTX *ctx, SslCAList caList, uint32_t size); +int32_t SSL_addCert(SSL_CTX *ctx, SslCert cert, uint32_t size); +int32_t SSL_storeCert(char *name, SslCert cert, uint32_t size); +int32_t SSL_loadCert(SSL_CTX *ctx, SSL_CERT_TYPE_T type, char *name); +int32_t SSL_listCert(SSL_FILE_NAME_LIST *fileNames); + +int32_t SSL_set_fd(SSL *ssl, uint32_t fd); +int32_t SSL_accept(SSL *ssl); +int32_t SSL_connect(SSL *ssl); +int32_t SSL_shutdown(SSL *ssl); +int32_t SSL_configure(SSL *ssl, SSL_CONFIG *cfg); + +#if ZERO_COPY +int32_t SSL_read(SSL *ssl, void **buf, int32_t num); +#else +int32_t SSL_read(SSL *ssl, void *buf, int32_t num); +#endif +int32_t SSL_write(SSL *ssl, const void *buf, int32_t num); + +#if defined(__cplusplus) +} +#endif + +#endif +#else // ENABLE_STACK_OFFLOAD +//typedef PREPACK struct ip6_addr +//{ +// uint8_t addr[16]; /* 128 bit IPv6 address */ +//} POSTPACK IP6_ADDR_T; +#endif // ENABLE_STACK_OFFLOAD + +#endif + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi.h new file mode 100644 index 00000000000..c84ef5e65ca --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi.h @@ -0,0 +1,58 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHEROS_WIFI_H__ +#define __ATHEROS_WIFI_H__ + +/* PORT_NOTE: atheros_wifi.h is intended to provide any system specific data + * structures and definitions required by the OS for a WIFI/Ethernet driver. + * Hence everything in this file is Customized to the requirements of the + * host OS. */ + +#include + +#include + +// ============================================================================ +// This is the ONLY place where the enet.h header files are included! +// ============================================================================ + +// typedef struct wlan_hardware_config_s { +//// /// The SPI bus instance number. Usually 0 or 1 +//// int spi_instance; +//// /// The SPI chip select (dspi_which_pcs_config_t) +//// int spi_cs; +//// /// The SPI baudrate +//// uint32_t spi_baudrate; +//// +//// /// The WLAN interrupt's IRQ number from the IRQn enum in MK22F51212.h (or similar) +//// int wlan_irq_number; +//// /// The GPIO ping used for power control of the WLAN chip, e.g. GPIO_MAKE_PIN(GPIOB_IDX, 19) +//// int wlan_power_pin; +//} wlan_hardware_config_t; + +#include "qca_structs.h" + +#endif /* __ATHEROS_WIFI_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi_api.h new file mode 100644 index 00000000000..7c40030f097 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi_api.h @@ -0,0 +1,575 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHEROS_WIFI_API_H__ +#define __ATHEROS_WIFI_API_H__ + +/* PORT_NOTE: atheros_wifi_api.h is intended to expose user level API's and + * data structures. These structures provide access to the driver that + * would not otherwise be provided by the system's existing driver interface. + * It is imagined that the existing driver interface would have some form + * of IO_CTRL API with pre-defined commands. These commands are intended to + * extend those provided by the default. It is further imagined that in + * such a system the developer would add an IO_CTRL for Vendor specific + * commands which would act as a wrapper for the ath_ioctl_cmd commands + * defined below. */ + +#include + +enum ath_ioctl_cmd +{ + ATH_SET_TXPWR, + ATH_SET_PMPARAMS, + ATH_SET_LISTEN_INT, + ATH_SET_CIPHER, + ATH_SET_SEC_MODE, + ATH_SET_PHY_MODE, + ATH_GET_PHY_MODE, + ATH_GET_RX_RSSI, /* output uint32_t */ + ATH_SET_CONNECT_STATE_CALLBACK, /* input ATH_CONNECT_CB */ + ATH_DEVICE_SUSPEND_ENABLE, /* input NONE */ + ATH_DEVICE_SUSPEND_START, /* */ + ATH_SET_PMK, + ATH_GET_PMK, + ATH_GET_VERSION, + ATH_START_WPS, + ATH_AWAIT_WPS_COMPLETION, + ATH_SCAN_CTRL, + ATH_CHIP_STATE, + ATH_MAC_TX_RAW, + ATH_SET_CHANNEL, + ATH_SET_AGGREGATION, + ATH_ASSERT_DUMP, + ATH_SET_SSID, + ATH_SET_CONNECT, + ATH_SET_SEC_TYPE, + ATH_SET_COMMIT, + ATH_SET_MODE, + ATH_SET_FREQ, + ATH_SET_RTS, + ATH_SET_PASSPHRASE, + ATH_SET_SCAN, + ATH_GET_SCAN_RESULTS, + ATH_SET_ENCODE, + ATH_SET_POWER, + ATH_GET_POWER, + ATH_GET_ESSID, + ATH_GET_SEC_TYPE, + ATH_PROGRAM_FLASH, + ATH_EXECUTE_FLASH, + ATH_GET_MACADDR, + ATH_IS_DRIVER_INITIALIZED, + ATH_GET_TX_STATUS, + ATH_SET_PROMISCUOUS_MODE, + ATH_GET_REG_DOMAIN, + ATH_START_SCAN_EXT, + ATH_GET_SCAN_EXT, + ATH_GET_LAST_ERROR, + ATH_GET_CHANNEL, + ATH_CONFIG_AP, + ATH_P2P_CONNECT, + ATH_P2P_CONNECT_CLIENT, + ATH_P2P_FIND, + ATH_P2P_LISTEN, + ATH_P2P_CANCEL, + ATH_P2P_STOP, + ATH_P2P_JOIN, + ATH_P2P_NODE_LIST, + ATH_P2P_SET_CONFIG, + ATH_P2P_WPS_CONFIG, + ATH_P2P_AUTH, + ATH_P2P_DISC_REQ, + ATH_P2P_SET, + ATH_P2P_INVITE_AUTH, + ATH_P2P_PERSISTENT_LIST, + ATH_P2P_INVITE, + ATH_P2P_INV_CONNECT, + ATH_P2P_JOIN_PROFILE, + ATH_P2P_APMODE, + ATH_P2P_APMODE_PP, + ATH_P2P_SWITCH, + ATH_P2P_SET_NOA, + ATH_P2P_SET_OPPPS, + ATH_P2P_SDPD, + ATH_SET_P2P_CALLBACK, + ATH_P2P_EVENT_CALLBACK, + ATH_ONOFF_LPL, + ATH_ONOFF_GTX, + ATH_PROGRAM_MAC_ADDR, + ATH_GET_RATE, + ATH_SET_RATE, + ATH_HTC_REVERSE_CREDITS_INIT, + ATH_GPIO_CMD, + ATH_SET_TX_PWR_SCALE, + + ATH_PFM_CMD, + ATH_DIAG_CMD, + ATH_PMU_SET_PARAMS, + ATH_SET_DEVICE_ID, + ATH_GET_VERSION_STR, + ATH_GET_CONC_DEV_CHANNEL, + ATH_DSET_READ_CMD, + ATH_DSET_WRITE_CMD, + + ATH_DSET_OP_CMD, + ATH_GET_TEMPERATURE, + ATH_ROAM_CTRL, + ATH_GET_CHANNELHINT, + ATH_SET_OP_MODE, + ATH_GET_OP_MODE, + ATH_SET_WEPKEY, + ATH_GET_WEPKEY, + ATH_SET_WEPINDEX, + ATH_GET_WEPINDEX, + ATH_SET_SCAN_PARAM, + ATH_SET_PARAM, + ATH_SET_PROBEREQ_CB, + ATH_SET_PROBEREQ_EV_ENABLE, + ATH_PROGRAM_COUNTRY_CODE, + ATH_GET_COUNTRY_CODE, + ATH_SET_APPIE, + ATH_WLAN_WPS_INIT_KEY, + ATH_HEARTBEAT_CHALLEANGE, + /************************************/ + /* add new commands above this line */ + /************************************/ + ATH_CMD_LAST /* NOTE: ensure that this is the last entry in the enum */ +}; + +// IEEE 802.11 channels in MHz Geographies where channel is allowed +#define ATH_IOCTL_FREQ_1 (2412) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_2 (2417) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_3 (2422) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_4 (2427) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_5 (2432) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_6 (2437) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_7 (2442) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_8 (2447) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_9 (2452) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_10 (2457) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_11 (2462) // USA, Canada, Europe, Japan +#define ATH_IOCTL_FREQ_12 (2467) // Europe, Japan +#define ATH_IOCTL_FREQ_13 (2472) // Europe, Japan +#define ATH_IOCTL_FREQ_14 (2484) // Japan +#define ATH_IOCTL_FREQ_36 (5180) // 11 A channels +#define ATH_IOCTL_FREQ_40 (5200) // 11 A channels +#define ATH_IOCTL_FREQ_44 (5220) // 11 A channels +#define ATH_IOCTL_FREQ_48 (5240) // 11 A channels +#define ATH_IOCTL_FREQ_52 (5260) // 11 A channels +#define ATH_IOCTL_FREQ_56 (5280) // 11 A channels +#define ATH_IOCTL_FREQ_60 (5300) // 11 A channels +#define ATH_IOCTL_FREQ_64 (5320) // 11 A channels +#define ATH_IOCTL_FREQ_100 (5500) // 11 A channels +#define ATH_IOCTL_FREQ_104 (5520) // 11 A channels +#define ATH_IOCTL_FREQ_108 (5540) // 11 A channels +#define ATH_IOCTL_FREQ_112 (5560) // 11 A channels +#define ATH_IOCTL_FREQ_116 (5580) // 11 A channels +#define ATH_IOCTL_FREQ_132 (5660) // 11 A channels +#define ATH_IOCTL_FREQ_136 (5680) // 11 A channels +#define ATH_IOCTL_FREQ_140 (5700) // 11 A channels +#define ATH_IOCTL_FREQ_149 (5745) // 11 A channels +#define ATH_IOCTL_FREQ_153 (5765) // 11 A channels +#define ATH_IOCTL_FREQ_157 (5785) // 11 A channels +#define ATH_IOCTL_FREQ_161 (5805) // 11 A channels +#define ATH_IOCTL_FREQ_165 (5825) // 11 A channels + +#define ATH_PMK_LEN (32) +#define ATH_PASSPHRASE_LEN (64) +#define ATH_MAX_SSID_LENGTH (32) +#define ATH_MAX_SCAN_CHANNELS (16) +#define ATH_MAX_SCAN_BUFFERS (12) + +#if DRIVER_CONFIG_ENABLE_STORE_RECALL +#define STORE_RECALL_BUF_SIZE (1400) // If store-recall is enabled, allocate shared buffer +// big enough to hold 1400 bytes of target data +#else +#define STORE_RECALL_BUF_SIZE (0) +#endif + +#define ATH_WPS_PIN_LEN (9) +#define ATH_WPS_MODE_PIN (1) +#define ATH_WPS_MODE_PUSHBUTTON (2) +#define WEP_SHORT_KEY (5) +#define WEP_LONG_KEY (13) +#define ATH_ACTIVE_CHAN_DWELL_TIME (60) // Max Dwell time per channel + +/*Structure definition for passing Atheros specific data from App*/ +typedef struct ath_ioctl_params +{ + uint16_t cmd_id; + void *data; + uint16_t length; +} ATH_IOCTL_PARAM_STRUCT, *ATH_IOCTL_PARAM_STRUCT_PTR; + +typedef struct ath_scan_list +{ + uint32_t num_scan_entries; + void *scan_list; +} ATH_SCAN_LIST, *ATH_SCAN_LIST_PTR; + +typedef struct ath_ap_params +{ + uint16_t cmd_subset; + void *data; +} ATH_AP_PARAM_STRUCT, *ATH_AP_PARAM_STRUCT_PTR; + +// AP mode sub commands +#define AP_SUB_CMD_BCON_INT 0x0001 +#define AP_SUB_CMD_HIDDEN_FLAG 0x0002 +#define AP_SUB_CMD_INACT_TIME 0x0003 +#define AP_SUB_CMD_SET_COUNTRY 0x0004 +#define AP_SUB_CMD_WPS_FLAG 0x0005 +#define AP_SUB_CMD_DTIM_INT 0x0006 +#define AP_SUB_CMD_PSBUF 0x0007 +/* A-MPDU aggregation is enabled on a per TID basis where each TID (0-7) + * represents a different traffic priority. The mapping to WMM access categories + * is as follows; WMM Best effort = TID 0-1 + * WMM Background = TID 2-3 + * WMM Video = TID 4-5 + * WMM Voice = TID 6-7 + * Once enabled A-MPDU aggregation may be negotiated with an Access Point/Peer + * device and then both devices may optionally use A-MPDU aggregation for + * transmission. Due to other bottle necks in the data path a system may not + * get improved performance by enabling A-MPDU aggregation. + */ +typedef struct +{ + uint16_t txTIDMask; /* bit mask to enable tx A-MPDU aggregation */ + uint16_t rxTIDMask; /* bit mask to enable rx A-MPDU aggregation */ +} ATH_SET_AGGREGATION_PARAM; + +#define ATH_CIPHER_TYPE_TKIP 0x04 +#define ATH_CIPHER_TYPE_CCMP 0x08 +#define ATH_CIPHER_TYPE_WEP 0x02 + +typedef struct cipher +{ + uint32_t ucipher; + uint32_t mcipher; +} cipher_t; + +typedef void (*ATH_CONNECT_CB)(int value, uint8_t devId, uint8_t *bssid, boolean bssConn); +typedef void (*WMI_HTTP_POST_EVENT_CB)(void *cxt, void *buf); +typedef void (*ATH_OTA_CB)(uint32_t ota_cmd, uint32_t resp_code, uint32_t result); +typedef void (*ATH_PROBEREQ_CB)(void *buf, int len, int freq); + +typedef struct _wepkeys +{ + uint8_t defKeyIndex; /* tx key index */ + uint8_t keyLength; /* must be one of WEP_SHORT_KEY || WEP_LONG_KEY */ + uint8_t numKeys; /* how many of the 4 keys below are populated */ + char *keys[4]; /* keys */ +} ATH_WEPKEYS, *ATH_WEPKEYS_PTR; + +typedef struct +{ + uint8_t ssid[32]; + uint8_t macaddress[6]; + uint16_t channel; + uint8_t ssid_len; +} WPS_SCAN_LST_ENTRY; + +typedef struct +{ + uint32_t host_ver; + uint32_t target_ver; + uint32_t wlan_ver; + uint32_t abi_ver; +} ATH_VERSION, *ATH_VERSION_PTR; + +typedef struct +{ + uint8_t host_ver[20]; + uint8_t target_ver[20]; + uint8_t wlan_ver[20]; + uint8_t abi_ver[20]; +} ATH_VERSION_STR, *ATH_VERSION_STR_PTR; + +typedef struct _wps_start +{ + WPS_SCAN_LST_ENTRY ssid_info; + uint8_t wps_mode; /* ATH_WPS_MODE_PIN | ATH_WPS_MODE_PUSHBUTTON */ + uint8_t timeout_seconds; + uint8_t connect_flag; + uint8_t pin[ATH_WPS_PIN_LEN]; + uint8_t pin_length; +} ATH_WPS_START, *ATH_WPS_START_PTR; + +typedef struct +{ + uint16_t idle_period; /* msec */ + uint16_t pspoll_number; + uint16_t dtim_policy; /*IGNORE_DTIM = 0x01, NORMAL_DTIM = 0x02,STICK_DTIM = 0x03, AUTO_DTIM = 0x04*/ + uint16_t tx_wakeup_policy; /*TX_WAKEUP_UPON_SLEEP = 1,TX_DONT_WAKEUP_UPON_SLEEP = 2*/ + uint16_t num_tx_to_wakeup; + uint16_t + ps_fail_event_policy; /*SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1,IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2*/ +} ATH_WMI_POWER_PARAMS_CMD; + +typedef enum +{ + ATH_WPS_ERROR_INVALID_START_INFO = 0x1, + ATH_WPS_ERROR_MULTIPLE_PBC_SESSIONS, + ATH_WPS_ERROR_WALKTIMER_TIMEOUT, + ATH_WPS_ERROR_M2D_RCVD +} ATH_WPS_ERROR_CODE; + +#define ATH_WPS_ERROR_SUCCESS 0x00 +#define ATH_WPS_ERROR_INVALID_START_INFO 0x01 +#define ATH_WPS_ERROR_MULTIPLE_PBC_SESSIONS 0x02 +#define ATH_WPS_ERROR_WALKTIMER_TIMEOUT 0x03 +#define ATH_WPS_ERROR_M2D_RCVD 0x04 +#define ATH_WPS_ERROR_PWD_AUTH_FAIL 0x05 +#define ATH_WPS_ERROR_CANCELLED 0x06 +#define ATH_WPS_ERROR_INVALID_PIN 0x07 + +typedef struct +{ + uint16_t ap_channel; + int8_t ssid[ATH_MAX_SSID_LENGTH + 1]; /* [OUT] network ssid */ + int16_t ssid_len; /* [OUT] number of valid chars in ssid[] */ + cipher_t cipher; /* [OUT] network cipher type values not defined */ + uint8_t key_index; /* [OUT] for WEP only. key index for tx */ + union + {/* [OUT] security key or passphrase */ + uint8_t wepkey[ATH_PASSPHRASE_LEN + 1]; + uint8_t passphrase[ATH_PASSPHRASE_LEN + 1]; + } u; + + uint8_t sec_type; /* [OUT] security type; one of QCA_MEDIACTL_SECURITY_TYPE... */ + uint8_t error; /* [OUT] error code one of ATH_WPS_ERROR_... */ + uint8_t dont_block; /* [IN] 1 - returns immediately if operation is not complete. + * 0 - blocks until operation completes. */ +} ATH_NETPARAMS; + +#define ATH_DISABLE_BG_SCAN (0x00000001) +#define ATH_DISABLE_FG_SCAN (0x00000002) + +typedef struct +{ + uint32_t flags; +} ATH_SCANPARAMS; + +typedef struct ath_program_flash +{ + uint8_t *buffer; + uint32_t load_addr; + uint16_t length; + uint32_t result; +} ATH_PROGRAM_FLASH_STRUCT; + +/* ATH_MAC_TX_FLAG... are used as TX qualifiers for frames containing WMI_TX_RATE_SCHEDULE in the + * meta data. 0 or more of these flags should be assigned to the flags member of the schedule. */ +#define ATH_MAC_TX_FLAG_ACK 0x01 // frame needs ACK response from receiver +#define ATH_MAC_TX_FLAG_SET_RETRY_BIT 0x02 // device will set retry bit in MAC header for retried frames. +#define ATH_MAC_TX_FLAG_SET_DURATION 0x04 // device will fill duration field in MAC header + /* NOTE: If ATH_MAC_TX_FLAG_USE_PREFIX == 0 device will NOT use prefix frame. + * If ATH_MAC_TX_FLAG_USE_PREFIX == 1 && ATH_MAC_TX_FLAG_PREFIX_RTS == 0 device will use CTS prefix. + * If ATH_MAC_TX_FLAG_USE_PREFIX == 1 && ATH_MAC_TX_FLAG_PREFIX_RTS == 1 device will use RTS prefix. + */ +#define ATH_MAC_TX_FLAG_USE_PREFIX 0x08 // device will send either RTS or CTS frame prior to subject frame. +#define ATH_MAC_TX_FLAG_PREFIX_RTS 0x10 // device will send RTS and wait for CTS prior to sending subject frame. +#define ATH_MAC_TX_LOAD_TSF 0x20 // device will fill the TSF field during transmit procedure. + +#define ATH_ACCESS_CAT_BE 0 /* best effort */ +#define ATH_ACCESS_CAT_BK 1 /* background */ +#define ATH_ACCESS_CAT_VI 2 /* video */ +#define ATH_ACCESS_CAT_VO 3 /* voice */ + +/* set ar4XXX_boot_param according to the desired boot options */ +/* AR4XXX_PARAM_MODE_NORMAL - instructs chip to boot normally; load wlan firmware to provide + * WMI services used in normal WIFI operation. + * AR4XXX_PARAM_MODE_BMI - instructs chip to boot to BMI and await further BMI communication + * from host processor. This option can be used to re-program chip serial flash and + * perform other non-standard tasks. + * AR4XXX_PARAM_QUAD_SPI_FLASH - instructs the chip to access flash chip using QUAD mode + * this mode is faster than standard mode but the flash chip must support it. This + * option can be OR'd (|) with other options. + * AR4XXX_PARAM_RAWMODE_BOOT - instructs the chip to boot a firmware image that supports the + * RAW TX mode but lacks support for many other WMI commands. This mode will allow for + * a faster boot in those instances where the full set of WMI commands is not necessary. + * This mode must be OR'd with AR4XXX_PARAM_NORMAL_BOOT. + */ + +#define AR4XXX_PARAM_MODE_NORMAL (0x00000002) +#define AR4XXX_PARAM_MODE_BMI (0x00000003) +#define AR4XXX_PARAM_MODE_MASK (0x0000000f) +#define AR4XXX_PARAM_QUAD_SPI_FLASH (0x80000000) +#define AR4XXX_PARAM_RAWMODE_BOOT (0x00000010 | AR4XXX_PARAM_MODE_NORMAL) +#define AR4XXX_PARAM_MACPROG_MODE (0x00000020 | AR4XXX_PARAM_MODE_NORMAL) +#define AR4XXX_PARAM_MANUFAC_MODE (0x00000030 | AR4XXX_PARAM_MODE_NORMAL) +#define AR4XXX_PARAM_COUNTRY_CODE_MODE (0x00000010 | AR4XXX_PARAM_MODE_NORMAL) + +/* combined params for common cases */ +#define AR4XXX_PARAM_NORMAL_QUAD (AR4XXX_PARAM_MODE_NORMAL | AR4XXX_PARAM_QUAD_SPI_FLASH) +#define AR4XXX_PARAM_RAW_QUAD (AR4XXX_PARAM_RAWMODE_BOOT | AR4XXX_PARAM_QUAD_SPI_FLASH) + +/*The following regulatory domain settings can be passed to target during boot*/ + +#define AR4XXX_PARAM_REG_DOMAIN_DEFAULT (0x00000000) /*Default regulatory domain*/ +#define AR4XXX_PARAM_REG_DOMAIN_1 (0x00000100) /* FCC3_FCCA reg domain*/ +#define AR4XXX_PARAM_REG_DOMAIN_2 (0x00000200) /* ETSI1_WORLD reg domain*/ +#define AR4XXX_PARAM_REG_DOMAIN_3 (0x00000300) /* MKK5_MKKC reg domain */ + +/* ATH_MAC_TX_RATE_SCHEDULE - Acts as a host-provided rate schedule to replace what would be normally determined + * by firmware. This allows the host to specify what rates and attempts should be used to transmit the + * frame. */ +typedef struct +{ +#define ATH_MAC_TX_MAX_RATE_SERIES (4) + uint8_t rateSeries[ATH_MAC_TX_MAX_RATE_SERIES]; // rate index for each series. first invalid rate terminates series. + uint8_t trySeries[ATH_MAC_TX_MAX_RATE_SERIES]; // number of tries for each series. + uint8_t flags; // combination of ATH_MAC_TX_FLAG... + uint8_t accessCategory; // should be ATH_ACCESS_CAT_BE for managment frames and multicast frames. +} ATH_MAC_TX_RATE_SCHEDULE; + +typedef struct +{ + ATH_MAC_TX_RATE_SCHEDULE rateSched; + uint8_t pktID; /* The packet ID to identify the tx request */ +} ATH_MAC_TX_PARAMS; + +typedef struct ath_mac_tx_raw +{ + uint8_t *buffer; /* pointer to contiguous tx buffer */ + uint16_t length; /* valid length in bytes of tx buffer */ + ATH_MAC_TX_PARAMS params; /* params governing transmit rules */ +} ATH_MAC_TX_RAW_S; + +typedef struct ath_tx_status +{ +#define ATH_TX_STATUS_IDLE 0x01 /* the TX pipe is 100% idle */ +#define ATH_TX_STATUS_HOST_PENDING 0x02 /* the TX pipe has 1 or more frames waiting in the host queue */ +#define ATH_TX_STATUS_WIFI_PENDING 0x03 /* the TX pipe has 1 or more frames in process on the WIFI device */ + uint16_t status; /* one of ATH_TX_STATUS_ */ +} ATH_TX_STATUS; + +typedef void (*ATH_PROMISCUOUS_CB)(void *); + +typedef struct ath_prom_mode +{ + uint8_t src_mac[6]; /* filter source mac address if desired. */ + uint8_t dst_mac[6]; /* filter destination mac address if desired. */ + uint8_t enable; /* 0 to disable promiscuous mode 1 to enable. */ +#define ATH_PROM_FILTER_SOURCE 0x01 /* only allow frames whose source mac matches src_mac */ +#define ATH_PROM_FILTER_DEST 0x02 /* only allow frames whose destination mac matches dst_mac */ + uint8_t filter_flags; /* filtering rules */ + ATH_PROMISCUOUS_CB cb; /* callback function driver will use to feed rx frames */ +} ATH_PROMISCUOUS_MODE; + +typedef struct ath_reg_domain +{ + uint32_t domain; +} ATH_REG_DOMAIN; + +#define SECURITY_AUTH_PSK 0x01 +#define SECURITY_AUTH_1X 0x02 + +typedef struct ath_scan_ext +{ + uint8_t channel; + uint8_t ssid_len; + uint8_t rssi; + uint8_t security_enabled; + uint16_t beacon_period; + uint8_t preamble; + uint8_t bss_type; + uint8_t bssid[6]; + uint8_t ssid[32]; + uint8_t rsn_cipher; + uint8_t rsn_auth; + uint8_t wpa_cipher; + uint8_t wpa_auth; +} ATH_SCAN_EXT; + +typedef struct ath_get_scan +{ + uint16_t num_entries; + ATH_SCAN_EXT *scan_list; +} ATH_GET_SCAN; + +typedef struct ath_program_country_code_addr +{ + uint8_t countryCode[3]; + uint8_t result; +} ATH_PROGRAM_COUNTRY_CODE_PARAM; +/* these result codes are provided in the result field of the ATH_PROGRAM_COUNTRY_CODE_PARAM structure */ +/*ATH_PROGRAM_COUNTRY_CODE_RESULT_SUCCESS - +successfully programmed country code address into wifi device +*/ +#define ATH_PROGRAM_COUNTRY_CODE_RESULT_SUCCESS (1) +/*ATH_PROGRAM_ COUNTRY_CODE _RESULT_DEV_DENIED - +Device denied the operation for several possible reasons. +The most common reason for this result is that the country code equals +the current country code found already in the device. +Also an invalid country code value can cause this result +*/ +#define ATH_PROGRAM_COUNTRY_CODE_RESULT_DEV_DENIED (2) +/*ATH_PROGRAM_ COUNTRY_CODE _RESULT_DEV_FAILED - +An error occurred on the device as it tried to program the country code. +*/ +#define ATH_PROGRAM_COUNTRY_CODE_RESULT_DEV_FAILED (3) +/*ATH_PROGRAM_ COUNTRY_CODE _RESULT_DRIVER_FAILED - +Driver tried but failed to program country code. +Possibly the driver did not have the proper code compiled to perform this operation. +*/ +#define ATH_PROGRAM_COUNTRY_CODE_RESULT_DRIVER_FAILED (4) +typedef struct ath_program_mac_addr +{ + uint8_t addr[6]; + uint8_t result; +} ATH_PROGRAM_MAC_ADDR_PARAM; + +/* these result codes are provided in the result field of the ATH_PROGRAM_MAC_ADDR_PARAM structure */ +/*ATH_PROGRAM_MAC_RESULT_SUCCESS - successfully (re-)programmed mac address into wifi device*/ +#define ATH_PROGRAM_MAC_RESULT_SUCCESS (1) +/*ATH_PROGRAM_MAC_RESULT_DEV_DENIED - Device denied the operation for several possible reasons + * the most common reason for this result is that the mac address equals the current mac + * address found already in the device. Also an invalid mac address value can cause this result + */ +#define ATH_PROGRAM_MAC_RESULT_DEV_DENIED (2) +/*ATH_PROGRAM_MAC_RESULT_DEV_FAILED - Device tried but failed to program mac address. + * An error occurred on the device as it tried to program the mac address. + */ +#define ATH_PROGRAM_MAC_RESULT_DEV_FAILED (3) +/*ATH_PROGRAM_MAC_RESULT_DRIVER_FAILED - Driver tried but failed to program mac address + * Possibly the driver did not have the proper code compiled to perform this operation. + */ +#define ATH_PROGRAM_MAC_RESULT_DRIVER_FAILED (4) + +#define ATH_MAX_IE_LEN 64 + +typedef struct ath_appie +{ + uint8_t mgmtFrmType; + uint8_t ieLen; + uint8_t *ieInfo; +} ATH_APPIE_PARAM; + +/* ATH_API_... return values should be of type ATH_API_RETURN_CODE and + * should be modified to suit the host sytem. */ +#define ATH_API_OK A_OK +#define ATH_API_ERROR A_ERROR +#endif /* __ATHEROS_WIFI_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi_internal.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi_internal.h new file mode 100644 index 00000000000..693fe5748ed --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/atheros_wifi_internal.h @@ -0,0 +1,73 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHEROS_WIFI_INTERNAL_H__ +#define __ATHEROS_WIFI_INTERNAL_H__ + +#define ATH_PROG_FEEDBACK_BLANK_FLASH (0x00000001) +#define ATH_PROG_FEEDBACK_LOADING (0x00000002) +#define ATH_PROG_FEEDBACK_EXECUTING (0x00000003) +#define ATH_PROG_FEEDBACK_DONE (0x00000004) +#define ATH_PROG_FEEDBACK_LOAD_FAIL (0x00000005) +#define ATH_PROG_FEEDBACK_COMM_ERROR (0x00000006) + +typedef struct +{ + A_STATUS (*Driver_TargetConfig)(void *); + A_STATUS (*Driver_BootComm)(void *); + A_STATUS (*Driver_BMIConfig)(void *); + void (*Api_TxComplete)(void *, void *); + void (*Api_RxComplete)(void *, void *); + void (*Boot_Profile)(uint32_t val); + void (*Custom_Delay)(uint32_t delay); + void (*Api_GpioDataEventRx)(uint8_t *datap, uint32_t len); + void (*Custom_reset_measure_timer)(void); + void (*Custom_Api_PfmDataEventRx)(uint8_t *datap, uint32_t len); + void (*Custom_Api_PfmDataDoneEventRx)(void *, uint8_t *datap, uint32_t len); + A_STATUS (*Driver_StoreRecallFirmwareDownload)(void *pCxt); + boolean skipWmi; + boolean exitAtBmi; +} ATH_CUSTOM_INIT_T; + +extern ATH_CUSTOM_INIT_T ath_custom_init; + +typedef struct +{ + uint32_t (*ath_ioctl_handler_ext)(void *, ATH_IOCTL_PARAM_STRUCT_PTR); +} ATH_CUSTOM_MEDIACTL_T; + +extern ATH_CUSTOM_MEDIACTL_T ath_custom_mediactl; + +typedef struct +{ + A_STATUS (*HTCConnectServiceExch)(void*, HTC_SERVICE_CONNECT_REQ*, HTC_SERVICE_CONNECT_RESP*, + HTC_ENDPOINT_ID*, uint32_t*); + A_STATUS (*HTCSendSetupComplete)(void *); + A_STATUS (*HTCGetReady)(void *); +} ATH_CUSTOM_HTC_T; + +extern ATH_CUSTOM_HTC_T ath_custom_htc; + +#endif /* __ATHEROS_WIFI_INTERNAL_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_init.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_init.c new file mode 100644 index 00000000000..a4c3669dc1d --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_init.c @@ -0,0 +1,291 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include "wifi_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const uint8_t max_performance_power_param = MAX_PERF_POWER; +const WMI_STORERECALL_CONFIGURE_CMD default_strrcl_config_cmd = {1, STRRCL_RECIPIENT_HOST}; +const WMI_POWER_PARAMS_CMD default_power_param = {0, + A_CPU2LE16(1), // nonzero value requires endian correction + 0, + 0, + A_CPU2LE16(1), // nonzero value requires endian correction + IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN}; + +const WMI_SCAN_PARAMS_CMD default_scan_param = {0, 0, 0, 0, 0, WMI_SHORTSCANRATIO_DEFAULT, DEFAULT_SCAN_CTRL_FLAGS, + 0, 0, 0}; + +#if ENABLE_P2P_MODE +const WMI_P2P_FW_SET_CONFIG_CMD default_p2p_config = {0, "US", 81, 6, 81, 6, A_CPU2LE32(3000), 10}; +#endif + +void Api_BootProfile(void *pCxt, uint8_t val) +{ + if (ath_custom_init.Boot_Profile != NULL) + { + ath_custom_init.Boot_Profile(val); + } +} + +/*****************************************************************************/ +/* Api_InitStart - implements common code for initializing the driver. + * This should be called before Api_InitFinish(). + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Api_InitStart(void *pCxt) +{ + A_STATUS status; + + do + { + /* 1 - initialize context */ + if (A_OK != (status = Driver_ContextInit(pCxt))) + { + break; + } + /* 2 - insert driver into system if necessary */ + if (A_OK != (status = DRIVER_INSERT(pCxt))) + { + break; + } + + /*3 - initilize socket context*/ + if (A_OK != (status = SOCKET_CONTEXT_INIT)) + { + break; + } + + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Api_InitFinish - implements common code for initializing the driver. + * This should be called after Api_InitStart(). + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Api_InitFinish(void *pCxt) +{ + // int32_t timeleft; + // int16_t i; + A_STATUS ret = A_OK; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + if (ath_custom_init.skipWmi) + { + return A_OK; + } + + do + { + // Api_BootProfile(pCxt, 0x00); + /* Wait for Wmi event to be ready Implementation of this macro is platform specific + * as multi-threaded systems will implement differently from single threaded. */ + /* Increased the WMI_READY timeout from 5 seconds to 15 seconds to allow + firmware download over SPI interface */ + if (A_OK != DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->wmiReady), true, 15000)) + { + ret = A_ERROR; + break; + } + + // Api_BootProfile(pCxt, BOOT_PROFILE_WMI_READY); + + // printf("%d\r\n", pDCxt->wmiReady); + if (pDCxt->wmiReady != true) + { + ret = A_ERROR; + break; + } + /* WMI_EVENT will have populated arVersion so now confirm that version is compatible */ + if (pDCxt->abiVersion != 1) + { + if ((pDCxt->abiVersion & ABI_MAJOR_MASK) != (AR6K_ABI_VERSION & ABI_MAJOR_MASK)) + { + ret = A_ERROR; + break; + } + } + + } while (0); + + return ret; +} + +static A_STATUS wmi_cmd_process(void *pCxt, WMI_COMMAND_ID cmd, const void *pParam, uint16_t length) +{ + A_STATUS status; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + status = wmi_cmd_start(pDCxt->pWmiCxt, pParam, cmd, length); + + if (status == A_NO_MEMORY) + { + pDCxt->tx_complete_pend = true; + + if (A_OK != DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->tx_complete_pend), false, 5000)) + { + A_ASSERT(0); + } + } + else if (status != A_OK) + { + A_ASSERT(0); + } + + return status; +} + +/*****************************************************************************/ +/* Api_WMIInitFinish - implements common code for sending default wmi commands + * to target. + * This should be called after Api_InitFinish(). + * void *pCxt - the driver context. + *****************************************************************************/ +void Api_WMIInitFinish(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + A_STATUS status; + WMI_ALLOW_AGGR_CMD allow_aggr_cmd; + + if (pDCxt->wmiReady == true) + { + do + { + status = STACK_INIT(pCxt); + + if (status == A_OK) + { + WAIT_FOR_WMI_RESPONSE(pCxt); + break; + } + else if (status == A_NO_MEMORY) + { + pDCxt->tx_complete_pend = true; + + if (A_OK != DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->tx_complete_pend), false, 5000)) + { + A_ASSERT(0); + } + } + else + { + A_ASSERT(0); + } + } while (1); + +/* issue some default WMI commands appropriate for most systems */ +#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN + wmi_cmd_process(pCxt, WMI_SET_POWER_PARAMS_CMDID, &default_power_param, sizeof(WMI_POWER_PARAMS_CMD)); +#endif + wmi_cmd_process(pCxt, WMI_SET_SCAN_PARAMS_CMDID, &default_scan_param, sizeof(WMI_SCAN_PARAMS_CMD)); + + wmi_cmd_process(pCxt, WMI_STORERECALL_CONFIGURE_CMDID, &default_strrcl_config_cmd, + sizeof(WMI_STORERECALL_CONFIGURE_CMD)); + pDCxt->strrclState = STRRCL_ST_INIT; + /* technically this call to wmi_allow_aggr_cmd is not necessary if both + * masks are 0 as the firmware has 0,0 as the default. */ + allow_aggr_cmd.tx_allow_aggr = A_CPU2LE16(pDCxt->txAggrTidMask); + allow_aggr_cmd.rx_allow_aggr = A_CPU2LE16(pDCxt->rxAggrTidMask); + wmi_cmd_process(pCxt, WMI_ALLOW_AGGR_CMDID, &allow_aggr_cmd, sizeof(WMI_ALLOW_AGGR_CMD)); +#if ENABLE_P2P_MODE + if (WLAN_NUM_OF_DEVICES == 2) + { + /* Device-0 is P2P Device and Device-1 is Legacy STA.\ + Set Default P2P Params + */ + wmi_cmd_process(pCxt, WMI_P2P_SET_CONFIG_CMDID, &default_p2p_config, sizeof(WMI_P2P_FW_SET_CONFIG_CMD)); + } +#endif + /* Set the BSS Filter to None. If this is not set, by default the firmware + sets to forward the beacons to host. This causes unnecessary BSSINFO events in + the host even after connecting to the AP */ + wmi_bssfilter_cmd(pDCxt->pWmiCxt, NONE_BSS_FILTER, 0); + } +} + +/*****************************************************************************/ +/* Api_DeInitStart - implements common code for de-initializing the driver. + * This should be called before Api_DeInitFinish(). + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Api_DeInitStart(void *pCxt) +{ + UNUSED_ARGUMENT(pCxt); + /* This is a place holder for future enhancements */ + return A_OK; +} + +/*****************************************************************************/ +/* Api_DeInitFinish - implements common code for de-initializing the driver. + * This should be called after Api_DeInitStart(). + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Api_DeInitFinish(void *pCxt) +{ + A_STATUS status = A_ERROR; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* 1 - block until driver thread is cleaned up. in systems without + * a driver thread this is a NOP. */ + if (A_OK != DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->driver_up), false, 5000)) + { + break; + } + /* 2 - remove driver from system */ + DRIVER_REMOVE(pCxt); + /* 3 - De-initialize context */ + Driver_ContextDeInit(pCxt); + + /*4 - Deinitialize socket context*/ + SOCKET_CONTEXT_DEINIT(); + + status = A_OK; + } while (0); + + return status; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_ioctl.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_ioctl.c new file mode 100644 index 00000000000..1255e8dd51c --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_ioctl.c @@ -0,0 +1,1164 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include "wifi_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hw20_mbox_host_reg.h" +#include +#include "hw20_apb_map.h" +#include "hw20_mbox_reg.h" +extern const WMI_SCAN_PARAMS_CMD default_scan_param; +uint8_t countryCode_storge[4]; +A_STATUS +Program_CountryCode(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt; + A_STATUS status = A_ERROR; + uint32_t param; + uint8_t pass_cycle = 0; + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + uint32_t country_code_word; + uint8_t *ptr_country_code = (uint8_t *)&country_code_word; + uint32_t i; + A_NETBUF_CONFIGURE(pReq, &country_code_word, 0, sizeof(uint32_t), sizeof(uint32_t)); + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* bring the chip down */ + pDCxt->wmiReady = false; + HW_PowerUpDown(pCxt, false); + /* bring the chip back up */ + HW_PowerUpDown(pCxt, true); + pDCxt->htc_creditInit = 0; + /* re-initialize host controller (sub-)driver = HCD */ + if ((status = Hcd_ReinitTarget(pCxt)) != A_OK) + { + A_ASSERT(0); + } + + if (pass_cycle == 0) + { + A_MDELAY(5); + /* wait for chip to reach point in initialization */ + do + { + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_refclk_hz)), (uint8_t *)¶m, + 4) != A_OK) + { + A_ASSERT(0); + } + } while (param != A_CPU2LE32(EXPECTED_REF_CLK_AR4100) && param != A_CPU2LE32(EXPECTED_REF_CLK_AR400X)); + /* on 1st pass the mac address is loaded into the + * scratch registers and the parameter is set to + * cause the firmware to read/program the mac address. + */ + ptr_country_code[0] = 0; + // the first byte is used to store the result, the rest three bytes are used to store countrycode + A_MEMCPY(&ptr_country_code[1], &countryCode_storge[1], 3); + QCADRV_PRINTF("ptr_country_code is %c, %c.\n", ptr_country_code[1], ptr_country_code[2]); + // ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, SCRATCH_ADDRESS, true, sizeof(uint32_t)); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, SCRATCH_ADDRESS, true, sizeof(uint32_t)); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + A_ASSERT(0); + } +#if 0 + A_MEMCPY(&ptr_country_code[0], &pDCxt->conn[pDCxt->devId].reqBssid[2], 4); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, SCRATCH_ADDRESS+4, true, sizeof(uint32_t)); + + if(A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))){ + A_ASSERT(0); + } +#endif + A_MDELAY(5); + param = A_CPU2LE32(AR4XXX_PARAM_COUNTRY_CODE_MODE); + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_flash_is_present)), + (uint8_t *)¶m, 4) != A_OK) + { + A_ASSERT(0); + } + /* wait some sufficient number of attempts before giving up. */ + for (i = 0; i < 100; i++) + { + /* poll scratch register for indication of completion */ + A_MDELAY(1); // delay 1 ms to make target execute the setting of countrycode + ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, SCRATCH_ADDRESS, true, sizeof(uint32_t)); + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + A_ASSERT(0); + } + // result from target is stored in ptr_country_code + if ((ptr_country_code[0] != 0)) + { + QCADRV_PRINTF("ptr_country_code break;.\n"); + break; /* done - exit loop */ + } + } + } + else + { + /* on 2nd pass the chip is brought up normally */ + A_MDELAY(5); + Driver_BootComm(pCxt); + pDCxt->chipDown = false; + } + + pass_cycle++; + } while (pass_cycle < 2); + + if (pass_cycle >= 2) + { + /* store result in reqBssid for use in calling function */ + countryCode_storge[0] = ptr_country_code[0]; + } + else + { + countryCode_storge[0] = 0; + } + QCADRV_PRINTF("target result is %c,%d.\n", ptr_country_code[0], ptr_country_code[0]); + status = A_OK; + pDCxt->asynchRequest = NULL; + // pDCxt->macProgramming = false; + DRIVER_WAKE_USER(pCxt); + + return status; +} +A_STATUS +Api_ProgramCountryCode(void *pCxt, uint8_t *country_code, uint16_t length, uint8_t *pResult) +{ + A_STATUS status = A_ERROR; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + boolean countryCodeProgram = true; + /* init pResult to an error code of 0 */ + *pResult = ATH_PROGRAM_COUNTRY_CODE_RESULT_DRIVER_FAILED; + + do + { + if (length != sizeof(ATH_PROGRAM_COUNTRY_CODE_PARAM)) + { + break; + } + + if (Api_DriverAccessCheck(pCxt, 0, ACCESS_REQUEST_IOCTL) != A_OK) + { + break; + } + + if (pDCxt->asynchRequest != NULL) + { + break; + } + /* use the reqBssid as storage for the country code. the Program_CountryCode + * function will retrieve this value for use in the operation. + */ + // A_MEMCPY(pDCxt->conn[pDCxt->devId].reqBssid, country_code, 3); + A_MEMCPY(&countryCode_storge[1], country_code, 3); + + QCADRV_PRINTF("api_ioctl countryCode_storge is %c,%c.\n", countryCode_storge[1], countryCode_storge[2]); + pDCxt->asynchRequest = Program_CountryCode; + DRIVER_WAKE_DRIVER(pCxt); + DRIVER_WAIT_FOR_CONDITION(pCxt, &countryCodeProgram, false, 5000); + + switch (countryCode_storge[0]) + { + case 1: /*successful result*/ + *pResult = ATH_PROGRAM_COUNTRY_CODE_RESULT_SUCCESS; + break; + case 2: /* device failed in the attempt */ + *pResult = ATH_PROGRAM_COUNTRY_CODE_RESULT_DEV_DENIED; + break; + case 4: /* the same country is already programmed */ + case 8: /* the device rejected the mac address */ + *pResult = ATH_PROGRAM_COUNTRY_CODE_RESULT_DEV_FAILED; + break; + case 0: /* driver failure to communicate with device */ + default: + break; + } + Api_InitFinish(pCxt); + Api_WMIInitFinish(pCxt); + status = A_OK; + + } while (0); + + A_MEMZERO(pDCxt->conn[pDCxt->devId].reqBssid, sizeof(pDCxt->conn[pDCxt->devId].reqBssid)); + + return status; +} + +#if DRIVER_CONFIG_PROGRAM_MAC_ADDR +/*****************************************************************************/ +/* program_mac_addr - Used to program a new mac address into the attached + * wifi device. the mac address is in pDCxt->reqBssid. Special firmware + * is loaded to perform the operation. the MAC address is provided to + * the firmware through the MBOX scratch registers. + * void *pCxt - the driver context. + *****************************************************************************/ +static A_STATUS program_mac_addr(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt; + A_STATUS status = A_ERROR; + uint32_t param; + uint8_t pass_cycle = 0; + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + uint32_t mac_word; + uint8_t *ptr_mac_word = (uint8_t *)&mac_word; + uint32_t i; + + A_NETBUF_CONFIGURE(pReq, &mac_word, 0, sizeof(uint32_t), sizeof(uint32_t)); + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* bring the chip down */ + pDCxt->wmiReady = false; + HW_PowerUpDown(pCxt, false); + /* bring the chip back up */ + HW_PowerUpDown(pCxt, true); + pDCxt->htc_creditInit = 0; + /* re-initialize host controller (sub-)driver = HCD */ + if ((status = Hcd_ReinitTarget(pCxt)) != A_OK) + { + A_ASSERT(0); + } + + if (pass_cycle == 0) + { + A_MDELAY(5); + /* wait for chip to reach point in initialization */ + do + { + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_refclk_hz)), (uint8_t *)¶m, + 4) != A_OK) + { + A_ASSERT(0); + } + } while (param != A_CPU2LE32(EXPECTED_REF_CLK_AR4100) && param != A_CPU2LE32(EXPECTED_REF_CLK_AR400X)); + /* on 1st pass the mac address is loaded into the + * scratch registers and the parameter is set to + * cause the firmware to read/program the mac address. + */ + ptr_mac_word[0] = 0; + ptr_mac_word[1] = 0; + A_MEMCPY(&ptr_mac_word[2], &pDCxt->conn[pDCxt->devId].reqBssid[0], 2); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, SCRATCH_ADDRESS, true, sizeof(uint32_t)); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + A_ASSERT(0); + } + + A_MEMCPY(&ptr_mac_word[0], &pDCxt->conn[pDCxt->devId].reqBssid[2], 4); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, SCRATCH_ADDRESS + 4, true, sizeof(uint32_t)); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + A_ASSERT(0); + } + A_MDELAY(5); + param = A_CPU2LE32(AR4XXX_PARAM_MACPROG_MODE); + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_flash_is_present)), + (uint8_t *)¶m, 4) != A_OK) + { + A_ASSERT(0); + } + /* wait some sufficient number of attempts before giving up. */ + for (i = 0; i < 100; i++) + { + /* poll scratch register for indication of completion */ + ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, SCRATCH_ADDRESS, true, sizeof(uint32_t)); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + A_ASSERT(0); + } + QCADRV_PRINTF("ptr_mac_word[1] is %c.\n", ptr_mac_word[1]); + if (ptr_mac_word[1] != 0) + { + break; /* done - exit loop */ + } + /* delay 1 msec before polling again to give the op time to complete */ + A_MDELAY(1); + } + } + else + { + /* on 2nd pass the chip is brought up normally */ + A_MDELAY(5); + Driver_BootComm(pCxt); + pDCxt->chipDown = false; + } + + pass_cycle++; + } while (pass_cycle < 2); + + if (pass_cycle >= 2) + { + /* store result in reqBssid for use in calling function */ + pDCxt->conn[pDCxt->devId].reqBssid[0] = ptr_mac_word[1]; + } + else + { + pDCxt->conn[pDCxt->devId].reqBssid[0] = 0; + } + status = A_OK; + pDCxt->asynchRequest = NULL; + pDCxt->macProgramming = false; + DRIVER_WAKE_USER(pCxt); + + return status; +} +#endif /* DRIVER_CONFIG_PROGRAM_MAC_ADDR */ + +/*****************************************************************************/ +/* Install_static_wep_keys - Used to install WEP keys to the device at the + * appropriate time. + * void *pCxt - the driver context. + *****************************************************************************/ +static void Install_static_wep_keys(void *pCxt) +{ + uint8_t index; + uint8_t keyUsage; + A_DRIVER_CONTEXT *pDCxt; + WMI_ADD_CIPHER_KEY_CMD add_key_param; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) + { + if (pDCxt->conn[pDCxt->devId].wepKeyList[index].keyLen) + { + keyUsage = GROUP_USAGE; + if (index == pDCxt->conn[pDCxt->devId].wepDefTxKeyIndex) + { + keyUsage |= TX_USAGE; + } + + A_MEMZERO(&add_key_param, sizeof(add_key_param)); + add_key_param.keyIndex = index; + add_key_param.keyType = WEP_CRYPT; + add_key_param.keyUsage = keyUsage; + add_key_param.keyLength = pDCxt->conn[pDCxt->devId].wepKeyList[index].keyLen; + A_MEMCPY(&add_key_param.key, pDCxt->conn[pDCxt->devId].wepKeyList[index].key, add_key_param.keyLength); + add_key_param.key_op_ctrl = KEY_OP_INIT_VAL; + wmi_cmd_start(pDCxt->pWmiCxt, &add_key_param, WMI_ADD_CIPHER_KEY_CMDID, sizeof(WMI_ADD_CIPHER_KEY_CMD)); + } + } +} + +/*****************************************************************************/ +/* Api_DisconnectWiFi - Called by upper layer to disconnect a network + * connection. Executes wmi_Disconnnect_cmd + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Api_DisconnectWiFi(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + if ((pDCxt->conn[pDCxt->devId].isConnected == true) || (pDCxt->conn[pDCxt->devId].isConnectPending == true)) + { + wmi_cmd_start(pDCxt->pWmiCxt, NULL, WMI_DISCONNECT_CMDID, 0); + /* + * Disconnect cmd is issued, clear connectPending. + * arConnected will be cleard in disconnect_event notification. + */ + pDCxt->conn[pDCxt->devId].isConnectPending = false; + /* + * clear connect state so that subsequent connect commands start with same + * initial configuration every time. + */ + pDCxt->conn[pDCxt->devId].dot11AuthMode = OPEN_AUTH; + pDCxt->conn[pDCxt->devId].wpaAuthMode = NONE_AUTH; + pDCxt->conn[pDCxt->devId].wpaPairwiseCrypto = pDCxt->conn[pDCxt->devId].wpaGroupCrypto = NONE_CRYPT; + pDCxt->conn[pDCxt->devId].wpaPairwiseCryptoLen = pDCxt->conn[pDCxt->devId].wpaGroupCryptoLen = 0; + A_MEMZERO(pDCxt->conn[pDCxt->devId].reqBssid, sizeof(pDCxt->conn[pDCxt->devId].reqBssid)); + pDCxt->conn[pDCxt->devId].channelHint = 0; + pDCxt->conn[pDCxt->devId].connectCtrlFlags = 0; + } + + return A_OK; +} + +/*****************************************************************************/ +/* Api_ConnectWiFi - Called by upper layer to start a network connection + * operation. Executes wmi_connnect_cmd + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Api_ConnectWiFi(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt; + A_STATUS status = A_OK; + WMI_CONNECT_CMD conn_cmd = {0}; + WMI_SCAN_PARAMS_CMD scan_param_cmd; + uint8_t devId; + + pDCxt = GET_DRIVER_COMMON(pCxt); + devId = pDCxt->devId; + /* The ssid length check prevents second "essid off" from the user, + to be treated as a connect cmd. The second "essid off" is ignored. + */ + if ((pDCxt->wmiReady == true) && (pDCxt->conn[devId].ssidLen > 0) && pDCxt->conn[devId].networkType != AP_NETWORK) + { + if (/*(ADHOC_NETWORK != ar->arNetworkType) &&*/ // Allow wep key installation in AD-HOC mode + (NONE_AUTH == pDCxt->conn[pDCxt->devId].wpaAuthMode) && + (WEP_CRYPT == pDCxt->conn[pDCxt->devId].wpaPairwiseCrypto)) + { + Install_static_wep_keys(pCxt); + } + /* set scan ctrl flags to default. this will ensure that the firmware will scan for + * an appropriate AP during connect operation. All params that are zero will remain + * unchanged from their pre existing value. If WPS had been previously used it would + * have set the scan ctrl flags in such a way that a subsequent connect might fail. + * This wmi_scanparams_cmd() fixes that issue. + */ + do + { + A_MEMCPY(&scan_param_cmd, &pDCxt->scan_param, sizeof(WMI_SCAN_PARAMS_CMD)); + scan_param_cmd.bg_period = pDCxt->scan_param.bg_period = A_CPU2LE16(0xffff); + if (A_OK != + wmi_cmd_start(pDCxt->pWmiCxt, &scan_param_cmd, WMI_SET_SCAN_PARAMS_CMDID, sizeof(WMI_SCAN_PARAMS_CMD))) + { + break; + } + else + { + WAIT_FOR_WMI_RESPONSE(pCxt); + } + + if (pDCxt->conn[devId].ssidLen) + { + A_MEMCPY(conn_cmd.ssid, pDCxt->conn[devId].ssid, pDCxt->conn[devId].ssidLen); + } + + conn_cmd.ssidLength = pDCxt->conn[devId].ssidLen; + conn_cmd.networkType = pDCxt->conn[devId].networkType; + conn_cmd.dot11AuthMode = pDCxt->conn[devId].dot11AuthMode; + conn_cmd.authMode = pDCxt->conn[devId].wpaAuthMode; + conn_cmd.pairwiseCryptoType = pDCxt->conn[devId].wpaPairwiseCrypto; + conn_cmd.pairwiseCryptoLen = pDCxt->conn[devId].wpaPairwiseCryptoLen; + conn_cmd.groupCryptoType = pDCxt->conn[devId].wpaGroupCrypto; + conn_cmd.groupCryptoLen = pDCxt->conn[devId].wpaGroupCryptoLen; + conn_cmd.channel = A_CPU2LE16(pDCxt->conn[devId].channelHint); + conn_cmd.ctrl_flags = A_CPU2LE32(pDCxt->conn[devId].connectCtrlFlags); + + //NOTE: coverity fix + A_MEMCPY(conn_cmd.bssid, pDCxt->conn[devId].reqBssid, ATH_MAC_LEN); + + status = wmi_cmd_start(pDCxt->pWmiCxt, (void *)&conn_cmd, WMI_CONNECT_CMDID, sizeof(WMI_CONNECT_CMD)); + + if (status != A_OK) + { + break; + } + else + { + WAIT_FOR_WMI_RESPONSE(pCxt); + } + + pDCxt->conn[pDCxt->devId].isConnectPending = true; + } while (0); + + return status; + } +#if ENABLE_AP_MODE + else if (pDCxt->wmiReady == true && pDCxt->conn[pDCxt->devId].networkType == AP_NETWORK) + { + if ((NONE_AUTH == pDCxt->conn[pDCxt->devId].wpaAuthMode) && + (WEP_CRYPT == pDCxt->conn[pDCxt->devId].wpaPairwiseCrypto)) + { + Install_static_wep_keys(pCxt); + } + A_MEMCPY(conn_cmd.ssid, (uint8_t *)pDCxt->conn[devId].ssid, sizeof(conn_cmd.ssid)); + conn_cmd.ssidLength = (int)pDCxt->conn[devId].ssidLen; + conn_cmd.pairwiseCryptoLen = (uint8_t)pDCxt->conn[devId].wpaPairwiseCryptoLen; + conn_cmd.groupCryptoLen = (uint8_t)pDCxt->conn[devId].wpaGroupCryptoLen; + conn_cmd.networkType = pDCxt->conn[devId].networkType; + conn_cmd.dot11AuthMode = pDCxt->conn[devId].dot11AuthMode; + conn_cmd.authMode = pDCxt->conn[devId].wpaAuthMode; + conn_cmd.pairwiseCryptoType = pDCxt->conn[devId].wpaPairwiseCrypto; + conn_cmd.groupCryptoType = pDCxt->conn[devId].wpaGroupCrypto; + + conn_cmd.ctrl_flags = (pDCxt->apmodeWPS) ? A_CPU2LE32(pDCxt->conn[devId].connectCtrlFlags | CONNECT_WPS_FLAG) : + A_CPU2LE32(pDCxt->conn[devId].connectCtrlFlags); + conn_cmd.channel = A_CPU2LE16(pDCxt->conn[devId].channelHint); + + status = wmi_cmd_start(pDCxt->pWmiCxt, (void *)&conn_cmd, WMI_AP_CONFIG_COMMIT_CMDID, sizeof(WMI_CONNECT_CMD)); + return status; + } +#endif /* ENABLE_AP_MODE */ + + return A_ERROR; +} + +static uint8_t wpa_auth_parse(uint8_t *sel) +{ +#define WPA_SEL(x) (((x) << 24) | WPA_OUI) + uint32_t w = A_LE_READ_4(sel); + + switch (w) + { + case WPA_SEL(WPA_ASE_8021X_UNSPEC): + return WPA_AUTH; + case WPA_SEL(WPA_ASE_8021X_PSK): + return WPA_PSK_AUTH; + case WPA_SEL(WPA_ASE_NONE): + return NONE_AUTH; + } + + return 0; +#undef WPA_SEL +} + +static uint8_t wpa_cipher_parse(uint8_t *sel, uint8_t *keylen) +{ +#define WPA_SEL(x) (((x) << 24) | WPA_OUI) + uint32_t w = A_LE_READ_4(sel); + + switch (w) + { + case WPA_SEL(WPA_CSE_NULL): + return NONE_CRYPT; + case WPA_SEL(WPA_CSE_WEP40): + if (keylen) + *keylen = 40 >> 3; // 40/bits_per_byte + return WEP_CRYPT; + case WPA_SEL(WPA_CSE_WEP104): + if (keylen) + *keylen = 104 >> 3; // 104/bits_per_byte + return WEP_CRYPT; + case WPA_SEL(WPA_CSE_TKIP): + return TKIP_CRYPT; + case WPA_SEL(WPA_CSE_CCMP): + return AES_CRYPT; + } + + return 0; +#undef WPA_SEL +} + +static CRYPTO_TYPE rsn_cipher_parse(uint8_t *sel, uint8_t *keylen) +{ +#define RSN_SEL(x) (((x) << 24) | RSN_OUI) + uint32_t w = A_LE_READ_4(sel); + + switch (w) + { + case RSN_SEL(RSN_CSE_NULL): + return NONE_CRYPT; + case RSN_SEL(RSN_CSE_WEP40): + if (keylen) + *keylen = 40 >> 3; // 40/bits_per_byte + return WEP_CRYPT; + case RSN_SEL(RSN_CSE_WEP104): + if (keylen) + *keylen = 104 >> 3; // 104/bits_per_byte + return WEP_CRYPT; + case RSN_SEL(RSN_CSE_TKIP): + return TKIP_CRYPT; + case RSN_SEL(RSN_CSE_CCMP): + return AES_CRYPT; + } + return NONE_CRYPT; +#undef RSN_SEL +} + +static uint8_t rsn_auth_parse(uint8_t *sel) +{ +#define RSN_SEL(x) (((x) << 24) | RSN_OUI) + uint32_t w = A_LE_READ_4(sel); + + switch (w) + { + case RSN_SEL(RSN_ASE_8021X_UNSPEC): + return WPA2_AUTH; + case RSN_SEL(RSN_ASE_8021X_PSK): + return WPA2_PSK_AUTH; + case RSN_SEL(RSN_ASE_NONE): + return NONE_AUTH; + } + + return 0; +#undef RSN_SEL +} + +static void security_ie_parse(uint8_t *pie, uint8_t ie_len, uint8_t *pResult, uint8_t ie_type) +{ + uint16_t cnt; + uint16_t i; + uint8_t wepKeyLen; + /* skip mcast cipher */ + if (ie_len >= 4) + { + ie_len -= 4; + pie += 4; + } + /* examine ucast cipher(s) */ + if (ie_len > 2) + { + cnt = A_LE_READ_2(pie); + ie_len -= 2; + pie += 2; + + for (i = 0; ((i < cnt) && (ie_len > 0)); i++) + { + if (ie_type == IEEE80211_ELEMID_RSN) + { + pResult[0] |= rsn_cipher_parse(pie, &wepKeyLen); + } + else + { + pResult[0] |= wpa_cipher_parse(pie, &wepKeyLen); + } + + ie_len -= 4; + pie += 4; + } + } + else + { + /* assume default TKIP for wpa */ + pResult[0] |= (ie_type == IEEE80211_ELEMID_RSN) ? AES_CRYPT : TKIP_CRYPT; + } + /* parse auth types */ + if (ie_len > 2) + { + cnt = A_LE_READ_2(pie); + ie_len -= 2; + pie += 2; + + for (i = 0; ((i < cnt) && (ie_len > 0)); i++) + { + if (ie_type == IEEE80211_ELEMID_RSN) + { + pResult[1] |= rsn_auth_parse(pie); + } + else + { + pResult[1] |= wpa_auth_parse(pie); + } + + ie_len -= 4; + pie += 4; + } + } + else + { + pResult[1] |= (ie_type == IEEE80211_ELEMID_RSN) ? WPA2_AUTH : WPA_AUTH; + } +} + +A_STATUS +Api_ParseInfoElem(void *pCxt, WMI_BSS_INFO_HDR *bih, int32_t len, A_SCAN_SUMMARY *pSummary) +{ + uint8_t *buf; + uint8_t *pie, *pieEnd, *pieTemp; + uint8_t ie_result[2]; + uint16_t ie_len; + + A_MEMZERO(pSummary, sizeof(A_SCAN_SUMMARY)); + + pSummary->channel = (uint8_t)Util_Freq2ieee(bih->channel); + pSummary->rssi = bih->snr; /* snr is a value from 0 -> 95 where 95 is a strong signal */ + A_MEMCPY(pSummary->bssid, bih->bssid, ATH_MAC_LEN); + + if ((uint32_t)len < sizeof(WMI_BSS_INFO_HDR) + IE_INDEX) + { + return A_ERROR; + } + + buf = (uint8_t *)(bih + 1); + len -= sizeof(WMI_BSS_INFO_HDR); + + pSummary->caps = (uint16_t)((uint16_t)buf[CAPS_IE_INDEX] | (uint16_t)(buf[CAPS_IE_INDEX + 1] << 8)); + pSummary->beacon_period = + (uint16_t)((uint16_t)buf[BEACON_PERIOD_IE_INDEX] | (uint16_t)(buf[BEACON_PERIOD_IE_INDEX + 1] << 8)); + /* loop through IE's to collect additional info */ + pie = &buf[IE_INDEX]; + len -= IE_INDEX; + pieEnd = &pie[len]; + + while (pie < pieEnd) + { + switch (*pie) + { + case IEEE80211_ELEMID_SSID: + if (pie[1] <= 32) + { + pSummary->ssid_len = pie[1]; + + if (pie[1]) + { + A_MEMCPY(pSummary->ssid, &pie[2], pie[1]); + } + } + break; + case IEEE80211_ELEMID_RSN: + /*******************/ + /* parse RSN IE */ + /*******************/ + ie_len = pie[1]; /* init ie_len - sizeof wpa_oui */ + pieTemp = &pie[2]; /* init pieTemp beyond wpa_oui */ + + if (A_LE_READ_2(pieTemp) != RSN_VERSION) + { + break; + } + ie_len -= 2; + pieTemp += 2; + ie_result[0] = ie_result[1] = 0; + + security_ie_parse(pieTemp, ie_len, &ie_result[0], IEEE80211_ELEMID_RSN); + pSummary->rsn_cipher = ie_result[0]; + pSummary->rsn_auth = ie_result[1]; + break; + case IEEE80211_ELEMID_VENDOR: + if (pie[1] > 6 && A_LE_READ_4(pie + 2) == ((WPA_OUI_TYPE << 24) | WPA_OUI)) + { + /*******************/ + /* parse WPA IE */ + /*******************/ + ie_len = pie[1] - 4; /* init ie_len - sizeof wpa_oui */ + pieTemp = &pie[6]; /* init pieTemp beyond wpa_oui */ + + if (A_LE_READ_2(pieTemp) != WPA_VERSION) + { + break; /* bad version */ + } + + ie_len -= 2; + pieTemp += 2; + ie_result[0] = ie_result[1] = 0; + + security_ie_parse(pieTemp, ie_len, &ie_result[0], IEEE80211_ELEMID_VENDOR); + pSummary->wpa_cipher = ie_result[0]; + pSummary->wpa_auth = ie_result[1]; + } + break; + } + + pie += pie[1] + 2; + } + + return A_OK; +} + +/*****************************************************************************/ +/* Api_DriverAccessCheck - Called by upper layer to confirm that the driver + * is in a State to allow IOCTL's and other requests. + * void *pCxt - the driver context. + * uint8_t block_allowed - caller can tolerate a task block if the + * check is not immediately satisfied. + * uint8_t request_reason - callers reason to request driver access. + *****************************************************************************/ +A_STATUS +Api_DriverAccessCheck(void *pCxt, uint8_t block_allowed, uint8_t request_reason) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + A_STATUS status = A_OK; + uint8_t blocked; + + UNUSED_ARGUMENT(request_reason); + + do + { + blocked = 0; + /* if the chip is powered down when a tx operation is submitted + * then the policy is to wait for the chip to come back */ + if (true == pDCxt->chipDown) + { + blocked = 1; + + if (block_allowed == 0) + { + /* caller forbids blocking so return A_ERROR */ + status = A_ERROR; + break; + } + + do + { + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->chipDown), false, 5000); + } while (true == pDCxt->chipDown); + } +#if DRIVER_CONFIG_ENABLE_STORE_RECALL + /*Check str-rcl state only if applications requests it*/ + if (request_reason != ACCESS_REQUEST_RX) + { + /* if a strrcl command is in process all ioctl's and tx operations + * must be blocked/deferred until it completes. + */ + if (true == pDCxt->strrclBlock) + { + blocked = 1; + + if (block_allowed == 0) + { + /* caller forbids blocking so return A_ERROR */ + status = A_ERROR; + break; + } + + do + { + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->strrclBlock), false, 5000); + } while (true == pDCxt->strrclBlock); + } + } +#endif + + } while (blocked); /* loop until all conditions are met at one pass */ + + return status; +} + +#if DRIVER_CONFIG_PROGRAM_MAC_ADDR +A_STATUS +Api_ProgramMacAddress(void *pCxt, uint8_t *addr, uint16_t length, uint8_t *pResult) +{ + A_STATUS status = A_ERROR; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + /* init pResult to an error code of 0 */ + *pResult = ATH_PROGRAM_MAC_RESULT_DRIVER_FAILED; + + do + { + if (length != sizeof(ATH_PROGRAM_MAC_ADDR_PARAM)) + { + break; + } + + if (Api_DriverAccessCheck(pCxt, 0, ACCESS_REQUEST_IOCTL) != A_OK) + { + break; + } + + if (pDCxt->asynchRequest != NULL) + { + break; + } + /* use the reqBssid as storage for the mac address. the program_mac_addr + * function will retrieve this value for use in the operation. + */ + A_MEMCPY(pDCxt->conn[pDCxt->devId].reqBssid, addr, sizeof(pDCxt->conn[pDCxt->devId].reqBssid)); + pDCxt->macProgramming = true; + pDCxt->asynchRequest = program_mac_addr; + DRIVER_WAKE_DRIVER(pCxt); + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->macProgramming), false, 5000); + + if (pDCxt->macProgramming == false) + { + switch (pDCxt->conn[pDCxt->devId].reqBssid[0]) + { + case 1: /*successful result*/ + *pResult = ATH_PROGRAM_MAC_RESULT_SUCCESS; + break; + case 2: /* device failed in the attempt */ + *pResult = ATH_PROGRAM_MAC_RESULT_DEV_FAILED; + break; + case 4: /* the same mac address is already programmed */ + case 8: /* the device rejected the mac address */ + *pResult = ATH_PROGRAM_MAC_RESULT_DEV_DENIED; + break; + case 0: /* driver failure to communicate with device */ + default: + break; + } + + Api_InitFinish(pCxt); + Api_WMIInitFinish(pCxt); + status = A_OK; + } + + } while (0); + + A_MEMZERO(pDCxt->conn[pDCxt->devId].reqBssid, sizeof(pDCxt->conn[pDCxt->devId].reqBssid)); + + return status; +} +#endif /* DRIVER_CONFIG_PROGRAM_MAC_ADDR */ +A_STATUS +Api_SetPowerMode(void *pCxt, POWER_MODE *app_setting) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + if (app_setting->pwr_module < PWR_MAX) + { + (app_setting->pwr_mode == REC_POWER) ? (pDCxt->pwrStateSetting &= ~(1 << app_setting->pwr_module)) : + (pDCxt->pwrStateSetting |= (1 << app_setting->pwr_module)); + } + /* Set MAX Perf */ + if ((app_setting->pwr_mode == MAX_PERF_POWER) && (pDCxt->userPwrMode == REC_POWER)) + { + pDCxt->userPwrMode = MAX_PERF_POWER; + } + /* Set REC Power */ + if ((app_setting->pwr_mode == REC_POWER) && (pDCxt->pwrStateSetting == 0x00)) + { + pDCxt->userPwrMode = REC_POWER; + } + QCADRV_PRINTF("Power Mode : %x,%d,%d \n", pDCxt->pwrStateSetting, app_setting->pwr_mode, app_setting->pwr_module); + if (A_OK != + wmi_cmd_start(pDCxt->pWmiCxt, &pDCxt->userPwrMode, WMI_SET_POWER_MODE_CMDID, sizeof(WMI_POWER_MODE_CMD))) + { + return A_ERROR; + } + + if ((app_setting->pwr_mode == REC_POWER) && pDCxt->userPwrMode == MAX_PERF_POWER) + { + QCADRV_PRINTF("Device will remain MAX_PERF \n"); + } + return A_OK; +} + +#if !ENABLE_STACK_OFFLOAD +extern const uint8_t max_performance_power_param; +int32_t power_state_for_module = 0; +/*****************************************************************************/ +/* move_to_maxperf - Changes the power mode to max perf in firmware. There are + * some commands which need to run in MAX_PERF mode like store_recall etc + * This function changes the power modeto MAX_PERF and will not + * intimate the application. Later after the command succeeds, + * use restore_power_state to change to original power state + * Note: Application should not directly use this function + * int32_t - module which request the change + * Returns- A_OK on success, A_ERROR otherwise + *****************************************************************************/ +A_STATUS move_power_state_to_maxperf(void *pCxt, int32_t module) +{ + A_DRIVER_CONTEXT *pDCxt = (A_DRIVER_CONTEXT *)pCxt; + + /* Already some HIGH module changes state */ + if (power_state_for_module >= module) + { + return A_OK; + } + + /* Change the power mode only when the current power mode is REC_POWER */ + if (pDCxt->userPwrMode == REC_POWER) + { + if (A_OK != wmi_cmd_start(pDCxt->pWmiCxt, &max_performance_power_param, WMI_SET_POWER_MODE_CMDID, + sizeof(WMI_POWER_MODE_CMD))) + { + return A_ERROR; + } + } + power_state_for_module = module; + return A_OK; +} +#endif +A_STATUS wait_scan_done(void *pCxt, void *pWmi) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + if (pDCxt->scanDone == false) + { + /* block until scan completes */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->scanDone), true, 5000); + + if (pDCxt->scanDone == false) + { + wmi_bssfilter_cmd(pWmi, NONE_BSS_FILTER, 0); + } + return A_ERROR; + } + pDCxt->scanDone = false; + return A_OK; +} + +A_STATUS scan_setup(void *pCxt, void *pWmi, WMI_START_SCAN_CMD *start_scan) +{ + union + { + WMI_START_SCAN_CMD scan_cmd; + WMI_PROBED_SSID_CMD probeParam; + } stackU; + A_STATUS error = A_OK; + uint32_t size; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + if (pDCxt->conn[pDCxt->devId].ssidLen > 0) + { + /* apply filter ssid */ + stackU.probeParam.entryIndex = 1; + stackU.probeParam.flag = SPECIFIC_SSID_FLAG; + stackU.probeParam.ssidLength = pDCxt->conn[pDCxt->devId].ssidLen; + A_MEMCPY(stackU.probeParam.ssid, pDCxt->conn[pDCxt->devId].ssid, pDCxt->conn[pDCxt->devId].ssidLen); + + if (A_OK != wmi_cmd_start(pWmi, &stackU.probeParam, WMI_SET_PROBED_SSID_CMDID, sizeof(WMI_PROBED_SSID_CMD))) + { + error = A_ERROR; + break; + } + + if (A_OK != wmi_bssfilter_cmd(pWmi, PROBED_SSID_FILTER, 0)) + { + error = A_ERROR; + break; + } + } + else + { + /* clear any pre-existing filter ssid */ + stackU.probeParam.entryIndex = 1; + stackU.probeParam.flag = DISABLE_SSID_FLAG; + stackU.probeParam.ssidLength = 0; + + if (A_OK != wmi_cmd_start(pWmi, &stackU.probeParam, WMI_SET_PROBED_SSID_CMDID, sizeof(WMI_PROBED_SSID_CMD))) + { + error = A_ERROR; + break; + } + + if (A_OK != wmi_bssfilter_cmd(pWmi, ALL_BSS_FILTER, 0)) + { + error = A_ERROR; + break; + } + } + + GET_DRIVER_COMMON(pCxt)->scanOutSize = ATH_MAX_SCAN_BUFFERS; + GET_DRIVER_COMMON(pCxt)->scanOutCount = 0; + pDCxt->scanDone = false; + /* start the scan */ + if (start_scan == NULL) + { + A_MEMZERO(&stackU.scan_cmd, sizeof(WMI_START_SCAN_CMD)); + stackU.scan_cmd.scanType = WMI_LONG_SCAN; + stackU.scan_cmd.forceFgScan = false; + stackU.scan_cmd.isLegacy = false; + stackU.scan_cmd.homeDwellTime = 0; + stackU.scan_cmd.forceScanInterval = 1; + stackU.scan_cmd.numChannels = 0; + if (A_OK != wmi_cmd_start(pWmi, (void *)&stackU.scan_cmd, WMI_START_SCAN_CMDID, sizeof(WMI_START_SCAN_CMD))) + { + error = A_ERROR; + } + } + else + { + size = sizeof(WMI_START_SCAN_CMD); + if (start_scan->numChannels > 0) + { + size = size + (start_scan->numChannels - 1) * sizeof(uint16_t); + } + + if (A_OK != wmi_cmd_start(pWmi, (void *)start_scan, WMI_START_SCAN_CMDID, size)) + { + error = A_ERROR; + } + } + + } while (0); + + return error; +} + +uint8_t Util_Ascii2Hex(char val) +{ + if ('0' <= val && '9' >= val) + { + return (uint8_t)(val - '0'); + } + else if ('a' <= val && 'f' >= val) + { + return (uint8_t)((val - 'a') + 0x0a); + } + else if ('A' <= val && 'F' >= val) + { + return (uint8_t)((val - 'A') + 0x0a); + } + + return 0xff; /* error */ +} + +A_STATUS +TxRawPacket(void *pCxt, void *pReq, ATH_MAC_TX_PARAMS *pParams) +{ + WMI_TX_META_V3 v3_meta; + HTC_ENDPOINT_ID eid; + A_DRIVER_CONTEXT *pDCxt; + A_STATUS status = A_ERROR; + + eid = Util_AC2EndpointID(pCxt, WMM_AC_BE); + A_NETBUF_SET_ELEM(pReq, A_REQ_EPID, eid); + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* translate from ATH_MAC_TX_PARAMS to WMI_TX_META_V3 */ + /* how convenient the values are all the same */ + v3_meta.pktID = pParams->pktID; + A_MEMCPY(&v3_meta.rateSched.rateSeries, &pParams->rateSched.rateSeries, + sizeof(uint8_t) * WMI_TX_MAX_RATE_SERIES); + A_MEMCPY(&v3_meta.rateSched.trySeries, &pParams->rateSched.trySeries, sizeof(uint8_t) * WMI_TX_MAX_RATE_SERIES); + v3_meta.rateSched.flags = pParams->rateSched.flags; + v3_meta.rateSched.accessCategory = pParams->rateSched.accessCategory; + + if (wmi_data_hdr_add(pDCxt->pWmiCxt, pReq, DATA_MSGTYPE, false, WMI_DATA_HDR_DATA_TYPE_802_11, + WMI_META_VERSION_3, (void *)&v3_meta) != A_OK) + { + break; + } + A_MDELAY(2); + /* HTC interface is asynchronous, if this fails, cleanup will happen in + * the ar6000_tx_complete callback */ + if (A_OK != Driver_SubmitTxRequest((void *)pCxt, pReq)) + { + A_NETBUF_FREE(pReq); + break; + } + + status = A_OK; + } while (0); + + return status; +} + +/* EOF */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_txrx.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_txrx.c new file mode 100644 index 00000000000..5ce8e752994 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_txrx.c @@ -0,0 +1,446 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "wifi_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*****************************************************************************/ +/* query_credit_deficit - Executed by the driver task to satisfy the + * Api_TxGetStatus() request. It will query the wifi credit counters on + * the Wifi device as needed to get the most up-to-date tx credit status. + * void *pCxt - the driver context. + *****************************************************************************/ +static A_STATUS query_credit_deficit(void *pCxt) +{ + uint32_t reg; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + if ((pDCxt->booleans & (SDHD_BOOL_FATAL_ERROR | SDHD_BOOL_DMA_IN_PROG | SDHD_BOOL_DMA_WRITE_WAIT_FOR_BUFFER))) + { + break; + } + + reg = Htc_ReadCreditCounter(pCxt, 1); + pDCxt->txQueryResult = (reg & 0x80000000) ? 1 : 0; + } while (0); + + pDCxt->asynchRequest = NULL; + pDCxt->txQueryInProgress = false; + DRIVER_WAKE_USER(pCxt); + return A_OK; +} + +/*****************************************************************************/ +/* Api_TxGetStatus - Learns the status regarding any TX requests. it will + * test the state of the driver first to learn if any TX requests are + * remaining on the host side. if none then it will test the state of + * the HTC credits to learn if any TX requests are still being processed + * by the WIFI device. If none then the function will return the idle + * status. + * void *pCxt - the driver context. + *****************************************************************************/ +uint16_t Api_TxGetStatus(void *pCxt) +{ + uint16_t status = ATH_TX_STATUS_IDLE; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + if (0 != A_NETBUF_QUEUE_SIZE(&(pDCxt->txQueue)) || pDCxt->driver_state == DRIVER_STATE_TX_PROCESSING) + { + status = ATH_TX_STATUS_HOST_PENDING; + break; + } + /* Check the AR410X status */ + status = ATH_TX_STATUS_WIFI_PENDING; + /* set up driver operation to read credits from device */ + if (pDCxt->asynchRequest == NULL) + { + pDCxt->txQueryInProgress = true; + pDCxt->asynchRequest = query_credit_deficit; + DRIVER_WAKE_DRIVER(pCxt); + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->txQueryInProgress), false, 5000); + + if (pDCxt->txQueryInProgress == false) + { + if (pDCxt->txQueryResult == 0) + { + status = ATH_TX_STATUS_IDLE; + } + } + } + } while (0); + + return status; +} + +/*****************************************************************************/ +/* API_TxComplete - Brings a transmit packet to its final conclusion. The + * packet is either a data packet in which case it will be freed back to + * the caller, or it is a wmi command in which case it will freed. + * void *pCxt - the driver context. + * void *pReq - the packet. + *****************************************************************************/ +void Api_TxComplete(void *pCxt, void *pReq) +{ + /* some user tasks may have blocked until a transmit complete occurs + * these lines wake up these tasks. */ + GET_DRIVER_COMMON(pCxt)->tx_complete_pend = false; + DRIVER_WAKE_USER(pCxt); + + if (ath_custom_init.Api_TxComplete != NULL) + { + ath_custom_init.Api_TxComplete(pCxt, pReq); + return; + } + else + { + API_TXCOMPLETE(pCxt, pReq); + A_NETBUF_FREE(pReq); + } +} + +/*****************************************************************************/ +/* API_RxComplete - Brings a received packet to its final conclusion. The + * packet is either a data packet in which case it will be processed and + * sent to the network layer, or it is a wmi event in which case it will + * be delivered to the wmi layer. + * void *pCxt - the driver context. + * void *pReq - the packet. + *****************************************************************************/ +void Api_RxComplete(void *pCxt, void *pReq) +{ + A_STATUS status = A_OK; + uint16_t minHdrLen; + uint16_t packetLen; + uint8_t containsDot11Hdr = 0; + WMI_DATA_HDR *dhdr; +#if WLAN_CONFIG_11N_AGGR_SUPPORT +#if !ENABLE_STACK_OFFLOAD + ATH_MAC_HDR *mac_hdr; +#endif +#endif + uint8_t is_amsdu, is_acl_data_frame; +#if !ENABLE_STACK_OFFLOAD + uint16_t seq_no; + uint8_t tid; +#endif + uint8_t devId; + uint8_t meta_type; + HTC_ENDPOINT_ID ept = (HTC_ENDPOINT_ID)A_NETBUF_GET_ELEM(pReq, A_REQ_EPID); + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + /* take lock to protect buffer counts + * and adaptive power throughput state */ + + if (ath_custom_init.Api_RxComplete != NULL) + { + ath_custom_init.Api_RxComplete(pCxt, pReq); + return; + } + else + { + if (pDCxt->wmiEnabled == true) + { + if (ept == ENDPOINT_1) + { + /* + * this is a wmi control packet. + */ + wmi_control_rx(pDCxt->pWmiCxt, pReq); + } + else if (pDCxt->promiscuous_mode) + { + wmi_data_hdr_remove(pDCxt->pWmiCxt, pReq); + CUSTOM_DELIVER_FRAME(pCxt, pReq); + status = A_OK; + } + else + { + /* + * this is a data packet. + */ + dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(pReq); + packetLen = A_NETBUF_LEN(pReq); + dhdr->info2 = A_LE2CPU16(dhdr->info2); + dhdr->info3 = A_LE2CPU16(dhdr->info3); + is_acl_data_frame = (uint8_t)(WMI_DATA_HDR_GET_DATA_TYPE(dhdr) == WMI_DATA_HDR_DATA_TYPE_ACL); + + devId = WMI_DATA_HDR_GET_DEVID(dhdr); + + minHdrLen = MIN_HDR_LEN; + + /* In the case of AP mode we may receive NULL data frames + * that do not have LLC hdr. They are 16 bytes in size. + * Allow these frames in the AP mode. + * ACL data frames don't follow ethernet frame bounds for + * min length + */ + do + { + if ((pDCxt->conn[devId].networkType != AP_NETWORK && (packetLen < minHdrLen)) || + (packetLen > AR4100_MAX_RX_MESSAGE_SIZE)) + { + /* + * packet is too short or too long + */ + status = A_ERROR; + break; + } + else + { + is_amsdu = (uint8_t)WMI_DATA_HDR_IS_AMSDU(dhdr); +#if !ENABLE_STACK_OFFLOAD + tid = (uint8_t)WMI_DATA_HDR_GET_UP(dhdr); + seq_no = (uint16_t)(WMI_DATA_HDR_GET_SEQNO(dhdr)); +#endif + meta_type = (uint8_t)WMI_DATA_HDR_GET_META(dhdr); + containsDot11Hdr = (uint8_t)WMI_DATA_HDR_GET_DOT11(dhdr); + /* NOTE: rssi is not currently managed on a per peer basis. + * therefore, if multiple peers are sending packets to + * this radio the rssi will be averaged across all + * indiscriminately. + */ + /* simple averaging algorithm. 7/8 of original value is combined + * with 1/8 of new value unless original value is 0 in which case + * just adopt the new value as its probably the first in the + * connection. + */ + pDCxt->rssi = (int8_t)((pDCxt->rssi) ? (pDCxt->rssi * 7 + dhdr->rssi) >> 3 : dhdr->rssi); + wmi_data_hdr_remove(pDCxt->pWmiCxt, pReq); + + if (meta_type) + { + /* this code does not accept per frame + * meta data */ + A_ASSERT(0); + } + /* NWF: print the 802.11 hdr bytes */ + if (containsDot11Hdr) + { + /* this code does not accept dot11 headers */ + A_ASSERT(0); + } + else if (!is_amsdu && !is_acl_data_frame) + { + status = WMI_DOT3_2_DIX(pReq); + } + else + { + /* this code does not accept amsdu or acl data */ + A_ASSERT(0); + } + + if (status != A_OK) + { + /* Drop frames that could not be processed (lack of memory, etc.) */ + break; + } + +#if WLAN_CONFIG_11N_AGGR_SUPPORT +#if !ENABLE_STACK_OFFLOAD + mac_hdr = A_NETBUF_DATA(pReq); + /*Check if packet is multicast, if so, do not check for aggregation*/ + if ((mac_hdr->dstMac[0] & 0x01) == 0) + { + if (false == aggr_process_recv_frm(pDCxt->pAggrCxt, tid, seq_no, is_amsdu, (void **)&pReq)) + { + status = A_ERROR; + break; + } + } +#endif /* !ENABLE_STACK_OFFLOAD*/ +#endif /* WLAN_CONFIG_11N_AGGR_SUPPORT */ + CUSTOM_DELIVER_FRAME(pCxt, pReq); + status = A_OK; + } + } while (0); + + if (A_OK != status) + { + A_NETBUF_FREE(pReq); + } + } + } + else + { + A_NETBUF_FREE(pReq); + } + + return; + } +} + +/*****************************************************************************/ +/* API_WmiTxStart - Function used by WMI via A_WMI_CONTROL_TX() to send + * a WMI command. + * void *pCxt - the driver context. + * void *pReq - the packet. + *****************************************************************************/ +A_STATUS +Api_WmiTxStart(void *pCxt, void *pReq, HTC_ENDPOINT_ID eid) +{ + A_STATUS status = A_ERROR; + + do + { + A_NETBUF_SET_ELEM(pReq, A_REQ_EPID, eid); + + if (A_OK != Driver_SubmitTxRequest(pCxt, pReq)) + { + break; + } + + status = A_OK; + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Api_DataTxStart - Starts the process of transmitting a data packet (pReq). + * Various checks are performed to ensure the driver and device are ready + * to open the data path. A dot.3 header is pre-pended if necessary and a + * WMI_DATA_HDR is pre-pended. In a multi-threaded system this function is + * expected to be executed on a non-driver thread. + * void *pCxt - the driver context. + * void *pReq - the Transmit packet. + *****************************************************************************/ +A_STATUS +Api_DataTxStart(void *pCxt, void *pReq) +{ +#define AC_NOT_MAPPED 99 + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint8_t ac = AC_NOT_MAPPED; + HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED; + boolean bMoreData = false; + uint8_t dot11Hdr = WLAN_CONFIG_TX_DOT11_HDR; + A_STATUS status = A_ERROR; + WMI_TX_META_V5 ip_meta; + + do + { + /* If target is not associated */ + if ((false == pDCxt->conn[0].isConnected && false == pDCxt->conn[0].isConnectPending) +#if (WLAN_NUM_OF_DEVICES > 1) + && (false == pDCxt->conn[1].isConnected && false == pDCxt->conn[1].isConnectPending) +#endif + ) + { + break; + } + else if ((false == pDCxt->conn[0].isConnected) +#if (WLAN_NUM_OF_DEVICES > 1) + && (false == pDCxt->conn[1].isConnected) +#endif + ) + { + // block until connection completes. + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->conn[0].isConnected), true, 5000); + + if ((false == pDCxt->conn[0].isConnected) +#if (WLAN_NUM_OF_DEVICES > 1) + && (false == pDCxt->conn[1].isConnected) +#endif + ) + { + break; + } + } + + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_TX)) + { + break; + } + + if (pDCxt->wmiReady == false) + { + break; + } + + if (false == pDCxt->wmiEnabled) + { + break; + } + +/* add wmi_data_hdr to front of frame */ +#if ENABLE_STACK_OFFLOAD + if (wmi_data_hdr_add(pDCxt->pWmiCxt, pReq, DATA_MSGTYPE, bMoreData, + (dot11Hdr) ? WMI_DATA_HDR_DATA_TYPE_802_11 : WMI_DATA_HDR_DATA_TYPE_802_3, + WMI_META_VERSION_5, (void *)&ip_meta) != A_OK) + { + break; + } +#else + /* convert frame header */ + if (wmi_dix_2_dot3(pDCxt->pWmiCxt, pReq) != A_OK) + { + break; + } + + if (wmi_data_hdr_add(pDCxt->pWmiCxt, pReq, DATA_MSGTYPE, bMoreData, + (dot11Hdr) ? WMI_DATA_HDR_DATA_TYPE_802_11 : WMI_DATA_HDR_DATA_TYPE_802_3, 0, + NULL) != A_OK) + { + break; + } +#endif + /* get the stream mapping */ + ac = wmi_implicit_create_pstream(pDCxt->pWmiCxt, pReq, 0, pDCxt->wmmEnabled); + eid = Util_AC2EndpointID(pCxt, ac); + + if (eid && eid != ENDPOINT_UNUSED) + { + A_NETBUF_SET_ELEM(pReq, A_REQ_EPID, eid); + /* Submit for transmission to next layer */ + if (A_OK != Driver_SubmitTxRequest(pCxt, pReq)) + { + break; + } + } + else + { + break; + } + + status = A_OK; + } while (0); + + return status; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_wmi_rx.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_wmi_rx.c new file mode 100644 index 00000000000..6e50f0792df --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/api_interface/api_wmi_rx.c @@ -0,0 +1,1596 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "wifi_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include //IGX_UD_CHANGES +#include //IGX_UD_CHANGES +#include +#include + +#if ENABLE_P2P_MODE +#include "p2p.h" +#include "wmi.h" +#include "wmi_api.h" +#include "wmi_host.h" +// WPS_CREDENTIAL persistCredential; +// WMI_WPS_PROFILE_EVENT wpsProfEv; +#endif + +#include "dset.h" +#include "dset_api.h" + +extern const uint8_t max_performance_power_param; +extern const WMI_SCAN_PARAMS_CMD default_scan_param; + +/*****************************************************************************/ +/* Api_TargetStatsEvent - Processes WMI_REPORT_STATISTICS_EVENTID + * from the device. + * void *pCxt - the driver context. + * uint8_t *ptr - pointer to the stats buffer. + * uint32_t len - length of the ptr buffer. + *****************************************************************************/ +void Api_TargetStatsEvent(void *pCxt, uint8_t devId, uint8_t *ptr, uint32_t len) +{ + UNUSED_ARGUMENT(devId); + if (ptr != NULL && len != 0) + { + GET_DRIVER_COMMON(pCxt)->rssi = ((WMI_TARGET_STATS *)ptr)->cservStats.cs_snr; + } + GET_DRIVER_COMMON(pCxt)->rssiFlag = false; + API_TARGET_STATS_EVENT(pCxt, ptr, len); +} + +/*****************************************************************************/ +/* Api_RegDomainEvent - Processes WMI_REGDOMAIN_EVENTID from the device. + * void *pCxt - the driver context. + * uint32_t regCode - the encoded regulatory domain value. + *****************************************************************************/ +void Api_RegDomainEvent(void *pCxt, uint8_t devId, uint32_t regCode) +{ + UNUSED_ARGUMENT(devId); + // A_PRINTF("AR4XXX Reg Code = 0x%x\n", regCode); + GET_DRIVER_COMMON(pCxt)->regCode = regCode; + API_REGDOMAIN_EVENT(pCxt, regCode); +} + +/*****************************************************************************/ +/* Api_BitrateEvent - Processes WMI_BIT_RATE_REPLY from the device. + * void *pCxt - the driver context. + * int32_t rateKbps - the rate in Kbps used for recent transmission. + *****************************************************************************/ +void Api_BitrateEvent(void *pCxt, uint8_t devId, int32_t rateKbps) +{ + UNUSED_ARGUMENT(devId); + GET_DRIVER_COMMON(pCxt)->bitRate = rateKbps; + API_BITRATE_EVENT(pCxt, rateKbps); +} + +/*****************************************************************************/ +/* Api_GetBitRateEvent - Processes WMI_GET_BITRATE_CMDID from the device. + * void *pCxt - the driver context. + * uint8_t *datap - the rate index for recent transmission is in this pointer. + *****************************************************************************/ +void Api_GetBitRateEvent(void *pCxt, uint8_t devId, void *datap) +{ + UNUSED_ARGUMENT(devId); + CUSTOM_API_BITRATE_EVENT_TX(pCxt, devId, ((WMI_BIT_RATE_REPLY *)datap)->rateIndex); +} + +/*****************************************************************************/ +/* Api_ChannelListEvent - Processes a WMI_GET_CHANNEL_LIST_CMD from the device. + * This event will come when the host issues a WMI_GET_CHANNEL_LIST_CMD to + * the device to request a current channel list. + * void *pCxt - the driver context. + * int8_t numChan - number of channels in the list. + * uint16_t *chanList - array of numChan channels. + *****************************************************************************/ +void Api_ChannelListEvent(void *pCxt, uint8_t devId, int8_t numChan, void *chanList) +{ + uint16_t i; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + UNUSED_ARGUMENT(devId); + A_MEMCPY(pDCxt->channelList, chanList, numChan * sizeof(uint16_t)); + pDCxt->numChannels = numChan; + /* convert each channel to proper endianness */ + for (i = 0; i < pDCxt->numChannels; i++) + { + pDCxt->channelList[i] = A_LE2CPU16(pDCxt->channelList[i]); + } + + API_CHANNEL_LIST_EVENT(pCxt, pDCxt->numChannels, pDCxt->channelList); +} + +/*****************************************************************************/ +/* Api_ScanCompleteEvent - Processes a WMI_SCAN_COMPLETE_EVENTID from the device. + * These events will occur if the host has previously initiated a scan request. + * This event indicates the final conclusion of the scan operation. + * void *pCxt - the driver context. + * A_STATUS status - indicates the status of the scan operation. + *****************************************************************************/ +void Api_ScanCompleteEvent(void *pCxt, uint8_t devId, A_STATUS status) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + UNUSED_ARGUMENT(status); + UNUSED_ARGUMENT(devId); + + wmi_bssfilter_cmd(pDCxt->pWmiCxt, NONE_BSS_FILTER, 0); + /* host initiated scan */ + pDCxt->scanDone = true; + + Api_BootProfile(pCxt, BOOT_PROFILE_DONE_SCAN); + + API_SCAN_COMPLETE_EVENT(pCxt, status); +} + +/*****************************************************************************/ +/* Api_BssInfoEvent - Processes a WMI_BSS_INFO_EVENT from the device. These + * events will occur if the host has previously initiated a scan request + * void *pCxt - the driver context. + * uint8_t *datap - the original event buffer. + * int32_t len - the length of datap. + *****************************************************************************/ +void Api_BssInfoEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len) +{ + UNUSED_ARGUMENT(devId); + CUSTOM_API_BSS_INFO_EVENT(pCxt, datap, len); +} + +/*****************************************************************************/ +/* Api_TkipMicErrorEvent - Processes a TKIP error event from the device. This + * event can happen when the device is using TKIP security and it detects a + * decryption error. + * void *pCxt - the driver context. + * uint8_t keyid - the Key ID used when the error occurred. + * boolean ismcast - 1 if packet was multi-cast 0 otherwise. + *****************************************************************************/ +void Api_TkipMicErrorEvent(void *pCxt, uint8_t devId, uint8_t keyid, boolean ismcast) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + UNUSED_ARGUMENT(ismcast); + UNUSED_ARGUMENT(keyid); + UNUSED_ARGUMENT(devId); + pDCxt->tkipCountermeasures = 1; + POWER_MODE pwrmode; + pwrmode.pwr_mode = MAX_PERF_POWER; + pwrmode.pwr_module = TKIP; + + Api_SetPowerMode(pCxt, &pwrmode); + + /* receiving this event informs the host that the wifi device + * encountered 2 TKIP MIC errors within the restricted time span. + * consequently, to fullfill the TKIP countermeasure requirement the + * host must disconnect from the network and remain disconnected for + * the specified period. + */ + wmi_cmd_start(pDCxt->pWmiCxt, NULL, WMI_DISCONNECT_CMDID, 0); + /* can't use A_MDELAY here as the wmi_disconnect_cmd() will + * cause a disconnect_event which should get processed. */ + // A_MDELAY(IEEE80211_TKIP_COUNTERMEASURES_TIMEOUT_MSEC); + API_TKIP_MIC_ERROR_EVENT(pCxt, keyid, ismcast); +} + +/*****************************************************************************/ +/* Api_GetPmkEvent - Processes a WMI_GET_PMK_REPLY from the + * device. + * This event will come when the caller has previously sent a WMI_GET_PMC_CMD. + * The function stores the result in wpaPmk for asynchronous access. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + *****************************************************************************/ +void Api_GetPmkEvent(void *pCxt, uint8_t devId, uint8_t *datap) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + WMI_GET_PMK_REPLY *pReply = (WMI_GET_PMK_REPLY *)datap; + + A_MEMCPY(pDCxt->conn[devId].wpaPmk, pReply->pmk, WMI_PMK_LEN); + pDCxt->conn[devId].wpaPmkValid = true; + API_GET_PMK_EVENT(pCxt, datap); +} + +/*****************************************************************************/ +/* Api_ConnectEvent - Processes a WMI_CONNECT_EVENT from the + * device. + * This event will come when the device has connected to a BSS + * network. + * void *pCxt - the driver context. + * uint16_t channel - RF channel on which connection exists. + * uint8_t *bssid - bssid address of the network. + * uint16_t listenInterval - assigned listen interval for sleep mode. + * uint16_t beaconInterval - BSS beacon interval. + * NETWORK_TYPE networkType - identifies the type of network. + * uint8_t beaconIeLen - length of beacon Information element. + * uint8_t assocReqLen - length of assocation request frame. + * uint8_t assocRespLen - length of assocation response length. + * uint8_t *assocInfo - pointer to assocation frame(s). + *****************************************************************************/ +void Api_ConnectEvent(void *pCxt, + uint8_t devId, + uint16_t channel, + uint8_t *bssid, + uint16_t listenInterval, + uint16_t beaconInterval, + NETWORK_TYPE networkType, + uint8_t beaconIeLen, + uint8_t assocReqLen, + uint8_t assocRespLen, + uint8_t *assocInfo) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + A_WEPKEY_T *pKey; + WMI_ADD_CIPHER_KEY_CMD add_key_param; + + UNUSED_ARGUMENT(listenInterval); + UNUSED_ARGUMENT(beaconInterval); + UNUSED_ARGUMENT(beaconIeLen); + UNUSED_ARGUMENT(assocReqLen); + UNUSED_ARGUMENT(assocRespLen); + UNUSED_ARGUMENT(assocInfo); + + /* In SoftAP mode, we will get connect event first time when we start as AP and then whenever a station connects to + * us. + * We should not set the channel and bssid, when the later connect event comes. + * The later connect event has network type as 0. + */ + if (networkType != 0) + { + A_MEMCPY(pDCxt->conn[devId].bssid, bssid, ATH_MAC_LEN); + pDCxt->conn[devId].bssChannel = channel; + } + + if ((networkType & ADHOC_NETWORK) && (OPEN_AUTH == pDCxt->conn[devId].dot11AuthMode) && + (NONE_AUTH == pDCxt->conn[devId].wpaAuthMode) && (WEP_CRYPT == pDCxt->conn[devId].wpaPairwiseCrypto)) + { + /* if we are connecting for the first time to an ad-hoc network with + * WEP. then submit the key via wmi_addKey_cmd */ + if (false == pDCxt->conn[devId].isConnected) + { + pKey = &(pDCxt->conn[devId].wepKeyList[pDCxt->conn[devId].wepDefTxKeyIndex]); + A_MEMZERO(&add_key_param, sizeof(add_key_param)); + add_key_param.keyIndex = pDCxt->conn[devId].wepDefTxKeyIndex; + add_key_param.keyType = WEP_CRYPT; + add_key_param.keyUsage = GROUP_USAGE | TX_USAGE; + add_key_param.keyLength = pKey->keyLen; + A_MEMCPY(&add_key_param.key, pKey->key, add_key_param.keyLength); + add_key_param.key_op_ctrl = KEY_OP_INIT_VAL; + wmi_cmd_start(pDCxt->pWmiCxt, &add_key_param, WMI_ADD_CIPHER_KEY_CMDID, sizeof(WMI_ADD_CIPHER_KEY_CMD)); + } + } + + /* Update connect & link status atomically */ + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + pDCxt->conn[devId].isConnected = true; + pDCxt->conn[devId].isConnectPending = false; + if ((channel > 2000) && (channel < 6500)) + { + pDCxt->conn[devId].channelHint = channel; + } + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + Api_BootProfile(pCxt, BOOT_PROFILE_DONE_CONNECT); + + pDCxt->rssi = 0; + +/* reset the rx aggr state */ + +#if WLAN_CONFIG_11N_AGGR_SUPPORT + aggr_reset_state(pDCxt->pAggrCxt); +#endif + if (pDCxt->wps_in_progress && pDCxt->devId == devId) + { + pDCxt->wps_in_progress = 0; + } + + CUSTOM_API_CONNECT_EVENT(pCxt, devId, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, + assocReqLen, assocRespLen, assocInfo); +} + +/*****************************************************************************/ +/* Api_DisconnectEvent - Processes a WMI_DISCONNECT_EVENT from the + * device. + * This event will come when the device has disconnected from the BSS + * network. + * void *pCxt - the driver context. + * uint8_t reason - encoded reason for the disconnection. + * uint8_t *bssid - bssid address of the network. + * uint8_t assocRespLen - association response frame length. + * uint8_t *assocInfo - association response frame payload. + * uint16_t protocolReasonStatus - reason field from assocation response + * frame. + *****************************************************************************/ +void Api_DisconnectEvent(void *pCxt, + uint8_t devId, + uint8_t reason, + uint8_t *bssid, + uint8_t assocRespLen, + uint8_t *assocInfo, + uint16_t protocolReasonStatus) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + POWER_MODE pwrmode; + + UNUSED_ARGUMENT(bssid); + UNUSED_ARGUMENT(assocRespLen); + UNUSED_ARGUMENT(assocInfo); + UNUSED_ARGUMENT(protocolReasonStatus); +/* it is necessary to clear the host-side rx aggregation state */ +#if WLAN_CONFIG_11N_AGGR_SUPPORT + aggr_reset_state(pDCxt->pAggrCxt); +#endif + + /* + * If the event is due to disconnect cmd from the host, only they the target + * would stop trying to connect. Under any other condition, target would + * keep trying to connect. + * + */ + if (reason == DISCONNECT_CMD) + { + pDCxt->conn[devId].isConnectPending = false; + } + else + { + pDCxt->conn[devId].isConnectPending = true; + } + + /* Update connect & link status atomically */ + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + pDCxt->conn[devId].isConnected = false; + pDCxt->conn[devId].channelHint = 0; + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + pDCxt->rssi = 0; + A_MEMZERO(pDCxt->conn[devId].bssid, ATH_MAC_LEN); + pDCxt->conn[devId].bssChannel = 0; + + if (pDCxt->wps_in_progress && pDCxt->devId == devId) + { + pDCxt->wps_in_progress = 0; + } + CUSTOM_API_DISCONNECT_EVENT(pCxt, devId, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus); + /* complete TKIP countermeasures operation. TKIP countermeasures + * requires that the STA avoid any contact with the AP for 60 seconds. + * this implementation simply blocks for that time via A_MDELAY(). + * Other implementations may choose to behave differently. */ + if (pDCxt->tkipCountermeasures != 0) + { + /* FIXME: should instead implement a way to block the driver at driver_main thus + * allowing the thread to continue running in single-threaded systems.*/ + A_MDELAY(IEEE80211_TKIP_COUNTERMEASURES_TIMEOUT_MSEC); + pDCxt->tkipCountermeasures = 0; + Api_ConnectWiFi(pCxt); + A_MDELAY(200); + + pwrmode.pwr_mode = REC_POWER; + pwrmode.pwr_module = TKIP; + Api_SetPowerMode(pCxt, &pwrmode); + } +} + +int dset_length; + +void Api_HostDsetStoreEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint8_t *strrclData = pDCxt->tempStorage; + uint16_t cur_len = pDCxt->strrclCxtLen; + + WMI_HOST_DSET_STORE_EVENT *pDsetEvent = (WMI_HOST_DSET_STORE_EVENT *)datap; + UNUSED_ARGUMENT(devId); + + dset_length = pDsetEvent->length; + + strrclData = pDCxt->tempStorage + cur_len; + + if (cur_len + dset_length <= pDCxt->tempStorageLength) + { + A_MEMCPY(strrclData, pDsetEvent->data, dset_length); + } + else + { + A_ASSERT(0); + } + pDCxt->strrclCxtLen += dset_length; +} + +#if 0 +A_STATUS +wmi_storerecall_recall_cmd(struct wmi_t *wmip, uint32_t length, void* pData) +{ + void *osbuf; + WMI_STORERECALL_RECALL_CMD *p; + uint32_t msgLength = sizeof(WMI_STORERECALL_RECALL_CMD) - sizeof(uint8_t); + + osbuf = A_NETBUF_ALLOC((int32_t)msgLength); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, (int32_t)msgLength); + + p = (WMI_STORERECALL_RECALL_CMD *)(A_NETBUF_DATA(osbuf)); + + p->length = A_CPU2LE32(length); + //A_MEMCPY(&p->data[0], pData, length); + /* here we append the payload to the msg rather than copy it. this is a + * memory and CPU optimization as the payload can be very large. + */ + A_NETBUF_APPEND_FRAGMENT(osbuf, pData, length); + + return (wmi_cmd_send(wmip, osbuf, WMI_STORERECALL_RECALL_CMDID, NO_SYNC_WMIFLAG)); +} +#endif + +void Api_HostDsetCreateEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + void *osbuf; + uint32_t msgLength; + WMI_HOST_DSET_RESP_CREATE_CMD *p; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + HOST_DSET *pHost; + + UNUSED_ARGUMENT(devId); + + WMI_HOST_DSET_CREATE_EVENT *pDsetEvent = (WMI_HOST_DSET_CREATE_EVENT *)datap; + pHost = dset_get(pDsetEvent->dset_id, pDsetEvent->length); + QCADRV_PRINTF("dset create id=%d length=%d\n", pDsetEvent->dset_id, pDsetEvent->length); + + /* + * respose KF dset create request + */ + msgLength = sizeof(WMI_HOST_DSET_RESP_CREATE_CMD); + osbuf = A_NETBUF_ALLOC((int32_t)msgLength); + + //NOTE: coverity fix + A_ASSERT(!(NULL == osbuf)); + if (NULL == osbuf) + { + return; + } + + A_NETBUF_PUT(osbuf, (int32_t)(msgLength)); + + p = (WMI_HOST_DSET_RESP_CREATE_CMD *)(A_NETBUF_DATA(osbuf)); + if (pHost != NULL) + p->flags = 0; + else + p->flags = 1; + + wmi_cmd_send(pDCxt->pWmiCxt, osbuf, WMI_HOST_DSET_RESP_CREATE_CMDID, NO_SYNC_WMIFLAG); +} + +void Api_HostDsetWriteEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + void *osbuf; + uint32_t msgLength; + WMI_HOST_DSET_RESP_WRITE_CMD *p; + HOST_DSET *pDset = NULL; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + WMI_HOST_DSET_WRITE_EVENT *pDsetEvent = (WMI_HOST_DSET_WRITE_EVENT *)datap; + + if (IS_STRRCL_DSET(pDsetEvent->dset_id)) + { + pDset = dset_get(pDsetEvent->dset_id, pDsetEvent->length); + } + + if (pDset == NULL) + return; + + QCADRV_PRINTF("dset write id=%d offset:%d length=%d\n", pDsetEvent->dset_id, pDsetEvent->offset, + pDsetEvent->length); + dset_write(pDset, pDsetEvent->data, pDsetEvent->offset, pDsetEvent->length); + + /* + * respose KF dset write request + */ + msgLength = sizeof(WMI_HOST_DSET_RESP_WRITE_CMD); + osbuf = A_NETBUF_ALLOC((int32_t)msgLength); + + //NOTE: coverity fix + A_ASSERT(!(NULL == osbuf)); + if (NULL == osbuf) + { + return; + } + + A_NETBUF_PUT(osbuf, (int32_t)(msgLength)); + + p = (WMI_HOST_DSET_RESP_WRITE_CMD *)(A_NETBUF_DATA(osbuf)); + p->dset_id = pDsetEvent->dset_id; + p->offset = pDsetEvent->offset; + p->length = pDsetEvent->length; + + wmi_cmd_send(pDCxt->pWmiCxt, osbuf, WMI_HOST_DSET_RESP_WRITE_CMDID, NO_SYNC_WMIFLAG); +} + +void Api_HostDsetReadbackEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + HOST_DSET *pDset; + uint32_t msgLength; + uint32_t strrcl_offset; + uint32_t offset, length; + // WMI_STORERECALL_RECALL_DSET *pRecallDset; + + uint16_t snd_size; + void *osbuf; + WMI_HOST_DSET_READBACK_CMD *p; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + UNUSED_ARGUMENT(devId); + + WMI_HOST_DSET_READBACK_EVENT *pDsetEvent = (WMI_HOST_DSET_READBACK_EVENT *)datap; + + msgLength = sizeof(WMI_HOST_DSET_READBACK_CMD) - sizeof(uint8_t); + QCADRV_PRINTF("dset id=%d\n", pDsetEvent->dset_id); + + pDset = dset_find(pDsetEvent->dset_id); + + //NOTE: coverity fix + A_ASSERT(!(NULL == pDset)); + if (NULL == pDset) + { + return; + } + + if (IS_STRRCL_DSET(pDsetEvent->dset_id)) + { + // pRecallDset = (WMI_STORERECALL_RECALL_DSET *)pDset->data_ptr; + strrcl_offset = sizeof(WMI_STORERECALL_RECALL_DSET); + } + + offset = pDsetEvent->offset; + length = pDsetEvent->length; + + if (pDset->length < offset + length) + length = pDset->length - offset; + + while (length > 0) + { + if (length > MAX_EVENT_SIZE) + snd_size = MAX_EVENT_SIZE; + else + snd_size = length; + + osbuf = A_NETBUF_ALLOC((int32_t)msgLength + snd_size); + if (osbuf == NULL) + { + return; + } + + A_NETBUF_PUT(osbuf, (int32_t)(msgLength + snd_size)); + p = (WMI_HOST_DSET_READBACK_CMD *)(A_NETBUF_DATA(osbuf)); + p->dset_id = pDsetEvent->dset_id; + + p->offset = offset; + p->length = snd_size; + + dset_read(pDset, p->data, offset + strrcl_offset, snd_size); + wmi_cmd_send(pDCxt->pWmiCxt, osbuf, WMI_HOST_DSET_READBACK_CMDID, NO_SYNC_WMIFLAG); + + offset += snd_size; + length -= snd_size; + } + + restore_power_state(pDCxt, 1); + A_MDELAY(50); +} + +void Api_HostDsetSyncEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + uint32_t msgLength; + uint16_t count; + void *osbuf; + WMI_HOST_DSET_SYNC_CMD *p; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + UNUSED_ARGUMENT(devId); + + WMI_HOST_DSET_SYNC_EVENT *pDsetEvent = (WMI_HOST_DSET_SYNC_EVENT *)datap; + + if (pDsetEvent->dset_count < MAX_DSET_SIZE) + count = pDsetEvent->dset_count; + else + count = MAX_DSET_SIZE; + + msgLength = sizeof(WMI_HOST_DSET_SYNC_CMD) - sizeof(uint8_t); + + dset_length = sizeof(HOST_DSET_ITEM) * count; + osbuf = A_NETBUF_ALLOC((int32_t)msgLength + dset_length); + if (osbuf == NULL) + { + return; + } + + A_NETBUF_PUT(osbuf, (int32_t)(msgLength + dset_length)); + p = (WMI_HOST_DSET_SYNC_CMD *)(A_NETBUF_DATA(osbuf)); + + count = dset_fill(&p->data[0], count); + p->dset_count = count; + + wmi_cmd_send(pDCxt->pWmiCxt, osbuf, WMI_HOST_DSET_SYNC_CMDID, NO_SYNC_WMIFLAG); +} + +void Api_HostDsetReadEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint8_t *strrclData = pDCxt->tempStorage; + void *osbuf; + WMI_STORERECALL_READ_CMD *p; + uint32_t msgLength = sizeof(WMI_STORERECALL_READ_CMD) - sizeof(uint8_t); + + UNUSED_ARGUMENT(devId); + + osbuf = A_NETBUF_ALLOC((int32_t)msgLength + dset_length); + if (osbuf == NULL) + { + return; + } + + A_NETBUF_PUT(osbuf, (int32_t)(msgLength + dset_length)); + + p = (WMI_STORERECALL_READ_CMD *)(A_NETBUF_DATA(osbuf)); + + p->length = A_CPU2LE32(dset_length); + A_MEMCPY(&p->data[0], strrclData, dset_length); + + QCADRV_PRINTF("[%02x][%02x][%02x][%02x] [%02x][%02x]\n", strrclData[0], strrclData[1], strrclData[2], strrclData[3], + strrclData[4], strrclData[5]); + + /* here we append the payload to the msg rather than copy it. this is a + * memory and CPU optimization as the payload can be very large. + */ + // A_NETBUF_APPEND_FRAGMENT(osbuf, strrclData, dset_length); + + wmi_cmd_send(pDCxt->pWmiCxt, osbuf, WMI_DSET_HOST_READ_CMDID, NO_SYNC_WMIFLAG); +} + +void Api_dset_read_event(A_DRIVER_CONTEXT *pDCxt, HOST_DSET_HANDLE *pDsetHandle, WMI_DSET_OP_READ_EVENT *pRespRead) +{ + uint32_t length; + uint32_t offset, buf_off; + + length = pRespRead->length; + offset = pRespRead->offset; + buf_off = offset - pRespRead->offset; + + if (pRespRead->status == 0) + { + QCADRV_PRINTF("read off:%d len:%d\n", pRespRead->offset, pRespRead->length); + + if (offset + length > pDsetHandle->offset + pDsetHandle->length) + length = pDsetHandle->offset + pDsetHandle->length - offset; + + A_MEMCPY(pDsetHandle->data_ptr + buf_off, pRespRead->data, length); + + pDsetHandle->left_len -= length; + + if (pDsetHandle->left_len != 0) + return; + } + + QCADRV_PRINTF("read done\n"); + + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pRespRead->status, pDsetHandle->cb_args); +} + +void Api_dset_write_event(A_DRIVER_CONTEXT *pDCxt, HOST_DSET_HANDLE *pDsetHandle, WMI_DSET_OP_READ_EVENT *pRespRead) +{ + uint32_t length; + uint32_t offset; + + length = pRespRead->length; + offset = pRespRead->offset; + + QCADRV_PRINTF("read off:%d len:%d\n", pRespRead->offset, pRespRead->length); + + if (offset + length > pDsetHandle->offset + pDsetHandle->length) + length = pDsetHandle->offset + pDsetHandle->length - offset; + + A_MEMCPY(pDsetHandle->data_ptr + offset, pRespRead->data, length); + + pDsetHandle->left_len -= length; + + if (pDsetHandle->left_len != 0) + return; + + QCADRV_PRINTF("write done\n"); + + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pRespRead->status, pDsetHandle->cb_args); +} + +void Api_DsetOPEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + struct WMIX_DSET_OP_SET_EVENT + { + uint32_t dset_id; + } * pCmd; + HOST_DSET_HANDLE *pDsetHandle; + + QCADRV_PRINTF("dset op event\n"); + + WMI_DSET_OP_EVENT *pDsetOPEvent = (WMI_DSET_OP_EVENT *)datap; + + pCmd = (struct WMIX_DSET_OP_SET_EVENT *)pDsetOPEvent->data; + pDsetHandle = dset_find_handle(pCmd->dset_id); + + //NOTE: coverity fix + A_ASSERT(!(NULL == pDsetHandle)); + if (NULL == pDsetHandle) + { + return; + } + + if (pDsetHandle->cb == NULL && (pDsetOPEvent->hdr.commandId != WMIX_DSET_READ_CMDID)) + pDCxt->dset_op_done = true; + + switch (pDsetOPEvent->hdr.commandId) + { + case WMIX_DSET_CREATE_CMDID: + { + WMI_DSET_OP_CREATE_EVENT *pCreateEvent; + pCreateEvent = (WMI_DSET_OP_CREATE_EVENT *)pDsetOPEvent->data; + + QCADRV_PRINTF("create return: %d\n", pCreateEvent->status); + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pCreateEvent->status, pDsetHandle->cb_args); + + pDCxt->setparamStatus = pCreateEvent->status; + pDCxt->dset_op_done = true; + break; + } + case WMIX_DSET_OPEN_CMDID: + { + WMI_DSET_OP_CREATE_EVENT *pCreateEvent; + pCreateEvent = (WMI_DSET_OP_CREATE_EVENT *)pDsetOPEvent->data; + + QCADRV_PRINTF("open return: %d\n", pCreateEvent->status); + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pCreateEvent->status, pDsetHandle->cb_args); + + pDCxt->setparamStatus = pCreateEvent->status; + pDCxt->dset_op_done = true; + break; + } + case WMIX_DSET_READ_CMDID: + { + WMI_DSET_OP_READ_EVENT *pRespRead; + pRespRead = (WMI_DSET_OP_READ_EVENT *)pDsetOPEvent->data; + + Api_dset_read_event(pDCxt, pDsetHandle, pRespRead); + + pDCxt->setparamStatus = pRespRead->status; + pDCxt->dset_op_done = true; + break; + } + case WMIX_DSET_WRITE_CMDID: + { + WMI_DSET_OP_CREATE_EVENT *pCreateEvent; + pCreateEvent = (WMI_DSET_OP_CREATE_EVENT *)pDsetOPEvent->data; + + QCADRV_PRINTF("write return: %d\n", pCreateEvent->status); + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pCreateEvent->status, pDsetHandle->cb_args); + + pDCxt->setparamStatus = pCreateEvent->status; + pDCxt->dset_op_done = true; + break; + } + case WMIX_DSET_COMMIT_CMDID: + { + WMI_DSET_OP_COMMIT_EVENT *pRespCommit; + pRespCommit = (WMI_DSET_OP_COMMIT_EVENT *)pDsetOPEvent->data; + + QCADRV_PRINTF("commit return: %d\n", pRespCommit->status); + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pRespCommit->status, pDsetHandle->cb_args); + + pDCxt->setparamStatus = pRespCommit->status; + pDCxt->dset_op_done = true; + break; + } + case WMIX_DSET_CLOSE_CMDID: + { + WMI_DSET_OP_CLOSE_EVENT *pRespClose; + pRespClose = (WMI_DSET_OP_CLOSE_EVENT *)pDsetOPEvent->data; + + QCADRV_PRINTF("close return: %d\n", pRespClose->status); + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pRespClose->status, pDsetHandle->cb_args); + + pDCxt->setparamStatus = pRespClose->status; + pDCxt->dset_op_done = true; + break; + } + case WMIX_DSET_SIZE_CMDID: + { + WMI_DSET_OP_CREATE_EVENT *pCreateEvent; + pCreateEvent = (WMI_DSET_OP_CREATE_EVENT *)pDsetOPEvent->data; + + QCADRV_PRINTF("size return: %d\n", pCreateEvent->status); + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pCreateEvent->status, pDsetHandle->cb_args); + + pDCxt->setparamStatus = pCreateEvent->status; + pDCxt->dset_op_done = true; + break; + } + case WMIX_DSET_DELETE_CMDID: + { + WMI_DSET_OP_CREATE_EVENT *pCreateEvent; + pCreateEvent = (WMI_DSET_OP_CREATE_EVENT *)pDsetOPEvent->data; + + QCADRV_PRINTF("delete return: %d\n", pCreateEvent->status); + if (pDsetHandle->cb != NULL) + pDsetHandle->cb(pCreateEvent->status, pDsetHandle->cb_args); + + pDCxt->setparamStatus = pCreateEvent->status; + pDCxt->dset_op_done = true; + break; + } + } + DRIVER_WAKE_DRIVER(pCxt); +} + +/*****************************************************************************/ +/* Api_StoreRecallEvent - Processes a WMI_STORERECALL_STORE_EVENT from the + * device. + * This event will come when the device is ready to be shutdown by the host + * as part of a store-and-recall sequence. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * int32_t len - length in bytes of datap + * void *pReq - original event rx-request object. + *****************************************************************************/ +void Api_StoreRecallEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + WMI_STORERECALL_STORE_EVENT *pEv; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint8_t *strrclData = pDCxt->tempStorage; + + UNUSED_ARGUMENT(devId); + + switch (pDCxt->strrclState) + { + case STRRCL_ST_START: + A_MEMCPY(strrclData, datap, len); + pEv = (WMI_STORERECALL_STORE_EVENT *)strrclData; + + if (pEv->msec_sleep == 0) + { + /* a 0 msec_sleep indicates a firmware condition which + * prevented StoreRecall from completing. in this event this + * driver merely aborts the operation and continues normally. + */ + pDCxt->strrclState = STRRCL_ST_INIT; + pDCxt->strrclBlock = false; + API_STORE_RECALL_EVENT(pCxt); + /* FIXME: Notify the application that S&R did not complete + * successfully. + */ + } + else + { + /* indicate chip shutdown via chip_down. */ + // pDCxt->strrclCxt = datap; + pDCxt->strrclCxt = strrclData; + pDCxt->strrclCxtLen = len; + pDCxt->strrclState = STRRCL_ST_ACTIVE; + /* this call should shutdown the chip and maintain that state for msec_sleep milliseconds */ + Strrcl_Recall(pCxt, A_LE2CPU32(pEv->msec_sleep)); + } + break; + case STRRCL_ST_AWAIT_FW: + pDCxt->strrclState = STRRCL_ST_INIT; + pDCxt->strrclBlock = false; + /* Indicate completion to the custom layer */ + API_STORE_RECALL_EVENT(pCxt); + break; + default: + /* do nothing but this should never happen */ + break; + } +} + +/*****************************************************************************/ +/* Api_StoreRecallEvent - Processes a WMI_STORERECALL_STORE_EVENT from the + * device. + * This event will come when the device is ready to be shutdown by the host + * as part of a store-and-recall sequence. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * int32_t len - length in bytes of datap + * void *pReq - original event rx-request object. + *****************************************************************************/ +void Api_StoreRecallStartEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + WMI_STORERECALL_START_EVENT *pEv; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + // uint8_t* strrclData = pDCxt->tempStorage; + + UNUSED_ARGUMENT(devId); + + pEv = (WMI_STORERECALL_START_EVENT *)datap; + if (pEv->msec_sleep == 0) + { + /* a 0 msec_sleep indicates a firmware condition which + * prevented StoreRecall from completing. in this event this + * driver merely aborts the operation and continues normally. + */ + pDCxt->strrclState = STRRCL_ST_INIT; + pDCxt->strrclBlock = false; + API_STORE_RECALL_EVENT(pCxt); + /* FIXME: Notify the application that S&R did not complete + * successfully. + */ + } + else + { + /* indicate chip shutdown via chip_down. */ + // pDCxt->strrclCxt = datap; + // pDCxt->strrclCxt = strrclData; + // pDCxt->strrclCxtLen = len; + + QCADRV_PRINTF("total = %d buff len=%d\n", pDCxt->strrclCxtLen, pDCxt->tempStorageLength); + + pDCxt->strrclState = STRRCL_ST_ACTIVE; + /* this call should shutdown the chip and maintain that state for msec_sleep milliseconds */ + Strrcl_Recall(pCxt, A_LE2CPU32(pEv->msec_sleep)); + } +} + +/*****************************************************************************/ +/* Api_WpsProfileEvent - Processes a WMI_WPS_PROFILE_EVENT from the device. + * this event will come when the device has finished a WPS operation. it + * announcess to the host the results of that operation. This function + * stores the information so that it can be processed asynchronously by + * an application thread waiting for the result. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * int32_t len - length in bytes of datap + * void *pReq - original event rx-request object. + *****************************************************************************/ +void Api_WpsProfileEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq) +{ + WMI_WPS_PROFILE_EVENT *pEv = (WMI_WPS_PROFILE_EVENT *)datap; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + UNUSED_ARGUMENT(len); + UNUSED_ARGUMENT(devId); + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + + do + { + /* cleanup previous buffer */ + if (pDCxt->wpsBuf != NULL) + { + A_NETBUF_FREE(pDCxt->wpsBuf); + pDCxt->wpsBuf = NULL; + } + + pDCxt->wpsBuf = pReq; + pDCxt->wpsEvent = (void *)pEv; + /* convert event values to host endian format */ + pEv->credential.auth_type = A_LE2CPU16(pEv->credential.auth_type); + pEv->credential.encr_type = A_LE2CPU16(pEv->credential.encr_type); + pEv->credential.ap_channel = A_LE2CPU16(pEv->credential.ap_channel); + /* announce event receive to any waiting threads */ + pDCxt->wpsState = false; + API_WPS_PROFILE_EVENT(pCxt, datap, len, pReq); + + } while (0); + + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); +} + +#if WLAN_CONFIG_11N_AGGR_SUPPORT +/*****************************************************************************/ +/* Api_AggrRecvAddbaReqEvent - processes a WMI_ADDBA_REQ_EVENT from the device. + * These events come when the device reveives a add-block-ACK packet from + * an AP or peer device. This is only relevant for 11n aggregation. + * void *pCxt - the driver context. + * WMI_ADDBA_REQ_EVENT *evt - the event structure + *****************************************************************************/ +void Api_AggrRecvAddbaReqEvent(void *pCxt, uint8_t devId, WMI_ADDBA_REQ_EVENT *evt) +{ + UNUSED_ARGUMENT(devId); + evt->st_seq_no = A_LE2CPU16(evt->st_seq_no); + + if (evt->status == 0) + { + aggr_recv_addba_req_evt(GET_DRIVER_COMMON(pCxt)->pAggrCxt, evt->tid, evt->st_seq_no, evt->win_sz); + } + API_AGGR_RECV_ADDBA_REQ_EVENT(pCxt, evt); +} + +/*****************************************************************************/ +/* Api_AggrRecvDelbaReqEvent - processes a WMI_DELBA_EVENT from the device. + * These events come when the device reveives a delete-block-ACK packet from + * an AP or peer device. This is only relevant for 11n aggregation. + * void *pCxt - the driver context. + * WMI_DELBA_EVENT *evt - the event structure + *****************************************************************************/ +void Api_AggrRecvDelbaReqEvent(void *pCxt, uint8_t devId, WMI_DELBA_EVENT *evt) +{ + UNUSED_ARGUMENT(devId); + aggr_recv_delba_req_evt(GET_DRIVER_COMMON(pCxt)->pAggrCxt, evt->tid); + API_AGGR_RECV_DELBA_REQ_EVENT(pCxt, evt); +} +#endif /* WLAN_CONFIG_11N_AGGR_SUPPORT */ + +/*****************************************************************************/ +/* Api_ReadyEvent - processes a WMI_READY_EVENT from the device. records + * usefull information from the event. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t phyCap - device phy capabilities. + * uint32_t sw_ver - device firmware version. + * uint32_t abi_ver - device ABI version. + *****************************************************************************/ +void Api_ReadyEvent(void *pCxt, uint8_t devId, uint8_t *datap, uint8_t phyCap, uint32_t sw_ver, uint32_t abi_ver) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + UNUSED_ARGUMENT(devId); + Api_BootProfile(pCxt, BOOT_PROFILE_WMI_READY); + + pDCxt->wmiReady = true; + pDCxt->phyCapability = phyCap; + pDCxt->wlanVersion = sw_ver; + pDCxt->abiVersion = abi_ver; + A_MEMCPY(&pDCxt->scan_param, &default_scan_param, sizeof(WMI_SCAN_PARAMS_CMD)); + + CUSTOM_API_READY_EVENT(pCxt, datap, phyCap, sw_ver, abi_ver); +} + +/*****************************************************************************/ +/* Api_RSNASuccessEvent - processes a RSNA SUCCESS Message from the device. + * void *pCxt - the driver context. + * uint8_t code - success code. + *****************************************************************************/ +void Api_RSNASuccessEvent(void *pCxt, uint8_t devId, uint8_t code) +{ + UNUSED_ARGUMENT(devId); + /* this will call the custom event which will call + * the WifiCallback which will indicate the status + */ + CUSTOM_API_RSNA_SUCCESS_EVENT(pCxt, devId, code); +} + +/*****************************************************************************/ +/* GetTemperatureReply - process the temperature reply from the device + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t len - buffer length + *****************************************************************************/ +void Api_GetTemperatureReply(void *pCxt, uint8_t *datap, uint32_t len) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + WMI_GET_TEMPERATURE_REPLY *pReply = (WMI_GET_TEMPERATURE_REPLY *)datap; + pDCxt->temperatureValid = true; + pDCxt->raw_temperature = pReply->tempRegVal; + pDCxt->tempDegree = pReply->tempDegree; + API_GET_TEMPERATURE_REPLY(pCxt, datap, len); +} + +/*****************************************************************************/ +/* Api_GetWpsInitReply - Init WPS event back + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t code - init return code + *****************************************************************************/ +void Api_GetWpsInitReply(void *pCxt, uint8_t *datap, uint32_t len) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + /* this will call the custom event which will call + * the WifiCallback which will indicate the status + */ + WMI_WLAN_WPS_INIT_KEY_REPLY *pReply = ( WMI_WLAN_WPS_INIT_KEY_REPLY *)datap; + pDCxt->wps_init_key = pReply->status; + API_WPS_INIT_REPLY(pCxt,datap, len); +} + +/*****************************************************************************/ +/* GetCountryCodeReply - process the countrycode reply from the device + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t len - buffer length + *****************************************************************************/ +void Api_GetCountryCodeReply(void *pCxt, uint8_t *datap, uint32_t len) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + WMI_GET_COUNTRY_CODE_REPLY *pReply = (WMI_GET_COUNTRY_CODE_REPLY *)datap; + pDCxt->countryCodeValid = true; + A_MEMCPY(pDCxt->raw_countryCode, pReply->country_code, 3); + QCADRV_PRINTF("code is %c , %c.\n", pDCxt->raw_countryCode[0], pDCxt->raw_countryCode[1]); + API_GET_COUNTRY_CODE_REPLY(pCxt, datap, len); +} +/* GetSetParamReply - recv param set ack from the device + * A_VOID *pCxt - the driver context. + * uint8_t *datap - original event buffer. + *****************************************************************************/ +void Api_GetSetParamReply(void *pCxt, uint8_t *datap) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + WMI_PARAM_SET_REPLY *reply = (WMI_PARAM_SET_REPLY *)datap; + + pDCxt->setparamValid = true; + pDCxt->setparamStatus = reply->status; + API_SET_PARAM_REPLY_EVENT(pCxt); +} + +#if ENABLE_P2P_MODE +/*****************************************************************************/ +/* p2p_go_neg_event - processes a P2P GO Negotiation event from the device. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t len - buffer length + *****************************************************************************/ +void p2p_go_neg_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len, WMI_P2P_PROV_INFO *wps_info) +{ + API_P2P_GO_NEG_EVENT(pCxt, devId, datap, len, wps_info); +} + +void p2p_invite_sent_result_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_P2P_INVITE_SEND_RESULT(pCxt, devId, datap, len); +} +/*****************************************************************************/ +/* p2p_node_list_event- event which gives the discovered nodes. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t len - buffer length + *****************************************************************************/ +void p2p_node_list_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_P2P_NODE_LIST_EVENT(pCxt, devId, datap, len); +} + +/*****************************************************************************/ +/* p2p_list_persistent_network_event - event which gives the discovered nodes. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t len - buffer length + *****************************************************************************/ +void p2p_list_persistent_network_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_P2P_LIST_PERSISTENT_NETWORK_EVENT(pCxt, devId, datap, len); +} + +/*****************************************************************************/ +/* p2p_req_auth_event - processes a response event for authentication request. + * void *pCxt - the driver context. + * uint8_t *datap - original event buffer. + * uint8_t len - buffer length + *****************************************************************************/ +void p2p_req_auth_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_P2P_REQ_AUTH_EVENT(pCxt, devId, datap, len); +} + +void get_p2p_ctx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_GET_P2P_CTX(pCxt, devId, datap, len); +} + +void get_p2p_prov_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_P2P_PROV_DISC_REQ(pCxt, devId, datap, len); +} +#if 1 // KK +void get_p2p_serv_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_P2P_SERV_DISC_REQ(pCxt, devId, datap, len); +} + +void p2p_invite_req_rx(void *pCxt, uint8_t devId, uint8_t *datap, uint8_t len) +{ + API_P2P_INVITE_REQ(pCxt, devId, datap, len); +} + +void p2p_invite_rcvd_result_ev(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + API_P2P_INVITE_RCVD_RESULT(pCxt, devId, datap, len); +} +#endif +#endif + +#if MANUFACTURING_SUPPORT +void Api_TestCmdEventRx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + UNUSED_ARGUMENT(devId); + API_TEST_RESP_EVENT(pCxt, datap, len); + + pDCxt->testResp = true; + DRIVER_WAKE_USER(pCxt); +} +#endif + +/*****************************************************************************/ +/* Api_RxDbglogEvent - Processes a WMIX_DBGLOG_EVENT from the device. + *****************************************************************************/ +void Api_RxDbglogEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len) +{ + UNUSED_ARGUMENT(devId); + API_WMIX_DBGLOG_EVENT(wmip, datap, len); +} + +/*****************************************************************************/ +/* Api_RxGpioDataEvent - Processes a WMIX_GPIO_DATA_EVENT from the device. + *****************************************************************************/ +void Api_RxGpioDataEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len) +{ + UNUSED_ARGUMENT(devId); + CUSTOM_API_WMIX_GPIO_DATA_EVENT(wmip, datap, len); +} + +/*****************************************************************************/ +/* Api_RxHBChallengeEvent - Processes a WMIX_GPIO_DATA_EVENT from the device. + *****************************************************************************/ +void Api_RxHBChallengeEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len) +{ + //pDCxt = GET_DRIVER_COMMON(pCxt); + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + WMIX_HB_CHALLENGE_RESP_EVENT *pEv = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap; + + if(pEv->cookie == pDCxt->hb_sequence) + pDCxt->hb_challenge_done = true; + + DRIVER_WAKE_USER(pCxt); +} + +#if ENABLE_KF_PERFORMANCE + +/*****************************************************************************/ +/* Api_RxPfmDataEvent - Processes a WMIX_PFM_DATA_EVENT from the device. + *****************************************************************************/ +void Api_RxPfmDataEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len) +{ + UNUSED_ARGUMENT(devId); + CUSTOM_API_WMIX_PFM_DATA_EVENT(wmip, datap, len); +} + +/*****************************************************************************/ +/* Api_RxPfmDataDoneEvent - Processes a WMIX_PFM_DATA_DONE_EVENT from the device. + *****************************************************************************/ + +void Api_RxPfmDataDoneEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len) +{ + UNUSED_ARGUMENT(devId); + CUSTOM_API_WMIX_PFM_DATA_DONE_EVENT(wmip, datap, len); +} +#endif + +#if 0 +/*****************************************************************************/ +/* Api_PFMReportEvent - Processes a WMI_PFM_REPORT_EVENTID from the device. + *****************************************************************************/ +void add_one_profile(uint8_t event_id, uint16_t timestamp); + +void +Api_PFMReportEvent(void *pCxt, uint8_t devId, WMI_PFM_REPORT_EVENT *pEv) +{ + uint8_t i; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + UNUSED_ARGUMENT(devId); + for (i=0; i < MAX_TIMESTAMP; i++) + { + if (pEv->eventID[i] == 0) + break; + + add_one_profile(pEv->eventID[i] + 15, (uint16_t)pEv->timestamp[i] / 32); + } + pDCxt->pfmDone = true; + + DRIVER_WAKE_USER(pCxt); +} + +/*****************************************************************************/ +/* Api_PFMReportEvent - Processes a WMI_PFM_REPORT_EVENTID from the device. + *****************************************************************************/ +void +Api_DiagReportEvent(void *pCxt, WMI_DIAG_EVENT *pEv) +{ + if(ath_custom_init.Boot_Profile == NULL) + return; + +/* if (pEv->commandId == WMID_FSM_AUTH_EVENTID) + { + ath_custom_init.Boot_Profile(BOOT_PROFILE_AUTH_EVENT); + } + + else if (pEv->commandId == WMID_FSM_ASSOC_EVENTID) + { + ath_custom_init.Boot_Profile(BOOT_PROFILE_ASSOC_EVENT); + } + else if (pEv->commandId == WMID_START_SCAN_EVENTID) + { + ath_custom_init.Boot_Profile(BOOT_PROFILE_START_SCAN); + } +*/ +} +#endif + +#if ENABLE_P2P_MODE +void Api_p2p_go_neg_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len, WMI_P2P_PROV_INFO *wps_info) +{ + uint32_t evt_id = 0; + evt_id = WMI_P2P_GO_NEG_RESULT_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, sizeof(WMI_P2P_GO_NEG_RESULT_EVENT)); + + if (GET_DRIVER_COMMON(pCxt)->p2pEvtState == true) + { + GET_DRIVER_COMMON(pCxt)->p2pEvtState = false; + } + else + { + GET_DRIVER_COMMON(pCxt)->p2pevtflag = true; + } + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_node_list_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + uint8_t *tmpBuf; + evt_id = WMI_P2P_NODE_LIST_EVENTID; + WMI_P2P_NODE_LIST_EVENT *handleP2PDev = (WMI_P2P_NODE_LIST_EVENT *)datap; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + tmpBuf = GET_DRIVER_COMMON(pCxt)->pScanOut; + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + tmpBuf += sizeof(uint32_t); + *tmpBuf = handleP2PDev->num_p2p_dev; + tmpBuf++; + + A_MEMCPY((uint8_t *)tmpBuf, ((uint8_t *)(handleP2PDev->data)), + (sizeof(P2P_DEVICE_LITE) * (handleP2PDev->num_p2p_dev))); + + GET_DRIVER_COMMON(pCxt)->p2pEvtState = false; + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_req_auth_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + evt_id = WMI_P2P_REQ_TO_AUTH_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, sizeof(WMI_P2P_REQ_TO_AUTH_EVENT)); + + GET_DRIVER_COMMON(pCxt)->p2pevtflag = true; + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_list_persistent_network_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + evt_id = WMI_P2P_LIST_PERSISTENT_NETWORK_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + WMI_P2P_PERSISTENT_LIST_NETWORK_EVENT *ev = (WMI_P2P_PERSISTENT_LIST_NETWORK_EVENT *)datap; + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), ev->data, + (MAX_LIST_COUNT * sizeof(WMI_PERSISTENT_MAC_LIST))); + + GET_DRIVER_COMMON(pCxt)->p2pEvtState = false; + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_get_p2p_ctx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + evt_id = WMI_P2P_PROV_DISC_RESP_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, sizeof(WMI_P2P_PROV_DISC_RESP_EVENT)); + + GET_DRIVER_COMMON(pCxt)->p2pEvtState = false; + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_prov_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + evt_id = WMI_P2P_PROV_DISC_REQ_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, sizeof(WMI_P2P_PROV_DISC_REQ_EVENT)); + + GET_DRIVER_COMMON(pCxt)->p2pevtflag = true; + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_serv_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + evt_id = WMI_P2P_SDPD_RX_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, sizeof(WMI_P2P_SDPD_RX_EVENT)); + + GET_DRIVER_COMMON(pCxt)->p2pevtflag = true; + } + + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_invite_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + // async event for peer invite + uint32_t evt_id = 0; + evt_id = WMI_P2P_INVITE_REQ_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, sizeof(WMI_P2P_FW_INVITE_REQ_EVENT)); + + GET_DRIVER_COMMON(pCxt)->p2pevtflag = true; + } + + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_invite_rcvd_result(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + evt_id = WMI_P2P_INVITE_RCVD_RESULT_EVENTID; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, + sizeof(WMI_P2P_INVITE_RCVD_RESULT_EVENT)); + + GET_DRIVER_COMMON(pCxt)->p2pevtflag = true; + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +void Api_p2p_invite_send_result(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len) +{ + uint32_t evt_id = 0; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + evt_id = WMI_P2P_INVITE_SENT_RESULT_EVENTID; + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + A_MEMZERO(GET_DRIVER_COMMON(pCxt)->pScanOut, pDCxt->tempStorageLength); + + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, &evt_id, sizeof(uint32_t)); + + A_MEMCPY((GET_DRIVER_COMMON(pCxt)->pScanOut) + sizeof(uint32_t), datap, + sizeof(WMI_P2P_INVITE_SENT_RESULT_EVENT)); + + GET_DRIVER_COMMON(pCxt)->p2pevtflag = true; + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); +} + +#endif +#if MANUFACTURING_SUPPORT +void Api_Test_Cmd_Event(void *pCxt, uint8_t *datap, uint32_t len) +{ + UNUSED_ARGUMENT(len); + A_MEMCPY(GET_DRIVER_COMMON(pCxt)->pScanOut, datap, len); + GET_DRIVER_COMMON(pCxt)->testCmdRespBufLen = len; +} +#endif + +void Api_ProbeReqEvent(void *pCxt, uint8_t *datap, uint32_t len) +{ + CUSTOM_API_PROBEREQ_EVENT(pCxt, datap, len); +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/bmi/bmi.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/bmi/bmi.c new file mode 100644 index 00000000000..0b68e053a1f --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/bmi/bmi.c @@ -0,0 +1,616 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include +#include +#include "hw20_mbox_host_reg.h" +//#include "bmi_internal.h" +#include "atheros_wifi_api.h" +#include "bmi.h" + +#define BMI_ENDPOINT 0 + +#define BMI_COMMUNICATION_TIMEOUT 100000 + +/* +Although we had envisioned BMI to run on top of HTC, this is not how the +final implementation ended up. On the Target side, BMI is a part of the BSP +and does not use the HTC protocol nor even DMA -- it is intentionally kept +very simple. +*/ + +#if DRIVER_CONFIG_INCLUDE_BMI + +static uint8_t bmiDone = true; +static uint32_t *pBMICmdCredits; +static uint8_t *pBMICmdBuf; +#define MAX_BMI_CMDBUF_SZ \ + (BMI_DATASZ_MAX + sizeof(uint32_t) /* cmd */ + sizeof(uint32_t) /* addr */ + sizeof(uint32_t)) /* length */ +#define BMI_COMMAND_FITS(sz) ((sz) <= MAX_BMI_CMDBUF_SZ) + +static A_STATUS bmiBufferSend(void *pCxt, uint8_t *buffer, uint32_t length) +{ + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + A_STATUS status; + uint32_t timeout; + uint32_t address; + // A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + A_NETBUF_CONFIGURE(pReq, pBMICmdCredits, 0, sizeof(uint32_t), sizeof(uint32_t)); + + *pBMICmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + + while (timeout-- && !(*pBMICmdCredits)) + { + /* Read the counter register to get the command credits */ + address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + BMI_ENDPOINT) * 4; + ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, address, true, sizeof(uint32_t)); + /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause + * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to + * make all HIF accesses 4-byte aligned */ + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + break; + } + + /* the counter is only 8=bits, ignore anything in the upper 3 bytes */ + + *pBMICmdCredits = A_LE2CPU32(*pBMICmdCredits); + + (*pBMICmdCredits) &= 0xFF; + } + + if (*pBMICmdCredits) + { + A_NETBUF_CONFIGURE(pReq, buffer, 0, length, length); + address = HW_GetMboxAddress(pCxt, BMI_ENDPOINT, length); + address &= ATH_TRANS_ADDR_MASK; + A_NETBUF_SET_ELEM(pReq, A_REQ_ADDRESS, address); + A_NETBUF_SET_ELEM(pReq, A_REQ_TRANSFER_LEN, length); + /* init the packet read params/cmd incremental vs fixed address etc. */ + A_NETBUF_SET_ELEM(pReq, A_REQ_COMMAND, (ATH_TRANS_WRITE | ATH_TRANS_DMA)); + status = Hcd_Request(pCxt, pReq); + if (status != A_OK) + { + return A_ERROR; + } + } + else + { + return A_ERROR; + } + + return status; +} + +static A_STATUS bmiBufferReceive(void *pCxt, uint8_t *buffer, uint32_t length, boolean want_timeout) +{ + A_STATUS status; + uint32_t address; + uint32_t availableRecvBytes; + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + // A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + if (length >= 4) + { /* NB: Currently, always true */ + /* + * NB: word_available is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static uint32_t word_available; + uint32_t timeout; + + word_available = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while ((!want_timeout || timeout--) && !word_available) + { + status = Hcd_DoPioInternalAccess(pCxt, ATH_SPI_RDBUF_BYTE_AVA_REG, &availableRecvBytes, true); + if (status != A_OK) + { + break; + } + + if (availableRecvBytes >= sizeof(uint32_t)) + { + word_available = 1; + } + } + + if (!word_available) + { + return A_ERROR; + } + } + + A_NETBUF_CONFIGURE(pReq, buffer, 0, length, length); + address = HW_GetMboxAddress(pCxt, BMI_ENDPOINT, length); + address &= ATH_TRANS_ADDR_MASK; + A_NETBUF_SET_ELEM(pReq, A_REQ_ADDRESS, address); + A_NETBUF_SET_ELEM(pReq, A_REQ_TRANSFER_LEN, length); + /* init the packet read params/cmd incremental vs fixed address etc. */ + A_NETBUF_SET_ELEM(pReq, A_REQ_COMMAND, (ATH_TRANS_READ | ATH_TRANS_DMA)); + status = Hcd_Request(pCxt, pReq); + if (status != A_OK) + { + return A_ERROR; + } + + return A_OK; +} + +/* APIs visible to the driver */ +A_STATUS +BMIInit(void *pCxt) +{ + bmiDone = false; + + /* + * On some platforms, it's not possible to DMA to a static variable + * in a device driver (e.g. Linux loadable driver module). + * So we need to A_MALLOC space for "command credits" and for commands. + * + * Note: implicitly relies on A_MALLOC to provide a buffer that is + * suitable for DMA (or PIO). This buffer will be passed down the + * bus stack. + */ + if (!pBMICmdCredits) + { + pBMICmdCredits = (uint32_t *)A_MALLOC(4, MALLOC_ID_TEMPORARY); + A_ASSERT(pBMICmdCredits); + } + + if (!pBMICmdBuf) + { + pBMICmdBuf = (uint8_t *)A_MALLOC(MAX_BMI_CMDBUF_SZ, MALLOC_ID_TEMPORARY); + A_ASSERT(pBMICmdBuf); + } + + return A_OK; +} + +void BMICleanup(void) +{ + if (pBMICmdCredits) + { + A_FREE(pBMICmdCredits, MALLOC_ID_TEMPORARY); + pBMICmdCredits = NULL; + } + + if (pBMICmdBuf) + { + A_FREE(pBMICmdBuf, MALLOC_ID_TEMPORARY); + pBMICmdBuf = NULL; + } +} + +A_STATUS +BMIDone(void *pCxt) +{ + A_STATUS status; + uint32_t cid; + + if (bmiDone) + { + return A_OK; + } + + bmiDone = true; + cid = A_CPU2LE32(BMI_DONE); + + status = bmiBufferSend(pCxt, (uint8_t *)&cid, sizeof(cid)); + if (status != A_OK) + { + return A_ERROR; + } + + if (pBMICmdCredits) + { + A_FREE(pBMICmdCredits, MALLOC_ID_TEMPORARY); + pBMICmdCredits = NULL; + } + + if (pBMICmdBuf) + { + A_FREE(pBMICmdBuf, MALLOC_ID_TEMPORARY); + pBMICmdBuf = NULL; + } + + return A_OK; +} + +A_STATUS +BMIGetTargetInfo(void *pCxt, struct bmi_target_info *targ_info) +{ + uint32_t cid; + + if (bmiDone) + { + return A_ERROR; + } + + cid = A_CPU2LE32(BMI_GET_TARGET_INFO); + + if (A_OK != bmiBufferSend(pCxt, (uint8_t *)&cid, sizeof(cid))) + { + return A_ERROR; + } + + if (A_OK != bmiBufferReceive(pCxt, (uint8_t *)&targ_info->target_ver, sizeof(targ_info->target_ver), true)) + { + return A_ERROR; + } + + targ_info->target_ver = A_LE2CPU32(targ_info->target_ver); + + if (targ_info->target_ver == TARGET_VERSION_SENTINAL) + { + /* Determine how many bytes are in the Target's targ_info */ + if (A_OK != bmiBufferReceive(pCxt, (uint8_t *)&targ_info->target_info_byte_count, + sizeof(targ_info->target_info_byte_count), true)) + { + return A_ERROR; + } + + targ_info->target_info_byte_count = A_LE2CPU32(targ_info->target_info_byte_count); + + /* + * The Target's targ_info doesn't match the Host's targ_info. + * We need to do some backwards compatibility work to make this OK. + */ + A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info)); + + /* Read the remainder of the targ_info */ + if (A_OK != bmiBufferReceive(pCxt, ((uint8_t *)targ_info) + sizeof(targ_info->target_info_byte_count), + sizeof(*targ_info) - sizeof(targ_info->target_info_byte_count), true)) + { + return A_ERROR; + } + + targ_info->target_ver = A_LE2CPU32(targ_info->target_ver); + targ_info->target_type = A_LE2CPU32(targ_info->target_type); + } + else + { + return A_ERROR; + } + + return A_OK; +} + +#if 1 +A_STATUS +BMIReadMemory(void *pCxt, uint32_t address, uint8_t *buffer, uint32_t length) +{ + uint32_t cid; + A_STATUS status; + uint32_t offset; + uint32_t remaining, rxlen, temp; + + A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length))); + memset(pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)); + + if (bmiDone) + { + return A_ERROR; + } + + cid = A_CPU2LE32(BMI_READ_MEMORY); + + remaining = length; + + while (remaining) + { + // rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX; + rxlen = (remaining < 4) ? remaining : 4; + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + temp = A_CPU2LE32(address); + A_MEMCPY(&(pBMICmdBuf[offset]), &temp, sizeof(address)); + offset += sizeof(address); + temp = A_CPU2LE32(rxlen); + A_MEMCPY(&(pBMICmdBuf[offset]), &temp, sizeof(rxlen)); + offset += sizeof(length); + + status = bmiBufferSend(pCxt, pBMICmdBuf, offset); + if (status != A_OK) + { + return A_ERROR; + } + status = bmiBufferReceive(pCxt, pBMICmdBuf, rxlen, true); + if (status != A_OK) + { + return A_ERROR; + } + A_MEMCPY(&buffer[length - remaining], pBMICmdBuf, rxlen); + remaining -= rxlen; + address += rxlen; + } + + return A_OK; +} +#endif + +A_STATUS +BMIWriteMemory(void *pCxt, uint32_t address, uint8_t *buffer, uint32_t length) +{ + uint32_t cid; + uint32_t remaining, txlen, temp; + const uint32_t header = sizeof(cid) + sizeof(address) + sizeof(length); + // uint8_t alignedBuffer[BMI_DATASZ_MAX]; + uint8_t *src; + uint8_t *ptr; + + A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + header)); + memset(pBMICmdBuf, 0, BMI_DATASZ_MAX + header); + + if (bmiDone) + { + return A_ERROR; + } + + cid = A_CPU2LE32(BMI_WRITE_MEMORY); + + remaining = length; + while (remaining) + { + src = &buffer[length - remaining]; + if (remaining < (BMI_DATASZ_MAX - header)) + { + if (remaining & 3) + { + /* align it with 4 bytes */ + remaining = remaining + (4 - (remaining & 3)); + // memcpy(alignedBuffer, src, remaining); + // src = alignedBuffer; + } + txlen = remaining; + } + else + { + txlen = (BMI_DATASZ_MAX - header); + } + + ptr = pBMICmdBuf; + A_MEMCPY(ptr, &cid, sizeof(cid)); + ptr += sizeof(cid); + temp = A_CPU2LE32(address); + A_MEMCPY(ptr, &temp, sizeof(address)); + ptr += sizeof(address); + temp = A_CPU2LE32(txlen); + A_MEMCPY(ptr, &temp, sizeof(txlen)); + ptr += sizeof(txlen); + A_MEMCPY(ptr, src, txlen); + ptr += txlen; + + if (A_OK != bmiBufferSend(pCxt, pBMICmdBuf, (uint32_t)(ptr - pBMICmdBuf))) + { + return A_ERROR; + } + remaining -= txlen; + address += txlen; + } + + return A_OK; +} + +A_STATUS +BMIExecute(void *pCxt, uint32_t address, uint32_t *param) +{ + uint32_t cid; + uint32_t temp; + uint8_t *ptr; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param))); + memset(pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) + { + return A_ERROR; + } + + cid = A_CPU2LE32(BMI_EXECUTE); + + ptr = pBMICmdBuf; + A_MEMCPY(ptr, &cid, sizeof(cid)); + ptr += sizeof(cid); + temp = A_CPU2LE32(address); + A_MEMCPY(ptr, &temp, sizeof(address)); + ptr += sizeof(address); + A_MEMCPY(ptr, param, sizeof(*param)); + ptr += sizeof(*param); + + if (A_OK != bmiBufferSend(pCxt, pBMICmdBuf, (uint32_t)(ptr - pBMICmdBuf))) + { + return A_ERROR; + } + + if (A_OK != bmiBufferReceive(pCxt, pBMICmdBuf, sizeof(*param), false)) + { + return A_ERROR; + } + + A_MEMCPY(param, pBMICmdBuf, sizeof(*param)); + + return A_OK; +} + +A_STATUS +BMIReadSOCRegister(void *pCxt, uint32_t address, uint32_t *param) +{ + uint32_t cid; + A_STATUS status; + uint32_t offset, temp; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address))); + memset(pBMICmdBuf, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) + { + return A_ERROR; + } + + cid = A_CPU2LE32(BMI_READ_SOC_REGISTER); + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + temp = A_CPU2LE32(address); + A_MEMCPY(&(pBMICmdBuf[offset]), &temp, sizeof(address)); + offset += sizeof(address); + + status = bmiBufferSend(pCxt, pBMICmdBuf, offset); + if (status != A_OK) + { + return A_ERROR; + } + + status = bmiBufferReceive(pCxt, pBMICmdBuf, sizeof(*param), true); + if (status != A_OK) + { + return A_ERROR; + } + A_MEMCPY(param, pBMICmdBuf, sizeof(*param)); + + return A_OK; +} + +A_STATUS +BMIWriteSOCRegister(void *pCxt, uint32_t address, uint32_t param) +{ + uint32_t cid; + A_STATUS status; + uint32_t offset, temp; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param))); + memset(pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) + { + return A_ERROR; + } + + cid = A_CPU2LE32(BMI_WRITE_SOC_REGISTER); + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + temp = A_CPU2LE32(address); + A_MEMCPY(&(pBMICmdBuf[offset]), &temp, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&(pBMICmdBuf[offset]), ¶m, sizeof(param)); + offset += sizeof(param); + + status = bmiBufferSend(pCxt, pBMICmdBuf, offset); + + if (status != A_OK) + { + return A_ERROR; + } + + return A_OK; +} + +A_STATUS +BMIRawWrite(void *pCxt, uint8_t *buffer, uint32_t length) +{ + return bmiBufferSend(pCxt, buffer, length); +} + +A_STATUS +BMIRawRead(void *pCxt, uint8_t *buffer, uint32_t length, boolean want_timeout) +{ + return bmiBufferReceive(pCxt, buffer, length, want_timeout); +} + +#else + +/* STUB'd version when BMI is not used by the driver */ + +/* APIs visible to the driver */ +A_STATUS +BMIInit(void *pCxt) +{ + return A_ERROR; +} + +A_STATUS +BMIDone(void *pCxt) +{ + return A_ERROR; +} + +A_STATUS +BMIGetTargetInfo(void *pCxt, struct bmi_target_info *targ_info) +{ + return A_ERROR; +} + +A_STATUS +BMIWriteMemory(void *pCxt, uint32_t address, uint8_t *buffer, uint32_t length) +{ + return A_ERROR; +} + +A_STATUS +BMIExecute(void *pCxt, uint32_t address, uint32_t *param) +{ + return A_ERROR; +} + +A_STATUS +BMIReadSOCRegister(void *pCxt, uint32_t address, uint32_t *param) +{ + return A_ERROR; +} + +A_STATUS +BMIWriteSOCRegister(void *pCxt, uint32_t address, uint32_t param) +{ + return A_ERROR; +} + +A_STATUS +BMIRawWrite(void *pCxt, uint8_t *buffer, uint32_t length) +{ + return A_ERROR; +} + +A_STATUS +BMIRawRead(void *pCxt, uint8_t *buffer, uint32_t length, boolean want_timeout) +{ + return A_ERROR; +} + +#endif /* DRIVER_CONFIG_INCLUDE_BMI */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_diag.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_diag.c new file mode 100644 index 00000000000..23dd499bef5 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_diag.c @@ -0,0 +1,337 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include +#include "hw20_mbox_host_reg.h" +#include "atheros_wifi_api.h" + +/* prototypes */ +static A_STATUS Driver_SetAddressWindowRegister(void *pCxt, uint32_t RegisterAddr, uint32_t Address); + +/* Compile the 4BYTE version of the window register setup routine, + * This mitigates host interconnect issues with non-4byte aligned bus requests, some + * interconnects use bus adapters that impose strict limitations. + * Since diag window access is not intended for performance critical operations, the 4byte mode should + * be satisfactory even though it generates 4X the bus activity. */ + +#ifdef USE_4BYTE_REGISTER_ACCESS + +/* set the window address register (using 4-byte register access ). */ +/*****************************************************************************/ +/* Driver_SetAddressWindowRegister - Utility function to set the window + * register. This is used for diagnostic reads and writes. + * void *pCxt - the driver context. + * uint32_t RegisterAddr - The window register address. + * uint32_t Address - the target address. + *****************************************************************************/ +static A_STATUS Driver_SetAddressWindowRegister(void *pCxt, uint32_t RegisterAddr, uint32_t Address) +{ + A_STATUS status; + uint8_t addrValue[4]; + int32_t i; + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + Address = A_CPU2LE32(Address); + + for (i = 1; i <= 3; i++) + { + /* fill the buffer with the address byte value we want to hit 4 times*/ + addrValue[0] = ((uint8_t *)&Address)[i]; + addrValue[1] = addrValue[0]; + addrValue[2] = addrValue[0]; + addrValue[3] = addrValue[0]; + + A_NETBUF_CONFIGURE(pReq, (void *)addrValue, 0, 4, 4); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, RegisterAddr + i, false, 4); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + break; + } + } + + if (status != A_OK) + { + return status; + } + + A_NETBUF_CONFIGURE(pReq, (void *)&Address, 0, 4, 4); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, RegisterAddr, true, 4); + status = Hcd_DoPioExternalAccess(pCxt, pReq); + + return status; +} + +#else + +/*****************************************************************************/ +/* Driver_SetAddressWindowRegister - Utility function to set the window + * register. This is used for diagnostic reads and writes. + * void *pCxt - the driver context. + * uint32_t RegisterAddr - The window register address. + * uint32_t Address - the target address. + *****************************************************************************/ +static A_STATUS Driver_SetAddressWindowRegister(void *pCxt, uint32_t RegisterAddr, uint32_t Address) +{ + A_STATUS status; + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + + Address = A_CPU2LE32(Address); + + do + { + A_NETBUF_CONFIGURE(pReq, (((uint8_t *)(&Address)) + 1), (sizeof(uint32_t) - 1)); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, RegisterAddr + 1, true, (sizeof(uint32_t) - 1)); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + break; + } + + A_NETBUF_CONFIGURE(pReq, ((uint8_t *)(&Address)), sizeof(uint8_t)); + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, RegisterAddr, true, sizeof(uint8_t)); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + break; + } + } while (0); + + return status; +} + +#endif + +/*****************************************************************************/ +/* Driver_ReadRegDiag - Reads four bytes of data from the specified chip + * device address. + * void *pCxt - the driver context. + * uint32_t address - the device chip address to start the read. + * uint8_t *data - the start of data destination buffer. + *****************************************************************************/ +A_STATUS +Driver_ReadRegDiag(void *pCxt, uint32_t *address, uint32_t *data) +{ + A_STATUS status; + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + + A_NETBUF_CONFIGURE(pReq, data, 0, sizeof(uint32_t), sizeof(uint32_t)); + + do + { + /* set window register to start read cycle */ + if (A_OK != (status = Driver_SetAddressWindowRegister(pCxt, WINDOW_READ_ADDR_ADDRESS, *address))) + { + break; + } + + ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, WINDOW_DATA_ADDRESS, true, sizeof(uint32_t)); + + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + break; + } + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Driver_WriteRegDiag - Writes four bytes of data to the specified chip + * device address. + * void *pCxt - the driver context. + * uint32_t address - the device chip address to start the write. + * uint8_t *data - the start of data source buffer. + *****************************************************************************/ +A_STATUS +Driver_WriteRegDiag(void *pCxt, uint32_t *address, uint32_t *data) +{ + A_STATUS status; + + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + + A_NETBUF_CONFIGURE(pReq, data, 0, sizeof(uint32_t), sizeof(uint32_t)); + + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, WINDOW_DATA_ADDRESS, true, sizeof(uint32_t)); + + do + { + if (A_OK != (status = Hcd_DoPioExternalAccess(pCxt, pReq))) + { + break; + } + /* set window register, which starts the write cycle */ + if (A_OK != (status = Driver_SetAddressWindowRegister(pCxt, WINDOW_WRITE_ADDR_ADDRESS, *address))) + { + break; + } + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Driver_ReadDataDiag - Reads a buffer of data starting from address. Length + * of data is specified by length. Data is read from a contiguous chip + * address memory/register space. + * void *pCxt - the driver context. + * uint32_t address - the device chip address to start the read. + * uint8_t *data - the start of data destination buffer. + * uint32_t length - the length of data in bytes. + *****************************************************************************/ +A_STATUS +Driver_ReadDataDiag(void *pCxt, uint32_t address, uint8_t *data, uint32_t length) +{ + uint32_t count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) + { + if ((status = Driver_ReadRegDiag(pCxt, &address, (uint32_t *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +/*****************************************************************************/ +/* Driver_WriteDataDiag - Writes a buffer of data starting at address. Length + * of data is specified by length. Data is written to a contiguous chip + * address memory/register space. + * void *pCxt - the driver context. + * uint32_t address - the device chip address to start the write. + * uint8_t *data - the start of data source buffer. + * uint32_t length - the length of data in bytes. + *****************************************************************************/ +A_STATUS +Driver_WriteDataDiag(void *pCxt, uint32_t address, uint8_t *data, uint32_t length) +{ + uint32_t count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) + { + if ((status = Driver_WriteRegDiag(pCxt, &address, (uint32_t *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +#define REG_DUMP_COUNT_AR4100 60 +#define REG_DUMP_COUNT_AR4002 60 +#define REGISTER_DUMP_LEN_MAX 60 + +/*****************************************************************************/ +/* Driver_DumpAssertInfo - Collects assert information from chip and writes + * it to stdout. + * void *pCxt - the driver context. + * uint32_t *pData - buffer to store UINT32 results + * uint16_t *pLength - IN/OUT param to store length of buffer for IN and + * length of contents for OUT. + *****************************************************************************/ +A_STATUS +Driver_DumpAssertInfo(void *pCxt, uint32_t *pData, uint16_t *pLength) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint32_t address; + uint32_t regDumpArea = 0; + A_STATUS status = A_ERROR; + uint32_t regDumpCount = 0; + + do + { + if (*pLength < REGISTER_DUMP_LEN_MAX) + { + break; + } + /* clear it */ + *pLength = 0; + /* the reg dump pointer is copied to the host interest area */ + address = HOST_INTEREST_ITEM_ADDRESS(hi_failure_state); + address = TARG_VTOP(address); + + if (pDCxt->targetType == TARGET_TYPE_AR4100 || pDCxt->targetType == TARGET_TYPE_AR400X) + { + regDumpCount = REG_DUMP_COUNT_AR4100; + } + else + { + A_ASSERT(0); /* should never happen */ +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif + } + + /* read RAM location through diagnostic window */ + if (A_OK != (status = Driver_ReadRegDiag(pCxt, &address, ®DumpArea))) + { + A_ASSERT(0); /* should never happen */ +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif + } + + regDumpArea = A_LE2CPU32(regDumpArea); + + if (regDumpArea == 0) + { + /* no reg dump */ + break; + } + + regDumpArea = TARG_VTOP(regDumpArea); + + /* fetch register dump data */ + if (A_OK != + (status = Driver_ReadDataDiag(pCxt, regDumpArea, (uint8_t *)&pData[0], regDumpCount * (sizeof(uint32_t))))) + { + A_ASSERT(0); /* should never happen */ +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif + } + + *pLength = regDumpCount; + } while (0); + + return status; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_init.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_init.c new file mode 100644 index 00000000000..2fe0efbb45f --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_init.c @@ -0,0 +1,908 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hw20_apb_map.h" +#include "cmsis_os.h" + +//#include "hw4.0/hw/rtc_reg.h" +#if (DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD) +#include +#include "hw20_mbox_reg.h" +#endif /* DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD */ + +#define HI_OPTION_NUM_DEV_SHIFT 0x9 +#define HI_OPTION_FW_MODE_BSS_STA 0x1 +#define HI_OPTION_FW_MODE_AP 0x2 +#define HI_OPTION_FW_MODE_SHIFT 0xC + +/* 2 bits of hi_option flag are usedto represent 4 submodes */ +#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ +#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ +#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ +#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ +#define HI_OPTION_FW_SUBMODE_BITS 0x2 +#define HI_OPTION_FW_SUBMODE_SHIFT 0x14 + +/* hi_option_flag3 options */ +#define HI_OPTION_USE_OFFLOAD_P2P 0x01 + +#if (DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD) +uint32_t ar4XXX_boot_param = AR4XXX_PARAM_MODE_NORMAL | AR4XXX_PARAM_MODE_BMI; // AR4XXX_PARAM_RAW_QUAD; +#else +uint32_t ar4XXX_boot_param = AR4XXX_PARAM_MODE_NORMAL; // AR4XXX_PARAM_RAW_QUAD; +#endif /* DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD */ +uint32_t ar4xx_reg_domain = AR4XXX_PARAM_REG_DOMAIN_DEFAULT; +uint32_t last_driver_error; // Used to store the last error encountered by the driver + +/*****************************************************************************/ +/* ConnectService - Utility to set up a single endpoint service. + * void *pCxt - the driver context. + * HTC_SERVICE_CONNECT_REQ *pConnect - pointer to connect request + * structure. + *****************************************************************************/ +static A_STATUS ConnectService(void *pCxt, HTC_SERVICE_CONNECT_REQ *pConnect) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + A_MEMZERO(&response, sizeof(response)); + + if (A_OK != (status = HTC_ConnectService(pCxt, pConnect, &response))) + { + break; + } + + switch (pConnect->ServiceID) + { + case WMI_CONTROL_SVC: + if (pDCxt->wmiEnabled == true) + { + /* set control endpoint for WMI use */ + wmi_set_control_ep(pDCxt->pWmiCxt, response.Endpoint); + } + break; + case WMI_DATA_BE_SVC: + pDCxt->ac2EpMapping[WMM_AC_BE] = response.Endpoint; + pDCxt->ep2AcMapping[response.Endpoint] = WMM_AC_BE; + break; + case WMI_DATA_BK_SVC: + pDCxt->ac2EpMapping[WMM_AC_BK] = response.Endpoint; + pDCxt->ep2AcMapping[response.Endpoint] = WMM_AC_BK; + break; + case WMI_DATA_VI_SVC: + pDCxt->ac2EpMapping[WMM_AC_VI] = response.Endpoint; + pDCxt->ep2AcMapping[response.Endpoint] = WMM_AC_VI; + break; + case WMI_DATA_VO_SVC: + pDCxt->ac2EpMapping[WMM_AC_VO] = response.Endpoint; + pDCxt->ep2AcMapping[response.Endpoint] = WMM_AC_VO; + break; + default: + status = A_EINVAL; + break; + } + + } while (0); + + return status; +} + +/*****************************************************************************/ +/* SetupServices - Utility to set up endpoint services. + * void *pCxt - the driver context. + *****************************************************************************/ +static A_STATUS SetupServices(void *pCxt) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_REQ connect; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + (void)(pDCxt); + + do + { + A_MEMZERO(&connect, sizeof(connect)); + /* meta data is unused for now */ + connect.pMetaData = NULL; + connect.MetaDataLength = 0; + /* connect to control service */ + connect.ServiceID = WMI_CONTROL_SVC; + + if (A_OK != (status = ConnectService(pCxt, &connect))) + { + break; + } + + connect.LocalConnectionFlags |= HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING; + /* limit the HTC message size on the send path, although we can receive A-MSDU frames of + * 4K, we will only send ethernet-sized (802.3) frames on the send path. */ + connect.MaxSendMsgSize = WMI_MAX_TX_DATA_FRAME_LENGTH; + + /* for the remaining data services set the connection flag to reduce dribbling, + * if configured to do so */ + if (WLAN_CONFIG_REDUCE_CREDIT_DRIBBLE) + { + connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE; + /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value + * of 0-3 */ + connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + connect.ConnectionFlags |= HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF; + } + /* connect to best-effort service */ + connect.ServiceID = WMI_DATA_BE_SVC; + + if (A_OK != (status = ConnectService(pCxt, &connect))) + { + break; + } + + /* connect to back-ground + * map this to WMI LOW_PRI */ + connect.ServiceID = WMI_DATA_BK_SVC; + + if (A_OK != (status = ConnectService(pCxt, &connect))) + { + break; + } + + /* connect to Video service, map this to + * to HI PRI */ + connect.ServiceID = WMI_DATA_VI_SVC; + + if (A_OK != (status = ConnectService(pCxt, &connect))) + { + break; + } + + /* connect to VO service, this is currently not + * mapped to a WMI priority stream due to historical reasons. + * WMI originally defined 3 priorities over 3 mailboxes + * We can change this when WMI is reworked so that priorities are not + * dependent on mailboxes */ + connect.ServiceID = WMI_DATA_VO_SVC; + + if (A_OK != (status = ConnectService(pCxt, &connect))) + { + break; + } + + A_ASSERT(pDCxt->ac2EpMapping[WMM_AC_BE] != 0); + A_ASSERT(pDCxt->ac2EpMapping[WMM_AC_BK] != 0); + A_ASSERT(pDCxt->ac2EpMapping[WMM_AC_VI] != 0); + A_ASSERT(pDCxt->ac2EpMapping[WMM_AC_VO] != 0); + } while (0); + + return status; +} + +#if (DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD) +/*****************************************************************************/ +/* Driver_DownloadFirmwareBinary - Utility to download Board data + and athwlan firmware binary to target. + * void *pCxt - the driver context. + *****************************************************************************/ +uint32_t Driver_DownloadFirmwareBinary(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint32_t address = 0, param = 0; + + /* Temporarily disable system sleep */ + address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; + (BMIReadSOCRegister(pCxt, address, ¶m)); + param |= A_CPU2LE32(AR6K_OPTION_SLEEP_DISABLE | AR6K_OPTION_WDT_DISABLE); + (BMIWriteSOCRegister(pCxt, address, param)); + + address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; + (BMIReadSOCRegister(pCxt, address, ¶m)); + param |= A_CPU2LE32(WLAN_SYSTEM_SLEEP_DISABLE_SET(1)); + (BMIWriteSOCRegister(pCxt, address, param)); + + /* Set Option3 flag in host interest item to boot up + hostproxy application in firmware download mode */ + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_option_flag3)), (uint8_t *)¶m, 4) != A_OK) + { + return A_ERROR; + } + + param |= HI_OPTION_EN_HOST_PROXY_FW_DLOAD_MODE; + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_option_flag3)), (uint8_t *)¶m, 4) != + A_OK) + { + return A_ERROR; + } + +#if ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1 + /* Set the board data address in HOST interest item for + target to use it */ + param = A_CPU2LE32(AR400X_BOARD_DATA_ADDRESS); + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_board_data)), (uint8_t *)¶m, 4) != A_OK) + { + return A_ERROR; + } + + /* non-zero value of hi_board_data_initialized indicates that the + board data is valid for the target */ + param = A_CPU2LE32(1); + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } +#endif /* ATH_FIRMWARE_TARGET */ + + /* Download firmware binary only if exitAtBmi is false as possibly flash + agent could be attempting to flash the binary onto target flash memory */ + if (true != ath_custom_init.exitAtBmi) + { + /* Clear BMI mode in hi_flash_is_present as we are already in BMI mode */ + param = A_CPU2LE32(AR4XXX_PARAM_MODE_NORMAL | ar4xx_reg_domain); + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_flash_is_present)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + + /* This is just a reference implementation to download the firmware + binary. If memory needs to be optimized, the binary file can be stored + in the host flash file system and can be opened, read in chunks using file + system APIs and can be downloaded using below BMI API */ + BMIWriteMemory(pCxt, BMI_SEGMENTED_WRITE_ADDR, (uint8_t *)&ath_fw_binary_buff, sizeof(ath_fw_binary_buff)); + } + + return 0; +} + +#endif /* DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD */ + +/*****************************************************************************/ +/* Driver_ContextInit - Initializes the drivers COMMON context. The allocation + * for the context should be made by the caller. This function will call + * the Custom_DRiverContextInit to perform any system specific initialization + * Look to Driver_ContextDeInit() to undo what gets done by this function. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Driver_ContextInit(void *pCxt) +{ + uint8_t i; + osMutexAttr_t attr = { 0 }; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + /* most elements are initialized by setting to zero the rest are explicitly + * initialized. boolean are explicit as it is not obvious what false might be */ + A_MEMZERO(pDCxt, sizeof(A_DRIVER_CONTEXT)); + pDCxt->driver_up = false; + pDCxt->rxBufferStatus = false; + pDCxt->hostVersion = AR6K_SW_VERSION; + pDCxt->wmiReady = false; + pDCxt->wmiEnabled = false; + pDCxt->wmmEnabled = false; + pDCxt->chipDown = true; + pDCxt->strrclState = STRRCL_ST_DISABLED; + pDCxt->strrclBlock = false; + pDCxt->wpsState = false; + + attr.name = "qca400x_mutex"; + attr.cb_mem = &pDCxt->context_mutex_mem; + attr.cb_size = sizeof(pDCxt->context_mutex_mem); + attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; + pDCxt->apiMutex = osMutexNew(&attr); + if (NULL == pDCxt->apiMutex) + return A_ERROR; + + /* Connection element for first device */ + pDCxt->conn[0].networkType = INFRA_NETWORK; + pDCxt->conn[0].dot11AuthMode = OPEN_AUTH; + pDCxt->conn[0].wpaAuthMode = NONE_AUTH; + pDCxt->conn[0].wpaPairwiseCrypto = NONE_CRYPT; + pDCxt->conn[0].wpaGroupCrypto = NONE_CRYPT; + pDCxt->conn[0].wpaPmkValid = false; + pDCxt->conn[0].isConnected = false; + pDCxt->conn[0].isConnectPending = false; + +#if (WLAN_NUM_OF_DEVICES > 1) + pDCxt->conn[1].networkType = INFRA_NETWORK; + pDCxt->conn[1].dot11AuthMode = OPEN_AUTH; + pDCxt->conn[1].wpaAuthMode = NONE_AUTH; + pDCxt->conn[1].wpaPairwiseCrypto = NONE_CRYPT; + pDCxt->conn[1].wpaGroupCrypto = NONE_CRYPT; + pDCxt->conn[1].wpaPmkValid = false; + pDCxt->conn[1].isConnected = false; + pDCxt->conn[1].isConnectPending = false; +#endif + + pDCxt->scanDone = false; + /* through measurement, it's in power save mode by default.*/ + pDCxt->userPwrMode = REC_POWER; + pDCxt->enabledSpiInts = ATH_SPI_INTR_PKT_AVAIL | ATH_SPI_INTR_LOCAL_CPU_INTR; + pDCxt->mboxAddress = HIF_MBOX_START_ADDR(HIF_ACTIVE_MBOX_INDEX); /* the address for mailbox reads/writes. */ + pDCxt->blockSize = HIF_MBOX_BLOCK_SIZE; /* the mailbox block size */ + pDCxt->blockMask = pDCxt->blockSize - 1; /* the mask derived from BlockSize */ + pDCxt->padBuffer = A_MALLOC(pDCxt->blockSize, MALLOC_ID_CONTEXT); + pDCxt->htcStart = false; + pDCxt->macProgramming = false; +#if MANUFACTURING_SUPPORT + pDCxt->testResp = false; +#endif + for (i = 0; i < ENDPOINT_MANAGED_MAX; i++) + { + pDCxt->ep[i].epIdx = i; + } + + if (NULL == pDCxt->padBuffer) + return A_ERROR; + + return CUSTOM_DRIVER_CXT_INIT(pCxt); +} + +/*****************************************************************************/ +/* Driver_ContextDeInit - Undoes any work performed by Driver_ContextInit. + * Used as part of the shutdown process. Calls Driver_ContextDeInit() + * to cleanup any work done by Driver_ContextInit(). + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Driver_ContextDeInit(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + CUSTOM_DRIVER_CXT_DEINIT(pCxt); + + if (pDCxt->padBuffer != NULL) + { + A_FREE(pDCxt->padBuffer, MALLOC_ID_CONTEXT); + pDCxt->padBuffer = NULL; + } + + return A_OK; +} + +/*****************************************************************************/ +/* Driver_Init - inits any HW resources for HW access. + * Turns CHIP on via GPIO if necessary. + * Performs initial chip interaction. + * If the system has a dedicated driver thread then + * this function should be called by the dedicated thread. + * If not then this function should be called between + * calls to api_InitStart and api_InitFinish + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Driver_Init(void *pCxt) +{ + A_STATUS status; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + A_EVENT_INIT(&GET_DRIVER_CXT(p_Global_Cxt)->driverWakeEvent, kEventAutoClear); + A_EVENT_INIT(&GET_DRIVER_CXT(p_Global_Cxt)->userWakeEvent, kEventManualClear); +#if T_SELECT_VER1 + A_EVENT_INIT(&GET_DRIVER_CXT(p_Global_Cxt)->sockSelectWakeEvent, kEventManualClear); +#endif // T_SELECT_VER1 + + do + { + /* initialize various protection elements */ + if (A_OK != (status = RXBUFFER_ACCESS_INIT(pCxt))) + { + break; + } + + if (A_OK != (status = TXQUEUE_ACCESS_INIT(pCxt))) + { + break; + } + + if (A_OK != (status = IRQEN_ACCESS_INIT(pCxt))) + { + break; + } + + if (A_OK != (status = DRIVER_SHARED_RESOURCE_ACCESS_INIT(pCxt))) + { + break; + } + /* - init hw resources */ + if (A_OK != (status = CUSTOM_HW_INIT(pCxt))) + { + break; + } + /* - Power up device */ + HW_PowerUpDown(pCxt, 1); + + Api_BootProfile(pCxt, BOOT_PROFILE_POWER_UP); + + /* - bring chip CPU out of reset */ + if (A_OK != (status = Hcd_Init(pCxt))) + { + break; + } + + /* It is necessary to postpone further SPI commands, + * until WiFI gets ready. Empirical value is 100ms */ + A_MDELAY(100); + + /* - initiate communication with chip firmware */ + if (A_OK != (status = Driver_BootComm(pCxt))) + { + break; + } + + if ((ar4XXX_boot_param & AR4XXX_PARAM_MODE_MASK) == AR4XXX_PARAM_MODE_BMI) + { + BMIInit(pCxt); + } + + /* - acquire target type */ + if (A_OK != (status = Driver_GetTargetInfo(pCxt))) + { + break; + } + /* - perform any BMI chip configuration */ + if (ath_custom_init.Driver_BMIConfig != NULL) + { + if (A_OK != (status = ath_custom_init.Driver_BMIConfig(pCxt))) + { + break; + } + } + +#if (DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD) + Driver_DownloadFirmwareBinary(pCxt); +#endif /* DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD */ + + /* - perform any target configuration */ + if (ath_custom_init.Driver_TargetConfig != NULL) + { + if (A_OK != (status = ath_custom_init.Driver_TargetConfig(pCxt))) + { + break; + } + } + /* - choose wmi or not wmi */ + if (ath_custom_init.skipWmi == false) + { + pDCxt->pWmiCxt = wmi_init(pCxt); + pDCxt->wmiEnabled = true; +#if WLAN_CONFIG_11N_AGGR_SUPPORT + pDCxt->pAggrCxt = aggr_init(); +#endif + } + + /* - alternate boot mode - exit driver init with BMI active */ + if (ath_custom_init.exitAtBmi) + { + break; + } + + if ((ar4XXX_boot_param & AR4XXX_PARAM_MODE_MASK) == AR4XXX_PARAM_MODE_BMI) + { + /* - done with BMI; call BMIDone */ + if (A_OK != (status = BMIDone(pCxt))) + { + break; + } + } + + /* - wait for HTC setup complete */ + if (A_OK != (status = HTC_WaitTarget(pCxt))) + { + break; + } + /* - setup other non-htc endpoints */ + if (A_OK != (status = SetupServices(pCxt))) + { + break; + } + + /* - start HTC */ + if (A_OK != (status = HTC_Start(pCxt))) + { + break; + } + + } while (0); + + if (status == A_OK) + { + pDCxt->chipDown = false; + pDCxt->driver_up = true; + pDCxt->driverShutdown = false; + } + + return status; +} + +/*****************************************************************************/ +/* Driver_DeInit - Undoes any work performed by Driver_Init. + * Used as part of the shutdown process. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Driver_DeInit(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + Hcd_Deinitialize(pCxt); /* not necessary if HW_PowerUpDown() actually + shuts down chip */ + HW_PowerUpDown(pCxt, 0); + CUSTOM_HW_DEINIT(pCxt); + + if (pDCxt->pWmiCxt) + { + wmi_shutdown(pDCxt->pWmiCxt); + pDCxt->pWmiCxt = NULL; + } +#if WLAN_CONFIG_11N_AGGR_SUPPORT + if (pDCxt->pAggrCxt) + { + aggr_deinit(pDCxt->pAggrCxt); + pDCxt->pAggrCxt = NULL; + } +#endif + + RXBUFFER_ACCESS_DESTROY(pCxt); + TXQUEUE_ACCESS_DESTROY(pCxt); + IRQEN_ACCESS_DESTROY(pCxt); + DRIVER_SHARED_RESOURCE_ACCESS_DESTROY(pCxt); + + pDCxt->driver_up = false; + A_EVENT_DELETE(&GET_DRIVER_CXT(p_Global_Cxt)->userWakeEvent); + A_EVENT_DELETE(&GET_DRIVER_CXT(p_Global_Cxt)->driverWakeEvent); +#if T_SELECT_VER1 + A_EVENT_DELETE(&GET_DRIVER_CXT(p_Global_Cxt)->sockSelectWakeEvent); +#endif // T_SELECT_VER1 + + return A_OK; +} + +/*****************************************************************************/ +/* Driver_GetTargetInfo - Used to get the device target info which includes + * the target version and target type. the results are stored in the + * context. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Driver_GetTargetInfo(void *pCxt) +{ + A_STATUS status = A_OK; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + struct bmi_target_info targ_info = {0}; + + if ((ar4XXX_boot_param & AR4XXX_PARAM_MODE_MASK) == AR4XXX_PARAM_MODE_BMI) + { + status = BMIGetTargetInfo(pCxt, &targ_info); + pDCxt->targetVersion = targ_info.target_ver; + pDCxt->targetType = targ_info.target_type; + } + else + { + /* hardcoded for boottime speedup */ + pDCxt->targetVersion = ATH_FIRMWARE_TARGET; + pDCxt->targetType = TARGET_TYPE; + } + + return status; +} + +/*****************************************************************************/ +/* Driver_TargReset - This function performs a warm reset operation on the + * wifi CPU after setting up firmware so that it can discover the + * nvram config structure. + * void *pCxt - the driver context. + *****************************************************************************/ +static uint16_t Driver_TargReset(void *pCxt) +{ +#if ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 + volatile uint32_t param; + + if ((ar4XXX_boot_param & AR4XXX_PARAM_MODE_MASK) == AR4XXX_PARAM_MODE_NORMAL) + { + do + { + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(AR4100_NVRAM_SAMPLE_ADDR), (uint8_t *)¶m, 4) != A_OK) + { + return A_ERROR; + } + } while (param != A_CPU2LE32(AR4100_NVRAM_SAMPLE_VAL)); + + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(AR4100_CONFIGFOUND_ADDR), (uint8_t *)¶m, 4) != A_OK) + { + return A_ERROR; + } + + if (param == A_CPU2LE32(AR4100_CONFIGFOUND_VAL)) + { + /* force config_found value */ + param = 0xffffffff; + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(AR4100_CONFIGFOUND_ADDR), (uint8_t *)¶m, 4) != A_OK) + { + return A_ERROR; + } + /* instruct ROM to preserve nvram values */ + param = A_CPU2LE32(HI_RESET_FLAG_PRESERVE_NVRAM_STATE); + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_reset_flag)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + /* instruct ROM to parse hi_reset_flag */ + param = A_CPU2LE32(HI_RESET_FLAG_IS_VALID); + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_reset_flag_valid)), + (uint8_t *)¶m, 4) != A_OK) + { + return A_ERROR; + } + /* clear hi_refclk_hz to identify reset point */ + param = A_CPU2LE32(0x00); + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_refclk_hz)), (uint8_t *)¶m, 4) != + A_OK) + { + return A_ERROR; + } + /* reset CPU */ + param = A_CPU2LE32(WLAN_RESET_CONTROL_WARM_RST_MASK); + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(RTC_BASE_ADDRESS | RESET_CONTROL_ADDRESS), (uint8_t *)¶m, 4) != + A_OK) + { + return A_ERROR; + } + /* force delay before further chip access after reset */ + CUSTOM_HW_USEC_DELAY(pCxt, 1000); + + return 1; + } + } +#else + UNUSED_ARGUMENT(pCxt); +#endif + return 0; +} + +/*****************************************************************************/ +/* Driver_BootComm - Communicates with the device using the diagnostic + * window to perform various interactions during the boot process. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Driver_BootComm(void *pCxt) +{ + volatile uint32_t param; + uint8_t resetpass = 0; + + if (ath_custom_init.Driver_BootComm != NULL) + { + return ath_custom_init.Driver_BootComm(pCxt); + } + +#if (ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 || ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1) + /* interact with host_proxy via HOST_INTEREST to control BMI active */ + + do + { +#if ENABLE_FPGA_BUILD + HW_USEC_DELAY(pCxt, 4000); +#endif + // On the QCA4004, the code sometimes hits one of the A_ASSERTs if this delay + // is not present. To be studied in detail later (THK, 2016-Jan) + A_MDELAY(4); + do + { + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_refclk_hz)), (uint8_t *)¶m, 4) != + A_OK) + { + return A_ERROR; + } + // printf("%d\r\n", param); + } while (param != A_CPU2LE32(EXPECTED_REF_CLK_AR4100) && param != A_CPU2LE32(EXPECTED_REF_CLK_AR400X)); + + Api_BootProfile(pCxt, BOOT_PROFILE_READ_REFCLK); + +#if 0 // Enabling firmware UART print and setting baud rate to 115200 + param = A_CPU2LE32(1); + if (Driver_WriteDataDiag(pCxt, + TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_serial_enable)), + (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + + param = A_CPU2LE32(115200); + if (Driver_WriteDataDiag(pCxt, + TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_desired_baud_rate)), + (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } +#endif + + param = A_CPU2LE32(0x31); + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_pwr_save_flags)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + +/* wait host_proxy ready */ +#if ENABLE_FPGA_BUILD + do + { + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_flash_is_present)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + } while ((param & HOST_PROXY_BOOTCTL_MASK) != A_CPU2LE32(HOST_PROXY_INIT)); +#endif + /* this code is called prior to BMIGetTargInfo so we must assume AR6003 */ + param = A_CPU2LE32(ar4XXX_boot_param | ar4xx_reg_domain); + + Api_BootProfile(pCxt, BOOT_PROFILE_BOOT_PARAMETER); + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_flash_is_present)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + + // Api_BootProfile(pCxt, 0x02); + if (WLAN_NUM_OF_DEVICES == 1) + { + param = ((1 << HI_OPTION_NUM_DEV_SHIFT) | (HI_OPTION_FW_MODE_BSS_STA << HI_OPTION_FW_MODE_SHIFT) | + (1 << HI_OPTION_FW_BRIDGE_SHIFT)) | + HI_OPTION_DISABLE_DBGLOG; + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_option_flag)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + } + else + { + /* Set P2P Offload support */ + param = HI_OPTION_USE_OFFLOAD_P2P; + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_option_flag3)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + /* Set number of Device and device mode + device 0 - P2P Device ; device 1 - IEEE STA */ + param = ((2 << HI_OPTION_NUM_DEV_SHIFT) | + (((HI_OPTION_FW_MODE_BSS_STA << 2 | HI_OPTION_FW_MODE_BSS_STA)) << HI_OPTION_FW_MODE_SHIFT) | + (((HI_OPTION_FW_SUBMODE_NONE << HI_OPTION_FW_SUBMODE_BITS) | HI_OPTION_FW_SUBMODE_P2PDEV) + << HI_OPTION_FW_SUBMODE_SHIFT) | + (1 << HI_OPTION_FW_BRIDGE_SHIFT)); + + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_option_flag)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + +#if !ENABLE_SCC_MODE + /* Enable MCC */ + if (Driver_ReadDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_option_flag2)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } + + param |= HI_OPTION_MCC_ENABLE; + if (Driver_WriteDataDiag(pCxt, TARG_VTOP(HOST_INTEREST_ITEM_ADDRESS(hi_option_flag2)), (uint8_t *)¶m, + 4) != A_OK) + { + return A_ERROR; + } +#endif /* ENABLE_SCC_MODE */ + } + + } while (resetpass++ < 1 && Driver_TargReset(pCxt)); + +#else + UNUSED_ARGUMENT(param); + UNUSED_ARGUMENT(loop); +#endif + return A_OK; +} + +#if (DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD) +A_STATUS Driver_StoreRecallFirmwareDownload(void *pCxt) +{ + A_STATUS status = A_OK; + + do + { + if ((ar4XXX_boot_param & AR4XXX_PARAM_MODE_MASK) == AR4XXX_PARAM_MODE_BMI) + { + BMIInit(pCxt); + } + + /* - acquire target type */ + if (A_OK != (status = Driver_GetTargetInfo(pCxt))) + { + break; + } + /* - perform any BMI chip configuration */ + if (ath_custom_init.Driver_BMIConfig != NULL) + { + if (A_OK != (status = ath_custom_init.Driver_BMIConfig(pCxt))) + { + break; + } + } + + /* Download the firmware binary */ + Driver_DownloadFirmwareBinary(pCxt); + + /* - perform any target configuration */ + if (ath_custom_init.Driver_TargetConfig != NULL) + { + if (A_OK != (status = ath_custom_init.Driver_TargetConfig(pCxt))) + { + break; + } + } + + if ((ar4XXX_boot_param & AR4XXX_PARAM_MODE_MASK) == AR4XXX_PARAM_MODE_BMI) + { + /* - done with BMI; call BMIDone */ + if (A_OK != (status = BMIDone(pCxt))) + { + break; + } + } + } while (0); + + return status; +} +#endif /* DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_main.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_main.c new file mode 100644 index 00000000000..1f4502367be --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_main.c @@ -0,0 +1,902 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mbed_rtos_storage.h" + +#include "atheros_wifi_api.h" +#include "atheros_wifi_internal.h" + +/*****************************************************************************/ +/********** IMPLEMENTATION **********/ +/*****************************************************************************/ + +osThreadId_t atheros_wifi_task_id = NULL; +mbed_rtos_storage_thread_t thread_cb; + +uint32_t g_totAlloc = 0; +uint32_t g_poolid = 0xffffffff; + +/*****************************************************************************/ +/* Driver_Main - This is the top level entry point for the Atheros wifi driver + * This should be called from either a dedicated thread running in a loop or, + * in the case of single threaded systems it should be called periodically + * from the main loop. Also, if in a single threaded system a API call + * requires synchronous completion then it may be necessary to call this + * function from within the API call. + * void *pCxt - the driver context. + * uint8_t scope - Limits/allows what type of activity may be processed. + * Options are any combination of DRIVER_SCOPE_TX + DRIVER_SCOPE_RX. + * boolean *pCanBlock - used to report to caller whether the driver is + * in a state where it is safe to block until further notice. + * uint16_t *pBlock_msec - used to report to caller how long the driver + * may block for. if zero then driver can block indefinitely. + *****************************************************************************/ +// uint32_t g_drv_progress = 0; +A_STATUS +Driver_Main(void *pCxt, uint8_t scope, boolean *pCanBlock, uint16_t *pBlock_msec) +{ + void *pReq; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + HW_ProcessPendingInterrupts(pCxt); // IGX_UD_CHANGES + + /* This is where packets are received from the + * wifi device. Because system buffers must be + * available to receive a packet we only call into + * this function if we know that buffers are + * available to satisfy the operation. + */ + if ((scope & DRIVER_SCOPE_RX) && true == Driver_RxReady(pCxt)) + { + // g_drv_progress = 0; + pDCxt->driver_state = DRIVER_STATE_RX_PROCESSING; + pReq = pDCxt->pRxReq; + pDCxt->pRxReq = NULL; + if (A_OK != Driver_RecvPacket(pCxt, pReq)) + { + /* if this happens it is a critical error */ + A_ASSERT(0); + } + /* FIXME: as an optimization the next lookahead may have + * been acquired from the trailer of the previous rx packet. + * in that case we should pre-load the lookahead so as to + * avoid reading it from the registers. */ + /* reset the lookahead for the next read operation */ + pDCxt->lookAhead = 0; + /* check to see if a deferred bus request has completed. if so + * process it. */ + if (pDCxt->booleans & SDHD_BOOL_DMA_COMPLETE) + { + /* get the request */ + if (A_OK == Driver_CompleteRequest(pCxt, pDCxt->spi_hcd.pCurrentRequest)) + { + /* clear the pending request and the boolean */ + pDCxt->spi_hcd.pCurrentRequest = NULL; + pDCxt->booleans &= ~SDHD_BOOL_DMA_COMPLETE; + } + } + } + + pDCxt->driver_state = DRIVER_STATE_PENDING_CONDITION_D; + + if ((scope & DRIVER_SCOPE_TX) && true == Driver_TxReady(pCxt)) + { + // g_drv_progress = 0; + pDCxt->driver_state = DRIVER_STATE_TX_PROCESSING; + /* after processing any outstanding device interrupts + * see if there is a packet that requires transmitting + */ + if (pDCxt->txQueue.count) + { + /* accesslock here to sync with threads calling + * submit TX + */ + TXQUEUE_ACCESS_ACQUIRE(pCxt); + { + pReq = A_NETBUF_DEQUEUE(&(pDCxt->txQueue)); + } + TXQUEUE_ACCESS_RELEASE(pCxt); + + if (pReq != NULL) + { + Driver_SendPacket(pCxt, pReq); + } + } + } + + pDCxt->driver_state = DRIVER_STATE_PENDING_CONDITION_E; + + /* execute any asynchronous/special request when possible */ + if (0 == (pDCxt->booleans & SDHD_BOOL_DMA_IN_PROG) && pDCxt->asynchRequest) + { + // g_drv_progress = 0; + pDCxt->driver_state = DRIVER_STATE_ASYNC_PROCESSING; + pDCxt->asynchRequest(pCxt); + pDCxt->driver_state = DRIVER_STATE_PENDING_CONDITION_F; + } + + pDCxt->driver_state = DRIVER_STATE_PENDING_CONDITION_G; + /* allow caller to block if all necessary conditions are satisfied */ + if (pCanBlock) + { + if ((pDCxt->spi_hcd.PendingIrqAcks == 0 || pDCxt->rxBufferStatus == false) && + (pDCxt->spi_hcd.IrqDetected == false) && (pDCxt->txQueue.count == 0 || Driver_TxReady(pCxt) == false) && + (0 == (pDCxt->booleans & SDHD_BOOL_DMA_COMPLETE))) + { + *pCanBlock = true; + + if (pDCxt->creditDeadlock == true) + { + if (pBlock_msec) + { + *pBlock_msec = DEADLOCK_BLOCK_MSEC; + } + + pDCxt->creditDeadlockCounter++; + } + + pDCxt->driver_state = DRIVER_STATE_IDLE; + } + else + { + *pCanBlock = false; + } + } + + // Used for testing purpose + // A_MDELAY(1); + // g_drv_progress++; + // if (g_drv_progress == 20) + // { + // extern A_STATUS DoPioWriteInternal(void *pCxt, uint16_t Addr, uint32_t Value); + // DoPioWriteInternal(pCxt, ATH_SPI_INTR_ENABLE_REG, 0x1f); + // g_drv_progress = 0; + // } + + return A_OK; +} + +/*****************************************************************************/ +/* Driver_ReportRxBuffStatus - Tracks availability of Rx Buffers for those + * systems that have a limited pool. The driver quearies this status before + * initiating a RX packet transaction. + * void *pCxt - the driver context. + * boolean status - new status true - RX buffers are available, + * false - RX buffers are not available. + *****************************************************************************/ + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) +uint8_t GetQueueIndexByEPID(uint8_t epid) +{ + uint8_t i; + + for (i = 0; i < 8; i++) + if (GET_QUEUE_MASK(i) & (1 << epid)) + break; + if (i >= 1 && i < 8) + i = 7; + return i; +} + +uint8_t GetQueueCtrlIndexByEPID(uint8_t epid) +{ + uint8_t i; + + for (i = 0; i < 8; i++) + if (GET_QUEUE_MASK(i) & (1 << epid)) + break; + return i; +} + +void Driver_ReportRxBuffStatus(void *pCxt, boolean status, uint8_t epid) +{ + boolean oldStatus; // CHECKME + uint8_t bufNdx; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + bufNdx = GetQueueIndexByEPID(epid); + /* NOTE: Dont acquire the lock here instead the + * caller should acquire this lock if necessary prior to calling this function */ + // RXBUFFER_ACCESS_ACQUIRE(pCxt); + + oldStatus = pDCxt->rxBufferStatus; + + if (status) + { + pDCxt->rxMultiBufferStatus |= 1 << bufNdx; + } + else + { + pDCxt->rxMultiBufferStatus &= ~(1 << bufNdx); + } + pDCxt->rxBufferStatus = (pDCxt->rxMultiBufferStatus != 0); + + // RXBUFFER_ACCESS_RELEASE(pCxt); + /* the driver thread may have blocked on this + * status so conditionally wake up the thread + * via QueueWork */ + if ((oldStatus == false) && (status == true)) + { + if (pDCxt->hcd.PendingIrqAcks) + { + DRIVER_WAKE_DRIVER(pCxt); + } + } +} +#else +void Driver_ReportRxBuffStatus(void *pCxt, boolean status) +{ + boolean oldStatus; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + /* NOTE: Dont acquire the lock here instead the + * caller should acquire this lock if necessary prior to calling this function */ + // RXBUFFER_ACCESS_ACQUIRE(pCxt); + { + oldStatus = pDCxt->rxBufferStatus; + pDCxt->rxBufferStatus = status; + } + // RXBUFFER_ACCESS_RELEASE(pCxt); + /* the driver thread may have blocked on this + * status so conditionally wake up the thread + * via QueueWork */ + if (oldStatus == false && status == true) + { + if (pDCxt->spi_hcd.PendingIrqAcks) + { + DRIVER_WAKE_DRIVER(pCxt); + } + } +} +#endif + +/*****************************************************************************/ +/* Driver_CompleteRequest - Completes a deferred request. One that finished + * asynchronously. Such a request must have a non-null callback that will + * be called by this function to fullfill the operation. + * void *pCxt - the driver context. + * void *pReq - the bus request object. + *****************************************************************************/ +A_STATUS +Driver_CompleteRequest(void *pCxt, void *pReq) +{ + A_STATUS status = A_ERROR; + void (*cb)(void *, void *); + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + /* A hardware WAR exists whereby interrupts from the device are disabled + * during an ongoing bus transaction. This function is called when + * the bus transaction completes. if irqMask is set then it means that + * interrupts should be re-enabled */ + if (pDCxt->spi_hcd.irqMask) + { + Hcd_UnmaskInterrupts(pCxt, pDCxt->spi_hcd.irqMask); + pDCxt->spi_hcd.irqMask = 0; + } + + if (pReq != NULL && NULL != (cb = A_NETBUF_GET_ELEM(pReq, A_REQ_CALLBACK))) + { + cb(pCxt, pReq); + status = A_OK; + } + else + { + A_ASSERT(0); + } + + return status; +} + +/*****************************************************************************/ +/* Driver_TxReady - Determines whether it is safe to start a TX operation. If + * a TX operation can be started this function returns true else false. + * void *pCxt - the driver context. + *****************************************************************************/ +boolean Driver_TxReady(void *pCxt) +{ + boolean res = false; + void *pReq; + A_ENDPOINT_T *pEp; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + pDCxt->creditDeadlock = false; + + do + { + /* there can be no errors */ + if (pDCxt->booleans & SDHD_BOOL_FATAL_ERROR) + { + break; + } + /* there can be no in-complete requests */ + if ((pDCxt->booleans & SDHD_BOOL_DMA_IN_PROG) || (pDCxt->booleans & SDHD_BOOL_DMA_COMPLETE) || + /* the write buffer watermark interrupt must not be configured */ + (pDCxt->booleans & SDHD_BOOL_DMA_WRITE_WAIT_FOR_BUFFER)) + { + break; + } + + /* there must be enough credits for the target endpoint */ + if (NULL == (pReq = A_NETBUF_PEEK_QUEUE(&(pDCxt->txQueue)))) + { + break; + } + + if (NULL == (pEp = Util_GetEndpoint(pCxt, A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)))) + { + break; + } + /* ensure as sanity check that the request length is less than a credit length */ + if (pDCxt->creditSize < DEV_CALC_SEND_PADDED_LEN(pDCxt, A_NETBUF_LEN(pReq))) + { + // THIS IS AN ERROR AS REQUESTS SHOULD NEVER EXCEED THE CREDIT SIZE + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif + } +#if RESERVE_ONE_CREDIT_FOR_CONTROL + if ((pEp->epIdx == 0) || (pEp->epIdx == 1)) + { + /* confirm there are enough credits for this transfer */ + if (0 == pEp->credits) + { + // if(pDCxt->rxBufferStatus == false) + { + /* need to use alternate mode to acquire credits */ + Htc_GetCreditCounterUpdate(pCxt, A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)); + + if (0 == pEp->credits) + { /* test again in case no new credits were acquired */ + if (pDCxt->rxBufferStatus == false) + { + /* with no rx buffers to receive a credit report and no interrupt + * credits a condition exists where the driver may become deadlocked. + * Hence the creditDeadlock boolean is set to prevent the driver from + * sleeping. this will cause the driver to poll for credits until + * the condition is passed. + */ + pDCxt->creditDeadlock = true; +#if 0 + assert(0); + if(pDCxt->creditDeadlockCounter >= MAX_CREDIT_DEADLOCK_ATTEMPTS){ + /* This is a serious condition that can be brought about by + * a flood of RX packets which generate TX responses and do not + * return the RX buffer to the driver until the TX response + * completes. To mitigate this situation purge the tx queue + * of any packets on data endpoints. + */ + Driver_DropTxDataPackets(pCxt); + pDCxt->creditDeadlockCounter = 0; + } +#endif + } + + break; + } + } + // else{ + // break;/* wait for credit report from device */ + //} + } + } + + else + { + /* confirm there are enough credits for this transfer */ + if (pEp->credits <= 1) + { + // if(pDCxt->rxBufferStatus == false) + { + /* need to use alternate mode to acquire credits */ + Htc_GetCreditCounterUpdate(pCxt, A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)); + + if (pEp->credits <= 1) + { /* test again in case no new credits were acquired */ + if (pDCxt->rxBufferStatus == false) + { + /* with no rx buffers to receive a credit report and no interrupt + * credits a condition exists where the driver may become deadlocked. + * Hence the creditDeadlock boolean is set to prevent the driver from + * sleeping. this will cause the driver to poll for credits until + * the condition is passed. + */ + pDCxt->creditDeadlock = true; +#if 0 + if(pDCxt->creditDeadlockCounter >= MAX_CREDIT_DEADLOCK_ATTEMPTS){ + /* This is a serious condition that can be brought about by + * a flood of RX packets which generate TX responses and do not + * return the RX buffer to the driver until the TX response + * completes. To mitigate this situation purge the tx queue + * of any packets on data endpoints. + */ + Driver_DropTxDataPackets(pCxt); + pDCxt->creditDeadlockCounter = 0; + } +#endif + } + + break; + } + } + // else{ + // break;/* wait for credit report from device */ + //} + } + + } /*(pEp->epIdx == 0) || (pEp->epIdx == 1)*/ +#else + if (0 == pEp->credits) + { + // if(pDCxt->rxBufferStatus == false) + { + /* need to use alternate mode to acquire credits */ + Htc_GetCreditCounterUpdate(pCxt, A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)); + + if (0 == pEp->credits) + { /* test again in case no new credits were acquired */ + if (pDCxt->rxBufferStatus == false) + { + /* with no rx buffers to receive a credit report and no interrupt + * credits a condition exists where the driver may become deadlocked. + * Hence the creditDeadlock boolean is set to prevent the driver from + * sleeping. this will cause the driver to poll for credits until + * the condition is passed. + */ + pDCxt->creditDeadlock = true; +#if 1 + if(pDCxt->creditDeadlockCounter >= MAX_CREDIT_DEADLOCK_ATTEMPTS){ + /* This is a serious condition that can be brought about by + * a flood of RX packets which generate TX responses and do not + * return the RX buffer to the driver until the TX response + * completes. To mitigate this situation purge the tx queue + * of any packets on data endpoints. + */ + Driver_DropTxDataPackets(pCxt); + pDCxt->creditDeadlockCounter = 0; + } +#endif + } + + break; + } + } + // else{ + // break;/* wait for credit report from device */ + //} + } +#endif + + pDCxt->creditDeadlockCounter = 0; + + /* there must be enough write buffer space in the target fifo */ + if (pDCxt->spi_hcd.WriteBufferSpace < + DEV_CALC_SEND_PADDED_LEN(pDCxt, A_NETBUF_LEN(pReq)) + ATH_SPI_WRBUF_RSVD_BYTES) + { + /* this will read the internal register to get the latest value for write buffer space */ + Hcd_RefreshWriteBufferSpace(pCxt); + + if (pDCxt->spi_hcd.WriteBufferSpace < + DEV_CALC_SEND_PADDED_LEN(pDCxt, A_NETBUF_LEN(pReq)) + ATH_SPI_WRBUF_RSVD_BYTES) + { + /* there currently isn't enough space in the target fifo to accept this packet. + * Hence setup the write buffer watermark interrupt for future notification and exit. */ + Hcd_ProgramWriteBufferWaterMark(pCxt, DEV_CALC_SEND_PADDED_LEN(pDCxt, A_NETBUF_LEN(pReq))); + /* wait for interrupt to indicate space available */ + break; + } + } + /* all conditions are met to transmit a packet */ + res = true; + } while (0); + + return res; +} + +/*****************************************************************************/ +/* Driver_RxReady - Determines whether it is safe to start a RX operation. If + * a RX operation can be started this function returns true else false. + * void *pCxt - the driver context. + *****************************************************************************/ +boolean Driver_RxReady(void *pCxt) +{ + boolean res = false; + HTC_FRAME_HDR *pHTCHdr; + int32_t fullLength; + uint32_t interrupts; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* there can be no errors */ + if (pDCxt->booleans & SDHD_BOOL_FATAL_ERROR) + { + break; + } + /* there can be no in-complete requests */ + if ((pDCxt->booleans & SDHD_BOOL_DMA_IN_PROG) || (pDCxt->booleans & SDHD_BOOL_DMA_COMPLETE)) + { + break; + } + /* the wifi device must have indicated that a packet is ready */ + if (0 == pDCxt->spi_hcd.PendingIrqAcks) + { + break; + } + /* there must be rx buffers to process the request */ + if (false == pDCxt->rxBufferStatus && NULL == pDCxt->pRxReq) + { + break; + } + /* clear the pkt interrupt if its set. We do this here rather than in the + * interrupt handler because we will continue to process packets until we + * read a lookahead==0. only then will we unmask the interrupt */ + if (A_OK != Hcd_DoPioInternalAccess(pCxt, ATH_SPI_INTR_CAUSE_REG, &interrupts, true)) + { + break; + } + + if (interrupts & ATH_SPI_INTR_PKT_AVAIL) + { + interrupts = ATH_SPI_INTR_PKT_AVAIL; + + if (A_OK != Hcd_DoPioInternalAccess(pCxt, ATH_SPI_INTR_CAUSE_REG, &interrupts, false)) + { + break; + } + } + /* RX packet interrupt processing must be enabled */ + if (0 == (pDCxt->enabledSpiInts & ATH_SPI_INTR_PKT_AVAIL)) + { + break; + } + /* As a last step read the lookahead and the Receive buffer register in an + * effort to determine that a complete packet is ready for transfer. Do this + * operation last as it does require several BUS transactions to complete. */ + if (0 == pDCxt->lookAhead) + { + /* need to refresh the lookahead */ + if (A_OK != Hcd_GetLookAhead(pCxt)) + { + /* this is a major error */ + A_ASSERT(0); + } + } + /* if lookahead is 0 then no need to proceed */ + if (0 == pDCxt->lookAhead) + { + if (0 != pDCxt->spi_hcd.PendingIrqAcks) + { + /* this should always be true here */ + pDCxt->spi_hcd.PendingIrqAcks = 0; + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_INTR_PKT_AVAIL); + } + + break; + } + /* compare lookahead and recv buf ready value */ + pHTCHdr = (HTC_FRAME_HDR *)&(pDCxt->lookAhead); + if (pDCxt->spi_hcd.ReadBufferSpace < sizeof(HTC_FRAME_HDR) || + pDCxt->spi_hcd.ReadBufferSpace < A_LE2CPU16(pHTCHdr->PayloadLen)) + { + /* force a call to BUS_GetLookAhead on the next pass */ + pDCxt->lookAhead = 0; + break; + } + /* there must be resources available to receive a packet */ + if (NULL == pDCxt->pRxReq) + { + fullLength = + (int32_t)DEV_CALC_RECV_PADDED_LEN(pDCxt, A_LE2CPU16(pHTCHdr->PayloadLen) + sizeof(HTC_FRAME_HDR)); + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) + { + uint32_t flags, bufNdx; + + bufNdx = GetQueueIndexByEPID(pHTCHdr->EndpointID); + flags = 1 << bufNdx; + + if (pDCxt->rxMultiBufferStatus & flags) + { + /* try to get an RX buffer */ + pDCxt->pRxReq = CUSTOM_DRIVER_GET_RX_REQ(pCxt, fullLength, pHTCHdr->EndpointID); + } + } +#else + + if (pDCxt->rxBufferStatus) + { + /* try to get an RX buffer */ + pDCxt->pRxReq = CUSTOM_DRIVER_GET_RX_REQ(pCxt, fullLength); + } +#endif + + if (pDCxt->pRxReq == NULL) + { + break; + } + /* init the packet callback */ + A_NETBUF_SET_ELEM(pDCxt->pRxReq, A_REQ_CALLBACK, Driver_RxComplete); + } + /* all conditions are met to receive a packet */ + res = true; + } while (0); + + return res; +} + + +extern void socket_set_driver_error(void *ctxt, int32_t error); +void Driver_DropTxDataPackets(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + void *pReq; + uint16_t i, count; + + if (pDCxt->txQueue.count) + { + count = pDCxt->txQueue.count; + /* accesslock here to sync with threads calling + * submit TX + */ + for (i = 0; i < count; i++) + { + TXQUEUE_ACCESS_ACQUIRE(pCxt); + { + pReq = A_NETBUF_DEQUEUE(&(pDCxt->txQueue)); + } + TXQUEUE_ACCESS_RELEASE(pCxt); + + if (pReq != NULL) + { + if (A_NETBUF_GET_ELEM(pReq, A_REQ_EPID) > ENDPOINT_1) + { + /* Get netbuffer socket context and set it into error state. */ + /* This field is used/readed in unblock function. */ + A_NETBUF_PTR a_netbuf_ptr = (A_NETBUF *)pReq; + DRV_BUFFER_PTR db_ptr = a_netbuf_ptr->native_orig; + socket_set_driver_error(db_ptr->context, A_DEADLOCK); + Driver_CompleteRequest(pCxt, pReq); + } + else + { + TXQUEUE_ACCESS_ACQUIRE(pCxt); + /* re-queue the packet as it is not one we can purge */ + A_NETBUF_ENQUEUE(&(pDCxt->txQueue), pReq); + TXQUEUE_ACCESS_RELEASE(pCxt); + } + } + } + } +} + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) +extern A_NETBUF *ep0_buf; + +void Driver_ReportReverseCredits(void *pReq) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(p_Global_Cxt); + A_NETBUF *pCurrTxReq; + +#if 0 + A_ENDPOINT_T *pEp; + void *osbuf; + void *pReq; + if (pDCxt->txQueue.count != 0) + { + pReq = A_NETBUF_PEEK_QUEUE(&(pDCxt->txQueue)); + pEp = Util_GetEndpoint(p_Global_Cxt, A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)); + if (pEp->credits != 0) + return; + } + osbuf = A_NETBUF_ALLOC(0); + A_NETBUF_SET_ELEM(osbuf, A_REQ_EPID, 0); + Driver_SubmitTxRequest(p_Global_Cxt, osbuf); +#else + + if (hasRCSReport() == false) + { + return; + } + + pCurrTxReq = A_NETBUF_PEEK_QUEUE(&(pDCxt->txQueue)); + if (pCurrTxReq != NULL) + { + if (A_NETBUF_GET_ELEM(pCurrTxReq, A_REQ_EPID) == ENDPOINT_0) + return; + } + + a_netbuf_reinit(ep0_buf, 0); + A_NETBUF_SET_ELEM(ep0_buf, A_REQ_EPID, 0); + + qosal_intr_disable(); + Driver_SubmitEp0TxRequest(p_Global_Cxt, ep0_buf); + + qosal_intr_enable(); + +#endif +} + +#endif + +A_STATUS +Driver_WaitForCondition(void *pCxt, volatile boolean *pCond, boolean value, uint32_t msec) +{ + A_STATUS status = A_OK; + + event_t *pEvent = &GET_DRIVER_CXT(pCxt)->userWakeEvent; + + while (1) + { + if (*pCond != value) + { + uint32_t setFlags; + if (A_OK != A_EVENT_WAIT(pEvent, 0x01, true, msec, &setFlags)) + { + status = A_ERROR; + break; + } + else + { + A_EVENT_CLEAR(pEvent, 0x01); + } + } + else + { + break; + } + } + + return status; +} + +#if 1 +A_STATUS setup_host_dset(void *handle) +{ + return wmi_dset_host_cfg_cmd(handle); +} +#else +A_STATUS setup_host_dset(void *handle) +{ + return A_OK; +} +#endif + +void Atheros_Driver_Task(void *pCxt) +{ + boolean canBlock = false; + uint16_t block_msec = 1000; // TODO: what should be a correct value?? + uint32_t timeout = 0; + + do + { + if (A_OK == Driver_Init(pCxt)) + { + while (1) + { + if (canBlock) + { + GET_DRIVER_COMMON(pCxt)->driverSleep = true; + timeout = block_msec; + + if (block_msec && timeout == 0) + { + timeout = 1; + } + event_t *pEvent = &(GET_DRIVER_CXT(pCxt)->driverWakeEvent); + uint32_t setFlags; + if (A_OK != A_EVENT_WAIT(pEvent, 0x01, true, timeout, &setFlags)) + { + if (timeout == 0) + { + break; + } + } + } + + GET_DRIVER_COMMON(pCxt)->driverSleep = false; + + if (GET_DRIVER_COMMON(pCxt)->driverShutdown == true) + { + break; + } + + Driver_Main(pCxt, DRIVER_SCOPE_RX | DRIVER_SCOPE_TX, &canBlock, &block_msec); + } + + Driver_DeInit(pCxt); + DRIVER_WAKE_USER(pCxt); + } +#if QOSAL_TASK_DESTRUCTION + } while (0); + + atheros_wifi_task_id = QOSAL_NULL_TASK_HANDLE; +#else + /* block on this event until a task wants to re-activate the driver thread */ + // qosal_task_suspend(NULL); + } while (1); +#endif +} + +// The WLAN driver task priority is set to the next highest priority (0 is highest priority) +// because blockForResponse() needs to temporarily boost caller task's priority +// over that of the driver task +#define ATHEROS_TASK_PRIORITY (osPriorityNormal1) +#define ATHEROS_TASK_STACKSIZE 2000 + +/* NOTE: the whole file will be included as part of freertos env */ +/* TODO: check stackSize/sizeof(portSTACK_TYPE) */ +uint16_t atheros_wifi_task_prio = ATHEROS_TASK_PRIORITY; + +A_STATUS Driver_CreateThread(void *pCxt) +{ + assert(atheros_wifi_task_id == NULL); + + osThreadAttr_t attr = {0}; + attr.name = "Atheros_Wifi_Task"; + attr.stack_mem = malloc(ATHEROS_TASK_STACKSIZE); + attr.cb_mem = &thread_cb; + attr.stack_size = ATHEROS_TASK_STACKSIZE; + attr.cb_size = sizeof(mbed_rtos_storage_thread_t); + attr.priority = ATHEROS_TASK_PRIORITY; + + atheros_wifi_task_id = osThreadNew((osThreadFunc_t)Atheros_Driver_Task, pCxt, &attr); + return (NULL == atheros_wifi_task_id) ? A_ERROR : A_OK; +} + +// Compliments CreateDriverThread +A_STATUS +Driver_DestroyThread(void *pCxt) +{ + GET_DRIVER_COMMON(pCxt)->driverShutdown = true; + DRIVER_WAKE_DRIVER(pCxt); + return A_OK; +} + +void Driver_WakeDriver(void *pCxt) +{ + A_EVENT_SET(&(GET_DRIVER_CXT(pCxt)->driverWakeEvent), 0x01); +} + +void Driver_WakeUser(void *pCxt) +{ + A_EVENT_SET(&(GET_DRIVER_CXT(pCxt)->userWakeEvent), 0x01); +} + +void qcadrv_assert_func(const char *func_name, int line) +{ + volatile int i = 1; + while (i) + ; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_netbuf.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_netbuf.c new file mode 100644 index 00000000000..879065734c5 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_netbuf.c @@ -0,0 +1,117 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include + +void Driver_ReportReverseCredits(void *pReq); + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) +uint8_t GET_QUEUE_INDEX(A_NETBUF_QUEUE_T *q) +{ + uint8_t i; + + for (i = 0; i < 8; i++) + { + if (&GET_FREE_QUEUE(i) == q) + break; + } + + return i; +} +#endif + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) + +extern uint8_t reverse_credits_init; +uint8_t credits_test = 0; + +void a_rxbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pReq) +{ + uint8_t epid; + uint32_t bufCtrlNdx; + + a_netbuf_enqueue(q, pReq); + + if (reverse_credits_init == 0) + return; + + epid = A_NETBUF_GET_ELEM(pReq, A_REQ_EPID); + if (epid == ENDPOINT_0) + return; + + // i = GET_QUEUE_INDEX(q); + bufCtrlNdx = GetQueueCtrlIndexByEPID(epid); + if (bufCtrlNdx < 8 && bufCtrlNdx != 7) + { + CREDIT_INC(bufCtrlNdx); + // Driver_ReportReverseCredits(pReq); + } + else + { + // printf("wrong\n"); + } +} + +void *a_rxbuf_dequeue(A_NETBUF_QUEUE_T *q) +{ + void *pReq; + // uint8_t i; + + pReq = a_netbuf_dequeue(q); + if (pReq == NULL) + { + return pReq; + } + + /* i = GET_QUEUE_INDEX(q); + + if ( i < 8) + CREDIT_DEC(i); + */ + return pReq; +} +#endif + +void *a_netbuf_peek_queue(A_NETBUF_QUEUE_T *q) +{ + return q->head; +} + +int32_t a_netbuf_queue_size(A_NETBUF_QUEUE_T *q) +{ + return q->count; +} + +int32_t a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q) +{ + return ((q->count == 0) ? 1 : 0); +} + +/* EOF */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_txrx.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_txrx.c new file mode 100644 index 00000000000..85fcda4bf19 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/driver/driver_txrx.c @@ -0,0 +1,312 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*****************************************************************************/ +/* Driver_RxComplete - For completed RX packet requests this function routes + * the request to a handler based on endpoint ID. Called when the Bus + * transfer operation has completed. + * void *pCxt - the driver context. + * void *pReq - the request object. + *****************************************************************************/ +void Driver_RxComplete(void *pCxt, void *pReq) +{ + uint32_t lookAheads[1]; + uint32_t NumLookAheads = 0; + + if (A_OK != Htc_ProcessRecvHeader(pCxt, pReq, lookAheads, &NumLookAheads)) + { + A_ASSERT(0); + } + + if (A_NETBUF_GET_ELEM(pReq, A_REQ_EPID) == ENDPOINT_0) + { + Htc_RxComplete(pCxt, pReq); + } + else + { + Api_RxComplete(pCxt, pReq); + } +} + +/*****************************************************************************/ +/* Driver_TxComplete - For completed TX packet requests this function routes + * the request to a handler based on endpoint ID. Called when the Bus + * transfer operation has completed. + * void *pCxt - the driver context. + * void *pReq - the request object. + *****************************************************************************/ +static void Driver_TxComplete(void *pCxt, void *pReq) +{ + Htc_ProcessTxComplete(pCxt, pReq); + +#if 0 + if(A_NETBUF_GET_ELEM(pReq, A_REQ_EPID) == ENDPOINT_0){ + /* this should never happen in practice as the driver + * does not SEND messages on the HTC endpoint */ + A_ASSERT(0); + //HTC_TxComplete(pCxt, pReq); + }else{ + Api_TxComplete(pCxt, pReq); + } +#else + Api_TxComplete(pCxt, pReq); +#endif +} + +/*****************************************************************************/ +/* Driver_PostProcessRequest - Utility to post process requests that have + * completed Hcd_Request(). + * void *pCxt - the driver context. + * void *pReq - the request object. + * A_STATUS reqStatus - the status of the transaction. + *****************************************************************************/ +static void Driver_PostProcessRequest(void *pCxt, void *pReq, A_STATUS reqStatus) +{ + A_DRIVER_CONTEXT *pDCxt; + + A_NETBUF_SET_ELEM(pReq, A_REQ_STATUS, reqStatus); + + if (A_NETBUF_GET_ELEM(pReq, A_REQ_CALLBACK) != NULL) + { + pDCxt = GET_DRIVER_COMMON(pCxt); + pDCxt->spi_hcd.pCurrentRequest = pReq; + + if (reqStatus != A_PENDING) + { + pDCxt->booleans |= SDHD_BOOL_DMA_COMPLETE; + } + } +} + +/*****************************************************************************/ +/* Driver_SubmitTxRequest - Called from a User thread to submit a new + * Tx packet to the driver. The function will append the request to the + * drivers txqueue and wake up the driver thread. + * void *pCxt - the driver context. + * void *pReq - the request object. + *****************************************************************************/ +A_STATUS +Driver_SubmitTxRequest(void *pCxt, void *pReq) +{ + A_STATUS status = A_ERROR; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint32_t transferLength, creditsRequired; + + do + { + A_NETBUF_SET_ELEM(pReq, A_REQ_CALLBACK, Driver_TxComplete); + /* reserve space for HTC header to allow for proper calculation + * of transmit length. The header will be populated when the + * request is transmitted. */ + if (A_NETBUF_PUSH(pReq, HTC_HDR_LENGTH) != A_OK) + { + break; + } + /* The length of the request is now complete so + * calculate and assign the number of credits required by this + * request. */ + transferLength = DEV_CALC_SEND_PADDED_LEN(pDCxt, A_NETBUF_LEN(pReq)); + + if (transferLength <= pDCxt->creditSize) + { + creditsRequired = 1; + } + else + { + /* figure out how many credits this message requires */ + creditsRequired = (uint32_t)(transferLength / pDCxt->creditSize); + + if (creditsRequired * pDCxt->creditSize < transferLength) + { + creditsRequired++; + } + } + + A_NETBUF_SET_ELEM(pReq, A_REQ_CREDITS, creditsRequired); + + TXQUEUE_ACCESS_ACQUIRE(pCxt); + { + A_NETBUF_ENQUEUE(&(pDCxt->txQueue), pReq); + status = A_OK; + } + TXQUEUE_ACCESS_RELEASE(pCxt); + + if (status == A_OK) + { + DRIVER_WAKE_DRIVER(pCxt); + } + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Driver_TxComplete - For completed TX packet requests this function routes + * the request to a handler based on endpoint ID. Called when the Bus + * transfer operation has completed. + * void *pCxt - the driver context. + * void *pReq - the request object. + *****************************************************************************/ +static void Driver_Ep0TxComplete(void *pCxt, void *pReq) +{ + Htc_ProcessTxComplete(pCxt, pReq); +} + +A_STATUS +Driver_SubmitEp0TxRequest(void *pCxt, void *pReq) +{ + A_STATUS status = A_ERROR; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint32_t transferLength, creditsRequired; + + do + { + A_NETBUF_SET_ELEM(pReq, A_REQ_CALLBACK, Driver_Ep0TxComplete); + /* reserve space for HTC header to allow for proper calculation + * of transmit length. The header will be populated when the + * request is transmitted. */ + if (A_NETBUF_PUSH(pReq, HTC_HDR_LENGTH) != A_OK) + { + break; + } + /* The length of the request is now complete so + * calculate and assign the number of credits required by this + * request. */ + transferLength = DEV_CALC_SEND_PADDED_LEN(pDCxt, A_NETBUF_LEN(pReq)); + + if (transferLength <= pDCxt->creditSize) + { + creditsRequired = 1; + } + else + { + /* figure out how many credits this message requires */ + creditsRequired = (uint32_t)(transferLength / pDCxt->creditSize); + + if (creditsRequired * pDCxt->creditSize < transferLength) + { + creditsRequired++; + } + } + + A_NETBUF_SET_ELEM(pReq, A_REQ_CREDITS, creditsRequired); + + TXQUEUE_ACCESS_ACQUIRE(pCxt); + { + A_NETBUF_PREQUEUE(&(pDCxt->txQueue), pReq); + status = A_OK; + } + TXQUEUE_ACCESS_RELEASE(pCxt); + + if (status == A_OK) + { + DRIVER_WAKE_DRIVER(pCxt); + } + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Driver_SendPacket - Entry point to send a packet from the device. Sets + * up request params address and other and calls HCD_Request to perform the + * work. If a callback is provided in the request then it will be used to + * complete the request. If a callback is not provided the lower layers + * must complete the request synchronously. + * void *pCxt - the driver context. + * void *pReq - the request object. + *****************************************************************************/ +A_STATUS Driver_SendPacket(void *pCxt, void *pReq) +{ + A_STATUS status = A_ERROR; + uint32_t address; + uint16_t transLength; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + if (A_OK != (status = Htc_SendPacket(pCxt, pReq))) + { + Driver_PostProcessRequest(pCxt, pReq, status); + break; + } + /* calc the padding and mbox address */ + /* NOTE: for Transmit the request length may not equal the transfer length due to + * padding requirements. */ + transLength = DEV_CALC_RECV_PADDED_LEN(pDCxt, A_NETBUF_LEN(pReq)); + address = HW_GetMboxAddress(pCxt, HIF_ACTIVE_MBOX_INDEX, transLength); + address &= ATH_TRANS_ADDR_MASK; + A_NETBUF_SET_ELEM(pReq, A_REQ_ADDRESS, address); + A_NETBUF_SET_ELEM(pReq, A_REQ_TRANSFER_LEN, transLength); + /* init the packet read params/cmd incremental vs fixed address etc. */ + A_NETBUF_SET_ELEM(pReq, A_REQ_COMMAND, (ATH_TRANS_WRITE | ATH_TRANS_DMA)); + status = Hcd_Request(pCxt, pReq); + Driver_PostProcessRequest(pCxt, pReq, status); + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Driver_RecvPacket - Entry point to receive a packet from the device. Sets + * up request params address and other and calls HCD_Request to perform the + * work. This path always provides a request callback for asynchronous + * completion. This is because DMA if available will always be used for + * packet requests. + * void *pCxt - the driver context. + * void *pReq - the request object. + *****************************************************************************/ +A_STATUS Driver_RecvPacket(void *pCxt, void *pReq) +{ + // uint16_t validLength, transLength, hdrLength; + + A_STATUS status; + uint32_t address; + + Htc_PrepareRecvPacket(pCxt, pReq); + + /* init the packet mailbox address - begin with mailbox end address and then subtract the request transfer length */ + address = HW_GetMboxAddress(pCxt, HIF_ACTIVE_MBOX_INDEX, A_NETBUF_LEN(pReq)); + address &= ATH_TRANS_ADDR_MASK; + A_NETBUF_SET_ELEM(pReq, A_REQ_ADDRESS, address); + /* init the packet read params/cmd incremental vs fixed address etc. */ + A_NETBUF_SET_ELEM(pReq, A_REQ_COMMAND, (ATH_TRANS_READ | ATH_TRANS_DMA)); + + status = Hcd_Request(pCxt, pReq); + Driver_PostProcessRequest(pCxt, pReq, status); + + return status; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hcd/hcd_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hcd/hcd_api.h new file mode 100644 index 00000000000..8e2d1572f17 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hcd/hcd_api.h @@ -0,0 +1,77 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +#ifndef _HCD_API_H_ +#define _HCD_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +A_STATUS +Hcd_Request(void *pCxt, void *pReq); +boolean Hcd_ReadCPUInterrupt(void *pCxt, uint8_t *cpuIntrCause); +void Hcd_ClearCPUInterrupt(void *pCxt); +A_STATUS +Hcd_UnmaskInterrupts(void *pCxt, uint16_t Mask); // IGX_UD_CHANGES +A_STATUS +Hcd_UnmaskInterrupts(void *pCxt, uint16_t Mask); +A_STATUS +Hcd_GetLookAhead(void *pCxt); +boolean Hcd_BusInterrupt(void *pCxt); +A_STATUS +Hcd_ReinitTarget(void *pCxt); +void Hcd_Deinitialize(void *pCxt); +A_STATUS +Hcd_Init(void *pCxt); +void Hcd_EnableCPUInterrupt(void *pCxt); +A_STATUS +Hcd_DoPioExternalAccess(void *pCxt, void *pReq); +void Hcd_MaskInterrupts(void *pCxt, uint16_t Mask); +A_STATUS +Hcd_ReinitTarget(void *pCxt); +A_STATUS +Hcd_UnmaskInterrupts(void *pCxt, uint16_t Mask); +A_STATUS +Bus_InOutDescriptorSet(void *pCxt, void *pReq); + +#if 0 +/* +* The below 3-functions are need to implement and +* HCD_SUSPEND_CB and HCD_RESUME_CB structures are not avialable with +* current driver source +*/ + +void Hcd_AckInterrupt(void *pCxt, uint16_t Mask); +void Hcd_RegisterSuspendHandler(HCD_SUSPEND_CB *suspendCallback, void *pSuspContext); +void Hcd_RegisterResumeHandler(HCD_RESUME_CB *resumeCallback, void *pSuspContext); +void +Hcd_RegisterInterruptHandler(HCD_INTR_CALLBACK_T *callback, void *pContext); +#endif //#if 0 + +#endif //_HCD_API_H_ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hcd/spi_hcd.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hcd/spi_hcd.c new file mode 100644 index 00000000000..714d9bfc1a6 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hcd/spi_hcd.c @@ -0,0 +1,1486 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include +#include "spi_hcd_if.h" +#include +#include "hw20_mbox_host_reg.h" +#include +#include "atheros_wifi_api.h" + +#define CMD_ADDR_READ (1 << 15) +#define CMD_ADDRESS_INTERNAL (1 << 14) + +#define ADJUST_WRBUF_SPACE(p, b) \ + \ +{ \ + (p)->spi_hcd.WriteBufferSpace = (p)->spi_hcd.WriteBufferSpace - (b)-ATH_SPI_WRBUF_RSVD_BYTES; \ + \ +} + +/* macro to issue command/address phase */ +#define OUT_TOKEN_CMD_ADDR_DMA_WRITE(pdev, addr) \ + Bus_InOutToken((pdev), (uint32_t)A_CPU2BE16((addr)), ATH_TRANS_DS_16, NULL) + +#define OUT_TOKEN_CMD_ADDR_DMA_READ(pdev, addr) OUT_TOKEN_CMD_ADDR_DMA_WRITE(pdev, ((addr) | CMD_ADDR_READ)) + +#define OUT_TOKEN_CMD_ADDR_INTERNAL_READ(pdev, addr) OUT_TOKEN_CMD_ADDR_DMA_READ(pdev, ((addr) | CMD_ADDRESS_INTERNAL)) + +#define OUT_TOKEN_CMD_ADDR_INTERNAL_WRITE(pdev, addr) \ + OUT_TOKEN_CMD_ADDR_DMA_WRITE(pdev, ((addr) | CMD_ADDRESS_INTERNAL)) + +static A_STATUS Hcd_TransferData(void *pCxt, void *pReq); + +/*****************************************************************************/ +/* DoPioReadInternal - Used to write a device internal register. + * void *pCxt - the driver context. + * uint16_t Addr - address of the register. + * uint32_t value - value to write to the register. + *****************************************************************************/ +#if 0 +A_STATUS +DoPioWriteInternal(void *pCxt, + uint16_t Addr, + uint32_t Value) +{ + A_STATUS status; + + Addr |= CMD_ADDRESS_INTERNAL; + + /* issue CMD/ADDR token */ + if(A_OK != (status = OUT_TOKEN_CMD_ADDR_INTERNAL_WRITE(pCxt,Addr))){ + return status; + } + /* despite the UINT32 there are only 2 bytes of data for internal + * register. These bytes must be set in Big Endian format for + * proper parsing by the chip. */ + Value = A_CPU2BE16(Value); + /* send out data */ + return Bus_InOutToken(pCxt, Value, ATH_TRANS_DS_16, NULL); +} +#else +A_STATUS DoPioWriteInternal(void *pCxt, uint16_t Addr, uint32_t Value) +{ + uint32_t dataIn; + uint32_t dataOut; + + /* despite the UINT32 there are only 2 bytes of data for internal + * register. These bytes must be set in Big Endian format for + * proper parsing by the chip. */ + Addr = (Addr | CMD_ADDRESS_INTERNAL); + Addr = A_CPU2BE16(Addr); + Value = A_CPU2BE16(Value); + dataOut = Addr | ((Value & 0xFFFF) << 16); + return (CUSTOM_BUS_INOUT_TOKEN(pCxt, dataOut, 4, &dataIn)); +} +#endif + +/*****************************************************************************/ +/* DoPioReadInternal - Used to read a device internal register. + * void *pCxt - the driver context. + * uint16_t Addr - address of the register. + * uint32_t *pValue - pointer to the location to where the value should + * be stored. + *****************************************************************************/ +#if 0 +static A_STATUS +DoPioReadInternal(void *pCxt, + uint16_t Addr, + uint32_t *pValue) +{ + A_STATUS status; + + do { + Addr |= CMD_ADDRESS_INTERNAL; + + if(A_OK != (status = OUT_TOKEN_CMD_ADDR_INTERNAL_READ(pCxt, Addr))){ + break; + } + + status = Bus_InOutToken(pCxt, 0x00000000, ATH_TRANS_DS_16, pValue); + /* despite the UINT32 storage there are only 2 bytes of data from the + * internal register. These bytes arrive in Big Endian format so + * must be converted to CPU format for proper consumption. */ + *pValue = (uint16_t) A_BE2CPU16(*pValue); + } while (false); + + return status; +} +#else +static A_STATUS DoPioReadInternal(void *pCxt, uint16_t Addr, uint32_t *pValue) +{ + A_STATUS status; + uint32_t dataIn; + uint32_t dataOut; + + Addr = (Addr | CMD_ADDRESS_INTERNAL | CMD_ADDR_READ); + dataOut = A_CPU2BE16(Addr); + status = CUSTOM_BUS_INOUT_TOKEN(pCxt, dataOut, 4, &dataIn); + *pValue = dataIn >> 16; + *pValue = A_BE2CPU16(*pValue); + return status; +} + +#endif + +/*****************************************************************************/ +/* EnableDisableSPIIRQHwDetect - Used to enable/disable SPI interrupt detection + * Ultimately this function calls HW_EnableDisableSPIIRQ to enable/disable the IRQ. + * void *pCxt - the driver context. + * boolean Enable - if true then enable SPI Interrupt if false then + * disable SPI Interrupt. + *****************************************************************************/ +static void EnableDisableSPIIRQHwDetect(void *pCxt, boolean Enable) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + if ((pDCxt->spi_hcd.SpiHWCapabilitiesFlags & HW_SPI_INT_EDGE_DETECT) && Enable) + { + /* the SPI interrupt is edge triggered and has requirements for a good edge + * when we enable interrupt detection we disable all interrupts on the module and + then re-enable them again to generate a good edge */ + + if (A_OK != DoPioWriteInternal(pCxt, ATH_SPI_INTR_ENABLE_REG, 0)) + { + A_ASSERT(0); + } + /* re-enable SPI interrupt detection at the host controller */ + HW_EnableDisableSPIIRQ(pCxt, true, false); + + /* re-enable interrupt sources, if there are pending interrupts, this should + * generate a nice clean edge */ + if (A_OK != DoPioWriteInternal(pCxt, ATH_SPI_INTR_ENABLE_REG, pDCxt->spi_hcd.SpiIntEnableShadow)) + { + A_ASSERT(0); + } + } + else + { + /* the SPI interrupt logic is level triggered (or we are simply disabling) so we can simply tell + * the hardware layer to enable/disable it */ + HW_EnableDisableSPIIRQ(pCxt, Enable, false); + } +} + +/*****************************************************************************/ +/* MaskSPIInterrupts - Used to mask specific device interrupts + * function will write the SPI Interrupt Enable register with the resulting + * mask value. + * void *pCxt - the driver context. + * uint16_t Mask - bit mask indicating which interrupts should be + * masked. + *****************************************************************************/ +static A_STATUS MaskSPIInterrupts(void *pCxt, uint16_t Mask) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + pDCxt->spi_hcd.SpiIntEnableShadow &= ~Mask; + + if (Mask & pDCxt->spi_hcd.SpiIntEnableShadow) + { + Hcd_UnmaskInterrupts(pCxt, Mask); + } + + return DoPioWriteInternal(pCxt, ATH_SPI_INTR_ENABLE_REG, (uint32_t)pDCxt->spi_hcd.SpiIntEnableShadow); +} + +/*****************************************************************************/ +/*****************************************************************************/ +/* HandleExternalReadDone - Utlity to complete an External IO read operation. + * void *pCxt - the driver context. + * void *pReq - the transfer request object. + *****************************************************************************/ +static A_STATUS HandleExternalReadDone(void *pCxt, void *pReq) +{ + A_STATUS status; + /* send out cmd/addr token */ + if (A_OK != (status = OUT_TOKEN_CMD_ADDR_INTERNAL_READ(pCxt, ATH_SPI_HOST_CTRL_RD_PORT_REG))) + { + return status; + } + /* do the data frames to get the data */ + status = Hcd_TransferData(pCxt, pReq); + /* this should never return pending, external I/O accesses do not invoke the DMA hardware */ + A_ASSERT(status != A_PENDING); + + return status; +} + +#if 0 +/*****************************************************************************/ +/* ReadSomeInternalReg - Utility function to read some device registers as + * a Workaround for some chipsets. + * void *pCxt - the driver context. + *****************************************************************************/ +static void +ReadSomeInternalReg(void *pCxt) +{ + uint32_t reg; + + do{ + if(A_OK != DoPioReadInternal(pCxt, ATH_SPI_WRBUF_SPC_AVA_REG, ®)){ + break; + } + + if(A_OK != DoPioReadInternal(pCxt, ATH_SPI_RDBUF_BYTE_AVA_REG, ®)){ + break; + } + + if(A_OK != DoPioReadInternal(pCxt, ATH_SPI_CONFIG_REG, ®)){ + break; + } + }while(0); +} +#endif +A_STATUS +Hcd_DoPioInternalAccess(void *pCxt, uint16_t addr, uint32_t *pValue, boolean isRead) +{ + A_STATUS status; + + if (isRead == true) + { + status = DoPioReadInternal(pCxt, addr, pValue); + } + else + { + status = DoPioWriteInternal(pCxt, addr, *pValue); + } + + return status; +} + +/*****************************************************************************/ +/* Hcd_DoPioExternalAccess - accessing external registers requires the use + * of the SPI slave controller's internal proxy state machine + * in the event that the chip is asleep. The internal proxy performs the operation + * and will signal us via an interrupt or polling operation + * void *pCxt - the driver context. + * void *pReq - the transfer request object. + *****************************************************************************/ +A_STATUS +Hcd_DoPioExternalAccess(void *pCxt, void *pReq) +{ + A_STATUS status; + uint32_t regValue; + int retry; + + do + { + /* set incrementing or fixed addressing */ + regValue = (uint32_t)(ATH_IS_TRANS_EXT_ADDR_FIXED(pReq) ? ATH_SPI_HOST_CTRL_NO_ADDR_INC : 0); + /* set the length */ + regValue |= A_NETBUF_LEN(pReq); + /* write control reg */ + if (A_OK != (status = DoPioWriteInternal(pCxt, ATH_SPI_HOST_CTRL_BYTE_SIZE_REG, regValue))) + { + break; + } + + if (ATH_IS_TRANS_WRITE(pReq)) + { + /* write to the data port */ + /* send out cmd/addr token */ + if (A_OK != (status = OUT_TOKEN_CMD_ADDR_INTERNAL_WRITE(pCxt, ATH_SPI_HOST_CTRL_WR_PORT_REG))) + { + break; + } + /* do the data frames */ + status = Hcd_TransferData(pCxt, pReq); + /* these frames should go out without using interrupts */ + A_ASSERT(status != A_PENDING); + if (A_OK != status) + { + break; + } + } + + /* enable, set direction and set address range to do the operation on */ + regValue = ATH_SPI_HOST_CTRL_CONFIG_ENABLE; + regValue |= ATH_IS_TRANS_READ(pReq) ? 0 : ATH_SPI_HOST_CTRL_CONFIG_DIR_WRITE; + regValue |= A_NETBUF_GET_ELEM(pReq, A_REQ_ADDRESS); // ATH_GET_IO_ADDRESS(pReq); + /* write config to start the operation */ + if (A_OK != (status = DoPioWriteInternal(pCxt, ATH_SPI_HOST_CTRL_CONFIG_REG, regValue))) + { + break; + } + /* poll the host_access_done bit in SPI_STATUS register, if the access takes longer + * than the retry count, the core was probably asleep, we need to wait for an interrupt + * for the operation to complete */ + // retry = EXTERNAL_ACCESS_DONE_RETRY_COUNT; + retry = 200; + + while (retry) + { + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_STATUS_REG, ®Value))) + { + break; + } + + if (regValue & ATH_SPI_STATUS_HOST_ACCESS_DONE) + { + break; + } + + retry--; + if (retry) + { + HW_USEC_DELAY(pCxt, 1000); + } + } + + if (0 == retry) + { + status = A_ERROR; + break; + } + + /* if we get here the chip was awake and the access finished within the polling interval */ + + if (ATH_IS_TRANS_READ(pReq)) + { + /* for reads, empty the read port */ + status = HandleExternalReadDone(pCxt, pReq); + } + + /* clear the interrupt cause, each host access operation will set the RD or WR + * cause bit */ + if (A_OK != (status = DoPioWriteInternal(pCxt, ATH_SPI_INTR_CAUSE_REG, + ATH_SPI_INTR_HOST_CTRL_RD_DONE | ATH_SPI_INTR_HOST_CTRL_WR_DONE))) + { + break; + } + } while (false); + + return status; +} + +/*****************************************************************************/ +/* ResetWriteBufferWaterMark - Used to reset the write buffer watermark on + * the device so as to prevent any further watermark interrupts from the + * device. + * void *pCxt - the driver context. + *****************************************************************************/ +static A_STATUS ResetWriteBufferWaterMark(void *pCxt) +{ + A_STATUS status; + + if (A_OK != (status = DoPioWriteInternal(pCxt, ATH_SPI_WRBUF_WATERMARK_REG, 0))) + { + return status; + } + /* the watermark interrupt status constantly latches, so after we + * set to zero, we need to clear the cause register */ + return DoPioWriteInternal(pCxt, ATH_SPI_INTR_CAUSE_REG, ATH_SPI_INTR_WRBUF_BELOW_WMARK); +} + +/*****************************************************************************/ +/* ConfigureByteSwap - Configures the byte swapping if any to be applied + * to any subsequent SPI transactions. This will write the SPI Config + * register as necessary to configure the device for proper byte swapping. + * void *pCxt - the driver context. + * uint8_t TransferType - indicates the unit size for SPI transfer. + *****************************************************************************/ +static A_STATUS ConfigureByteSwap(void *pCxt, uint8_t TransferType) +{ + uint16_t swapSettings; + + swapSettings = GET_DRIVER_COMMON(pCxt)->spi_hcd.SpiConfigShadow; + + /* based on the transfer type, figure out what mode settings we need */ + + if (TransferType == ATH_TRANS_DS_32) + { + /* make sure swap is turned on */ + swapSettings |= ATH_SPI_CONFIG_BYTE_SWAP; + /* turn off 16 bit mode - which actually turns ON 32 bit swapping */ + swapSettings &= ~ATH_SPI_CONFIG_SWAP_16BIT; + } + else if (TransferType == ATH_TRANS_DS_16) + { + /* make sure swap is turned on */ + swapSettings |= ATH_SPI_CONFIG_BYTE_SWAP; + /* turn on 16 bit swapping mode */ + swapSettings |= ATH_SPI_CONFIG_SWAP_16BIT; + } + else if (TransferType == ATH_TRANS_DS_8) + { + /* disable byte swapping entirely */ + swapSettings &= ~ATH_SPI_CONFIG_BYTE_SWAP; + swapSettings &= ~ATH_SPI_CONFIG_SWAP_16BIT; + } + else + { + A_ASSERT(0); + } + + /* did any bits change? */ + if (swapSettings ^ GET_DRIVER_COMMON(pCxt)->spi_hcd.SpiConfigShadow) + { + /* save new value */ + GET_DRIVER_COMMON(pCxt)->spi_hcd.SpiConfigShadow = swapSettings; + /* write it out */ + return DoPioWriteInternal(pCxt, ATH_SPI_CONFIG_REG, swapSettings); + } + + return A_OK; +} + +/*****************************************************************************/ +/* DoDMAOp - Utility function to initiate a DMA or other SPI transaction. + * Starts by writing the SPI DMA Size Register as required by the device. + * void *pCxt - the driver context. + * void *pReq - The request packet object. + *****************************************************************************/ +static A_STATUS DoDMAOp(void *pCxt, void *pReq) +{ + A_STATUS status; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint16_t mask = (uint16_t)(pDCxt->spi_hcd.SpiIntEnableShadow & ATH_SPI_INTR_PKT_AVAIL); + /* WAR during a data transfer/mbox operation it is necessary + * to mask the interrupt from the wifi device as that has been shown + * to corrupt SPI communication. */ + if (mask) + { + MaskSPIInterrupts(pCxt, mask); + } + + do + { + /* setup DMA size register */ + if (A_OK != + (status = DoPioWriteInternal(pCxt, ATH_SPI_DMA_SIZE_REG, A_NETBUF_GET_ELEM(pReq, A_REQ_TRANSFER_LEN)))) + { + break; + } + + if (ATH_IS_TRANS_READ(pReq)) + { + /* send out the read DMA token */ + status = OUT_TOKEN_CMD_ADDR_DMA_READ(pCxt, A_NETBUF_GET_ELEM(pReq, A_REQ_ADDRESS)); + } + else + { + /* send out the write DMA token */ + status = OUT_TOKEN_CMD_ADDR_DMA_WRITE(pCxt, A_NETBUF_GET_ELEM(pReq, A_REQ_ADDRESS)); + } + + if (A_OK != status) + { + break; + } + /* call transfer state machine to handle data frames */ + status = Hcd_TransferData(pCxt, pReq); + + if (A_PENDING == status) + { + /* transfer routine requires DMA to start */ + pDCxt->booleans |= SDHD_BOOL_DMA_IN_PROG; + /* we are transfering control to the SPI hardware's DMA engine, while it is + * running we cannot process SPI interrupts. SPI interrupt processing requires + * CMD/Data frames on the SPI bus and requires ownership of the SPI hardware. + * this function is called with the driver lock held to hold off the SPI interrupt + * handler HcdSpiInterrupt() , the handler should wake up and check for a pending + * DMA hardware transfer and exit. On completion of the DMA transfer, the SPI + * interrupt detection will be enabled */ + /* disable SPI interrupt detection at the hardware layer */ + EnableDisableSPIIRQHwDetect(pCxt, false); + // HW_StartDMA(pCxt); + } + + } while (false); + + if (mask) + { + if (status == A_PENDING) + { + pDCxt->spi_hcd.irqMask = mask; + } + else + { + Hcd_UnmaskInterrupts(pCxt, mask); + } + } + + return status; +} + +/*****************************************************************************/ +/* Hcd_ProgramWriteBufferWaterMark - Programs the device's write buffer + * watermark level to trigger an interrupt when device FiFo space becomes + * available. + * void *pCxt - the driver context. + * uint32_t length - the desired byte length to program watermark. + *****************************************************************************/ +A_STATUS +Hcd_ProgramWriteBufferWaterMark(void *pCxt, uint32_t length) +{ + uint32_t waterMarkLevel, regValue; + A_STATUS status = A_OK; + boolean waitInterrupt = true; + uint32_t param; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* calculate the water mark based on the number of bytes currently in the buffer + * and the number of bytes we need to fullfill the request, this is the level + * the buffer needs to drop below to trigger an interrupt */ + waterMarkLevel = pDCxt->spi_hcd.MaxWriteBufferSpace - length; + + if (waterMarkLevel < pDCxt->spi_hcd.MaxWriteBufferSpace) + { + /* also... watermark level cannot be zero */ + waterMarkLevel = waterMarkLevel ? waterMarkLevel : 1; + } + else + { + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + waterMarkLevel = 1; +#endif + } + + /* update watermark trigger */ + if (A_OK != (status = DoPioWriteInternal(pCxt, ATH_SPI_WRBUF_WATERMARK_REG, waterMarkLevel))) + { + break; + } + /* re-sample SPI_STATUS and space available, the operation to update the watermark could + * miss the window when the core is still awake, if this happens the + * watermark level will be reached but it will not generate an interrupt + * as INTR_CAUSE is only updated while the core clock is active, so any updates to + * WR_BUF_WATERMARK_REG are only valid while the core is awake */ + + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_STATUS_REG, ®Value))) + { + break; + } + + if ((regValue & ATH_SPI_STATUS_RTC_STATE_MASK) == ATH_SPI_STATUS_RTC_STATE_SLEEP) + { + /* it can take up to 60 microseconds for the sleep state to change */ + HW_USEC_DELAY(pCxt, 60); + + /* re-read status and re-check the sleep state */ + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_STATUS_REG, ®Value))) + { + break; + } + + if ((regValue & ATH_SPI_STATUS_RTC_STATE_MASK) != ATH_SPI_STATUS_RTC_STATE_SLEEP) + { + /* core is awake or is just about to wakeup. We can wait for an interrupt */ + break; + } + + /* re-read space available, the core went to sleep and we may never get an interrupt */ + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_WRBUF_SPC_AVA_REG, ¶m))) + { + break; + } + + pDCxt->spi_hcd.WriteBufferSpace = param; + /* no need to wait, we have buffer space to send this packet */ + waitInterrupt = false; + + /* the core drained the write buffer after we sampled + * SPC_AVAIL, we now have room and the core went to sleep. + * reset watermark since we won't be using it */ + if (A_OK != (status = ResetWriteBufferWaterMark(pCxt))) + { + break; + } + /* fall through and return SUCCESS */ + } + + } while (false); + + if (A_OK == status && waitInterrupt) + { + /* no space, need to wait for interrupt */ + pDCxt->booleans |= SDHD_BOOL_DMA_WRITE_WAIT_FOR_BUFFER; + /* wait for the buffer to empty below the water mark */ + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_INTR_WRBUF_BELOW_WMARK); + status = A_PENDING; + } + + return status; +} + +/*****************************************************************************/ +/* Hcd_RefreshWriteBufferSpace - Reads the device Write buffer space available + * register to learn the available byte length that the device can + * currently accept for transmit operations. + * void *pCxt - the driver context. + *****************************************************************************/ +void Hcd_RefreshWriteBufferSpace(void *pCxt) +{ + uint32_t param; + if (A_OK == DoPioReadInternal(pCxt, ATH_SPI_WRBUF_SPC_AVA_REG, ¶m)) + { + GET_DRIVER_COMMON(pCxt)->spi_hcd.WriteBufferSpace = param; + } +} + +#if 1 // Common_HCD API's +/*****************************************************************************/ +/* Hcd_Request - Used to process a bus request. This could be a Tx or Rx + * request. + * void *pCxt - the driver context. + * void *pReq - the packet object + *****************************************************************************/ +A_STATUS +Hcd_Request(void *pCxt, void *pReq) +{ + A_STATUS status = A_OK; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint32_t transLength = 0; + + do + { + if (pDCxt->booleans & SDHD_BOOL_FATAL_ERROR) + { + status = A_HARDWARE; + break; + } + + if (pDCxt->booleans & SDHD_BOOL_SHUTDOWN) + { + status = A_ECANCELED; + break; + } + /* check if we need to change byte swap logic + * TODO : normally DMADataWidth does not change, however for testing + * purposes we allow the width to change dynamically through a config request */ + if (A_OK != (status = ConfigureByteSwap(pCxt, pDCxt->spi_hcd.DMADataWidth))) + { + break; + } + + if (ATH_IS_TRANS_READ(pReq)) + { + status = DoDMAOp(pCxt, pReq); + } + else + { + transLength = A_NETBUF_GET_ELEM(pReq, A_REQ_TRANSFER_LEN); + + /* for writes we keep track of the write buffer space */ + ADJUST_WRBUF_SPACE(pDCxt, transLength); + /* fire off the write operation */ + status = DoDMAOp(pCxt, pReq); + } + } while (false); + + return status; +} + +boolean Hcd_ReadCPUInterrupt(void *pCxt, uint8_t *cpuIntrCause) +{ + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + uint8_t data; + boolean ret = 1; + + A_NETBUF_CONFIGURE(pReq, &data, 0, sizeof(uint8_t), sizeof(uint8_t)); + + do + { + ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, CPU_INT_STATUS_ADDRESS, true, sizeof(uint8_t)); + + if (A_OK != Hcd_DoPioExternalAccess(pCxt, pReq)) + { + ret = 0; + break; + } + *cpuIntrCause = data; + } while (0); + + return ret; +} + +void Hcd_ClearCPUInterrupt(void *pCxt) +{ + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + uint8_t data; + + A_NETBUF_CONFIGURE(pReq, &data, 0, sizeof(uint8_t), sizeof(uint8_t)); + + do + { + data = 0xff; + + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, CPU_INT_STATUS_ADDRESS, true, sizeof(uint8_t)); + + if (A_OK != Hcd_DoPioExternalAccess(pCxt, pReq)) + { + break; + } + } while (0); +} + +/* Hcd_UnmaskInterrupts - Used to un-mask specific device interrupts + * function will write the SPI Interrupt Enable register with the resulting + * mask value. + * void *pCxt - the driver context. + * uint16_t Mask - bit mask indicating which interrupts should be + * unmasked. + *****************************************************************************/ +A_STATUS +Hcd_UnmaskInterrupts(void *pCxt, uint16_t Mask) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + pDCxt->spi_hcd.SpiIntEnableShadow |= Mask; + + if ((Mask & pDCxt->spi_hcd.SpiIntEnableShadow) == 0) + { + MaskSPIInterrupts(pCxt, Mask); + } + + return DoPioWriteInternal(pCxt, ATH_SPI_INTR_ENABLE_REG, (uint32_t)pDCxt->spi_hcd.SpiIntEnableShadow); +} + +void Hcd_EnableCPUInterrupt(void *pCxt) +{ + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + uint8_t data; + + A_NETBUF_CONFIGURE(pReq, &data, 0, sizeof(uint8_t), sizeof(uint8_t)); + + do + { + data = 0xff; + + ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, CPU_INT_STATUS_ENABLE_ADDRESS, true, sizeof(uint8_t)); + + if (A_OK != Hcd_DoPioExternalAccess(pCxt, pReq)) + { + break; + } + } while (0); +} + +/*****************************************************************************/ +/* HcdSpiInterrupt - Used to process an Interrupt from the device. It reads + * the SPI_INTR_CAUSE register to learn the reason(s) for the interrupt. + * Error causes are handled inside this function and other reasons are + * stored and used to notify other driver layers. + * void *pCxt - the driver context. + *****************************************************************************/ +boolean Hcd_BusInterrupt(void *pCxt) +{ + A_STATUS status; + boolean notifyFunctionIRQs = false; + uint32_t interrupts, entry_interrupts, entry_mask; + uint32_t hostIrqs; + uint32_t param; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + /* check for pending DMA HW transfers */ + if (pDCxt->booleans & SDHD_BOOL_DMA_IN_PROG) + { + /* The DMA engine owns the hardware. We may not have been able to stop this task/thread + * from running, so we need to abort processing interrupts immediately. + * The SPI interrupts would have been disabled at this point so we can pick up the pending + * interrupts later when the DMA completion routine turns interrupts back on */ + /* exit immediately, we do not want to turn the interrupts back on */ + return true; + } + + do + { + /* read the Interrupt Cause register to determine the reason(s) for the interrupt */ + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_INTR_CAUSE_REG, &interrupts))) + { + break; + } + + /* save first interrupt flags and mask */ + entry_interrupts = interrupts; + entry_mask = pDCxt->spi_hcd.SpiIntEnableShadow; + + interrupts &= pDCxt->spi_hcd.SpiIntEnableShadow; + /* get the HCD-owned IRQs */ + hostIrqs = interrupts & (ATH_SPI_HCD_IRQ_SOURCES | ATH_SPI_INTR_HOST_CTRL_ACCESS_DONE); + + /* before processing HCD-owned IRQ sources we need to Ack them, some processing + * may cause additional bus requests which can generate more interrupts , we want to + * avoid clearing an interrupt that might be valid */ + + if (hostIrqs) + { + /* ack interrupts that are HCD owned */ + if (A_OK != (status = DoPioWriteInternal(pCxt, ATH_SPI_INTR_CAUSE_REG, hostIrqs))) + { + break; + } + } + + /* process errors */ + if (interrupts & ATH_SPI_HCD_ERROR_IRQS) + { + /* if an error has occurred the device will need to be reset before + * any new communication can be attempted. There is not graceful + * recovery from one of these errors. */ + if (interrupts & ATH_SPI_INTR_ADDRESS_ERROR) + { + // REL_PRINT(SDDBG_ERROR, ("ATH SPI - ADDRESS ERROR \n")); + } + + if (interrupts & ATH_SPI_INTR_WRBUF_ERROR) + { + // REL_PRINT(SDDBG_ERROR, ("ATH SPI - WRBUF ERROR \n")); + } + + if (interrupts & ATH_SPI_INTR_RDBUF_ERROR) + { + // REL_PRINT(SDDBG_ERROR, ("ATH SPI - RDBUF ERROR \n")); + } + /* ack error interrupts */ + DoPioWriteInternal(pCxt, ATH_SPI_INTR_CAUSE_REG, interrupts & ATH_SPI_HCD_ERROR_IRQS); + + interrupts &= ~ATH_SPI_HCD_ERROR_IRQS; + pDCxt->booleans |= SDHD_BOOL_FATAL_ERROR; + /* mask all interrupts */ + DoPioWriteInternal(pCxt, ATH_SPI_INTR_ENABLE_REG, 0); + break; + } + + if (interrupts & ATH_SPI_INTR_HOST_CTRL_ACCESS_DONE) + { + /* this should not happen */ + interrupts &= ~ATH_SPI_INTR_HOST_CTRL_ACCESS_DONE; + + /* mask host access interrupts */ + MaskSPIInterrupts(pCxt, (ATH_SPI_INTR_HOST_CTRL_RD_DONE | ATH_SPI_INTR_HOST_CTRL_WR_DONE)); + } + + if (interrupts & ATH_SPI_INTR_WRBUF_BELOW_WMARK) + { + interrupts &= ~ATH_SPI_INTR_WRBUF_BELOW_WMARK; + /* disable interrupt */ + MaskSPIInterrupts(pCxt, ATH_SPI_INTR_WRBUF_BELOW_WMARK); + /* check to see if we need to start any pending DMA waiting on more buffer space */ + if (pDCxt->booleans & SDHD_BOOL_DMA_WRITE_WAIT_FOR_BUFFER) + { + /* re-cache the buffer space available register */ + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_WRBUF_SPC_AVA_REG, ¶m))) + { + break; + } + + pDCxt->spi_hcd.WriteBufferSpace = param; + pDCxt->booleans &= ~SDHD_BOOL_DMA_WRITE_WAIT_FOR_BUFFER; + /* reset water mark */ + if (A_OK != (status = ResetWriteBufferWaterMark(pCxt))) + { + break; + } + } + } + /* check to see if any other sources remain, these belong to the function driver */ + + if (interrupts & ATH_SPI_INTR_PKT_AVAIL) + { + /* If there are pending interrupts of interest to the function driver + * we disable all function-driver IRQ sources while the function driver processes + * the interrupt event. This allows the host driver to continue processing + * host access done and write buffer water mark interrupts. + * + * The function driver will re-enable sources when it is done */ + MaskSPIInterrupts(pCxt, ATH_SPI_INTR_PKT_AVAIL); + + /* if flood is detected, postpone driver task */ + if ((entry_interrupts & entry_mask) == 0x1) + { + uint32_t tmp = 0; + status = Hcd_DoPioInternalAccess(pCxt, ATH_SPI_RDBUF_BYTE_AVA_REG, &tmp, true); + assert(A_OK == status); + if (tmp == 0) + { + wait_us(5 * 1000); + } + } + + notifyFunctionIRQs = true; + } + + /* process the CPU interrupt */ + if (interrupts & ATH_SPI_INTR_LOCAL_CPU_INTR) + { + MaskSPIInterrupts(pCxt, ATH_SPI_INTR_CPU_INTR | ATH_SPI_INTR_LOCAL_CPU_INTR); + pDCxt->spi_hcd.CpuInterrupt = 1; + } + } while (0); + + if ((pDCxt->booleans & SDHD_BOOL_DMA_IN_PROG) == 0) + { + /* re-enable SPI interrupt detection at the hardware layer, note we always enable the + * SPI interrupt so that the HCD can get host-access-done interrupts. + * Note also that we do not enable interrupts if a DMA transfer is in progress */ + EnableDisableSPIIRQHwDetect(pCxt, true); + } + + if (notifyFunctionIRQs) + { + pDCxt->spi_hcd.PendingIrqAcks = 1 << 1; + } + + if (A_OK != status) + { + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + return false; +#endif + } + + return true; +} + +/*****************************************************************************/ +/* Hcd_ReinitTarget - Used to re-initialize the device. If the HCD layer is + * already up but the device has been shutdown and needs to be re-started + * this function can be used to bring the chip out of reset and set the + * write buffer watermark. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Hcd_ReinitTarget(void *pCxt) +{ + A_STATUS status; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + if (A_OK != (status = DoPioWriteInternal(pCxt, ATH_SPI_CONFIG_REG, pDCxt->spi_hcd.SpiConfigShadow))) + { + break; + } + + if (A_OK != (status = ResetWriteBufferWaterMark(pCxt))) + { + break; + } + + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_HCD_ERROR_IRQS); + /* Enable the CPU interrupt so that the first interrupt + * is not lost. */ + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_INTR_LOCAL_CPU_INTR); + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Hcd_Deinitialize - Used to de-initialize the HCD layer. Conditionally + * write the SPI config register to reset the device. + * void *pCxt - the driver context. + *****************************************************************************/ +void Hcd_Deinitialize(void *pCxt) +{ + if (GET_DRIVER_COMMON(pCxt)->spi_hcd.MiscFlags & MISC_FLAG_RESET_SPI_IF_SHUTDOWN) + { + /* reset spi */ + DoPioWriteInternal(pCxt, ATH_SPI_CONFIG_REG, ATH_SPI_CONFIG_RESET); + } +} + +/*****************************************************************************/ +/* Hcd_GetLookAhead - Interacts with device over SPI to acquire lookahead + * structure. This structure provides details of a rx packet. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Hcd_GetLookAhead(void *pCxt) +{ + A_STATUS status; + uint16_t lookAhead1, lookAhead2; + uint32_t bytesAvail; + uint32_t assembledLookAhead; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* get the bytes available in the SPI buffer */ + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_RDBUF_BYTE_AVA_REG, &bytesAvail))) + { + break; + } + + pDCxt->spi_hcd.ReadBufferSpace = bytesAvail; + /* is there a header's worth ?*/ + if (bytesAvail < 4) + { + /* not enough bytes for the look-ahead */ + break; + } + + /* peak into the SPI read buffer using the look aheads since we + * established that there is at least a look-ahead number of bytes */ + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_RDBUF_LOOKAHEAD1_REG, &assembledLookAhead))) + { + break; + } + + lookAhead1 = (uint16_t)assembledLookAhead; + + if (A_OK != (status = DoPioReadInternal(pCxt, ATH_SPI_RDBUF_LOOKAHEAD2_REG, &assembledLookAhead))) + { + break; + } + + lookAhead2 = (uint16_t)assembledLookAhead; + /* the lookaheads were already converted to native Endian by DoPioReadInternal + * however for the assembledLookAhead code to work properly for both + * big E and little E it must be converted again for little E. + */ + lookAhead1 = A_BE2CPU16(lookAhead1); + lookAhead2 = A_BE2CPU16(lookAhead2); + /* assemble look-ahead , first we need to swap bytes */ + ((uint8_t *)&assembledLookAhead)[0] = ((uint8_t *)&lookAhead1)[0]; + ((uint8_t *)&assembledLookAhead)[1] = ((uint8_t *)&lookAhead1)[1]; + ((uint8_t *)&assembledLookAhead)[2] = ((uint8_t *)&lookAhead2)[0]; + ((uint8_t *)&assembledLookAhead)[3] = ((uint8_t *)&lookAhead2)[1]; + + A_ASSERT(assembledLookAhead != 0); + pDCxt->lookAhead = assembledLookAhead; + } while (0); + + return status; +} + +/* Hcd_Init - Used to initialize the Host Controller Driver (HCD) layer. Uses + * SPI API to write the SPI config register which will bring the device + * out of reset. reads the WRITE buffer space register to learn the default + * size for this fifo. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Hcd_Init(void *pCxt) +{ + A_STATUS status; + uint32_t startUpClock; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + // if (0 == (pDCxt->spi_hcd.SpiHWCapabilitiesFlags & (HW_SPI_FRAME_WIDTH_8 | HW_SPI_FRAME_WIDTH_16))) { + // /* We minimally require 8 and 16 bit frame widths + // * 16-bits - Command/Addr frames + // * 8-bits - data frames including early termination */ + // status = A_ERROR; + // A_ASSERT(0); + //#if DRIVER_CONFIG_DISABLE_ASSERT + // break; + //#endif + // } + + /* the SPI module has byte swapping capability for DMA requests and we will be turning it on + * set the DMA buffer copy mode to not swap */ + pDCxt->booleans &= ~SDHD_BOOL_HOST_DMA_COPY_MODE; + /* for host access data frames, byte swaping is required */ + pDCxt->booleans |= SDHD_BOOL_HOST_ACCESS_COPY_MODE; + + if (pDCxt->spi_hcd.SpiHWCapabilitiesFlags & HW_SPI_FRAME_WIDTH_32) + { + pDCxt->spi_hcd.HostAccessDataWidth = ATH_TRANS_DS_32; + pDCxt->spi_hcd.DMADataWidth = ATH_TRANS_DS_32; + } + else if (pDCxt->spi_hcd.SpiHWCapabilitiesFlags & HW_SPI_FRAME_WIDTH_8) + { + pDCxt->spi_hcd.HostAccessDataWidth = ATH_TRANS_DS_8; + pDCxt->spi_hcd.DMADataWidth = ATH_TRANS_DS_8; + pDCxt->booleans &= ~SDHD_BOOL_HOST_ACCESS_COPY_MODE; + } + else + { + pDCxt->spi_hcd.HostAccessDataWidth = ATH_TRANS_DS_16; + pDCxt->spi_hcd.DMADataWidth = ATH_TRANS_DS_16; + } + pDCxt->spi_hcd.SpiConfigShadow = 0; + + startUpClock = AR4XXX_NORMAL_CLOCK_RATE; + + if (startUpClock > pDCxt->spi_hcd.OperationalClock) + { + /* the hardware layer wants a clock rate that is less than the normal rate */ + startUpClock = pDCxt->spi_hcd.OperationalClock; + } + + if (pDCxt->spi_hcd.OperationalClock > AR4XXX_NORMAL_CLOCK_RATE) + { + /* when operating above the normal clock rate, we need to enable some + * logic to improve timing margins. + * *** NOTE : setting the config register must be done at our startup clock rate. + * We can switch to the higher clock rate once the SPI config register is written + * */ + pDCxt->spi_hcd.SpiConfigShadow |= (0x1 << ATH_SPI_CONFIG_MISO_MUXSEL_MASK_SHIFT); + } + + /* set our startup clock mode, the config register must be written with the startup clock + * rate */ + HW_SET_CLOCK(pCxt, &startUpClock); + + /* start off with the I/O enable bit and byte swapping turned off */ + pDCxt->spi_hcd.SpiConfigShadow |= ATH_SPI_CONFIG_IO_ENABLE; + + if (ATH_TRANS_DS_32 == pDCxt->spi_hcd.DMADataWidth) + { + /* enable byte swapping logic, default is 32 bit mode */ + pDCxt->spi_hcd.SpiConfigShadow |= ATH_SPI_CONFIG_BYTE_SWAP; + } + else if (ATH_TRANS_DS_16 == pDCxt->spi_hcd.DMADataWidth) + { + /* enable byte swapping logic for 16 bit mode */ + pDCxt->spi_hcd.SpiConfigShadow |= (ATH_SPI_CONFIG_SWAP_16BIT | ATH_SPI_CONFIG_BYTE_SWAP); + } + else + { + /* for 8 bit mode, do not turn on byte swapping */ + } + +/* delay a bit before our first SPI operation */ +#if ENABLE_FPGA_BUILD + HW_USEC_DELAY(pCxt, pDCxt->hcd.PowerUpDelay * 500000); +#else + HW_USEC_DELAY(pCxt, pDCxt->spi_hcd.PowerUpDelay * 1000); +#endif + + // FIRST SPI OPERATION START!!! + status = DoPioWriteInternal(pCxt, ATH_SPI_CONFIG_REG, pDCxt->spi_hcd.SpiConfigShadow); + + Api_BootProfile(pCxt, BOOT_PROFILE_DONE_CONFIG); + + if (A_OK != status) + { + break; + } + /* SPI configuration has been written, we can safely switch to the desired operating clock rate */ + startUpClock = pDCxt->spi_hcd.OperationalClock; + HW_SET_CLOCK(pCxt, &startUpClock); + + /* read the buffer space available for this chip, at reset we should have an empty buffer */ + status = DoPioReadInternal(pCxt, ATH_SPI_WRBUF_SPC_AVA_REG, &pDCxt->spi_hcd.WriteBufferSpace); + assert(A_OK == status); +// DoPioReadInternal(pDevice,ATH_SPI_WRBUF_SPC_AVA_REG,&pDevice->WriteBufferSpace); +#if 0 +{ +int i=0; +while(i<50000){ + DoPioReadInternal(pCxt, ATH_SPI_WRBUF_SPC_AVA_REG, (uint32_t*)&test); + if(test == EXPECTED_MAX_WRITE_BUFFER_SPACE){ + good++; + }else{ + bad++; + } + test = 0; + i++; +} +} +#endif + + if (A_OK != status) + { + break; + } + + /* save this off for watermark level calculations */ + pDCxt->spi_hcd.MaxWriteBufferSpace = pDCxt->spi_hcd.WriteBufferSpace; + + // printf("%d\r\n", pDCxt->spi_hcd.MaxWriteBufferSpace); + /* NOTE: if this assert fails it suggests that SPI communication with the WIFI device + * is not functioning. Perhaps the 2 chips are not connected. */ + A_ASSERT((uint16_t)pDCxt->spi_hcd.MaxWriteBufferSpace == EXPECTED_MAX_WRITE_BUFFER_SPACE); + /* set write buffer watermark to zero, we only set it when we need an interrupt */ + if (A_OK != (status = ResetWriteBufferWaterMark(pCxt))) + { + break; + } + /* Enable error IRQ sources */ + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_HCD_ERROR_IRQS); + /* Enable the CPU interrupt so that the first interrupt + * is not lost. */ + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_INTR_LOCAL_CPU_INTR); + /* enable interrupts at the HW layer */ + EnableDisableSPIIRQHwDetect(pCxt, true); + /* this delay is necessary to prevent other driver code from accessing + * the chip before it has had sufficient time to boot. accessing + * prematurely will put the chip in a failed state. + */ + A_MDELAY(2); + } while (false); + + return status; +} + +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + HcdTransferData - transfer data state machine + Input: pDevice - device object + pReq - transfer request + Output: + Return: + Notes: This state machine handles the data phases of a DMA request or an external I/O access through + the read and write ports. + This state machine handles early termination of bytes and transfers bytes manually if + the remaining bytes is small. + +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +// FIXME remove this function later +static A_STATUS Hcd_TransferData(void *pCxt, void *pReq) +{ + return Bus_InOutDescriptorSet(pCxt, pReq); +} + +#endif //#if 1 //Common HCD API's + +/*****************************************************************************/ +void HW_EnableDisableSPIIRQ(void *pCxt, boolean Enable, boolean FromIrq) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + if (false == FromIrq) + { + IRQEN_ACCESS_ACQUIRE(pCxt); + OSA_EnterCritical(kCriticalDisableInt); + } + + do + { + if (Enable) + { + if (false == pDCxt->spi_hcd.IrqsEnabled) + { + pDCxt->spi_hcd.IrqsEnabled = true; + // Custom_Hcd_EnableDisableSPIIRQ(pCxt, Enable); + } + } + else + { + if (true == pDCxt->spi_hcd.IrqsEnabled) + { + pDCxt->spi_hcd.IrqsEnabled = false; + // Custom_Hcd_EnableDisableSPIIRQ(pCxt, Enable); + } + } + } while (0); + + if (false == FromIrq) + { + OSA_ExitCritical(kCriticalDisableInt); + IRQEN_ACCESS_RELEASE(pCxt); + } +} + +/*****************************************************************************/ +/* BUS_InOut_DescriptorSet - Attempts to read OR write a set of buffers + * on the BUS (SPI or other). The effort is required to occur synchronously + * if the sync boolean is true. Otherwise it may optionally occur + * asynchronously. If the underlying bus cannot satisfy a synchronous + * request then the custom code must by written in such a way that + * any asychronous activity is handled under the covers. + * void * pCxt - the driver context. + * A_TRANSPORT_OBJ *pObj - The object containing the buffers. + * boolean sync - indication of synchronous or asynchronous completion. + *****************************************************************************/ +A_STATUS +Bus_InOutDescriptorSet(void *pCxt, void *pReq) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + A_STATUS status; + uint16_t i, totalLength; + boolean sync = (A_NETBUF_GET_ELEM(pReq, A_REQ_CALLBACK) != NULL) ? false : true; + uint8_t *pBuf; + int32_t length; + uint8_t doRead; + + doRead = (A_NETBUF_GET_ELEM(pReq, A_REQ_COMMAND) & ATH_TRANS_READ) ? 1 : 0; + + do + { + /* Custom_Bus_Start_Transfer - allows the custom solution + * to perform any pre transfer operations such as + * changing the SPI chip select if necessary. */ + if (A_OK != (status = CUSTOM_BUS_START_TRANSFER(pCxt, sync))) + { + break; + } + + i = 0; + totalLength = 0; + + while (NULL != (pBuf = A_NETBUF_GET_FRAGMENT(pReq, i, &length))) + { + if (length) + { + /* Submit each buffer with a length to the underlying custom + * bus solution. whether the buffers actually transfer in + * the context of this function call is up to the solution. + */ + if (A_OK != (status = CUSTOM_BUS_INOUT_BUFFER(pCxt, pBuf, length, doRead, sync))) + { + break; + } + } + + totalLength += length; + i++; + } + /* account for any padding bytes that were not part of the request length */ + if (totalLength < A_NETBUF_GET_ELEM(pReq, A_REQ_TRANSFER_LEN)) + { + A_ASSERT((uint32_t)(A_NETBUF_GET_ELEM(pReq, A_REQ_TRANSFER_LEN) - totalLength) <= pDCxt->blockSize); + + status = CUSTOM_BUS_INOUT_BUFFER(pCxt, (uint8_t *)pDCxt->padBuffer, + A_NETBUF_GET_ELEM(pReq, A_REQ_TRANSFER_LEN) - totalLength, doRead, sync); + } + + /* Custom_Bus_Complete_Transfer - allows the custom solution + * to perform any post transfer operations such as + * changing the SPI chip select if necessary. */ + if (A_OK == status) + { + status = CUSTOM_BUS_COMPLETE_TRANSFER(pCxt, sync); + } + } while (0); + return status; +} + +/*****************************************************************************/ +/* BUS_InOut_Token - Attempts to read AND write 4 or less bytes on the SPI bus. + * The effort is expected to occur synchronously so that when the function + * call returns the operation will have completed. If the underlying + * bus cannot satisfy this requirement then Custom_InOut_Token must be + * written in such a way that any asychronous activity is handled under + * the covers. + * void * pCxt - the driver context. + * uint32_t OutToken - 4 or less bytes of write data. + * uint8_t dataSize - length of data. + * uint32_t *pInToken - pointer to memory to store 4 or less bytes of + * read data. + *****************************************************************************/ +A_STATUS +Bus_InOutToken(void *pCxt, uint32_t OutToken, uint8_t DataSize, uint32_t *pInToken) +{ + uint32_t dummy; + A_STATUS status; + + if (pInToken == NULL) + { + pInToken = &dummy; + } + + DataSize += 1; // data size if really a enum that is 1 less than number of bytes +#if A_BIG_ENDIAN + // because OutToken is passed in as a U32 the + // valid bytes will be the last bytes as this + // is a big-endian cpu. so we need to shift + // the valid bytes over to eliminate the invalid bytes. + OutToken <<= (32 - (DataSize << 3)); +#endif + status = CUSTOM_BUS_INOUT_TOKEN(pCxt, OutToken, DataSize, pInToken); + + if (pInToken != &dummy) + { +#if A_BIG_ENDIAN + // reading less than 4 bytes requires that the bytes + // be shifted by the number of invalid bytes. + *pInToken >>= (32 - (DataSize << 3)); +#endif + } + + return status; +} + +/*****************************************************************************/ +/* BUS_TransferComplete - Callback for the Custom Bus solution to indicate + * when an asynchronous operation has completed. This function is intended + * to be called from an interrupt level context if required by the custom + * solution. + * void *pCxt - the driver context. + * A_STATUS status - A_OK if transfer completed successfully. + *****************************************************************************/ +void Bus_TransferComplete(void *pCxt, A_STATUS status) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + UNUSED_ARGUMENT(status); + if (0 == (pDCxt->booleans & SDHD_BOOL_DMA_IN_PROG)) + { + /* error condition */ + return; + } + + pDCxt->booleans |= SDHD_BOOL_DMA_COMPLETE; + pDCxt->booleans &= ~SDHD_BOOL_DMA_IN_PROG; + /* QueueWork will kick start the driver thread if needed to perform any + * any deferred work. */ + DRIVER_WAKE_DRIVER(pCxt); +} + +void HW_EnableDisableIRQ(void *pCxt, boolean Enable, boolean FromIrq) +{ + HW_EnableDisableSPIIRQ(pCxt, Enable, FromIrq); +} + +void Hcd_Irq(void *pCxt) +{ + /* pass global context to common layer */ + HW_InterruptHandler(p_Global_Cxt); + UNUSED_ARGUMENT(pCxt); +} + +void Hcd_MaskInterrupts(void *pCxt, uint16_t Mask) +{ + MaskSPIInterrupts(pCxt, Mask); +} + +#if 0 // TBD +/* +* The below 3-functions are need to implement and +* HCD_SUSPEND_CB and HCD_RESUME_CB structures are not avialable with +* current driver source +*/ + +void Hcd_AckInterrupt(void *pCxt, uint16_t Mask) +{ + //TBD +} + +void Hcd_RegisterSuspendHandler(HCD_SUSPEND_CB *suspendCallback, void *pSuspContext) +{ + //TBD +} + +void Hcd_RegisterResumeHandler(HCD_RESUME_CB *resumeCallback, void *pSuspContext) +{ + //TBD +} + +#endif //#if 0 diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/htc/htc.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/htc/htc.c new file mode 100644 index 00000000000..943860d9fd4 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/htc/htc.c @@ -0,0 +1,960 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "wifi_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hw20_mbox_host_reg.h" +#include + +//#include "htc_internal.h" + +extern uint8_t reverse_credits_init; +uint8_t trailor[sizeof(HTC_RECORD_HDR) + 6 * sizeof(HTC_CREDIT_REPORT)]; + +void Htc_PrepareRecvPacket(void *pCxt, void *pReq) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + HTC_FRAME_HDR *pHTCHdr; + uint16_t validLength, transLength; + + pHTCHdr = (HTC_FRAME_HDR *)&(pDCxt->lookAhead); + /* Credits are only used in TX so init to 0 here. */ + A_NETBUF_SET_ELEM(pReq, A_REQ_CREDITS, 0); + /* get the endpoint ID from the lookahead */ + A_NETBUF_SET_ELEM(pReq, A_REQ_EPID, pHTCHdr->EndpointID); + /* calc the full recv length */ + validLength = A_LE2CPU16(pHTCHdr->PayloadLen) + sizeof(HTC_FRAME_HDR); + transLength = DEV_CALC_RECV_PADDED_LEN(pDCxt, validLength); + /* init the packet length = payloadLen + sizeof(HTC_FRAME_HDR) + */ + /* NOTE: For receive packets the request transfer length and actual buffer length are the same + * this may not be true for transmit as the driver does not have control of the transmit + * buffers. + */ + A_NETBUF_PUT(pReq, transLength); + A_NETBUF_SET_ELEM(pReq, A_REQ_TRANSFER_LEN, transLength); + /* init the packet lookahead value */ + A_NETBUF_SET_ELEM(pReq, A_REQ_LOOKAHEAD, pDCxt->lookAhead); +} + +/*****************************************************************************/ +/* HTC_RxComplete - Completes processing of received packets whose + * endpoint ID == ENDPOINT_0. This is the special HTC control endpoint. + * void *pCxt - the driver context. + * void *pReq - the packet. + *****************************************************************************/ +void Htc_RxComplete(void *pCxt, void *pReq) +{ + UNUSED_ARGUMENT(pCxt); + /* the only control messages we are expecting are NULL messages (credit resports) */ + if (A_NETBUF_LEN(pReq) > 0) + { + A_ASSERT(0); + } + + A_NETBUF_FREE(pReq); +} + +uint32_t Htc_ReadCreditCounter(void *pCxt, uint32_t index) +{ + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + uint32_t collector; + + A_NETBUF_CONFIGURE(pReq, &collector, 0, sizeof(uint32_t), sizeof(uint32_t)); + /* read the target credit counter */ + ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, COUNT_ADDRESS + 4 * index, true, sizeof(uint32_t)); + + if (A_OK != Hcd_DoPioExternalAccess(pCxt, pReq)) + { + A_ASSERT(0); + } + + collector = A_LE2CPU32(collector); + + return collector; +} + +void Htc_GetCreditCounterUpdate(void *pCxt, uint16_t epId) +{ + A_ENDPOINT_T *pEp; + uint32_t collector; + uint16_t reg_index, array_index; +#if USE_16BIT_CREDIT_COUNTER + uint16_t credits; +#else + uint8_t credits; +#endif + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + pEp = Util_GetEndpoint(pCxt, epId); + + if (pDCxt->htc_creditInit == 0) + { + /* never got interrupt from chip to indicate that this + * credit scheme was supported */ + pEp->intCreditCounter = 0; + return; + } + + reg_index = pEp->epIdx >> 2; + array_index = pEp->epIdx & 0x03; + /* read the target credit counter */ + collector = Htc_ReadCreditCounter(pCxt, reg_index); + +#if USE_16BIT_CREDIT_COUNTER + credits = (collector >> (8 * array_index)) & 0xffff; // modify this credits variable to 16bit + if ((credits & 0xFF00) >> 8) + { + credits = 255 + ((credits & 0xFF00) >> 8); + // ath_io_printf("Credits 0x%x \n",255 + ((credits & 0xFF00) >> 8)); + } + else + { + credits = (credits & 0xFF); + } +#else + credits = (collector >> (8 * array_index)) & 0xff; +#endif + pEp->intCreditCounter = credits; + credits = pEp->intCreditCounter - pEp->rptCreditCounter; + + /* The below condition occurs when we stop recieving in-band credits and are purely relying */ + /* on out-of-band credits. In such cases it is possible that out-of-band credit can wrap around and this prevents + * the same */ + if (credits < pEp->intCredits) + { + return; + } + + credits = credits - pEp->intCredits; // deduct any previous int credits + pEp->intCredits += credits; // track num credits acquired this way. + /* add the new credits to the EP credit count */ + pEp->credits += credits; +} + +static void Htc_DistributeCredits(void *pCxt) +{ + uint32_t numCredits; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + numCredits = (uint16_t)pDCxt->creditCount; + pDCxt->ep[0].maxCredits = pDCxt->ep[0].credits = 1; + pDCxt->ep[0].rptCreditCounter = 0; + pDCxt->ep[0].intCreditCounter = 0; + pDCxt->ep[0].intCredits = 0; + numCredits--; + pDCxt->ep[1].maxCredits = pDCxt->ep[1].credits = 1; + pDCxt->ep[1].rptCreditCounter = 0; + pDCxt->ep[1].intCreditCounter = 0; + pDCxt->ep[1].intCredits = 0; + numCredits--; + +#if USE_16BIT_CREDIT_COUNTER + pDCxt->ep[2].maxCredits = pDCxt->ep[2].credits = (uint16_t)numCredits; +#else + pDCxt->ep[2].maxCredits = pDCxt->ep[2].credits = (uint8_t)numCredits; +#endif + pDCxt->ep[2].rptCreditCounter = 0; + pDCxt->ep[2].intCreditCounter = 0; + pDCxt->ep[2].intCredits = 0; +} + +/* process credit reports and call distribution function */ +static void Htc_ProcessCreditRpt(void *pCxt, HTC_CREDIT_REPORT *pRpt, int32_t NumEntries, HTC_ENDPOINT_ID FromEndpoint) +{ + int i; + A_ENDPOINT_T *pEndpoint; +#if USE_16BIT_CREDIT_COUNTER + uint16_t credits; +#else + uint8_t credits; +#endif + UNUSED_ARGUMENT(FromEndpoint); + + for (i = 0; i < NumEntries; i++) + { + if (pRpt[i].EndpointID >= ENDPOINT_MAX) + { + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif + } + + pEndpoint = Util_GetEndpoint(pCxt, pRpt[i].EndpointID); + /* this variable will and should wrap around. */ + pEndpoint->rptCreditCounter += pRpt[i].Credits; + + credits = pRpt[i].Credits; + + if (pEndpoint->intCredits) + { + if (pEndpoint->intCredits <= pRpt[i].Credits) + { + credits = pRpt[i].Credits - pEndpoint->intCredits; + pEndpoint->intCredits = 0; + } + else + { + credits = 0; + pEndpoint->intCredits -= pRpt[i].Credits; + } + } + + pEndpoint->credits += credits; + } +} + +/* Interrupt cause register bit definitions: + * bit 0 - used for initial credit distribution + * bit 1 - Start of frame in Argos + * bit 2-7 - unused + */ +void HTC_ProcessCpuInterrupt(void *pCxt) +{ + A_NETBUF_DECLARE req; + void *pReq = (void *)&req; + uint32_t collector; + uint8_t *ptr = (uint8_t *)&collector; + + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + /* The interrupt cause register indicates the reason who raised + * this interrupt. Use it to decode*/ + /* bit 0 is for credit distribution */ + if (pDCxt->spi_hcd.CpuInterruptCause & 0x1) + { + /* if this is the first such interrupt then acquire the + * address of the HTC comm memory. */ + A_NETBUF_CONFIGURE(pReq, &collector, 0, sizeof(uint32_t), sizeof(uint32_t)); + + if (pDCxt->htc_creditInit == 0) + { + pDCxt->htc_creditInit = 1; + ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, COUNT_ADDRESS + 4, true, sizeof(uint32_t)); + + if (A_OK != Hcd_DoPioExternalAccess(pCxt, pReq)) + { + A_ASSERT(0); + } + + /* the last byte of the COUNT_ADDRESS contain the creditCount */ + pDCxt->creditCount = ptr[3]; + /* distribute the credits among the endpoints */ + Htc_DistributeCredits(pCxt); + } + } + + /* bit 1 is for SOF in argos */ + if (pDCxt->spi_hcd.CpuInterruptCause & 0x2) + { + // printf("SOF intr\n"); + } + + /* All interrupts have been processed */ + pDCxt->spi_hcd.CpuInterruptCause = 0x0; +} + +/*****************************************************************************/ +/* Htc_ProcessTrailer - Trailers can be appended to the end of a received + * packet. This function processes those trailers prior to their removal + * from the packet. + * void *pCxt - the driver context. + * uint8_t *pBuffer - the buffer holding the trailers. + * int32_t Length - the length of the pBuffer in bytes. + * uint32_t *pNextLookAheads - storage for any lookaheads found in + * the trailer. + * int32_t *pNumLookAheads - storage for a count of valid lookaheads + * stored in pNextLookAheads. + * HTC_ENDPOINT_ID FromEndpoint - the endpoint ID of the received packet. + *****************************************************************************/ +static A_STATUS Htc_ProcessTrailer(void *pCxt, + uint8_t *pBuffer, + int32_t Length, + uint32_t *pNextLookAheads, + uint32_t *pNumLookAheads, + HTC_ENDPOINT_ID FromEndpoint) +{ + HTC_RECORD_HDR *pRecord; + uint8_t *pRecordBuf; + HTC_LOOKAHEAD_REPORT *pLookAhead; + A_STATUS status; + + status = A_OK; + + while (Length > 0) + { + if (Length < (int32_t)sizeof(HTC_RECORD_HDR)) + { + status = A_EPROTO; + break; + } + /* these are byte aligned structs */ + pRecord = (HTC_RECORD_HDR *)pBuffer; + Length -= sizeof(HTC_RECORD_HDR); + pBuffer += sizeof(HTC_RECORD_HDR); + + if (pRecord->Length > Length) + { + /* no room left in buffer for record */ + status = A_EPROTO; + break; + } + /* start of record follows the header */ + pRecordBuf = pBuffer; + + switch (pRecord->RecordID) + { + case HTC_RECORD_CREDITS: /* the device is indicating that new TX credits are available */ + Htc_ProcessCreditRpt(pCxt, (HTC_CREDIT_REPORT *)pRecordBuf, + (int32_t)(pRecord->Length / (sizeof(HTC_CREDIT_REPORT))), FromEndpoint); + break; + case HTC_RECORD_LOOKAHEAD: /* the device is providing the lookahead for the next packet */ + A_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT)); + pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf; + if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) && (pNextLookAheads != NULL)) + { + /* look ahead bytes are valid, copy them over */ + ((uint8_t *)(&pNextLookAheads[0]))[0] = pLookAhead->LookAhead[0]; + ((uint8_t *)(&pNextLookAheads[0]))[1] = pLookAhead->LookAhead[1]; + ((uint8_t *)(&pNextLookAheads[0]))[2] = pLookAhead->LookAhead[2]; + ((uint8_t *)(&pNextLookAheads[0]))[3] = pLookAhead->LookAhead[3]; + + /* just one normal lookahead */ + *pNumLookAheads = 1; + } + break; + case HTC_RECORD_LOOKAHEAD_BUNDLE: +#if 0 /* this feature is not currently supported by this driver */ + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT)); + if (pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT) && + (pNextLookAheads != NULL)) { + HTC_BUNDLED_LOOKAHEAD_REPORT *pBundledLookAheadRpt; + int32_t i; + + pBundledLookAheadRpt = (HTC_BUNDLED_LOOKAHEAD_REPORT *)pRecordBuf; + + if ((pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))) > + HTC_HOST_MAX_MSG_PER_BUNDLE) { + /* this should never happen, the target restricts the number + * of messages per bundle configured by the host */ + A_ASSERT(false); + status = A_EPROTO; + break; + } + + for (i = 0; i < (int)(pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))); i++) { + ((uint8_t *)(&pNextLookAheads[i]))[0] = pBundledLookAheadRpt->LookAhead[0]; + ((uint8_t *)(&pNextLookAheads[i]))[1] = pBundledLookAheadRpt->LookAhead[1]; + ((uint8_t *)(&pNextLookAheads[i]))[2] = pBundledLookAheadRpt->LookAhead[2]; + ((uint8_t *)(&pNextLookAheads[i]))[3] = pBundledLookAheadRpt->LookAhead[3]; + pBundledLookAheadRpt++; + } + + *pNumLookAheads = i; + } + break; +#else + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif +#endif + + default: + break; + } + + if (A_OK != status) + { + break; + } + + /* advance buffer past this record for next time around */ + pBuffer += pRecord->Length; + Length -= pRecord->Length; + } + + if (A_OK != status) + { + A_ASSERT(0); + } + + return status; +} + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) +int hasRCSReport() +{ + uint8_t i; + +#if TWO_MSQ + for (i = 0; i < 8; i++) +#else + for (i = 1; i < 8; i++) +#endif + { + if (GET_CREDIT(i) != 0) + return true; + } + return false; +} + +static int CollectCredits(uint8_t *buff, int lenFreeTrail) +{ + HTC_RECORD_HDR *hd; + HTC_CREDIT_REPORT *rec; + + int len = 0; + uint8_t i; + + hd = (HTC_RECORD_HDR *)buff; + rec = (HTC_CREDIT_REPORT *)(buff + sizeof(HTC_RECORD_HDR)); + +// qosal_intr_disable(); + +#if TWO_MSQ + for (i = 0; i < 8; i++) +#else + for (i = 1; i < 8; i++) +#endif + { + if (len + sizeof(HTC_CREDIT_REPORT) > lenFreeTrail) + break; + + if (GET_CREDIT(i) != 0) + { + rec->EndpointID = i; + rec->Credits = GET_CREDIT(i); + CLEAR_CREDIT(i); + + len += sizeof(HTC_CREDIT_REPORT); + rec++; + } + } + hd->RecordID = HTC_RECORD_CREDITS; + hd->Length = len; + + len += sizeof(HTC_RECORD_HDR); + // send_reverse_credits_flag = 0; + + // qosal_intr_enable(); + + return len; +} +#endif + +A_NETBUF *p; + +A_STATUS +Htc_SendPacket(void *pCxt, void *pReq) +{ + A_STATUS status = A_ERROR; + A_ENDPOINT_T *pEp; + uint8_t htcFlags = 0; + uint8_t SeqNo = 0; + uint8_t *pHdrBuf; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /* adjust the Endpoint credit count */ + if (NULL == (pEp = Util_GetEndpoint(pCxt, A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)))) + { + break; + } + if (pDCxt->htcStart == true) + { + if (0 == pEp->credits) + { + break; + } + + if (A_NETBUF_GET_ELEM(pReq, A_REQ_CREDITS) == 0) + { + SeqNo = 0; + } + + A_ASSERT(A_NETBUF_GET_ELEM(pReq, A_REQ_CREDITS)); + pEp->credits -= A_NETBUF_GET_ELEM(pReq, A_REQ_CREDITS); + SeqNo = pEp->seqNo; + pEp->seqNo++; + + if (0 == pEp->credits) + { + htcFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE; + } + } + + pHdrBuf = A_NETBUF_DATA(pReq); + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) + if (reverse_credits_init != 0) + { + int lenRecord, lenFreeTrail; + uint8_t buff[sizeof(HTC_RECORD_HDR) + 6 * sizeof(HTC_CREDIT_REPORT)]; + uint8_t *data; + + if (A_NETBUF_GET_ELEM(pReq, A_REQ_EPID) == ENDPOINT_0) + { + lenFreeTrail = A_NETBUF_TAILROOM(pReq); + if (lenFreeTrail < 12) + { + p = (A_NETBUF *)pReq; + } + A_ASSERT(lenFreeTrail >= 12); + + lenRecord = CollectCredits(buff, lenFreeTrail); + + pHdrBuf = A_NETBUF_DATA(pReq); + if (lenRecord > sizeof(HTC_RECORD_HDR)) + { + A_NETBUF_PUT_DATA(pReq, buff, lenRecord); + htcFlags |= HTC_FLAGS_SEND_TRAILER; + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, ControlBytes[1], lenRecord); + } + else + { + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, ControlBytes[1], 0); + } + } + else + { + lenRecord = CollectCredits(buff, lenFreeTrail); + + pHdrBuf = A_NETBUF_DATA(pReq); + data = NULL; + + if (lenRecord > sizeof(HTC_RECORD_HDR)) + { + data = trailor; + } + + if (data != NULL) + { + A_MEMCPY(data, buff, lenRecord); + A_NETBUF_APPEND_FRAGMENT(pReq, data, lenRecord); + htcFlags |= HTC_FLAGS_SEND_TRAILER; + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, ControlBytes[1], lenRecord); + } + else + { + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, ControlBytes[1], 0); + } + } + } +#else + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, ControlBytes[1], (uint8_t)(SeqNo)); +#endif + /* fill in elements of the HTC header. treat the header as an un-aligned struct for safety */ + A_SET_UINT16_FIELD(pHdrBuf, HTC_FRAME_HDR, PayloadLen, (uint16_t)A_NETBUF_LEN(pReq) - HTC_HDR_LENGTH); + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, Flags, (htcFlags)); + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, EndpointID, (uint8_t)A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)); + A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR, ControlBytes[0], (uint8_t)(0)); + /* A_SET_UINT8_FIELD(pHdrBuf, HTC_FRAME_HDR,ControlBytes[1], (uint8_t)(SeqNo)); + */ + status = A_OK; + } while (0); + + return status; +} + +A_STATUS +Htc_ProcessTxComplete(void *pCxt, void *pReq) +{ + UNUSED_ARGUMENT(pCxt); + /* remove the HTC header from the front of the packet. */ + return A_NETBUF_PULL(pReq, HTC_HDR_LENGTH); +} + +/*****************************************************************************/ +/* HTC_ProcessRecvHeader - Processes HTC headers and removes them from the + * front of the packet. + * void *pCxt - the driver context. + * void *pReq - the packet. + * uint32_t *pNextLookAheads - storage for any lookaheads found in + * the trailer. + * int32_t *pNumLookAheads - storage for a count of valid lookaheads + * stored in pNextLookAheads. + *****************************************************************************/ +A_STATUS +Htc_ProcessRecvHeader(void *pCxt, void *pReq, uint32_t *pNextLookAheads, uint32_t *pNumLookAheads) +{ + uint8_t temp; + uint8_t *pBuf; + A_STATUS status = A_OK; + uint16_t payloadLen, bufLength; + uint32_t lookAhead; + + //NOTE: coverity fix + if (NULL == pNumLookAheads) + { + return A_ERROR; + } + + *pNumLookAheads = 0; + + do + { + bufLength = A_NETBUF_LEN(pReq); + /* gets the first buffer which will/must contain the HTC header */ + if (NULL == (pBuf = A_NETBUF_DATA(pReq)) || bufLength < HTC_HDR_LENGTH) + { + /* this is a critical error */ + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + status = A_EPROTO; + break; +#endif + } + /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to + * retrieve 16 bit fields */ + payloadLen = (uint16_t)A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen); + + ((uint8_t *)&lookAhead)[0] = pBuf[0]; + ((uint8_t *)&lookAhead)[1] = pBuf[1]; + ((uint8_t *)&lookAhead)[2] = pBuf[2]; + ((uint8_t *)&lookAhead)[3] = pBuf[3]; + + if (lookAhead != A_NETBUF_GET_ELEM(pReq, A_REQ_LOOKAHEAD)) + { + /* this is a critical error */ + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + status = A_EPROTO; + break; +#endif + } + /* now that the payloadLen and the HTC header has been confirmed + * remove any padding length that may have been added to the buffer + */ + if (payloadLen + HTC_HDR_LENGTH < A_NETBUF_LEN(pReq)) + { + A_NETBUF_TRIM(pReq, A_NETBUF_LEN(pReq) - (payloadLen + HTC_HDR_LENGTH)); + } + + /* get flags */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags); + + if (temp & HTC_FLAGS_RECV_TRAILER) + { + /* this packet has a trailer */ + + /* extract the trailer length in control byte 0 */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]); + + if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) + { + /* this is a critical error */ + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + status = A_EPROTO; + break; +#endif + } + /* process trailer data that follows HDR + application payload */ + if (A_OK != + (status = Htc_ProcessTrailer(pCxt, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp, pNextLookAheads, + pNumLookAheads, (HTC_ENDPOINT_ID)A_NETBUF_GET_ELEM(pReq, A_REQ_EPID)))) + { + break; + } + /* remove the trailer bytess via buffer trim */ + A_NETBUF_TRIM(pReq, temp); + } + /* if we get to this point, the packet is good */ + /* remove header and adjust length */ + A_NETBUF_PULL(pReq, HTC_HDR_LENGTH); + + } while (0); + + if (A_OK != status) + { + A_ASSERT(0); + } + + return status; +} + +A_STATUS +HTC_WaitTarget(void *pCxt) +{ + A_STATUS status; + // HTC_READY_EX_MSG *pRdyMsg; + HTC_SERVICE_CONNECT_REQ connect; + HTC_SERVICE_CONNECT_RESP resp; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + if (ath_custom_htc.HTCGetReady != NULL) + { + if (A_OK != (status = ath_custom_htc.HTCGetReady(pCxt))) + { + break; + } + } + else + { + pDCxt->creditCount = AR4100_DEFAULT_CREDIT_COUNT; // TODO: ??? + pDCxt->creditSize = AR4100_BUFFER_SIZE; + } + /* setup our pseudo HTC control endpoint connection */ + A_MEMZERO(&connect, sizeof(connect)); + A_MEMZERO(&resp, sizeof(resp)); + + connect.ServiceID = HTC_CTRL_RSVD_SVC; + + /* connect fake service */ + status = HTC_ConnectService(pCxt, &connect, &resp); + + if (!A_FAILED(status)) + { + break; + } + } while (false); + + return status; +} + +A_STATUS +HTC_ConnectService(void *pCxt, HTC_SERVICE_CONNECT_REQ *pConnectReq, HTC_SERVICE_CONNECT_RESP *pConnectResp) +{ + A_STATUS status = A_OK; + HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX; + A_ENDPOINT_T *pEndpoint; + uint32_t maxMsgSize = 0; + + do + { + if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) + { + /* special case for pseudo control service */ + assignedEndpoint = ENDPOINT_0; + maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH; + } + else + { + if (ath_custom_htc.HTCConnectServiceExch != NULL) + { + status = ath_custom_htc.HTCConnectServiceExch(pCxt, pConnectReq, pConnectResp, &assignedEndpoint, + &maxMsgSize); + + if (status != A_OK) + { + break; + } + } + else + { + pConnectResp->ConnectRespCode = HTC_SERVICE_SUCCESS; + + switch (pConnectReq->ServiceID) + { + case WMI_CONTROL_SVC: + assignedEndpoint = ENDPOINT_1; + maxMsgSize = 1542; + break; + case WMI_DATA_BE_SVC: + assignedEndpoint = ENDPOINT_2; + maxMsgSize = 4144; + break; + case WMI_DATA_BK_SVC: + assignedEndpoint = ENDPOINT_3; + maxMsgSize = 4144; + break; + case WMI_DATA_VI_SVC: + assignedEndpoint = ENDPOINT_4; + maxMsgSize = 4144; + break; + case WMI_DATA_VO_SVC: + assignedEndpoint = ENDPOINT_5; + maxMsgSize = 4144; + break; + } + } + } + + /* the rest of these are parameter checks so set the error status */ + status = A_EPROTO; + + if (0 == maxMsgSize) + { + A_ASSERT(0); +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif + } + + pEndpoint = Util_GetEndpoint(pCxt, assignedEndpoint); + /* this marks the endpoint in use */ + pEndpoint->serviceID = pConnectReq->ServiceID; + /* return assigned endpoint to caller */ + pConnectResp->Endpoint = assignedEndpoint; + pConnectResp->MaxMsgLength = maxMsgSize; + + pEndpoint->maxMsgLength = (int32_t)maxMsgSize; + + status = A_OK; + + } while (0); + + return status; +} + +/* Start HTC, enable interrupts and let the target know host has finished setup */ +A_STATUS +HTC_Start(void *pCxt) +{ + A_STATUS status = A_OK; + + do + { + Htc_DistributeCredits(pCxt); + + if (ath_custom_htc.HTCSendSetupComplete != NULL) + { + /* the caller is done connecting to services, so we can indicate to the + * target that the setup phase is complete */ + status = ath_custom_htc.HTCSendSetupComplete(pCxt); + + if (A_FAILED(status)) + { + break; + } + } + + /* unmask the packet interrupt on-chip */ + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_INTR_PKT_AVAIL); + GET_DRIVER_COMMON(pCxt)->htcStart = true; + } while (0); + + return status; +} + +/* synchronously wait for a message from the target, + */ +#if 0 +A_STATUS +Htc_WaitforMessage(HTC_HANDLE HTCHandle, HTC_PACKET **ppControlPacket, uint8_t EndpointID) +{ + A_STATUS status; + uint32_t lookAhead; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr; + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + do { + + /* call the polling function to see if we have a message */ + status = DevPollMboxMsgRecv(&target->Device, + &lookAhead, + HTC_TARGET_RESPONSE_TIMEOUT); + + if (A_FAILED(status)) { + break; + } + + /* check the lookahead */ + pHdr = (HTC_FRAME_HDR *)&lookAhead; + + if (pHdr->EndpointID != EndpointID) { + /* unexpected endpoint number, should be zero */ + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + /* bad message */ + status = A_EPROTO; + break; + } + + if(*ppControlPacket != NULL){ + pPacket = *ppControlPacket; + }else{ + pPacket = HTC_ALLOC_CONTROL_RX(target); + + if (pPacket == NULL) { + status = A_NO_MEMORY; + break; + } + } + + pPacket->PktInfo.AsRx.HTCRxFlags = 0; + pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead; + pPacket->ActualLength = A_LE2CPU16(pHdr->PayloadLen) + HTC_HDR_LENGTH; + + if (pPacket->ActualLength > pPacket->BufferLength) { + status = A_EPROTO; + break; + } + + /* we want synchronous operation */ + pPacket->Completion = NULL; + + /* get the message from the device, this will block */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + /* process receive header */ + status = HTCProcessRecvHeader(target,pPacket,NULL,NULL); + + pPacket->Status = status; + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCWaitforMessage, HTCProcessRecvHeader failed (status = %d) \n", + status)); + break; + } + + /* give the caller this control message packet, they are responsible to free */ + *ppControlPacket = pPacket; + + } while (false); + + if (A_FAILED(status)) { + if (pPacket != NULL && *ppControlPacket == NULL) { + /* cleanup buffer on error */ + HTC_FREE_CONTROL_RX(target,pPacket); + } + } + + return status; +} + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hw_interface/hw_api.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hw_interface/hw_api.c new file mode 100644 index 00000000000..0298a6bf9b6 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/hw_interface/hw_api.c @@ -0,0 +1,151 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +A_STATUS HW_ProcessPendingInterrupts(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + uint8_t cpuIntrCause; + + pDCxt->driver_state = DRIVER_STATE_PENDING_CONDITION_A; + + /* identify the interrupt and mask it */ + if (pDCxt->spi_hcd.IrqDetected == true) + { + pDCxt->driver_state = DRIVER_STATE_INTERRUPT_PROCESSING; + pDCxt->spi_hcd.IrqDetected = false; + + if (false == Hcd_BusInterrupt(pCxt)) + { + /* FIXME: HANDLE ERROR CONDITION */ + } + } + + pDCxt->driver_state = DRIVER_STATE_PENDING_CONDITION_B; + /* check to see if a deferred bus request has completed. if so + * process it. */ + if (pDCxt->booleans & SDHD_BOOL_DMA_COMPLETE) + { + /* get the request */ + if (A_OK == Driver_CompleteRequest(pCxt, pDCxt->spi_hcd.pCurrentRequest)) + { + /* clear the pending request and the boolean */ + pDCxt->spi_hcd.pCurrentRequest = NULL; + pDCxt->booleans &= ~SDHD_BOOL_DMA_COMPLETE; + } + } + + if (pDCxt->spi_hcd.CpuInterrupt) + { + cpuIntrCause = 0x0; + if (Hcd_ReadCPUInterrupt(pCxt, &cpuIntrCause)) + { + pDCxt->spi_hcd.CpuInterruptCause = cpuIntrCause; + } + pDCxt->driver_state = DRIVER_STATE_INTERRUPT_PROCESSING; + Hcd_ClearCPUInterrupt(pCxt); + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_INTR_LOCAL_CPU_INTR); + HTC_ProcessCpuInterrupt(pCxt); + pDCxt->spi_hcd.CpuInterrupt = 0; + } + + pDCxt->driver_state = DRIVER_STATE_PENDING_CONDITION_C; + return A_OK; +} + +void HW_PowerUpDown(void *pCxt, uint8_t powerUp) +{ +#if WLAN_CONFIG_ENABLE_CHIP_PWD_GPIO + /* NOTE: when powering down it is necessary that the SPI MOSI on the MCU + * be configured high so that current does not leak from the AR6003. + * Hence because the SPI interface retains its last state we write a single + * 0xf out the SPI bus prior to powering the chip down. + */ + if (powerUp == 0) + { + Bus_InOutToken(pCxt, (uint32_t)0xff, 1, NULL); + } + + HW_USEC_DELAY(pCxt, 1000); + CUSTOM_HW_POWER_UP_DOWN(pCxt, powerUp); + + if (powerUp) + { + if (ath_custom_init.Custom_reset_measure_timer != NULL) + { + ath_custom_init.Custom_reset_measure_timer(); + } + + // delay to give chip time to come alive + HW_USEC_DELAY(pCxt, 2000); + } +#endif +} + +void HW_InterruptHandler(void *pCxt) +{ + if (pCxt) + { + GET_DRIVER_COMMON(pCxt)->spi_hcd.IrqDetected = true; + + /* disable IRQ while we process it */ + HW_EnableDisableIRQ(pCxt, false, true); + /* startup work item to process IRQs */ + DRIVER_WAKE_DRIVER(pCxt); + } +} + +void HW_SetClock(void *pCxt, uint32_t *pClockRate) +{ + UNUSED_ARGUMENT(pCxt); + UNUSED_ARGUMENT(pClockRate); +} + +uint32_t HW_GetMboxAddress(void *pCxt, uint16_t mbox, uint32_t length) +{ + uint32_t address = 0; + + if (mbox == 0) + { + address = GET_DRIVER_COMMON(pCxt)->mboxAddress + HIF_MBOX_WIDTH - length; + } + else + { + A_ASSERT(0); + } + + return address; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_debug.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_debug.h new file mode 100644 index 00000000000..61f6bfc9157 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_debug.h @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DEBUG_H_ +#define _A_DEBUG_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define A_REGISTER_MODULE_DEBUG_INFO(mod) +#define AR_DEBUG_PRINTF(mask, args) +//#define AR_DEBUG_PRINTF(mask, args) do { if(1) PRINTF args ; } while(0) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_drv.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_drv.h new file mode 100644 index 00000000000..96942438148 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_drv.h @@ -0,0 +1,29 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_H_ +#define _A_DRV_H_ + +#endif /* _ADRV_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_drv_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_drv_api.h new file mode 100644 index 00000000000..158f6b94c49 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/a_drv_api.h @@ -0,0 +1,264 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_API_H_ +#define _A_DRV_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** WMI related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ +void Api_ChannelListEvent(void *pCxt, uint8_t devId, int8_t numChan, void *chanList); +void Api_TargetStatsEvent(void *pCxt, uint8_t devId, uint8_t *ptr, uint32_t len); +void Api_ScanCompleteEvent(void *pCxt, uint8_t devId, A_STATUS status); +void Api_RegDomainEvent(void *pCxt, uint8_t devId, uint32_t regCode); +void Api_DisconnectEvent(void *pCxt, + uint8_t devId, + uint8_t reason, + uint8_t *bssid, + uint8_t assocRespLen, + uint8_t *assocInfo, + uint16_t protocolReasonStatus); +void Api_ConnectEvent(void *pCxt, + uint8_t devId, + uint16_t channel, + uint8_t *bssid, + uint16_t listenInterval, + uint16_t beaconInterval, + NETWORK_TYPE networkType, + uint8_t beaconIeLen, + uint8_t assocReqLen, + uint8_t assocRespLen, + uint8_t *assocInfo); +void Api_BitrateEvent(void *pCxt, uint8_t devId, int32_t rateKbps); +void Api_ReadyEvent(void *pCxt, uint8_t devId, uint8_t *datap, uint8_t phyCap, uint32_t sw_ver, uint32_t abi_ver); +void Api_BssInfoEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len); +void Api_TkipMicErrorEvent(void *pCxt, uint8_t devId, uint8_t keyid, boolean ismcast); +void Api_GetPmkEvent(void *pCxt, uint8_t devId, uint8_t *datap); +void Api_RxDbglogEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len); +void Api_RxGpioDataEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len); +void Api_RxHBChallengeEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len); +void Api_RxPfmDataEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len); +void Api_RxPfmDataDoneEvent(void *wmip, uint8_t devId, uint8_t *datap, int32_t len); + +void Api_StoreRecallEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_StoreRecallStartEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_HostDsetStoreEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_HostDsetReadEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_HostDsetCreateEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_HostDsetWriteEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_HostDsetReadbackEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_HostDsetSyncEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_DsetOPEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); + +void Api_WpsProfileEvent(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); +void Api_AggrRecvAddbaReqEvent(void *pCxt, uint8_t devId, WMI_ADDBA_REQ_EVENT *evt); +void Api_AggrRecvDelbaReqEvent(void *pCxt, uint8_t devId, WMI_DELBA_EVENT *evt); +A_STATUS +Api_WmiTxStart(void *pCxt, void *pReq, HTC_ENDPOINT_ID eid); +void Api_RSNASuccessEvent(void *pCxt, uint8_t devId, uint8_t code); +void Api_GetBitRateEvent(void *pCxt, uint8_t devId, void *datap); +A_STATUS +Api_SockResponseEventRx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len, void *pReq); +void Api_ProbeReqEvent(void *pCxt, uint8_t *datap, uint32_t len); + +#if MANUFACTURING_SUPPORT +void Api_TestCmdEventRx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); +#endif +void Api_GetTemperatureReply(void *pCxt, uint8_t *datap, uint32_t len); +void Api_GetCountryCodeReply(void *pCxt, uint8_t *datap, uint32_t len); +void Api_GetSetParamReply(void *pCxt, uint8_t *datap); +void Api_GetWpsInitReply(void *pCxt, uint8_t *datap, uint32_t len); +#if ENABLE_P2P_MODE +void p2p_go_neg_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len, WMI_P2P_PROV_INFO *wps_info); + +void p2p_invite_sent_result_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void p2p_node_list_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void p2p_list_persistent_network_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void p2p_req_auth_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void get_p2p_ctx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void get_p2p_prov_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void get_p2p_serv_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void p2p_invite_req_rx(void *pCxt, uint8_t devId, uint8_t *datap, uint8_t len); + +void p2p_invite_rcvd_result_ev(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +#define A_WMI_P2P_GO_NEG_EVENT(devt, devId, res, len, wps_info) \ + p2p_go_neg_event((devt), (devId), (res), (len), (wps_info)) + +#define A_WMI_P2P_NODE_LIST_EVENT(devt, devId, res, len) p2p_node_list_event((devt), (devId), (res), (len)) + +#define A_WMI_P2P_PERSISTENT_LIST_NETWORK_EVENT(devt, devId, res, len) \ + p2p_list_persistent_network_event((devt), (devId), (res), (len)) + +#define A_WMI_P2P_REQ_AUTH_EVENT(devt, devId, res, len) p2p_req_auth_event((devt), (devId), (res), (len)) + +#define A_WMI_GET_P2P_CTX(devt, devId, res, len) get_p2p_ctx((devt), (devId), (res), (len)) + +#define A_WMI_P2P_PROV_DISC_REQ(devt, devId, res, len) get_p2p_prov_disc_req((devt), (devId), (res), (len)) +#if 1 // KK +#define A_WMI_P2P_SERV_DISC_REQ(devt, devId, res, len) get_p2p_serv_disc_req((devt), (devId), (res), (len)) + +#define A_WMI_P2P_INVITE_REQ_RX(devt, devId, datap, len) p2p_invite_req_rx((devt), (devId), (datap), (len)) + +#define A_WMI_P2P_INVITE_RCVD_RESULT_EVENT(devt, devId, datap, len) \ + p2p_invite_rcvd_result_ev((devt), (devId), (datap), (len)) + +#define A_WMI_P2P_INVITE_SENT_RESULT_EVENT(devt, devId, res, len) \ + p2p_invite_sent_result_event((devt), (devId), (res), (len)) +#endif +#endif + +#define A_WMI_CHANNELLIST_RX(devt, devId, numChan, chanList) \ + Api_ChannelListEvent((devt), (devId), (numChan), (chanList)) + +#define A_WMI_SET_NUMDATAENDPTS(devt, num) + +#define A_WMI_CONTROL_TX(devt, osbuf, streamID) Api_WmiTxStart((devt), (osbuf), (streamID)) + +#define A_WMI_TARGETSTATS_EVENT(devt, devId, pStats, len) Api_TargetStatsEvent((devt), (devId), (pStats), (len)) + +#define A_WMI_SCANCOMPLETE_EVENT(devt, devId, status) Api_ScanCompleteEvent((devt), (devId), (status)) + +#define A_WMI_CONNECT_EVENT(devt, devId, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, \ + assocReqLen, assocRespLen, assocInfo) \ + Api_ConnectEvent((devt), (devId), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), \ + (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo)) + +#define A_WMI_REGDOMAIN_EVENT(devt, devId, regCode) Api_RegDomainEvent((devt), (devId), (regCode)) + +#define A_WMI_DISCONNECT_EVENT(devt, devId, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \ + Api_DisconnectEvent((devt), (devId), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus)) + +#define A_WMI_RSNA_SUCCESS_EVENT(devt, devId, code) Api_RSNASuccessEvent((devt), (devId), (code)) + +#define A_WMI_BITRATE_RX(devt, devId, rateKbps) Api_BitrateEvent((devt), (devId), (rateKbps)) + +/* A_WMI_TXPWR_RX - not currently supported */ +#define A_WMI_TXPWR_RX(devt, devId, txPwr) + +#define A_WMI_READY_EVENT(devt, devId, datap, phyCap, sw_ver, abi_ver) \ + Api_ReadyEvent((devt), (devId), (datap), (phyCap), (sw_ver), (abi_ver)) + +#define A_WMI_GET_BITRATE_EVEVT(devt, devId, datap) Api_GetBitRateEvent((devt), (devId), (datap)) + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) +#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) + +#define A_WMI_BSSINFO_EVENT_RX(ar, devId, datap, len) Api_BssInfoEvent((ar), (devId), (datap), (len)) + +#define A_WMI_TKIP_MICERR_EVENT(devt, devId, keyid, ismcast) Api_TkipMicErrorEvent((devt), (devId), (keyid), (ismcast)) + +#define A_WMI_Ac2EndpointID(devht, devId, ac) Driver_AC2EndpointID((devht), (devId), (ac)) + +#define A_WMI_Endpoint2Ac(devt, devId, ep) Driver_EndpointID2AC((devt), (devId), (ep)) + +#define A_WMI_GET_PMK_RX(devt, devId, datap) Api_GetPmkEvent((devt), (devId), (datap)) + +#define A_WMIX_DBGLOG_EVENT(wmip, devId, datap, len) Api_RxDbglogEvent((wmip), (devId), (datap), (len)) + +#define A_WMIX_GPIO_DATA_EVENT(wmip, devId, datap, len) Api_RxGpioDataEvent((wmip), (devId), (datap), (len)) + +#define WMIX_HB_CHALLENGE_RESP_RX(wmip, devId, datap, len) Api_RxHBChallengeEvent((wmip), (devId), (datap), (len)) + +#define A_WMIX_PFM_DATA_EVENT(wmip, devId, datap, len) Api_RxPfmDataEvent((wmip), (devId), (datap), (len)) + +#define A_WMIX_PFM_DATA_DONE_EVENT(wmip, devId, datap, len) Api_RxPfmDataDoneEvent((wmip), (devId), (datap), (len)) + +#if DRIVER_CONFIG_ENABLE_STORE_RECALL +#define A_WMI_STORERECALL_EVENT_RX(devt, devId, datap, len, osbuf) \ + Api_StoreRecallEvent((devt), (devId), (datap), (len), (osbuf)) +#else +#define A_WMI_STORERECALL_EVENT_RX(devt, devId, datap, len, osbuf) A_OK +#endif + +#define A_WMI_STORERECALL_START_EVENT_RX(devt, devId, datap, len, osbuf) \ + Api_StoreRecallStartEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_PROBE_REQ_EVENT_RX(devt, datap, len) Api_ProbeReqEvent((devt), (datap), (len)) + +#define A_WMI_HOST_DSET_EVENT_STORE_RX(devt, devId, datap, len, osbuf) \ + Api_HostDsetStoreEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_HOST_DSET_EVENT_READ_RX(devt, devId, datap, len, osbuf) \ + Api_HostDsetReadEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_HOST_DSET_EVENT_CREATE_RX(devt, devId, datap, len, osbuf) \ + Api_HostDsetCreateEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_HOST_DSET_EVENT_WRITE_RX(devt, devId, datap, len, osbuf) \ + Api_HostDsetWriteEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_HOST_DSET_EVENT_READBACK_RX(devt, devId, datap, len, osbuf) \ + Api_HostDsetReadbackEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_HOST_DSET_EVENT_SYNC_RX(devt, devId, datap, len, osbuf) \ + Api_HostDsetSyncEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_DSET_EVENT_OP_RX(devt, devId, datap, len, osbuf) Api_DsetOPEvent((devt), (devId), (datap), (len), (osbuf)) + +#define A_WMI_WPS_PROFILE_EVENT_RX(devt, devId, datap, len, osbuf) \ + Api_WpsProfileEvent((devt), (devId), (datap), (len), (osbuf)) + +#if WLAN_CONFIG_11N_AGGR_SUPPORT +#define A_WMI_AGGR_RECV_ADDBA_REQ_EVT(devt, devId, cmd) Api_AggrRecvAddbaReqEvent((devt), (devId), (cmd)) + +#define A_WMI_AGGR_RECV_DELBA_REQ_EVT(devt, devId, cmd) Api_AggrRecvDelbaReqEvent((devt), (devId), (cmd)) +#endif + +#define A_WMI_GET_TEMPERATURE_REPLY(devt, datap, len) Api_GetTemperatureReply((devt), (datap), (len)) + +#define A_WMI_GET_COUNTRY_CODE_REPLY(devt, datap, len) Api_GetCountryCodeReply((devt), (datap), (len)) +#define A_WMI_SET_PARAM_REPLY(devt, datap) Api_GetSetParamReply((devt), (datap)) +#define A_WMI_WLAN_WPS_INIT_REPLY_RX(devt, datap, len) Api_GetWpsInitReply((devt), (datap), (len)) + +#if ENABLE_STACK_OFFLOAD +#define A_WMI_SOCK_RESPONSE_EVENT_RX(devt, devId, datap, len, osbuf) \ + Api_SockResponseEventRx((devt), (devId), (datap), (len), (osbuf)) +#else +#define A_WMI_SOCK_RESPONSE_EVENT_RX(devt, devId, datap, len, osbuf) A_OK +#endif +#if MANUFACTURING_SUPPORT +#define A_WMI_TEST_CMD_EVENT_RX(devt, devId, datap, len) Api_TestCmdEventRx((devt), (devId), (datap), (len)) +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/aggr_recv_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/aggr_recv_api.h new file mode 100644 index 00000000000..7adc10cca2c --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/aggr_recv_api.h @@ -0,0 +1,108 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __AGGR_RECV_API_H__ +#define __AGGR_RECV_API_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*RX_CALLBACK)(void *dev, void *osbuf); + +typedef void (*ALLOC_NETBUFS)(A_NETBUF_QUEUE_T *q, uint16_t num); + +/* + * aggr_init: + * Initialises the data structures, allocates data queues and + * os buffers. Netbuf allocator is the input param, used by the + * aggr module for allocation of NETBUFs from driver context. + * These NETBUFs are used for AMSDU processing. + * Returns the context for the aggr module. + */ +void *aggr_init(void); + +/* + * aggr_deinit: + * Frees any allocated resources allocated by aggr_init. + */ +void aggr_deinit(void *cntxt); + +/* + * aggr_recv_addba_req_evt: + * This event is to initiate/modify the receive side window. + * Target will send WMI_ADDBA_REQ_EVENTID event to host - to setup + * recv re-ordering queues. Target will negotiate ADDBA with peer, + * and indicate via this event after succesfully completing the + * negotiation. This happens in two situations: + * 1. Initial setup of aggregation + * 2. Renegotiation of current recv window. + * Window size for re-ordering is limited by target buffer + * space, which is reflected in win_sz. + * (Re)Start the periodic timer to deliver long standing frames, + * in hold_q to OS. + */ +void aggr_recv_addba_req_evt(void *cntxt, uint8_t tid, uint16_t seq_no, uint8_t win_sz); + +/* + * aggr_recv_delba_req_evt: + * Target indicates deletion of a BA window for a tid via the + * WMI_DELBA_EVENTID. Host would deliver all the frames in the + * hold_q, reset tid config and disable the periodic timer, if + * aggr is not enabled on any tid. + */ +void aggr_recv_delba_req_evt(void *cntxt, uint8_t tid); + +/* + * aggr_process_recv_frm: + * Called only for data frames. When aggr is ON for a tid, the buffer + * is always consumed, and osbuf would be NULL. For a non-aggr case, + * osbuf is not modified. + * AMSDU frames are consumed and are later freed. They are sliced and + * diced to individual frames and dispatched to stack. + * After consuming a osbuf(when aggr is ON), a previously registered + * callback may be called to deliver frames in order. + */ +boolean aggr_process_recv_frm(void *cntxt, uint8_t tid, uint16_t seq_no, boolean is_amsdu, void **osbuf); + +/* + * aggr_module_destroy: + * Frees up all the queues and frames in them. Releases the cntxt to OS. + */ +void aggr_module_destroy(void *cntxt); + +/* + * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate + * hold Q state. Examples include when a Connect event or disconnect event is + * received. + */ +void aggr_reset_state(void *cntxt); + +#ifdef __cplusplus +} +#endif + +#endif /*__AGGR_RECV_API_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/bmi.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/bmi.h new file mode 100644 index 00000000000..f63801bcd27 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/bmi.h @@ -0,0 +1,77 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _BMI_H_ +#define _BMI_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +//#include "hif.h" +#include "a_osapi.h" +#include "bmi_msg.h" + +A_STATUS +BMIInit(void *pCxt); + +void BMICleanup(void); + +A_STATUS +BMIDone(void *pCxt); + +A_STATUS +BMIGetTargetInfo(void *pCxt, struct bmi_target_info *targ_info); + +A_STATUS +BMIReadMemory(void *pCxt, uint32_t address, uint8_t *buffer, uint32_t length); + +A_STATUS +BMIWriteMemory(void *pCxt, uint32_t address, uint8_t *buffer, uint32_t length); + +A_STATUS +BMIExecute(void *pCxt, uint32_t address, uint32_t *param); + +A_STATUS +BMIReadSOCRegister(void *pCxt, uint32_t address, uint32_t *param); + +A_STATUS +BMIWriteSOCRegister(void *pCxt, uint32_t address, uint32_t param); + +A_STATUS +BMIRawWrite(void *pCxt, uint8_t *buffer, uint32_t length); + +A_STATUS +BMIRawRead(void *pCxt, uint8_t *buffer, uint32_t length, boolean want_timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* _BMI_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/common_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/common_api.h new file mode 100644 index 00000000000..0d2f09ca54a --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/common_api.h @@ -0,0 +1,311 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _COMMON_API_H_ +#define _COMMON_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +// IGX_UD_CHANGES +typedef struct hcd_intr_callback_t +{ + void *pCxt; +} HCD_INTR_CB, *HCD_INTR_CALLBACK_T; + +A_STATUS Driver_CreateThread(void *pCxt); + +A_STATUS Driver_DestroyThread(void *pCxt); + +void HW_EnableDisableIRQ(void *pCxt, boolean Enable, boolean FromIrq); + +A_STATUS HW_ProcessPendingInterrupts(void *pCxt); + +A_STATUS wmi_dset_host_cfg_cmd(void *handle); + +A_STATUS Driver_Init(void *pCxt); + +A_STATUS Driver_DeInit(void *pCxt); + +A_STATUS Driver_ContextInit(void *pCxt); + +A_STATUS Driver_ContextDeInit(void *pCxt); + +uint32_t Htc_ReadCreditCounter(void *pCxt, uint32_t index); + +void Htc_GetCreditCounterUpdate(void *pCxt, uint16_t epid); + +void Htc_PrepareRecvPacket(void *pCxt, void *pReq); + +A_STATUS Htc_SendPacket(void *pCxt, void *pReq); + +void Htc_RxComplete(void *pCxt, void *pReq); + +A_STATUS Htc_ProcessTxComplete(void *pCxt, void *pReq); + +A_STATUS Htc_ProcessRecvHeader(void *pCxt, void *pReq, uint32_t *pNextLookAheads, uint32_t *pNumLookAheads); + +A_STATUS HTC_Start(void *pCxt); + +A_STATUS HTC_WaitTarget(void *pCxt); + +A_STATUS HTC_ConnectService(void *pCxt, HTC_SERVICE_CONNECT_REQ *pConnectReq, HTC_SERVICE_CONNECT_RESP *pConnectResp); + +void HTC_ProcessCpuInterrupt(void *pCxt); + +void Hcd_Irq(void *pCxt); + +A_STATUS Driver_Main(void *pCxt, uint8_t scope, boolean *pCanBlock, uint16_t *pBlock_msec); + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) +void Driver_ReportRxBuffStatus(void *pCxt, boolean status, uint8_t epid); +#else +void Driver_ReportRxBuffStatus(void *pCxt, boolean status); +#endif + +A_STATUS Driver_CompleteRequest(void *pCxt, void *pReq); + +boolean Driver_TxReady(void *pCxt); + +A_STATUS Driver_SubmitTxRequest(void *pCxt, void *pReq); + +A_STATUS Driver_SubmitEp0TxRequest(void *pCxt, void *pReq); + +boolean Driver_RxReady(void *pCxt); + +void Driver_DropTxDataPackets(void *pCxt); + +A_STATUS Driver_SendPacket(void *pCxt, void *pReq); + +A_STATUS Driver_RecvPacket(void *pCxt, void *pReq); + +A_STATUS Driver_GetTargetInfo(void *pCxt); + +A_STATUS Driver_BootComm(void *pCxt); + +void Driver_RxComplete(void *pCxt, void *pReq); + +A_STATUS Driver_ReadRegDiag(void *pCxt, uint32_t *address, uint32_t *data); + +A_STATUS Driver_WriteRegDiag(void *pCxt, uint32_t *address, uint32_t *data); + +A_STATUS Driver_ReadDataDiag(void *pCxt, uint32_t address, uint8_t *data, uint32_t length); + +A_STATUS Driver_WriteDataDiag(void *pCxt, uint32_t address, uint8_t *data, uint32_t length); + +A_STATUS Driver_DumpAssertInfo(void *pCxt, uint32_t *pData, uint16_t *pLength); + +A_STATUS Driver_StoreRecallFirmwareDownload(void *pCxt); + +void HW_EnableDisableSPIIRQ(void *pCxt, boolean Enable, boolean FromIrq); + +void HW_PowerUpDown(void *pCxt, uint8_t powerUp); + +A_STATUS Bus_InOutToken(void *pCxt, uint32_t OutToken, uint8_t DataSize, uint32_t *pInToken); + +void Bus_TransferComplete(void *pCxt, A_STATUS status); + +void HW_InterruptHandler(void *pCxt); + +void Strrcl_Recall(void *pCxt, uint32_t msec_sleep); + +A_STATUS Hcd_ProgramWriteBufferWaterMark(void *pCxt, uint32_t length); + +void Hcd_RefreshWriteBufferSpace(void *pCxt); + +// Todo +A_STATUS Hcd_DoPioInternalAccess(void *pCxt, uint16_t addr, uint32_t *pValue, boolean isRead); + +/**********TBD**********/ +uint16_t Api_TxGetStatus(void *pCxt); + +void Api_TxComplete(void *pCxt, void *pReq); + +void Api_RxComplete(void *pCxt, void *pReq); + +A_STATUS Api_WmiTxStart(void *pCxt, void *pReq, HTC_ENDPOINT_ID eid); + +A_STATUS Api_DataTxStart(void *pCxt, void *pReq); + +void Api_BootProfile(void *pCxt, uint8_t val); + +A_STATUS Api_InitStart(void *pCxt); + +A_STATUS Api_InitFinish(void *pCxt); + +void Api_WMIInitFinish(void *pCxt); + +A_STATUS Api_DeInitStart(void *pCxt); + +A_STATUS Api_DeInitFinish(void *pCxt); + +A_STATUS Api_DisconnectWiFi(void *pCxt); + +A_STATUS Api_ConnectWiFi(void *pCxt); + +A_STATUS Api_ParseInfoElem(void *pCxt, WMI_BSS_INFO_HDR *bih, int32_t len, A_SCAN_SUMMARY *pSummary); + +A_STATUS Api_DriverAccessCheck(void *pCxt, uint8_t block_allowed, uint8_t request_reason); + +A_STATUS Api_ProgramCountryCode(void *pCxt, uint8_t *country_code, uint16_t length, uint8_t *pResult); + +A_STATUS Api_ProgramMacAddress(void *pCxt, uint8_t *addr, uint16_t length, uint8_t *pResult); + +A_STATUS Api_SetPowerMode(void *pCxt, POWER_MODE *pwrmode); + +uint32_t HW_GetMboxAddress(void *pCxt, uint16_t mbox, uint32_t length); + +A_ENDPOINT_T *Util_GetEndpoint(void *pCxt, uint16_t id); + +uint16_t Util_Ieee2freq(int32_t chan); + +uint32_t Util_Freq2ieee(uint16_t freq); + +HTC_ENDPOINT_ID Util_AC2EndpointID(void *pCxt, uint8_t ac); + +uint8_t Util_EndpointID2AC(void *pCxt, HTC_ENDPOINT_ID ep); + +uint8_t Util_Ascii2Hex(char val); + +A_STATUS scan_setup(void *pCxt, void *pWmi, WMI_START_SCAN_CMD *start_scan); + +A_STATUS wait_scan_done(void *pCxt, void *pWmi); + +A_STATUS move_power_state_to_maxperf(void *pCxt, int32_t module); + +A_STATUS TxRawPacket(void *pCxt, void *pReq, ATH_MAC_TX_PARAMS *pParams); + +#if MANUFACTURING_SUPPORT +void Api_Test_Cmd_Event(void *pCxt, uint8_t *datap, uint32_t len); +#endif + +#if MANUFACTURING_SUPPORT +#define API_TEST_RESP_EVENT(pCxt, datap, len) Api_Test_Cmd_Event((pCxt), (datap), (len)) +#endif + +void Driver_WakeDriver(void *pCxt); + +void Driver_WakeUser(void *pCxt); + + +#define DRIVER_WAKE_DRIVER(pCxt) Driver_WakeDriver((pCxt)) +#define DRIVER_WAKE_USER(pCxt) Driver_WakeUser((pCxt)) + +#if ENABLE_STACK_OFFLOAD + +#define SOCKET_CONTEXT_INIT socket_context_init() +#define STACK_INIT(pCxt) send_stack_init((pCxt)) +#define SOCKET_CONTEXT_DEINIT() socket_context_deinit() +#define MIN_HDR_LEN sizeof(WMI_DATA_HDR) +#define WMI_DOT3_2_DIX(pReq) A_OK + +#else + +#define STACK_INIT(pCxt) A_OK +#define SOCKET_CONTEXT_INIT A_OK +#define SOCKET_CONTEXT_DEINIT() A_OK +#define MIN_HDR_LEN sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR) +#define WMI_DOT3_2_DIX(pReq) wmi_dot3_2_dix((pReq)) + +#endif + +enum BOOT_PROFILE +{ + BOOT_PROFILE_WMI_READY = 0, + BOOT_PROFILE_READ_REFCLK, + BOOT_PROFILE_DONE_CONFIG, + BOOT_PROFILE_START_CONNECT, + BOOT_PROFILE_DONE_CONNECT, + BOOT_PROFILE_DRIVE_READY, + BOOT_PROFILE_START_SCAN, + BOOT_PROFILE_DONE_SCAN, + BOOT_PROFILE_POWER_UP, + BOOT_PROFILE_BOOT_PARAMETER, +}; + +#if ENABLE_P2P_MODE + +#define API_P2P_GO_NEG_EVENT(devt, devId, res, len, wps_info) \ + Api_p2p_go_neg_event((devt), (devId), (res), (len), (wps_info)) + +#define API_P2P_INVITE_SEND_RESULT(pCxt, devId, datap, len) Api_p2p_invite_send_result((pCxt), (devId), (datap), (len)) + +#define API_P2P_NODE_LIST_EVENT(devt, devId, res, len) Api_p2p_node_list_event((devt), (devId), (res), (len)) + +#define API_P2P_LIST_PERSISTENT_NETWORK_EVENT(devt, devId, res, len) \ + Api_p2p_list_persistent_network_event((devt), (devId), (res), (len)) + +#define API_GET_P2P_CTX(devt, devId, res, len) Api_get_p2p_ctx((devt), (devId), (res), (len)) + +#define API_P2P_PROV_DISC_REQ(devt, devId, res, len) Api_p2p_prov_disc_req((devt), (devId), (res), (len)) + +#define API_P2P_SERV_DISC_REQ(devt, devId, res, len) Api_p2p_serv_disc_req((devt), (devId), (res), (len)) + +#define API_P2P_INVITE_REQ(pCxt, devId, datap, len) Api_p2p_invite_req((pCxt), (devId), (datap), (len)) + +#define API_P2P_INVITE_RCVD_RESULT(pCxt, devId, datap, len) Api_p2p_invite_rcvd_result((pCxt), (devId), (datap), (len)) + +#define API_P2P_REQ_AUTH_EVENT(devt, devId, res, len) Api_p2p_req_auth_event((devt), (devId), (res), (len)) + +void Api_p2p_go_neg_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len, WMI_P2P_PROV_INFO *wps_info); + +void Api_p2p_invite_send_result(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_p2p_node_list_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_p2p_list_persistent_network_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_get_p2p_ctx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_p2p_prov_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_p2p_serv_disc_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_p2p_invite_req(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_p2p_req_auth_event(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); + +void Api_p2p_invite_rcvd_result(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len); +#endif // ENABLE_P2P_MODE + +#if MANUFACTURING_SUPPORT +#define API_TEST_RESP_EVENT(pCxt, datap, len) Api_Test_Cmd_Event((pCxt), (datap), (len)) + +void Api_Test_Cmd_Event(void *pCxt, uint8_t *datap, uint32_t len); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _COMMON_API_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dbglog_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dbglog_api.h new file mode 100644 index 00000000000..edb92dc41bf --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dbglog_api.h @@ -0,0 +1,49 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DBGLOG_API_H_ +#define _DBGLOG_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif +#if 0 +#include "dbglog.h" + +#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE + +#define DBGLOG_GET_DBGID(arg) ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) + +#define DBGLOG_GET_MODULEID(arg) ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) + +#define DBGLOG_GET_NUMARGS(arg) ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) + +#define DBGLOG_GET_TIMESTAMP(arg) ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_API_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/driver_cxt.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/driver_cxt.h new file mode 100644 index 00000000000..74d0efe65a4 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/driver_cxt.h @@ -0,0 +1,372 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DRIVER_CXT_H_ +#define _DRIVER_CXT_H_ + +#include "a_types.h" +#include +#include +#include +#include "ieee80211.h" +#include "atheros_wifi.h" +#include "mbed_rtos_storage.h" + +#define MIN_STRRCL_MSEC (100) + +#define AR4100_DEFAULT_CREDIT_COUNT 6 + +#define AR4100_BUFFER_SIZE 1664 + +#define AR4100_MAX_AMSDU_RX_BUFFERS 4 +#define AR4100_AMSDU_REFILL_THRESHOLD 3 + +#define AR4100_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) + +#if WLAN_CONFIG_AMSDU_ON_HOST +#define AR4100_MAX_RX_MESSAGE_SIZE (max(WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH, WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH)) +/* The RX MESSAGE SIZE is ultimately dictated by the size of the firmware buffers used to + * hold packets. This is because any remaining space may be used by HTC for trailers. hence + * a full size buffer must be anticipated by the host. */ +#else +#define AR4100_MAX_RX_MESSAGE_SIZE (AR4100_BUFFER_SIZE) +#endif + +#define MAX_NUM_CHANLIST_CHANNELS (16) + +#define MAX_WEP_KEY_SZ (16) + +#define STRRCL_ST_DISABLED 0 +#define STRRCL_ST_INIT 1 +#define STRRCL_ST_START 2 +#define STRRCL_ST_ACTIVE 3 +#define STRRCL_ST_ACTIVE_B 4 +#define STRRCL_ST_AWAIT_FW 5 + +#define AES_KEY_SIZE_BYTES 16 + +#define ACCESS_REQUEST_IOCTL 0 +#define ACCESS_REQUEST_TX 1 +#define ACCESS_REQUEST_RX 2 + +#define DRIVER_SCOPE_RX 0x01 +#define DRIVER_SCOPE_TX 0x02 + +#define DRIVER_STATE_IDLE 0x00 /* the driver task is idle/sleeping */ +#define DRIVER_STATE_RX_PROCESSING 0x01 /* the driver task is processing a RX request */ +#define DRIVER_STATE_TX_PROCESSING 0x02 /* the driver task is processing a TX request */ +#define DRIVER_STATE_INTERRUPT_PROCESSING 0x03 /* the driver task is processing a chip Interrupt */ +#define DRIVER_STATE_ASYNC_PROCESSING 0x04 /* the driver task is processing an asynch operation */ +#define DRIVER_STATE_PENDING_CONDITION_A 0x05 /* the driver task is waiting for a condition to be met */ +#define DRIVER_STATE_PENDING_CONDITION_B 0x06 +#define DRIVER_STATE_PENDING_CONDITION_C 0x07 +#define DRIVER_STATE_PENDING_CONDITION_D 0x08 +#define DRIVER_STATE_PENDING_CONDITION_E 0x09 +#define DRIVER_STATE_PENDING_CONDITION_F 0x0a +#define DRIVER_STATE_PENDING_CONDITION_G 0x0b + +#define MAX_CREDIT_DEADLOCK_ATTEMPTS 2 +#define DEADLOCK_BLOCK_MSEC 10 + +typedef struct ar_wep_key +{ + uint8_t keyLen; + uint8_t key[MAX_WEP_KEY_SZ]; +} A_WEPKEY_T; + +/* A_SCAN_SUMMARY provides useful information that + * has been parsed from bss info headers and probe/beacon information elements. + */ +typedef struct scan_summary +{ + uint16_t beacon_period; + uint16_t caps; + uint8_t bssid[6]; + uint8_t ssid[32]; + uint8_t channel; + uint8_t ssid_len; + uint8_t rssi; + uint8_t bss_type; + uint8_t rsn_cipher; + uint8_t rsn_auth; + uint8_t wpa_cipher; + uint8_t wpa_auth; + uint8_t wep_support; + uint8_t reserved; // keeps struct on 4-byte boundary +} A_SCAN_SUMMARY; + +typedef struct +{ + uint16_t maxMsgLength; + uint16_t serviceID; + uint32_t intCredits; + uint8_t intCreditCounter; + uint8_t rptCreditCounter; + uint8_t epIdx; + uint8_t credits; + uint8_t maxCredits; + uint8_t seqNo; +} A_ENDPOINT_T; + +#if USE_16BIT_CREDIT_COUNTER +typedef struct +{ + uint16_t maxMsgLength; + uint16_t serviceID; + uint32_t intCredits; + uint16_t intCreditCounter; + uint16_t rptCreditCounter; + uint8_t epIdx; + uint8_t rsvd; + uint16_t credits; + uint16_t maxCredits; + uint8_t seqNo; +} A_ENDPOINT_T; +#endif + +typedef A_STATUS (*TEMP_FUNC_T)(void *pCxt); + +typedef struct _a_connection_elements +{ + int32_t ssidLen; + uint8_t ssid[32]; + uint8_t networkType; /* one of NETWORK_TYPE enum */ + uint32_t connectCtrlFlags; + uint8_t dot11AuthMode; + uint8_t wpaAuthMode; + uint8_t wpaPairwiseCrypto; + uint8_t wpaPairwiseCryptoLen; + uint8_t wpaGroupCrypto; + uint8_t wpaGroupCryptoLen; + uint8_t wepDefTxKeyIndex; + A_WEPKEY_T wepKeyList[WMI_MAX_KEY_INDEX + 1]; + uint8_t wpaPmk[WMI_PMK_LEN]; + boolean wpaPmkValid; + uint8_t bssid[ATH_MAC_LEN]; + uint8_t reqBssid[ATH_MAC_LEN]; + uint16_t channelHint; + uint16_t bssChannel; + boolean isConnected; + boolean isConnectPending; + uint8_t phyMode; +} A_CONNECTION_ELEMENTS_T; + +typedef struct _a_spi_hcd_context +{ +#define SDHD_BOOL_SHUTDOWN 0x00000001 +#define SDHD_BOOL_EXTERNALIO_PENDING 0x00000002 +#define SDHD_BOOL_DMA_WRITE_WAIT_FOR_BUFFER 0x00000004 +#define SDHD_BOOL_DMA_IN_PROG 0x00000008 +#define SDHD_BOOL_TRANSFER_DIR_RX 0x00000010 +#define SDHD_BOOL_HOST_DMA_COPY_MODE 0x00000020 +#define SDHD_BOOL_HOST_ACCESS_COPY_MODE 0x00000040 +#define SDHD_BOOL_FATAL_ERROR 0x00000080 +#define SDHD_BOOL_DMA_COMPLETE 0x00000100 + +#define BYTE_SWAP true +#define NO_BYTE_SWAP false + + /******************************************* + * + * the following fields must be filled in by the hardware specific layer + * + ********************************************/ + // from SDHCD START HERE + uint8_t PendingIrqAcks; /* mask of pending interrupts that have not been ACK'd */ + uint8_t IrqsEnabled; + uint8_t IrqDetected; + // from SDHCD END HERE + uint8_t CpuInterrupt; + uint8_t CpuInterruptCause; + + uint16_t SpiIntEnableShadow; /* shadow copy of interrupt enables */ + uint16_t SpiConfigShadow; /* shadow copy of configuration register */ + uint16_t irqMask; + uint8_t HostAccessDataWidth; /* data width to use for host access */ + uint8_t DMADataWidth; /* data width to use for DMA access */ + uint32_t ReadBufferSpace; /* cached copy of read buffer available register */ + uint32_t WriteBufferSpace; /* cached copy of space remaining in the SPI write buffer */ + uint32_t MaxWriteBufferSpace; /* max write buffer space that the SPI interface supports */ + uint32_t PktsInSPIWriteBuffer; /* number of packets in SPI write buffer so far */ + void *pCurrentRequest; /* pointer to a request in-progress used only for deferred SPI ops. */ + + uint32_t OperationalClock; /* spi module operational clock */ + uint32_t PowerUpDelay; /* delay before the common layer should initialize over spi */ +/* SPI SPECIFICE ELEMENTS Starts here */ +#define HW_SPI_FRAME_WIDTH_8 0x01 +#define HW_SPI_FRAME_WIDTH_16 0x02 +#define HW_SPI_FRAME_WIDTH_24 0x04 +#define HW_SPI_FRAME_WIDTH_32 0x08 +#define HW_SPI_INT_EDGE_DETECT 0x80 +#define HW_SPI_NO_DMA 0x40 + uint8_t SpiHWCapabilitiesFlags; /* SPI hardware capabilities flags */ + +#define MISC_FLAG_SPI_SLEEP_WAR 0x04 +#define MISC_FLAG_RESET_SPI_IF_SHUTDOWN 0x02 +#define MISC_FLAG_DUMP_STATE_ON_SHUTDOWN 0x01 + uint8_t MiscFlags; + A_MUTEX_T lock; +} A_SPI_HCD_CXT; + +typedef struct _a_driver_context +{ + uint16_t driver_state; /* maintains current state of driver one of DRIVER_STATE_... */ + uint8_t txQueryResult; + boolean txQueryInProgress; + boolean driver_up; /* maintains driver status for external access */ + boolean chipDown; + boolean rxBufferStatus; /* maintains available status of rx buffers */ + boolean creditDeadlock; + uint32_t creditDeadlockCounter; + A_NETBUF_QUEUE_T txQueue; + void *pRxReq; + A_ENDPOINT_T ep[ENDPOINT_MANAGED_MAX]; + HTC_ENDPOINT_ID ac2EpMapping[WMM_NUM_AC]; + uint8_t ep2AcMapping[ENDPOINT_MAX]; + uint16_t creditCount; /* number of tx credits available at init */ + uint16_t creditSize; // size in bytes of a credit + /* the 5 version values maintained by the context */ + uint32_t targetType; /* general type value */ + uint32_t targetVersion; /* identifies the target chip */ + uint32_t wlanVersion; /* identifies firmware running on target chip */ + uint32_t abiVersion; /* identifies the interface compatible with wlan firmware */ + uint32_t hostVersion; /* identifies version of host driver */ + + uint8_t phyCapability; /* identifies chip phy capability */ + boolean wmiReady; + boolean wmiEnabled; + void *pWmiCxt; /* context for wmi driver component */ + void *pAggrCxt; /* context for rx aggregate driver component */ + uint16_t txAggrTidMask; + uint16_t rxAggrTidMask; + + int8_t numChannels; + uint16_t channelList[MAX_NUM_CHANLIST_CHANNELS]; + + uint32_t regCode; + int8_t rssi; + int32_t bitRate; + boolean wmmEnabled; + boolean tx_complete_pend; /* tracks new tx completes for task sync */ + TEMP_FUNC_T asynchRequest; + /* STORE&RECALL SPECIFICE ELEMENTS Starts here */ + void *strrclCxt; + int32_t strrclCxtLen; + boolean strrclBlock; + uint8_t strrclState; + /* STORE&RECALL SPECIFICE ELEMENTS Ends here */ + /* WPS SPECIFICE ELEMENTS Starts here */ + void *wpsBuf; + void *wpsEvent; + boolean wpsState; + /* WPS SPECIFIC ELEMENTS Ends here */ + uint8_t userPwrMode; + uint8_t tkipCountermeasures; + /* CONNECT SPECIFIC ELEMENTS Start Here */ + uint8_t devId; + A_CONNECTION_ELEMENTS_T conn[WLAN_NUM_OF_DEVICES]; + /* CONNECT SPECIFIC ELEMENTS End Here */ + /* from hif_device START HERE */ + uint16_t enabledSpiInts; + uint32_t lookAhead; + uint32_t mboxAddress; /* the address for mailbox reads/writes. */ + uint32_t blockSize; /* the mailbox block size */ + uint32_t blockMask; /* the mask derived from BlockSize */ + uint32_t *padBuffer; + uint16_t booleans; + /* from hif_device ENDS HERE */ + /* SPI SPECIFICE ELEMENTS Starts here */ + A_SPI_HCD_CXT spi_hcd; + + /* SPI SPECIFIC ELEMENTS Ends here */ + boolean scanDone; /* scan done indicator, set by WMI_SCAN_COMPLETE_EVENTID */ + boolean driverSleep; + boolean htcStart; + uint8_t htc_creditInit; + uint8_t *tempStorage; /*temporary storage shared by independent modules*/ + uint16_t tempStorageLength; /*size of temp storage allocated at init time, decided by feature set*/ + uint8_t promiscuous_mode; /* if 1 promiscuous mode is enabled */ + boolean rssiFlag; + + uint8_t apmodeWPS; +#if ENABLE_P2P_MODE + boolean p2p_avail; + uint8_t wpsRole; +#endif + boolean macProgramming; +#if MANUFACTURING_SUPPORT + boolean testResp; +#endif + uint8_t rxMultiBufferStatus; /* maintains available status of rx buffers */ + boolean pfmDone; /* scan done indicator, set by WMI_SCAN_COMPLETE_EVENTID */ + boolean wps_in_progress; + uint32_t pwrStateSetting; + boolean dset_op_done; /* dset op done indicator, set by WMI_SCAN_COMPLETE_EVENTID */ + uint8_t raw_temperature; /*register value */ + uint32_t tempDegree; /*temperature degree*/ + boolean temperatureValid; + uint8_t raw_countryCode[3]; + boolean countryCodeValid; + boolean setparamValid; + uint32_t setparamStatus; +/* PORT_NOTE: rxFreeQueue stores pre-allocated rx net-buffers. If dynamic heap +* allocation is preferred for RX net-buffers then this option should be disabled. */ +#if DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE + A_NETBUF_QUEUE_T rxFreeQueue; +#endif + + /* PORT_NOTE: pScanOut stores scan results in a buffer so that they + * can be retrieved aysnchronously by a User task. */ + uint8_t *pScanOut; /* callers buffer to hold results. */ + uint16_t scanOutSize; /* size of pScanOut buffer */ + uint16_t scanOutCount; /* current fill count of pScanOut buffer */ + + boolean driverShutdown; /* used to shutdown the driver */ + uint32_t line; + uint8_t securityType; /* used to satisfy SEC_TYPE */ + uint8_t extended_scan; /* used to indicate whether an extended scan is in progress */ +#if ENABLE_P2P_MODE + void *p2pevtCB; + boolean p2pEvtState; + boolean p2pevtflag; +#endif +#if MANUFACTURING_SUPPORT + uint32_t testCmdRespBufLen; +#endif + boolean wps_init_key; + uint32_t hb_sequence; + boolean hb_challenge_done; + WMI_SCAN_PARAMS_CMD scan_param; // save scan parameters for roam mode change + osMutexId_t apiMutex; + mbed_rtos_storage_mutex_t context_mutex_mem; +} A_DRIVER_CONTEXT; + +extern uint32_t last_driver_error; + +#define DEV_CALC_RECV_PADDED_LEN(pDCxt, length) (((length) + (pDCxt)->blockMask) & (~((pDCxt)->blockMask))) +#define DEV_CALC_SEND_PADDED_LEN(pDCxt, length) DEV_CALC_RECV_PADDED_LEN(pDCxt, length) +#define DEV_IS_LEN_BLOCK_ALIGNED(pDCxt, length) (((length) % (pDCxt)->blockSize) == 0) + +#endif /* _DRIVER_CXT_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dset.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dset.h new file mode 100644 index 00000000000..ca206e6bdb6 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dset.h @@ -0,0 +1,98 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +/**HEADER******************************************************************** +* +* +* $FileName: dset.h$ +* $Version : 3.8.40.0$ +* $Date : May-28-2014$ +* +* Comments: +* +* This file contains the defines, externs and data +* structure definitions required by application +* programs in order to use the Ethernet packet driver. +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*END************************************************************************/ +#ifndef __dset_h__ +#define __dset_h__ + +/*--------------------------------------------------------------------------*/ +/* +** CONSTANT DEFINITIONS +*/ + +#define MAX_DSET_SIZE 16 + +/*--------------------------------------------------------------------------*/ +/* +** TYPE DEFINITIONS +*/ + +typedef struct host_dset_struct +{ + uint32_t dset_id; /* dset id */ + uint32_t length; /* dset length */ + uint8_t *data_ptr; /* dset buffer address */ +} HOST_DSET; + +typedef struct host_dset_item +{ + uint32_t dset_id; /* dset id */ + uint32_t length; /* dset length */ +} HOST_DSET_ITEM; + +/*--------------------------------------------------------------------------*/ +/* +** PROTOTYPES AND GLOBAL EXTERNS +*/ + +HOST_DSET *dset_find(uint32_t dset_id); +HOST_DSET *dset_get(uint32_t dset_id, uint32_t length); +uint32_t dset_write(HOST_DSET *pDset, uint8_t *pData, uint32_t offset, uint32_t length); +uint32_t dset_read(HOST_DSET *pDset, uint8_t *pData, uint32_t offset, uint32_t length); +uint32_t dset_fill(uint8_t *pData, uint32_t max_dset_count); + +HOST_DSET *dset_get_first(void); +HOST_DSET *dset_get_next(void); + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dset_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dset_api.h new file mode 100644 index 00000000000..eaa30a0f640 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/dset_api.h @@ -0,0 +1,145 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +/**HEADER******************************************************************** +* +* +* +* $FileName: dset.h$ +* $Version : 3.8.40.0$ +* $Date : May-28-2014$ +* +* Comments: +* +* This file contains the defines, externs and data +* structure definitions required by application +* programs in order to use the Ethernet packet driver. +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*END************************************************************************/ +#ifndef __dset_api_h__ +#define __dset_api_h__ + +/*--------------------------------------------------------------------------*/ +/* +** CONSTANT DEFINITIONS +*/ + +#define MAX_HOST_DSET_SIZE 8 + +#define INVALID_DSET_ID 0 + +typedef enum __DSET_OP +{ + DSET_OP_CREATE = 1, + DSET_OP_OPEN = 2, + DSET_OP_READ = 3, + DSET_OP_WRITE = 4, + DSET_OP_COMMIT = 5, + DSET_OP_CLOSE = 6, + DSET_OP_SIZE = 7, + DSET_OP_DELETE = 8, +} DSET_OP; + +#define MAX_DSET_BUFF_SIZE 1500 + +/*--------------------------------------------------------------------------*/ +/* +** TYPE DEFINITIONS +*/ + +typedef void (*dset_callback_fn_t)(uint32_t status, void *pv); + +typedef struct host_api_dset_struct +{ + uint32_t dset_id; /* dset id */ + uint32_t media_id; + uint32_t flags; + uint32_t offset; /* dset offset */ + uint32_t length; /* dset length */ + uint32_t left_len; /* for large read/write */ + dset_callback_fn_t cb; + void *cb_args; + uint8_t done_flag; + uint8_t *data_ptr; /* dset buffer address */ +} HOST_DSET_HANDLE; + +// typedef struct host_dset_item { +// uint32_t dset_id; /* dset id */ +// uint32_t length; /* dset length */ +//} HOST_DSET_ITEM; + +/*--------------------------------------------------------------------------*/ +/* +** PROTOTYPES AND GLOBAL EXTERNS +*/ + +extern HOST_DSET_HANDLE dset_handles[]; + +HOST_DSET_HANDLE *dset_find_handle(uint32_t dset_id); + +int32_t qcom_dset_create(HOST_DSET_HANDLE **pDsetHandle, + uint32_t dset_id, + uint32_t media_id, + uint32_t length, + uint32_t flags, + dset_callback_fn_t create_cb, + void *callback_arg); +int32_t qcom_dset_open( + HOST_DSET_HANDLE **pDsetHandle, uint32_t dset_id, uint32_t flags, dset_callback_fn_t open_cb, void *callback_arg); +uint32_t qcom_dset_write(HOST_DSET_HANDLE *pDsetHandle, + uint8_t *buffer, + uint32_t length, + uint32_t offset, + uint32_t flags, + dset_callback_fn_t write_cb, + void *callback_arg); +uint32_t qcom_dset_read(HOST_DSET_HANDLE *pDsetHandle, + uint8_t *buffer, + uint32_t length, + uint32_t offset, + dset_callback_fn_t read_cb, + void *callback_arg); +uint32_t qcom_dset_commit(HOST_DSET_HANDLE *pDsetHandle, dset_callback_fn_t read_cb, void *callback_arg); +uint32_t qcom_dset_close(HOST_DSET_HANDLE *pDsetHandle, dset_callback_fn_t read_cb, void *callback_arg); +uint32_t qcom_dset_size(HOST_DSET_HANDLE *pDsetHandle, dset_callback_fn_t read_cb, void *callback_arg); +uint32_t qcom_dset_delete(uint32_t dset_id, uint32_t flags, dset_callback_fn_t read_cb, void *callback_arg); + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/hif_internal.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/hif_internal.h new file mode 100644 index 00000000000..ae92a7ca57e --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/hif_internal.h @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HIF_INTERNAL_H_ +#define _HIF_INTERNAL_H_ + +#define HIF_ACTIVE_MBOX_INDEX (0) + +#define HIF_MBOX_BLOCK_SIZE 32 +#define HIF_MBOX_BASE_ADDR 0x800 +#define HIF_MBOX_WIDTH 0x800 +#define HIF_MBOX0_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE + +#define SPI_CLOCK_FREQUENCY_DEFAULT 24000000 +#define SPI_CLOCK_FREQUENCY_REDUCED 12000000 + +#define HIF_MBOX_START_ADDR(mbox) HIF_MBOX_BASE_ADDR + mbox *HIF_MBOX_WIDTH + +#define HIF_MBOX_END_ADDR(mbox) HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1 + +#endif /* _HIF_INTERNAL_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/htc_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/htc_api.h new file mode 100644 index 00000000000..b60502b627c --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/htc_api.h @@ -0,0 +1,80 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _HTC_API_H_ +#define _HTC_API_H_ + +#include + +typedef uint16_t HTC_SERVICE_ID; + +#define HTC_MAILBOX_NUM_MAX 4 + +/* ------ Endpoint IDS ------ */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT_0 = 0, + ENDPOINT_1, + ENDPOINT_2, + ENDPOINT_MANAGED_MAX, + ENDPOINT_3 = ENDPOINT_2 + 1, + ENDPOINT_4, + ENDPOINT_5, +#if WLAN_CONFIG_TRUNCATED_ENDPOINTS + ENDPOINT_MAX +#else + ENDPOINT_6, + ENDPOINT_7, + ENDPOINT_8, + ENDPOINT_MAX +#endif +} HTC_ENDPOINT_ID; + +/* service connection information */ +typedef struct _HTC_SERVICE_CONNECT_REQ +{ + HTC_SERVICE_ID ServiceID; /* service ID to connect to */ + uint16_t ConnectionFlags; /* connection flags, see htc protocol definition */ + uint8_t *pMetaData; /* ptr to optional service-specific meta-data */ + uint8_t MetaDataLength; /* optional meta data length */ + int32_t MaxSendQueueDepth; /* maximum depth of any send queue */ + uint32_t LocalConnectionFlags; /* HTC flags for the host-side (local) connection */ + uint32_t MaxSendMsgSize; /* override max message size in send direction */ +} HTC_SERVICE_CONNECT_REQ; + +#define HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING (1 << 0) /* enable send bundle padding for this endpoint */ + +/* service connection response information */ +typedef struct _HTC_SERVICE_CONNECT_RESP +{ + uint8_t *pMetaData; /* caller supplied buffer to optional meta-data */ + uint8_t BufferLength; /* length of caller supplied buffer */ + uint8_t ActualLength; /* actual length of meta data */ + HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */ + uint32_t MaxMsgLength; /* max length of all messages over this endpoint */ + uint8_t ConnectRespCode; /* connect response code from target */ +} HTC_SERVICE_CONNECT_RESP; + +#endif /* _HTC_API_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/ieee80211.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/ieee80211.h new file mode 100644 index 00000000000..03bd26bc043 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/ieee80211.h @@ -0,0 +1,388 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + +/* + * 802.11 protocol definitions. + */ +#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ +#define IEEE80211_WEP_IVLEN 3 /* 24bit */ +#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ +#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ +#define IEEE80211_WEP_NKID 4 /* number of key ids */ + +/* + * 802.11i defines an extended IV for use with non-WEP ciphers. + * When the EXTIV bit is set in the key id byte an additional + * 4 bytes immediately follow the IV for TKIP. For CCMP the + * EXTIV bit is likewise set but the 8 bytes represent the + * CCMP header rather than IV+extended-IV. + */ +#define IEEE80211_WEP_EXTIV 0x20 +#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */ +#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */ + +#define IEEE80211_CRC_LEN 4 + +#ifdef WAPI_ENABLE +#define IEEE80211_WAPI_EXTIVLEN 10 /* extended IV length */ +#endif /* WAPI ENABLE */ + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +/* is 802.11 address multicast/broadcast? */ +#define IEEE80211_IS_MULTICAST(_a) (*(_a)&0x01) +#define IEEE80211_IS_BROADCAST(_a) (*(_a) == 0xFF) +#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN) +#define WEP_TRAILER IEEE80211_WEP_CRCLEN +#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_EXTIVLEN) +#define CCMP_TRAILER IEEE80211_WEP_MICLEN +#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_EXTIVLEN) +#define TKIP_TRAILER IEEE80211_WEP_CRCLEN +#define TKIP_MICLEN IEEE80211_WEP_MICLEN + +#define IEEE80211_ADDR_EQ(addr1, addr2) (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0) + +#define IEEE80211_ADDR_COPY(dst, src) A_MEMCPY(dst, src, IEEE80211_ADDR_LEN) + +#define IEEE80211_KEYBUF_SIZE 16 +#define IEEE80211_MICBUF_SIZE (8 + 8) /* space for both tx and rx */ + +/* + * NB: these values are ordered carefully; there are lots of + * of implications in any reordering. In particular beware + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY. + */ +#define IEEE80211_CIPHER_WEP 0 +#define IEEE80211_CIPHER_TKIP 1 +#define IEEE80211_CIPHER_AES_OCB 2 +#define IEEE80211_CIPHER_AES_CCM 3 +#define IEEE80211_CIPHER_CKIP 5 +#define IEEE80211_CIPHER_CCKM_KRK 6 +#define IEEE80211_CIPHER_NONE 7 /* pseudo value */ + +#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE + 1) + +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) (((len) == 5) || ((len) == 13) || ((len) == 16)) + +/* + * generic definitions for IEEE 802.11 frames + */ +PREPACK struct ieee80211_frame +{ + uint8_t i_fc[2] FIELD_PACKED; + uint8_t i_dur[2] FIELD_PACKED; + uint8_t i_addr1[IEEE80211_ADDR_LEN] FIELD_PACKED; + uint8_t i_addr2[IEEE80211_ADDR_LEN] FIELD_PACKED; + uint8_t i_addr3[IEEE80211_ADDR_LEN] FIELD_PACKED; + uint8_t i_seq[2] FIELD_PACKED; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} POSTPACK; + +PREPACK struct ieee80211_qosframe +{ + uint8_t i_fc[2] FIELD_PACKED; + uint8_t i_dur[2] FIELD_PACKED; + uint8_t i_addr1[IEEE80211_ADDR_LEN] FIELD_PACKED; + uint8_t i_addr2[IEEE80211_ADDR_LEN] FIELD_PACKED; + uint8_t i_addr3[IEEE80211_ADDR_LEN] FIELD_PACKED; + uint8_t i_seq[2] FIELD_PACKED; + uint8_t i_qos[2] FIELD_PACKED; +} POSTPACK; + +#define IEEE80211_FC0_VERSION_MASK 0x03 +#define IEEE80211_FC0_VERSION_SHIFT 0 +#define IEEE80211_FC0_VERSION_0 0x00 +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_SHIFT 2 +#define IEEE80211_FC0_TYPE_MGT 0x00 +#define IEEE80211_FC0_TYPE_CTL 0x04 +#define IEEE80211_FC0_TYPE_DATA 0x08 + +#define IEEE80211_FC0_SUBTYPE_MASK 0xf0 +#define IEEE80211_FC0_SUBTYPE_SHIFT 4 +/* for TYPE_MGT */ +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 +#define IEEE80211_FC0_SUBTYPE_BEACON 0x80 +#define IEEE80211_FC0_SUBTYPE_ATIM 0x90 +#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 +#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 +#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 +/* for TYPE_CTL */ +#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 +#define IEEE80211_FC0_SUBTYPE_RTS 0xb0 +#define IEEE80211_FC0_SUBTYPE_CTS 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACK 0xd0 +#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 +/* for TYPE_DATA (bit combination) */ +#define IEEE80211_FC0_SUBTYPE_DATA 0x00 +#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 +#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 +#define IEEE80211_FC0_SUBTYPE_NODATA 0x40 +#define IEEE80211_FC0_SUBTYPE_CFACK 0x50 +#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 + +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ + +#define IEEE80211_FC1_MORE_FRAG 0x04 +#define IEEE80211_FC1_RETRY 0x08 +#define IEEE80211_FC1_PWR_MGT 0x10 +#define IEEE80211_FC1_MORE_DATA 0x20 +#define IEEE80211_FC1_WEP 0x40 +#define IEEE80211_FC1_ORDER 0x80 + +#define IEEE80211_SEQ_FRAG_MASK 0x000f +#define IEEE80211_SEQ_FRAG_SHIFT 0 +#define IEEE80211_SEQ_SEQ_MASK 0xfff0 +#define IEEE80211_SEQ_SEQ_SHIFT 4 + +#define IEEE80211_NWID_LEN 32 + +/* + * 802.11 rate set. + */ +#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ +#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */ + +#define WMM_NUM_AC 4 /* 4 AC categories */ + +#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */ +#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */ +#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */ +#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */ +#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */ +#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */ +#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */ +#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ + +#define WMM_AC_TO_TID(_ac) (((_ac) == WMM_AC_VO) ? 6 : ((_ac) == WMM_AC_VI) ? 5 : ((_ac) == WMM_AC_BK) ? 1 : 0) + +#define TID_TO_WMM_AC(_tid) (((_tid) < 1) ? WMM_AC_BE : ((_tid) < 3) ? WMM_AC_BK : ((_tid) < 6) ? WMM_AC_VI : WMM_AC_VO) +/* + * Management information element payloads. + */ + +enum +{ + IEEE80211_ELEMID_SSID = 0, + IEEE80211_ELEMID_RATES = 1, + IEEE80211_ELEMID_FHPARMS = 2, + IEEE80211_ELEMID_DSPARMS = 3, + IEEE80211_ELEMID_CFPARMS = 4, + IEEE80211_ELEMID_TIM = 5, + IEEE80211_ELEMID_IBSSPARMS = 6, + IEEE80211_ELEMID_COUNTRY = 7, + IEEE80211_ELEMID_CHALLENGE = 16, + /* 17-31 reserved for challenge text extension */ + IEEE80211_ELEMID_PWRCNSTR = 32, + IEEE80211_ELEMID_PWRCAP = 33, + IEEE80211_ELEMID_TPCREQ = 34, + IEEE80211_ELEMID_TPCREP = 35, + IEEE80211_ELEMID_SUPPCHAN = 36, + IEEE80211_ELEMID_CHANSWITCH = 37, + IEEE80211_ELEMID_MEASREQ = 38, + IEEE80211_ELEMID_MEASREP = 39, + IEEE80211_ELEMID_QUIET = 40, + IEEE80211_ELEMID_IBSSDFS = 41, + IEEE80211_ELEMID_ERP = 42, + IEEE80211_ELEMID_HTCAP_ANA = 45, /* Address ANA, and non-ANA story, for interop. CL#171733 */ + IEEE80211_ELEMID_RSN = 48, + IEEE80211_ELEMID_XRATES = 50, + IEEE80211_ELEMID_HTINFO_ANA = 61, +#ifdef WAPI_ENABLE + IEEE80211_ELEMID_WAPI = 68, +#endif + IEEE80211_ELEMID_TPC = 150, + IEEE80211_ELEMID_CCKM = 156, + IEEE80211_ELEMID_VENDOR = 221 /* vendor private */ +}; + +#define ATH_OUI 0x7f0300 /* Atheros OUI */ +#define ATH_OUI_TYPE 0x01 +#define ATH_OUI_SUBTYPE 0x01 +#define ATH_OUI_VERSION 0x00 + +#define WPA_OUI 0xf25000 +#define WPA_OUI_TYPE 0x01 +#define WPA_VERSION 1 /* current supported version */ + +#define WPA_CSE_NULL 0x00 +#define WPA_CSE_WEP40 0x01 +#define WPA_CSE_TKIP 0x02 +#define WPA_CSE_CCMP 0x04 +#define WPA_CSE_WEP104 0x05 + +#define WPA_ASE_NONE 0x00 +#define WPA_ASE_8021X_UNSPEC 0x01 +#define WPA_ASE_8021X_PSK 0x02 + +#define RSN_OUI 0xac0f00 +#define RSN_VERSION 1 /* current supported version */ + +#define RSN_CSE_NULL 0x00 +#define RSN_CSE_WEP40 0x01 +#define RSN_CSE_TKIP 0x02 +#define RSN_CSE_WRAP 0x03 +#define RSN_CSE_CCMP 0x04 +#define RSN_CSE_WEP104 0x05 + +#define RSN_ASE_NONE 0x00 +#define RSN_ASE_8021X_UNSPEC 0x01 +#define RSN_ASE_8021X_PSK 0x02 + +#define RSN_CAP_PREAUTH 0x01 + +#define WMM_OUI 0xf25000 +#define WMM_OUI_TYPE 0x02 +#define WMM_INFO_OUI_SUBTYPE 0x00 +#define WMM_PARAM_OUI_SUBTYPE 0x01 +#define WMM_VERSION 1 + +/* WMM stream classes */ +#define WMM_NUM_AC 4 +#define WMM_AC_BE 0 /* best effort */ +#define WMM_AC_BK 1 /* background */ +#define WMM_AC_VI 2 /* video */ +#define WMM_AC_VO 3 /* voice */ + +/* TSPEC related */ +#define ACTION_CATEGORY_CODE_TSPEC 17 +#define ACTION_CODE_TSPEC_ADDTS 0 +#define ACTION_CODE_TSPEC_ADDTS_RESP 1 +#define ACTION_CODE_TSPEC_DELTS 2 + +typedef enum +{ + TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0, + TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1, + TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3, + TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8, + TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9, + TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA, + TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB, + TSPEC_STATUS_CODE_DELTS_SENT = 0x30, + TSPEC_STATUS_CODE_DELTS_RECV = 0x31 +} TSPEC_STATUS_CODE; + +#define TSPEC_TSID_MASK 0xF +#define TSPEC_TSID_S 1 + +/* + * WMM/802.11e Tspec Element + */ +typedef PREPACK struct wmm_tspec_ie_t +{ + uint8_t elementId FIELD_PACKED; + uint8_t len FIELD_PACKED; + uint8_t oui[3] FIELD_PACKED; + uint8_t ouiType FIELD_PACKED; + uint8_t ouiSubType FIELD_PACKED; + uint8_t version FIELD_PACKED; + uint16_t tsInfo_info FIELD_PACKED; + uint8_t tsInfo_reserved FIELD_PACKED; + uint16_t nominalMSDU FIELD_PACKED; + uint16_t maxMSDU FIELD_PACKED; + uint32_t minServiceInt FIELD_PACKED; + uint32_t maxServiceInt FIELD_PACKED; + uint32_t inactivityInt FIELD_PACKED; + uint32_t suspensionInt FIELD_PACKED; + uint32_t serviceStartTime FIELD_PACKED; + uint32_t minDataRate FIELD_PACKED; + uint32_t meanDataRate FIELD_PACKED; + uint32_t peakDataRate FIELD_PACKED; + uint32_t maxBurstSize FIELD_PACKED; + uint32_t delayBound FIELD_PACKED; + uint32_t minPhyRate FIELD_PACKED; + uint16_t sba FIELD_PACKED; + uint16_t mediumTime FIELD_PACKED; +} POSTPACK WMM_TSPEC_IE; + +/* + * BEACON management packets + * + * octet timestamp[8] + * octet beacon interval[2] + * octet capability information[2] + * information element + * octet elemid + * octet length + * octet information[length] + */ + +#define IEEE80211_BEACON_INTERVAL(beacon) ((beacon)[8] | ((beacon)[9] << 8)) +#define IEEE80211_BEACON_CAPABILITY(beacon) ((beacon)[10] | ((beacon)[11] << 8)) + +#define IEEE80211_CAPINFO_ESS 0x0001 +#define IEEE80211_CAPINFO_IBSS 0x0002 +#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 +#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 +#define IEEE80211_CAPINFO_PRIVACY 0x0010 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 +#define IEEE80211_CAPINFO_PBCC 0x0040 +#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 +/* bits 8-9 are reserved */ +#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 +#define IEEE80211_CAPINFO_APSD 0x0800 +/* bit 12 is reserved */ +#define IEEE80211_CAPINFO_DSSSOFDM 0x2000 +/* bits 14-15 are reserved */ + +/* + * Authentication Modes + */ + +enum ieee80211_authmode +{ + IEEE80211_AUTH_NONE = 0, + IEEE80211_AUTH_OPEN = 1, + IEEE80211_AUTH_SHARED = 2, + IEEE80211_AUTH_8021X = 3, + IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */ + /* NB: these are used only for ioctls */ + IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */ + IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */ + IEEE80211_AUTH_WPA_CCKM = 7 /* WPA/RSN IE w/ CCKM */ +}; + +#define IEEE80211_PS_MAX_QUEUE 50 /*Maximum no of buffers that can be queues for PS*/ + +#define IEEE80211_TKIP_COUNTERMEASURES_TIMEOUT_MSEC (60000) + +#endif /* _NET80211_IEEE80211_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/netbuf.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/netbuf.h new file mode 100644 index 00000000000..77e7e08bfac --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/netbuf.h @@ -0,0 +1,178 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _NETBUF_H_ +#define _NETBUF_H_ + +#include +#include +#include + +/* + * Network buffer queue support + */ +typedef struct +{ + void *head; + void *tail; + uint16_t count; +} A_NETBUF_QUEUE_T; + +typedef void (*A_TRANS_CB)(void *, void *); + +/* A_TRANSPORT_OBJ - the structure used to encapsulate any/all bus requests */ +typedef struct _transport_obj +{ + uint32_t lookahead; /* expected lookahead value for sanity checking */ + uint16_t transferLength; /* total transfer length including any pad bytes */ + uint16_t address; /* register address from which the transfer will begin */ + uint16_t cmd; /* bit field containing command values */ + uint8_t credits; /* num credits consumed by this request (TX only) */ + uint8_t epid; /* endpoint ID */ + A_STATUS status; /* transport status */ + A_TRANS_CB cb; /* callback to be used upon completion */ +} A_TRANSPORT_OBJ; + +#define A_NETBUF_QUEUE_INIT(q) a_netbuf_queue_init(q) + +#define A_NETBUF_ENQUEUE(q, pReq) a_netbuf_enqueue((q), (pReq)) +#define A_NETBUF_PREQUEUE(q, pReq) a_netbuf_prequeue((q), (pReq)) +#define A_NETBUF_DEQUEUE(q) (a_netbuf_dequeue((q))) +#define A_NETBUF_PEEK_QUEUE(q) ((A_NETBUF_QUEUE_T *)(q))->head +#define A_NETBUF_QUEUE_SIZE(q) ((A_NETBUF_QUEUE_T *)(q))->count +#define A_NETBUF_QUEUE_EMPTY(q) (!((A_NETBUF_QUEUE_T *)(q))->count) + +/* + * receiver buffer + */ + +#define A_RXBUF_ENQUEUE(q, pReq) a_rxbuf_enqueue((q), (pReq)) +#define A_RXBUF_DEQUEUE(q) (a_rxbuf_dequeue((q))) + +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pReq); +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pReq); +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q); + +void a_rxbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pReq); +void *a_rxbuf_dequeue(A_NETBUF_QUEUE_T *q); + +// int32_t a_netbuf_queue_size(A_NETBUF_QUEUE_T *q); +// int32_t a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q); +// void *a_netbuf_peek_queue(A_NETBUF_QUEUE_T *q); + +#define MAX_NUM_FREE_QUEUES 8 +#define AR6000_DATA_OFFSET 64 + +typedef struct mgmt_credits +{ + uint16_t rxMaxBufferSizeInQueues; + uint8_t rxMaxBuffersInQueues; + uint8_t rxQueueMask; + uint8_t credit_count; + uint8_t init_credits; +} MGMT_CREDITS; + +extern uint8_t send_reverse_credits_flag; +extern MGMT_CREDITS host_credits[MAX_NUM_FREE_QUEUES]; + +extern A_NETBUF_QUEUE_T rxFreeQueues[MAX_NUM_FREE_QUEUES]; + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) +extern uint8_t credits_test; +#endif + +// extern uint16_t rxMaxBuffersInQueues[MAX_NUM_FREE_QUEUES]; +// extern uint16_t rxMaxBufferSizeInQueues[MAX_NUM_FREE_QUEUES]; +// extern uint8_t rxQueueMask[MAX_NUM_FREE_QUEUES]; + +#define GET_NUM_CREDIT_QUEUES() (MAX_NUM_FREE_QUEUES) + +#define GET_MAX_BUFFERS_IN_QUEUE(i) (MAX_BUFFERS_IN_QUEUE_##i) + +#define GET_INIT_CREDITS_IN_QUEUES(a) \ + a[0].init_credits = GET_MAX_BUFFERS_IN_QUEUE(0); \ + a[1].init_credits = GET_MAX_BUFFERS_IN_QUEUE(1); \ + a[2].init_credits = GET_MAX_BUFFERS_IN_QUEUE(2); \ + a[3].init_credits = GET_MAX_BUFFERS_IN_QUEUE(3); \ + a[4].init_credits = GET_MAX_BUFFERS_IN_QUEUE(4); \ + a[5].init_credits = GET_MAX_BUFFERS_IN_QUEUE(5); \ + a[6].init_credits = GET_MAX_BUFFERS_IN_QUEUE(6); \ + a[7].init_credits = GET_MAX_BUFFERS_IN_QUEUE(7); + +#define GET_MAX_BUFFERS_IN_QUEUES(a) \ + a[0].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(0); \ + a[1].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(1); \ + a[2].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(2); \ + a[3].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(3); \ + a[4].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(4); \ + a[5].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(5); \ + a[6].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(6); \ + a[7].rxMaxBuffersInQueues = GET_MAX_BUFFERS_IN_QUEUE(7); + +#define GET_BUFFER_SIZE_IN_QUEUE(i) (BUFFER_SIZE_IN_QUEUE_##i) + +#define GET_BUFFER_SIZE_IN_QUEUES(a) \ + a[0].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(0); \ + a[1].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(1); \ + a[2].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(2); \ + a[3].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(3); \ + a[4].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(4); \ + a[5].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(5); \ + a[6].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(6); \ + a[7].rxMaxBufferSizeInQueues = GET_BUFFER_SIZE_IN_QUEUE(7); + +#define QUEUE_MASK(i) (QUEUE_MASK_##i) + +#define GET_MASK_ALL_QUEUES(a) \ + a[0].rxQueueMask = QUEUE_MASK(0); \ + a[1].rxQueueMask = QUEUE_MASK(1); \ + a[2].rxQueueMask = QUEUE_MASK(2); \ + a[3].rxQueueMask = QUEUE_MASK(3); \ + a[4].rxQueueMask = QUEUE_MASK(4); \ + a[5].rxQueueMask = QUEUE_MASK(5); \ + a[6].rxQueueMask = QUEUE_MASK(6); \ + a[7].rxQueueMask = QUEUE_MASK(7); + +#define GET_FREE_QUEUE(i) (rxFreeQueues[i]) + +#define GET_QUEUE_BUFFER_SIZE(i) (host_credits[i].rxMaxBufferSizeInQueues + AR6000_DATA_OFFSET) +#define GET_QUEUE_DATA_BUFFER_SIZE(i) (host_credits[i].rxMaxBufferSizeInQueues) +#define GET_MAX_NUM_BUFFERS(i) (host_credits[i].rxMaxBuffersInQueues) +#define GET_QUEUE_MASK(i) (host_credits[i].rxQueueMask) +#define CREDIT_INC(i) \ + { \ + if (credits_test == 0) \ + host_credits[i].credit_count++; \ + } +#define CREDIT_ADD(i, c) \ + { \ + host_credits[i].credit_count += c; \ + } +#define CREDIT_DEC(i) (host_credits[i].credit_count--) +#define GET_CREDIT(i) (host_credits[i].credit_count) +#define GET_INIT_CREDITS(i) (host_credits[i].init_credits) +#define CLEAR_CREDIT(i) (host_credits[i].credit_count = 0) + +#endif /* _NETBUF_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/spi_hcd_if.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/spi_hcd_if.h new file mode 100644 index 00000000000..f1973f73e4a --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/spi_hcd_if.h @@ -0,0 +1,246 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __SPI_HCD_IF_H___ +#define __SPI_HCD_IF_H___ + +typedef uint8_t ATH_TRANS_CMD; + +/* transfer SPI frame size flags for HCD internal use */ +#define ATH_TRANS_DS_8 0x00 +#define ATH_TRANS_DS_16 0x01 +#define ATH_TRANS_DS_24 0x02 /* 24 bit transfer, for HCD internal use only! */ +#define ATH_TRANS_DS_32 0x03 + +#define ATH_TRANS_DS_MASK 0x03 +#define ATH_TRANS_DMA 0x04 /* special DMA transfer */ +#define ATH_TRANS_TYPE_MASK 0x07 +/* register access is internal or external */ +#define ATH_TRANS_INT_TRANS 0x00 /* internal register (SPI internal) transfer */ +#define ATH_TRANS_EXT_TRANS 0x10 /* external register transfer */ +/* transfer to fixed or incrementing address (external transfers only) */ +#define ATH_TRANS_EXT_TRANS_ADDR_INC 0x00 +#define ATH_TRANS_EXT_TRANS_ADDR_FIXED 0x20 +/* direction of operation */ +#define ATH_TRANS_READ 0x80 +#define ATH_TRANS_WRITE 0x00 + +#define ATH_TRANS_EXT_MAX_PIO_BYTES 32 + +/* address mask */ +#define ATH_TRANS_ADDR_MASK 0x7FFF +/* macro to get the transfer type from a command */ +#define ATH_GET_TRANS_TYPE(cmd) ((cmd)&ATH_TRANS_TYPE_MASK) +/* macro to get the transfer data size */ +#define ATH_GET_TRANS_DS(cmd) ((cmd)&ATH_TRANS_DS_MASK) + +#define ATH_TRANS_IS_DIR_READ(cmd) ((cmd)&ATH_TRANS_READ) +#define ATH_TRANS_IS_DIR_WRITE(cmd) !ATH_TRANS_IS_DIR_READ(cmd) + +/* macros for passing values in writes and getting read data and status values */ +#define ATH_GET_PIO_WRITE_VALUE(pReq) GET_REQ_HEADER_ELEM((pReq), A_REQ_HEADER_DATA)[0] +#define ATH_SET_PIO_WRITE_VALUE(pReq, v) GET_REQ_HEADER_ELEM((pReq), A_REQ_HEADER_DATA)[0] = (UINT32)(v) +#define ATH_GET_PIO_INTERNAL_READ_RESULT(pReq) (UINT16) GET_REQ_HEADER_ELEM((pReq), A_REQ_HEADER_DATA)[1] +#define ATH_SET_PIO_INTERNAL_READ_RESULT(pReq, result) \ + GET_REQ_HEADER_ELEM((pReq), A_REQ_HEADER_DATA)[1] = (UINT32)(result) + +#define ATH_GET_IO_CMD(pReq) A_NETBUF_GET_ELEM((pReq), A_REQ_COMMAND) +#define ATH_SET_IO_CMD(pReq, cmd) A_NETBUF_SET_ELEM((pReq), A_REQ_COMMAND, (cmd)) +#define ATH_GET_IO_DS(pReq) ATH_GET_TRANS_DS(ATH_GET_IO_CMD(pReq)) + +#define ATH_GET_IO_ADDRESS(pReq) A_NETBUF_GET_ELEM((pReq), A_REQ_ADDRESS) +#define ATH_SET_IO_ADDRESS(pReq, addr) A_NETBUF_SET_ELEM((pReq), A_REQ_ADDRESS, (addr)) +#define ATH_GET_DMA_TRANSFER_BYTES(pReq) A_NETBUF_GET_ELEM((pReq), A_REQ_TRANSFER_LEN) +#define ATH_GET_EXT_TRANSFER_BYTES(pReq) A_NETBUF_LEN(pReq) +#define ATH_SET_TRANSFER_BYTES(pReq, bytes) A_NETBUF_SET_ELEM((pReq), A_REQ_TRANSFER_LEN, (bytes)) + +#define ATH_IS_TRANS_READ(pReq) (ATH_TRANS_IS_DIR_READ(ATH_GET_IO_CMD(pReq))) +#define ATH_IS_TRANS_WRITE(pReq) (!ATH_IS_TRANS_READ(pReq)) +#define ATH_IS_TRANS_DMA(pReq) (ATH_GET_IO_CMD(pReq) & ATH_TRANS_DMA) +#define ATH_IS_TRANS_PIO(pReq) (!ATH_IS_TRANS_DMA(pReq)) +#define ATH_IS_TRANS_PIO_EXTERNAL(pReq) (ATH_GET_IO_CMD(pReq) & ATH_TRANS_EXT_TRANS) +#define ATH_IS_TRANS_PIO_INTERNAL(pReq) !ATH_IS_TRANS_PIO_EXTERNAL(pReq) +#define ATH_IS_TRANS_EXT_ADDR_FIXED(pReq) (ATH_GET_IO_CMD(pReq) & ATH_TRANS_EXT_TRANS_ADDR_FIXED) +#define ATH_IS_TRANS_EXT_ADDR_INC(pReq) !ATH_IS_TRANS_EXT_ADDR_FIXED(pReq) + +/* macros to setup PIO write transfer requests */ +#define ATH_SET_PIO_INTERNAL_WRITE_OPERATION(pReq, addr, value) \ + \ +{ \ + ATH_SET_IO_CMD(pReq, ATH_TRANS_WRITE | ATH_TRANS_INT_TRANS); \ + ATH_SET_IO_ADDRESS(pReq, (uint16_t)((addr)&ATH_TRANS_ADDR_MASK)); \ + ATH_SET_PIO_WRITE_VALUE(pReq, value); \ + \ +} + +/* macros to setup PIO read transfer requests */ +#define ATH_SET_PIO_INTERNAL_READ_OPERATION(pReq, addr) \ + \ +{ \ + ATH_SET_IO_CMD(pReq, ATH_TRANS_READ | ATH_TRANS_INT_TRANS); \ + ATH_SET_IO_ADDRESS(pReq, (uint16_t)((addr)&ATH_TRANS_ADDR_MASK)); \ + \ +} + +/* macro to setup external register transfer request + * note: caller must set pReq->pDataBuffer separately */ +#define ATH_SET_PIO_EXTERNAL_OPERATION(pReq, type, addr, incaddr, length) \ + \ +{ \ + ATH_SET_IO_CMD(pReq, (type) | ATH_TRANS_EXT_TRANS | \ + ((incaddr) ? ATH_TRANS_EXT_TRANS_ADDR_INC : ATH_TRANS_EXT_TRANS_ADDR_FIXED)); \ + ATH_SET_IO_ADDRESS(pReq, (uint16_t)((addr)&ATH_TRANS_ADDR_MASK)); \ + ATH_SET_TRANSFER_BYTES(pReq, (uint16_t)(length)); \ + \ +} + +#define ATH_SET_PIO_EXTERNAL_WRITE_OPERATION(pReq, addr, incaddr, length) \ + ATH_SET_PIO_EXTERNAL_OPERATION(pReq, ATH_TRANS_WRITE, addr, incaddr, length) + +#define ATH_SET_PIO_EXTERNAL_READ_OPERATION(pReq, addr, incaddr, length) \ + ATH_SET_PIO_EXTERNAL_OPERATION(pReq, ATH_TRANS_READ, addr, incaddr, length) + +/* macros to setup DMA transfer requests, 64K max transfers + * note, the caller must set pReq->pDataBuffer separately + * and the number bytes (length) must be aligned to the DMA data width */ +#define ATH_SET_DMA_OPERATION(pReq, dir, addr, length) \ + \ +{ \ + ATH_SET_IO_CMD(pReq, ATH_TRANS_DMA | (dir)); \ + ATH_SET_IO_ADDRESS(pReq, (UINT16)((addr)&ATH_TRANS_ADDR_MASK)); \ + ATH_SET_TRANSFER_BYTES(pReq, (UINT16)(length)); \ + \ +} + +#define ATH_SPI_DMA_SIZE_REG (0x0100) /* internal */ +#define ATH_SPI_DMA_SIZE_MAX (4095) /* 12 bit counter 0-4095 are valid */ + +#define ATH_SPI_WRBUF_SPC_AVA_REG (0x0200) /* internal */ + +#define ATH_SPI_RDBUF_BYTE_AVA_REG (0x0300) /* internal */ + +#define ATH_SPI_CONFIG_REG (0x0400) /* internal */ +#define ATH_SPI_CONFIG_RESET (1 << 15) /* SPI interface reset */ +#define ATH_SPI_CONFIG_MBOX_INTR_EN (1 << 8) +#define ATH_SPI_CONFIG_IO_ENABLE (1 << 7) +#define ATH_SPI_CONFIG_CORE_RESET (1 << 6) /* core reset */ +#define ATH_SPI_CONFIG_KEEP_AWAKE_ON_INTR (1 << 4) +#define ATH_SPI_CONFIG_KEEP_AWAKE (1 << 3) +#define ATH_SPI_CONFIG_BYTE_SWAP (1 << 2) +#define ATH_SPI_CONFIG_SWAP_16BIT (1 << 1) +#define ATH_SPI_CONFIG_PREFETCH_MODE_RR (1 << 0) + +#define ATH_SPI_CONFIG_MISO_MUXSEL_MASK_SHIFT 9 + +#define ATH_SPI_STATUS_REG (0x0500) /* internal */ +#define ATH_SPI_STATUS_MBOX_FLOW_CTRL (1 << 5) +#define ATH_SPI_STATUS_WRBUF_ERROR (1 << 4) +#define ATH_SPI_STATUS_RDBUF_ERROR (1 << 3) +#define ATH_SPI_STATUS_RTC_STATE_MASK (0x3 << 1) +#define ATH_SPI_STATUS_RTC_STATE_WAKEUP (0x3 << 1) +#define ATH_SPI_STATUS_RTC_STATE_SLEEP (0x2 << 1) +#define ATH_SPI_STATUS_RTC_STATE_ON (0x1 << 1) +#define ATH_SPI_STATUS_RTC_STATE_SHUTDOWN (0x0) +#define ATH_SPI_STATUS_HOST_ACCESS_DONE (1 << 0) +#define ATH_SPI_STATUS_ERRORS (ATH_SPI_STATUS_WRBUF_ERROR | ATH_SPI_STATUS_RDBUF_ERROR) + +#define ATH_SPI_HOST_CTRL_BYTE_SIZE_REG (0x0600) /* internal */ +#define ATH_SPI_HOST_CTRL_NO_ADDR_INC (1 << 6) +#define ATH_SPI_HOST_CTRL_MAX_BYTES 32 + +#define ATH_SPI_HOST_CTRL_CONFIG_REG (0x0700) /* internal */ +#define ATH_SPI_HOST_CTRL_CONFIG_ENABLE (1 << 15) +#define ATH_SPI_HOST_CTRL_CONFIG_DIR_WRITE (1 << 14) + +#define ATH_SPI_HOST_CTRL_RD_PORT_REG (0x0800) /* internal */ +#define ATH_SPI_HOST_CTRL_WR_PORT_REG (0x0A00) /* internal */ + +#define ATH_SPI_INTR_CAUSE_REG (0x0C00) /* internal */ +#define ATH_SPI_INTR_ENABLE_REG (0x0D00) /* internal */ +#define ATH_SPI_INTR_WRBUF_BELOW_WMARK (1 << 10) +#define ATH_SPI_INTR_HOST_CTRL_RD_DONE (1 << 9) +#define ATH_SPI_INTR_HOST_CTRL_WR_DONE (1 << 8) +#define ATH_SPI_INTR_HOST_CTRL_ACCESS_DONE (ATH_SPI_INTR_HOST_CTRL_RD_DONE | ATH_SPI_INTR_HOST_CTRL_WR_DONE) + +#define ATH_SPI_INTR_CPU_INTR (1 << 7) +#define ATH_SPI_INTR_CPU_ON (1 << 6) +#define ATH_SPI_INTR_COUNTER_INTR (1 << 5) +#define ATH_SPI_INTR_LOCAL_CPU_INTR (1 << 4) +#define ATH_SPI_INTR_ADDRESS_ERROR (1 << 3) +#define ATH_SPI_INTR_WRBUF_ERROR (1 << 2) +#define ATH_SPI_INTR_RDBUF_ERROR (1 << 1) +#define ATH_SPI_INTR_PKT_AVAIL (1 << 0) + +#define ATH_SPI_RDBUF_WATERMARK_REG (0x1200) +#define ATH_SPI_RDBUF_WATERMARK_MAX 0x0FFF +#define ATH_SPI_WRBUF_WATERMARK_REG (0x1300) + +#define ATH_SPI_WRBUF_WRPTR_REG (0x0E00) /* internal */ +#define ATH_SPI_WRBUF_RDPTR_REG (0x0F00) /* internal */ +#define ATH_SPI_RDBUF_WRPTR_REG (0x1000) /* internal */ +#define ATH_SPI_RDBUF_RDPTR_REG (0x1100) /* internal */ + +#define ATH_SPI_WRBUF_RSVD_BYTES \ + 5 /* the SPI write buffer also contains 4 bytes \ + for mailbox and length, these bytes must be \ + taken into account when the write space is checked */ + +/* the 4-byte look ahead is split into 2 registers */ +#define ATH_SPI_RDBUF_LOOKAHEAD1_REG (0x1400) +#define ATH_SPI_GET_LOOKAHEAD1_BYTE_0(word) ((UINT8)((word) >> 8)) +#define ATH_SPI_GET_LOOKAHEAD1_BYTE_1(word) ((UINT8)(word)) +#define ATH_SPI_RDBUF_LOOKAHEAD2_REG (0x1500) +#define ATH_SPI_GET_LOOKAHEAD2_BYTE_3(word) ((UINT8)((word) >> 8)) +#define ATH_SPI_GET_LOOKAHEAD2_BYTE_4(word) ((UINT8)(word)) + +/* get/set clock, takes an UINT32 parameter */ +#define ATH_SPI_CONFIG_SET_CLOCK (SDCONFIG_PUT_HOST_CUSTOM + 2) +#define ATH_SPI_CONFIG_GET_CLOCK (SDCONFIG_GET_HOST_CUSTOM + 2) + +/* for testing purposes, set the DMA data frame width + * takes a UINT8 paramter with data size */ +#define ATH_SPI_CONFIG_SET_DMA_DATA_WIDTH (SDCONFIG_PUT_HOST_CUSTOM + 3) + +/* for testing purposes, set the host access data frame width + * takes a UINT8 paramter with data size */ +#define ATH_SPI_CONFIG_SET_HOST_ACCESS_DATA_WIDTH (SDCONFIG_PUT_HOST_CUSTOM + 4) + +/* for testing purposes dump the SPI registers, takes no data */ +#define ATH_SPI_CONFIG_DUMP_SPI_INTERNAL_REGISTERS (SDCONFIG_PUT_HOST_CUSTOM + 5) + +/* turn on/off the power of the SPI bus */ +#define ATH_SPI_CONFIG_SET_POWER (SDCONFIG_PUT_HOST_CUSTOM + 6) + +/* function driver IRQ sources */ +#define ATH_SPI_FUNC_DRIVER_IRQ_SOURCES (ATH_SPI_INTR_CPU_INTR | ATH_SPI_INTR_PKT_AVAIL) + +/* host driver error IRQs */ +#define ATH_SPI_HCD_ERROR_IRQS (ATH_SPI_INTR_ADDRESS_ERROR | ATH_SPI_INTR_WRBUF_ERROR | ATH_SPI_INTR_RDBUF_ERROR) +/* host driver IRQ sources */ +#define ATH_SPI_HCD_IRQ_SOURCES (ATH_SPI_INTR_WRBUF_BELOW_WMARK | ATH_SPI_HCD_ERROR_IRQS) + +#define AR4XXX_MAX_SPI_CLOCK_RATE 48000000 +#define AR4XXX_NORMAL_CLOCK_RATE 24000000 +#define AR4XXX_WRITE_BUFFER_SIZE 3163 +#endif /* __RAW_SPI_HCD_IF_H___ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/wlan_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/wlan_api.h new file mode 100644 index 00000000000..d88505594a7 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/wlan_api.h @@ -0,0 +1,83 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _HOST_WLAN_API_H_ +#define _HOST_WLAN_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "platform/mbed_wait_api.h" + +#define DRIVER_INSERT(pCxt) A_OK +#define DRIVER_REMOVE(pCxt) + +A_STATUS Driver_WaitForCondition(void *pCxt, volatile boolean *pCond, boolean value, uint32_t msec); +#define DRIVER_WAIT_FOR_CONDITION(pCxt, pC, v, ms) Driver_WaitForCondition((pCxt), (pC), (v), (ms)) +#define WAIT_FOR_WMI_RESPONSE(pCxt) + +#define API_TXCOMPLETE(pCxt, pReq) \ + UNUSED_ARGUMENT((pCxt)); \ + UNUSED_ARGUMENT((pReq)); + +#define API_TARGET_STATS_EVENT(pCxt, ptr, len) Driver_WakeUser((pCxt)) + +#define API_REGDOMAIN_EVENT(pCxt, regCode) + +#define API_BITRATE_EVENT(pCxt, rateKbps) Driver_WakeUser((pCxt)) +#define API_CHANNEL_LIST_EVENT(pCxt, numChan, chanList) Driver_WakeUser((pCxt)) +#define API_SCAN_COMPLETE_EVENT(pCxt, status) Driver_WakeUser((pCxt)) +#define API_GET_PMK_EVENT(pCxt, datap) Driver_WakeUser((pCxt)) +#define API_STORE_RECALL_EVENT(pCxt) Driver_WakeUser((pCxt)) +#define API_WPS_PROFILE_EVENT(pCxt, datap, len, pReq) Driver_WakeUser((pCxt)) +#define API_GET_TEMPERATURE_REPLY(pCxt, datap, len) Driver_WakeUser((pCxt)) +#define API_SET_PARAM_REPLY_EVENT(pCxt) Driver_WakeUser((pCxt)) +#define API_GET_COUNTRY_CODE_REPLY(pCxt, datap, len) Driver_WakeUser((pCxt)) +#define API_WPS_INIT_REPLY(pCxt, datap, len) Driver_WakeUser((pCxt)) + +#define API_TKIP_MIC_ERROR_EVENT(pCxt, keyid, ismcast) +#define API_AGGR_RECV_ADDBA_REQ_EVENT(pCxt, evt) +#define API_AGGR_RECV_DELBA_REQ_EVENT(pCxt, evt) +#define API_WMIX_DBGLOG_EVENT(wmip, datap, len) + +// The best resolution we have is 1 millisecond so there is no microsecond delay. +// To avoid OSA_TimeDelay() delaying for 0ms, we add 1 millisecond +/* TODO: move to env layer !!*/ +#define HW_USEC_DELAY(pCxt, usec) wait_us(usec) + +void HW_SetClock(void *pCxt, uint32_t *pClockRate); +#define HW_SET_CLOCK(pCxt, pClockRate) HW_SetClock((pCxt), (pClockRate)) + +#define A_WMI_EVENT(evt, pCxt, datap, len, osbuf) A_ERROR + +uint16_t wlan_ieee2freq(int chan); +uint32_t wlan_freq2ieee(uint16_t freq); + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_WLAN_API_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/wmi_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/wmi_api.h new file mode 100644 index 00000000000..110891c4407 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/include/wmi_api.h @@ -0,0 +1,155 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _WMI_API_H_ +#define _WMI_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* WMI converts a dix frame with an ethernet payload (up to 1500 bytes) + * to an 802.3 frame (adds SNAP header) and adds on a WMI data header */ +#define WMI_MAX_TX_DATA_FRAME_LENGTH \ + (1500 + sizeof(WMI_DATA_HDR) + WMI_MAX_TX_META_SZ + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR)) + +/* A normal WMI data frame */ +#define WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH \ + (1500 + HTC_HEADER_LEN + sizeof(WMI_DATA_HDR) + WMI_MAX_RX_META_SZ + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR)) + +/* An AMSDU frame */ +#define WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH \ + (4096 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR)) + +/* + * IP QoS Field definitions according to 802.1p + */ +#define BEST_EFFORT_PRI 0 +#define BACKGROUND_PRI 1 +#define EXCELLENT_EFFORT_PRI 3 +#define CONTROLLED_LOAD_PRI 4 +#define VIDEO_PRI 5 +#define VOICE_PRI 6 +#define NETWORK_CONTROL_PRI 7 +#define MAX_NUM_PRI 8 + +#define UNDEFINED_PRI (0xff) + +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */ + +#define A_ROUND_UP(x, y) ((((x) + ((y)-1)) / (y)) * (y)) + +typedef enum +{ + ATHEROS_COMPLIANCE = 0x1 +} TSPEC_PARAM_COMPLIANCE; + +struct wmi_t; + +void *wmi_init(void *devt); + +void wmi_qos_state_init(struct wmi_t *wmip); +void wmi_shutdown(struct wmi_t *wmip); +HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t *wmip); +void wmi_set_control_ep(struct wmi_t *wmip, HTC_ENDPOINT_ID eid); +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_meta_add(struct wmi_t *wmip, void *osbuf, uint8_t *pVersion, void *pTxMetaS); +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, + void *osbuf, + uint8_t msgType, + boolean bMoreData, + WMI_DATA_HDR_DATA_TYPE data_type, + uint8_t metaVersion, + void *pTxMetaS); +A_STATUS wmi_dot3_2_dix(void *osbuf); + +A_STATUS wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode); + +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf); + +uint8_t wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, uint32_t layer2Priority, boolean wmmEnabled); + +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf); + +typedef enum +{ + NO_SYNC_WMIFLAG = 0, + SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */ + SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */ + SYNC_BOTH_WMIFLAG, + END_WMIFLAG /* end marker */ +} WMI_SYNC_FLAG; + +A_STATUS +wmi_cmd_start(struct wmi_t *wmip, const void *pInput, WMI_COMMAND_ID cmdID, uint16_t buffsize); + +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, WMI_SYNC_FLAG flag); + +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, uint8_t filter, uint32_t ieMask); + +#if WLAN_CONFIG_ENABLE_WMI_SYNC +A_STATUS wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid); +#endif + +A_STATUS +wmi_storerecall_recall_cmd(struct wmi_t *wmip, uint32_t length, void *pData); + +A_STATUS wmi_socket_cmd(struct wmi_t *wmip, uint32_t cmd_type, void *pData, uint32_t length); + +#if ENABLE_P2P_MODE +void wmi_save_key_info(WMI_P2P_PROV_INFO *p2p_info); + +void p2p_go_neg_complete_rx(void *ctx, const uint8_t *datap, uint8_t len); + +A_STATUS +wmi_p2p_set_noa(struct wmi_t *wmip, WMI_NOA_INFO_STRUCT *buf); + +A_STATUS +wmi_p2p_set_oppps(struct wmi_t *wmip, WMI_OPPPS_INFO_STRUCT *pOpp); + +A_STATUS wmi_sdpd_send_cmd(struct wmi_t *wmip, WMI_P2P_SDPD_TX_CMD *buf); +#endif + +#if ENABLE_AP_MODE +A_STATUS +wmi_ap_set_param(struct wmi_t *wmip, void *data); +#endif + +A_STATUS wmi_reverse_credit_cmd(void *handle, boolean enable, uint8_t *endpoints, uint8_t *credits); +A_STATUS wmi_rcv_data_classifier_cmd(void *handle, + uint8_t offset, + uint8_t shift, + uint32_t mask, + uint8_t count, + uint32_t *class_mapping, + uint8_t *ep_mapping); +A_STATUS wmi_update_reverse_credits_cmd(void *handle, uint8_t endpoint, uint32_t nCredits); +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, void *data); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_API_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_api.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_api.c new file mode 100644 index 00000000000..ae882eb53e3 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_api.c @@ -0,0 +1,2905 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if ENABLE_P2P_MODE +#include +#include "p2p.h" +#endif +#include "atheros_wifi.h" +#include "atheros_wifi_api.h" +#include "atheros_wifi_internal.h" +#include "atheros_stack_offload.h" +#include "dset_api.h" +#include "common_stack_offload.h" +#include "qcom_api.h" +//------------------------------------------------------------------------------------------------------------ +qcom_wps_credentials_t gWpsCredentials; + +//------------------------------------------------------------------------------------------------------------ + +A_STATUS custom_qapi(uint8_t device_id, uint32_t cmd, void *param); +void *Custom_Api_GetDriverCxt(uint8_t device_id); + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : qcom_set_deviceid() +* Returned Value : A_ERROR is command failed, else A_OK +* Comments : Sets device ID in driver context +* +*END*-----------------------------------------------------------------*/ +A_STATUS qcom_set_deviceid(uint16_t id) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + + inout_param.cmd_id = ATH_SET_DEVICE_ID; + inout_param.data = (void *)&id; + inout_param.length = sizeof(uint16_t); + + return (custom_qapi(id, ATH_SET_DEVICE_ID, &inout_param)); +} + +#if 0 +static enum p2p_wps_method qcom_p2p_get_wps(P2P_WPS_METHOD wps) +{ + switch (wps) { + case P2P_WPS_NOT_READY: + return WPS_NOT_READY; + case P2P_WPS_PIN_LABEL: + return WPS_PIN_LABEL; + case P2P_WPS_PIN_DISPLAY: + return WPS_PIN_DISPLAY; + case P2P_WPS_PIN_KEYPAD: + return WPS_PIN_KEYPAD; + case P2P_WPS_PBC: + return WPS_PBC; + default: + return WPS_NOT_READY; + } +} +#endif + +//------------------------------------------------------------------------------------------------------------ + +#if ENABLE_STACK_OFFLOAD + +int qcom_socket(int family, int type, int protocol) +{ + return (t_socket(Custom_Api_GetDriverCxt(0), family, type, protocol)); +} + +int qcom_connect(int s, struct sockaddr *addr, int addrlen) +{ + return (t_connect(Custom_Api_GetDriverCxt(0), s, addr, addrlen)); +} + +int qcom_bind(int s, struct sockaddr *addr, int addrlen) +{ + return (t_bind(Custom_Api_GetDriverCxt(0), s, addr, addrlen)); +} + +int qcom_listen(int s, int backlog) +{ + return (t_listen(Custom_Api_GetDriverCxt(0), s, backlog)); +} + +int qcom_accept(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + return (t_accept(Custom_Api_GetDriverCxt(0), s, addr, *addrlen)); +} + +int qcom_setsockopt(int s, int level, int name, void *arg, int arglen) +{ + return (t_setsockopt(Custom_Api_GetDriverCxt(0), s, level, name, arg, arglen)); +} + +int qcom_getsockopt(int s, int level, int name, void *arg, int arglen) +{ + return (t_getsockopt(Custom_Api_GetDriverCxt(0), s, level, name, arg, arglen)); +} + +#if ZERO_COPY +int qcom_recv(int s, char **buf, int len, int flags) +#else +int qcom_recv(int s, char *buf, int len, int flags) +#endif +{ + return (t_recv(Custom_Api_GetDriverCxt(0), s, (void *)buf, len, flags)); +} + +#if ZERO_COPY +int qcom_recvfrom(int s, char **buf, int len, int flags, struct sockaddr *from, socklen_t *fromlen) +#else +int qcom_recvfrom(int s, char *buf, int len, int flags, struct sockaddr *from, socklen_t *fromlen) +#endif +{ + return (t_recvfrom(Custom_Api_GetDriverCxt(0), s, (void *)buf, len, flags, from, (socklen_t*)fromlen)); +} + +#if ENABLE_DNS_CLIENT +A_STATUS qcom_dnsc_enable(boolean enable) +{ + return ((A_STATUS)custom_ip_dns_client(Custom_Api_GetDriverCxt(0), enable)); +} + +A_STATUS qcom_dnsc_add_server_address(uint8_t *ipaddress, uint8_t type) +{ + IP46ADDR dnsaddr; + + memset(&dnsaddr, 0, sizeof(IP46ADDR)); + if (type == ATH_AF_INET) + { + dnsaddr.type = ATH_AF_INET; + dnsaddr.addr4 = (uint32_t) * (uint32_t *)ipaddress; + } + else + { + dnsaddr.type = ATH_AF_INET6; + memcpy(&dnsaddr.addr6, ipaddress, sizeof(IP6_ADDR_T)); + } + + return ((A_STATUS)custom_ip_dns_server_addr(Custom_Api_GetDriverCxt(0), &dnsaddr)); +} + +A_STATUS qcom_dnsc_del_server_address(uint8_t *ipaddress, uint8_t type) +{ + IP46ADDR dnsaddr; +#define DELETE_DNS_SERVER_ADDR 1 + + memset(&dnsaddr, 0, sizeof(IP46ADDR)); + dnsaddr.au1Rsvd[0] = DELETE_DNS_SERVER_ADDR; + if (type == ATH_AF_INET) + { + dnsaddr.type = ATH_AF_INET; + dnsaddr.addr4 = (uint32_t) * (uint32_t *)ipaddress; + } + else + { + dnsaddr.type = ATH_AF_INET6; + memcpy(&dnsaddr.addr6, ipaddress, sizeof(IP6_ADDR_T)); + } + + return ((A_STATUS)custom_ip_dns_server_addr(Custom_Api_GetDriverCxt(0), &dnsaddr)); +} + +A_STATUS qcom_dnsc_get_host_by_name(char *pname, uint32_t *pipaddress) +{ + DNC_CFG_CMD DnsCfg; + DNC_RESP_INFO DnsRespInfo; + + memset(&DnsRespInfo, 0, sizeof(DnsRespInfo)); + strcpy((char *)DnsCfg.ahostname, pname); + DnsCfg.domain = 2; + DnsCfg.mode = GETHOSTBYNAME; + if (A_OK != custom_ip_resolve_hostname(Custom_Api_GetDriverCxt(0), &DnsCfg, &DnsRespInfo)) + { + return A_ERROR; + } + *pipaddress = A_CPU2BE32(DnsRespInfo.ipaddrs_list[0]); + return A_OK; +} + +A_STATUS qcom_dnsc_get_host_by_name2(char *pname, uint32_t *pipaddress, int32_t domain, uint32_t mode) +{ + DNC_CFG_CMD DnsCfg; + DNC_RESP_INFO DnsRespInfo; + + memset(&DnsRespInfo, 0, sizeof(DnsRespInfo)); + strcpy((char *)DnsCfg.ahostname, pname); + DnsCfg.domain = domain; + DnsCfg.mode = mode; + if (A_OK != custom_ip_resolve_hostname(Custom_Api_GetDriverCxt(0), &DnsCfg, &DnsRespInfo)) + { + return A_ERROR; + } + + if (domain == 3) + memcpy(pipaddress, (void*)&DnsRespInfo.ip6addrs_list[0], 16); + else + memcpy(pipaddress, (void*)&DnsRespInfo.ipaddrs_list[0], 4); + return A_OK; +} + +#endif +#if ENABLE_DNS_SERVER +A_STATUS qcom_dns_server_address_get(uint32_t pdns[], uint32_t *number) +{ + int i; + A_STATUS error; + IP46ADDR dnsaddr[MAX_DNSADDRS]; + + memset(&dnsaddr[0], 0, sizeof(dnsaddr)); + error = t_ipconfig(Custom_Api_GetDriverCxt(0), IPCFG_QUERY, NULL, NULL, NULL, dnsaddr, NULL); + *number = 0; + + if (error == A_OK) + { + for (i = 0; i < MAX_DNSADDRS; i++) + { + if (dnsaddr[i].addr4 != 0) + { + pdns[i] = A_CPU2BE32(dnsaddr[i].addr4); + *number = *number + 1; + } + else + { + break; + } + } + } + + return error; +} + +A_STATUS qcom_dnss_enable(boolean enable) +{ + return ((A_STATUS)custom_ip_dns_server(Custom_Api_GetDriverCxt(0), (uint32_t)enable)); +} + +A_STATUS qcom_dns_local_domain(char *local_domain) +{ + return ((A_STATUS)custom_ip_dns_local_domain(Custom_Api_GetDriverCxt(0), local_domain)); +} + +A_STATUS qcom_dns_entry_create(char *hostname, uint32_t ipaddress) +{ + IP46ADDR dnsaddr = {0}; + dnsaddr.type = ATH_AF_INET; + dnsaddr.addr4 = ipaddress; + return ((A_STATUS)custom_ipdns(Custom_Api_GetDriverCxt(0), 1, hostname, &dnsaddr)); +} + +A_STATUS qcom_dns_entry_delete(char *hostname, uint32_t ipaddress) +{ + IP46ADDR dnsaddr = {0}; + dnsaddr.type = ATH_AF_INET; + dnsaddr.addr4 = ipaddress; + return ((A_STATUS)custom_ipdns(Custom_Api_GetDriverCxt(0), 2, hostname, &dnsaddr)); +} + +A_STATUS qcom_dns_6entry_create(char *hostname, IP6_ADDR_T *ip6addr) +{ + IP46ADDR dnsaddr = {0}; + dnsaddr.type = ATH_AF_INET6; + memcpy(&dnsaddr.addr6, ip6addr, sizeof(dnsaddr.addr6)); + return ((A_STATUS)custom_ipdns(Custom_Api_GetDriverCxt(0), 1, hostname, &dnsaddr)); +} + +A_STATUS qcom_dns_6entry_delete(char *hostname, IP6_ADDR_T *ip6addr) +{ + IP46ADDR dnsaddr = {0}; + dnsaddr.type = ATH_AF_INET6; + memcpy(&dnsaddr.addr6, ip6addr, sizeof(dnsaddr.addr6)); + return ((A_STATUS)custom_ipdns(Custom_Api_GetDriverCxt(0), 2, hostname, &dnsaddr)); +} + +#endif + +#if ENABLE_SNTP_CLIENT +void qcom_sntp_srvr_addr(int flag, char *srv_addr) +{ + custom_ip_sntp_srvr_addr(Custom_Api_GetDriverCxt(0), flag, srv_addr); +} + +void qcom_sntp_get_time(uint8_t device_id, tSntpTime *time) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return; + } + custom_ip_sntp_get_time(Custom_Api_GetDriverCxt(device_id), time); +} + +void qcom_sntp_get_time_of_day(uint8_t device_id, tSntpTM *time) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return; + } + custom_ip_sntp_get_time_of_day(Custom_Api_GetDriverCxt(device_id), time); +} +void qcom_sntp_zone(int hour, int min, int add_sub, int enable) +{ + custom_ip_sntp_modify_zone_dse(Custom_Api_GetDriverCxt(0), hour, min, add_sub, enable); +} + +void qcom_sntp_query_srvr_address(uint8_t device_id, tSntpDnsAddr *addr) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return; + } + custom_ip_sntp_query_srvr_address(Custom_Api_GetDriverCxt(device_id), addr); +} + +void qcom_enable_sntp_client(int enable) +{ + custom_ip_sntp_client(Custom_Api_GetDriverCxt(0), enable); +} + +#endif + +/****************QCOM_OTA_APIs************************/ + +A_STATUS qcom_ota_upgrade(uint8_t device_id, + uint32_t addr, + char *filename, + uint8_t mode, + uint8_t preserve_last, + uint8_t protocol, + uint32_t *resp_code, + uint32_t *length) +{ + return ((A_STATUS)custom_ota_upgrade(Custom_Api_GetDriverCxt(device_id), addr, filename, mode, preserve_last, + protocol, resp_code, length)); +} + +A_STATUS qcom_ota_read_area(uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *retlen) +{ + return ((A_STATUS)custom_ota_read_area(Custom_Api_GetDriverCxt(0), offset, size, buffer, retlen)); +} + +A_STATUS qcom_ota_done(boolean good_image) +{ + return ((A_STATUS)custom_ota_done(Custom_Api_GetDriverCxt(0), good_image)); +} + +QCOM_OTA_STATUS_CODE_t qcom_ota_session_start(uint32_t flags, uint32_t partition_index) +{ + return ((QCOM_OTA_STATUS_CODE_t)custom_ota_session_start(Custom_Api_GetDriverCxt(0), flags, partition_index)); +} + +uint32_t qcom_ota_partition_get_size(void) +{ + return (custom_ota_partition_get_size(Custom_Api_GetDriverCxt(0))); +} + +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_erase(void) +{ + return ((QCOM_OTA_STATUS_CODE_t)custom_ota_partition_erase(Custom_Api_GetDriverCxt(0))); +} + +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_verify_checksum(void) +{ + return ((QCOM_OTA_STATUS_CODE_t)custom_ota_partition_verify_checksum(Custom_Api_GetDriverCxt(0))); +} + +QCOM_OTA_STATUS_CODE_t qcom_ota_parse_image_hdr(uint8_t *header, uint32_t *offset) +{ + return ((QCOM_OTA_STATUS_CODE_t)custom_ota_parse_image_hdr(Custom_Api_GetDriverCxt(0), header, offset)); +} + +uint32_t qcom_ota_partition_read_data(uint32_t offset, uint8_t *buf, uint32_t size) +{ + uint32_t rtn_len = 0; + if (qcom_ota_read_area(offset, size, buf, &rtn_len) != A_OK) + { + if (rtn_len > 0) + { + rtn_len = rtn_len; + } + } + return (rtn_len); +} + +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_write_data(uint32_t offset, uint8_t *buf, uint32_t size, uint32_t *ret_size) +{ + return ((QCOM_OTA_STATUS_CODE_t)custom_ota_partition_write_data(Custom_Api_GetDriverCxt(0), offset, buf, size, + ret_size)); +} + +QCOM_OTA_STATUS_CODE_t qcom_ota_session_end(uint32_t good_image) +{ + return (QCOM_OTA_STATUS_CODE_t)qcom_ota_done(good_image); +} + +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_format(uint32_t partition_index) +{ + QCOM_OTA_STATUS_CODE_t rtn; + + if (partition_index == 0) + return QCOM_OTA_ERR_INVALID_PARTITION_INDEX; + + if ((rtn = qcom_ota_session_start(QCOM_OTA_ERASING_RW_DSET, partition_index)) == QCOM_OTA_OK) + { + rtn = (QCOM_OTA_STATUS_CODE_t)qcom_ota_partition_erase(); + qcom_ota_session_end(0); + } + return rtn; +} + +A_STATUS qcom_ota_set_callback(void *callback) +{ + return ((A_STATUS)custom_ota_set_response_cb(Custom_Api_GetDriverCxt(0), callback)); +} + +int qcom_sendto(int s, char *buffer, int length, int flags, struct sockaddr *to, int tolen) +{ + return (t_sendto(Custom_Api_GetDriverCxt(0), s, (uint8_t *)buffer, length, flags, to, tolen)); +} + +int qcom_send(int s, char *buffer, int length, int flags) +{ + return (t_send(Custom_Api_GetDriverCxt(0), s, (uint8_t *)buffer, length, flags)); +} + +int qcom_socket_close(int s) +{ + return (t_shutdown(Custom_Api_GetDriverCxt(0), s)); +} + +A_STATUS qcom_ipconfig(uint8_t device_id, QCOM_IPCONFIG_MODE mode, uint32_t *address, uint32_t *submask, uint32_t *gateway) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (t_ipconfig(Custom_Api_GetDriverCxt(device_id), mode, address, submask, gateway, NULL, NULL)); +} + +A_STATUS qcom_ip6_address_get(uint8_t device_id, + IP6_ADDR_T *v6Global, + IP6_ADDR_T *v6Link, + IP6_ADDR_T *v6DefGw, + IP6_ADDR_T *v6GlobalExtd, + int32_t *LinkPrefix, + int32_t *GlbPrefix, + int32_t *DefgwPrefix, + int32_t *GlbPrefixExtd) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (t_ip6config(Custom_Api_GetDriverCxt(device_id), IPCFG_QUERY, (IP6_ADDR_T *)v6Global, (IP6_ADDR_T *)v6Link, + (IP6_ADDR_T *)v6DefGw, (IP6_ADDR_T *)v6GlobalExtd, LinkPrefix, GlbPrefix, DefgwPrefix, + GlbPrefixExtd)); +} + +A_STATUS qcom_ping(uint32_t host, uint32_t size) +{ + return (t_ping(Custom_Api_GetDriverCxt(0), host, size, COMMAND_BLOCK_TIMEOUT)); +} + +A_STATUS qcom_ping_ms(uint32_t host, uint32_t size, uint32_t ms_interval) +{ + return (t_ping(Custom_Api_GetDriverCxt(0), host, size, ms_interval)); +} + +A_STATUS qcom_ping6(uint8_t *host, uint32_t size) +{ + return (t_ping6(Custom_Api_GetDriverCxt(0), host, size, COMMAND_BLOCK_TIMEOUT)); +} + +A_STATUS qcom_ping6_ms(uint8_t *host, uint32_t size, uint32_t ms_interval) +{ + return (t_ping6(Custom_Api_GetDriverCxt(0), host, size, ms_interval)); +} + +A_STATUS qcom_ip6config_router_prefix( + uint8_t device_id, IP6_ADDR_T *addr, int32_t prefixlen, int32_t prefix_lifetime, int32_t valid_lifetime) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (t_ip6config_router_prefix(Custom_Api_GetDriverCxt(0), addr, prefixlen, prefix_lifetime, valid_lifetime)); +} + +A_STATUS qcom_bridge_mode_enable(uint16_t bridgemode) +{ + return (custom_ipbridgemode(Custom_Api_GetDriverCxt(0), bridgemode)); +} + +A_STATUS qcom_tcp_set_exp_backoff(uint8_t device_id, int32_t retry) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (custom_ipconfig_set_tcp_exponential_backoff_retry(Custom_Api_GetDriverCxt(device_id), retry)); +} + +#if ENABLE_ROUTING_CMDS +A_STATUS qcom_ip4_route(uint8_t device_id, + uint32_t cmd, + IP_ADDR_T *addr, + IP_ADDR_T *subnet, + IP_ADDR_T *gw, + uint32_t *ifindex, + IPV4_ROUTE_LIST_T *rtlist) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (custom_ipv4_route(Custom_Api_GetDriverCxt(device_id), cmd, addr, subnet, gw, ifindex, rtlist)); +} + +A_STATUS qcom_ip6_route(uint8_t device_id, + uint32_t cmd, + IP6_ADDR_T *ip6addr, + uint32_t *prefixLen, + IP6_ADDR_T *gw, + uint32_t *ifindex, + IPV6_ROUTE_LIST_T *rtlist) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (custom_ipv6_route(Custom_Api_GetDriverCxt(device_id), cmd, ip6addr, prefixLen, gw, ifindex, rtlist)); +} + +#endif + +A_STATUS qcom_tcp_conn_timeout(uint32_t timeout_val) +{ + return (custom_tcp_connection_timeout(Custom_Api_GetDriverCxt(0), timeout_val)); +} + +int32_t qcom_dhcps_set_pool(uint8_t device_id, uint32_t startip, uint32_t endip, int32_t leasetime) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (t_ipconfig_dhcp_pool(Custom_Api_GetDriverCxt(device_id), &startip, &endip, leasetime)); +} + +int32_t qcom_dhcps_register_cb(uint8_t device_id, void *callback) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (t_ipconfig_dhcps_cb_enable(Custom_Api_GetDriverCxt(device_id), callback)); +} + +int32_t qcom_dhcpc_register_cb(uint8_t device_id, void *callback) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (t_ipconfig_dhcpc_cb_enable(Custom_Api_GetDriverCxt(device_id), callback)); +} + +A_STATUS qcom_dhcps_release_pool(uint8_t device_id) +{ + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + return (custom_ipconfig_dhcp_release(Custom_Api_GetDriverCxt(device_id))); +} + +A_STATUS qcom_http_server(int32_t enable) +{ + return (custom_ip_http_server(Custom_Api_GetDriverCxt(0), enable)); +} + +A_STATUS qcom_http_set_post_cb(void *cxt, void *callback) +{ + if (callback == NULL) + { + return A_ERROR; + } + return ((A_STATUS)custom_http_set_post_cb(Custom_Api_GetDriverCxt(0), cxt, callback)); +} + +A_STATUS qcom_ip_http_server_method( + int32_t cmd, uint8_t *pagename, uint8_t *objname, int32_t objtype, int32_t objlen, uint8_t *value) +{ + return (custom_ip_http_server_method(Custom_Api_GetDriverCxt(0), cmd, pagename, objname, objtype, objlen, value)); +} + +#if ENABLE_HTTP_CLIENT +A_STATUS qcom_http_client_method(uint32_t cmd, uint8_t *url, uint8_t *data, uint8_t *value) +{ + HTTPC_RESPONSE *output = NULL; + A_STATUS result = A_OK; + + if (NULL == value) + { + // for HTTPC_CONNECT or HTTPC_DISC + result = custom_httpc_method(Custom_Api_GetDriverCxt(0), cmd, url, data, NULL); + } + else + { + result = custom_httpc_method(Custom_Api_GetDriverCxt(0), cmd, url, data, (uint8_t **)&output); + } + + if (result == A_OK) + { + if (output && value) + { + A_MEMCPY(value, output, sizeof(HTTPC_RESPONSE) + output->length - 1); + zero_copy_http_free((void *)output); + } + } + + return result; +} +#endif + +#if ENABLE_SSL +SSL_CTX *qcom_SSL_ctx_new(SSL_ROLE_T role, int32_t inbufSize, int32_t outbufSize, int32_t reserved) +{ + return ((SSL_CTX *)SSL_ctx_new(role, inbufSize, outbufSize, reserved)); +} + +int32_t qcom_SSL_ctx_free(SSL_CTX *ctx) +{ + return (SSL_ctx_free(ctx)); +} + +SSL *qcom_SSL_new(SSL_CTX *ctx) +{ + return ((SSL *)SSL_new(ctx)); +} + +int32_t qcom_SSL_setCaList(SSL_CTX *ctx, SslCAList caList, uint32_t size) +{ + return (SSL_setCaList(ctx, caList, size)); +} + +int32_t qcom_SSL_addCert(SSL_CTX *ctx, SslCert cert, uint32_t size) +{ + return (SSL_addCert(ctx, cert, size)); +} + +int32_t qcom_SSL_storeCert(char *name, SslCert cert, uint32_t size) +{ + return (SSL_storeCert(name, cert, size)); +} +int32_t qcom_SSL_loadCert(SSL_CTX *ctx, SSL_CERT_TYPE_T type, char *name) +{ + return (SSL_loadCert(ctx, type, name)); +} + +int32_t qcom_SSL_listCert(SSL_FILE_NAME_LIST *fileNames) +{ + return (SSL_listCert(fileNames)); +} + +int32_t qcom_SSL_set_fd(SSL *ssl, uint32_t fd) +{ + return (SSL_set_fd(ssl, fd)); +} + +int32_t qcom_SSL_accept(SSL *ssl) +{ + return (SSL_accept(ssl)); +} + +int32_t qcom_SSL_connect(SSL *ssl) +{ + return (SSL_connect(ssl)); +} + +int32_t qcom_SSL_shutdown(SSL *ssl) +{ + return (SSL_shutdown(ssl)); +} + +int32_t qcom_SSL_configure(SSL *ssl, SSL_CONFIG *cfg) +{ + return (SSL_configure(ssl, cfg)); +} + +#if ZERO_COPY +int32_t qcom_SSL_read(SSL *ssl, void **buf, int32_t num) +#else +int32_t qcom_SSL_read(SSL *ssl, void *buf, int32_t num) +#endif +{ + return (SSL_read(ssl, buf, num)); +} +int32_t qcom_SSL_write(SSL *ssl, const void *buf, int32_t num) +{ + return (SSL_write(ssl, buf, num)); +} + +#endif // ENABLE_SSL +#endif + +/****************************************************************************************/ +A_STATUS _qcom_set_scan(uint8_t device_id, qcom_start_scan_params_t *pScanParams) +{ + uint32_t size; + WMI_START_SCAN_CMD *pStartScan; + A_STATUS error = A_OK; + uint8_t *buffer = NULL; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + if (pScanParams == NULL) + { + pStartScan = NULL; + } + else + { + size = sizeof(WMI_START_SCAN_CMD); + if (pScanParams->numChannels > 0) + { + size = size + (pScanParams->numChannels - 1) * sizeof(uint16_t); + } + + if (NULL == (buffer = A_MALLOC(size, MALLOC_ID_CONTEXT))) + { + return A_ERROR; + } + + pStartScan = (WMI_START_SCAN_CMD *)buffer; + A_MEMZERO(pStartScan, size); + pStartScan->forceFgScan = pScanParams->forceFgScan; + pStartScan->isLegacy = false; + pStartScan->homeDwellTime = pScanParams->homeDwellTimeInMs; + pStartScan->forceScanInterval = pScanParams->forceScanIntervalInMs; + pStartScan->scanType = pScanParams->scanType; + pStartScan->numChannels = pScanParams->numChannels; + A_MEMCPY((uint8_t *)pStartScan->channelList, (uint8_t *)pScanParams->channelList, + pScanParams->numChannels * sizeof(uint16_t)); + } + if (custom_qapi(device_id, ATH_SET_SCAN, (void *)pStartScan) != A_OK) + error = A_ERROR; + + if (buffer) + A_FREE(buffer, MALLOC_ID_CONTEXT); + return error; +} + +A_STATUS qcom_get_scan(uint8_t device_id, QCOM_BSS_SCAN_INFO **buf, int16_t *numResults) +{ + ATH_SCAN_LIST param = {0}; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + if (custom_qapi(device_id, ATH_GET_SCAN_RESULTS, ¶m) != A_OK) + { + return A_ERROR; + } + *buf = (QCOM_BSS_SCAN_INFO *)param.scan_list; + *numResults = param.num_scan_entries; + + return A_OK; +} + +/* NOTE: Passing NULL to pssid is not longer supported. Use empty + * string "" instead */ +A_STATUS qcom_set_ssid(uint8_t device_id, QCOM_SSID *pssid) +{ + ATH_IOCTL_PARAM_STRUCT param = {0}; + if (NULL == pssid) + { + return A_ERROR; + } + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + //TODO: check sizeof vs strlen ? + param.data = pssid; + if (A_OK != custom_qapi(device_id, ATH_SET_SSID, ¶m)) + { + return A_ERROR; + } + return A_OK; +} + +A_STATUS qcom_get_ssid(uint8_t device_id, QCOM_SSID *pssid) +{ + ATH_IOCTL_PARAM_STRUCT param = {0}; + uint32_t null_position; + if (NULL == pssid) + { + return A_ERROR; + } + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + param.data = (void *)pssid; + if (A_OK != custom_qapi(device_id, ATH_GET_ESSID, ¶m)) + { + return A_ERROR; + } + /* terminate SSID string */ + null_position = param.length < sizeof(QCOM_SSID) ? param.length : sizeof(QCOM_SSID) - 1; + pssid->ssid[null_position] = '\0'; + return A_OK; +} + +A_STATUS qcom_set_connect_callback(uint8_t device_id, void *callback) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_SET_CONNECT_STATE_CALLBACK; + inout_param.data = (void *)callback; + inout_param.length = sizeof(void *); + + if (custom_qapi(device_id, ATH_SET_CONNECT_STATE_CALLBACK, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_set_probe_req_callback(uint8_t device_id, void *callback) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_SET_PROBEREQ_CB; + inout_param.data = (void *)callback; + inout_param.length = sizeof(void *); + + if (custom_qapi(device_id, ATH_SET_PROBEREQ_CB, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_enable_probe_req_event(uint8_t device_id, uint8_t enable) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_SET_PROBEREQ_EV_ENABLE; + inout_param.data = (void *)&enable; + inout_param.length = sizeof(void *); + + if (custom_qapi(device_id, ATH_SET_PROBEREQ_EV_ENABLE, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +#if ENABLE_SCC_MODE +static A_STATUS qcom_get_concurrent_channel(uint8_t device_id, uint16_t *conc_channel) +{ + ATH_IOCTL_PARAM_STRUCT ath_param = {0}; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + ath_param.cmd_id = ATH_GET_CONC_DEV_CHANNEL; + ath_param.data = conc_channel; + + if (custom_qapi(device_id, ATH_GET_CONC_DEV_CHANNEL, &ath_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +static A_STATUS qcom_get_channelhint(uint8_t device_id, uint16_t *pchannel) +{ + ATH_IOCTL_PARAM_STRUCT inout_param = {0}; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_GET_CHANNELHINT; + inout_param.data = pchannel; + + if (custom_qapi(device_id, ATH_GET_CHANNELHINT, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +#endif + +A_STATUS qcom_commit(uint8_t device_id) +{ +#if ENABLE_SCC_MODE + uint16_t conc_channel, cur_channel; + QCOM_SSID ssid; + int num_dev = WLAN_NUM_OF_DEVICES; + + if (qcom_get_ssid(device_id, &ssid) != A_OK) + return A_ERROR; + + /*this is connect request */ + if ((strlen(ssid.ssid) != 0) && (num_dev > 1)) + { + qcom_get_channelhint(device_id, &cur_channel); + qcom_get_concurrent_channel(device_id, &conc_channel); + /* if device 1 is connected and this connect request is from device 0, + check both devices whether stay at same channel, if not, return fail due to device 1 is primary + */ + if ((conc_channel != 0) && (device_id == 0) && (conc_channel != cur_channel)) + { + return A_ERROR; + } + /* if device 0 is connected and this connect request is from device 1, + check both devices whether stay at same channel, if not, p2p_cancel is issue to device 0 because device 1 is + promary + */ + if ((conc_channel != 0) && (device_id == 1) && (conc_channel != cur_channel)) + { + qcom_set_deviceid(0); + qcom_set_channel(0, conc_channel); + A_MDELAY(50); + qcom_p2p_func_cancel(0); + A_MDELAY(500); + qcom_set_deviceid(1); + qcom_set_channel(1, cur_channel); + A_MDELAY(50); + } + } + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + return (custom_qapi(device_id, ATH_SET_COMMIT, NULL)); + +#else + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + return (custom_qapi(device_id, ATH_SET_COMMIT, NULL)); +#endif // ENABLE_SCC_MODE +} + +A_STATUS qcom_sta_get_rssi(uint8_t device_id, uint8_t *prssi) +{ + A_STATUS error = A_OK; + ATH_IOCTL_PARAM_STRUCT inout_param; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_GET_RX_RSSI; + inout_param.data = prssi; + + if (custom_qapi(device_id, ATH_GET_RX_RSSI, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +/* for hostless , the listentime is 1Tus, 1Tus = 1024 us. need to confirm the UNIT */ +A_STATUS qcom_sta_set_listen_time(uint8_t device_id, uint32_t listentime) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + inout_param.cmd_id = ATH_SET_LISTEN_INT; + inout_param.data = &listentime; + inout_param.length = 4; + + if (custom_qapi(device_id, ATH_SET_LISTEN_INT, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_ap_set_beacon_interval(uint8_t device_id, uint16_t beacon_interval) +{ + ATH_IOCTL_PARAM_STRUCT inout_param = {0}; + ATH_AP_PARAM_STRUCT ap_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_CONFIG_AP; + ap_param.cmd_subset = AP_SUB_CMD_BCON_INT; + ap_param.data = &beacon_interval; + inout_param.data = &ap_param; + + if (custom_qapi(device_id, ATH_CONFIG_AP, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_ap_hidden_mode_enable(uint8_t device_id, boolean enable) +{ + ATH_IOCTL_PARAM_STRUCT inout_param = {0}; + ATH_AP_PARAM_STRUCT ap_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + inout_param.cmd_id = ATH_CONFIG_AP; + ap_param.cmd_subset = AP_SUB_CMD_HIDDEN_FLAG; + ap_param.data = &enable; + inout_param.data = &ap_param; + + if (custom_qapi(device_id, ATH_CONFIG_AP, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +//TODO: always check return value in place of call +A_STATUS qcom_op_get_mode(uint8_t device_id, QCOM_WLAN_DEV_MODE *pmode) +{ + uint32_t inout_param = 0; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + if (custom_qapi(device_id, ATH_GET_OP_MODE, &inout_param) != A_OK) + { + return A_ERROR; + } + *pmode = (QCOM_WLAN_DEV_MODE)inout_param; + + return A_OK; +} + +A_STATUS qcom_op_set_mode(uint8_t device_id, QCOM_WLAN_DEV_MODE mode) +{ + uint32_t inout_param = 0; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param = mode; + + if (A_OK != custom_qapi(device_id, ATH_SET_OP_MODE, &inout_param)) + { + return A_ERROR; + } + + return A_OK; +} + +A_STATUS qcom_disconnect(uint8_t device_id) +{ + A_STATUS error = A_OK; + QCOM_SSID tmp_ssid = QCOM_SSID_FROM_STR(""); + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + /* set ssid to be blank string , ssid length is 0 , the fist step to disconnectl*/ + if (qcom_set_ssid(device_id, &tmp_ssid) != A_OK) + { + return A_ERROR; + } + /* a zero length ssid + a COMMIT command is interpreted as a + request from the caller to disconnect.*/ + if (qcom_commit(device_id) != A_OK) + { + return A_ERROR; + } + return error; +} + +static const char qcom_phy_mode_a[] = "a"; +static const char qcom_phy_mode_g[] = "g"; +static const char qcom_phy_mode_b[] = "b"; +static const char qcom_phy_mode_mixed[] = "mixed"; + +A_STATUS qcom_get_phy_mode(uint8_t device_id, char **pphymode) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + uint32_t value = 0; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_GET_PHY_MODE; + inout_param.data = &value; + + if (custom_qapi(device_id, ATH_GET_PHY_MODE, &inout_param) != A_OK) + { + return A_ERROR; + } + + if (*(uint32_t *)(inout_param.data) == 0x01) + { + *pphymode = (char*)qcom_phy_mode_a; + } + else if (*(uint32_t *)(inout_param.data) == 0x02) + { + *pphymode = (char*)qcom_phy_mode_g; + } + else if (*(uint32_t *)(inout_param.data) == 0x04) + { + *pphymode = (char*)qcom_phy_mode_b; + } + else + { + *pphymode = (char*)qcom_phy_mode_mixed; + } + return A_OK; +} + +A_STATUS qcom_get_country_code(uint8_t device_id, uint8_t *countryCode) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + WMI_GET_COUNTRY_CODE_REPLY para_countryCode; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + inout_param.cmd_id = ATH_GET_COUNTRY_CODE; + inout_param.data = (uint8_t *)¶_countryCode; + inout_param.length = sizeof(para_countryCode); + + if (custom_qapi(device_id, ATH_GET_COUNTRY_CODE, &inout_param) != A_OK) + { + return A_ERROR; + } + A_MEMCPY(countryCode, para_countryCode.country_code, 3); + + return A_OK; +} + +A_STATUS qcom_set_country_code(uint8_t device_id, uint8_t *countryCode) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + ATH_PROGRAM_COUNTRY_CODE_PARAM data; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + A_MEMZERO(data.countryCode, 3); + A_MEMCPY(data.countryCode, countryCode, 3); + + inout_param.cmd_id = ATH_PROGRAM_COUNTRY_CODE; + inout_param.length = sizeof(data); + inout_param.data = (uint8_t *)&data; + + if (custom_qapi(device_id, ATH_PROGRAM_COUNTRY_CODE, &inout_param) != A_OK) + { + QCADRV_PRINTF("countryCode PROGRAM ERROR: unknown driver error\n"); + return A_ERROR; + } + else + { + switch (data.result) + { + case ATH_PROGRAM_COUNTRY_CODE_RESULT_DRIVER_FAILED: + QCADRV_PRINTF("COUNTRY_CODE PROGRAM ERROR: the driver was unable to complete the request.\n"); + break; + case ATH_PROGRAM_COUNTRY_CODE_RESULT_SUCCESS: + QCADRV_PRINTF("COUNTRY_CODE PROGRAM SUCCESS.\n"); + break; + case ATH_PROGRAM_COUNTRY_CODE_RESULT_DEV_DENIED: + QCADRV_PRINTF("COUNTRY_CODE PROGRAM ERROR: the firmware failed to program the country_code.\n"); + QCADRV_PRINTF(" possibly the same COUNTRY_CODEis already programmed.\n"); + break; + case ATH_PROGRAM_COUNTRY_CODE_RESULT_DEV_FAILED: + default: + QCADRV_PRINTF("COUNTRY_CODE PROGRAM ERROR: Device unknown failure.\n"); + break; + } + } + + return A_OK; +} +A_STATUS qcom_set_phy_mode(uint8_t device_id, uint8_t phymode) +{ +#define BUF_LEN 20 + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + char p[BUF_LEN]; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + if (phymode == QCOM_11A_MODE) + strcpy(p, "a"); + else if (phymode == QCOM_11B_MODE) + strcpy(p, "b"); + else if (phymode == QCOM_11G_MODE) + strcpy(p, "g"); + else if (phymode == QCOM_11N_MODE) + strcpy(p, "n"); + else if (phymode == QCOM_HT40_MODE) + strcpy(p, "ht40"); + + inout_param.cmd_id = ATH_SET_PHY_MODE; + inout_param.data = p; + inout_param.length = strlen(p); + + if (custom_qapi(device_id, ATH_SET_PHY_MODE, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_set_channel(uint8_t device_id, uint16_t channel) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + if (channel < 1 || channel > 165) + { + return A_ERROR; + } + if (channel < 27) + { + channel = ATH_IOCTL_FREQ_1 + (channel - 1) * 5; + } + else + { + channel = (5000 + (channel * 5)); + } + + inout_param.cmd_id = ATH_SET_CHANNEL; + inout_param.data = &channel; + inout_param.length = 4; + + if (custom_qapi(device_id, ATH_SET_CHANNEL, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_get_channel(uint8_t device_id, uint16_t *pchannel) +{ + ATH_IOCTL_PARAM_STRUCT inout_param = {0}; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_GET_CHANNEL; + inout_param.data = pchannel; + + if (custom_qapi(device_id, ATH_GET_CHANNEL, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_get_tx_power(uint8_t device_id, uint32_t *pdbm) +{ + /* No command id for get tx_power */ + return A_OK; +} + +A_STATUS qcom_set_tx_power(uint8_t device_id, uint32_t dbm) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + uint8_t pdBm; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + pdBm = (uint8_t)dbm; + inout_param.cmd_id = ATH_SET_TXPWR; + inout_param.data = &pdBm; + inout_param.length = 1; // strlen(dBm); + + if (custom_qapi(device_id, ATH_SET_TXPWR, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_allow_aggr_set_tid(uint8_t device_id, uint16_t tx_allow_aggr, uint16_t rx_allow_aggr) +{ + A_STATUS error = A_OK; + ATH_SET_AGGREGATION_PARAM param; + ATH_IOCTL_PARAM_STRUCT inout_param; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + param.txTIDMask = tx_allow_aggr; + param.rxTIDMask = rx_allow_aggr; + + inout_param.cmd_id = ATH_SET_AGGREGATION; + inout_param.data = ¶m; + inout_param.length = sizeof(ATH_SET_AGGREGATION_PARAM); + if (custom_qapi(device_id, ATH_SET_AGGREGATION, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_scan_set_mode(uint8_t device_id, uint32_t mode) +{ + A_STATUS error = A_OK; + ATH_IOCTL_PARAM_STRUCT inout_param; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param.cmd_id = ATH_SCAN_CTRL; + inout_param.data = &mode; + inout_param.length = 4; + + if (custom_qapi(device_id, ATH_SCAN_CTRL, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_scan_params_set(uint8_t device_id, qcom_scan_params_t *pParam) +{ + A_STATUS error = A_OK; + ATH_IOCTL_PARAM_STRUCT inout_param; + WMI_SCAN_PARAMS_CMD scan_param; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + scan_param.fg_start_period = pParam->fgStartPeriod; + scan_param.fg_end_period = pParam->fgEndPeriod; + scan_param.bg_period = pParam->bgPeriod; + scan_param.maxact_chdwell_time = pParam->maxActChDwellTimeInMs; + scan_param.pas_chdwell_time = pParam->pasChDwellTimeInMs; + scan_param.shortScanRatio = pParam->shortScanRatio; + scan_param.scanCtrlFlags = pParam->scanCtrlFlags; + scan_param.minact_chdwell_time = pParam->minActChDwellTimeInMs; + scan_param.maxact_scan_per_ssid = pParam->maxActScanPerSsid; + scan_param.max_dfsch_act_time = pParam->maxDfsChActTimeInMs; + + inout_param.cmd_id = ATH_SET_SCAN_PARAM; + inout_param.data = &scan_param; + inout_param.length = sizeof(WMI_SCAN_PARAMS_CMD); + + if (custom_qapi(device_id, ATH_SET_SCAN_PARAM, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +/*************************************************************************************** +* QCOM SECURITY APIs +***************************************************************************************/ +/*FUNCTION*----------------------------------------------------------------- +* +* Function Name : set_wep_key +* Returned Value : A_ERROR on error else A_OK +* Comments : Store WEP key for later use. Size of Key must be 10 or 26 +* Hex characters +* +*END------------------------------------------------------------------*/ +A_STATUS qcom_sec_set_wepkey(uint8_t device_id, uint32_t keyindex, char *pkey) +{ + A_STATUS error = A_OK; + uint32_t len = strlen(pkey); + ATH_IOCTL_PARAM_STRUCT inout_param; + ATH_WEPKEYS param; + + param.defKeyIndex = keyindex; + param.keyLength = len; + param.numKeys = 1; + param.keys[0] = pkey; + + inout_param.cmd_id = ATH_SET_WEPKEY; + inout_param.data = ¶m; + inout_param.length = sizeof(ATH_WEPKEYS); + if (custom_qapi(device_id, ATH_SET_WEPKEY, &inout_param) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_sec_get_wepkey(uint8_t device_id, uint32_t keyindex, char *pkey) +{ + A_STATUS error = A_OK; + ATH_IOCTL_PARAM_STRUCT inout_param; + ATH_WEPKEYS param; + + param.defKeyIndex = keyindex; + param.numKeys = 1; + param.keys[0] = pkey; + + inout_param.cmd_id = ATH_GET_WEPKEY; + inout_param.data = ¶m; + inout_param.length = sizeof(ATH_WEPKEYS); + if (custom_qapi(device_id, ATH_GET_WEPKEY, &inout_param) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_sec_set_wepkey_index(uint8_t device_id, uint32_t keyindex) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + uint32_t param; + + param = keyindex; + + inout_param.cmd_id = ATH_SET_WEPINDEX; + inout_param.data = ¶m; + inout_param.length = sizeof(uint32_t); + if (custom_qapi(device_id, ATH_SET_WEPINDEX, &inout_param) != A_OK) + { + return A_ERROR; + } + + param = WLAN_AUTH_WEP; + return (custom_qapi(device_id, ATH_SET_SEC_TYPE, ¶m)); +} + +A_STATUS qcom_sec_get_wepkey_index(uint8_t device_id, uint32_t *pkeyindex) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + uint32_t param; + + inout_param.cmd_id = ATH_GET_WEPINDEX; + inout_param.data = ¶m; + inout_param.length = sizeof(uint32_t); + if (custom_qapi(device_id, ATH_GET_WEPINDEX, &inout_param) != A_OK) + { + return A_ERROR; + } + + *pkeyindex = param; + return A_OK; +} + +A_STATUS qcom_sec_set_auth_mode(uint8_t device_id, WLAN_AUTH_MODE mode) +{ + uint32_t inout_param = {0}; + if ((uint32_t)mode >= (uint32_t)WLAN_AUTH_INVALID) + { + return A_ERROR; + } + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + inout_param = mode; + return (custom_qapi(device_id, ATH_SET_SEC_TYPE, &inout_param)); +} + +A_STATUS qcom_sec_set_encrypt_mode(uint8_t device_id, WLAN_CRYPT_TYPE mode) +{ + cipher_t cipher_mode; + ATH_IOCTL_PARAM_STRUCT inout_param = {0}; + + /* NOTE: lower layer does not perform *any* range check !! */ + if ((uint32_t)mode >= (uint32_t)WLAN_CRYPT_INVALID) + { + return A_ERROR; + } + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + cipher_mode.ucipher = 0x1 << mode; + cipher_mode.mcipher = cipher_mode.ucipher; + inout_param.cmd_id = ATH_SET_CIPHER; + inout_param.data = &cipher_mode; + inout_param.length = sizeof(cipher_t); + + if (A_OK != custom_qapi(device_id, ATH_SET_CIPHER, &inout_param)) + { + return A_ERROR; + } + + return A_OK; +} + +A_STATUS qcom_sec_set_passphrase(uint8_t device_id, QCOM_PASSPHRASE *passphrase) +{ + ATH_IOCTL_PARAM_STRUCT param = {0}; + if (NULL == passphrase) + { + return A_ERROR; + } + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + param.data = passphrase; + param.length = strlen(passphrase->passphrase); + + if (param.length >= sizeof(QCOM_PASSPHRASE)) + { + return A_ERROR; + } + if (A_OK != custom_qapi(device_id, ATH_SET_PASSPHRASE, ¶m)) + { + return A_ERROR; + } + return A_OK; +} + +A_STATUS qcom_sec_set_pmk(uint8_t device_id, char *pmk) +{ + int j; + uint8_t val = 0; + WMI_SET_PMK_CMD cmd; + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + A_MEMZERO(cmd.pmk, WMI_PMK_LEN); + cmd.pmk_len = WMI_PMK_LEN; + + for (j = 0; j < 64; j++) + { + val = Util_Ascii2Hex(pmk[j]); + if (val == 0xff) + { + QCADRV_PRINTF("Invalid character\n"); + return A_ERROR; + } + else + { + if ((j & 1) == 0) + val <<= 4; + + cmd.pmk[j >> 1] |= val; + } + } + + inout_param.cmd_id = ATH_SET_PMK; + inout_param.data = &cmd; + inout_param.length = sizeof(cmd); + if (custom_qapi(device_id, ATH_SET_PMK, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_power_set_mode(uint8_t device_id, uint32_t powerMode, uint8_t powerModule) +{ + ATH_IOCTL_PARAM_STRUCT param; + POWER_MODE power; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + power.pwr_module = powerModule; + power.pwr_mode = powerMode; + + param.cmd_id = ATH_SET_POWER; + param.data = (void *)&power; + param.length = sizeof(POWER_MODE); + + if (custom_qapi(device_id, ATH_SET_POWER, ¶m) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_power_get_mode(uint8_t device_id, uint32_t *powerMode) +{ + uint32_t inout_param = 0; + A_STATUS error; + + error = custom_qapi(device_id, ATH_GET_POWER, &inout_param); + if (A_OK != error) + { + return A_ERROR; + } + + if (inout_param == 1) + { + *powerMode = REC_POWER; + } + else if (inout_param == 0) + { + *powerMode = MAX_PERF_POWER; + } + else + { + *powerMode = 0; + } + return error; +} + +A_STATUS qcom_suspend_enable(boolean enable) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + inout_param.cmd_id = ATH_DEVICE_SUSPEND_ENABLE; + inout_param.data = NULL; + inout_param.length = 0; + + if (custom_qapi(0, ATH_DEVICE_SUSPEND_ENABLE, &inout_param) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_suspend_start(uint32_t susp_time) +{ + uint32_t suspend_time; + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + suspend_time = susp_time; + inout_param.cmd_id = ATH_DEVICE_SUSPEND_START; + inout_param.data = &suspend_time; + inout_param.length = sizeof(uint32_t); + + if (custom_qapi(0, ATH_DEVICE_SUSPEND_START, &inout_param) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_power_set_parameters(uint8_t device_id, + uint16_t idlePeriod, + uint16_t psPollNum, + uint16_t dtimPolicy, + uint16_t tx_wakeup_policy, + uint16_t num_tx_to_wakeup, + uint16_t ps_fail_event_policy) +{ + ATH_WMI_POWER_PARAMS_CMD pm; + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + pm.idle_period = idlePeriod; + pm.pspoll_number = psPollNum; + pm.dtim_policy = dtimPolicy; + pm.tx_wakeup_policy = tx_wakeup_policy; + pm.num_tx_to_wakeup = num_tx_to_wakeup; + pm.ps_fail_event_policy = ps_fail_event_policy; + + inout_param.cmd_id = ATH_SET_PMPARAMS; + inout_param.data = ± + inout_param.length = sizeof(ATH_WMI_POWER_PARAMS_CMD); + + if (custom_qapi(device_id, ATH_SET_PMPARAMS, &inout_param) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_get_bssid(uint8_t device_id, uint8_t mac_addr[ATH_MAC_LEN]) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + inout_param.cmd_id = ATH_GET_MACADDR; + inout_param.data = mac_addr; + inout_param.length = ATH_MAC_LEN; + + if (custom_qapi(device_id, ATH_GET_MACADDR, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +/*************************************************************************************************************** +* QCOM WPS APIs +****************************************************************************************************************/ + +A_STATUS qcom_wps_start(uint8_t device_id, int connect, int use_pinmode, char *pin) +{ +#define WPS_STANDARD_TIMEOUT (30) + ATH_IOCTL_PARAM_STRUCT param; + ATH_WPS_START wps_start; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + do + { + A_MEMZERO(&wps_start, sizeof(ATH_WPS_START)); + param.cmd_id = ATH_START_WPS; + param.data = &wps_start; + param.length = sizeof(wps_start); + + wps_start.connect_flag = connect; + if (use_pinmode == 0) + { + wps_start.wps_mode = ATH_WPS_MODE_PIN; + wps_start.pin_length = strlen(pin); + // FIXME: This hardcoded pin value needs to be changed + // for production to reflect what is on a sticker/label + // TODO: what is this ???? + memcpy(wps_start.pin, pin, wps_start.pin_length + 1); + } + else + { + wps_start.wps_mode = ATH_WPS_MODE_PUSHBUTTON; + } + wps_start.timeout_seconds = WPS_STANDARD_TIMEOUT; + + if (gWpsCredentials.ssid_len == 0) + { + wps_start.ssid_info.ssid_len = 0; + } + else + { + memcpy(wps_start.ssid_info.ssid, &gWpsCredentials.ssid, sizeof(wps_start.ssid_info.ssid)); + memcpy(wps_start.ssid_info.macaddress, gWpsCredentials.mac_addr, ATH_MAC_LEN); + wps_start.ssid_info.channel = gWpsCredentials.ap_channel; + wps_start.ssid_info.ssid_len = gWpsCredentials.ssid_len; + } + + /* this starts WPS on the Aheros wifi */ + if (custom_qapi(device_id, ATH_START_WPS, ¶m) != A_OK) + { + error = A_ERROR; + } + } while (0); + + return error; +} + +A_STATUS qcom_wps_connect(uint8_t device_id) +{ + qcom_set_ssid(device_id, &gWpsCredentials.ssid); + if (gWpsCredentials.key_idx != 0) + { + qcom_sec_set_wepkey(device_id, gWpsCredentials.key_idx, (char *)gWpsCredentials.key); + qcom_sec_set_wepkey_index(device_id, gWpsCredentials.key_idx); + } + else if (gWpsCredentials.auth_type != WLAN_AUTH_NONE) + { + qcom_sec_set_auth_mode(device_id, gWpsCredentials.auth_type); + qcom_sec_set_encrypt_mode(device_id, gWpsCredentials.encr_type); + } + + return qcom_commit(device_id); +} + +A_STATUS qcom_wps_set_credentials(uint8_t device_id, qcom_wps_credentials_t *pwps_prof) +{ + /* save wps credentials */ + A_MEMZERO(&gWpsCredentials, sizeof(qcom_wps_credentials_t)); + if (pwps_prof != NULL) + A_MEMCPY(&gWpsCredentials, pwps_prof, sizeof(qcom_wps_credentials_t)); + return A_OK; +} + +A_STATUS qcom_param_set( + uint8_t device_id, uint16_t grp_id, uint16_t param_id, void *data, uint32_t data_length, boolean wait_for_status) +{ + A_STATUS error = A_OK; + ATH_IOCTL_PARAM_STRUCT inout_param; + uint32_t which_param = QCOM_PARAM_MAKE_ID(grp_id, param_id); + uint32_t cmd_length = sizeof(WMI_PARAM_SET_CMD) + data_length - 1; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + WMI_PARAM_SET_CMD *cmd = (WMI_PARAM_SET_CMD *)A_MALLOC(cmd_length + sizeof(boolean), MALLOC_ID_CONTEXT); + + if (!cmd) + { + QCADRV_PRINTF("malloc fail\n"); + return A_ERROR; + } + cmd->length = cmd_length; + cmd->which_param = which_param; + memcpy(cmd->data_buffer, data, data_length); + + inout_param.cmd_id = ATH_SET_PARAM; + inout_param.data = cmd; + *((uint32_t *)((uint8_t *)(inout_param.data) + cmd_length)) = wait_for_status; + inout_param.length = cmd_length; + + if (custom_qapi(device_id, ATH_SET_PARAM, &inout_param) != A_OK) + { + error = A_ERROR; + } + + A_FREE(cmd, MALLOC_ID_CONTEXT); + + return error; +} + +#if ENABLE_P2P_MODE + +A_STATUS qcom_p2p_enable(uint8_t device_id, P2P_DEV_CTXT *dev, int32_t enable) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_SET_PROFILE_CMD p2p; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&p2p, sizeof(WMI_P2P_SET_PROFILE_CMD)); + p2p.enable = enable; + + param.cmd_id = ATH_P2P_SWITCH; + param.data = &p2p; + param.length = sizeof(p2p); + if (custom_qapi(device_id, ATH_P2P_SWITCH, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +static A_STATUS qcom_p2p_group_init(uint8_t device_id, uint8_t persistent_group, uint8_t group_formation) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_GRP_INIT_CMD grpInit; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&grpInit, sizeof(WMI_P2P_GRP_INIT_CMD)); + grpInit.group_formation = group_formation; + grpInit.persistent_group = persistent_group; + + param.cmd_id = ATH_P2P_APMODE; + param.data = &grpInit; + param.length = sizeof(grpInit); + if (custom_qapi(device_id, ATH_P2P_APMODE, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +static A_STATUS qcom_set_ap_params(uint8_t device_id, uint16_t param_cmd, uint8_t *data_val) +{ + ATH_IOCTL_PARAM_STRUCT inout_param = {0}; + ATH_AP_PARAM_STRUCT ap_param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + inout_param.cmd_id = ATH_CONFIG_AP; + ap_param.cmd_subset = param_cmd; + ap_param.data = data_val; + inout_param.data = &ap_param; + + if (custom_qapi(device_id, ATH_CONFIG_AP, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_start_go( + uint8_t device_id, QCOM_SSID *pssid, QCOM_PASSPHRASE *ppass, int32_t channel, boolean ucpersistent) +{ + A_STATUS error = A_OK; + uint8_t wps_flag; + + qcom_sec_set_auth_mode(device_id, WLAN_AUTH_WPA2_PSK); + qcom_sec_set_encrypt_mode(device_id, WLAN_CRYPT_AES_CRYPT); + if (pssid != NULL) + { + qcom_p2p_func_set_pass_ssid(device_id, ppass, pssid); + } + + qcom_op_set_mode(device_id, QCOM_WLAN_DEV_MODE_AP); + + if (channel != P2P_AUTO_CHANNEL) + { + qcom_set_channel(device_id, channel); + } + + wps_flag = 0x01; + if (qcom_set_ap_params(device_id, AP_SUB_CMD_WPS_FLAG, &wps_flag) != A_OK) + { + return A_ERROR; + } + + qcom_op_set_mode(device_id, QCOM_WLAN_DEV_MODE_AP); + + if (qcom_p2p_group_init(device_id, ucpersistent, 1) != A_OK) + { + return A_ERROR; + } + + /* Set MAX PERF */ + qcom_power_set_mode(device_id, MAX_PERF_POWER, P2P); + return error; +} + +A_STATUS qcom_p2p_func_init(uint8_t device_id, int32_t enable) +{ + static int32_t p2p_enable_flag = 0xFEFE; + + if (enable == p2p_enable_flag) + { + return A_OK; + } + p2p_enable_flag = enable; + + qcom_p2p_enable(device_id, NULL, enable); + qcom_p2p_func_set_config(device_id, 0, 1, 1, 3000, 81, 81, 5); + + return A_OK; +} + +A_STATUS qcom_p2p_func_find(uint8_t device_id, void *dev, uint8_t type, uint32_t timeout) +{ + WMI_P2P_FIND_CMD find_params; + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + find_params.type = type; + find_params.timeout = A_CPU2LE32(timeout); + param.cmd_id = ATH_P2P_FIND; + param.data = &find_params; + param.length = sizeof(WMI_P2P_FIND_CMD); + if (custom_qapi(device_id, ATH_P2P_FIND, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_set_pass_ssid(uint8_t device_id, QCOM_PASSPHRASE *ppass, QCOM_SSID *pssid) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_SET_PASSPHRASE_CMD setPassPhrase; + + if (qcom_set_ssid(device_id, pssid) != A_OK) + return A_ERROR; + + strcpy((char *)setPassPhrase.passphrase, ppass->passphrase); + setPassPhrase.passphrase_len = strlen(ppass->passphrase); + strcpy((char *)setPassPhrase.ssid, pssid->ssid); + setPassPhrase.ssid_len = strlen(pssid->ssid); + + param.cmd_id = ATH_P2P_APMODE_PP; + param.data = &setPassPhrase; + param.length = sizeof(WMI_SET_PASSPHRASE_CMD); + if (custom_qapi(device_id, ATH_P2P_APMODE_PP, ¶m) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_p2p_func_listen(uint8_t device_id, uint32_t timeout) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + uint32_t tout; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + tout = timeout; + param.cmd_id = ATH_P2P_LISTEN; + param.data = &tout; + param.length = sizeof(tout); + if (custom_qapi(device_id, ATH_P2P_LISTEN, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_connect(uint8_t device_id, P2P_WPS_METHOD wps_method, uint8_t *peer_mac, boolean persistent) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_FW_CONNECT_CMD_STRUCT p2p_connect; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + A_MEMZERO(&p2p_connect, sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + p2p_connect.wps_method = wps_method; + A_MEMCPY(p2p_connect.peer_addr, peer_mac, ATH_MAC_LEN); + + /* Setting Default Value for now !!! */ + p2p_connect.dialog_token = 1; + p2p_connect.go_intent = 0; + p2p_connect.go_dev_dialog_token = 0; + p2p_connect.dev_capab = 0x23; + if (persistent) + { + p2p_connect.dev_capab |= P2P_PERSISTENT_FLAG; + } + + param.cmd_id = ATH_P2P_CONNECT_CLIENT; + param.data = &p2p_connect; + param.length = sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT); + if (custom_qapi(device_id, ATH_P2P_CONNECT_CLIENT, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_auth( + uint8_t device_id, int32_t dev_auth, P2P_WPS_METHOD wps_method, uint8_t *peer_mac, boolean persistent) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_FW_CONNECT_CMD_STRUCT p2p_connect; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&p2p_connect, sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + + if (persistent) + p2p_connect.dev_capab |= P2P_PERSISTENT_FLAG; + p2p_connect.dev_auth = dev_auth; + p2p_connect.wps_method = wps_method; + A_MEMCPY(p2p_connect.peer_addr, peer_mac, ATH_MAC_LEN); + /* If go_intent <= 0, wlan firmware will use the intent value configured via + * qcom_p2p_set + */ + p2p_connect.go_intent = 0; + + param.cmd_id = ATH_P2P_AUTH; + param.data = &p2p_connect; + param.length = sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT); + if (custom_qapi(device_id, ATH_P2P_AUTH, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_cancel(uint8_t device_id) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + param.cmd_id = ATH_P2P_CANCEL; + param.data = NULL; + param.length = 0; + if (custom_qapi(device_id, ATH_P2P_CANCEL, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_stop_find(uint8_t device_id) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + param.cmd_id = ATH_P2P_STOP; + param.data = NULL; + param.length = 0; + if (custom_qapi(device_id, ATH_P2P_STOP, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +/* NODE_LIST */ +A_STATUS qcom_p2p_func_get_node_list(uint8_t device_id, void *app_buf, uint32_t buf_size) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + param.cmd_id = ATH_P2P_NODE_LIST; + param.data = app_buf; + param.length = buf_size; + if (custom_qapi(device_id, ATH_P2P_NODE_LIST, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_set_config(uint8_t device_id, + uint32_t uigo_intent, + uint32_t uiclisten_ch, + uint32_t uiop_ch, + uint32_t uiage, + uint32_t reg_class, + uint32_t op_reg_class, + uint32_t max_node_count) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_FW_SET_CONFIG_CMD stp2p_cfg_cmd; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&stp2p_cfg_cmd, sizeof(stp2p_cfg_cmd)); + stp2p_cfg_cmd.go_intent = uigo_intent; + stp2p_cfg_cmd.reg_class = reg_class; + stp2p_cfg_cmd.op_reg_class = op_reg_class; + stp2p_cfg_cmd.op_channel = uiop_ch; + stp2p_cfg_cmd.listen_channel = uiclisten_ch; + stp2p_cfg_cmd.node_age_to = uiage; + stp2p_cfg_cmd.max_node_count = max_node_count; + + param.cmd_id = ATH_P2P_SET_CONFIG; + param.data = &stp2p_cfg_cmd; + param.length = sizeof(WMI_P2P_FW_SET_CONFIG_CMD); + if (custom_qapi(device_id, ATH_P2P_SET_CONFIG, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_wps_config(uint8_t device_id, uint8_t *p2p_ptr) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + param.cmd_id = ATH_P2P_WPS_CONFIG; + param.data = p2p_ptr; + param.length = sizeof(WMI_WPS_SET_CONFIG_CMD); + if (custom_qapi(device_id, ATH_P2P_WPS_CONFIG, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_disc_req(uint8_t device_id, uint8_t *p2p_ptr) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + param.cmd_id = ATH_P2P_DISC_REQ; + param.data = p2p_ptr; + param.length = sizeof(WMI_P2P_FW_PROV_DISC_REQ_CMD); + if (custom_qapi(device_id, ATH_P2P_DISC_REQ, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_set(uint8_t device_id, P2P_CONF_ID config_id, void *data, uint32_t data_length) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_SET_CMD p2p_set_params; + WMI_P2P_CONF_ID wmi_config_id; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&p2p_set_params, sizeof(p2p_set_params)); + + /*TODO: aren't WMI_P2P_CONF_ID / P2P_CONF_ID the same ?*/ + switch (config_id) + { + case P2P_CONFIG_LISTEN_CHANNEL: + wmi_config_id = WMI_P2P_CONFID_LISTEN_CHANNEL; + break; + case P2P_CONFIG_CROSS_CONNECT: + wmi_config_id = WMI_P2P_CONFID_CROSS_CONNECT; + break; + case P2P_CONFIG_SSID_POSTFIX: + wmi_config_id = WMI_P2P_CONFID_SSID_POSTFIX; + break; + case P2P_CONFIG_INTRA_BSS: + wmi_config_id = WMI_P2P_CONFID_INTRA_BSS; + break; + case P2P_CONFIG_CONCURRENT_MODE: + wmi_config_id = WMI_P2P_CONFID_CONCURRENT_MODE; + break; + case P2P_CONFIG_GO_INTENT: + wmi_config_id = WMI_P2P_CONFID_GO_INTENT; + break; + case P2P_CONFIG_DEV_NAME: + wmi_config_id = WMI_P2P_CONFID_DEV_NAME; + break; + case P2P_CONFIG_P2P_OPMODE: + wmi_config_id = WMI_P2P_CONFID_P2P_OPMODE; + break; + case P2P_CONFIG_CCK_RATES: + wmi_config_id = WMI_P2P_CONFID_CCK_RATES; + break; + default: + /* Unknown parameter */ + return A_ERROR; + } + + p2p_set_params.config_id = wmi_config_id; + A_MEMCPY(&p2p_set_params.val, data, data_length); + + param.cmd_id = ATH_P2P_SET; + param.data = &p2p_set_params; + param.length = sizeof(WMI_P2P_SET_CMD); + if (custom_qapi(device_id, ATH_P2P_SET, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_join(uint8_t device_id, P2P_WPS_METHOD wps_method, uint8_t *pmac, char *ppin, uint16_t channel) +{ + uint16_t conc_channel; + WMI_P2P_FW_CONNECT_CMD_STRUCT p2p_join_profile; + WMI_P2P_PROV_INFO p2p_info; + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + +#if ENABLE_SCC_MODE + int num_dev = WLAN_NUM_OF_DEVICES; + if ((num_dev > 1) && (device_id == 0)) + { + qcom_get_concurrent_channel(device_id, &conc_channel); + if ((conc_channel != 0) && (channel == 0)) + { + return A_ERROR; + } + if ((conc_channel != 0) && (channel != conc_channel)) + { + return A_ERROR; + } + } +#endif /* ENABLE_SCC_MODE */ + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + A_MEMZERO(&p2p_join_profile, sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + A_MEMCPY(p2p_join_profile.peer_addr, pmac, ATH_MAC_LEN); + p2p_join_profile.go_oper_freq = channel; + p2p_join_profile.wps_method = wps_method; + + if (wps_method != (uint8_t)WPS_PBC) + { + strcpy(p2p_info.wps_pin, ppin); + wmi_save_key_info(&p2p_info); + } + + param.cmd_id = ATH_P2P_JOIN; + param.data = &p2p_join_profile; + param.length = sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT); + if (custom_qapi(device_id, ATH_P2P_JOIN, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_invite_auth(uint8_t device_id, uint8_t *inv) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + param.cmd_id = ATH_P2P_INVITE_AUTH; + param.data = inv; + param.length = sizeof(WMI_P2P_FW_INVITE_REQ_RSP_CMD); + if (custom_qapi(device_id, ATH_P2P_INVITE_AUTH, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +/* LIST_NETWORK */ +A_STATUS qcom_p2p_func_get_network_list(uint8_t device_id, void *app_buf, uint32_t buf_size) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + param.cmd_id = ATH_P2P_PERSISTENT_LIST; + param.data = app_buf; + param.length = buf_size; + if (custom_qapi(device_id, ATH_P2P_PERSISTENT_LIST, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_invite( + uint8_t device_id, char *pssid, P2P_WPS_METHOD wps_method, uint8_t *pmac, boolean persistent, P2P_INV_ROLE role) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_INVITE_CMD p2pInvite; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + A_MEMZERO(&p2pInvite, sizeof(p2pInvite)); + + A_MEMCPY(p2pInvite.ssid.ssid, pssid, strlen(pssid)); + p2pInvite.ssid.ssidLength = strlen(pssid); + A_MEMCPY(p2pInvite.peer_addr, pmac, ATH_MAC_LEN); + p2pInvite.wps_method = wps_method; + p2pInvite.is_persistent = persistent; + p2pInvite.role = role; + + param.cmd_id = ATH_P2P_INVITE; + param.data = &p2pInvite; + param.length = sizeof(WMI_P2P_INVITE_CMD); + + if (custom_qapi(device_id, ATH_P2P_INVITE, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_join_profile(uint8_t device_id, uint8_t *pmac) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_FW_CONNECT_CMD_STRUCT p2p_connect; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&p2p_connect, sizeof(p2p_connect)); + A_MEMCPY(p2p_connect.peer_addr, pmac, ATH_MAC_LEN); + + param.cmd_id = ATH_P2P_JOIN_PROFILE; + param.data = &p2p_connect; + param.length = sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT); + if (custom_qapi(device_id, ATH_P2P_JOIN_PROFILE, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_ap_mode(uint8_t device_id, uint8_t *p2p_ptr) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + param.cmd_id = ATH_P2P_APMODE; + param.data = p2p_ptr; + param.length = sizeof(WMI_P2P_GRP_INIT_CMD); + if (custom_qapi(device_id, ATH_P2P_APMODE, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_on_off(uint8_t device_id, uint8_t *p2p_ptr) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + param.cmd_id = ATH_P2P_SWITCH; + param.data = p2p_ptr; + param.length = sizeof(WMI_P2P_SET_PROFILE_CMD); + if (custom_qapi(device_id, ATH_P2P_SWITCH, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_set_noa( + uint8_t device_id, uint8_t uccount, uint32_t uistart, uint32_t uiduration, uint32_t uiinterval) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + P2P_NOA_INFO p2p_noa_desc; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + if (uccount >= P2P_MAX_NOA_DESCRIPTORS) + { + return A_ERROR; + } + + A_MEMZERO(&p2p_noa_desc, sizeof(p2p_noa_desc)); + if (uccount > 0) + { + uint8_t i; + p2p_noa_desc.enable = 1; + p2p_noa_desc.count = uccount; + + for (i = 0; i < uccount; i++) + { + p2p_noa_desc.noas[i].count_or_type = uccount; + p2p_noa_desc.noas[i].duration = uiduration; + p2p_noa_desc.noas[i].interval = uiinterval; + p2p_noa_desc.noas[i].start_or_offset = uistart; + } + } + + param.cmd_id = ATH_P2P_SET_NOA; + param.data = &p2p_noa_desc; + param.length = sizeof(p2p_noa_desc); + if (custom_qapi(device_id, ATH_P2P_SET_NOA, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_set_oppps(uint8_t device_id, uint8_t enable, uint8_t ctwin) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_OPPPS_INFO_STRUCT p2p_oppps; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&p2p_oppps, sizeof(WMI_OPPPS_INFO_STRUCT)); + p2p_oppps.enable = enable; + p2p_oppps.ctwin = ctwin; + + param.cmd_id = ATH_P2P_SET_OPPPS; + param.data = &p2p_oppps; + param.length = sizeof(WMI_OPPPS_INFO_STRUCT); + if (custom_qapi(device_id, ATH_P2P_SET_OPPPS, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_p2p_func_prov(uint8_t device_id, P2P_WPS_METHOD wps_method, uint8_t *pmac) +{ + ATH_IOCTL_PARAM_STRUCT param; + A_STATUS error = A_OK; + WMI_P2P_FW_PROV_DISC_REQ_CMD p2p_prov_disc; + + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + A_MEMZERO(&p2p_prov_disc, sizeof(p2p_prov_disc)); + p2p_prov_disc.dialog_token = 1; + p2p_prov_disc.wps_method = wps_method; + A_MEMCPY(p2p_prov_disc.peer, pmac, ATH_MAC_LEN); + + param.cmd_id = ATH_P2P_DISC_REQ; + param.data = &p2p_prov_disc; + param.length = sizeof(p2p_prov_disc); + if (custom_qapi(device_id, ATH_P2P_DISC_REQ, ¶m) != A_OK) + { + error = A_ERROR; + } + return error; +} +#endif + +A_STATUS qcom_raw_mode_send_pkt(QCOM_RAW_MODE_PARAM_t *ppara) +{ + uint8_t access_cat; + int32_t i; + ATH_IOCTL_PARAM_STRUCT param; + ATH_MAC_TX_RAW_S details; + uint8_t *buffer = NULL; + typedef struct + { + uint8_t fc[2]; + uint8_t duration[2]; + uint8_t addr[3][6]; + uint8_t seq[2]; + } WIFI_HDR; + + typedef struct + { + uint8_t fc[2]; + uint8_t duration[2]; + uint8_t addr[3][6]; + uint8_t seq[2]; + uint8_t addr_3[6]; + uint8_t pad[2]; // pad required by firmware + } WIFI_4_HDR; + + typedef struct + { + uint8_t fc[2]; + uint8_t duration[2]; + uint8_t addr[3][6]; + uint8_t seq[2]; + uint8_t qos[2]; + uint8_t pad[2]; // pad required by firmware + } WIFI_QOS_HDR; +#define WIFI_HDR_SZ (24) +#define WIFI_4_HDR_SZ (32) +#define WIFI_QOS_HDR_SZ (28) + uint8_t header_sz[3] = {WIFI_HDR_SZ, WIFI_QOS_HDR_SZ, WIFI_4_HDR_SZ}; + WIFI_4_HDR *p4Hdr; + WIFI_HDR *pHdr; + WIFI_QOS_HDR *pQosHdr; + A_STATUS error = A_OK; + + uint8_t rate_index = ppara->rate_index; + uint8_t tries = ppara->tries; + uint32_t size = ppara->size; + uint32_t chan = ppara->chan; + uint8_t header_type = ppara->header_type; + uint16_t bcn_seq_num = ppara->seq; + uint8_t *paddr1 = &ppara->addr1.addr[0]; + uint8_t *paddr2 = &ppara->addr2.addr[0]; + uint8_t *paddr3 = &ppara->addr3.addr[0]; + uint8_t *paddr4 = &ppara->addr4.addr[0]; + uint8_t *pdatabuf = ppara->pdatabuf; + uint32_t buflen = ppara->buflen; + + do + { + if (rate_index > 19 || tries > 14 || size > 1400 || chan > 14 || header_type > 2) + { + error = A_ERROR; + break; + } + + if ((pdatabuf != NULL) && (buflen >= size)) + { + error = A_ERROR; + break; + } + + if (chan != 0) + { + error = qcom_set_channel(0, chan); + if (A_OK != error) + { + break; + } + } + + size += header_sz[header_type]; + if (NULL == (buffer = A_MALLOC(size, MALLOC_ID_CONTEXT))) + { + error = A_ERROR; + break; + } + + pHdr = (WIFI_HDR *)&buffer[0]; + + A_MEMZERO(pHdr, WIFI_HDR_SZ); + + pHdr->fc[0] = 0x80; // beacon + pHdr->seq[0] = ((bcn_seq_num & 0xf) << 4); + pHdr->seq[1] = ((bcn_seq_num & 0xff0) >> 4); + + A_MEMCPY(&pHdr->addr[0][0], paddr1, ATH_MAC_LEN); + A_MEMCPY(&pHdr->addr[1][0], paddr2, ATH_MAC_LEN); + A_MEMCPY(&pHdr->addr[2][0], paddr3, ATH_MAC_LEN); + + access_cat = ATH_ACCESS_CAT_BE; + + if (header_type == 1) + { + // change frame control to qos data + pHdr->fc[0] = 0x88; + pHdr->fc[1] = 0x01; // to-ds + pQosHdr = (WIFI_QOS_HDR *)pHdr; + pQosHdr->qos[0] = 0x03; + pQosHdr->qos[1] = 0x00; + // bssid == addr[0] + // memcpy(&(pHdr->addr[0][0]), &(pHdr->addr[1][0]), 6); + // change destination address + // pHdr->addr[2][3] = 0xaa; + // pHdr->addr[2][4] = 0xaa; + // pHdr->addr[2][5] = 0xaa; + access_cat = ATH_ACCESS_CAT_VI; + } + else if (header_type == 2) + { + pHdr->fc[0] = 0x08; + pHdr->fc[1] = 0x03; // to-ds | from-ds + p4Hdr = (WIFI_4_HDR *)pHdr; + p4Hdr->addr_3[0] = paddr4[0]; + p4Hdr->addr_3[1] = paddr4[1]; + p4Hdr->addr_3[2] = paddr4[2]; + p4Hdr->addr_3[3] = paddr4[3]; + p4Hdr->addr_3[4] = paddr4[4]; + p4Hdr->addr_3[5] = paddr4[5]; + } + + /* now setup the frame for transmission */ + if (pdatabuf == NULL) + { + for (i = header_sz[header_type]; i < (int32_t)size; i++) + buffer[i] = (i - header_sz[header_type]) & 0xff; + } + else + { + i = header_sz[header_type]; + A_MEMCPY(&(buffer[i]), pdatabuf, buflen); + } + + A_MEMZERO(&details, sizeof(details)); + + details.buffer = buffer; + details.length = size; + details.params.pktID = 1; + details.params.rateSched.accessCategory = access_cat; + /* we set the ACK bit simply to force the desired number of retries */ + details.params.rateSched.flags = ATH_MAC_TX_FLAG_ACK; + details.params.rateSched.trySeries[0] = tries; + details.params.rateSched.rateSeries[0] = rate_index; + details.params.rateSched.rateSeries[1] = 0xff; // terminate series + + param.cmd_id = ATH_MAC_TX_RAW; + param.data = &details; + param.length = sizeof(details); + + if (custom_qapi(0, ATH_MAC_TX_RAW, ¶m) != A_OK) + { + error = A_ERROR; + } + } while (0); + + if (buffer) + A_FREE(buffer, MALLOC_ID_CONTEXT); + + return error; +} + +A_STATUS qcom_get_versionstr(ATH_VERSION_STR *versionstr) +{ + ATH_IOCTL_PARAM_STRUCT param; + + param.cmd_id = ATH_GET_VERSION_STR; + param.data = versionstr; + param.length = sizeof(ATH_VERSION_STR); + + return custom_qapi(0, ATH_GET_VERSION_STR, ¶m); +} + +A_STATUS qcom_set_appie(uint8_t device_id, uint8_t mgmtType, uint8_t *appie, uint8_t ieLen) +{ + A_STATUS error = A_OK; + ATH_IOCTL_PARAM_STRUCT inout_param; + ATH_APPIE_PARAM param; + + if(A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + + /* appie is a hex string beginning with DD */ + param.mgmtFrmType = mgmtType; + param.ieLen = ieLen; + param.ieInfo = appie; + + inout_param.cmd_id = ATH_SET_APPIE; + inout_param.data = ¶m; + inout_param.length = sizeof(ATH_APPIE_PARAM); + + if(param.ieLen > ATH_MAX_IE_LEN) + { + return A_ERROR; + } + + if(custom_qapi(device_id, ATH_SET_APPIE, &inout_param) != A_OK) + { + error = A_ERROR; + } + + return error; +} + +A_STATUS qcom_wps_init_key (uint8_t device_id) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + + inout_param.cmd_id = ATH_WLAN_WPS_INIT_KEY; + inout_param.data = NULL; + inout_param.length = 0; + + if(custom_qapi(device_id, ATH_WLAN_WPS_INIT_KEY, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + +A_STATUS qcom_heartbeat_challenge (uint8_t device_id) +{ + ATH_IOCTL_PARAM_STRUCT inout_param; + A_STATUS error = A_OK; + +#define HB_MAGIC 0x63825363L + + struct WMIX_GPIO_REGISTER_GET { + WMIX_CMD_HDR cmd; + WMIX_HB_CHALLENGE_RESP_CMD hb; + } hb_challenge_cmd; + + + hb_challenge_cmd.cmd.commandId =WMIX_HB_CHALLENGE_RESP_CMDID; + hb_challenge_cmd.hb.cookie = HB_MAGIC; + hb_challenge_cmd.hb.source = 0; //TODO + + inout_param.cmd_id = ATH_HEARTBEAT_CHALLEANGE; + inout_param.data = (void *)&hb_challenge_cmd; + inout_param.length = sizeof(hb_challenge_cmd); + + if(custom_qapi(device_id, ATH_HEARTBEAT_CHALLEANGE, &inout_param) != A_OK) + { + error = A_ERROR; + } + return error; +} + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_dns.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_dns.c new file mode 100644 index 00000000000..7d85a892fd1 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_dns.c @@ -0,0 +1,244 @@ +/************************************************************************** +* +* Copyright 2011-2017 by Andrey Butok. FNET Community. +* +*************************************************************************** +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*************************************************************************** +* +* DNS Resolver implementation. +* +***************************************************************************/ + +#include "wifi_common.h" +#include "qcom_api.h" +#include "atheros_wifi.h" + +#define WIFI_DNS_HEADER_FLAGS_QR (0x8000U) +#define WIFI_DNS_HEADER_FLAGS_AA (0x0400U) +#define WIFI_DNS_HEADER_FLAGS_TC (0x0200U) +#define WIFI_DNS_HEADER_FLAGS_RD (0x0100U) +#define WIFI_DNS_HEADER_FLAGS_RA (0x0080U) +#define WIFI_DNS_TYPE_A (0x0001U) +#define WIFI_DNS_HEADER_CLASS_IN (0x01U) + +#define WIFI_MAX_DNS_NAME_LENGTH (253) + +/* Taken from FNET */ +typedef PREPACK struct +{ + uint16_t id; + uint16_t flags; + uint16_t qdcount; + uint16_t ancount; + uint16_t nscount; + uint16_t arcount; +} POSTPACK wifi_dns_header_t; + +/* Taken from FNET */ +typedef PREPACK struct +{ + uint8_t zero_length; + uint16_t qtype; + uint16_t qclass; + +} POSTPACK wifi_dns_q_tail_t; + +/* Taken from FNET */ +typedef PREPACK struct +{ + PREPACK union + { + uint8_t name_ptr_c[2]; + uint16_t name_ptr; + } POSTPACK name; + uint16_t type; + uint16_t rr_class; + uint32_t ttl; + uint16_t rdlength; + uint32_t rdata; + +} POSTPACK wifi_dns_rr_header_t; + +static int32_t wifi_dns_assemble_request(char *buffer, char *hostname, uint32_t buff_len) +{ + uint32_t total_length = 0, label_length = 0; + wifi_dns_q_tail_t *q_tail; + /* Separate strings by '\0'*/ + uint32_t hostname_len = strlen(hostname); + + /* Buffer too small to handle 'hostname' */ + if ((buff_len < 0) || (buff_len <= hostname_len + sizeof(wifi_dns_q_tail_t))) + return -1; + + strcpy(&buffer[1], hostname); + buffer[0] = '\0'; + + /* Force '\0' delimiter */ + for (int32_t i = 0; i < hostname_len + 1; i++) + { + if ('.' == buffer[i]) + buffer[i] = '\0'; + } + + /* Replace '\0' with string length */ + total_length = 0; + while ((label_length = strlen(&buffer[total_length + 1])) > 0) + { + buffer[total_length] = label_length; + total_length += label_length + 1; + } + + q_tail = (wifi_dns_q_tail_t *)&buffer[total_length]; + + /* QTYPE */ + q_tail->qtype = A_CPU2BE16(WIFI_DNS_TYPE_A); + + /* QCLASS */ + q_tail->qclass = A_CPU2BE16(WIFI_DNS_HEADER_CLASS_IN); + + return (total_length + sizeof(wifi_dns_q_tail_t)); +} + + +static uint16_t wifi_id_cnt = 1; + + +A_STATUS qcom_dns_resolver(IP_ADDR_T dns_ip, char * hostname, IP_ADDR_T *host_ip, uint32_t timeout_ms) +{ + int32_t dns_sock = -1; + SOCKADDR_T dns_addr = {0}; + char * tx_buffer = NULL; + uint32_t tx_len = 0; + char * rx_buffer = NULL; + wifi_dns_rr_header_t *dns_resp = NULL; + wifi_dns_header_t *dns_hdr = NULL; + int32_t result = 0; + uint16_t dns_addr_len = sizeof(dns_addr); + A_STATUS status = A_ERROR; + int32_t tmp_len = 0; + + const uint32_t rx_buffer_max = 512; + /* The total DNS query message is the size of the header + a null character before the host name + the maximum host name + * length + the size of the tail */ + const uint32_t tx_buffer_max = sizeof(wifi_dns_header_t) + 1 + WIFI_MAX_DNS_NAME_LENGTH + sizeof(wifi_dns_q_tail_t); + + do { + /* Try to allocate buffer for request, must be fill with '\0' */ + tx_buffer = (char *)CUSTOM_ALLOC(tx_buffer_max); + memset(tx_buffer, 0, tx_buffer_max); + if (NULL == tx_buffer) + break; + + /* Set DNS address */ + /* qcom code is expecting the port, address, and family in host order */ + dns_addr.sin_port = 53; + dns_addr.sin_addr.s_addr = dns_ip.s_addr; + dns_addr.sin_family = ATH_AF_INET; + + /* Create UDP socket */ + dns_sock = qcom_socket(ATH_AF_INET, SOCK_DGRAM_TYPE, 0); + if (-1 == dns_sock) + break; + + /* Prepare request header */ + dns_hdr = (wifi_dns_header_t*)&tx_buffer[0]; + dns_hdr->id = wifi_id_cnt++; + dns_hdr->flags = A_CPU2BE16(WIFI_DNS_HEADER_FLAGS_RD); + dns_hdr->qdcount = A_CPU2BE16(1U); + + /* Prepare request body */ + tx_len = sizeof(wifi_dns_header_t); + if (0 > (tmp_len = wifi_dns_assemble_request(&tx_buffer[ tx_len ], hostname, tx_buffer_max - tx_len))) + break; + tx_len += tmp_len; + + /* Send data over UDP */ + result = qcom_sendto(dns_sock, tx_buffer, tx_len, 0, (void *)(&dns_addr), sizeof(dns_addr)); + if (-1 == result) + break; + + /* Free TX resources*/ + CUSTOM_FREE(tx_buffer); + tx_buffer = NULL; + + /* Obtain WiFi context */ + QCA_CONTEXT_STRUCT *qcaCtx = Custom_Api_GetDriverCxt(0); + if (NULL == qcaCtx) + break; + + /* Block on receive max 'timeout_ms' */ + result = t_select(qcaCtx, dns_sock, timeout_ms); + if (A_OK != result) + break; + + /* Receive data from DNS server */ + result = qcom_recvfrom(dns_sock, &rx_buffer, rx_buffer_max, 0, (struct sockaddr *)&dns_addr, &dns_addr_len); + if (-1 == result) + break; + + /* Typecast header */ + dns_hdr = (wifi_dns_header_t*)rx_buffer; + + /* Try to find response (should be always at addr '&rx_buffer[ tx_len ]') */ + for (tx_len = sizeof(wifi_dns_header_t); tx_len < result; tx_len++) + { + /* However, more stable solution is to find DNS_NAME_COMPRESSED_MASK (0xC) in stream (according to FNET) */ + if (0xC0 == (uint8_t)rx_buffer[tx_len]) + { + /* Typecast response */ + dns_resp = (wifi_dns_rr_header_t*)&rx_buffer[ tx_len ]; + /* Expected IPv4 response*/ + if ( + (dns_resp->rr_class == A_CPU2BE16(WIFI_DNS_HEADER_CLASS_IN)) && + (dns_resp->type == A_CPU2BE16(WIFI_DNS_TYPE_A)) + ) + { + /* Get IPv4 address */ + /* Uncomment in case of wrong byte order */ + // host_ip->s_addr = A_CPU2BE32(dns_resp->rdata); + host_ip->s_addr = dns_resp->rdata; + status = A_OK; + break; + } + } + } + } while(0); + + /* Cleanup */ + /* Free TX buffer */ + if (NULL != tx_buffer) + { + CUSTOM_FREE(tx_buffer); + tx_buffer = NULL; + } + /* Free RxBuffer */ + if (NULL != rx_buffer) + { + zero_copy_free(rx_buffer); + rx_buffer = NULL; + } + /* Close socket */ + if (-1 != dns_sock) + { + qcom_socket_close(dns_sock); + dns_sock = -1; + } + + return status; +} + + + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_legacy.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_legacy.c new file mode 100644 index 00000000000..2d4161f82a2 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/qapi/qcom_legacy.c @@ -0,0 +1,71 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if ENABLE_P2P_MODE +#include +#include "p2p.h" +#endif +#include "atheros_wifi.h" +#include "atheros_wifi_api.h" +#include "atheros_wifi_internal.h" +#include "atheros_stack_offload.h" +#include "dset_api.h" +#include "common_stack_offload.h" +#include "qcom_api.h" + +extern A_STATUS qcom_set_deviceid(uint16_t id); +A_STATUS custom_qapi(uint8_t device_id, uint32_t cmd, void *param); + +/*-----------------------------------------------------------------------------------------------------------------*/ +A_STATUS depr_qcom_set_scan(uint8_t device_id) +{ + A_STATUS error = A_OK; + if (A_OK != qcom_set_deviceid(device_id)) + { + return A_ERROR; + } + if (custom_qapi(device_id, ATH_SET_SCAN, NULL) != A_OK) + error = A_ERROR; + + return error; +} + +A_STATUS depr_qcom_ota_done() +{ +#if ENABLE_STACK_OFFLOAD + return ((A_STATUS)custom_ota_done(Custom_Api_GetDriverCxt(0), 1)); +#else + return A_ERROR; +#endif +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/reorder/rcv_aggr.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/reorder/rcv_aggr.c new file mode 100644 index 00000000000..56018151f14 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/reorder/rcv_aggr.c @@ -0,0 +1,187 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include "wmi.h" +#include "atheros_wifi_api.h" + +#if WLAN_CONFIG_11N_AGGR_SUPPORT + +#define NUM_OF_TIDS 8 +#define AGGR_SZ_DEFAULT 8 + +#define IEEE80211_MAX_SEQ_NO 0xFFF + +typedef struct +{ + uint32_t aggr_enabled_tid_mask; /* config value of aggregation size */ + uint16_t seq_last[NUM_OF_TIDS]; +} AGGR_INFO; + +static AGGR_INFO aggr_context; + +void aggr_deinit(void *cntxt) +{ + UNUSED_ARGUMENT(cntxt); +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : aggr_init +* Returned Value : +* Comments : +* Initializes aggregation data structures. +* +*END*-----------------------------------------------------------------*/ +void *aggr_init(void) +{ + /* some implementations malloc a context but this version simply uses + * a global context */ + + aggr_reset_state((void *)&aggr_context); + + return &aggr_context; +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : aggr_recv_addba_req_evt +* Returned Value : +* Comments : +* Firmware has indicated that aggregation is enabled +* for this TID. +* +*END*-----------------------------------------------------------------*/ +void aggr_recv_addba_req_evt(void *cntxt, uint8_t tidaid, uint16_t seq_no, uint8_t win_sz) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + uint8_t tid = tidaid & 0xF; + A_ASSERT(p_aggr); + A_ASSERT(tid < NUM_OF_TIDS); + UNUSED_ARGUMENT(win_sz); + p_aggr->aggr_enabled_tid_mask |= (1 << tid); + p_aggr->seq_last[tid] = seq_no; +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : aggr_recv_delba_req_evt +* Returned Value : +* Comments : +* Firmware has indicated that aggregation is no longer enabled +* for this TID. +* +*END*-----------------------------------------------------------------*/ +void aggr_recv_delba_req_evt(void *cntxt, uint8_t tidaid) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + uint8_t tid = tidaid & 0xF; + A_ASSERT(p_aggr); + A_ASSERT(tid < NUM_OF_TIDS); + + p_aggr->aggr_enabled_tid_mask &= ~(1 << tid); +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : aggr_reset_state +* Returned Value : +* Comments : +* Called when it is deemed necessary to clear the aggregate +* hold Q state. Examples include when a Connect event or +* disconnect event is received. +* +*END*-----------------------------------------------------------------*/ +void aggr_reset_state(void *cntxt) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + + A_ASSERT(p_aggr); + + p_aggr->aggr_enabled_tid_mask = 0; +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : aggr_process_recv_frm +* Returned Value : true - forward frame it is in-order +* false - drop frame as its out-of-order +* Comments : +* Processes a received frame to determine whether it should be +* dropped. Aggregation allows for frames to be sent out-of-order +* which some systems/tcp stacks fail to handle. One option is +* to queue packets in the driver and re-order them so that the +* driver always delivers packets to the next layer in-order. +* That however requires significant buffer space and so this +* implementation instead will drop any out-of-order packets. +* it does this by returning true for in-order packets and +* false for out-of-order packets. If aggregation +* is not enabled then there is no need to monitor the tid +* and the return value will always be true. +* +*END*-----------------------------------------------------------------*/ +boolean aggr_process_recv_frm(void *cntxt, uint8_t tid, uint16_t seq_no, boolean is_amsdu, void **osbuf) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + boolean result = false; + A_ASSERT(p_aggr); + A_ASSERT(tid < NUM_OF_TIDS); + UNUSED_ARGUMENT(osbuf); + UNUSED_ARGUMENT(is_amsdu); + + do + { + if ((!p_aggr->aggr_enabled_tid_mask) & (1 << tid)) + { + result = true; + break; + } + + if (p_aggr->seq_last[tid] > seq_no) + { + if (p_aggr->seq_last[tid] - seq_no <= (IEEE80211_MAX_SEQ_NO >> 1)) + { + /* drop this out-of-order packet */ + break; + } + } + else + { + if (seq_no - p_aggr->seq_last[tid] > (IEEE80211_MAX_SEQ_NO >> 1)) + { + /* drop this out-of-order packet */ + break; + } + } + /* adopt the new seq_no and allow the packet */ + result = true; + p_aggr->seq_last[tid] = seq_no; + } while (0); + + return result; +} +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/stack_common/api_stack_offload.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/stack_common/api_stack_offload.c new file mode 100644 index 00000000000..dd70d424529 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/stack_common/api_stack_offload.c @@ -0,0 +1,4698 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" + +// This conditional encapsulates the entire file +#if ENABLE_STACK_OFFLOAD + +#include "wifi_common.h" +#include +#include +#include +#include +#include "wmi_api.h" +#include "a_drv_api.h" +#include "cust_netbuf.h" +#include +#include "atheros_wifi_api.h" + +#include "atheros_stack_offload.h" +#include "common_stack_offload.h" +#include "custom_stack_offload.h" + +#define MAX_CERT_DATA_LENGTH 1400 +#define SSL_MAX_CERT_NAME_LEN 31 +extern const uint8_t max_performance_power_param; +ATH_SOCKET_CONTEXT *ath_sock_context[MAX_SOCKETS_SUPPORTED + 1]; + +/*****************************************************************************/ +/* custom_queue_empty - Checkes whether a socket queue is empty + * RETURNS: 1 - empty or 0 - not empty + *****************************************************************************/ +uint32_t queue_empty(uint32_t index) +{ + SOCKET_CONTEXT_PTR pcustctxt; + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); + + return A_NETBUF_QUEUE_EMPTY(&(pcustctxt->rxqueue)); +} + +#if ENABLE_SSL +void *sslhandle = NULL; // Driver context ptr needed by the SSL_xxx() API functions + +int32_t find_socket_context_from_ssl(SSL *ssl) +{ + int32_t index = 0; + + for (index = 0; index < MAX_SOCKETS_SUPPORTED; index++) + { + if (ath_sock_context[index]->ssl == ssl) + return index; + } + /*Index not found*/ + return SOCKET_NOT_FOUND; +} +#endif + +/*****************************************************************************/ +/* find_socket_context - Finds socket context based on socket handle. "retrieve" + * flag is used to identify if a new context is requested or an + * exiting context is retrieved. + * uint32_t handle - socket handle. + * uint8_t retrieve - see description + * Returns- index in context array + *****************************************************************************/ +int32_t find_socket_context(uint32_t handle, uint8_t retrieve) +{ + int32_t index = 0; + if (retrieve) + { + if (handle == 0) + return SOCKET_NOT_FOUND; + } + + /*If handle is 0, we want to find first empty context and return the index. + If handle is non zero, return the index that matches */ + for (index = 0; index < MAX_SOCKETS_SUPPORTED; index++) + { + if ((uint32_t)ath_sock_context[index]->handle == handle) + return index; + } + /*Index not found*/ + return SOCKET_NOT_FOUND; +} + +/*****************************************************************************/ +/* socket_context_init - Initializes common socket context, called during + * driver init. + * + * Returns- A_OK in case of successful init, A_ERROR otherwise + *****************************************************************************/ +A_STATUS socket_context_init(void) +{ + SOCKET_CONTEXT_PTR pcustctxt = NULL; + uint32_t index = 0; + + for (index = 0; index < MAX_SOCKETS_SUPPORTED + 1; index++) + { + /*Allocate socket contexts*/ + if ((ath_sock_context[index] = A_MALLOC(sizeof(ATH_SOCKET_CONTEXT), MALLOC_ID_CONTEXT)) == NULL) + return A_NO_MEMORY; + + memset(ath_sock_context[index], 0, sizeof(ATH_SOCKET_CONTEXT)); + } + + for (index = 0; index < MAX_SOCKETS_SUPPORTED + 1; index++) + { + if ((pcustctxt = A_MALLOC(sizeof(SOCKET_CONTEXT), MALLOC_ID_CONTEXT)) == NULL) + { + return A_NO_MEMORY; + } + memset(pcustctxt, 0, sizeof(SOCKET_CONTEXT)); + A_EVENT_INIT(&pcustctxt->sockRxWakeEvent, kEventManualClear); + A_EVENT_INIT(&pcustctxt->sockTxWakeEvent, kEventManualClear); + + A_NETBUF_QUEUE_INIT(&(pcustctxt->rxqueue)); + + pcustctxt->blockFlag = 0; + pcustctxt->respAvailable = false; + ath_sock_context[index]->sock_context = pcustctxt; + ath_sock_context[index]->remaining_bytes = 0; + ath_sock_context[index]->old_netbuf = NULL; + +#if NON_BLOCKING_TX + A_NETBUF_QUEUE_INIT(&(pcustctxt->non_block_queue)); + A_MUTEX_INIT(&pcustctxt->nb_tx_mutex); +#endif + } + +#if ZERO_COPY + /*Initilize common queue used to store Rx packets for zero copy option*/ + A_NETBUF_QUEUE_INIT(&zero_copy_free_queue); +#endif + + return A_OK; +} + +/*****************************************************************************/ +/* socket_context_deinit - De-initializes common socket context, called during + * driver deinit. + *****************************************************************************/ +void socket_context_deinit(void) +{ + uint32_t index = 0; + SOCKET_CONTEXT_PTR pcustctxt = NULL; + + for (index = 0; index < MAX_SOCKETS_SUPPORTED + 1; index++) + { + A_FREE(ath_sock_context[index], MALLOC_ID_CONTEXT); + ath_sock_context[index] = NULL; + } + /*Free the custom context as well*/ + + for (index = 0; index < MAX_SOCKETS_SUPPORTED + 1; index++) + { + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); +#if NON_BLOCKING_TX + A_MUTEX_DELETE(&pcustctxt->nb_tx_mutex); +#endif + A_EVENT_DELETE(&pcustctxt->sockRxWakeEvent); + A_EVENT_DELETE(&pcustctxt->sockTxWakeEvent); + A_FREE(pcustctxt, MALLOC_ID_CONTEXT); + } +} + +/*****************************************************************************/ +/* Api_SockResponseEventRx - Handler for WMI socket receive events. + * void *pCxt - driver context + * uint8_t *datap - pointer to incoming event data + * uint32_t len - length of event data + *****************************************************************************/ +A_STATUS Api_SockResponseEventRx(void *pCxt, uint8_t devId, uint8_t *datap, uint32_t len, void *pReq) +{ + int32_t index = 0; + uint8_t unblock_flag = 0; + WMI_SOCK_RESPONSE_EVENT *response = (WMI_SOCK_RESPONSE_EVENT *)datap; + uint32_t resp_type = A_CPU2LE32(response->resp_type); + A_STATUS status = A_OK; + uint8_t freeBuf = 1; + + switch (resp_type) + { + case SOCK_OPEN: + index = find_socket_context(SOCKET_HANDLE_PLACEHOLDER, true); + + if (index < 0 || index > MAX_SOCKETS_SUPPORTED) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + status = A_ERROR; + break; + } + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Store the newly created socket handle*/ + ath_sock_context[index]->handle = A_CPU2LE32(response->sock_handle); + /* unlock the application thread*/ + unblock_flag = 1; + } + break; + + case SOCK_ACCEPT: + index = find_socket_context(A_CPU2LE32(response->sock_handle), true); + + if (index < 0 || index > MAX_SOCKETS_SUPPORTED) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + status = A_ERROR; + break; + } + + /*Check if a socket is waiting on the response*/ + // if(SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy incoming socket related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->pReq = pReq; + + /*Store the response in socket context result field*/ + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + unblock_flag = 1; + } + freeBuf = 0; + UNBLOCK_SELECT(pCxt); + } + break; + case SOCK_CLOSE: + /* A socket close event may be received under two scenarios- + 1. In response to explicit socket close request from host. + 2. An unsolicited socket close to close a socket created earlier for + an incoming TCP connection + In the first scenario, the application thread is waiting for the response, + so unblock the thread. + In the second case, just cleanup the socket context*/ + + index = find_socket_context(A_CPU2LE32(response->sock_handle), true); + + if (index < 0 || index > MAX_SOCKETS_SUPPORTED) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + status = A_ERROR; + break; + } + + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /* the blocked flag will clear the context. clearing + * the context here will erase the mask which would + * break up the task synchronization. */ + /*unlock the thread*/ + unblock_flag = 1; + /*Store the response in socket context result field*/ + ath_sock_context[index]->result = A_CPU2LE32(response->error); + } + else + { + /* Case 2: clear the context here, no one is waiting */ + if(QUEUE_EMPTY(index)) { + clear_socket_context(index); + } + else + { + ath_sock_context[index]->TCPCtrFlag = TCP_FIN; + } +#if T_SELECT_VER1 + // Asynchronous sock_close event. + // printf("Asynch SOCK Close for socket index %d\n", index); + // SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_CLOSE); + UNBLOCK_SELECT(pCxt); +#endif // T_SELECT_VER1 + } + break; + case SOCK_CONNECT: + index = find_socket_context(A_CPU2LE32(response->sock_handle), true); + + if (index < 0 || index > MAX_SOCKETS_SUPPORTED) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + status = A_ERROR; + break; + } + /*Store the response in socket context result field*/ + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*unlock the thread*/ + unblock_flag = 1; + } + else + { + if (A_CPU2LE32(response->error) == TCP_CONNECTION_AVAILABLE) + { + /*Special case: async listen event has been received indicating a new + TCP connection is available. The User thread may be blocked with a select + call, set the unblock_flag so the user thread can be unlocked*/ + unblock_flag = 1; + } + } + UNBLOCK_SELECT(pCxt); + break; + + case SOCK_BIND: + case SOCK_LISTEN: + /*Listen Event may be received in two cases: + Case 1: In response to a listen request from host, that puts TCP socket in + Listen state. + Case 2: An unsolicited listen with a result value TCP_CONNECTION_AVAILABLE, + that informs an application thread that a new TCP connection is + available. This allows the application to call accept.*/ + case SOCK_ERRNO: + case SOCK_SETSOCKOPT: + index = find_socket_context(A_CPU2LE32(response->sock_handle), true); + + if (index < 0 || index > MAX_SOCKETS_SUPPORTED) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + status = A_ERROR; + break; + } + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Store the response in socket context result field*/ + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + else + { + if (A_CPU2LE32(response->error) == TCP_CONNECTION_AVAILABLE) + { + /*Special case: async listen event has been received indicating a new + TCP connection is available. The User thread may be blocked with a select + call, set the unblock_flag so the user thread can be unlocked*/ + ath_sock_context[index]->result = A_CPU2LE32(response->error); + unblock_flag = 1; + } + } + break; + case SOCK_GETSOCKOPT: + index = find_socket_context(A_CPU2LE32(response->sock_handle), true); + + if (index < 0 || index > MAX_SOCKETS_SUPPORTED) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + status = A_ERROR; + break; + } + + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*Copy select related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->pReq = pReq; + /* unlock the application thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_IPCONFIG: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->pReq = pReq; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_PING: + case SOCK_PING6: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + + break; + case SOCK_IP6CONFIG: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; +#if ENABLE_HTTP_SERVER + case SOCK_HTTP_SERVER: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + break; + case SOCK_HTTP_SERVER_CMD: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->pReq = pReq; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*Copy select related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_HTTP_POST_EVENT: + CUSTOM_API_HTTP_POST_EVENT(pCxt, response->data); + break; +#endif +#if ENABLE_HTTP_CLIENT + case SOCK_HTTPC: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->pReq = pReq; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*Copy select related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + // printf("Received http client resp :%d req %x\n", ath_sock_context[index]->result, + // ath_sock_context[index]->pReq); + break; +#endif /* ENABLE_HTTP_CLIENT */ + case SOCK_DNC_CMD: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_DNC_ENABLE: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + case SOCK_DNS_SRVR_CFG_ADDR: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + break; + case SOCK_IP_HOST_NAME: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + break; + case SOCK_IP_DNS: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + break; + case SOCK_IP_SNTP_GET_TIME: + index = GLOBAL_SOCK_INDEX; + // printf("resp from sntp \r\n"); + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + //("unblock\r\n"); + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_IP_SNTP_GET_TIME_OF_DAY: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + //("unblock\r\n"); + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_IP_SNTP_QUERY_SNTP_ADDRESS: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + //("unblock\r\n"); + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_IPV4_ROUTE: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_IPV6_ROUTE: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; +#if ENABLE_SSL + case SOCK_SSL_SET_FD: + case SOCK_SSL_ACCEPT: + case SOCK_SSL_CONNECT: + index = find_socket_context_from_ssl((SSL *)response->sock_handle); // ssl context + if (index == SOCKET_NOT_FOUND) + { + /* We send the configure command on the "global socket" if the configure is + * done before the socket is created */ + index = GLOBAL_SOCK_INDEX; + } + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + break; + + case SOCK_SSL_CONFIGURE: + case SOCK_SSL_SHUTDOWN: + index = find_socket_context_from_ssl((SSL *)response->sock_handle); // ssl context + if (index == SOCKET_NOT_FOUND) + { + index = GLOBAL_SOCK_INDEX; + } + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + break; + + case SOCK_SSL_CTX_NEW: + case SOCK_SSL_CTX_FREE: + case SOCK_SSL_NEW: + case SOCK_SSL_ADD_CERT: + case SOCK_SSL_STORE_CERT: + case SOCK_SSL_LOAD_CERT: + index = GLOBAL_SOCK_INDEX; + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + } + break; + + case SOCK_SSL_LIST_CERT: + index = GLOBAL_SOCK_INDEX; + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + ath_sock_context[index]->pReq = pReq; + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; +#endif + case SOCK_OTA_UPGRADE: + case SOCK_OTA_READ: + case SOCK_OTA_DONE: + case SOCK_OTA_SESSION_START: + case SOCK_OTA_PARTITION_GET_SIZE: + case SOCK_OTA_PARTITION_ERASE: + case SOCK_OTA_PARTITION_VERIFY_CHECKSUM: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + break; + case SOCK_OTA_PARSE_IMAGE_HDR: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + else + { + tOtaParseImageHdrResp *tmp_resp = (tOtaParseImageHdrResp*)response->data; + Custom_Api_Ota_Resp_Result(pCxt, SOCK_OTA_PARSE_IMAGE_HDR, + tmp_resp->resp_code, + tmp_resp->offset); + } + break; + case SOCK_OTA_PARTITION_WRITE_DATA: + index = GLOBAL_SOCK_INDEX; + /*Check if a socket is waiting on the response*/ + if (SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)) + { + /*Copy ipconfig related information*/ + ath_sock_context[index]->data = response->data; + ath_sock_context[index]->result = A_CPU2LE32(response->error); + ath_sock_context[index]->pReq = pReq; + /*unlock the thread*/ + unblock_flag = 1; + freeBuf = 0; + } + else + { + tOtaPartitionWriteDataResp *tmp_resp = (tOtaPartitionWriteDataResp*)response->data; + Custom_Api_Ota_Resp_Result(pCxt, SOCK_OTA_PARTITION_WRITE_DATA, + tmp_resp->resp_code, + tmp_resp->size); + } + break; + case SOCK_DHCPS_SUCCESS_CALLBACK: + Custom_Api_Dhcps_Success_Callback_Event(pCxt, response->data); + break; + case SOCK_DHCPC_SUCCESS_CALLBACK: + Custom_Api_Dhcpc_Success_Callback_Event(pCxt, response->data); + break; + default: + last_driver_error = A_UNKNOWN_CMD; + status = A_ERROR; + break; + } + /* if a user task is blocked on this event then unblock it. */ + if (unblock_flag /* && SOCK_EV_MASK_TEST(ath_sock_context[index], resp_type)*/) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], resp_type); + UNBLOCK(ath_sock_context[index], RX_DIRECTION); + } + + if (freeBuf) + { + /*Free the netbuf*/ + A_NETBUF_FREE(pReq); + } + return status; +} + +/*****************************************************************************/ +/* getIPLength - Calculates total IP header length. + * uint8_t version - IP version + * Returns- IP header length + *****************************************************************************/ +uint32_t getIPLength(uint8_t version) +{ + uint32_t length = 0; + switch (version) + { + case ATH_AF_INET: + length = IPV4_HEADER_LENGTH; + break; + + case ATH_AF_INET6: + length = IPV6_HEADER_LENGTH; + break; + default: + break; + } + + return length; +} + +/*****************************************************************************/ +/* getTransportLength - Calculates Transport layer header length + * uint8_t proto - UDP or TCP + * Returns- Transport layer header length + *****************************************************************************/ +uint32_t getTransportLength(uint8_t proto) +{ + uint32_t length = 0; + switch (proto) + { + case SOCK_STREAM_TYPE: + length = TCP_HEADER_LENGTH; + break; + + case SOCK_DGRAM_TYPE: + length = UDP_HEADER_LENGTH; + break; + default: + break; + } + + return length; +} + +/*****************************************************************************/ +/* Api_socket - API to create new socket + * void *pCxt- driver context + * uint32_t domain- IPv4, IPv6 + * uint32_t type- TCP, UDP + * uint32_t protocol- + * Returns- socket handle in case of success, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_socket(void *pCxt, uint32_t domain, uint32_t type, uint32_t protocol) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_OPEN_T sock_open; + int32_t index = 0; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + osMutexAcquire(pDCxt->apiMutex, osWaitForever); + + do + { + /*Create new context*/ + if ((index = find_socket_context(EMPTY_SOCKET_CONTEXT, false)) != SOCKET_NOT_FOUND) + { + ath_sock_context[index]->handle = SOCKET_HANDLE_PLACEHOLDER; + ath_sock_context[index]->domain = domain; + ath_sock_context[index]->type = type; + } + else + { + last_driver_error = A_SOCK_UNAVAILABLE; + result = A_ERROR; + break; + } + + /*Create socket open wmi message*/ + sock_open.domain = A_CPU2LE32(domain); + sock_open.type = A_CPU2LE32(type); + sock_open.protocol = A_CPU2LE32(protocol); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OPEN); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OPEN, (void *)(&sock_open), sizeof(SOCK_OPEN_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OPEN); + /*Command failed, clear socket context and return error*/ + clear_socket_context(index); + result = A_ERROR; + break; + } + + /*Wait for response from target*/ + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OPEN)); + + /* Generic error reported in handle field */ + if (ath_sock_context[index]->handle == A_ERROR) + { + /*Socket not created, return error*/ + clear_socket_context(index); + result = A_ERROR; + break; + } +// /* 'handle' 0 means (probably) not enough resources */ +// else if (ath_sock_context[index]->handle == 0) +// { +// /*Socket not created, return error*/ +// clear_socket_context(index); +// result = A_RESOURCES; +// break; +// } + /* cosider any other number as valid 'handle' reference */ + else + { + result = ath_sock_context[index]->handle; + } + } while (0); + + osMutexRelease(pDCxt->apiMutex); + + return result; +} + +/*****************************************************************************/ +/* Api_shutdown - Close a previously opened socket + * void *pCxt- driver context + * uint32_t handle- socket handle + * Returns- 0 in case of successful shutdown, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_shutdown(void *pCxt, uint32_t handle) +{ + SOCK_CLOSE_T sock_close; + int32_t index = 0; + A_DRIVER_CONTEXT *pDCxt; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_SOCK_INVALID; + break; + } + + /*Check if some other thread is wating on this socket*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_CLOSE); + + /*Delete all pending packets in the receive queue*/ + CUSTOM_PURGE_QUEUE(index); + + /*Create a socket close wmi message*/ + sock_close.handle = A_CPU2LE32(handle); + /* set the sock_st_flags before calling wmi_ to avoid possible race conditions */ + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_CLOSE, (void *)(&sock_close), sizeof(SOCK_CLOSE_T)) != A_OK) + { + /* clear the flag that would have been cleared by receiving the event */ + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_CLOSE); + result = A_ERROR; + break; + } + +#if 1 + /* Wait for response from target */ + do { + if(BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) { + A_ASSERT(0); + } + } while(SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_CLOSE)); +#endif + + result = ath_sock_context[index]->result; + /* Delete all pending packets */ + CUSTOM_PURGE_QUEUE(index); + + /* clear the socket to make it available for re-use */ + clear_socket_context(index); + } while (0); + + return result; +} + +/*****************************************************************************/ +/* Api_connect - API to connect to a peer + * void *pCxt- driver context + * uint32_t handle- socket handle + * void* name- sock addr structure + * uint16_t length- sock add length + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_connect(void *pCxt, uint32_t handle, void *name, uint16_t length) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_CONNECT_CMD_T sock_connect; + int32_t index = 0; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Retrieve context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + sock_connect.handle = A_CPU2LE32(handle); + sock_connect.length = A_CPU2LE16(length); + + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + sock_connect.addr.name.sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + sock_connect.addr.name.sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + sock_connect.addr.name.sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + } + else + { + sock_connect.addr.name6.sin6_port = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_port); + sock_connect.addr.name6.sin6_family = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_family); + sock_connect.addr.name6.sin6_flowinfo = A_CPU2LE32(((SOCKADDR_6_T *)name)->sin6_flowinfo); + A_MEMCPY((uint8_t *)&(sock_connect.addr.name6.sin6_addr), (uint8_t *)&((SOCKADDR_6_T *)name)->sin6_addr, + sizeof(IP6_ADDR_T)); + } + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_CONNECT); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_CONNECT, (void *)(&sock_connect), sizeof(SOCK_CONNECT_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_CONNECT); + result = A_ERROR; + break; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_CONNECT)); + result = ath_sock_context[index]->result; + if (A_OK == result) + { + ath_sock_context[index]->TCPCtrFlag = TCP_CONNECTED; + } + } while (0); + + return result; +} + +// Non blocking version of connect +int32_t Api_connect_nb(void *pCxt, uint32_t handle, void *name, uint16_t length) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_CONNECT_CMD_T sock_connect; + int32_t index = 0; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Retrieve context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + sock_connect.handle = A_CPU2LE32(handle); + sock_connect.length = A_CPU2LE16(length); + + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + sock_connect.addr.name.sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + sock_connect.addr.name.sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + sock_connect.addr.name.sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + } + else + { + sock_connect.addr.name6.sin6_port = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_port); + sock_connect.addr.name6.sin6_family = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_family); + sock_connect.addr.name6.sin6_flowinfo = A_CPU2LE32(((SOCKADDR_6_T *)name)->sin6_flowinfo); + A_MEMCPY((uint8_t *)&(sock_connect.addr.name6.sin6_addr), (uint8_t *)&((SOCKADDR_6_T *)name)->sin6_addr, + sizeof(IP6_ADDR_T)); + } + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_CONNECT, (void *)(&sock_connect), sizeof(SOCK_CONNECT_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_CONNECT); + result = A_ERROR; + break; + } + + } while (0); + + return result; +} + +/*****************************************************************************/ +/* Api_bind - API to bind to an interface. Works for both IPv4 and v6, name + * field must be populated accordingly. + * void *pCxt- driver context + * uint32_t handle- socket handle + * void* name- sock addr structure + * uint16_t length- sock add length + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_bind(void *pCxt, uint32_t handle, void *name, uint16_t length) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_BIND_CMD_T sock_bind; + int32_t index = 0; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + sock_bind.handle = A_CPU2LE32(handle); + sock_bind.length = A_CPU2LE16(length); + + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + sock_bind.addr.name.sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + sock_bind.addr.name.sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + sock_bind.addr.name.sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + } + else + { + sock_bind.addr.name6.sin6_port = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_port); + sock_bind.addr.name6.sin6_family = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_family); + sock_bind.addr.name6.sin6_flowinfo = A_CPU2LE32(((SOCKADDR_6_T *)name)->sin6_flowinfo); + A_MEMCPY((uint8_t *)&(sock_bind.addr.name6.sin6_addr), (uint8_t *)&((SOCKADDR_6_T *)name)->sin6_addr, + sizeof(IP6_ADDR_T)); + } + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_BIND); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_BIND, (void *)(&sock_bind), sizeof(SOCK_BIND_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_BIND); + result = A_ERROR; + break; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_BIND)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* Api_listen - API to Listen for incoming connections. Only used on stream sockets + * Works for both IPv4 and v6. + * void *pCxt- driver context + * uint32_t handle- socket handle + * uint32_t backlog- backlog of pending connections. The backlog parameter defines + * the maximum length for the queue of pending connections + * Returns- 0 in case of success, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_listen(void *pCxt, uint32_t handle, uint32_t backlog) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_LISTEN_T sock_listen; + int32_t index = 0; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + sock_listen.handle = A_CPU2LE32(handle); + sock_listen.backlog = A_CPU2LE16(backlog); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_LISTEN, (void *)(&sock_listen), sizeof(SOCK_LISTEN_T)) != A_OK) + { + result = A_ERROR; + break; + } + + // result = ath_sock_context[index]->result; + } while (0); + + if (index >= 0 && result == A_OK) + { + ath_sock_context[index]->TCPCtrFlag = TCP_LISTEN; + } + else + { + // TODO: fixme, how to handle this case !!! + assert(0); + } + + return result; +} + +/*****************************************************************************/ +/* Api_accept - API to accept incoming inconnections. Works for both IPv4 and v6, + * name field must be populated accordingly. Must call select to wait + * for incoming connection before calling this API. + * void *pCxt- driver context + * uint32_t handle- socket handle + * void* name- sock addr structure + * uint16_t length- sock add length + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_accept(void *pCxt, uint32_t handle, void *name, socklen_t length) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_ACCEPT_CMD_T sock_accept; + int32_t index = 0; + int32_t accept_index = 0; + int32_t result = A_OK; + uint8_t free_buf = 1; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + free_buf = 0; + break; + } + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + free_buf = 0; + break; + } + /* prepare wmi accept structure*/ + sock_accept.handle = A_CPU2LE32(handle); + sock_accept.length = A_CPU2LE16(length); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_ACCEPT); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_ACCEPT, (void *)(&sock_accept), sizeof(SOCK_ACCEPT_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_ACCEPT); + result = A_ERROR; + free_buf = 0; + break; + } + + /*Block until stack provides a response*/ + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_ACCEPT)); + + if (ath_sock_context[index]->result == TCP_CONNECTION_AVAILABLE) + { + /*Special case: Received TCP_CONN_AVAILABLE from target in response to accept, call + Accept again to create new connection, free the previos netbuf*/ + if (free_buf) + { + /*Free the netbuf*/ + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + /*Target stack indicates that a new TCP connection is available, accept it*/ + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_ACCEPT); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_ACCEPT, (void *)(&sock_accept), sizeof(SOCK_ACCEPT_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_ACCEPT); + result = A_ERROR; + free_buf = 0; + break; + } + + /*Block until stack provides a response*/ + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_ACCEPT)); + } + + if (ath_sock_context[index]->result != A_ERROR) + { + /*Create new context*/ + if ((accept_index = find_socket_context(EMPTY_SOCKET_CONTEXT, false)) != SOCKET_NOT_FOUND) + { + ath_sock_context[accept_index]->handle = ath_sock_context[index]->result; + ath_sock_context[accept_index]->domain = ath_sock_context[index]->domain; + ath_sock_context[accept_index]->type = ath_sock_context[index]->type; + } + else + { + last_driver_error = A_SOCK_UNAVAILABLE; + result = A_ERROR; + break; + } + + if (ath_sock_context[index]->data != NULL) + { + /*Based on IPv4 vs IPv6, fill in name fields*/ + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + A_MEMCPY(name, &((SOCK_ACCEPT_RECV_T *)(ath_sock_context[index]->data))->addr.name, + sizeof(SOCKADDR_T)); + ((SOCKADDR_T *)name)->sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + ((SOCKADDR_T *)name)->sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + ((SOCKADDR_T *)name)->sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + + if (SOCK_STREAM_TYPE == ath_sock_context[accept_index]->type) + { + ath_sock_context[accept_index]->TCPCtrFlag = TCP_CONNECTED; + } + } + else + { + A_MEMCPY(name, &((SOCK_ACCEPT_RECV_T *)(ath_sock_context[index]->data))->addr.name6, + sizeof(SOCKADDR_6_T)); + ((SOCKADDR_6_T *)name)->sin6_port = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_port); + ((SOCKADDR_6_T *)name)->sin6_family = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_family); + + if (SOCK_STREAM_TYPE == ath_sock_context[accept_index]->type) + { + ath_sock_context[accept_index]->TCPCtrFlag = TCP_CONNECTED; + } + } + // A_FREE(ath_sock_context[index]->data, MALLOC_ID_CONTEXT); + // ath_sock_context[index]->data = NULL; + + ath_sock_context[index]->data = NULL; + } + } + result = ath_sock_context[index]->result; + } while (0); + + if (free_buf) + { + /*Free the netbuf*/ + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + return result; +} + +#if T_SELECT_VER1 + +// Non blocking accept +int32_t Api_accept_ver1(void *pCxt, uint32_t handle, void *name, socklen_t length) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_ACCEPT_CMD_T sock_accept; + int32_t index = 0; + int32_t accept_index = 0; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + // The accept was issued earlier and the result of accept is avaible here + if ((ath_sock_context[index]->result != TCP_CONNECTION_AVAILABLE) && (ath_sock_context[index]->data != NULL)) + { + /*Create new context*/ + if ((accept_index = find_socket_context(EMPTY_SOCKET_CONTEXT, false)) != SOCKET_NOT_FOUND) + { + ath_sock_context[accept_index]->handle = ath_sock_context[index]->result; + ath_sock_context[accept_index]->domain = ath_sock_context[index]->domain; + ath_sock_context[accept_index]->type = ath_sock_context[index]->type; + } + else + { + last_driver_error = A_SOCK_UNAVAILABLE; + result = A_ERROR; + break; + } + if (ath_sock_context[index]->data != NULL) + { + /*Based on IPv4 vs IPv6, fill in name fields*/ + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + A_MEMCPY(name, &((SOCK_ACCEPT_RECV_T *)(ath_sock_context[index]->data))->addr.name, + sizeof(SOCKADDR_T)); + ((SOCKADDR_T *)name)->sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + ((SOCKADDR_T *)name)->sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + ((SOCKADDR_T *)name)->sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + } + else + { + A_MEMCPY(name, &((SOCK_ACCEPT_RECV_T *)(ath_sock_context[index]->data))->addr.name6, + sizeof(SOCKADDR_6_T)); + ((SOCKADDR_6_T *)name)->sin6_port = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_port); + ((SOCKADDR_6_T *)name)->sin6_family = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_family); + } + // A_FREE(ath_sock_context[index]->data, MALLOC_ID_CONTEXT); + // ath_sock_context[index]->data = NULL; + + ath_sock_context[index]->data = NULL; + } + result = ath_sock_context[index]->result; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + else + { + /* prepare wmi accept structure*/ + sock_accept.handle = A_CPU2LE32(handle); + sock_accept.length = A_CPU2LE16(length); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_ACCEPT); + + // This is a non-blocking accept + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_ACCEPT, (void *)(&sock_accept), sizeof(SOCK_ACCEPT_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_ACCEPT); + result = A_ERROR; + break; + } + } + } while (0); + + return result; +} +#endif // T_SELECT_VER1 + +/*****************************************************************************/ +/* Api_errno - API to fetch last error code from target + * + * void *pCxt- driver context + * uint32_t handle- socket handle + * Returns- error code in case of success, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_errno(void *pCxt, uint32_t handle) +{ + A_DRIVER_CONTEXT *pDCxt; + int32_t index = 0; + int32_t result = A_OK; + SOCK_ERRNO_T sock_errno; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + sock_errno.errno = A_CPU2LE32(handle); + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_ERRNO); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_ERRNO, (uint8_t *)&sock_errno, sizeof(SOCK_ERRNO_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_ERRNO); + result = A_ERROR; + break; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_ERRNO)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* Api_select - + * + * void *pCxt- driver context + * uint32_t handle- socket handle + * uint32_t tv - time to wait in milliseconds + * Returns- 0 in case of successful connect, A_ERROR otherwise + * Select can be called to check for incoming connections or for incoming data. + * It waits for a specified time period before returning. This call does not + * propagate to the target, it is consumed in the host. + *****************************************************************************/ +int32_t Api_select(void *pCxt, uint32_t handle, uint32_t tv) +{ + int32_t index = 0; + int32_t result = A_OK; + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_SOCK_INVALID; + break; + } + + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + if ((ath_sock_context[index]->type == SOCK_STREAM_TYPE) && (ath_sock_context[index]->remaining_bytes != 0) && + (ath_sock_context[index]->old_netbuf != NULL)) + { + result = A_OK; + break; + } + /*Packet is available, return*/ + if (!QUEUE_EMPTY(index)) + { + result = A_OK; + break; + } + + if (ath_sock_context[index]->TCPCtrFlag == TCP_FIN) + { + if (QUEUE_EMPTY(index)) + { + clear_socket_context(index); + result = A_SOCK_INVALID; + // Why on earth is this here? (MMJ) + // OS_INT_ENABLE(0); + break; + } + } + + if (ath_sock_context[index]->TCPCtrFlag == TCP_LISTEN) + { + /*Wait for specified time*/ + if (BLOCK(pCxt, ath_sock_context[index], tv, RX_DIRECTION) != A_OK) + { + /*Check if Peer closed socket while we were waiting*/ + if (ath_sock_context[index]->handle == 0) + { + result = A_SOCK_INVALID; + break; + } + /*Timeout, no activity detected*/ + result = A_ERROR; + } + else + { + /*Something is available, it may be a new incoming connection or data*/ + if ((!QUEUE_EMPTY(index)) || (ath_sock_context[index]->result == TCP_CONNECTION_AVAILABLE)) + { + ath_sock_context[index]->result = 0; + result = A_OK; + } + else + { + result = A_ERROR; + } + } + } + else + { + /*Wait for specified time*/ + if (BLOCK_FOR_DATA(pCxt, ath_sock_context[index], tv, RX_DIRECTION) != A_OK) + { + /*Check if Peer closed socket while we were waiting*/ + if (ath_sock_context[index]->handle == 0) + { + result = A_SOCK_INVALID; + break; + } + /*Timeout, no activity detected*/ + result = A_ERROR; + } + else + { + /*Something is available, it may be a new incoming connection or data*/ + if ((!QUEUE_EMPTY(index)) || (ath_sock_context[index]->result == TCP_CONNECTION_AVAILABLE)) + { + ath_sock_context[index]->result = 0; + result = A_OK; + } + else + { + result = A_ERROR; + } + } + } + } while (0); + return result; +} + +#if T_SELECT_VER1 +/*****************************************************************************/ +/* Api_select - + * + * void *pCxt- driver context + * uint32_t handle- socket handle + * uint32_t tv - time to wait in milliseconds + * Returns- 0 in case of successful connect, A_ERROR otherwise + * Select can be called to check for incoming connections or for incoming data. + * It waits for a specified time period before returning. This call does not + * propagate to the target, it is consumed in the host. + *****************************************************************************/ + +int32_t Api_select_ver1(void *pCxt, int32_t num, uint32_t *r_fd, uint32_t *w_fd, uint32_t *e_fd, uint32_t tv) +{ + int32_t index = 0; + int32_t result = 0; + int32_t first_time = 1; + uint32_t r_mask, w_mask; + HTC_ENDPOINT_ID eid; + A_ENDPOINT_T *pEp; + static uint32_t next_txsock = 0; + uint32_t startsock; + uint8_t credits; + + w_mask = r_mask = 0; + + // w_fd and r_fd are used to return the socket indexes which have some + // activity. Take a backup and initialize them to zero + if (w_fd) + { + eid = Util_AC2EndpointID(pCxt, WMM_AC_BE); + pEp = Util_GetEndpoint(pCxt, eid); + credits = pEp->credits; + + if (credits > 0) /* Credits Available */ + { + /* Save the last serviced socket and start from the next one to avoid + * servicing the first socket alone in case of only one credit available + */ + startsock = next_txsock; + for (index = startsock; index < (MAX_SOCKETS_SUPPORTED + startsock); index++) + { + index %= MAX_SOCKETS_SUPPORTED; + if (w_mask & (1 << index)) + { + if (ath_sock_context[index]->handle != 0) + { + *w_fd |= 1 << index; + result += 1; + + next_txsock = index + 1; + credits--; + } + else + { + // STALE socket. Update the mask for this handle. The next + // read will return 0/-1 + *(w_fd) |= (1 << index); + result += 1; + } + } + /* If there are no credits, break */ + if (!credits) + break; + } + } /* credits > 0 */ + } /* w_mask */ + + if (r_fd) + { + r_mask = *r_fd; + *r_fd = 0; + } + + if ((w_mask == 0) && (r_mask == 0)) + { + // Nothing to do + return result; + } + +AGAIN: + // Check if we have enough credits + if (w_mask) + { + eid = Util_AC2EndpointID(pCxt, WMM_AC_BE); + pEp = Util_GetEndpoint(pCxt, eid); + if (pEp->credits > 0) + { + for (index = 0; index < MAX_SOCKETS_SUPPORTED; index++) + { + if (w_mask & (1 << index)) + { + *w_fd = 1 << index; + result += 1; + break; + } + } + } + } + + // Go through all read handles + if (r_mask) + { + for (index = 0; index < MAX_SOCKETS_SUPPORTED; index++) + { + if (r_mask & (1 << index)) + { + if (ath_sock_context[index]->handle != 0) + { +#if 0 + if(/*(ath_sock_context[index]->type == SOCK_STREAM_TYPE) && */ + (ath_sock_context[index]->remaining_bytes != 0) && + (ath_sock_context[index]->old_netbuf != NULL)) + { + //Update the mask for this handle + *(r_fd) |= (1<result == TCP_CONNECTION_AVAILABLE) || + (ath_sock_context[index]->data != NULL)) + { + // Update the mask for this handle + *(r_fd) |= (1 << index); + result += 1; + } + + // Update the mask for this handle. The next + // read will return 0/-1 + if (ath_sock_context[index]->TCPCtrFlag == TCP_FIN) + { + // Update the mask for this handle + *(r_fd) |= (1 << index); + result += 1; + } + } + else // if( (r_mask & (1<handle == 0) ) + { + // STALE socket. Update the mask for this handle. The next + // read will return 0/-1 + *(r_fd) |= (1 << index); + result += 1; + } + } + } + } + + // If no pending activity, wait for the time requested and again check for + // activity + if ((result == 0) && (first_time)) + { + first_time = 0; + // Wait for the specified time + if (BLOCK_SELECT(pCxt, tv) == A_OK) + { + // Some activity happened because of which we were woken up. Figure + // out the activity and set the mask accordingly + goto AGAIN; + } + } + + return result; +} + +#endif + +/*****************************************************************************/ +/* Api_setsockopt - API to set specified socket option + * name field must be populated accordingly. + * void *pCxt- driver context + * uint32_t handle- socket handle + * uint32_t level- option level + * uint32_t optname- option name + * uint32_t optlen- option length + * Returns- 0 in case of success, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_setsockopt(void *pCxt, uint32_t handle, uint32_t level, uint32_t optname, uint8_t *optval, uint32_t optlen) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_OPT_T *sockSetopt; + // uint8_t* data = NULL; + int32_t index = 0, total_length = 0; + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + total_length = sizeof(SOCK_OPT_T); + + if (optval != NULL && optlen != 0) + { + total_length += optlen - sizeof(uint8_t); + } + + /*Allocate space for option*/ + if ((sockSetopt = A_MALLOC(total_length, MALLOC_ID_CONTEXT)) == NULL) + { + result = A_NO_MEMORY; + break; + } + + if (optval != NULL && optlen != 0) + { + A_MEMCPY(sockSetopt->optval, optval, optlen); + } + + sockSetopt->handle = A_CPU2LE32(handle); + sockSetopt->level = A_CPU2LE32(level); + sockSetopt->optname = A_CPU2LE32(optname); + sockSetopt->optlen = A_CPU2LE32(optlen); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SETSOCKOPT); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SETSOCKOPT, (uint8_t *)sockSetopt, total_length) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SETSOCKOPT); + A_FREE(sockSetopt, MALLOC_ID_CONTEXT); + result = A_ERROR; + break; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SETSOCKOPT)); + + A_FREE(sockSetopt, MALLOC_ID_CONTEXT); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* Api_getsockopt - API to fetch specified socket option + * name field must be populated accordingly. + * void *pCxt- driver context + * uint32_t handle- socket handle + * uint32_t level- option level + * uint32_t optname- option name + * uint32_t optlen- option length + * Returns- 0 in case of success, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_getsockopt(void *pCxt, uint32_t handle, uint32_t level, uint32_t optname, uint8_t *optval, uint32_t optlen) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_OPT_T *sock_getopt = NULL; + uint32_t index = 0, total_length = 0; + int32_t result = A_OK; + uint8_t free_buf = 1; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Find context*/ + if ((int32_t)(index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + result = A_ERROR; + free_buf = 0; + break; + } + + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + free_buf = 0; + break; + } + /*Cannot call getsockopt with NULL*/ + if (optval == NULL || optlen == 0) + { + result = A_ERROR; + free_buf = 0; + break; + } + /*Total length depends upon the type of option*/ + total_length = sizeof(SOCK_OPT_T) + optlen - sizeof(uint8_t); + + /*Allocate buffer for option*/ + if ((sock_getopt = A_MALLOC(total_length, MALLOC_ID_CONTEXT)) == NULL) + { + result = A_NO_MEMORY; + free_buf = 0; + break; + } + + sock_getopt->handle = A_CPU2LE32(handle); + sock_getopt->level = A_CPU2LE32(level); + sock_getopt->optname = A_CPU2LE32(optname); + sock_getopt->optlen = A_CPU2LE32(optlen); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_GETSOCKOPT); + /*Send the packet*/ + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_GETSOCKOPT, (uint8_t *)sock_getopt, total_length) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_GETSOCKOPT); + result = A_ERROR; + free_buf = 0; + break; + } + + /*Wait for response from stack*/ + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_GETSOCKOPT)); + + if (ath_sock_context[index]->data != NULL) + { + A_MEMCPY(optval, ((SOCK_OPT_T *)ath_sock_context[index]->data)->optval, optlen); + // A_FREE(ath_sock_context[index]->data,MALLOC_ID_CONTEXT); + ath_sock_context[index]->data = NULL; //TODO: check possible leak !! + } + result = ath_sock_context[index]->result; + } while (0); + + A_FREE(sock_getopt, MALLOC_ID_CONTEXT); + + if (free_buf) + { + /*Free the netbuf*/ + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + + return result; +} + +/*****************************************************************************/ +/* Api_ipconfig - API to obtain IP address information from target + * void *pCxt- driver context + * uint32_t mode- query vs set + * uint32_t* ipv4_addrA_UINT32* subnetMask, uint32_t* gateway4 + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipconfig(void *pCxt, + uint32_t mode, + uint32_t *ipv4_addr, + uint32_t *subnetMask, + uint32_t *gateway4, + IP46ADDR *dnsaddr, + char *hostname) +{ + A_DRIVER_CONTEXT *pDCxt; + IPCONFIG_CMD_T ipcfg = {0}; + IPCONFIG_RECV_T *result; + uint32_t index = GLOBAL_SOCK_INDEX; // reserved for global commands ToDo- cleanup later + int32_t res = A_OK; + uint8_t free_buf = 1; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + res = A_ERROR; + free_buf = 0; + break; + } + if (IPCFG_STATIC == mode) + { + /*This is not a query or dhcp command*/ + ipcfg.mode = A_CPU2LE32(mode); + ipcfg.ipv4 = A_CPU2LE32(*ipv4_addr); + ipcfg.subnetMask = A_CPU2LE32(*subnetMask); + ipcfg.gateway4 = A_CPU2LE32(*gateway4); + } + else if (IPCFG_AUTO == mode) + { + ipcfg.ipv4 = A_CPU2LE32(*ipv4_addr); + } + ipcfg.mode = A_CPU2LE32(mode); + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IPCONFIG); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IPCONFIG, (void *)(&ipcfg), sizeof(IPCONFIG_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IPCONFIG); + res = A_ERROR; + free_buf = 0; + break; + } + + do + { + if (IPCFG_DHCP == mode) + { + if (BLOCK(pCxt, ath_sock_context[index], DHCP_WAIT_TIME, RX_DIRECTION) != A_OK) + { + return (int32_t)A_TIMEOUT; + } + } + else if (IPCFG_AUTO == mode) + { + if (BLOCK(pCxt, ath_sock_context[index], DHCP_AUTO_WAIT_TIME, RX_DIRECTION) != A_OK) + { + return (int32_t)A_TIMEOUT; + } + } + else + { + if (BLOCK(pCxt, ath_sock_context[index], IPCONFIG_WAIT_TIME, RX_DIRECTION) != A_OK) + { + return (int32_t)A_TIMEOUT; + } + } + + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IPCONFIG)); + + /*Got a response*/ + if (ath_sock_context[index]->result != -1) + { + result = (IPCONFIG_RECV_T *)(ath_sock_context[index]->data); + if (mode != 1) + { + if (ipv4_addr != NULL) + *ipv4_addr = A_CPU2LE32(result->ipv4); + if (subnetMask != NULL) + *subnetMask = A_CPU2LE32(result->subnetMask); + if (gateway4 != NULL) + *gateway4 = A_CPU2LE32(result->gateway4); + if (dnsaddr != NULL) + memcpy(dnsaddr, &result->dnsaddr, sizeof(result->dnsaddr)); + if (hostname != NULL) + strcpy(hostname, result->hostname); + } + } + res = ath_sock_context[index]->result; + } while (0); + + if (free_buf) + { + /*Free the netbuf*/ + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + return res; +} + +/*****************************************************************************/ +/* Api_ip6config - API to obtain IPv6 address information from target + * void *pCxt- driver context + * uint32_t mode- query vs set + * + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ip6config(void *pCxt, + uint32_t mode, + IP6_ADDR_T *v6Global, + IP6_ADDR_T *v6Link, + IP6_ADDR_T *v6DefGw, + IP6_ADDR_T *v6GlobalExtd, + int32_t *LinkPrefix, + int32_t *GlbPrefix, + int32_t *DefgwPrefix, + int32_t *GlbPrefixExtd) +{ + A_DRIVER_CONTEXT *pDCxt; + IPCONFIG_CMD_T ipcfg; + IPCONFIG_RECV_T *result; + uint32_t index = GLOBAL_SOCK_INDEX; // reserved for global commands ToDo- cleanup later + int32_t res = A_OK; + uint8_t free_buf = 1; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[GLOBAL_SOCK_INDEX])) + { + res = A_ERROR; + free_buf = 0; + break; + } + + ipcfg.mode = A_CPU2LE32(mode); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP6CONFIG); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP6CONFIG, (void *)(&ipcfg), sizeof(IPCONFIG_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP6CONFIG); + res = A_ERROR; + free_buf = 0; + break; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IP6CONFIG)); + + /*Got a response*/ + if (ath_sock_context[index]->result != -1) + { + result = (IPCONFIG_RECV_T *)(ath_sock_context[index]->data); + + A_MEMCPY(v6Global, &result->ipv6GlobalAddr, sizeof(IP6_ADDR_T)); + A_MEMCPY(v6Link, &result->ipv6LinkAddr, sizeof(IP6_ADDR_T)); + A_MEMCPY(v6DefGw, &result->ipv6DefGw, sizeof(IP6_ADDR_T)); + A_MEMCPY(v6GlobalExtd, &result->ipv6LinkAddrExtd, sizeof(IP6_ADDR_T)); + *LinkPrefix = A_CPU2LE32(result->LinkPrefix); + *GlbPrefix = A_CPU2LE32(result->GlbPrefix); + *DefgwPrefix = A_CPU2LE32(result->DefGwPrefix); + *GlbPrefixExtd = A_CPU2LE32(result->GlbPrefixExtd); + } + res = ath_sock_context[index]->result; + } while (0); + + if (free_buf) + { + /*Free the netbuf*/ + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + + return res; +} + +/*****************************************************************************/ +/* Api_ipconfig_dhcp_pool - API to configure dhcp pool + * void *pCxt- driver context + * uint32_t *start_ipv4_addr - Start ip address + * uint32_t* end_ipv4_addr int32_t leasetime + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipconfig_dhcp_pool(void *pCxt, uint32_t *start_ipv4_addr, uint32_t *end_ipv4_addr, int32_t leasetime) +{ + A_DRIVER_CONTEXT *pDCxt; + IPCONFIG_DHCP_POOL_T ipcfg; + uint32_t index = GLOBAL_SOCK_INDEX; // reserved for global commands ToDo- cleanup later + pDCxt = GET_DRIVER_COMMON(pCxt); + + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + ipcfg.startaddr = A_CPU2LE32(*start_ipv4_addr); + ipcfg.endaddr = A_CPU2LE32(*end_ipv4_addr); + ipcfg.leasetime = A_CPU2LE32(leasetime); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IPCONFIG_DHCP_POOL, (void *)(&ipcfg), sizeof(IPCONFIG_DHCP_POOL_T)) != A_OK) + { + return A_ERROR; + } + + return (A_OK); +} + +/*****************************************************************************/ +/* Api_ip6config_router_prefix - API to configure router prefix + * void *pCxt- driver context + * uint8_t *v6addr - v6prefix + * int32_t prefixlen int32_t prefix_lifetime ,int32_t valid_lifetime + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ip6config_router_prefix( + void *pCxt, IP6_ADDR_T *v6addr, int32_t prefixlen, int32_t prefix_lifetime, int32_t valid_lifetime) +{ + A_DRIVER_CONTEXT *pDCxt; + IP6CONFIG_ROUTER_PREFIX_T ip6cfg; + uint32_t index = GLOBAL_SOCK_INDEX; // reserved for global commands ToDo- cleanup later + pDCxt = GET_DRIVER_COMMON(pCxt); + + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMCPY(ip6cfg.v6addr, v6addr, sizeof(IP6_ADDR_T)); + ip6cfg.prefixlen = A_CPU2LE32(prefixlen); + ip6cfg.prefix_lifetime = A_CPU2LE32(prefix_lifetime); + ip6cfg.valid_lifetime = A_CPU2LE32(valid_lifetime); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP6CONFIG_ROUTER_PREFIX, (void *)(&ip6cfg), + sizeof(IP6CONFIG_ROUTER_PREFIX_T)) != A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +/*****************************************************************************/ +/* Api_ipbridgemode - API to enable bridge mode + * void *pCxt- driver context + * int32_t status - enable the bridge mode + * Returns- A_OK in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipbridgemode(void *pCxt, uint16_t status) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_BRIDGEMODE_T sock_ipbridgemode; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[GLOBAL_SOCK_INDEX])) + { + return A_ERROR; + } + sock_ipbridgemode.bridgemode = A_CPU2LE16(status); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_BRIDGEMODE, (void *)(&sock_ipbridgemode), sizeof(sock_ipbridgemode)) != + A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +/*****************************************************************************/ +/* Api_ipconfig_set_tcp_exponential_backoff_retry - API to tcp exponential backoff retry + * void *pCxt- driver context + * int32_t retry - No of MAX Retries + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipconfig_set_tcp_exponential_backoff_retry(void *pCxt, int32_t retry) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_BACKOFF_T sock_backoff; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[GLOBAL_SOCK_INDEX])) + { + return A_ERROR; + } + sock_backoff.max_retry = A_CPU2LE32(retry); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SET_TCP_EXP_BACKOFF_RETRY, (void *)(&sock_backoff), + sizeof(SOCK_IP_BACKOFF_T)) != A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +/*****************************************************************************/ +/* Api_ipconfig_set_ip6_status - API to set ip6 status + * void *pCxt- driver context + * uint16_t status - enable or diable + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipconfig_set_ip6_status(void *pCxt, uint16_t status) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IPv6_STATUS_T sock_ip6status; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[GLOBAL_SOCK_INDEX])) + { + return A_ERROR; + } + sock_ip6status.ipv6_status = A_CPU2LE16(status); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SET_IP6_STATUS, (void *)(&sock_ip6status), sizeof(sock_ip6status)) != + A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +/*****************************************************************************/ +/* Api_ipconfig_dhcp_release - API to release dhcp ip address + * void *pCxt- driver context + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipconfig_dhcp_release(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_DHCP_RELEASE_T release; + uint16_t ifindx = 0; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[GLOBAL_SOCK_INDEX])) + { + return A_ERROR; + } + release.ifIndex = A_CPU2LE16(ifindx); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_DHCP_RELEASE, (void *)(&release), sizeof(SOCK_IP_DHCP_RELEASE_T)) != + A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +int32_t Api_ipconfig_set_tcp_rx_buffer(void *pCxt, int32_t rxbuf) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_TCP_RX_BUF_T sock_tcp_rx_buf; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[GLOBAL_SOCK_INDEX])) + { + return A_ERROR; + } + sock_tcp_rx_buf.rxbuf = A_CPU2LE32(rxbuf); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SET_TCP_RX_BUF, (void *)(&sock_tcp_rx_buf), + sizeof(SOCK_IP_TCP_RX_BUF_T)) != A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +#if ENABLE_HTTP_SERVER +int32_t Api_ip_http_server(void *pCxt, int32_t command) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_HTTP_SERVER_T sock_http_server; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + sock_http_server.enable = A_CPU2LE32(command); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_HTTP_SERVER); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_HTTP_SERVER, (void *)(&sock_http_server), sizeof(SOCK_IP_HTTP_SERVER_T)) != + A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_HTTP_SERVER); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_HTTP_SERVER)); + + return (ath_sock_context[index]->result); +} + +int32_t Api_ip_http_server_method( + void *pCxt, int32_t command, uint8_t *pagename, uint8_t *objname, int32_t objtype, int32_t objlen, uint8_t *value) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_HTTP_SERVER_CMD_T sock_http_server; + int index = GLOBAL_SOCK_INDEX; + uint32_t *length; + uint8_t *buf; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + sock_http_server.command = A_CPU2LE32(command); + strcpy((char *)sock_http_server.pagename, (const char *)pagename); + strcpy((char *)sock_http_server.objname, (const char *)objname); + sock_http_server.objlen = A_CPU2LE32(objlen); + if (command == HTTP_POST_METHOD) /* For POST command */ + strcpy((char *)sock_http_server.value, (const char *)value); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_HTTP_SERVER_CMD); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_HTTP_SERVER_CMD, (void *)(&sock_http_server), + sizeof(SOCK_IP_HTTP_SERVER_CMD_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_HTTP_SERVER_CMD); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_HTTP_SERVER_CMD)); + + if ((ath_sock_context[index]->result != -1) && (command == HTTP_GET_METHOD)) + { + length = (uint32_t *)ath_sock_context[index]->data; + if (*length > 512) + A_ASSERT(0); + buf = (uint8_t *)(length + 1); + A_MEMCPY(value, buf, *length); + value[*length] = '\0'; // NULL terminating the string + } + + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return (ath_sock_context[index]->result); +} +#endif + +#if ENABLE_HTTP_CLIENT +/*****************************************************************************/ +/* Api_httpc_method - API to use http client methods + * It is a non blocking call. Just sends the HTTP command and return + * void *pCxt- driver context + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ + +int32_t Api_httpc_method(void *pCxt, uint32_t command, uint8_t *url, uint8_t *data, uint8_t **output) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_HTTPC_T httpc; + int32_t index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + + memset(&httpc, 0, sizeof(httpc)); + + httpc.command = A_CPU2LE32(command); + if (url) + A_MEMCPY(httpc.url, url, strlen((const char *)url)); + if (data) + A_MEMCPY(httpc.data, data, strlen((const char *)data)); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_HTTPC); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_HTTPC, (void *)(&httpc), sizeof(SOCK_HTTPC_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_HTTPC); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_HTTPC)); + + if ((ath_sock_context[index]->result != A_ERROR) && (output != NULL)) + { + *output = ath_sock_context[index]->data; + // printf("Adding Q %p %p\n", ath_sock_context[index]->pReq, ath_sock_context[index]->data); + A_NETBUF_ENQUEUE(&zero_copy_free_queue, ath_sock_context[index]->pReq); + } + else + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return ath_sock_context[index]->result; +} + +#endif /* ENABLE_HTTP_CLIENT */ + +#if ENABLE_DNS_CLIENT +extern uint32_t dns_block_time; + +int32_t Api_ip_resolve_host_name(void *pCxt, DNC_CFG_CMD *DncCfg, DNC_RESP_INFO *DncRespInfo) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + int index = GLOBAL_SOCK_INDEX; + DNC_RESP_INFO *result = NULL; + int32_t res = A_OK; + uint8_t free_buf = 1; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + free_buf = 0; + return A_ERROR; + } + DncCfg->mode = A_CPU2LE32(DncCfg->mode); + DncCfg->domain = A_CPU2LE32(DncCfg->domain); + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_DNC_CMD); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_DNC_CMD, (void *)DncCfg, sizeof(DNC_CFG_CMD)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_DNC_CMD); + free_buf = 0; + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], dns_block_time, RX_DIRECTION) != A_OK) + { + // printf("dnsclient timed out \r\n"); + return -1; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_DNC_CMD)); + + if (ath_sock_context[index]->result != -1) + { + result = (DNC_RESP_INFO *)(ath_sock_context[index]->data); + A_MEMCPY(DncRespInfo, result, sizeof(DNC_RESP_INFO)); + } + res = ath_sock_context[index]->result; + /*Free the netbuf*/ + if (free_buf) + { + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + return res; +} + +int32_t Api_ip_dns_client(void *pCxt, int32_t command) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_DNS_CLIENT_T sock_dns_client; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + sock_dns_client.command = A_CPU2LE32(command); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_DNC_ENABLE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_DNC_ENABLE, (void *)(&sock_dns_client), sizeof(SOCK_IP_DNS_CLIENT_T)) != + A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_DNC_ENABLE); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_DNC_ENABLE)); + + return (ath_sock_context[index]->result); +} + +int32_t Api_ip_dns_server_addr(void *pCxt, IP46ADDR *addr) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_CFG_DNS_SRVR_ADDR sock_dns_srvr_addr; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + + if (addr->type == ATH_AF_INET) + { + sock_dns_srvr_addr.addr.type = ATH_AF_INET; + sock_dns_srvr_addr.addr.addr4 = addr->addr4; + sock_dns_srvr_addr.addr.au1Rsvd[0] = addr->au1Rsvd[0]; + } + if (addr->type == ATH_AF_INET6) + { + sock_dns_srvr_addr.addr.type = ATH_AF_INET6; + sock_dns_srvr_addr.addr.au1Rsvd[0] = addr->au1Rsvd[0]; + memcpy(&sock_dns_srvr_addr.addr.addr6, &addr->addr6, sizeof(IP6_ADDR_T)); + } + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_DNS_SRVR_CFG_ADDR); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_DNS_SRVR_CFG_ADDR, (void *)(&sock_dns_srvr_addr), + sizeof(SOCK_IP_CFG_DNS_SRVR_ADDR)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_DNS_SRVR_CFG_ADDR); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_DNS_SRVR_CFG_ADDR)); + + return (ath_sock_context[index]->result); +} +#endif /* ENABLE_DNS_CLIENT */ + +int32_t Api_ip_hostname(void *pCxt, char *domain_name) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_CFG_HOST_NAME sock_ip_host_name; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + strcpy(sock_ip_host_name.domain_name, domain_name); + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP_HOST_NAME); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_HOST_NAME, (void *)(&sock_ip_host_name), + sizeof(SOCK_IP_CFG_HOST_NAME)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP_HOST_NAME); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IP_HOST_NAME)); + + return (ath_sock_context[index]->result); +} + +#if ENABLE_DNS_SERVER + +int32_t Api_ip_dns_local_domain(void *pCxt, char *domain_name) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_CFG_DNS_LOCAL_DOMAIN sock_dns_local_domain; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + strcpy(sock_dns_local_domain.domain_name, domain_name); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_DNS_LOCAL_DOMAIN, (void *)(&sock_dns_local_domain), + sizeof(SOCK_IP_CFG_DNS_LOCAL_DOMAIN)) != A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +int32_t Api_ipdns(void *pCxt, int32_t command, char *domain_name, IP46ADDR *dnsaddr) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_DNS_T sock_ip_dns; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + memset(&sock_ip_dns, 0, sizeof(SOCK_IP_DNS_T)); + strcpy(sock_ip_dns.domain_name, domain_name); + sock_ip_dns.command = A_CPU2LE32(command); + // printf("api_dns addr type %d \r\n",dnsaddr->type); + if (dnsaddr->type == ATH_AF_INET) + { + sock_ip_dns.addr.type = ATH_AF_INET; + sock_ip_dns.addr.addr4 = dnsaddr->addr4; + sock_ip_dns.addr.au1Rsvd[0] = dnsaddr->au1Rsvd[0]; + } + if (dnsaddr->type == ATH_AF_INET6) + { + sock_ip_dns.addr.type = ATH_AF_INET6; + sock_ip_dns.addr.au1Rsvd[0] = dnsaddr->au1Rsvd[0]; + memcpy(&sock_ip_dns.addr.addr6, &dnsaddr->addr6, sizeof(IP6_ADDR_T)); + } + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP_DNS); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_DNS, (void *)(&sock_ip_dns), sizeof(SOCK_IP_DNS_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP_DNS); + return A_ERROR; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IP_DNS)); + + return (ath_sock_context[index]->result); +} + +int32_t Api_ip_dns_server(void *pCxt, int32_t command) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + + SOCK_IP_DNS_SERVER_STATUS_T sock_dns_server; + int index = GLOBAL_SOCK_INDEX; + pDCxt = GET_DRIVER_COMMON(pCxt); + + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + memset(&sock_dns_server, 0, sizeof(SOCK_IP_DNS_SERVER_STATUS_T)); + sock_dns_server.enable = A_CPU2LE32(command); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_DNS_SERVER_STATUS, (void *)(&sock_dns_server), + sizeof(SOCK_IP_DNS_SERVER_STATUS_T)) != A_OK) + { + return A_ERROR; + } + + return (A_OK); +} + +#endif /* ENABLE_DNS_SERVER */ + +#if ENABLE_SNTP_CLIENT +int32_t Api_ip_sntp_srvr_addr(void *pCxt, int32_t command, char *sntp_srvr_addr) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_CFG_SNTP_SRVR_ADDR sock_ip_sntp_srvr_addr; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + strcpy(sock_ip_sntp_srvr_addr.addr, sntp_srvr_addr); + sock_ip_sntp_srvr_addr.command = A_CPU2LE32(command); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SNTP_SRVR_ADDR, (void *)(&sock_ip_sntp_srvr_addr), + sizeof(SOCK_IP_CFG_SNTP_SRVR_ADDR)) != A_OK) + { + return A_ERROR; + } + return (A_OK); +} + +int32_t Api_ip_sntp_get_time(void *pCxt, tSntpTime *SntpTime) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + uint8_t free_buf = 1; + tSntpTime *result = NULL; + uint8_t buffer[sizeof(WMI_SOCKET_CMD) + 4]; + WMI_SOCKET_CMD *sock_cmd = (WMI_SOCKET_CMD *)&buffer[0]; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + free_buf = 0; + return A_ERROR; + } + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP_SNTP_GET_TIME); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SNTP_GET_TIME, (void *)&sock_cmd, (sizeof(WMI_SOCKET_CMD) + 4)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP_SNTP_GET_TIME); + free_buf = 0; + return A_ERROR; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], (DHCP_WAIT_TIME * 2), RX_DIRECTION) != A_OK) + { + return -1; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IP_SNTP_GET_TIME)); + + if (ath_sock_context[index]->result != -1) + { + result = (tSntpTime *)(ath_sock_context[index]->data); + A_MEMCPY(SntpTime, result, sizeof(tSntpTime)); + } + res = ath_sock_context[index]->result; + /*Free the netbuf*/ + if (free_buf) + { + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + return res; +} + +int32_t Api_ip_sntp_get_time_of_day(void *pCxt, tSntpTM *SntpTm) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + uint8_t free_buf = 1; + tSntpTM *result = NULL; + uint8_t buffer[sizeof(WMI_SOCKET_CMD) + 4]; + WMI_SOCKET_CMD *sock_cmd = (WMI_SOCKET_CMD *)&buffer[0]; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + free_buf = 0; + return A_ERROR; + } + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP_SNTP_GET_TIME_OF_DAY); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SNTP_GET_TIME_OF_DAY, (void *)&sock_cmd, (sizeof(WMI_SOCKET_CMD) + 4)) != + A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP_SNTP_GET_TIME_OF_DAY); + free_buf = 0; + return A_ERROR; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], (DHCP_WAIT_TIME * 2), RX_DIRECTION) != A_OK) + { + return -1; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IP_SNTP_GET_TIME_OF_DAY)); + + if (ath_sock_context[index]->result != -1) + { + result = (tSntpTM *)(ath_sock_context[index]->data); + A_MEMCPY(SntpTm, result, sizeof(tSntpTM)); + } + res = ath_sock_context[index]->result; + /*Free the netbuf*/ + if (free_buf) + { + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + return res; +} + +int32_t Api_ip_sntp_modify_zone_dse(void *pCxt, uint8_t hr, uint8_t mn, uint8_t zone_cal, uint8_t dse_en_dis) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + SOCK_SNTP_MODIFY_TIMEZONE sock_ip_sntp_time_zone; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + sock_ip_sntp_time_zone.hour = hr; + sock_ip_sntp_time_zone.min = mn; + sock_ip_sntp_time_zone.add_sub = zone_cal; + sock_ip_sntp_time_zone.dse = dse_en_dis; + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP_SNTP_CONFIG_TIMEZONE_DSE); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SNTP_CONFIG_TIMEZONE_DSE, (void *)(&sock_ip_sntp_time_zone), + sizeof(SOCK_SNTP_MODIFY_TIMEZONE)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP_SNTP_CONFIG_TIMEZONE_DSE); + return A_ERROR; + } + + return res; +} + +int32_t Api_ip_sntp_query_srvr_address(void *pCxt, tSntpDnsAddr SntpDnsAddr[MAX_SNTP_SERVERS]) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + uint8_t free_buf = 1; + tSntpDnsAddr *result = NULL; + SOCK_IP_QUERY_SNTP_CONFIG sock_ip_query_sntp_config; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + free_buf = 0; + return A_ERROR; + } + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP_SNTP_QUERY_SNTP_ADDRESS); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SNTP_QUERY_SNTP_ADDRESS, (void *)(&sock_ip_query_sntp_config), + sizeof(SOCK_IP_QUERY_SNTP_CONFIG)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP_SNTP_QUERY_SNTP_ADDRESS); + free_buf = 0; + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], (DHCP_WAIT_TIME * 2), RX_DIRECTION) != A_OK) + { + return -1; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IP_SNTP_QUERY_SNTP_ADDRESS)); + + if (ath_sock_context[index]->result != -1) + { + result = (tSntpDnsAddr *)(ath_sock_context[index]->data); + A_MEMCPY(SntpDnsAddr, result, (sizeof(tSntpDnsAddr) * MAX_SNTP_SERVERS)); + } + res = ath_sock_context[index]->result; + /*Free the netbuf*/ + if (free_buf) + { + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + return res; +} + +int32_t Api_ip_sntp_client(void *pCxt, int32_t command) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IP_SNTP_CLIENT_T sock_sntp_client; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + sock_sntp_client.command = A_CPU2LE32(command); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IP_SNTP_CLIENT_ENABLE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IP_SNTP_CLIENT_ENABLE, (void *)(&sock_sntp_client), + sizeof(SOCK_IP_SNTP_CLIENT_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IP_SNTP_CLIENT_ENABLE); + return A_ERROR; + } + + return (res); +} + +#endif /* ENABLE_SNTP_CLIENT */ + +#if ENABLE_ROUTING_CMDS +/*****************************************************************************/ +/* Api_ipv4_route - API to add, del and show IPv4 routes + * void *pCxt- driver context + * uint32_t* ipv4_addr + * uint32_t* subnetMask + * uint32_t* gateway + * uint32_t* ifIndex + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipv4_route(void *pCxt, + uint32_t command, + IP_ADDR_T *ipv4_addr, + IP_ADDR_T *subnetMask, + IP_ADDR_T *gateway, + uint32_t *ifIndex, + IPV4_ROUTE_LIST_T *routelist) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IPV4_ROUTE_T sock_ipv4_route; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + sock_ipv4_route.command = A_CPU2LE32(command); + sock_ipv4_route.address = A_CPU2LE32(ipv4_addr->s_addr); + sock_ipv4_route.mask = A_CPU2LE32(subnetMask->s_addr); + sock_ipv4_route.gateway = A_CPU2LE32(gateway->s_addr); + sock_ipv4_route.ifIndex = A_CPU2LE32(*ifIndex); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IPV4_ROUTE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IPV4_ROUTE, (void *)(&sock_ipv4_route), sizeof(SOCK_IPV4_ROUTE_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IPV4_ROUTE); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IPV4_ROUTE)); + + if (command == 2) + { + A_MEMCPY(routelist, ath_sock_context[index]->data, sizeof(IPV4_ROUTE_LIST_T)); + } + A_NETBUF_FREE(ath_sock_context[index]->pReq); + return (res); +} + +/*****************************************************************************/ +/* Api_ipv6_route - API to add, del and show IPv6 routes + * void *pCxt- driver context + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ipv6_route(void *pCxt, + uint32_t command, + IP6_ADDR_T *ip6addr, + uint32_t *prefixLen, + IP6_ADDR_T *gateway, + uint32_t *ifIndex, + IPV6_ROUTE_LIST_T *routelist) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_IPV6_ROUTE_T sock_ipv6_route; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + sock_ipv6_route.command = A_CPU2LE32(command); + A_MEMCPY(sock_ipv6_route.address, ip6addr->s6_addr, sizeof(sock_ipv6_route.address)); + sock_ipv6_route.prefixLen = A_CPU2LE32(*prefixLen); + A_MEMCPY(sock_ipv6_route.nexthop, gateway, sizeof(sock_ipv6_route.nexthop)); + sock_ipv6_route.ifIndex = A_CPU2LE32(*ifIndex); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_IPV6_ROUTE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_IPV6_ROUTE, (void *)(&sock_ipv6_route), sizeof(SOCK_IPV6_ROUTE_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_IPV6_ROUTE); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_IPV6_ROUTE)); + + if (command == 2) + { + A_MEMCPY(routelist, ath_sock_context[index]->data, sizeof(IPV6_ROUTE_LIST_T)); + } + A_NETBUF_FREE(ath_sock_context[index]->pReq); + return (res); +} +#endif /* ENABLE_ROUTING_CMDS */ + /*****************************************************************************/ + /* Api_tcp_connection_timeout - API to set TCp Connection Timeout + * void *pCxt- driver context + * Returns- 0 on Success , A_ERROR otherwise + *****************************************************************************/ +int32_t Api_tcp_connection_timeout(void *pCxt, uint32_t timeout_val) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_TCP_CONN_TIMEOUT_T sock_tcp_conn_timeout; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&sock_tcp_conn_timeout, sizeof(SOCK_TCP_CONN_TIMEOUT_T)); + sock_tcp_conn_timeout.timeout_val = timeout_val; + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_TCP_CONN_TIMEOUT); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_TCP_CONN_TIMEOUT, (void *)(&sock_tcp_conn_timeout), + sizeof(SOCK_TCP_CONN_TIMEOUT_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_TCP_CONN_TIMEOUT); + return A_ERROR; + } + return A_OK; +} +/*****************************************************************************/ +/* Api_ota_upgrade - API to intialize OTA upgrade + * void *pCxt- driver context + * Returns- 0 in case of successful OTA, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_upgrade(void *pCxt, + uint32_t addr, + char *filename, + uint8_t mode, + uint8_t preserve_last, + uint8_t protocol, + uint32_t *resp_code, + uint32_t *length) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_OTA_UPGRADE_T sock_ota_upgrade; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&sock_ota_upgrade, sizeof(SOCK_OTA_UPGRADE_T)); + sock_ota_upgrade.ipaddress = addr; + A_MEMCPY(sock_ota_upgrade.filename, filename, strlen(filename)); + sock_ota_upgrade.mode = mode; + sock_ota_upgrade.preserve_last = preserve_last; + sock_ota_upgrade.protocol = protocol; + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_UPGRADE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_UPGRADE, (void *)(&sock_ota_upgrade), sizeof(SOCK_OTA_UPGRADE_T)) != + A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_UPGRADE); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_UPGRADE)); + + *resp_code = ((tOtaUpgradeResp *)(ath_sock_context[index]->data))->resp_code; + *length = ((tOtaUpgradeResp *)(ath_sock_context[index]->data))->size; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return A_OK; +} +/*****************************************************************************/ +/* Api_ota_read - API to read OTA upgrade area + * void *pCxt- driver context + * Returns- 0 in case of successful OTA READ, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_read_area(void *pCxt, uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *ret_len) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_OTA_READ_OTA_AREA_T sock_ota_read; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&sock_ota_read, sizeof(SOCK_OTA_READ_OTA_AREA_T)); + sock_ota_read.offset = offset; + sock_ota_read.size = size; + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_READ); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_READ, (void *)(&sock_ota_read), sizeof(SOCK_OTA_READ_OTA_AREA_T)) != + A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_READ); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_READ)); + + // resp->resp_code=((tOtaReadResp*)(ath_sock_context[index]->data))->resp_code; + *ret_len = ((tOtaReadResp *)(ath_sock_context[index]->data))->size; + + A_MEMCPY(buffer, (void*)&((tOtaReadResp *)(ath_sock_context[index]->data))->data, *ret_len); + + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return A_OK; +} +/*****************************************************************************/ +/* Api_ota_done - API to send OTA Complete event to target + * void *pCxt- driver context + * Returns- 0 in case of successful OTA , A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_done(void *pCxt, boolean good_image) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_OTA_DONE_T sock_ota_done; + int index = GLOBAL_SOCK_INDEX; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&sock_ota_done, sizeof(SOCK_OTA_DONE_T)); + sock_ota_done.data = good_image; + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_DONE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_DONE, (void *)(&sock_ota_done), sizeof(SOCK_OTA_DONE_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_DONE); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_DONE)); + + // A_MEMCPY(resp, ath_sock_context[index]->data, sizeof(tOtaDoneResp)); + + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return A_OK; +} + +/*****************************************************************************/ +/* Api_ota_session_start - API to send OTA Session Start command to target + * A_VOID *pCxt- driver context + * Returns- 0 in case of successful OTA , A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_session_start(void *pCxt, uint32_t flags, uint32_t partition_index) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_OTA_SESSION_START_T ota_cmd; + int index = GLOBAL_SOCK_INDEX; + int32_t res = A_OK; + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&ota_cmd, sizeof(ota_cmd)); + ota_cmd.flags = flags; + ota_cmd.partition_index = partition_index; + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_SESSION_START); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_SESSION_START, (void *)(&ota_cmd), sizeof(ota_cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_SESSION_START); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_SESSION_START)); + res = ((tOtaResp *)(ath_sock_context[index]->data))->resp_code; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return res; +} + +/*****************************************************************************/ +/* Api_ota_partition_get_size - API to send OTA Partition Get Size command to target + * A_VOID *pCxt- driver context + * Returns- partition size in case of successful OTA , 0 otherwise + *****************************************************************************/ +uint32_t Api_ota_partition_get_size(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + struct sock_ota_cmd_s + { + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t data[1]; + } POSTPACK ota_cmd; + int index = GLOBAL_SOCK_INDEX; + int32_t res; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return 0; + } + A_MEMZERO(&ota_cmd, sizeof(ota_cmd)); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_PARTITION_GET_SIZE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_PARTITION_GET_SIZE, (void *)(&ota_cmd), sizeof(ota_cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_PARTITION_GET_SIZE); + return 0; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return 0; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_PARTITION_GET_SIZE)); + + res = ((tOtaPartitionGetSizeResp *)(ath_sock_context[index]->data))->size; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return res; +} + +/*****************************************************************************/ +/* Api_ota_partition_erase - API to send OTA Partition Erase command to target + * A_VOID *pCxt- driver context + * Returns- 0 in case of successful OTA , A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_partition_erase(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + struct sock_ota_cmd_s + { + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t data[1]; + } POSTPACK ota_cmd; + int index = GLOBAL_SOCK_INDEX; + int32_t res; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&ota_cmd, sizeof(ota_cmd)); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_PARTITION_ERASE); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_PARTITION_ERASE, (void *)(&ota_cmd), sizeof(ota_cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_PARTITION_ERASE); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_PARTITION_ERASE)); + + res = ((tOtaResp *)(ath_sock_context[index]->data))->resp_code; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return res; +} + +/*****************************************************************************/ +/* Api_ota_partition_verify_checksum - API to send OTA Partition Verify Checksum command to target + * A_VOID *pCxt- driver context + * Returns- 0 in case of successful OTA , A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_partition_verify_checksum(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + struct sock_ota_cmd_s + { + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t data[1]; + } POSTPACK ota_cmd; + int index = GLOBAL_SOCK_INDEX; + int32_t res; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&ota_cmd, sizeof(ota_cmd)); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_PARTITION_VERIFY_CHECKSUM); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_PARTITION_VERIFY_CHECKSUM, (void *)(&ota_cmd), sizeof(ota_cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_PARTITION_VERIFY_CHECKSUM); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_PARTITION_VERIFY_CHECKSUM)); + + res = ((tOtaResp *)(ath_sock_context[index]->data))->resp_code; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + + return res; +} + +/*****************************************************************************/ +/* Api_ota_parse_image_hdr - API to send OTA Parse Image Header command to target + * A_VOID *pCxt- driver context + * Returns- 0 in case of successful OTA , A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_parse_image_hdr(void *pCxt, uint8_t *header, uint32_t *offset) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_OTA_PARSE_IMAGE_HDR_T ota_cmd; + int index = GLOBAL_SOCK_INDEX; + int32_t res; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + A_MEMZERO(&ota_cmd, sizeof(ota_cmd)); + A_MEMCPY(ota_cmd.header, header, 24); // copy ota image header + + if (GET_DRIVER_CXT(pCxt)->otaCB != NULL) // non blocking */ + { + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_PARSE_IMAGE_HDR, (void *)(&ota_cmd), sizeof(ota_cmd)) != A_OK) + { + return A_ERROR; + } + else + { + return A_PENDING; + } + } + else + { + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_PARSE_IMAGE_HDR); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_PARSE_IMAGE_HDR, (void *)(&ota_cmd), sizeof(ota_cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_PARSE_IMAGE_HDR); + return A_ERROR; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + return A_ERROR; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_PARSE_IMAGE_HDR)); + + *offset = ((tOtaParseImageHdrResp *)(ath_sock_context[index]->data))->offset; + res = ((tOtaParseImageHdrResp *)(ath_sock_context[index]->data))->resp_code; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } + return res; +} + +/*****************************************************************************/ +/* Api_ota_partition_write_data - API to send OTA Partition Write Data command to target + * A_VOID *pCxt- driver context + * Returns- 0 in case of successful OTA , A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ota_partition_write_data(void *pCxt, uint32_t offset, uint8_t *buf, uint32_t buf_size, uint32_t *ret_size) +{ + A_DRIVER_CONTEXT *pDCxt = NULL; + SOCK_OTA_PARTITON_WRITE_DATA_T *ota_cmd = NULL; + int index = GLOBAL_SOCK_INDEX; + int32_t res = QCOM_OTA_ERR_WRITE_DATA_ERROR; + uint32_t cmd_len; + + pDCxt = GET_DRIVER_COMMON(pCxt); + // Check if socket is blocked for a previous command + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + goto ota_error; + } + + *ret_size = 0; + if (buf_size == 0) + return QCOM_OTA_OK; + if ((buf == NULL) || (buf_size > MAX_OTA_AREA_READ_SIZE)) + return QCOM_OTA_ERR_WRITE_DATA_ERROR; + + cmd_len = sizeof(SOCK_OTA_PARTITON_WRITE_DATA_T) + buf_size - 1; + + ota_cmd = A_MALLOC(cmd_len, MALLOC_ID_CONTEXT); + if (ota_cmd == NULL) + { + return A_NO_MEMORY; + } + + A_MEMZERO(ota_cmd, cmd_len); + A_MEMCPY(ota_cmd->data, buf, buf_size); + ota_cmd->offset = offset; + ota_cmd->size = buf_size; + + if (GET_DRIVER_CXT(pCxt)->otaCB != NULL) // non blocking */ + { + if ((res = wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_PARTITION_WRITE_DATA, (void *)(ota_cmd), cmd_len)) != A_OK) + { + goto ota_error; + } + else + { + res = A_PENDING; + } + } + else + { + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_OTA_PARTITION_WRITE_DATA); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_OTA_PARTITION_WRITE_DATA, (void *)(ota_cmd), cmd_len) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_OTA_PARTITION_WRITE_DATA); + goto ota_error; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + goto ota_error; + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_OTA_PARTITION_WRITE_DATA)); + + *ret_size = ((tOtaPartitionWriteDataResp *)(ath_sock_context[index]->data))->size; + res = ((tOtaPartitionWriteDataResp *)(ath_sock_context[index]->data))->resp_code; + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } +ota_error: + if (ota_cmd != NULL) + A_FREE(ota_cmd, MALLOC_ID_CONTEXT); + return res; +} + +/*****************************************************************************/ +/* Api_ping - API to obtain IP address information from target + * void *pCxt- driver context + * uint32_t* ipv4_addr + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ping(void *pCxt, uint32_t ipv4_addr, uint32_t size, uint32_t ms_interval) +{ + A_DRIVER_CONTEXT *pDCxt; + PING_T ping; + uint32_t index = GLOBAL_SOCK_INDEX; // reserved for global commands ToDo- cleanup later + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + ping.ip_addr = A_CPU2LE32(ipv4_addr); + ping.size = A_CPU2LE32(size); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_PING); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_PING, (void *)(&ping), sizeof(PING_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_PING); + result = A_ERROR; + break; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], ms_interval, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_PING)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* Api_ping6 - API to obtain IP address information from target + * void *pCxt- driver context + * uint32_t* ipv4_addr + * Returns- 0 in case of successful connect, A_ERROR otherwise + *****************************************************************************/ +int32_t Api_ping6(void *pCxt, uint8_t *ip6addr, uint32_t size, uint32_t ms_interval) +{ + A_DRIVER_CONTEXT *pDCxt; + PING_6_T ping6; + uint32_t index = GLOBAL_SOCK_INDEX; // reserved for global commands ToDo- cleanup later + int32_t result = A_OK; + + pDCxt = GET_DRIVER_COMMON(pCxt); + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + A_MEMCPY(ping6.ip6addr, ip6addr, sizeof(ping6.ip6addr)); + ping6.size = A_CPU2LE32(size); + + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_PING6); + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_PING6, (void *)(&ping6), sizeof(PING_6_T)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_PING6); + result = A_ERROR; + break; + } + + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_PING6)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* clear_socket_context - clears all elements of socket context + * int32_t - index to socket context + * Returns- None + *****************************************************************************/ +void clear_socket_context(int32_t index) +{ + ath_sock_context[index]->handle = 0; + ath_sock_context[index]->domain = 0; + ath_sock_context[index]->type = 0; + ath_sock_context[index]->TCPCtrFlag = 0; + A_MEMZERO(&ath_sock_context[index]->sock_st_mask[0], sizeof(ath_sock_context[index]->sock_st_mask)); + + /* Free remaining data when socket is closed */ + if (ath_sock_context[index]->old_netbuf != NULL) + { + A_NETBUF_FREE(ath_sock_context[index]->old_netbuf); + ath_sock_context[index]->old_netbuf = NULL; + } + ath_sock_context[index]->remaining_bytes = 0; + + /*If for some reason, data field is not freed, free it here + This may happen when a command response comes later than Timeout period*/ + if (ath_sock_context[index]->data) + { + QCADRV_PRINTF("%s index:%d data:%p\n", __func__, index, ath_sock_context[index]->data); + A_FREE(ath_sock_context[index]->data, MALLOC_ID_CONTEXT); + ath_sock_context[index]->data = NULL; + } +} + +/*****************************************************************************/ +/* send_stack_init - Sends Stack initialization information. + * RETURNS: A_OK on success A_ERROR otherwise + *****************************************************************************/ +A_STATUS send_stack_init(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt; + uint8_t buffer[sizeof(WMI_SOCKET_CMD) + 4]; + WMI_SOCKET_CMD *sock_cmd = (WMI_SOCKET_CMD *)&buffer[0]; + pDCxt = GET_DRIVER_COMMON(pCxt); + + buffer[8] = 1; + buffer[9] = 2; + buffer[10] = MAX_SOCKETS_SUPPORTED; + + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_STACK_INIT, (void *)(sock_cmd), sizeof(WMI_SOCKET_CMD) + 4) != A_OK) + { + return A_ERROR; + } + +#if ENABLE_SSL + sslhandle = (GET_DRIVER_CXT(pCxt)->pUpperCxt[0]); +#endif + + return A_OK; +} + +enum +{ + /* Least priority since we dont allow any operation during store-recall */ + POWER_STATE_MOVED_FOR_STRRCL = 1, + /* IPDHCP will happen only after the network connection usually */ + POWER_STATE_MOVED_FOR_IPDHCP, + POWER_STATE_MOVED_FOR_TCPRX +}; + +int32_t power_state_for_module = 0; +/*****************************************************************************/ +/* move_to_maxperf - Changes the power mode to max perf in firmware. There are + * some commands which need to run in MAX_PERF mode like store_recall etc + * This function changes the power modeto MAX_PERF and will not + * intimate the application. Later after the command succeeds, + * use restore_power_state to change to original power state + * Note: Application should not directly use this function + * int32_t - module which request the change + * Returns- A_OK on success, A_ERROR otherwise + *****************************************************************************/ +A_STATUS move_power_state_to_maxperf(void *pCxt, int32_t module) +{ + A_DRIVER_CONTEXT *pDCxt = (A_DRIVER_CONTEXT *)pCxt; + + /* Already some HIGH module changes state */ + if (power_state_for_module >= module) + { + return A_OK; + } + + /* Change the power mode only when the current power mode is REC_POWER */ + if (pDCxt->userPwrMode == REC_POWER) + { + if (A_OK != wmi_cmd_start(pDCxt->pWmiCxt, &max_performance_power_param, WMI_SET_POWER_MODE_CMDID, + sizeof(WMI_POWER_MODE_CMD))) + { + return A_ERROR; + } + } + power_state_for_module = module; + return A_OK; +} +/*****************************************************************************/ +/* restore_power_state - Restores the original power state, which is changed by + * "move_power_state_to_maxperf" + * int32_t - module which request the change + * RETURNS: A_OK on success A_ERROR otherwise + *****************************************************************************/ +A_STATUS restore_power_state(void *pCxt, int32_t module) +{ + A_DRIVER_CONTEXT *pDCxt = (A_DRIVER_CONTEXT *)pCxt; + + /* Already some HIGH priority module changes state, + * so don't change the state now */ + if (!power_state_for_module || (power_state_for_module > module)) + { + return A_OK; + } + if (pDCxt->userPwrMode != max_performance_power_param) + { + if (A_OK != + wmi_cmd_start(pDCxt->pWmiCxt, &pDCxt->userPwrMode, WMI_SET_POWER_MODE_CMDID, sizeof(WMI_POWER_MODE_CMD))) + { + return A_ERROR; + } + } + + power_state_for_module = 0; + return A_OK; +} +#if ENABLE_SSL +/*****************************************************************************/ +/* SSL_ctx_new - Create new SSL context. This function must be called before + * using any other SSL functions. It needs to be called as either + * server or client + * Sslrole role - 1 = server, 2 = client + * int32_t inbufSize - initial inBuf size: Can grow + * int32_t outbufSize - outBuf size: Fixed + * int32_t reserved - currently not used (must be zero) + * Returns - SSL context handle on success or NULL on error (out of memory) + *****************************************************************************/ +SSL_CTX *Api_SSL_ctx_new(void *pCxt, SSL_ROLE_T role, int32_t inbufSize, int32_t outbufSize, int32_t reserved) +{ + SOCK_SSL_CTX_NEW_T cmd; + SSL_CTX *result = NULL; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + int32_t index = GLOBAL_SOCK_INDEX; + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + break; + } + + /* Send command and wait for response */ + cmd.role = role; + cmd.inbufSize = inbufSize; + cmd.outbufSize = outbufSize; + cmd.reserved = reserved; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_CTX_NEW); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_CTX_NEW, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_CTX_NEW); + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_CTX_NEW)); + result = (SSL_CTX *)ath_sock_context[GLOBAL_SOCK_INDEX]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* SSL_ctx_free - Free the SSL context + * SSL_CTX *ctx - sslContext + *****************************************************************************/ +int32_t Api_SSL_ctx_free(void *pCxt, SSL_CTX *ctx) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + SOCK_SSL_CTX_FREE_T cmd; + int32_t result = A_OK; + int32_t index = GLOBAL_SOCK_INDEX; + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + /* Send command and wait for response */ + cmd.ctx = (uint32_t)ctx; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_CTX_FREE); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_CTX_FREE, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_CTX_FREE); + result = A_ERROR; + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_CTX_FREE)); + result = ath_sock_context[GLOBAL_SOCK_INDEX]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* SSL_new - Create SSL connection object. When SSL transaction is done, close + * it with ssl_shutdown(). + * Note that the socket should subsequently also be closed. + * SSL_CTX *ctx - sslContext + * Return - SSL object handle on success or NULL on error (out of memory) + *****************************************************************************/ +SSL *Api_SSL_new(void *pCxt, SSL_CTX *ctx) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + SOCK_SSL_NEW_T cmd; + SSL *result = NULL; + int32_t index = GLOBAL_SOCK_INDEX; + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + break; + } + + /* Send command and wait for response */ + cmd.ctx = (uint32_t)ctx; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_NEW); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_NEW, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_NEW); + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_NEW)); + result = (SSL *)ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* SSL_set_fd - Attach given socket descriptor to the SSL connection + * SSL *ssl - SSL connection + * uint32_t fd - Socket descriptor + * Return - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t Api_SSL_set_fd(void *pCxt, SSL *ssl, uint32_t fd) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + SOCK_SSL_SET_FD_T cmd; + int32_t result = A_OK; + int32_t index; + + do + { + /* Find the socket */ + index = find_socket_context(fd, true); + if (index == SOCKET_NOT_FOUND) + { + return A_ERROR; + } + + /* Check if socket is blocked for a previous command */ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + return A_ERROR; + } + + /* Store the ssl object pointer in the socket struct */ + ath_sock_context[index]->ssl = ssl; + + /* Send command and wait for response */ + cmd.ssl = (uint32_t)ssl; + cmd.fd = fd; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_SET_FD); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_SET_FD, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_SET_FD); + result = A_ERROR; + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_SET_FD)); + result = ath_sock_context[index]->result; + } while (0); + + if (result < 0) + { + /* remove the ssl pointer again if the cmd failed */ + ath_sock_context[index]->ssl = NULL; + } + + return result; +} + +/*****************************************************************************/ +/* SSL_accept - Initiate SSL handshake. + * SSL *ssl - SSL connection + * Returns - 1 on success, ESSL_HSDONE if handshake has already been performed. + * Negative error code otherwise. + *****************************************************************************/ +int32_t Api_SSL_accept(void *pCxt, SSL *ssl) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + SOCK_SSL_ACCEPT_T cmd; + int32_t result = A_OK; + int32_t index; + + do + { + /* Find the socket used with this SSL connection */ + index = find_socket_context_from_ssl(ssl); + if (index == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + + /* Check if socket is blocked for a previous command */ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + /* Send command and wait for response */ + cmd.ssl = (uint32_t)ssl; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_ACCEPT); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_ACCEPT, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_ACCEPT); + result = A_ERROR; + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_ACCEPT)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* SSL_connect - Initiate SSL handshake. + * SSL *ssl - SSL connection + * Returns - 1 on success, ESSL_HSDONE if handshake has already been performed. + * Negative error code otherwise. + *****************************************************************************/ +int32_t Api_SSL_connect(void *pCxt, SSL *ssl) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_SSL_ACCEPT_T cmd; + int32_t result = A_OK; + int32_t index; + + pDCxt = GET_DRIVER_COMMON(pCxt); + do + { + index = find_socket_context_from_ssl(ssl); + if (index == SOCKET_NOT_FOUND) + { + result = A_ERROR; + break; + } + + /* Check if socket is blocked for a previous command */ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + /* Send command and wait for response */ + cmd.ssl = (uint32_t)ssl; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_CONNECT); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_CONNECT, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_CONNECT); + result = A_ERROR; + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_CONNECT)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* SSL_shutdown - Close SSL connection. + * The socket must be closed by other means. + * SSL *ssl - SSL connection + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t Api_SSL_shutdown(void *pCxt, SSL *ssl) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + ; + SOCK_SSL_SHUTDOWN_T cmd; + int32_t result = A_OK; + int32_t index = find_socket_context_from_ssl(ssl); + + if (index == SOCKET_NOT_FOUND) + { + /* We send the shutdown command on the "global socket" if the socket used for + the SSL is disconnected/closed before the SSL connection is shutdown. */ + index = GLOBAL_SOCK_INDEX; + } + do + { + /* Check if socket is blocked for a previous command */ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + /* Send command and wait for response */ + cmd.ssl = (uint32_t)ssl; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_SHUTDOWN); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_SHUTDOWN, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_SHUTDOWN); + result = A_ERROR; + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_SHUTDOWN)); + result = ath_sock_context[index]->result; + + /* clear the SSL object ptr in the socket struct */ + ath_sock_context[index]->ssl = NULL; + } while (0); + + return result; +} + +int32_t Api_SSL_configure(void *pCxt, SSL *ssl, SSL_CONFIG *cfg) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + ; + SOCK_SSL_CONFIGURE_T cmd; + int32_t result = A_OK; + int32_t index = find_socket_context_from_ssl(ssl); + + if (index == SOCKET_NOT_FOUND) + { + /* We send the configure command on the "global socket" if the configure is + * done before the socket is created */ + index = GLOBAL_SOCK_INDEX; + } + do + { + /* Check if socket is blocked for a previous command */ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + /* Send command and wait for response */ + cmd.ssl = (uint32_t)ssl; + cmd.size = sizeof(SSL_CONFIG); + memcpy(cmd.data, cfg, sizeof(SSL_CONFIG)); + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_CONFIGURE); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_CONFIGURE, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_CONFIGURE); + result = A_ERROR; + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_CONFIGURE)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +/*****************************************************************************/ +/* SSL_addCert - Add a certificate or Certificate Authority (CA) list to the + * SharkSsl object. + * A SharkSsl object in server mode is required to have at least + * one certificate. + * You can only set one CA list, thus the CA list must include + * all root certificates required for the session. + * SSL *ssl - SSL connection + * SslCert cert -address of array of binary data + * uint32_t size - size of array + * SSL_CERT_TYPE_T type - certificate or CA list + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t Api_SSL_addCert(void *pCxt, SSL_CTX *ctx, SSL_CERT_TYPE_T type, uint8_t *cert, uint32_t size) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_SSL_ADD_CERT_T *pCmd; + int32_t result = A_OK; + uint32_t n, buffSize, offset = 0; + void *pBuff; + int index = GLOBAL_SOCK_INDEX; + uint8_t *data = (uint8_t *)cert; + + pDCxt = GET_DRIVER_COMMON(pCxt); + do + { + /* Check if socket is blocked for a previous command */ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + do + { + n = size - offset; + if (n > MAX_CERT_DATA_LENGTH) + { + n = MAX_CERT_DATA_LENGTH; + } + buffSize = sizeof(SOCK_SSL_ADD_CERT_T) + n - 1; + pBuff = A_NETBUF_ALLOC(buffSize); + if (pBuff) + { + /* reserve the necessary space in the buffer */ + A_NETBUF_PUT(pBuff, buffSize); + + pCmd = A_NETBUF_DATA(pBuff); + pCmd->wmi_cmd.cmd_type = SOCK_SSL_ADD_CERT; + pCmd->wmi_cmd.length = buffSize - sizeof(WMI_SOCKET_CMD); + pCmd->ctx = (uint32_t)ctx; + pCmd->type = type; + pCmd->total = size; + pCmd->offset = offset; + pCmd->size = n; + A_MEMCPY(pCmd->data, &data[offset], n); + offset += n; + + /* send the buffer to the wifi device */ + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_ADD_CERT); + result = wmi_cmd_send(pDCxt->pWmiCxt, pBuff, WMI_SOCKET_CMDID, NO_SYNC_WMIFLAG); + if (result != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_ADD_CERT); + return A_ERROR; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_ADD_CERT)); + result = ath_sock_context[index]->result; + } + } while (offset < size && result >= A_OK); + if (offset != size) + { + result = A_ERROR; + } + } while (0); + + return result; +} + +int32_t Api_SSL_storeCert(void *pCxt, char *name, uint8_t *cert, uint32_t size) +{ + A_DRIVER_CONTEXT *pDCxt; + SOCK_SSL_STORE_CERT_T *pCmd; + int32_t result = A_OK; + uint32_t n, buffSize, offset = 0; + void *pBuff; + int index = GLOBAL_SOCK_INDEX; + uint8_t *data = (uint8_t *)cert; + + pDCxt = GET_DRIVER_COMMON(pCxt); + do + { + /* Check if socket is blocked for a previous command */ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + result = A_ERROR; + break; + } + + do + { + n = size - offset; + if (n > MAX_CERT_DATA_LENGTH) + { + n = MAX_CERT_DATA_LENGTH; + } + buffSize = sizeof(SOCK_SSL_STORE_CERT_T) + n - 1; + pBuff = A_NETBUF_ALLOC(buffSize); + if (pBuff) + { + /* reserve the necessary space in the buffer */ + A_NETBUF_PUT(pBuff, buffSize); + + pCmd = A_NETBUF_DATA(pBuff); + pCmd->wmi_cmd.cmd_type = SOCK_SSL_STORE_CERT; + pCmd->wmi_cmd.length = buffSize - sizeof(WMI_SOCKET_CMD); + strncpy((char *)pCmd->name, name, SSL_MAX_CERT_NAME_LEN); + pCmd->name[SSL_MAX_CERT_NAME_LEN] = '\0'; + pCmd->total = size; + pCmd->offset = offset; + pCmd->size = n; + A_MEMCPY(pCmd->data, &data[offset], n); + offset += n; + + /* send the buffer to the wifi device */ + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_STORE_CERT); + result = wmi_cmd_send(pDCxt->pWmiCxt, pBuff, WMI_SOCKET_CMDID, NO_SYNC_WMIFLAG); + if (result != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_STORE_CERT); + return A_ERROR; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_STORE_CERT)); + result = ath_sock_context[index]->result; + } + } while (offset < size && result >= A_OK); + if (offset != size) + { + result = A_ERROR; + } + } while (0); + + return result; +} + +int32_t Api_SSL_loadCert(void *pCxt, SSL_CTX *ctx, SSL_CERT_TYPE_T type, char *name) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + SOCK_SSL_LOAD_CERT_T cmd; + int32_t result = A_ERROR; + int32_t index = GLOBAL_SOCK_INDEX; + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + break; + } + + /* Send command and wait for response */ + cmd.ctx = (uint32_t)ctx; + cmd.type = type; + strncpy((char *)cmd.name, name, SSL_MAX_CERT_NAME_LEN); + cmd.name[SSL_MAX_CERT_NAME_LEN] = '\0'; + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_LOAD_CERT); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_LOAD_CERT, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_LOAD_CERT); + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_LOAD_CERT)); + result = ath_sock_context[index]->result; + } while (0); + + return result; +} + +int32_t Api_SSL_listCert(void *pCxt, SSL_FILE_NAME_LIST *fileNames) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + SOCK_SSL_LIST_CERT_T cmd; + int32_t result = A_ERROR; + int32_t index = GLOBAL_SOCK_INDEX; + + do + { + /*Check if socket is blocked for a previous command*/ + if (IS_SOCKET_BLOCKED(ath_sock_context[index])) + { + break; + } + + /* Send command and wait for response */ + SOCK_EV_MASK_SET(ath_sock_context[index], SOCK_SSL_LIST_CERT); + if (wmi_socket_cmd(pDCxt->pWmiCxt, SOCK_SSL_LIST_CERT, (void *)(&cmd), sizeof(cmd)) != A_OK) + { + SOCK_EV_MASK_CLEAR(ath_sock_context[index], SOCK_SSL_LIST_CERT); + break; + } + do + { + if (BLOCK(pCxt, ath_sock_context[index], COMMAND_BLOCK_TIMEOUT, RX_DIRECTION) != A_OK) + { + A_ASSERT(0); + } + } while (SOCK_EV_MASK_TEST(ath_sock_context[index], SOCK_SSL_LIST_CERT)); + result = ath_sock_context[index]->result; + memcpy(fileNames, ath_sock_context[index]->data, sizeof(SSL_FILE_NAME_LIST)); + A_NETBUF_FREE(ath_sock_context[index]->pReq); + } while (0); + + return result; +} + +#endif // ENABLE_SSL + +A_STATUS blockForDataRx(void *pCxt, void *ctxt, uint32_t msec, uint8_t direction) +{ + SOCKET_CONTEXT_PTR pcustctxt = GET_SOCKET_CONTEXT(ctxt); + pcustctxt->respAvailable = false; + return (blockForResponse(pCxt, ctxt, msec, direction)); +} +/*****************************************************************************/ +/* blockForResponse - blocks a thread, either indefinitely or for a specified + * time period in milliseconds + * RETURNS: A_OK on success or error if timeout occurs. + *****************************************************************************/ +A_STATUS blockForResponse(void *pCxt, void *ctxt, uint32_t msec, uint8_t direction) +{ + A_STATUS result = A_OK; + SOCKET_CONTEXT_PTR pcustctxt = GET_SOCKET_CONTEXT(ctxt); + uint32_t setFlags; + + pcustctxt->blockFlag = 1; + if (msec == 0) + { + msec = 1; + } + + if (direction == RX_DIRECTION) + { + if (pcustctxt->respAvailable == false) + { + pcustctxt->rxBlock = true; + event_t *pEvent = &pcustctxt->sockRxWakeEvent; + A_STATUS res = A_EVENT_WAIT(pEvent, 0x01, false, msec, &setFlags); + if (A_OK != res) + { + result = A_ERROR; + } + else + { + A_EVENT_CLEAR(pEvent, 0x01); + } + pcustctxt->rxBlock = false; + pcustctxt->respAvailable = false; + } + else if (pcustctxt->respAvailable == true) + { + /*Response is available, reset the flag for future use*/ + result = A_OK; + pcustctxt->respAvailable = false; + } + else + { + // undefined state + assert(0); + } + } + else if (direction == TX_DIRECTION) + { + if (pcustctxt->txUnblocked == false) + { + pcustctxt->txBlock = true; + event_t *pEvent = &pcustctxt->sockTxWakeEvent; + if (A_OK != A_EVENT_WAIT(pEvent, 0x01, false, msec, &setFlags)) + { + result = A_ERROR; + } + else + { + A_EVENT_CLEAR(pEvent, 0x01); + } + pcustctxt->txBlock = false; + pcustctxt->txUnblocked = false; + } + + if (pcustctxt->txUnblocked == true) + { + /*Response is available, reset the flag for future use*/ + result = A_OK; + pcustctxt->txUnblocked = false; + } + /* Propagate error, thread unsafe */ + result = (A_STATUS)socket_get_driver_error(ctxt); + /* Clear error, thread unsafe*/ + socket_set_driver_error(ctxt, A_OK); + } + else + { + last_driver_error = A_EINVAL; + } + + pcustctxt->blockFlag = 0; + return result; +} + +#if T_SELECT_VER1 +A_STATUS blockSelect(void *pCxt, uint32_t msec) +{ + A_STATUS result = A_OK; + if (msec == 0) + { + msec = 1; + } + + event_t *pEvent = &GET_DRIVER_CXT(pCxt)->sockSelectWakeEvent; + uint32_t setFlags; + if (A_OK != A_EVENT_WAIT(pEvent, 0x01, true, msec, &setFlags)) + { + result = A_ERROR; + } + else + { + A_EVENT_CLEAR(pEvent, 0x01); + } + return result; +} +#endif // T_SELECT_VER1 + +/*****************************************************************************/ +/* isSocketBlocked - Checks if a thread is blocked on a given socket + * RETURNS: value of block flag + *****************************************************************************/ +uint32_t isSocketBlocked(void *ctxt) +{ + SOCKET_CONTEXT_PTR pcustctxt = GET_SOCKET_CONTEXT(ctxt); + return pcustctxt->blockFlag; +} + +/*****************************************************************************/ +/* unblock - Unblocks a thread if it is blocked. + * RETURNS: A_OK if unblock was successful, A_ERROR if thread was not blocked + *****************************************************************************/ +A_STATUS unblock(void *ctxt, uint8_t direction) +{ + A_STATUS result = A_OK; + SOCKET_CONTEXT_PTR pcustctxt = GET_SOCKET_CONTEXT(ctxt); + + /*Unblock task if it is blocked*/ + if (direction == RX_DIRECTION) + { + pcustctxt->respAvailable = true; + /*Unblock task if it is blocked*/ + if (pcustctxt->rxBlock == true) + { + A_EVENT_SET(&pcustctxt->sockRxWakeEvent, 0x01); + } + } + else if (direction == TX_DIRECTION) + { + pcustctxt->txUnblocked = true; + if (pcustctxt->txBlock == true) + { + A_EVENT_SET(&pcustctxt->sockTxWakeEvent, 0x01); + } + } + return result; +} + +/*****************************************************************************/ +/* Set socket 'driver_error' field + *****************************************************************************/ +void socket_set_driver_error(void *ctxt, int32_t error) +{ + assert(NULL != ctxt); + SOCKET_CONTEXT_PTR socket = GET_SOCKET_CONTEXT(ctxt); + assert(NULL != socket); + socket->driver_error = error; +} + +/*****************************************************************************/ +/* Get socket 'driver_error' field + *****************************************************************************/ +int32_t socket_get_driver_error(void *ctxt) +{ + assert(NULL != ctxt); + SOCKET_CONTEXT_PTR socket = GET_SOCKET_CONTEXT(ctxt); + assert(NULL != socket); + return socket->driver_error; +} + +#if T_SELECT_VER1 +A_STATUS unblockSelect(void *pCxt) +{ + A_STATUS result = A_OK; + A_EVENT_SET(&((GET_DRIVER_CXT(pCxt))->sockSelectWakeEvent), 0x01); + return result; +} +#endif + +#if T_SELECT_VER1 + +#define __FDMASK(d) (((uint32_t)1) << (d)) +#define __FD_SET(d, set) ((*set) |= __FDMASK(d)) +#define __FD_CLR(d, set) ((*set) &= ~__FDMASK(d)) +#define __FD_ISSET(d, set) (((set)&__FDMASK(d)) != 0) +#define __FD_ZERO(set) ((*set) = 0) + +int32_t FD_IsSet(uint32_t handle, uint32_t mask) +{ + int32_t index = 0; + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + return 1; + } + return (__FD_ISSET(index, mask)); +} + +int32_t FD_Set(uint32_t handle, uint32_t *mask) +{ + int32_t index = 0; + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + return 0; + } + __FD_SET(index, (mask)); + return (A_OK); +} + +int32_t FD_Clr(uint32_t handle, uint32_t *mask) +{ + int32_t index = 0; + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + // special case, we are trying to clear the mask for a non-existent socket. + // This is a workaround now. Need to come up with an elegant solution. + // Go through the all the existing sockets and remove the mask elements for which no valid sockets exists. + + *mask &= ((1 << (MAX_SOCKETS_SUPPORTED + 1)) - 1); + for (index = 0; index < MAX_SOCKETS_SUPPORTED; index++) + { + if ((*mask & (1 << index)) && (ath_sock_context[index]->handle == 0)) + { + __FD_CLR(index, (mask)); + } + } + return A_OK; + } + __FD_CLR(index, (mask)); + return (A_OK); +} + +int32_t FD_Zero(uint32_t *mask) +{ + *mask = 0; + return (A_OK); +} + +#endif // T_SELECT_VER1 + +#endif // ENABLE_STACK_OFFLOAD diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/stack_common/common_stack_offload.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/stack_common/common_stack_offload.h new file mode 100644 index 00000000000..5f361239445 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/stack_common/common_stack_offload.h @@ -0,0 +1,888 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __COMMON_STACK_OFFLOAD_H__ +#define __COMMON_STACK_OFFLOAD_H__ + +#if ENABLE_STACK_OFFLOAD + +#include "atheros_stack_offload.h" + +#define COMMAND_BLOCK_TIMEOUT (960000) // Socket will block for this period in msec, if no +// response is received, socket will unblock +#define TRANSMIT_BLOCK_TIMEOUT (900000) // Time in ms for which a send operation blocks, +// after this time, error is returned to application +#define LAST_FRAGMENT (0x01) // Indicates this is the last fragment +#define RX_DIRECTION (0) +#define TX_DIRECTION (1) +#define TCP_CONNECTION_AVAILABLE (99) // Sent by Target in Listen event that a new TCP +// incoming connection is available. Application +// should call accept on receving this from target. + +/* Wait 1 minute for DHCP response, report error otherwise */ +#ifndef DHCP_WAIT_TIME +#define DHCP_WAIT_TIME (60000) +#endif + +/* Wait 1 second for IPCONFIG response, report error otherwise */ +#ifndef IPCONFIG_WAIT_TIME +#define IPCONFIG_WAIT_TIME (1000) +#endif + +/* Wait 2 minutes for AUTOIP/DHCP response, report error otherwise */ +#ifndef DHCP_AUTO_WAIT_TIME +#define DHCP_AUTO_WAIT_TIME (60000 * 2) +#endif + +#define TCP_MSS 1452 +#if DEBUG +#define DEBUG_PRINT(arg) // User may define +#endif + +#define TCP_FIN 1 +#define TCP_LISTEN 2 +#define TCP_CONNECTED 4 + +enum SOCKET_CMDS +{ + SOCK_OPEN = 0, /*0x00 - Open a socket*/ + SOCK_CLOSE, /*0x01 - Close existing socket*/ + SOCK_CONNECT, /*0x02 - Connect to a peer*/ + SOCK_BIND, /*0x03 - Bind to interface*/ + SOCK_LISTEN, /*0x04 - Listen on socket*/ + SOCK_ACCEPT, /*0x05 - Accept incoming connection*/ + SOCK_SELECT, /*0x06 - Wait for specified file descriptors*/ + SOCK_SETSOCKOPT, /*0x07 - Set specified socket option*/ + SOCK_GETSOCKOPT, /*0x08 - Get socket option*/ + SOCK_ERRNO, /*0x09 - Get error number for last error*/ + SOCK_IPCONFIG, /*0x0A - Set static IP information, or get current IP config*/ + SOCK_PING, /*0x0B*/ + SOCK_STACK_INIT, /*0x0C - Command to initialize stack*/ + SOCK_STACK_MISC, /*0x0D - Used to exchanges miscellaneous info, e.g. reassembly etc*/ + SOCK_PING6, /*0x0E*/ + SOCK_IP6CONFIG, /*0x0F - Set static IP information, or get current IP config*/ + SOCK_IPCONFIG_DHCP_POOL, /*0x10 - Set DHCP Pool */ + SOCK_IP6CONFIG_ROUTER_PREFIX, /*0x11 - Set ipv6 router prefix */ + SOCK_IP_SET_TCP_EXP_BACKOFF_RETRY, /*0x12 - set tcp exponential backoff retry */ + SOCK_IP_SET_IP6_STATUS, /*0x13 - set ip6 module status enable/disable */ + SOCK_IP_DHCP_RELEASE, /*0x14 - Release the DHCP IP Addres */ + SOCK_IP_SET_TCP_RX_BUF, /*0x15 - set tcp rx buffer space */ + SOCK_HTTP_SERVER, /*0x16 - Http Server Command */ + SOCK_HTTP_SERVER_CMD, /*0x17 - Commands to get and post data */ + SOCK_DNC_CMD, /*0x18 - Commands related to resolver */ + SOCK_DNC_ENABLE, /*0x19 - Command to enable/disable DNS Client */ + SOCK_DNS_SRVR_CFG_ADDR, /*0x1A - Command to configure DNS Server Address */ + SOCK_HTTPC, /*0x1B - HTTP Client commands */ + SOCK_DNS_LOCAL_DOMAIN, /*0x1C - Configures the local domain */ + SOCK_IP_HOST_NAME, /*0x1D - Configures the local host name */ + SOCK_IP_DNS, /*0x1F - Configures DNS Database */ + SOCK_IP_SNTP_SRVR_ADDR, /*0x1F - Configures the sntp server addr */ + SOCK_IP_SNTP_GET_TIME, /*0x20 - GET UTC Time from SNTP Client */ + SOCK_IP_SNTP_GET_TIME_OF_DAY, /*0x21 - Get time of day (secs) */ + SOCK_IP_SNTP_CONFIG_TIMEZONE_DSE, /*0x22 - Command to modify time zone and to enable/disable DSE */ + SOCK_IP_SNTP_QUERY_SNTP_ADDRESS, /*0x23 - Command to query SNTP Server Address */ + SOCK_IP_SNTP_CLIENT_ENABLE, /*0x24 - Command to enable/disable SNTP client */ + SOCK_IPV4_ROUTE, /*0x25 - Commands to add,del and show IPv4 routes */ + SOCK_IPV6_ROUTE, /*0x26 - Commands to add,del and show IPv6 routes */ + SOCK_IP_BRIDGEMODE, /*0x27 - Command to enable bridge mode */ + SOCK_DNS_SERVER_STATUS, /*0x28 - Command to enable/disable DNS Server*/ + SOCK_SSL_CTX_NEW, /*0x29 - Create a new SSL context */ + SOCK_SSL_CTX_FREE, /*0x2A - Free/close SSL context */ + SOCK_SSL_NEW, /*0x2B - Create new SSL connection object/instance */ + SOCK_SSL_SET_FD, /*0x2C - Add socket handle to a SSL connection */ + SOCK_SSL_ACCEPT, /*0x2D - Accept SSL connection request from SSL client */ + SOCK_SSL_CONNECT, /*0x2E - Establish SSL connection from SSL client to SSL server */ + SOCK_SSL_SHUTDOWN, /*0x2F - Shutdown/close SSL connection */ + SOCK_SSL_ADD_CERT, /*0x30 - Add a certificate to SSL context */ + SOCK_SSL_STORE_CERT, /*0x31 - Store a certificate or CA list file in FLASH */ + SOCK_SSL_LOAD_CERT, /*0x32 - Reads a certificate or CA list from FLASH and adds it to SSL context */ + SOCK_SSL_CONFIGURE, /*0x33 - Configure a SSL connection */ + SOCK_SSL_LIST_CERT, /*0x34 - Request the names of the cert's stored in FLASH */ + SOCK_GET_DEV_ID_FROM_DEST_IP, /*0x35 - Gets the device ID for the given destination IP address */ + SOCK_OTA_UPGRADE, /*0x36 - Intializes OTA upgrade */ + SOCK_OTA_READ, /*0x37 - Reads OTA Area after OTA download */ + SOCK_OTA_DONE, /*0x38 - OTA download Complete Event */ + SOCK_SET_DHCP_HOSTNAME, /*0x39 - set the DHCP Hostname */ + SOCK_TCP_CONN_TIMEOUT, /*0x3A - TCP Connection Timeout */ + SOCK_HTTP_POST_EVENT, /*0x3B - HTTP server post event */ + SOCK_OTA_SESSION_START, /*0x3C - start OTA session */ + SOCK_OTA_PARTITION_GET_SIZE, /*0x3D - start OTA session */ + SOCK_OTA_PARTITION_ERASE, /*0x3E - start OTA session */ + SOCK_OTA_PARSE_IMAGE_HDR, /*0x3F - parse OTA image header */ + SOCK_OTA_PARTITION_VERIFY_CHECKSUM, /*0x40 - veirfy OTA partition checksum */ + SOCK_OTA_PARTITION_WRITE_DATA, /*0x41 - write OTA partition data */ + SOCK_DHCPS_SUCCESS_CALLBACK, /*0x42 - DHCP Server callback event */ + SOCK_DHCPC_SUCCESS_CALLBACK, /*0x43 - DHCP Client callback event */ + /************************************/ + /* add new socket commands above this line */ + /************************************/ + SOCK_CMD_LAST /* NOTE: ensure that this is the last entry in the enum */ +}; + +/***socket context. This must be adjusted based on the underlying OS ***/ +typedef struct socket_context +{ + A_EVENT sockRxWakeEvent; // Event to unblock waiting RX socket + A_EVENT sockTxWakeEvent; // Event to unblock waiting TX socket + A_NETBUF_QUEUE_T rxqueue; // Queue to hold incoming packets + uint8_t blockFlag; + boolean respAvailable; // Flag to indicate a response from target is available + boolean txUnblocked; + boolean txBlock; + boolean rxBlock; + int32_t driver_error; +#if NON_BLOCKING_TX + A_NETBUF_QUEUE_T non_block_queue; // Queue to hold packets to be freed later + A_MUTEX_T nb_tx_mutex; // Mutex to synchronize access to non blocking queue +#endif +} SOCKET_CONTEXT, *SOCKET_CONTEXT_PTR; + +#define GET_SOCKET_CONTEXT(ctxt) ((SOCKET_CONTEXT_PTR)(((ATH_SOCKET_CONTEXT_PTR)ctxt)->sock_context)) + +typedef struct ath_socket_context +{ + int32_t handle; // Socket handle + uint32_t sock_st_mask[SOCK_CMD_LAST / 32 + 1]; + int32_t result; // API return value + void *sock_context; // Pointer to custom socket context + void *pReq; // Used to hold wmi netbuf to be freed from the user thread + uint8_t *data; // Generic pointer to data recevied from target + uint8_t domain; // IPv4/v6 + uint8_t type; // TCP vs UDP + uint16_t remaining_bytes; + void *old_netbuf; +#if ENABLE_SSL + SSL *ssl; // SSL connection object +#endif + uint8_t TCPCtrFlag; +} ATH_SOCKET_CONTEXT, *ATH_SOCKET_CONTEXT_PTR; + +typedef struct ath_sock_stack_init +{ + uint8_t stack_enabled; // Flag to indicate if stack should be enabled in the target + uint8_t num_sockets; // number of sockets supported by the host + uint8_t num_buffers; // Number of RX buffers supported by host + uint8_t reserved; +} ATH_STACK_INIT; + +typedef PREPACK struct sock_open +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t domain FIELD_PACKED; // ATH_AF_INET, ATH_AF_INET6 + uint32_t type FIELD_PACKED; // SOCK_STREAM_TYPE, SOCK_DGRAM_TYPE + uint32_t protocol FIELD_PACKED; // 0 +} POSTPACK SOCK_OPEN_T; + +typedef PREPACK struct sock_close +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t handle FIELD_PACKED; // socket handle +} POSTPACK SOCK_CLOSE_T; + +typedef PREPACK struct sock_connect_cmd +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t handle FIELD_PACKED; // socket handle + PREPACK union + { + SOCKADDR_T name FIELD_PACKED; + SOCKADDR_6_T name6 FIELD_PACKED; + } POSTPACK addr; + uint16_t length FIELD_PACKED; // socket address length +} POSTPACK SOCK_CONNECT_CMD_T, SOCK_BIND_CMD_T, SOCK_ACCEPT_CMD_T; + +typedef PREPACK struct sock_connect_recv +{ + uint32_t handle FIELD_PACKED; // socket handle + PREPACK union + { + SOCKADDR_T name FIELD_PACKED; + SOCKADDR_6_T name6 FIELD_PACKED; + } POSTPACK addr; + uint16_t length FIELD_PACKED; // socket address length +} POSTPACK SOCK_CONNECT_RECV_T, SOCK_BIND_RECV_T, SOCK_ACCEPT_RECV_T; + +typedef PREPACK struct sock_errno +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t errno; +} POSTPACK SOCK_ERRNO_T; + +typedef struct sock_listen +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t handle FIELD_PACKED; // Socket handle + uint32_t backlog FIELD_PACKED; // Max length of queue of backlog connections +} POSTPACK SOCK_LISTEN_T; + +typedef PREPACK struct sock_setopt +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t handle FIELD_PACKED; // socket handle + uint32_t level FIELD_PACKED; // Option level (ATH_IPPROTO_IP, ATH_IPPROTO_UDP, ATH_IPPROTO_TCP...) + uint32_t optname FIELD_PACKED; // Choose from list above + uint32_t optlen FIELD_PACKED; // option of length + uint8_t optval[1] FIELD_PACKED; // option value +} POSTPACK SOCK_OPT_T; + +typedef PREPACK struct ipconfig_recv +{ + uint32_t mode FIELD_PACKED; // 0-query, 1-static, 2-dhcp + uint32_t ipv4 FIELD_PACKED; // IPv4 address + uint32_t subnetMask FIELD_PACKED; + uint32_t gateway4 FIELD_PACKED; + IP6_ADDR_T ipv6LinkAddr FIELD_PACKED; /* IPv6 Link Local address */ + IP6_ADDR_T ipv6GlobalAddr FIELD_PACKED; /* IPv6 Global address */ + IP6_ADDR_T ipv6DefGw FIELD_PACKED; /* IPv6 Default Gateway */ + IP6_ADDR_T ipv6LinkAddrExtd FIELD_PACKED; /* IPv6 Link Local address for Logo*/ + int32_t LinkPrefix FIELD_PACKED; + int32_t GlbPrefix FIELD_PACKED; + int32_t DefGwPrefix FIELD_PACKED; + int32_t GlbPrefixExtd FIELD_PACKED; + IP46ADDR dnsaddr[MAX_DNSADDRS] FIELD_PACKED; + char hostname[33] FIELD_PACKED; +} POSTPACK IPCONFIG_RECV_T; + +typedef PREPACK struct ipconfig +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t mode FIELD_PACKED; // 0-query, 1-static, 2-dhcp + uint32_t ipv4 FIELD_PACKED; // IPv4 address + uint32_t subnetMask FIELD_PACKED; + uint32_t gateway4 FIELD_PACKED; + IP6_ADDR_T ipv6LinkAddr FIELD_PACKED; /* IPv6 Link Local address */ + IP6_ADDR_T ipv6GlobalAddr FIELD_PACKED; /* IPv6 Global address */ + IP6_ADDR_T ipv6DefGw FIELD_PACKED; /* IPv6 Default Gateway */ + IP6_ADDR_T ipv6LinkAddrExtd FIELD_PACKED; /* IPv6 Link Local address for Logo*/ + int32_t LinkPrefix; + int32_t GlbPrefix; + int32_t DefGwPrefix; + int32_t GlbPrefixExtd; +} POSTPACK IPCONFIG_CMD_T; + +typedef PREPACK struct ping +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ip_addr FIELD_PACKED; // Destination IPv4 address + uint32_t size FIELD_PACKED; +} POSTPACK PING_T; + +typedef PREPACK struct ping6 +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t ip6addr[16] FIELD_PACKED; // Destination IPv6 address + uint32_t size FIELD_PACKED; +} POSTPACK PING_6_T; + +typedef PREPACK struct ipconfigdhcppool +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t startaddr FIELD_PACKED; + uint32_t endaddr FIELD_PACKED; + int32_t leasetime FIELD_PACKED; +} POSTPACK IPCONFIG_DHCP_POOL_T; + +typedef PREPACK struct ip6config_router_prefix +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t v6addr[16] FIELD_PACKED; + int32_t prefixlen FIELD_PACKED; + int32_t prefix_lifetime FIELD_PACKED; + int32_t valid_lifetime FIELD_PACKED; +} POSTPACK IP6CONFIG_ROUTER_PREFIX_T; + +typedef PREPACK struct sock_ip_backoff +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t max_retry FIELD_PACKED; +} POSTPACK SOCK_IP_BACKOFF_T; + +typedef PREPACK struct sock_ipv6_status +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint16_t ipv6_status FIELD_PACKED; +} POSTPACK SOCK_IPv6_STATUS_T; + +typedef PREPACK struct sock_ip_bridgemode +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint16_t bridgemode FIELD_PACKED; +} POSTPACK SOCK_IP_BRIDGEMODE_T; + +typedef PREPACK struct sock_ip_dhcp_release +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint16_t ifIndex FIELD_PACKED; +} POSTPACK SOCK_IP_DHCP_RELEASE_T; + +typedef PREPACK struct sock_ip_tcp_rx_buf +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t rxbuf FIELD_PACKED; +} POSTPACK SOCK_IP_TCP_RX_BUF_T; + +typedef PREPACK struct sock_ip_http_server +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t enable FIELD_PACKED; +} POSTPACK SOCK_IP_HTTP_SERVER_T; + +typedef PREPACK struct sock_ip_http_server_cmd +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t command FIELD_PACKED; + uint8_t pagename[32] FIELD_PACKED; + uint8_t objname[32] FIELD_PACKED; + uint32_t objlen FIELD_PACKED; + uint8_t value[32] FIELD_PACKED; +} POSTPACK SOCK_IP_HTTP_SERVER_CMD_T; + +typedef PREPACK struct sock_ip_dns_client +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t command FIELD_PACKED; +} POSTPACK SOCK_IP_DNS_CLIENT_T; + +typedef PREPACK struct sock_ip_dns_config_server_addr +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + IP46ADDR addr FIELD_PACKED; // Server address +} POSTPACK SOCK_IP_CFG_DNS_SRVR_ADDR; + +typedef PREPACK struct sock_ip_dns_local_domain +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + char domain_name[33] FIELD_PACKED; // Server address +} POSTPACK SOCK_IP_CFG_DNS_LOCAL_DOMAIN; + +typedef PREPACK struct sock_ip_dns_hostname +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + char domain_name[33] FIELD_PACKED; // Server address +} POSTPACK SOCK_IP_CFG_HOST_NAME; + +typedef PREPACK struct sock_ip_dns +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t command FIELD_PACKED; + char domain_name[36] FIELD_PACKED; // Server address + IP46ADDR addr FIELD_PACKED; +} POSTPACK SOCK_IP_DNS_T; + +typedef PREPACK struct sock_ip_dns_server +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t enable FIELD_PACKED; +} POSTPACK SOCK_IP_DNS_SERVER_STATUS_T; + +#if ENABLE_HTTP_CLIENT +typedef PREPACK struct httpc_command +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t command FIELD_PACKED; + uint8_t url[256] FIELD_PACKED; + uint8_t data[128] FIELD_PACKED; +} POSTPACK SOCK_HTTPC_T; +#endif /* ENABLE_HTTP_CLIENT */ + +typedef PREPACK struct sock_ip_sntp_local_domain +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t command FIELD_PACKED; + char addr[68] FIELD_PACKED; // Server address +} POSTPACK SOCK_IP_CFG_SNTP_SRVR_ADDR; + +typedef PREPACK struct sock_ip_sntp_zone +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t hour FIELD_PACKED; + uint8_t min FIELD_PACKED; + uint8_t add_sub FIELD_PACKED; // add=1,sub=0 + uint8_t dse FIELD_PACKED; // enable/disable day light saving +} POSTPACK SOCK_SNTP_MODIFY_TIMEZONE; + +typedef PREPACK struct sock_ip_sntp_config +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + tSntpDnsAddr SntpDnsAddr[MAX_SNTP_SERVERS] FIELD_PACKED; +} POSTPACK SOCK_IP_QUERY_SNTP_CONFIG; + +typedef PREPACK struct sDestIpToDevMapEvtType +{ + int8_t result; + uint8_t domain; + int16_t device_id; + PREPACK union + { + uint32_t ip_addr FIELD_PACKED; + IP6_ADDR_T ip6_addr FIELD_PACKED; + } POSTPACK dev_addr; + PREPACK union + { + uint32_t ip_addr FIELD_PACKED; + IP6_ADDR_T ip6_addr FIELD_PACKED; + } POSTPACK dest_addr; +} POSTPACK tDestIpToDevMapEvtType; + +typedef PREPACK struct sock_destip_dev_map_evt_type +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + tDestIpToDevMapEvtType ipToDevMap FIELD_PACKED; +} POSTPACK WMI_SOCK_DESTIP_TO_DEV_MAP_EVENT; + +typedef PREPACK struct sock_ip_sntp_client +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t command FIELD_PACKED; +} POSTPACK SOCK_IP_SNTP_CLIENT_T; + +typedef PREPACK struct sock_ipv4_route +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + int32_t command FIELD_PACKED; + uint32_t address FIELD_PACKED; + uint32_t mask FIELD_PACKED; + uint32_t gateway FIELD_PACKED; + uint32_t ifIndex FIELD_PACKED; + uint32_t prot FIELD_PACKED; +} POSTPACK SOCK_IPV4_ROUTE_T; + +typedef PREPACK struct sock_ipv6_route +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t command FIELD_PACKED; + uint8_t address[16] FIELD_PACKED; + int32_t prefixLen FIELD_PACKED; + uint8_t nexthop[16] FIELD_PACKED; + uint32_t ifIndex FIELD_PACKED; + uint32_t prot FIELD_PACKED; +} POSTPACK SOCK_IPV6_ROUTE_T; + +typedef PREPACK struct sock_tcp_conn_timeout +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t timeout_val; +} POSTPACK SOCK_TCP_CONN_TIMEOUT_T; + +typedef PREPACK struct sock_ota_upgrade +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ipaddress FIELD_PACKED; + char filename[256] FIELD_PACKED; + uint8_t mode FIELD_PACKED; + uint8_t preserve_last FIELD_PACKED; + uint8_t protocol FIELD_PACKED; +} POSTPACK SOCK_OTA_UPGRADE_T; + +typedef PREPACK struct sock_ota_read_ota_area +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t offset; + uint32_t size; +} POSTPACK SOCK_OTA_READ_OTA_AREA_T; + +typedef PREPACK struct sock_ota_done +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t data; +} POSTPACK SOCK_OTA_DONE_T; + +typedef PREPACK struct sock_ota_session_start_s +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t flags; + uint32_t partition_index; +} POSTPACK SOCK_OTA_SESSION_START_T; + +typedef PREPACK struct sock_ota_parse_image_hdr_s +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t header[40]; +} POSTPACK SOCK_OTA_PARSE_IMAGE_HDR_T; + +typedef PREPACK struct sock_ota_partion_write_data_s +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t offset; + uint32_t size; + uint8_t data[1]; +} POSTPACK SOCK_OTA_PARTITON_WRITE_DATA_T; + +typedef PREPACK struct dhcps_success_cb_resp +{ + uint32_t resp_code; + uint8_t mac[16]; + uint32_t ip; +} POSTPACK SOCK_DHCPS_SUCCESS_CALLBACK_T; + +typedef PREPACK struct dhcpc_success_cb_resp +{ + uint32_t resp_code; + uint32_t ip; + uint32_t mask; + uint32_t gw; +} POSTPACK SOCK_DHCPC_SUCCESS_CALLBACK_T; + +/*This structure is sent to the target in a data packet. + It allows the target to route the data to correct socket with + all the necessary parameters*/ +typedef PREPACK struct sock_send +{ + uint32_t handle FIELD_PACKED; // Socket handle + uint16_t length FIELD_PACKED; // Payload length + uint16_t reserved FIELD_PACKED; // Reserved + uint32_t flags FIELD_PACKED; // Send flags + SOCKADDR_T name FIELD_PACKED; // IPv4 destination socket information + uint16_t socklength FIELD_PACKED; +} POSTPACK SOCK_SEND_T; + +typedef PREPACK struct sock_send6 +{ + uint32_t handle FIELD_PACKED; // Socket handle + uint16_t length FIELD_PACKED; // Payload length + uint16_t reserved FIELD_PACKED; // Reserved + uint32_t flags FIELD_PACKED; // Send flags + SOCKADDR_6_T name6 FIELD_PACKED; // IPv6 destination socket information + uint16_t socklength FIELD_PACKED; +} POSTPACK SOCK_SEND6_T; + +typedef PREPACK struct sock_recv +{ + uint32_t handle FIELD_PACKED; // Socket handle + SOCKADDR_T name FIELD_PACKED; // IPv4 destination socket information + uint16_t socklength FIELD_PACKED; // Length of sockaddr structure + uint16_t reserved FIELD_PACKED; // Length of sockaddr structure + uint32_t reassembly_info FIELD_PACKED; // Placeholder for reassembly info +} POSTPACK SOCK_RECV_T; + +typedef PREPACK struct sock_recv6 +{ + uint32_t handle FIELD_PACKED; // Socket handle + SOCKADDR_6_T name6 FIELD_PACKED; // IPv6 destination socket information + uint16_t socklength FIELD_PACKED; + uint16_t reserved FIELD_PACKED; // Reserved + uint32_t reassembly_info FIELD_PACKED; // Placeholder for reassembly info +} POSTPACK SOCK_RECV6_T; + +#if ENABLE_SSL +typedef PREPACK struct sock_ssl_new +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ctx FIELD_PACKED; // SSL context +} POSTPACK SOCK_SSL_NEW_T; + +typedef PREPACK struct sock_ssl_set_fd +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ssl FIELD_PACKED; // SSL connection object + uint32_t fd FIELD_PACKED; // Socket handle +} POSTPACK SOCK_SSL_SET_FD_T; + +typedef PREPACK struct sock_ssl_accept +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ssl FIELD_PACKED; // SSL connection object +} POSTPACK SOCK_SSL_ACCEPT_T; + +typedef PREPACK struct sock_ssl_connect +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ssl FIELD_PACKED; // SSL connection object +} POSTPACK SOCK_SSL_CONNECT_T; + +typedef PREPACK struct sock_ssl_shutdown +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ssl FIELD_PACKED; // SSL connection object +} POSTPACK SOCK_SSL_SHUTDOWN_T; + +typedef PREPACK struct sock_ssl_configure +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ssl FIELD_PACKED; // SSL connection object + uint32_t size FIELD_PACKED; // the size of the configuration data + uint8_t data[sizeof(SSL_CONFIG)] FIELD_PACKED; // The configuration data +} POSTPACK SOCK_SSL_CONFIGURE_T; + +typedef PREPACK struct sock_ssl_ctx_new +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t role FIELD_PACKED; + int32_t inbufSize FIELD_PACKED; + int32_t outbufSize FIELD_PACKED; + int32_t reserved FIELD_PACKED; +} POSTPACK SOCK_SSL_CTX_NEW_T; + +typedef PREPACK struct sock_ssl_ctx_free +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ctx FIELD_PACKED; // SSL context +} POSTPACK SOCK_SSL_CTX_FREE_T; + +typedef PREPACK struct sock_ssl_add_cert +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ctx FIELD_PACKED; // SSL context + uint32_t type FIELD_PACKED; // Type: 1 for device certificate, 2: CA list + uint32_t total FIELD_PACKED; // The size of ca_list + uint32_t offset FIELD_PACKED; // offset of this fragment + uint32_t size FIELD_PACKED; // fragment size + uint8_t data[1] FIELD_PACKED; // CA list or certificate data +} POSTPACK SOCK_SSL_ADD_CERT_T; + +typedef PREPACK struct sock_ssl_store_cert +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint8_t name[32] FIELD_PACKED; // The name of the certificate or CA list + uint32_t total FIELD_PACKED; // The size of the certificate or CA list + uint32_t offset FIELD_PACKED; // offset of this fragment + uint32_t size FIELD_PACKED; // fragment size + uint8_t data[1] FIELD_PACKED; // certificate or CA list data +} POSTPACK SOCK_SSL_STORE_CERT_T; + +typedef PREPACK struct sock_ssl_load_cert +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t ctx FIELD_PACKED; // SSL context + uint32_t type FIELD_PACKED; // Type: 1 for device certificate, 2: CA list + uint8_t name[32] FIELD_PACKED; // The name of the certificate or CA list +} POSTPACK SOCK_SSL_LOAD_CERT_T; + +typedef PREPACK struct sock_ssl_list_cert +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t reserved FIELD_PACKED; +} POSTPACK SOCK_SSL_LIST_CERT_T; + +#endif + +typedef PREPACK struct sock_get_dev_from_dest_ip +{ + WMI_SOCKET_CMD wmi_cmd FIELD_PACKED; + uint32_t handle FIELD_PACKED; // socket handle + PREPACK union + { + uint32_t ipaddr FIELD_PACKED; + IP6_ADDR_T ip6addr FIELD_PACKED; + } POSTPACK addr; + uint8_t domain FIELD_PACKED; // socket domain +} POSTPACK SOCK_GET_DEV_FROM_DEST_T; + +//#define SOCK_EV_MASK_SET(_pcxt, _cmd) (_pcxt)->sock_st_mask[(_cmd) >> 5] |= ((uint32_t)((uint32_t)1 << ((_cmd)&0x1f))) +static inline void SOCK_EV_MASK_SET(ATH_SOCKET_CONTEXT *_pcxt, uint32_t _cmd) +{ + _pcxt->sock_st_mask[(_cmd) >> 5] |= ((uint32_t)((uint32_t)1 << ((_cmd)&0x1f))); +} + +//#define SOCK_EV_MASK_CLEAR(_pcxt, _cmd) (_pcxt)->sock_st_mask[(_cmd) >> 5] &= ((uint32_t)(~((uint32_t)1 << ((_cmd)&0x1f)))) +static inline void SOCK_EV_MASK_CLEAR(ATH_SOCKET_CONTEXT *_pcxt, uint32_t _cmd) +{ + _pcxt->sock_st_mask[(_cmd) >> 5] &= ((uint32_t)(~((uint32_t)1 << ((_cmd)&0x1f)))); +} + +//#define SOCK_EV_MASK_TEST(_pcxt, _cmd) (( ((uint32_t)(_pcxt)->sock_st_mask[(_cmd) >> 5]) & ((uint32_t)((uint32_t)1 << ((_cmd)&0x1f))) ) ? 1 : 0) +static inline uint32_t SOCK_EV_MASK_TEST(ATH_SOCKET_CONTEXT *_pcxt, uint32_t _cmd) +{ + uint32_t tmp = ( ((uint32_t)(_pcxt)->sock_st_mask[(_cmd) >> 5]) & ((uint32_t)((uint32_t)1 << ((_cmd)&0x1f))) ); + return tmp ? 1 : 0; +} + +extern ATH_SOCKET_CONTEXT *ath_sock_context[]; + +/************************** Internal Function declarations*****************************/ + +uint32_t queue_empty(uint32_t index); + +#define QUEUE_EMPTY(index) queue_empty((index)) + +#define BLOCK_FOR_DATA(pCxt, ctxt, msec, direction) blockForDataRx((pCxt), (ctxt), (msec), (direction)) + +/******* Function Declarations *******************/ +A_STATUS unblock(void *ctxt, uint8_t direction); +A_STATUS blockForResponse(void *pCxt, void *ctxt, uint32_t msec, uint8_t direction); +A_STATUS blockForDataRx(void *pCxt, void *ctxt, uint32_t msec, uint8_t direction); + +#define BLOCK(pCxt, ctxt, msec, direction) blockForResponse((pCxt), (ctxt), (msec), (direction)) + +#define UNBLOCK(ctxt, direction) unblock((ctxt), (direction)) + +#if T_SELECT_VER1 +A_STATUS unblockSelect(void *ctxt); +A_STATUS blockSelect(void *pCxt, uint32_t msec); +#endif + +#if T_SELECT_VER1 + +#define BLOCK_SELECT(pCxt, msec) blockSelect((pCxt), (msec)) + +#define UNBLOCK_SELECT(pCxt) unblockSelect((pCxt)) +#else + +#define BLOCK_SELECT(pCxt, msec) + +#define UNBLOCK_SELECT(pCxt) + +#endif // T_SELECT_VER1 + +void socket_set_driver_error(void *ctxt, int32_t error); +int32_t socket_get_driver_error(void *ctxt); +A_STATUS socket_context_init(void); +int32_t find_socket_context(uint32_t handle, uint8_t retrieve); +uint32_t getTransportLength(uint8_t proto); +uint32_t getIPLength(uint8_t version); +A_STATUS move_power_state_to_maxperf(void *pDCxt, int32_t module); +A_STATUS restore_power_state(void *pDCxt, int32_t module); + +/************************* Socket APIs *************************************************/ +int32_t Api_socket(void *pCxt, uint32_t domain, uint32_t type, uint32_t protocol); +int32_t Api_shutdown(void *pCxt, uint32_t handle); +int32_t Api_connect(void *pCxt, uint32_t handle, void *name, uint16_t length); +int32_t Api_bind(void *pCxt, uint32_t handle, void *name, uint16_t length); +int32_t Api_listen(void *pCxt, uint32_t handle, uint32_t backlog); +int32_t Api_accept(void *pCxt, uint32_t handle, void *name, socklen_t length); + +#if T_SELECT_VER1 +int32_t Api_accept_ver1(void *pCxt, uint32_t handle, void *name, socklen_t length); +int32_t Api_select_ver1(void *pCxt, int32_t num, uint32_t *r_fd, uint32_t *w_fd, uint32_t *e_fd, uint32_t tv); +#endif + +int32_t Api_sendto(void *pCxt, + uint32_t handle, + uint8_t *buffer, + uint32_t length, + uint32_t flags, + SOCKADDR_T *name, + uint32_t socklength); +int32_t Api_select(void *pCxt, uint32_t handle, uint32_t tv); +int32_t Api_errno(void *pCxt, uint32_t handle); +int32_t Api_getsockopt(void *pCxt, uint32_t handle, uint32_t level, uint32_t optname, uint8_t *optval, uint32_t optlen); +int32_t Api_setsockopt(void *pCxt, uint32_t handle, uint32_t level, uint32_t optname, uint8_t *optval, uint32_t optlen); +#if ZERO_COPY +int32_t Api_recvfrom( + void *pCxt, uint32_t handle, void **buffer, uint32_t length, uint32_t flags, void *name, socklen_t *socklength); +#else +int32_t Api_recvfrom( + void *pCxt, uint32_t handle, void *buffer, uint32_t length, uint32_t flags, void *name, socklen_t *socklength); +#endif +int32_t Api_ipconfig(void *pCxt, + uint32_t mode, + uint32_t *ipv4_addr, + uint32_t *subnetMask, + uint32_t *gateway4, + IP46ADDR *dnsaddr, + char *hostname); +void clear_socket_context(int32_t index); +int32_t Api_ping(void *pCxt, uint32_t ipv4_addr, uint32_t size, uint32_t ms_interval); +int32_t Api_ping6(void *pCxt, uint8_t *ip6addr, uint32_t size, uint32_t ms_interval); +int32_t Api_ip6config(void *pCxt, + uint32_t mode, + IP6_ADDR_T *v6Global, + IP6_ADDR_T *v6Link, + IP6_ADDR_T *v6DefGw, + IP6_ADDR_T *v6GlobalExtd, + int32_t *LinkPrefix, + int32_t *GlbPrefix, + int32_t *DefgwPrefix, + int32_t *GlbPrefixExtd); +A_STATUS send_stack_init(void *pCxt); +void socket_context_deinit(void); +int32_t Api_ipconfig_dhcp_pool(void *pCxt, uint32_t *start_ipv4_addr, uint32_t *end_ipv4_addr, int32_t leasetime); +int32_t Api_ip6config_router_prefix( + void *pCxt, IP6_ADDR_T *v6addr, int32_t prefixlen, int32_t prefix_lifetime, int32_t valid_lifetime); +int32_t Api_ipconfig_set_tcp_exponential_backoff_retry(void *pCxt, int32_t retry); +int32_t Api_ipconfig_set_ip6_status(void *pCxt, uint16_t status); +int32_t Api_ipconfig_dhcp_release(void *pCxt); +int32_t Api_ipbridgemode(void *handle, uint16_t status); +int32_t Api_ipconfig_set_tcp_rx_buffer(void *pCxt, int32_t rxbuf); +int32_t Api_ip_http_server(void *pCxt, int32_t command); +int32_t Api_ip_http_server_method( + void *pCxt, int32_t command, uint8_t *pagename, uint8_t *objname, int32_t objtype, int32_t objlen, uint8_t *value); +int32_t Api_httpc_method(void *pCxt, uint32_t command, uint8_t *url, uint8_t *data, uint8_t **output); +int32_t Api_ip_resolve_host_name(void *pCxt, DNC_CFG_CMD *DncCfg, DNC_RESP_INFO *DncRespInfo); +int32_t Api_ip_dns_client(void *pCxt, int32_t command); +int32_t Api_ip_dns_server_addr(void *pCxt, IP46ADDR *addr); +int32_t Api_ip_dns_local_domain(void *pCxt, char *domain_name); +int32_t Api_ip_hostname(void *pCxt, char *domain_name); +int32_t Api_ipdns(void *pCxt, int32_t command, char *domain_name, IP46ADDR *dnsaddr); +int32_t Api_ip_sntp_srvr_addr(void *pCxt, int32_t command, char *sntp_srvr_addr); +int32_t Api_ip_sntp_get_time(void *pCxt, tSntpTime *SntpTime); +int32_t Api_ip_sntp_get_time_of_day(void *pCxt, tSntpTM *SntpTm); +int32_t Api_ip_sntp_modify_zone_dse(void *pCxt, uint8_t hr, uint8_t mn, uint8_t zone_cal, uint8_t dse_en_dis); +int32_t Api_ip_sntp_query_srvr_address(void *pcxt, tSntpDnsAddr SntpDnsAddr[MAX_SNTP_SERVERS]); +int32_t Api_ip_sntp_client(void *pCxt, int32_t command); + +int32_t Api_tcp_connection_timeout(void *pCxt, uint32_t timeout_val); + +int32_t Api_ota_upgrade(void *pCxt, + uint32_t addr, + char *filename, + uint8_t mode, + uint8_t preserve_last, + uint8_t protocol, + uint32_t *resp_code, + uint32_t *length); +int32_t Api_ota_read_area(void *pCxt, uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *retlen); +int32_t Api_ota_done(void *pCxt, boolean good_image); +int32_t Api_ota_session_start(void *pCxt, uint32_t flags, uint32_t partition_index); +uint32_t Api_ota_partition_get_size(void *pCxt); +int32_t Api_ota_partition_erase(void *pCxthandle); +int32_t Api_ota_partition_verify_checksum(void *pCxthandle); +int32_t Api_ota_parse_image_hdr(void *pCxt, uint8_t *header, uint32_t *offset); +int32_t Api_ota_partition_write_data(void *pCxt, uint32_t offset, uint8_t *buf, uint32_t size, uint32_t *ret_size); + +#if ENABLE_ROUTING_CMDS +int32_t Api_ipv4_route(void *pCxt, + uint32_t command, + IP_ADDR_T *ipv4_addr, + IP_ADDR_T *subnetMask, + IP_ADDR_T *gateway, + uint32_t *ifIndex, + IPV4_ROUTE_LIST_T *routelist); +int32_t Api_ipv6_route(void *pCxt, + uint32_t command, + IP6_ADDR_T *ipv6_addr, + uint32_t *prefixLen, + IP6_ADDR_T *gateway, + uint32_t *ifIndex, + IPV6_ROUTE_LIST_T *routelist); +#endif + +int32_t Api_ip_dns_server(void *pCxt, int32_t command); +#if ENABLE_SSL +SSL_CTX *Api_SSL_ctx_new(void *pCxt, SSL_ROLE_T role, int32_t inbufSize, int32_t outbufSize, int32_t reserved); +int32_t Api_SSL_ctx_free(void *pCxt, SSL_CTX *ctx); +SSL *Api_SSL_new(void *pCxt, SSL_CTX *ctx); +int32_t Api_SSL_set_fd(void *pCxt, SSL *ssl, uint32_t fd); +int32_t Api_SSL_accept(void *pCxt, SSL *ssl); +int32_t Api_SSL_connect(void *pCxt, SSL *ssl); +int32_t Api_SSL_shutdown(void *pCxt, SSL *ssl); +int32_t Api_SSL_configure(void *pCxt, SSL *ssl, SSL_CONFIG *cfg); +int32_t Api_SSL_addCert(void *pCxt, SSL_CTX *ctx, SSL_CERT_TYPE_T type, uint8_t *cert, uint32_t size); +int32_t Api_SSL_storeCert(void *pCxt, char *name, uint8_t *cert, uint32_t size); +int32_t Api_SSL_loadCert(void *pCxt, SSL_CTX *ctx, SSL_CERT_TYPE_T type, char *name); +int32_t Api_SSL_listCert(void *pCxt, SSL_FILE_NAME_LIST *fileNames); +#endif +#endif // ENABLE_STACK_OFFLOAD +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/dset.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/dset.c new file mode 100644 index 00000000000..4175d10c704 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/dset.c @@ -0,0 +1,190 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include + +#include "dset.h" + +HOST_DSET host_dsets[MAX_DSET_SIZE]; + +HOST_DSET *dset_find(uint32_t dset_id) +{ + uint16_t i; + HOST_DSET *pDset; + + for (i = 0, pDset = host_dsets; i < MAX_DSET_SIZE; i++, pDset++) + { + if (pDset->dset_id == dset_id) + return pDset; + } + + return NULL; +} + +HOST_DSET *dset_insert(uint32_t dset_id) +{ + uint16_t i; + HOST_DSET *pDset; + + for (i = 0, pDset = host_dsets; i < MAX_DSET_SIZE; i++, pDset++) + { + if (pDset->dset_id == 0) + { + pDset->dset_id = dset_id; + if (pDset->data_ptr) + { + A_FREE(pDset->data_ptr, MALLOC_ID_CONTEXT); + pDset->data_ptr = NULL; + } + + return pDset; + } + } + + return NULL; +} + +HOST_DSET *dset_get(uint32_t dset_id, uint32_t length) +{ + unsigned char *pbuf; + + HOST_DSET *pDset; + + pDset = dset_find(dset_id); + + if (pDset == NULL) + { + pDset = dset_insert(dset_id); + if (pDset == NULL) + return pDset; + } + + /* Free the data buffer and reallocate based on new length */ + if (pDset->data_ptr) + { + A_FREE(pDset->data_ptr, MALLOC_ID_CONTEXT); + pDset->data_ptr = NULL; + } + + pbuf = (unsigned char *)A_MALLOC(length, MALLOC_ID_CONTEXT); + if (pbuf == NULL) + { + pDset->dset_id = 0; + return NULL; + } + + pDset->data_ptr = pbuf; + pDset->length = length; + + return pDset; +} + +uint32_t dset_write(HOST_DSET *pDset, uint8_t *pData, uint32_t offset, uint32_t length) +{ + uint32_t wrt_len; + + if (offset + length > pDset->length) + wrt_len = pDset->length - offset; + else + wrt_len = length; + + memcpy(pDset->data_ptr + offset, pData, wrt_len); + + return wrt_len; +} + +uint32_t dset_read(HOST_DSET *pDset, uint8_t *pData, uint32_t offset, uint32_t length) +{ + uint32_t wrt_len; + + if (offset + length > pDset->length) + wrt_len = pDset->length - offset; + else + wrt_len = length; + + memcpy(pData, pDset->data_ptr + offset, wrt_len); + + return wrt_len; +} + +uint32_t dset_fill(uint8_t *pData, uint32_t max_dset_count) +{ + uint16_t i, count = 0; + HOST_DSET *pDset; + HOST_DSET_ITEM *pItem = (HOST_DSET_ITEM *)pData; + + for (i = 0, pDset = host_dsets; i < MAX_DSET_SIZE && count < max_dset_count; i++, pDset++) + { + if (pDset->dset_id != 0) + { + pItem->dset_id = pDset->dset_id; + pItem->length = pDset->length; + pItem++; + count++; + } + } + + return count; +} + +uint16_t next_dset_ndx; + +HOST_DSET *dset_get_first(void) +{ + uint16_t i; + HOST_DSET *pDset; + + for (i = 0, pDset = host_dsets; i < MAX_DSET_SIZE; i++, pDset++) + { + if (pDset->dset_id != 0) + { + next_dset_ndx = i + 1; + return pDset; + } + } + + return NULL; +} + +HOST_DSET *dset_get_next(void) +{ + uint16_t i; + HOST_DSET *pDset; + + pDset = &host_dsets[next_dset_ndx]; + + for (i = next_dset_ndx; i < MAX_DSET_SIZE; i++, pDset++) + { + if (pDset->dset_id != 0) + { + next_dset_ndx = i + 1; + return pDset; + } + } + + return NULL; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/dset_api.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/dset_api.c new file mode 100644 index 00000000000..753b12af3c2 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/dset_api.c @@ -0,0 +1,245 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include + +#include "dset_api.h" + +HOST_DSET_HANDLE dset_handles[MAX_HOST_DSET_SIZE]; + + +//TODO: fixme. dummy fn, implemented in app +PREWEAK_CODE int32_t POSTWEAK_CODE remote_dset_op(DSET_OP op, HOST_DSET_HANDLE *pDsetHandle) +{ + return A_ERROR; +} + + +HOST_DSET_HANDLE *dset_find_handle(uint32_t dset_id) +{ + uint16_t i; + HOST_DSET_HANDLE *pDsetHandle = dset_handles; + + for (i = 0; i < MAX_HOST_DSET_SIZE; i++) + { + if (pDsetHandle->dset_id == dset_id) + return pDsetHandle; + } + return NULL; +} + +void dset_close_handle(HOST_DSET_HANDLE *pDsetHandle) +{ + pDsetHandle->dset_id = INVALID_DSET_ID; + if (pDsetHandle->data_ptr) + A_FREE(pDsetHandle->data_ptr, MALLOC_ID_TEMPORARY); +} + +HOST_DSET_HANDLE *dset_insert_handle(uint32_t dset_id, uint32_t flags, dset_callback_fn_t cb, void *cb_args) +{ + uint16_t i; + HOST_DSET_HANDLE *pDsetHandle = dset_handles; + + for (i = 0; i < MAX_HOST_DSET_SIZE; i++, pDsetHandle++) + { + if (pDsetHandle->dset_id == INVALID_DSET_ID) + { + pDsetHandle->dset_id = dset_id; + pDsetHandle->flags = flags; + pDsetHandle->cb = cb; + pDsetHandle->cb_args = cb_args; + pDsetHandle->data_ptr = NULL; + return pDsetHandle; + }; + } + return NULL; +} + +int32_t qcom_dset_create(HOST_DSET_HANDLE **pDsetHandle, + uint32_t dset_id, + uint32_t media_id, + uint32_t length, + uint32_t flags, + dset_callback_fn_t create_cb, + void *callback_arg) +{ + int32_t status; + + *pDsetHandle = dset_find_handle(dset_id); + if (*pDsetHandle != NULL) + return A_ERROR; + + *pDsetHandle = dset_insert_handle(dset_id, flags, create_cb, callback_arg); + if (*pDsetHandle == NULL) + return A_ERROR; + + (*pDsetHandle)->length = length; + (*pDsetHandle)->media_id = media_id; + + status = remote_dset_op(DSET_OP_CREATE, *pDsetHandle); + + return status; +} + +int32_t qcom_dset_open( + HOST_DSET_HANDLE **ppDsetHandle, uint32_t dset_id, uint32_t flags, dset_callback_fn_t open_cb, void *callback_arg) +{ + int32_t status; + + *ppDsetHandle = dset_find_handle(dset_id); + if (*ppDsetHandle != NULL) + return A_OK; + + *ppDsetHandle = dset_insert_handle(dset_id, flags, open_cb, callback_arg); + if (*ppDsetHandle == NULL) + return A_ERROR; + + status = remote_dset_op(DSET_OP_OPEN, *ppDsetHandle); + + return status; +} + +uint32_t qcom_dset_write(HOST_DSET_HANDLE *pDsetHandle, + uint8_t *buffer, + uint32_t length, + uint32_t offset, + uint32_t flags, + dset_callback_fn_t write_cb, + void *callback_arg) +{ +#define DSET_WRITE_HEAD_SIZE (sizeof(WMIX_DSET_OP_WRITE_PARAM_CMD) + +sizeof(WMIX_DSET_CMD_HDR) - 1) + + uint32_t status; + + pDsetHandle->offset = offset; + pDsetHandle->length = length; + pDsetHandle->flags = flags; + pDsetHandle->cb = write_cb; + pDsetHandle->cb_args = callback_arg; + + if (length + DSET_WRITE_HEAD_SIZE > MAX_DSET_BUFF_SIZE) + return 0; + + if (pDsetHandle->data_ptr == NULL) + pDsetHandle->data_ptr = A_MALLOC(MAX_DSET_BUFF_SIZE, MALLOC_ID_TEMPORARY); + + memcpy(pDsetHandle->data_ptr + DSET_WRITE_HEAD_SIZE, buffer, length); + + status = remote_dset_op(DSET_OP_WRITE, pDsetHandle); + return status; +} + +uint32_t qcom_dset_read(HOST_DSET_HANDLE *pDsetHandle, + uint8_t *buffer, + uint32_t length, + uint32_t offset, + dset_callback_fn_t read_cb, + void *callback_arg) +{ + uint32_t status; + + pDsetHandle->offset = offset; + pDsetHandle->length = length; + + pDsetHandle->cb = read_cb; + pDsetHandle->cb_args = callback_arg; + + if (length + sizeof(WMIX_DSET_OP_WRITE_PARAM_CMD) > MAX_DSET_BUFF_SIZE) + return 0; + + if (pDsetHandle->data_ptr == NULL) + pDsetHandle->data_ptr = A_MALLOC(MAX_DSET_BUFF_SIZE, MALLOC_ID_TEMPORARY); + + status = remote_dset_op(DSET_OP_READ, pDsetHandle); + memcpy(buffer, pDsetHandle->data_ptr, length); + return status; +} + +uint32_t qcom_dset_commit(HOST_DSET_HANDLE *pDsetHandle, dset_callback_fn_t commit_cb, void *callback_arg) +{ + uint32_t status; + + pDsetHandle->cb = commit_cb; + pDsetHandle->cb_args = callback_arg; + status = remote_dset_op(DSET_OP_COMMIT, pDsetHandle); + + dset_close_handle(pDsetHandle); + + return status; +} + +uint32_t qcom_dset_close(HOST_DSET_HANDLE *pDsetHandle, dset_callback_fn_t close_cb, void *callback_arg) +{ + uint32_t status; + + pDsetHandle->cb = close_cb; + pDsetHandle->cb_args = callback_arg; + + status = remote_dset_op(DSET_OP_CLOSE, pDsetHandle); + + dset_close_handle(pDsetHandle); + + return status; +} + +uint32_t qcom_dset_size(HOST_DSET_HANDLE *pDsetHandle, dset_callback_fn_t size_cb, void *callback_arg) +{ + uint32_t status; + + pDsetHandle->cb = size_cb; + pDsetHandle->cb_args = callback_arg; + + status = remote_dset_op(DSET_OP_SIZE, pDsetHandle); + return status; +} + +uint32_t qcom_dset_delete(uint32_t dset_id, uint32_t flags, dset_callback_fn_t delete_cb, void *callback_arg) +{ + uint32_t status; + HOST_DSET_HANDLE *pDsetHandle; + + pDsetHandle = dset_find_handle(dset_id); + if (pDsetHandle == NULL) + { + pDsetHandle = dset_insert_handle(dset_id, flags, delete_cb, callback_arg); + if (pDsetHandle == NULL) + return false; + } + else + { + pDsetHandle->cb = delete_cb; + pDsetHandle->cb_args = callback_arg; + pDsetHandle->dset_id = dset_id; + pDsetHandle->flags = flags; + } + + status = remote_dset_op(DSET_OP_DELETE, pDsetHandle); + return status; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/storerecall.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/storerecall.c new file mode 100644 index 00000000000..1abd739732d --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/storerecall/storerecall.c @@ -0,0 +1,264 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +A_STATUS setup_host_dset(void *handle); + +#if DRIVER_CONFIG_ENABLE_STORE_RECALL +extern const uint8_t max_performance_power_param; + +#if !ENABLE_STACK_OFFLOAD +extern int32_t power_state_for_module; +/*****************************************************************************/ +/* restore_power_state - Restores the original power state, which is changed by + * "move_power_state_to_maxperf" + * int32_t - module which request the change + * RETURNS: A_OK on success A_ERROR otherwise + *****************************************************************************/ +A_STATUS restore_power_state(void *pCxt, int32_t module) +{ + A_DRIVER_CONTEXT *pDCxt = (A_DRIVER_CONTEXT *)pCxt; + + /* Already some HIGH priority module changes state, + * so don't change the state now */ + if (!power_state_for_module || (power_state_for_module > module)) + { + return A_OK; + } + if (pDCxt->userPwrMode != max_performance_power_param) + { + if (A_OK != + wmi_cmd_start(pDCxt->pWmiCxt, &pDCxt->userPwrMode, WMI_SET_POWER_MODE_CMDID, sizeof(WMI_POWER_MODE_CMD))) + { + return A_ERROR; + } + } + + power_state_for_module = 0; + return A_OK; +} +#endif +/*****************************************************************************/ +/* Strrcl_ChipUpFinish - Utility function to complete the chip_up process. + * when WMI_READY is received from chip this function clears the chipDown + * boolean and sends the wmi store recall command to the chip so that its + * associated State can be refreshed. + * void *pCxt - the driver context. + *****************************************************************************/ +static A_STATUS Strrcl_ChipUpFinish(void *pCxt) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + WMI_STORERECALL_RECALL_CMD *pDsetInfo; + uint32_t dset_info_len; + + if (pDCxt->wmiReady == true) + { + switch (pDCxt->strrclState) + { + case STRRCL_ST_ACTIVE: + /* clear the chipDown boolean to allow outside activity to resume */ + pDCxt->chipDown = false; + + if (A_OK != STACK_INIT(pCxt)) + { + break; + } + + pDCxt->strrclState = STRRCL_ST_ACTIVE_B; + // INTENTIONAL FALL_THRU + case STRRCL_ST_ACTIVE_B: +/* send recall */ +#if 0 + pEv = (WMI_STORERECALL_STORE_EVENT*)pDCxt->strrclCxt; + + if(A_OK != wmi_storerecall_recall_cmd(pDCxt->pWmiCxt, A_LE2CPU32(pEv->length), &pEv->data[0])){ + break; //try again later this is likely because a previous wmi cmd has not finished. + } +#elifndef ENABLE_LARGE_DSET + + setup_host_dset(pCxt); + + pDsetData = pDCxt->tempStorage; + + if(A_OK != wmi_storerecall_recall_cmd(pDCxt->pWmiCxt, A_LE2CPU32(pDCxt->strrclCxtLen), pDsetData)){ + break; //try again later this is likely because a previous wmi cmd has not finished. + } +#else + setup_host_dset(pCxt); + + pDsetInfo = (WMI_STORERECALL_RECALL_CMD *)pDCxt->tempStorage; + if (pDsetInfo->length == 0) + { + dset_info_len = sizeof(WMI_STORERECALL_RECALL_CMD); + } + else + { + dset_info_len = sizeof(WMI_STORERECALL_RECALL_CMD) - sizeof(uint8_t); + dset_info_len += sizeof(WMI_STORERECALL_RECALL_DSET) * pDsetInfo->length; + } + + if (A_OK != wmi_storerecall_recall_cmd(pDCxt->pWmiCxt, dset_info_len, pDsetInfo)) + { + break; // try again later this is likely because a previous wmi cmd has not finished. + } +#endif + + pDCxt->strrclCxt = NULL; + pDCxt->strrclCxtLen = 0; + + // pDCxt->strrclState = STRRCL_ST_AWAIT_FW; + + pDCxt->strrclState = STRRCL_ST_INIT; + pDCxt->strrclBlock = false; + + /* Indicate completion to the custom layer */ + API_STORE_RECALL_EVENT(pCxt); + + /* clear this function from the driver's temporary calls */ + pDCxt->asynchRequest = NULL; + /* Since we are setting MAX_PERF before going to store-recall we need to set the state + after we wakes up */ + restore_power_state(pDCxt, 1); /* POWER_STATE_MOVED_FOR_STRRCL */ + + break; // done!! + default: + A_ASSERT(0); // should never happen +#if DRIVER_CONFIG_DISABLE_ASSERT + break; +#endif + } + } + + return A_OK; +} + +/*****************************************************************************/ +/* Strrcl_ChipUpStart - Utility function to bring bring the chip back up. Also + * sets up the driver tempFunc so that when the WMI_READY is received the + * store recall process can be completed via Strrcl_ChipUpFinish. + * void *pCxt - the driver context. + *****************************************************************************/ +static A_STATUS Strrcl_ChipUpStart(void *pCxt) +{ + A_STATUS status = A_ERROR; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + A_MDELAY(2); + /* assert pwd line */ + HW_PowerUpDown(pCxt, true); + + A_MDELAY(2); + do + { + /* reset htc_creditInit to re-process the HTC interrupt */ + pDCxt->htc_creditInit = 0; + + if ((status = Hcd_ReinitTarget(pCxt)) != A_OK) + { + break; + } + + A_MDELAY(1); + + if (A_OK != (status = Driver_BootComm(pCxt))) + { + break; + } + +#if (DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD) + if (A_OK != (status = Driver_StoreRecallFirmwareDownload(pCxt))) + { + break; + } +#endif /* DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD */ + + /* unmask the packet interrupt on-chip */ + Hcd_UnmaskInterrupts(pCxt, ATH_SPI_INTR_PKT_AVAIL); + /* when the driver receives the WMI_READY event chip_up_finish + * will complete the re-boot process and open the way for + * outside requests to resume. */ + pDCxt->asynchRequest = Strrcl_ChipUpFinish; + + } while (0); + + return status; +} + +/*****************************************************************************/ +/* Strrcl_ChipDown - Utility function to bring the chip down. Also sets + * driver booleans to prevent any unwanted activity until the chip is + * brought back up. + * void *pCxt - the driver context. + *****************************************************************************/ +static void Strrcl_ChipDown(void *pCxt) +{ + /* disable interrupt line - prevent un-expected INTs when chip powers down */ + // EnableDisableSPIIRQHwDetect(pDevice,false); + GET_DRIVER_COMMON(pCxt)->chipDown = true; + GET_DRIVER_COMMON(pCxt)->wmiReady = false; + /* assert pwd line */ + HW_PowerUpDown(pCxt, false); +} + +/*****************************************************************************/ +/* Strrcl_Recall - Implements the store-recall procedure. powers down the chip + * waits for x msec powers up the chip, reboots the chip. Called when the + * store-recall event is received from the chip indicating that it can be + * powered down for the specified timeout. + * void *pCxt - the driver context. + * uint32_t msec_sleep - number of milliseconds to wait + *****************************************************************************/ +void Strrcl_Recall(void *pCxt, uint32_t msec_sleep) +{ + /* bring down the chip */ + Strrcl_ChipDown(pCxt); + /* this will block the driver thread */ + /* FIXME: should instead implement a way to block the driver at driver_main thus + * allowing the thread to continue running in single-threaded systems.*/ + if (ath_custom_init.Custom_Delay != NULL) + { + /*It is possible that some hosts support low power modes, this would be a + good place to invoke it. Call app defined function if available*/ + ath_custom_init.Custom_Delay(msec_sleep); + } + else + A_MDELAY(msec_sleep); + + /* wake up chip */ + Strrcl_ChipUpStart(pCxt); +} + +#endif // DRIVER_CONFIG_ENABLE_STORE_RECALL diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/util/util_wifi.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/util/util_wifi.c new file mode 100644 index 00000000000..006b310a883 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/util/util_wifi.c @@ -0,0 +1,87 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include + +A_ENDPOINT_T *Util_GetEndpoint(void *pCxt, uint16_t id) +{ + /* this translation allows multiple virtual endpoints to be mapped to + * a common endpoint object. */ + if (id >= ENDPOINT_MANAGED_MAX) + { + id = ENDPOINT_MANAGED_MAX - 1; + } + return &(GET_DRIVER_COMMON(pCxt)->ep[id]); +} + +/* + * converts ieee channel number to frequency + */ +uint16_t Util_Ieee2freq(int32_t chan) +{ + if (chan == 14) + { + return (uint16_t)2484; + } + if (chan < 14) + { /* 0-13 */ + return (uint16_t)(2407 + (chan * 5)); + } + if (chan < 27) + { /* 15-26 */ + return (uint16_t)(2512 + ((chan - 15) * 20)); + } + return (uint16_t)(5000 + (chan * 5)); +} + +/* + * Converts MHz frequency to IEEE channel number. + */ +uint32_t Util_Freq2ieee(uint16_t freq) +{ + if (freq == 2484) + return (uint32_t)14; + if (freq < 2484) + return (uint32_t)((freq - 2407) / 5); + if (freq < 5000) + return (uint32_t)(15 + ((freq - 2512) / 20)); + return (uint32_t)((freq - 5000) / 5); +} + +HTC_ENDPOINT_ID +Util_AC2EndpointID(void *pCxt, uint8_t ac) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + return pDCxt->ac2EpMapping[ac]; +} + +uint8_t Util_EndpointID2AC(void *pCxt, HTC_ENDPOINT_ID ep) +{ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + return pDCxt->ep2AcMapping[ep]; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/wmi/wmi.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/wmi/wmi.c new file mode 100644 index 00000000000..dab716523b8 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/wmi/wmi.c @@ -0,0 +1,1698 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifdef WIN_MOBILE7 +#include +#endif + +#include +#include +#include +#include +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include +#include +#include +#include "wmi_host.h" +#include "a_drv.h" +#include "a_drv_api.h" +#include "atheros_wifi_api.h" +#define ATH_MODULE_NAME wmi +#include "a_debug.h" +#include "dbglog_api.h" +#include "cust_netbuf.h" +#include "custom_wlan_api.h" + +#if ENABLE_P2P_MODE +#include "p2p.h" +#endif + +#include "driver_cxt.h" +#include "dset.h" + +extern uint32_t last_driver_error; +// static uint16_t channel_no = 0; + +#define ATH_DEBUG_WMI 1 +#define ATH_DEBUG_ERR 1 + +#ifdef DEBUG_WMI_TRACE + +static ATH_DEBUG_MASK_DESCRIPTION wmi_debug_desc[] = { + {ATH_DEBUG_WMI, "General WMI Tracing"}, +}; + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(wmi, + "wmi", + "Wireless Module Interface", + ATH_DEBUG_MASK_DEFAULTS, + ATH_DEBUG_DESCRIPTION_COUNT(wmi_debug_desc), + wmi_debug_desc); + +#endif + +#ifndef REXOS +#define DBGARG __func__ +#define DBGFMT "%s() : " +#define DBG_WMI ATH_DEBUG_WMI +#define DBG_ERROR ATH_DEBUG_ERR +#define DBG_WMI2 ATH_DEBUG_WMI +#define A_DPRINTF AR_DEBUG_PRINTF +#endif + +#if ENABLE_P2P_MODE +static A_STATUS wmi_p2p_goneg_result_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); + +static A_STATUS wmi_p2p_list_peristent_network(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); + +static A_STATUS wmi_p2p_req_auth_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint32_t len); + +static A_STATUS wmi_p2p_node_list_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint32_t len); + +static A_STATUS wmi_p2p_invite_sent_result_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); +static A_STATUS wmi_p2p_prov_disc_resp_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); +static A_STATUS wmi_p2p_prov_disc_req_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); +#if 1 // KK +static A_STATUS wmi_p2p_sdpd_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); +static A_STATUS wmi_p2p_invite_req_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); +static A_STATUS wmi_p2p_invite_rcvd_result_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len); +#endif +WMI_P2P_PROV_INFO p2p_key_val; + +#endif +#if MANUFACTURING_SUPPORT +static A_STATUS wmi_test_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint32_t len); +#endif +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, int len); + +#define MODE_A_SUPPORT_RATE_START ((int32_t)4) +#define MODE_A_SUPPORT_RATE_STOP ((int32_t)11) + +#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START +#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP + +#define MODE_B_SUPPORT_RATE_START ((int32_t)0) +#define MODE_B_SUPPORT_RATE_STOP ((int32_t)3) + +#define MODE_G_SUPPORT_RATE_START ((int32_t)0) +#define MODE_G_SUPPORT_RATE_STOP ((int32_t)11) + +#define MODE_GHT20_SUPPORT_RATE_START ((int32_t)0) +#define MODE_GHT20_SUPPORT_RATE_STOP ((int32_t)19) + +#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_GHT20_SUPPORT_RATE_STOP + 1) + +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */ +const uint8_t up_to_ac[] = { + WMM_AC_BE, WMM_AC_BK, WMM_AC_BK, WMM_AC_BE, WMM_AC_VI, WMM_AC_VI, WMM_AC_VO, WMM_AC_VO, +}; + +void *wmi_init(void *devt) +{ + struct wmi_t *wmip; + + A_REGISTER_MODULE_DEBUG_INFO(wmi); + + wmip = A_MALLOC(sizeof(struct wmi_t), MALLOC_ID_CONTEXT); + if (wmip == NULL) + { + return (NULL); + } + A_MEMZERO(wmip, sizeof(*wmip)); + A_MUTEX_INIT(&wmip->wmi_lock); + wmip->wmi_devt = devt; + wmi_qos_state_init(wmip); + + return (wmip); +} + +void wmi_qos_state_init(struct wmi_t *wmip) +{ + uint8_t i; + + if (wmip == NULL) + { + return; + } + LOCK_WMI(wmip); + + /* Initialize QoS States */ + wmip->wmi_numQoSStream = 0; + + wmip->wmi_fatPipeExists = 0; + + for (i = 0; i < WMM_NUM_AC; i++) + { + wmip->wmi_streamExistsForAC[i] = 0; + } + + UNLOCK_WMI(wmip); + + A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1); +} + +void wmi_set_control_ep(struct wmi_t *wmip, HTC_ENDPOINT_ID eid) +{ + A_ASSERT(eid != ENDPOINT_UNUSED); + wmip->wmi_endpoint_id = eid; +} + +HTC_ENDPOINT_ID +wmi_get_control_ep(struct wmi_t *wmip) +{ + return (wmip->wmi_endpoint_id); +} + +void wmi_shutdown(struct wmi_t *wmip) +{ + if (wmip != NULL) + { + if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) + { + A_MUTEX_DELETE(&wmip->wmi_lock); + } + A_FREE(wmip, MALLOC_ID_CONTEXT); + } +} + +/* + * performs DIX to 802.3 encapsulation for transmit packets. + * uses passed in buffer. Returns buffer or NULL if failed. + * Assumes the entire DIX header is contigous and that there is + * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers. + */ +A_STATUS +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf) +{ + uint8_t *datap; + uint16_t typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + UNUSED_ARGUMENT(wmip); + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < (int32_t)(sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(uint16_t *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) + { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + return (A_OK); + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = (uint16_t)A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) + { + return A_NO_MEMORY; + } + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof(ATH_MAC_HDR)); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + + return (A_OK); +} + +A_STATUS +wmi_meta_add(struct wmi_t *wmip, void *osbuf, uint8_t *pVersion, void *pTxMetaS) +{ + WMI_TX_META_V3 v3In; + WMI_TX_META_V3 *pV3 = NULL; + WMI_TX_META_V5 v5In; + WMI_TX_META_V5 *pV5 = NULL; + UNUSED_ARGUMENT(wmip); + + switch (*pVersion) + { + case WMI_META_VERSION_3: + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) + { + return A_NO_MEMORY; + } + + A_MEMCPY(&v3In, pTxMetaS, sizeof(WMI_TX_META_V3)); + /* convert for any endianness */ + // no conversions for this structure + /* copy to frame */ + pV3 = (WMI_TX_META_V3 *)A_NETBUF_DATA(osbuf); + A_MEMCPY(pV3, &v3In, sizeof(WMI_TX_META_V3)); + + A_ASSERT(pVersion != NULL); + /* the version must be used to populate the meta field of the WMI_DATA_HDR */ + *pVersion = WMI_META_VERSION_3; + break; + + case WMI_META_VERSION_5: + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) + { + return A_NO_MEMORY; + } + + A_MEMCPY(&v5In, pTxMetaS, sizeof(WMI_TX_META_V5)); + /* convert for any endianness */ + // no conversions for this structure + /* copy to frame */ + pV5 = (WMI_TX_META_V5 *)A_NETBUF_DATA(osbuf); + A_MEMCPY(pV5, &v5In, sizeof(WMI_TX_META_V5)); + + A_ASSERT(pVersion != NULL); + /* the version must be used to populate the meta field of the WMI_DATA_HDR */ + *pVersion = WMI_META_VERSION_5; + break; + } + + return A_OK; +} + +/* Adds a WMI data header */ +A_STATUS +wmi_data_hdr_add(struct wmi_t *wmip, + void *osbuf, + uint8_t msgType, + boolean bMoreData, + WMI_DATA_HDR_DATA_TYPE data_type, + uint8_t metaVersion, + void *pTxMetaS) +{ + WMI_DATA_HDR *dtHdr; + // uint8_t metaVersion = 0; + A_STATUS status = A_OK; + A_ASSERT(osbuf != NULL); + + if ((status = wmi_meta_add(wmip, osbuf, &metaVersion, pTxMetaS)) != A_OK) + { + return status; + } + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) + { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + A_MEMZERO(dtHdr, sizeof(WMI_DATA_HDR)); + + WMI_DATA_HDR_SET_MSG_TYPE(dtHdr, msgType); + WMI_DATA_HDR_SET_DATA_TYPE(dtHdr, data_type); + + if (bMoreData) + { + WMI_DATA_HDR_SET_MORE_BIT(dtHdr); + } + + WMI_DATA_HDR_SET_META(dtHdr, metaVersion); + // dtHdr->rssi = 0; + // lastly convert the U16 value to LE + dtHdr->info2 = A_CPU2LE16(dtHdr->info2); + return status; +} + +/* This stuff is used when we want a simple layer-3 visibility */ +typedef PREPACK struct _iphdr +{ + uint8_t ip_ver_hdrlen FIELD_PACKED; /* version and hdr length */ + uint8_t ip_tos FIELD_PACKED; /* type of service */ + uint16_t ip_len FIELD_PACKED; /* total length */ + uint16_t ip_id FIELD_PACKED; /* identification */ + int16_t ip_off FIELD_PACKED; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + uint8_t ip_ttl FIELD_PACKED; /* time to live */ + uint8_t ip_p FIELD_PACKED; /* protocol */ + uint16_t ip_sum FIELD_PACKED; /* checksum */ + uint8_t ip_src[4] FIELD_PACKED; /* source and dest address */ + uint8_t ip_dst[4] FIELD_PACKED; +} POSTPACK iphdr; + +static uint8_t wmi_determine_userPriority(uint8_t *pkt, uint32_t layer2Pri) +{ + uint8_t ipPri; + iphdr *ipHdr = (iphdr *)pkt; + + /* Determine IPTOS priority */ + /* + * IP Tos format : + * (Refer Pg 57 WMM-test-plan-v1.2) + * IP-TOS - 8bits + * : DSCP(6-bits) ECN(2-bits) + * : DSCP - P2 P1 P0 X X X + * where (P2 P1 P0) form 802.1D + */ + ipPri = ipHdr->ip_tos >> 5; + ipPri &= 0x7; + + if ((layer2Pri & 0x7) > ipPri) + return ((uint8_t)layer2Pri & 0x7); + else + return ipPri; +} + +uint8_t wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, uint32_t layer2Priority, boolean wmmEnabled) +{ + uint8_t *datap; + uint8_t trafficClass = WMM_AC_BE; + uint16_t ipType = IP_ETHERTYPE; + WMI_DATA_HDR *dtHdr; + uint8_t userPriority; + uint32_t metasize; + ATH_LLC_SNAP_HDR *llcHdr; + + // WMI_CREATE_PSTREAM_CMD cmd; + UNUSED_ARGUMENT(wmip); + + A_ASSERT(osbuf != NULL); + + datap = A_NETBUF_DATA(osbuf); + dtHdr = (WMI_DATA_HDR *)datap; + metasize = (WMI_DATA_HDR_GET_META(dtHdr)) ? WMI_MAX_TX_META_SZ : 0; + + if (!wmmEnabled) + { + /* If WMM is disabled all traffic goes as BE traffic */ + userPriority = 0; + } + else + { + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize + sizeof(ATH_MAC_HDR)); + + if (llcHdr->etherType == A_CPU2BE16(ipType)) + { + /* Extract the endpoint info from the TOS field in the IP header */ + + userPriority = wmi_determine_userPriority(((uint8_t *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR), layer2Priority); + } + else + { + userPriority = layer2Priority & 0x7; + } + } + + trafficClass = (up_to_ac[userPriority & 0x7]); + + WMI_DATA_HDR_SET_UP(dtHdr, userPriority); + + return trafficClass; +} + +/* + * performs 802.3 to DIX encapsulation for received packets. + * Assumes the entire 802.3 header is contigous. + */ +A_STATUS +wmi_dot3_2_dix(void *osbuf) +{ + uint8_t *datap; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + macHdr.typeOrLen = llcHdr->etherType; + + if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof(ATH_MAC_HDR)); + + return (A_OK); +} + +/* + * Removes a WMI data header + */ +A_STATUS +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + UNUSED_ARGUMENT(wmip); + A_ASSERT(osbuf != NULL); + + return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR))); +} + +static A_STATUS wmi_test_ev_length(uint16_t id, int32_t len) +{ + uint16_t i; + const struct + { + uint16_t id; + uint16_t len; + } length_array[] = {{WMI_BSSINFO_EVENTID, sizeof(WMI_BSS_INFO_HDR)}, + {WMI_CONNECT_EVENTID, sizeof(WMI_CONNECT_EVENT)}, + {WMI_GET_CHANNEL_LIST_CMDID, sizeof(WMI_CHANNEL_LIST_REPLY)}, + {WMI_READY_EVENTID, sizeof(WMI_READY_EVENT)}, + {WMI_DISCONNECT_EVENTID, sizeof(WMI_DISCONNECT_EVENT)}, + {WMI_BSSINFO_EVENTID, sizeof(WMI_BSS_INFO_HDR)}, + {WMI_REGDOMAIN_EVENTID, sizeof(WMI_REG_DOMAIN_EVENT)}, + {WMI_GET_PMK_EVENTID, WMI_PMK_LEN}, + {WMI_TKIP_MICERR_EVENTID, sizeof(WMI_TKIP_MICERR_EVENT)}, + {WMI_PEER_NODE_EVENTID, sizeof(WMI_PEER_NODE_EVENT)}}; + + for (i = 0; i < sizeof(length_array) / sizeof(length_array[0]); i++) + { + if (id == length_array[i].id) + { + if (len < length_array[i].len) + { + return A_ERROR; + } + + return A_OK; + } + } + + return A_OK; // could not find entry for eventID +} + +/* + * WMI Extended Event received from Target. + */ +A_STATUS +wmi_control_rx_xtnd(struct wmi_t *wmip, uint8_t devId, void *osbuf) +{ + WMIX_CMD_HDR *cmd; + uint16_t id; + uint8_t *datap; + uint32_t len; + A_STATUS status = A_OK; + + if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) + { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) + { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + switch (id) + { + case (WMIX_DBGLOG_EVENTID): + A_WMIX_DBGLOG_EVENT(wmip, devId, datap, len); + break; + case (WMIX_GPIO_DATA_EVENTID): + A_WMIX_GPIO_DATA_EVENT(wmip, devId, datap, len); + break; + +#if ENABLE_KF_PERFORMANCE + case (WMIX_PFM_DATA_EVENTID): + A_WMIX_PFM_DATA_EVENT(wmip, devId, datap, len); + break; + case (WMIX_PFM_DATA_DONE_EVENTID): + A_WMIX_PFM_DATA_DONE_EVENT(wmip, devId, datap, len); + break; +#endif + + case (WMIX_HB_CHALLENGE_RESP_EVENTID): + WMIX_HB_CHALLENGE_RESP_RX(wmip->wmi_devt, devId, datap, len); + break; + + default: + A_DPRINTF(DBG_WMI | DBG_ERROR, (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + return status; +} + +/* + * Control Path + */ + +A_STATUS +wmi_control_rx(struct wmi_t *wmip, void *osbuf) +{ + // printf("wmi_control_rx.\n"); + WMI_CMD_HDR *cmd; + uint16_t id; + uint8_t *datap; + int32_t len; + A_STATUS status = A_OK; + uint8_t spareBuf = 0; + WMI_BSS_INFO_HDR2 bih2; + WMI_BSS_INFO_HDR *bih; + union + { + void *void_ev; // used for initialization only + WMI_CONNECT_EVENT *conn_ev; + WMI_CHANNEL_LIST_REPLY *chan_ev; + WMI_READY_EVENT *ready_ev; + WMI_DISCONNECT_EVENT *disc_ev; + WMI_REG_DOMAIN_EVENT *regdom_ev; + WMI_SCAN_COMPLETE_EVENT *scan_comp_ev; + WMI_TKIP_MICERR_EVENT *tkip_err_ev; + WMI_PEER_NODE_EVENT *peer_ev; + } stackU; + uint8_t devId; + +#define VOID_EV (stackU.void_ev) +#define CONN_EV (stackU.conn_ev) +#define CHAN_EV (stackU.chan_ev) +#define READY_EV (stackU.ready_ev) +#define DISC_EV (stackU.disc_ev) +#define REG_EV (stackU.regdom_ev) +#define SCAN_EV (stackU.scan_comp_ev) +#define TKIP_EV (stackU.tkip_err_ev) +#define PEER_EV (stackU.peer_ev) + + A_ASSERT(osbuf != NULL); + if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) + { + A_NETBUF_FREE(osbuf); + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = A_LE2CPU16(cmd->commandId); + + cmd->info1 = A_LE2CPU16(cmd->info1); + devId = WMI_GET_DEVICE_ID(cmd->info1); + + if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) + { + A_NETBUF_FREE(osbuf); + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + VOID_EV = datap; + len = (int32_t)A_NETBUF_LEN(osbuf); + + if (A_OK != wmi_test_ev_length(id, len)) + { + A_ASSERT(0); + } + + WMI_DEBUG_RX_EVENT(id, osbuf); + + switch (id) + { + case (WMI_GET_CHANNEL_LIST_CMDID): + A_WMI_CHANNELLIST_RX(wmip->wmi_devt, devId, (int8_t)CHAN_EV->numChannels, (void*)CHAN_EV->channelList); + break; + case (WMI_GET_BITRATE_CMDID): + { + A_WMI_GET_BITRATE_EVEVT(wmip->wmi_devt, devId, datap); + } + break; + case (WMI_GET_TEMPERATURE_REPLY_EVENTID): + { + A_WMI_GET_TEMPERATURE_REPLY(wmip->wmi_devt, datap, len); + }; + break; + case (WMI_GET_COUNTRY_CODE_REPLY_EVENTID): + { + // printf("wmi code reply.\n"); + A_WMI_GET_COUNTRY_CODE_REPLY(wmip->wmi_devt, datap, len); + }; + break; + case (WMI_PARAM_SET_REPLY_EVENTID): + A_WMI_SET_PARAM_REPLY(wmip->wmi_devt, datap); + break; + case (WMI_READY_EVENTID): + A_WMI_READY_EVENT(wmip->wmi_devt, devId, READY_EV->macaddr, READY_EV->phyCapability, + A_LE2CPU32(READY_EV->sw_version), A_LE2CPU32(READY_EV->abi_version)); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_CONNECT_EVENTID): + // convert for native endianness + CONN_EV->channel = A_LE2CPU16(stackU.conn_ev->channel); + CONN_EV->listenInterval = A_LE2CPU16(CONN_EV->listenInterval); + CONN_EV->beaconInterval = A_LE2CPU16(CONN_EV->beaconInterval); + CONN_EV->networkType = A_LE2CPU32(CONN_EV->networkType); + A_WMI_CONNECT_EVENT(wmip->wmi_devt, devId, CONN_EV->channel, CONN_EV->bssid, CONN_EV->listenInterval, + CONN_EV->beaconInterval, (NETWORK_TYPE)CONN_EV->networkType, CONN_EV->beaconIeLen, + CONN_EV->assocReqLen, CONN_EV->assocRespLen, CONN_EV->assocInfo); + + A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_DISCONNECT_EVENTID): + A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, devId, DISC_EV->disconnectReason, DISC_EV->bssid, + DISC_EV->assocRespLen, DISC_EV->assocInfo, + A_LE2CPU16(DISC_EV->protocolReasonStatus)); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_PEER_NODE_EVENTID): + /* this event will be sent from device to indicate 4 way success + */ + // status = wmi_rsna_4way_rx(wmip, datap, len); + if (PEER_EV->eventCode == PEER_NODE_JOIN_EVENT) + { + /* need to call an custom event which will give a callback + * to the application this event will indicate to application + * 4 way handshake success from the firmware + */ + A_WMI_RSNA_SUCCESS_EVENT(wmip->wmi_devt, devId, PEER_FIRST_NODE_JOIN_EVENT); + } + break; + case (WMI_BSSINFO_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG)); + { + /* + * convert WMI_BSS_INFO_HDR2 to WMI_BSS_INFO_HDR + * Take a local copy of the WMI_BSS_INFO_HDR2 from the wmi buffer + * and reconstruct the WMI_BSS_INFO_HDR in its place + */ + A_MEMCPY(&bih2, datap, sizeof(WMI_BSS_INFO_HDR2)); + + A_NETBUF_PUSH(osbuf, 4); + datap = A_NETBUF_DATA(osbuf); + len = (int32_t)A_NETBUF_LEN(osbuf); + bih = (WMI_BSS_INFO_HDR *)datap; + + bih->channel = A_LE2CPU16(bih2.channel); + bih->frameType = bih2.frameType; + bih->snr = bih2.snr; + bih->rssi = (int16_t)(bih2.snr - 95); + bih->ieMask = A_LE2CPU16(bih2.ieMask); + A_MEMCPY(bih->bssid, bih2.bssid, ATH_MAC_LEN); + + if (bih->rssi <= 0) + { + A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, devId, datap, len); + A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + } + } + break; + case (WMI_REGDOMAIN_EVENTID): + A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, devId, A_LE2CPU32(REG_EV->regDomain)); + break; + case (WMI_SCAN_COMPLETE_EVENTID): + A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, devId, (A_STATUS)A_LE2CPU32(SCAN_EV->status)); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_CMDERROR_EVENTID): + status = wmi_errorEvent_rx(wmip, devId, datap, len); + break; + case (WMI_REPORT_STATISTICS_EVENTID): + A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, devId, datap, (uint32_t)len); + break; + case (WMI_EXTENSION_EVENTID): + status = wmi_control_rx_xtnd(wmip, devId, osbuf); + break; + case (WMI_GET_PMK_EVENTID): + A_WMI_GET_PMK_RX(wmip->wmi_devt, devId, datap); + break; + case (WMI_STORERECALL_STORE_EVENTID): + A_WMI_STORERECALL_EVENT_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + + /* new store-recall event */ + case (WMI_STORERECALL_START_EVENTID): + A_WMI_STORERECALL_START_EVENT_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + case (WMI_HOST_DSET_STORE_EVENTID): + A_WMI_HOST_DSET_EVENT_STORE_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + case (WMI_HOST_DSET_READ_EVENTID): + A_WMI_HOST_DSET_EVENT_READ_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + case (WMI_HOST_DSET_CREATE_EVENTID): + A_WMI_HOST_DSET_EVENT_CREATE_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + case (WMI_HOST_DSET_LARGE_WRITE_EVENTID): + A_WMI_HOST_DSET_EVENT_WRITE_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + case (WMI_HOST_DSET_LARGE_READ_EVENTID): + A_WMI_HOST_DSET_EVENT_READBACK_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + case (WMI_HOST_DSET_SYNC_EVENTID): + A_WMI_HOST_DSET_EVENT_SYNC_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + case (WMI_DSET_OP_EVENTID): + A_WMI_DSET_EVENT_OP_RX(wmip->wmi_devt, devId, datap, len, osbuf); + break; + /* */ + + case (WMI_WPS_PROFILE_EVENTID): + A_WMI_WPS_PROFILE_EVENT_RX(wmip->wmi_devt, devId, datap, len, osbuf); + spareBuf = 1; /* prevent buffer from A_NETBUF_FREE() below */ + break; +#if WLAN_CONFIG_11N_AGGR_SUPPORT + case (WMI_ADDBA_REQ_EVENTID): + A_WMI_AGGR_RECV_ADDBA_REQ_EVT(wmip->wmi_devt, devId, (WMI_ADDBA_REQ_EVENT *)datap); + break; + case (WMI_DELBA_REQ_EVENTID): + A_WMI_AGGR_RECV_DELBA_REQ_EVT(wmip->wmi_devt, devId, (WMI_DELBA_EVENT *)datap); + break; +#endif + case (WMI_TKIP_MICERR_EVENTID): + A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, devId, TKIP_EV->keyid, TKIP_EV->ismcast); + break; + case (WMI_SOCKET_RESPONSE_EVENTID): + status = A_WMI_SOCK_RESPONSE_EVENT_RX(wmip->wmi_devt, devId, datap, len, osbuf); + spareBuf = 1; /* prevent buffer from A_NETBUF_FREE() below */ + break; + +#if ENABLE_P2P_MODE + case WMI_P2P_LIST_PERSISTENT_NETWORK_EVENTID: + status = wmi_p2p_list_peristent_network(wmip, devId, datap, len); + break; + case WMI_P2P_GO_NEG_RESULT_EVENTID: + status = wmi_p2p_goneg_result_event_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_NODE_LIST_EVENTID: + status = wmi_p2p_node_list_event_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_REQ_TO_AUTH_EVENTID: + status = wmi_p2p_req_auth_event_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_PROV_DISC_RESP_EVENTID: + status = wmi_p2p_prov_disc_resp_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_PROV_DISC_REQ_EVENTID: + status = wmi_p2p_prov_disc_req_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_INVITE_REQ_EVENTID: + status = wmi_p2p_invite_req_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_INVITE_RCVD_RESULT_EVENTID: + status = wmi_p2p_invite_rcvd_result_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_INVITE_SENT_RESULT_EVENTID: + status = wmi_p2p_invite_sent_result_rx(wmip, devId, datap, len); + break; + + case WMI_P2P_SDPD_RX_EVENTID: + status = wmi_p2p_sdpd_event_rx(wmip, devId, datap, len); + break; + +#endif +#if MANUFACTURING_SUPPORT + case WMI_TEST_EVENTID: + status = wmi_test_event_rx(wmip, devId, datap, len); + break; +#endif + case WMI_RX_PROBE_REQ_EVENTID: + A_WMI_PROBE_REQ_EVENT_RX(wmip->wmi_devt, datap, len); + break; + + case WMI_WLAN_WPS_INIT_KEY_EVENTID: + A_WMI_WLAN_WPS_INIT_REPLY_RX(wmip->wmi_devt, datap, len); + break; + + default: + if (A_OK != (status = A_WMI_EVENT(id, wmip->wmi_devt, datap, len, osbuf))) + { + A_DPRINTF(DBG_WMI | DBG_ERROR, (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + } + break; + } + /* spareBuf != 0 if the packet handler needed to keep the buffer. + * it becomes the handler's responsibility to free it. + */ + if (spareBuf == 0) + { + A_NETBUF_FREE(osbuf); + } + + return status; +} + +/* + * Target is reporting a programming error. This is for + * developer aid only. Target only checks a few common violations + * and it is responsibility of host to do all error checking. + * Behavior of target after wmi error event is undefined. + * A reset is recommended. + */ +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, int len) +{ + WMI_CMD_ERROR_EVENT *ev; + UNUSED_ARGUMENT(wmip); + UNUSED_ARGUMENT(len); + UNUSED_ARGUMENT(devId); + ev = (WMI_CMD_ERROR_EVENT *)datap; + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId)); + switch (ev->errorCode) + { + case (INVALID_PARAM): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n")); + break; + case (ILLEGAL_STATE): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n")); + break; + case (INTERNAL_ERROR): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n")); + break; + case (STACK_ERROR): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("TCP/IP stack not present on Target\n")); + A_ASSERT(0); + } + + return A_OK; +} + +/* + * Called to send a wmi command. Command specific data is already built + * on osbuf and current osbuf->data points to it. + */ +A_STATUS +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, WMI_SYNC_FLAG syncflag) +{ + A_STATUS status = A_OK; + WMI_CMD_HDR *cHdr; + HTC_ENDPOINT_ID eid = wmip->wmi_endpoint_id; + + A_ASSERT(osbuf != NULL); + + if (syncflag >= END_WMIFLAG) + { + A_NETBUF_FREE(osbuf); + return A_EINVAL; + } + + WMI_DEBUG_TX_COMMAND(cmdId, osbuf); + +#if 0 + WMI_SOCKET_CMD *cmd; + cmd = (WMI_SOCKET_CMD *)A_NETBUF_DATA(osbuf); + printf("cmd type is %d.\n",cmd->cmd_type); +#endif + +#if WLAN_CONFIG_ENABLE_WMI_SYNC + if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) + { + /* + * We want to make sure all data currently queued is transmitted before + * the cmd execution. Establish a new sync point. + */ + wmi_sync_point(wmip); + } +#endif + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) + { + A_NETBUF_FREE(osbuf); + return A_NO_MEMORY; + } + + cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = A_CPU2LE16((uint16_t)cmdId); + + WMI_SET_DEVICE_ID(cHdr, wmip->deviceid); + cHdr->info1 = A_CPU2LE16(cHdr->info1); // added for virtual interface + + A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid); + +#if WLAN_CONFIG_ENABLE_WMI_SYNC + if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) + { + /* + * We want to make sure all new data queued waits for the command to + * execute. Establish a new sync point. + */ + wmi_sync_point(wmip); + } +#endif + + return (status); +} + +#if ENABLE_AP_MODE +A_STATUS +wmi_ap_set_param(struct wmi_t *wmip, void *data) +{ + ATH_AP_PARAM_STRUCT *ap_param = (ATH_AP_PARAM_STRUCT *)data; + union + { + uint8_t hidden_ssid_flag; + WMI_AP_CONN_INACT_CMD conn_inact_cmd; + WMI_BEACON_INT_CMD beacon_int_cmd; + WMI_AP_SET_DTIM_CMD set_dtim_cmd; + WMI_AP_PSBUF_OFFLOAD_CMD psbuf_offload_cmd; + } stackU; + + switch (ap_param->cmd_subset) + { + case AP_SUB_CMD_HIDDEN_FLAG: + { + stackU.hidden_ssid_flag = HIDDEN_SSID_TRUE; + return (wmi_cmd_start(wmip, &stackU.hidden_ssid_flag, WMI_AP_HIDDEN_SSID_CMDID, + sizeof(WMI_AP_HIDDEN_SSID_CMD))); + } + + case AP_SUB_CMD_INACT_TIME: + { + A_MEMZERO(&stackU.conn_inact_cmd, sizeof(WMI_AP_CONN_INACT_CMD)); + stackU.conn_inact_cmd.period = A_CPU2LE32(*(uint32_t *)(ap_param->data)); + return ( + wmi_cmd_start(wmip, &stackU.conn_inact_cmd, WMI_AP_CONN_INACT_CMDID, sizeof(WMI_AP_CONN_INACT_CMD))); + } + + case AP_SUB_CMD_BCON_INT: + { + A_MEMZERO(&stackU.beacon_int_cmd, sizeof(WMI_BEACON_INT_CMD)); + stackU.beacon_int_cmd.beaconInterval = A_CPU2LE16((*(uint16_t *)(ap_param->data))); + return (wmi_cmd_start(wmip, &stackU.conn_inact_cmd, WMI_SET_BEACON_INT_CMDID, sizeof(WMI_BEACON_INT_CMD))); + } + + case AP_SUB_CMD_DTIM_INT: + { + A_MEMZERO(&stackU.set_dtim_cmd, sizeof(WMI_AP_SET_DTIM_CMD)); + stackU.set_dtim_cmd.dtim = *(uint8_t *)(ap_param->data); + return (wmi_cmd_start(wmip, &stackU.conn_inact_cmd, WMI_AP_SET_DTIM_CMDID, sizeof(WMI_AP_SET_DTIM_CMD))); + } + case AP_SUB_CMD_PSBUF: + { + A_MEMZERO(&stackU.psbuf_offload_cmd, sizeof(WMI_AP_PSBUF_OFFLOAD_CMD)); + stackU.psbuf_offload_cmd.enable = ((uint8_t *)ap_param->data)[0]; + stackU.psbuf_offload_cmd.psBufCount = ((uint8_t *)ap_param->data)[1]; + return (wmi_cmd_start(wmip, &stackU.conn_inact_cmd, WMI_AP_PSBUF_OFFLOAD_CMDID, + sizeof(WMI_AP_PSBUF_OFFLOAD_CMD))); + } + default: + break; + } + + return A_OK; +} +#endif + +#if WLAN_CONFIG_ENABLE_WMI_SYNC + +A_STATUS +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT(eid != wmip->wmi_endpoint_id); + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) + { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid)); + + return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid)); +} + +typedef struct _WMI_DATA_SYNC_BUFS +{ + uint8_t trafficClass; + void *osbuf; +} WMI_DATA_SYNC_BUFS; + +static A_STATUS wmi_sync_point(struct wmi_t *wmip) +{ + void *cmd_osbuf; + WMI_SYNC_CMD *cmd; + WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC]; + uint8_t i, numPriStreams = 0; + A_STATUS status = A_OK; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + memset(dataSyncBufs, 0, sizeof(dataSyncBufs)); + + /* lock out while we walk through the priority list and assemble our local array */ + LOCK_WMI(wmip); + + for (i = 0; i < WMM_NUM_AC; i++) + { + if (wmip->wmi_fatPipeExists & (1 << i)) + { + numPriStreams++; + dataSyncBufs[numPriStreams - 1].trafficClass = i; + } + } + + UNLOCK_WMI(wmip); + + /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */ + + do + { + /* + * We allocate all network buffers needed so we will be able to + * send all required frames. + */ + cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (cmd_osbuf == NULL) + { + status = A_NO_MEMORY; + break; + } + + A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd)); + + cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + /* In the SYNC cmd sent on the control Ep, send a bitmap of the data + * eps on which the Data Sync will be sent + */ + cmd->dataSyncMap = wmip->wmi_fatPipeExists; + + for (i = 0; i < numPriStreams; i++) + { + dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0); + if (dataSyncBufs[i].osbuf == NULL) + { + status = A_NO_MEMORY; + break; + } + } // end for + + /* if Buffer allocation for any of the dataSync fails, then do not + * send the Synchronize cmd on the control ep + */ + if (A_FAILED(status)) + { + break; + } + + /* + * Send sync cmd followed by sync data messages on all endpoints being + * used + */ + status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID, NO_SYNC_WMIFLAG); + + if (A_FAILED(status)) + { + break; + } + /* cmd buffer sent, we no longer own it */ + cmd_osbuf = NULL; + + for (i = 0; i < numPriStreams; i++) + { + A_ASSERT(dataSyncBufs[i].osbuf != NULL); + status = wmi_dataSync_send(wmip, dataSyncBufs[i].osbuf, + A_WMI_Ac2EndpointID(wmip->wmi_devt, dataSyncBufs[i].trafficClass)); + + if (A_FAILED(status)) + { + break; + } + /* we don't own this buffer anymore, NULL it out of the array so it + * won't get cleaned up */ + dataSyncBufs[i].osbuf = NULL; + } // end for + + } while (false); + + /* free up any resources left over (possibly due to an error) */ + + if (cmd_osbuf != NULL) + { + A_NETBUF_FREE(cmd_osbuf); + } + + for (i = 0; i < numPriStreams; i++) + { + if (dataSyncBufs[i].osbuf != NULL) + { + A_NETBUF_FREE(dataSyncBufs[i].osbuf); + } + } + + return (status); +} +#endif /* WLAN_CONFIG_ENABLE_WMI_SYNC */ + +A_STATUS +wmi_storerecall_recall_cmd(struct wmi_t *wmip, uint32_t length, void *pData) +{ + void *osbuf; + WMI_STORERECALL_RECALL_CMD *p; + uint32_t msgLength = sizeof(WMI_STORERECALL_RECALL_CMD) - sizeof(uint8_t); + + osbuf = A_NETBUF_ALLOC((int32_t)msgLength); + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, (int32_t)msgLength); + + p = (WMI_STORERECALL_RECALL_CMD *)(A_NETBUF_DATA(osbuf)); + + p->length = A_CPU2LE32(length); + // A_MEMCPY(&p->data[0], pData, length); + /* here we append the payload to the msg rather than copy it. this is a + * memory and CPU optimization as the payload can be very large. + */ + A_NETBUF_APPEND_FRAGMENT(osbuf, pData, length); + + return (wmi_cmd_send(wmip, osbuf, WMI_STORERECALL_RECALL_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bssfilter_cmd(struct wmi_t *wmip, uint8_t filter, uint32_t ieMask) +{ + WMI_BSS_FILTER_CMD bssFilterParam = {0}; + + bssFilterParam.bssFilter = filter; + bssFilterParam.ieMask = A_CPU2LE32(ieMask); + + return wmi_cmd_start(wmip, &bssFilterParam, WMI_SET_BSS_FILTER_CMDID, sizeof(bssFilterParam)); +} + +#if ENABLE_STACK_OFFLOAD +A_STATUS wmi_socket_cmd(struct wmi_t *wmip, uint32_t cmd_type, void *pData, uint32_t length) +{ + WMI_SOCKET_CMD *cmd; + + if (pData == NULL || length < sizeof(WMI_SOCKET_CMD)) + { + // Should not happen + A_ASSERT(0); + } + + cmd = (WMI_SOCKET_CMD *)pData; + cmd->cmd_type = A_CPU2LE32(cmd_type); + cmd->length = A_CPU2LE32((length - sizeof(WMI_SOCKET_CMD))); + + return (wmi_cmd_start(wmip, pData, WMI_SOCKET_CMDID, length)); +} +#endif + +#if MANUFACTURING_SUPPORT +static A_STATUS wmi_test_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint32_t len) +{ + UNUSED_ARGUMENT(devId); + A_WMI_TEST_CMD_EVENT_RX(wmip->wmi_devt, devId, datap, len); + return A_OK; +} +#endif + +#if ENABLE_P2P_MODE + +static A_STATUS wmi_p2p_goneg_result_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + // A_WMI_P2P_GO_NEG_EVENT(wmip->wmi_devt, datap, len); + A_WMI_P2P_GO_NEG_EVENT(wmip->wmi_devt, devId, datap, len, &p2p_key_val); + return A_OK; +} + +static A_STATUS wmi_p2p_list_peristent_network(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + A_WMI_P2P_PERSISTENT_LIST_NETWORK_EVENT(wmip->wmi_devt, devId, datap, len); + return A_OK; +} + +static A_STATUS wmi_p2p_req_auth_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint32_t len) +{ + A_WMI_P2P_REQ_AUTH_EVENT(wmip->wmi_devt, devId, datap, len); + return A_OK; +} + +static A_STATUS wmi_p2p_node_list_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint32_t len) +{ + A_WMI_P2P_NODE_LIST_EVENT(wmip->wmi_devt, devId, datap, len); + return A_OK; +} + +static A_STATUS wmi_p2p_prov_disc_resp_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + A_WMI_GET_P2P_CTX(wmip->wmi_devt, devId, datap, len); + return A_OK; +} + +static A_STATUS wmi_p2p_prov_disc_req_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + A_WMI_P2P_PROV_DISC_REQ(wmip->wmi_devt, devId, datap, len); + return A_OK; +} +#if 1 // KK +static A_STATUS wmi_p2p_sdpd_event_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + A_WMI_P2P_SERV_DISC_REQ(wmip->wmi_devt, devId, datap, len); + return A_OK; +} + +static A_STATUS wmi_p2p_invite_req_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + A_WMI_P2P_INVITE_REQ_RX(wmip->wmi_devt, devId, datap, len); + return A_OK; +} + +static A_STATUS wmi_p2p_invite_rcvd_result_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + A_WMI_P2P_INVITE_RCVD_RESULT_EVENT(wmip->wmi_devt, devId, datap, len); + return A_OK; +} +#endif + +static A_STATUS wmi_p2p_invite_sent_result_rx(struct wmi_t *wmip, uint8_t devId, uint8_t *datap, uint8_t len) +{ + A_WMI_P2P_INVITE_SENT_RESULT_EVENT(wmip->wmi_devt, devId, datap, len); + return A_OK; +} + +A_STATUS wmi_sdpd_send_cmd(struct wmi_t *wmip, WMI_P2P_SDPD_TX_CMD *buf) +{ + void *osbuf; + WMI_P2P_SDPD_TX_CMD *sdpd_tx_cmd; + A_STATUS status; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_P2P_SDPD_TX_CMD)); + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_P2P_SDPD_TX_CMD)); + + sdpd_tx_cmd = (WMI_P2P_SDPD_TX_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(sdpd_tx_cmd, sizeof(WMI_P2P_SDPD_TX_CMD)); + A_MEMCPY(sdpd_tx_cmd, buf, sizeof(WMI_P2P_SDPD_TX_CMD)); + sdpd_tx_cmd->freq = A_CPU2LE16(sdpd_tx_cmd->freq); + sdpd_tx_cmd->status_code = A_CPU2LE16(sdpd_tx_cmd->status_code); + sdpd_tx_cmd->comeback_delay = A_CPU2LE16(sdpd_tx_cmd->comeback_delay); + sdpd_tx_cmd->tlv_length = A_CPU2LE16(sdpd_tx_cmd->tlv_length); + sdpd_tx_cmd->update_indic = A_CPU2LE16(sdpd_tx_cmd->update_indic); + sdpd_tx_cmd->total_length = A_CPU2LE16(sdpd_tx_cmd->total_length); + + status = wmi_cmd_send(wmip, osbuf, WMI_P2P_SDPD_TX_CMDID, NO_SYNC_WMIFLAG); + + if (status != A_OK) + { + A_NETBUF_FREE(osbuf); + } + + return status; +} + +A_STATUS +wmi_p2p_set_oppps(struct wmi_t *wmip, WMI_OPPPS_INFO_STRUCT *pOpp) +{ + WMI_OPPPS_INFO_STRUCT *cmd; + void *osbuf; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_OPPPS_INFO_STRUCT)); + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_OPPPS_INFO_STRUCT)); + cmd = (WMI_OPPPS_INFO_STRUCT *)(A_NETBUF_DATA(osbuf)); + + cmd->enable = pOpp->enable; + cmd->ctwin = pOpp->ctwin; + + return (wmi_cmd_send(wmip, osbuf, WMI_P2P_FW_SET_OPPPS_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS wmi_p2p_set_noa(struct wmi_t *wmip, WMI_NOA_INFO_STRUCT *noa) +{ + void *osbuf; + WMI_NOA_INFO_STRUCT *p2p_set_noa_cmd; + int i; + A_STATUS status; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_NOA_INFO_STRUCT) - 1 + noa->count * sizeof(P2P_NOA_DESCRIPTOR)); + if (osbuf == NULL) + { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_NOA_INFO_STRUCT) - 1 + noa->count * sizeof(P2P_NOA_DESCRIPTOR)); + + p2p_set_noa_cmd = (WMI_NOA_INFO_STRUCT *)(A_NETBUF_DATA(osbuf)); + + p2p_set_noa_cmd->enable = noa->enable; + p2p_set_noa_cmd->count = noa->count; + + for (i = 0; i < p2p_set_noa_cmd->count; i++) + { + A_MEMCPY(((P2P_NOA_DESCRIPTOR *)p2p_set_noa_cmd->noas) + i, ((P2P_NOA_DESCRIPTOR *)noa->noas) + i, + sizeof(P2P_NOA_DESCRIPTOR)); + } + + status = wmi_cmd_send(wmip, osbuf, WMI_P2P_FW_SET_NOA_CMDID, NO_SYNC_WMIFLAG); + + if (status != A_OK) + { + A_NETBUF_FREE(osbuf); + } + + return status; +} + +void wmi_save_key_info(WMI_P2P_PROV_INFO *p2p_info) +{ + A_MEMCPY(&p2p_key_val, p2p_info, sizeof(WMI_P2P_PROV_INFO)); +} + +#endif + +A_STATUS +wmi_cmd_start(struct wmi_t *wmip, const void *pInput, WMI_COMMAND_ID cmdID, uint16_t buffSize) +{ + A_STATUS status = A_ERROR; + void *osbuf; + + do + { + /* allocate a buffer for communication to the wifi device */ + if (NULL == (osbuf = A_NETBUF_ALLOC(buffSize))) + { + status = A_NO_MEMORY; + break; + } + + if (buffSize) + { + /* reserve the necessary space in the buffer */ + A_NETBUF_PUT(osbuf, buffSize); + A_MEMCPY(A_NETBUF_DATA(osbuf), pInput, buffSize); + } + /* send the buffer to the wifi device */ + if (A_OK != (status = wmi_cmd_send(wmip, osbuf, cmdID, NO_SYNC_WMIFLAG))) + { + // No need to free the buffer. wmi_cmd_send is freeing the + // buffer in case of error (the error condition is very rare). + // Hence commenting this out. + // A_NETBUF_FREE(osbuf); //wmi_cmd_send is freeing the buffer + } + } while (0); + + return status; +} + +#if defined(DRIVER_CONFIG_IMPLEMENT_RX_FREE_MULTIPLE_QUEUE) + +uint8_t reverse_credits_init = 0; + +A_STATUS wmi_reverse_credit_cmd(void *handle, boolean enable, uint8_t *endpoints, uint8_t *credits) +{ + A_STATUS status = A_ERROR; + uint8_t i; + + WMI_INIT_REVERSE_CREDIT_CMD reverse_credits; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(handle); + + for (i = 0; i < 8; i++) + { + if (endpoints[i] == 0) + break; + } + + reverse_credits.num_credit_queues = i; + reverse_credits.max_queued_buffers = 64; /// GET_TOTAL_BUFFERS(); + + memcpy(reverse_credits.endpoint_mapping, endpoints, sizeof(reverse_credits.endpoint_mapping)); + memcpy(reverse_credits.start_credits_per_queue, credits, sizeof(reverse_credits.start_credits_per_queue)); + + do + { + status = wmi_cmd_start(pDCxt->pWmiCxt, &reverse_credits, WMI_SET_CREDIT_REVERSE_CMDID, + sizeof(WMI_INIT_REVERSE_CREDIT_CMD)); + + if (status == A_OK) + { + break; + } + else if (status == A_NO_MEMORY) + { + pDCxt->tx_complete_pend = true; + + if (A_OK != DRIVER_WAIT_FOR_CONDITION(p_Global_Cxt, &(pDCxt->tx_complete_pend), false, 5000)) + { + A_ASSERT(0); + } + } + else + { + A_ASSERT(0); + } + } while (1); + + Driver_WakeDriver(p_Global_Cxt); + A_MDELAY(10); + + reverse_credits_init = 1; +} + +#define CLASS_HEAD_LEN(a) (sizeof((a)->offset) + sizeof((a)->shift) + sizeof((a)->mask) + sizeof((a)->count)) +#define CLASS_MAPPING_LEN(n) (sizeof(uint32_t) * n + n) + +A_STATUS wmi_rcv_data_classifier_cmd(void *handle, + uint8_t offset, + uint8_t shift, + uint32_t mask, + uint8_t count, + uint32_t *category_mapping, + uint8_t *ep_mapping) +{ + A_STATUS status = A_ERROR; + WMI_INIT_RCV_DATA_CLASSIFIER_CMD DataCls; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(handle); + uint16_t len; + + if (count > 8) + return status; +#if 0 + len = CLASS_HEAD_LEN(pDataCls) + CLASS_MAPPING_LEN(count); + pDataCls = (WMI_INIT_RCV_DATA_CLASSIFIER_CMD *)A_MALLOC(len, MALLOC_ID_TEMPORARY); + if (pDataCls == NULL) + return status; +#endif + + DataCls.offset = offset; + DataCls.shift = shift; + DataCls.mask = mask; + DataCls.count = count; + + memcpy(DataCls.category_mapping_data, category_mapping, sizeof(uint32_t) * count); + memcpy(DataCls.ep_mapping_data, ep_mapping, count); + + do + { + status = wmi_cmd_start(pDCxt->pWmiCxt, &DataCls, WMI_SET_RCV_DATA_CLASSIFIER_CMDID, + sizeof(WMI_INIT_RCV_DATA_CLASSIFIER_CMD)); + + if (status == A_OK) + { + break; + } + else if (status == A_NO_MEMORY) + { + pDCxt->tx_complete_pend = true; + + if (A_OK != DRIVER_WAIT_FOR_CONDITION(p_Global_Cxt, &(pDCxt->tx_complete_pend), false, 5000)) + { + A_ASSERT(0); + } + } + else + { + A_ASSERT(0); + } + } while (1); + +#if 0 + A_FREE(pDataCls, MALLOC_ID_TEMPORARY); +#endif + + return status; +} + +A_STATUS wmi_update_reverse_credits_cmd(void *handle, uint8_t endpoint, uint32_t nCredits) +{ + A_STATUS status = A_ERROR; + + return status; +} +#endif + +#ifndef ENABLE_LARGE_DSET +A_STATUS wmi_dset_host_cfg_cmd(void *handle) +{ + A_STATUS status = A_ERROR; + uint8_t i; + + WMI_DSET_HOST_CFG_CMD dset; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(handle); + + dset.length = 1; + + dset.dset[0].dset_id = 0x0901; + // dset.dset[0].dset_id = 0x0902; + dset.dset[0].len = 2048; + dset.dset[0].offset = 0; + + do + { + status = wmi_cmd_start(pDCxt->pWmiCxt, &dset, WMI_DSET_HOST_CFG_CMDID, sizeof(WMI_DSET_HOST_CFG_CMD)); + + if (status == A_OK) + { + break; + } + else if (status == A_NO_MEMORY) + { + pDCxt->tx_complete_pend = true; + + if (A_OK != DRIVER_WAIT_FOR_CONDITION(p_Global_Cxt, &(pDCxt->tx_complete_pend), false, 5000)) + { + A_ASSERT(0); + } + } + else + { + A_ASSERT(0); + } + } while (1); + + Driver_WakeDriver(p_Global_Cxt); + A_MDELAY(10); +} + +#else + +A_STATUS wmi_dset_host_cfg_cmd(void *handle) +{ + HOST_DSET *pDset; + WMI_STORERECALL_RECALL_CMD *pStrrclCmd; + WMI_STORERECALL_RECALL_DSET *pDsetInfo; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(handle); + + pStrrclCmd = (WMI_STORERECALL_RECALL_CMD *)pDCxt->tempStorage; + pStrrclCmd->length = 0; + + pDsetInfo = (WMI_STORERECALL_RECALL_DSET *)pStrrclCmd->data; + + pDset = dset_get_first(); + + while (pDset != NULL) + { + if (IS_STRRCL_DSET(pDset->dset_id)) + { + pDsetInfo->dset_id = pDset->dset_id; + pDsetInfo->length = pDset->length; + + pStrrclCmd->length++; + pDsetInfo++; + } + pDset = dset_get_next(); + } + + return A_OK; +} +#endif + +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, void *data) +{ + ATH_APPIE_PARAM *appie_param = (ATH_APPIE_PARAM *)data; + void *osbuf = NULL; + WMI_SET_APPIE_CMD *set_appie_cmd; + A_STATUS status; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_APPIE_CMD) + appie_param->ieLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_SET_APPIE_CMD) + appie_param->ieLen); + + set_appie_cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf)); + set_appie_cmd->mgmtFrmType = appie_param->mgmtFrmType; + set_appie_cmd->ieLen = appie_param->ieLen; + + A_MEMCPY(set_appie_cmd->ieInfo, appie_param->ieInfo, appie_param->ieLen); + status = wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG); + + if (status != A_OK) { + A_NETBUF_FREE(osbuf); + } + + return status; +} + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/wmi/wmi_host.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/wmi/wmi_host.h new file mode 100644 index 00000000000..9e07b9c8c42 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/common_src/wmi/wmi_host.h @@ -0,0 +1,73 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _WMI_HOST_H_ +#define _WMI_HOST_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +struct wmi_stats +{ + uint32_t cmd_len_err; + uint32_t cmd_id_err; +}; + +#define BEACON_PERIOD_IE_INDEX 8 +#define CAPS_IE_INDEX 10 +#define IE_INDEX 12 + +/* + * These constants are used with A_WLAN_BAND_SET. + */ +#define A_BAND_24GHZ 0 +#define A_BAND_5GHZ 1 +#define A_NUM_BANDS 2 + +struct wmi_t +{ + boolean wmi_numQoSStream; + uint16_t wmi_streamExistsForAC[WMM_NUM_AC]; + uint8_t wmi_fatPipeExists; + void *wmi_devt; + struct wmi_stats wmi_stats; + A_MUTEX_T wmi_lock; + HTC_ENDPOINT_ID wmi_endpoint_id; + void *persistentProfile; + uint16_t deviceid; +#if ENABLE_P2P_MODE + // WMI_P2P_PERSISTENT_PROFILE_CMD persistentNode; + WMI_SET_PASSPHRASE_CMD apPassPhrase; +#endif +}; + +#define LOCK_WMI(w) A_MUTEX_ACQUIRE(&(w)->wmi_lock); +#define UNLOCK_WMI(w) A_MUTEX_RELEASE(&(w)->wmi_lock); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_HOST_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_init.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_init.c new file mode 100644 index 00000000000..cb4b1815c09 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_init.c @@ -0,0 +1,302 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "wifi_common.h" + +#include +#include +#include +#include +#include +#include +#include + +// This is A_CUSTOM_DRIVER_CONTEXT, the top-level driver context. +// It contains pCommonCxt which points to the internal (aka "common") +// driver context (of type A_DRIVER_CONTEXT) +void *p_Global_Cxt = NULL; + +/*The following pointers store the custom driver context used by QAPIs*/ +// The pointers are of type QCA_CONTEXT_STRUCT_PTR +// and first entry is initialized by Custom_Api_Initialize(QCA_CONTEXT_STRUCT_PTR qca_ptr) +// (near the bottom) while the second is initialized in same function near the top +// Custom_Api_Initialize() also initializes p_Global_Cxt->pUpperCxt[] which +// is the exact same array as this one! +void *p_Driver_Cxt[2]; + +static uint32_t Custom_Api_Readmii(struct qca_context_struct *p_ctxt, uint32_t val, uint32_t *p_val, uint32_t val2); +static uint32_t Custom_Api_Writemii(struct qca_context_struct *p_ctxt, uint32_t val1, uint32_t val2, uint32_t val3); + +static uint32_t Custom_Api_Join(struct qca_context_struct *p_ctxt, struct qca_mcb_struct *p_mcb); +static uint32_t Custom_Api_Rejoin(struct qca_context_struct *p_ctxt); +static uint32_t Custom_Api_Initialize(QCA_CONTEXT_STRUCT_PTR qca_ptr); +static uint32_t Custom_Api_Shutdown(struct qca_context_struct *qca_ptr); +extern uint32_t Custom_Api_Send( + QCA_CONTEXT_STRUCT_PTR qca_ptr, PCB_PTR pcb_ptr, uint32_t size, uint32_t frags, uint32_t flags); +extern uint32_t Custom_Api_Mediactl(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t command_id, void *inout_param); + +uint32_t chip_state_ctrl(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t state); + +const QCA_MAC_IF_STRUCT ATHEROS_WIFI_IF = {Custom_Api_Initialize, Custom_Api_Shutdown, Custom_Api_Send, + Custom_Api_Readmii, Custom_Api_Writemii, Custom_Api_Join, + Custom_Api_Rejoin, Custom_Api_Mediactl}; + +static uint32_t Custom_Api_Readmii(struct qca_context_struct *p_ctxt, uint32_t val, uint32_t *p_val, uint32_t val2) +{ + /* NOTHING TO DO HERE */ + UNUSED_ARGUMENT(p_ctxt); + UNUSED_ARGUMENT(val); + UNUSED_ARGUMENT(p_val); + UNUSED_ARGUMENT(val2); + + return 0; +} + +static uint32_t Custom_Api_Writemii(struct qca_context_struct *p_ctxt, uint32_t val1, uint32_t val2, uint32_t val3) +{ + /* NOTHING TO DO HERE */ + UNUSED_ARGUMENT(p_ctxt); + UNUSED_ARGUMENT(val1); + UNUSED_ARGUMENT(val2); + UNUSED_ARGUMENT(val3); + + return 0; +} + +static uint32_t Custom_Api_Join(struct qca_context_struct *p_ctxt, struct qca_mcb_struct *p_mcb) +{ + /* NOTHING TO DO HERE */ + UNUSED_ARGUMENT(p_ctxt); + UNUSED_ARGUMENT(p_mcb); + + return 0; +} + +static uint32_t Custom_Api_Rejoin(struct qca_context_struct *p_ctxt) +{ + /* NOTHING TO DO HERE */ + UNUSED_ARGUMENT(p_ctxt); + + return 0; +} + +uint32_t chip_state_ctrl(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t state) +{ + uint32_t error = QCA_OK; + + if (state == 0) + { + /* confirm that the driver is not already down */ + if (qca_ptr->MAC_CONTEXT_PTR != NULL) + { + /* shutdown chip and driver */ + error = Custom_Api_Shutdown(qca_ptr); + } + } + else + { + /* confirm that the driver is not already up */ + if (qca_ptr->MAC_CONTEXT_PTR == NULL) + { + /* bring up chip and driver */ + error = Custom_Api_Initialize(qca_ptr); + } + } + + return error; +} + +/*****************************************************************************/ +/* Custom_Api_Initialize - Entry point for MQX to initialize the Driver. + * QCA_CONTEXT_STRUCT_PTR qca_ptr - pointer to MQX ethernet object. + * RETURNS: QCA_OK on success or QCA_ERROR otherwise. + *****************************************************************************/ +static uint32_t Custom_Api_Initialize(QCA_CONTEXT_STRUCT_PTR qca_ptr) +{ + uint32_t error = QCA_OK; + + /* If it is the second device which is getting initialised, + * Fill the pointers and generate the MAC address from the + * first device + */ + if (p_Global_Cxt) + { + QCA_CONTEXT_STRUCT_PTR tempqca_ptr = (QCA_CONTEXT_STRUCT_PTR)GET_DRIVER_CXT(p_Global_Cxt)->pUpperCxt[0]; + uint8_t devId; + + devId = qca_ptr->PARAM_PTR->QCA_IF->PHY_NUMBER; + if (devId >= WLAN_NUM_OF_DEVICES) { + return QCA_ERROR; + } + /* Generating the MAC Address of the second interface using the first interface MAC */ + A_MEMCPY(qca_ptr->ADDRESS, tempqca_ptr->ADDRESS, ATH_MAC_LEN); + qca_ptr->ADDRESS[0] = (((qca_ptr->ADDRESS[0]) ^ (1 << devId)) | 0x2); + // qca_ptr->ADDRESS[0] = ((qca_ptr->ADDRESS[0])+ (devId << 4)) | 0x2; + + qca_ptr->MAC_CONTEXT_PTR = p_Global_Cxt; + GET_DRIVER_CXT(p_Global_Cxt)->pUpperCxt[devId] = qca_ptr; + p_Driver_Cxt[1] = qca_ptr; + return error; + } + + do + { + /* allocate the driver context and assign it to the qca_ptr mac_param */ + if (NULL == (p_Global_Cxt = (void *)A_MALLOC(sizeof(A_CUSTOM_DRIVER_CONTEXT), MALLOC_ID_CONTEXT))) + { + error = QCA_ERROR; + break; + } + + A_MEMZERO(p_Global_Cxt, sizeof(A_CUSTOM_DRIVER_CONTEXT)); + /* alloc the driver common context */ + void *pCommonCxt = A_MALLOC(sizeof(A_DRIVER_CONTEXT), MALLOC_ID_CONTEXT); + GET_DRIVER_CXT(p_Global_Cxt)->pCommonCxt = pCommonCxt; + if (NULL == pCommonCxt) + { + error = QCA_ERROR; + break; + } + + qca_ptr->MAC_CONTEXT_PTR = p_Global_Cxt; + /* initialize backwards pointers */ + GET_DRIVER_CXT(p_Global_Cxt)->pUpperCxt[0] = qca_ptr; + GET_DRIVER_CXT(p_Global_Cxt)->pDriverParam = qca_ptr->PARAM_PTR->MAC_PARAM; + /* create the 2 driver events. */ + + /* Api_InitStart() will perform any additional allocations that are done as part of + * the common_driver initialization */ + if (A_OK != Api_InitStart(p_Global_Cxt)) + { + error = QCA_ERROR; + break; + } +/* CreateDriverThread is a custom function to create or restart the driver thread. + * the bulk of the driver initialization is handled by the driver thread. + */ + // Start the driver thread with maximum priority. + // It will be scheduled immediately ensuring that Driver_Init() is called before + // the main thread calls Api_InitFinish() below + if (A_OK != Driver_CreateThread(p_Global_Cxt)) + { + error = QCA_ERROR; + break; + } + + /* Api_InitFinish waits for wmi_ready event from chip. */ + if (A_OK != Api_InitFinish(p_Global_Cxt)) + { + error = QCA_ERROR; + break; + } + + g_driverState = DRIVER_STATE_RUN; + + Api_WMIInitFinish(p_Global_Cxt); + } while (0); + + if (error != QCA_OK) + { + if (p_Global_Cxt != NULL) + { +#if 0 + void * tmp_addr; + /* NOTE: ***do not free memory*** in case of timeout/failure + * there is no proper initialization fallback ! */ + + /* Free driver context, may be interrupted */ + tmp_addr = ((cust_context_t *)p_Global_Cxt)->pCommonCxt; + ((cust_context_t *)p_Global_Cxt)->pCommonCxt = NULL; + A_FREE(tmp_addr, MALLOC_ID_CONTEXT); + + /* Free custom driver context, may be interrupted */ + tmp_addr = p_Global_Cxt; + p_Global_Cxt = NULL; + A_FREE(tmp_addr, MALLOC_ID_CONTEXT); +#endif + return error; + } + } + else + { + p_Driver_Cxt[0] = qca_ptr; + } + +#if 0 +if(g_totAlloc){ + A_PRINTF("init alloc: %d\n", g_totAlloc); + //for more information one can implement _mem_get_free() to + //determine how much free memory exists in the system pool. +} +#endif + + Api_BootProfile(p_Global_Cxt, BOOT_PROFILE_DRIVE_READY); + + return error; +} + +/*****************************************************************************/ +/* Custom_Api_Shutdown - Entry point for MQX to shutdown the Driver. + * QCA_CONTEXT_STRUCT_PTR qca_ptr - pointer to MQX ethernet object. + * RETURNS: QCA_OK on success or QCA_ERROR otherwise. + *****************************************************************************/ +static uint32_t Custom_Api_Shutdown(struct qca_context_struct *qca_ptr) +{ + void *pCxt = qca_ptr->MAC_CONTEXT_PTR; + + // Notify driver task to reset itself + Driver_DestroyThread(pCxt); + +//TODO: It simply cannot work +#if 0 + if (pCxt != NULL) + { + Api_DeInitStart(pCxt); + Driver_DestroyThread(pCxt); + Api_DeInitFinish(pCxt); + + if (NULL != GET_DRIVER_COMMON(pCxt)) + { + A_FREE(GET_DRIVER_COMMON(pCxt), MALLOC_ID_CONTEXT); + } + + A_FREE(pCxt, MALLOC_ID_CONTEXT); + p_Global_Cxt = NULL; + qca_ptr->MAC_CONTEXT_PTR = NULL; + } +#endif + + return (uint32_t)QCA_OK; +} + +/*****************************************************************************/ +/* Custom_Api_GetDriverCxt - return driver context based on device ID + * QCA_CONTEXT_STRUCT_PTR qca_ptr - pointer to MQX ethernet object. + * RETURNS: QCA_OK on success or QCA_ERROR otherwise. + *****************************************************************************/ +void *Custom_Api_GetDriverCxt(uint8_t device_id) +{ + return (p_Driver_Cxt[device_id]); +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_ioctl.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_ioctl.c new file mode 100644 index 00000000000..a294cac9b9a --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_ioctl.c @@ -0,0 +1,1993 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if ENABLE_P2P_MODE +#include +#include "p2p.h" +#endif + +#include "atheros_wifi.h" +#include "atheros_wifi_api.h" +#include "atheros_wifi_internal.h" +#include "dset_api.h" +#include "hw20_mbox_host_reg.h" +#include +#include "hw20_apb_map.h" +#include "hw20_mbox_reg.h" + +#if ENABLE_P2P_MODE +// extern WPS_CREDENTIAL persistCredential; +extern WMI_P2P_PROV_INFO p2p_key_val; +#endif + +extern const uint8_t max_performance_power_param; +extern const WMI_STORERECALL_CONFIGURE_CMD default_strrcl_config_cmd; +extern const WMI_SCAN_PARAMS_CMD default_scan_param; + +uint32_t Custom_Api_Mediactl(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t command_id, void *inout_param); +extern uint32_t chip_state_ctrl(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t state); + +/* used to translate from the WPS_ERROR_CODE to that ATH_WPS_ERROR_CODE exposed to app */ +const uint8_t const_wps_error_code_translation[] = { + ATH_WPS_ERROR_SUCCESS, ATH_WPS_ERROR_INVALID_START_INFO, ATH_WPS_ERROR_MULTIPLE_PBC_SESSIONS, + ATH_WPS_ERROR_WALKTIMER_TIMEOUT, ATH_WPS_ERROR_M2D_RCVD, ATH_WPS_ERROR_PWD_AUTH_FAIL, + ATH_WPS_ERROR_CANCELLED, ATH_WPS_ERROR_INVALID_PIN, +}; + +static A_STATUS config_dump_target_assert_info(void *pCxt) +{ + uint32_t regDumpValues[60]; + uint16_t length = 60; + uint16_t i; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + if (A_OK == Driver_DumpAssertInfo(pCxt, regDumpValues, &length)) + { + for (i = 0; i < length; i += 4) + { + QCADRV_PRINTF("0x%08X ", A_LE2CPU32(regDumpValues[i])); + QCADRV_PRINTF("0x%08X ", A_LE2CPU32(regDumpValues[i + 1])); + QCADRV_PRINTF("0x%08X ", A_LE2CPU32(regDumpValues[i + 2])); + QCADRV_PRINTF("0x%08X\n", A_LE2CPU32(regDumpValues[i + 3])); + } + } + /* clear this request */ + pDCxt->asynchRequest = NULL; + return A_OK; +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : ath_ioctl_handler +* PARAMS : +* qca_ptr-> ptr to enet context +* inout_param -> input/output data for command. +* Returned Value : QCA_OK or error code +* Comments : +* IOCTL implementation of Atheros Wifi device. +* +*END*-----------------------------------------------------------------*/ + +int32_t ath_ioctl_handler(QCA_CONTEXT_STRUCT_PTR qca_ptr, ATH_IOCTL_PARAM_STRUCT_PTR param_ptr) +{ + A_STATUS status = A_OK; + int32_t error = QCA_OK; + void *pCxt, *pWmi; + A_DRIVER_CONTEXT *pDCxt; + void *data; + WMI_WPS_PROFILE_EVENT *pWpsEv; + WMI_SCAN_PARAMS_CMD scan_param_cmd; + WMI_CHANNEL_PARAMS_CMD channel_param_cmd; + WMI_SET_ROAM_CTRL_CMD *pRoamCtrl; + uint32_t devId; + uint32_t i, ii; + uint8_t val; + int32_t wait_for_status; + +#if ENABLE_P2P_MODE + WMI_P2P_FW_CONNECT_CMD_STRUCT *pP2PConnect; + WMI_P2P_INVITE_CMD *p2pInvite; + WMI_P2P_GRP_INIT_CMD *p2pGroup; + + union + { + WMI_WPS_START_CMD wps_start; + WMI_P2P_FW_CONNECT_CMD_STRUCT joinProfile; + WMI_SET_HT_CAP_CMD ht_cap_cmd; + WPS_CREDENTIAL *pCred; + A_NETBUF *a_netbuf_ptr; + uint32_t param; + WMI_SCAN_PARAMS_CMD scan_param_cmd; + WMI_LISTEN_INT_CMD listen_param; + WMI_ALLOW_AGGR_CMD allow_aggr_param; + WMI_STORERECALL_HOST_READY_CMD storerecall_ready_param; + WMI_POWER_PARAMS_CMD power_param_param; + WMI_SET_CHANNEL_CMD set_channel_param; + WMI_SET_FILTERED_PROMISCUOUS_MODE_CMD set_prom_param; + WMI_GREENTX_PARAMS_CMD gtx_param; + WMI_LPL_FORCE_ENABLE_CMD lpl_param; + } stackU; +#else + union + { + WMI_WPS_START_CMD wps_start; + WMI_SET_HT_CAP_CMD ht_cap_cmd; + WPS_CREDENTIAL *pCred; + A_NETBUF *a_netbuf_ptr; + uint32_t param; + WMI_SCAN_PARAMS_CMD scan_param_cmd; + WMI_LISTEN_INT_CMD listen_param; + WMI_ALLOW_AGGR_CMD allow_aggr_param; + WMI_STORERECALL_HOST_READY_CMD storerecall_ready_param; + WMI_POWER_PARAMS_CMD power_param_param; + WMI_SET_CHANNEL_CMD set_channel_param; + WMI_SET_FILTERED_PROMISCUOUS_MODE_CMD set_prom_param; + WMI_GREENTX_PARAMS_CMD gtx_param; + WMI_LPL_FORCE_ENABLE_CMD lpl_param; + } stackU; +#endif + +#define WPS_START (stackU.wps_start) +#define HT_CAP (stackU.ht_cap_cmd) +#define CRED_PTR (stackU.pCred) +#define PCB_PTR (stackU.a_netbuf_ptr) +#define PARAM (stackU.param) +#define SCAN_PARAM (stackU.scan_param_cmd) +#define LISTEN_PARAM (stackU.listen_param) +#define AGGR_PARAM (stackU.allow_aggr_param) +#define STRRCL_RDY_PARAM (stackU.storerecall_ready_param) +#define POWER_PARAM_PARAM (stackU.power_param_param) +#define SET_CHANNEL_PARAM (stackU.set_channel_param) +#define SET_PROM_PARAM (stackU.set_prom_param) +#define GTX_PARAM (stackU.gtx_param) +#define LPL_PARAM (stackU.lpl_param) + +#define PTR_POWER_PARAM ((WMI_POWER_PARAMS_CMD *)(data)) +#define PTR_LI ((uint32_t *)(data)) +#define PTR_HOST_MODE ((char *)(data)) +#define PTR_CIPHER ((cipher_t *)(data)) +#define PTR_SEC_MODE ((char *)(data)) +#define PTR_PHY_MODE ((char *)(data)) +#define PTR_CONNECT_CB ((ATH_CONNECT_CB)(data)) +#define PTR_PROBE_CB ((ATH_PROBEREQ_CB)(data)) +#define PTR_STRRCL_START ((uint32_t *)(data)) +#define PTR_VERSION ((ATH_VERSION_PTR)(data)) +#define PTR_VERSION_STR ((ATH_VERSION_STR_PTR)(data)) +#define PTR_WPS_START ((ATH_WPS_START *)(data)) +#define PTR_WPS_GET ((ATH_NETPARAMS *)(data)) +#define PTR_PMK_SET ((uint8_t *)(data)) +#define PTR_SCAN_CTRL ((ATH_SCANPARAMS *)(data)) +#define PTR_SCAN_PARAMS ((WMI_SCAN_PARAMS_CMD *)(data)) +#define PTR_MAC_TX ((ATH_MAC_TX_RAW_S *)(data)) +#define PTR_SET_CHAN ((uint32_t *)(data)) +#define PTR_SET_AGGR ((ATH_SET_AGGREGATION_PARAM *)(data)) +#define PTR_FLASH_CMD ((ATH_PROGRAM_FLASH_STRUCT *)(data)) +#define PTR_TX_STATUS_CMD ((ATH_TX_STATUS *)(data)) +#define PTR_PROM_MODE ((ATH_PROMISCUOUS_MODE *)(data)) +#define PTR_REG_DOMAIN_CMD ((ATH_REG_DOMAIN *)(data)) +#define PTR_EXT_SCAN_CMD ((ATH_GET_SCAN *)(data)) +#define PTR_WEP_IN ((ATH_WEPKEYS *)data) +#define PTR_WEP_INDEX ((uint32_t *)(data)) + +#if ENABLE_P2P_MODE +#define INVITE_PROF (stackU.wpsProfile) +#define JOIN_CONN_PROF (stackU.joinProfile) +#define PTR_PASS_PHRASE ((WMI_SET_PASSPHRASE_CMD *)(data)) +#endif + +#define PTR_LAST_ERROR (uint32_t *)(data) +#define PTR_GTX (uint8_t *)(data) +#define PTR_LPL (uint8_t *)(data) +#define PTR_MAC_ADDR ((ATH_PROGRAM_MAC_ADDR_PARAM *)(data)) +#define PTR_COUNTRY_CODE ((ATH_PROGRAM_COUNTRY_CODE_PARAM *)(data)) + + data = param_ptr->data; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return QCA_ERROR; + } + + pDCxt = GET_DRIVER_COMMON(pCxt); + pWmi = pDCxt->pWmiCxt; + devId = pDCxt->devId; + + switch (param_ptr->cmd_id) + { + case ATH_SCAN_CTRL: + A_MEMCPY(&SCAN_PARAM, &default_scan_param, sizeof(WMI_SCAN_PARAMS_CMD)); + SCAN_PARAM.fg_start_period = + ((PTR_SCAN_CTRL->flags & ATH_DISABLE_FG_SCAN) ? A_CPU2LE16(0xffff) : A_CPU2LE16(0)); + SCAN_PARAM.fg_end_period = + ((PTR_SCAN_CTRL->flags & ATH_DISABLE_FG_SCAN) ? A_CPU2LE16(0xffff) : A_CPU2LE16(0)); + SCAN_PARAM.bg_period = ((PTR_SCAN_CTRL->flags & ATH_DISABLE_BG_SCAN) ? A_CPU2LE16(0xffff) : A_CPU2LE16(0)); + if (A_OK != wmi_cmd_start(pWmi, &SCAN_PARAM, WMI_SET_SCAN_PARAMS_CMDID, sizeof(WMI_SCAN_PARAMS_CMD))) + { + error = QCA_ERROR; + } + else + { + A_MEMCPY(&pDCxt->scan_param, &SCAN_PARAM, sizeof(WMI_SCAN_PARAMS_CMD));//to save scan parameters + } + break; + case ATH_SET_SCAN_PARAM: + A_MEMCPY(&SCAN_PARAM, PTR_SCAN_PARAMS, sizeof(WMI_SCAN_PARAMS_CMD)); + + if (A_OK != wmi_cmd_start(pWmi, &SCAN_PARAM, WMI_SET_SCAN_PARAMS_CMDID, sizeof(WMI_SCAN_PARAMS_CMD))) + { + error = QCA_ERROR; + } + else + { + A_MEMCPY(&pDCxt->scan_param, &SCAN_PARAM, sizeof(WMI_SCAN_PARAMS_CMD));//to save scan parameters + } + break; + case ATH_SET_TXPWR: + if (A_OK != wmi_cmd_start(pWmi, param_ptr->data, WMI_SET_TX_PWR_CMDID, sizeof(WMI_SET_TX_PWR_CMD))) + { + error = QCA_ERROR; + } + break; + case ATH_SET_DEVICE_ID: + { + uint16_t deviceId = *(uint16_t *)(param_ptr->data); + /*No change needed, don't return failure*/ + if (pDCxt->devId == deviceId) + { + break; + } + + if (pDCxt->wps_in_progress) + { + error = QCA_ERROR; + } + + if (deviceId >= WLAN_NUM_OF_DEVICES) + { + error = QCA_ERROR; + break; + } + + ((struct wmi_t *)pWmi)->deviceid = deviceId; + pDCxt->devId = deviceId; + } + break; + case ATH_SET_PMPARAMS: + A_MEMZERO(&POWER_PARAM_PARAM, sizeof(WMI_POWER_PARAMS_CMD)); + POWER_PARAM_PARAM.idle_period = A_CPU2LE16(PTR_POWER_PARAM->idle_period); + POWER_PARAM_PARAM.pspoll_number = A_CPU2LE16(PTR_POWER_PARAM->pspoll_number); + POWER_PARAM_PARAM.dtim_policy = A_CPU2LE16(PTR_POWER_PARAM->dtim_policy); + POWER_PARAM_PARAM.tx_wakeup_policy = A_CPU2LE16(PTR_POWER_PARAM->tx_wakeup_policy); + POWER_PARAM_PARAM.num_tx_to_wakeup = A_CPU2LE16(PTR_POWER_PARAM->num_tx_to_wakeup); + POWER_PARAM_PARAM.ps_fail_event_policy = A_CPU2LE16(PTR_POWER_PARAM->ps_fail_event_policy); + + if (A_OK != + wmi_cmd_start(pWmi, &POWER_PARAM_PARAM, WMI_SET_POWER_PARAMS_CMDID, sizeof(WMI_POWER_PARAMS_CMD))) + { + error = QCA_ERROR; + } + break; + case ATH_SET_LISTEN_INT: + LISTEN_PARAM.listenInterval = A_CPU2LE16((*PTR_LI)); + LISTEN_PARAM.numBeacons = A_CPU2LE16(0); + if (A_OK != wmi_cmd_start(pWmi, &LISTEN_PARAM, WMI_SET_LISTEN_INT_CMDID, sizeof(WMI_LISTEN_INT_CMD))) + { + error = QCA_ERROR; + } + break; + case ATH_SET_CIPHER: + pDCxt->conn[pDCxt->devId].wpaPairwiseCrypto = (uint8_t)PTR_CIPHER->ucipher; + pDCxt->conn[pDCxt->devId].wpaGroupCrypto = (uint8_t)PTR_CIPHER->mcipher; + break; + case ATH_GET_CONC_DEV_CHANNEL: + *(uint16_t *)(param_ptr->data) = 0; +#if WLAN_NUM_OF_DEVICES == 2 + if (pDCxt->devId == 1) + { + if ((pDCxt->conn[0].isConnected) && (!(pDCxt->conn[1].isConnected))) + { + *(uint16_t *)(param_ptr->data) = pDCxt->conn[0].channelHint; + } + } + else if (pDCxt->devId == 0) + { + if ((pDCxt->conn[1].isConnected) && (!(pDCxt->conn[0].isConnected))) + { + *(uint16_t *)(param_ptr->data) = pDCxt->conn[1].channelHint; + } + } +#elif WLAN_NUM_OF_DEVICES == 1 + if (pDCxt->devId == 0) + { + if (pDCxt->conn[0].isConnected) + { + *(uint16_t *)(param_ptr->data) = pDCxt->conn[0].channelHint; + } + } + +#endif + break; + case ATH_SET_SEC_MODE: + if (strcmp(PTR_SEC_MODE, "open") == 0) + { + pDCxt->conn[pDCxt->devId].dot11AuthMode = OPEN_AUTH; + } + else if (strcmp(PTR_SEC_MODE, "shared") == 0) + { + pDCxt->conn[pDCxt->devId].dot11AuthMode = SHARED_AUTH; + } + else + { + error = QCA_ERR_INVALID_INIT_PARAM; + } + break; + case ATH_SET_PHY_MODE: + A_MEMZERO(&HT_CAP, sizeof(WMI_SET_HT_CAP_CMD)); + + if (strcmp(PTR_PHY_MODE, "b") == 0) + { + pDCxt->conn[pDCxt->devId].phyMode = WMI_11B_MODE; + } + else if (strcmp(PTR_PHY_MODE, "g") == 0) + { + pDCxt->conn[pDCxt->devId].phyMode = WMI_11G_MODE; + } + else if (strcmp(PTR_PHY_MODE, "a") == 0) + { + pDCxt->conn[pDCxt->devId].phyMode = WMI_11A_MODE; + } + else if (strcmp(PTR_PHY_MODE, "n") == 0) + { + pDCxt->conn[pDCxt->devId].phyMode = + (pDCxt->conn[pDCxt->devId].phyMode == WMI_11A_MODE) ? WMI_11A_MODE : WMI_11G_MODE; + HT_CAP.band = (pDCxt->conn[pDCxt->devId].phyMode == WMI_11A_MODE) ? 0x01 : 0x00; + HT_CAP.enable = 1; + HT_CAP.short_GI_20MHz = 1; + HT_CAP.max_ampdu_len_exp = 2; + } + else if (strcmp(PTR_PHY_MODE, "ht40") == 0) + { + pDCxt->conn[pDCxt->devId].phyMode = + (pDCxt->conn[pDCxt->devId].phyMode == WMI_11A_MODE) ? WMI_11A_MODE : WMI_11G_MODE; + HT_CAP.band = (pDCxt->conn[pDCxt->devId].phyMode == WMI_11A_MODE) ? 0x01 : 0x00; + HT_CAP.enable = 1; + HT_CAP.short_GI_20MHz = 1; + HT_CAP.short_GI_40MHz = 1; + HT_CAP.intolerance_40MHz = 0; + HT_CAP.max_ampdu_len_exp = 2; + HT_CAP.chan_width_40M_supported = 1; + } + + A_MEMZERO(&channel_param_cmd, sizeof(WMI_CHANNEL_PARAMS_CMD)); + channel_param_cmd.scanParam = 1; + channel_param_cmd.phyMode = pDCxt->conn[pDCxt->devId].phyMode; + if (A_OK != + wmi_cmd_start(pWmi, &channel_param_cmd, WMI_SET_CHANNEL_PARAMS_CMDID, sizeof(WMI_CHANNEL_PARAMS_CMD))) + { + error = QCA_ERROR; + break; + } + + if (A_OK != wmi_cmd_start(pWmi, &HT_CAP, WMI_SET_HT_CAP_CMDID, sizeof(WMI_SET_HT_CAP_CMD))) + { + error = QCA_ERROR; + break; + } + break; + case ATH_GET_PHY_MODE: + *(uint32_t *)(param_ptr->data) = pDCxt->conn[pDCxt->devId].phyMode; + break; + case ATH_GET_RX_RSSI: + pDCxt->rssiFlag = true; + wmi_cmd_start(pWmi, NULL, WMI_GET_STATISTICS_CMDID, 0); + + while (pDCxt->rssiFlag == true) + { + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->rssiFlag), false, 1000); + } + *(uint8_t *)(param_ptr->data) = pDCxt->rssi; + break; + case ATH_GET_TEMPERATURE: + pDCxt->temperatureValid = false; + if (A_OK == wmi_cmd_start(pWmi, NULL, WMI_GET_TEMPERATURE_CMDID, 0)) + { + /* block here until event arrives from wifi device */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->temperatureValid), true, 1000); + } + if (pDCxt->temperatureValid == false) + { + error = QCA_ERROR; + } + else + { + (((WMI_GET_TEMPERATURE_REPLY *)(param_ptr->data))->tempRegVal) = pDCxt->raw_temperature; + (((WMI_GET_TEMPERATURE_REPLY *)(param_ptr->data))->tempDegree) = pDCxt->tempDegree; + pDCxt->temperatureValid = false; + } + break; + case ATH_GET_COUNTRY_CODE: + pDCxt->countryCodeValid = false; + + if (A_OK == wmi_cmd_start(pWmi, param_ptr->data, WMI_GET_COUNTRY_CODE_CMDID, param_ptr->length)) + { + /* block here until event arrives from wifi device */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->countryCodeValid), true, 1000); + } + + if (pDCxt->countryCodeValid == false) + { + error = QCA_ERROR; + } + else + { + A_MEMCPY(((WMI_GET_COUNTRY_CODE_REPLY *)(param_ptr->data))->country_code, pDCxt->raw_countryCode, 3); + + pDCxt->countryCodeValid = false; + } + + break; + case ATH_SET_PARAM: + wait_for_status = *((uint32_t *)((uint8_t *)param_ptr->data + param_ptr->length)); + pDCxt->setparamValid = false; + if (A_OK == wmi_cmd_start(pWmi, param_ptr->data, WMI_PARAM_SET_CMDID, param_ptr->length)) + { + if (wait_for_status) + { + /* block here until event arrives from wifi device */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->setparamValid), true, 1000); + if (pDCxt->setparamValid == false) + { + error = QCA_ERROR; + } + else + { + if (pDCxt->setparamStatus != A_OK) + { + error = QCA_ERROR; + } + } + } + } + else + { + error = QCA_ERROR; + } + break; + case ATH_ROAM_CTRL: + A_MEMCPY( &SCAN_PARAM,&pDCxt->scan_param, sizeof(WMI_SCAN_PARAMS_CMD)); + pRoamCtrl = (WMI_SET_ROAM_CTRL_CMD *) param_ptr->data; + //pDCxt->roam_req_enable = (pRoamCtrl->info.roamMode == 1) ? A_TRUE:A_FALSE ; + if(pRoamCtrl->info.roamMode == 3)//disable roaming and forbid PROREQ_SEND + { + SCAN_PARAM.scanCtrlFlags &= ~ROAM_SCAN_CTRL_FLAGS; + } + else + { + SCAN_PARAM.scanCtrlFlags |= ROAM_SCAN_CTRL_FLAGS ; + } + //wmi_cmd_start(pWmi, param_ptr->data, WMI_SET_ROAM_CTRL_CMDID, sizeof(WMI_SET_ROAM_CTRL_CMD)) ; + if(A_OK != wmi_cmd_start(pWmi, &SCAN_PARAM, WMI_SET_SCAN_PARAMS_CMDID, sizeof(WMI_SCAN_PARAMS_CMD))) + { + error = A_ERROR; + } + else + { + A_MEMCPY(&pDCxt->scan_param, &SCAN_PARAM, sizeof(WMI_SCAN_PARAMS_CMD));//update scan parameters + } + break; + case ATH_SET_CONNECT_STATE_CALLBACK: + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + GET_DRIVER_CXT(pCxt)->connectStateCB = (void *)PTR_CONNECT_CB; + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + break; + + case ATH_SET_PROBEREQ_CB: + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + GET_DRIVER_CXT(pCxt)->probeReqCB = (void *)PTR_PROBE_CB; + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + break; + +#if DRIVER_CONFIG_ENABLE_STORE_RECALL + case ATH_DEVICE_SUSPEND_ENABLE: + if (pDCxt->strrclState == STRRCL_ST_DISABLED && + A_OK == wmi_cmd_start(pDCxt->pWmiCxt, &default_strrcl_config_cmd, WMI_STORERECALL_CONFIGURE_CMDID, + sizeof(WMI_STORERECALL_CONFIGURE_CMD))) + { + pDCxt->strrclState = STRRCL_ST_INIT; + error = QCA_OK; + } + else + { + if (pDCxt->strrclState != STRRCL_ST_INIT) + error = QCA_ERROR; + } + break; + + case ATH_DEVICE_SUSPEND_START: + error = QCA_ERROR; + +/* ensure that no power save is used during Suspend. Store-recall and Power save + are not supposed to work together, it is one-or-the-other */ +#if 1 + if (A_OK != move_power_state_to_maxperf(pDCxt, 1)) /* refer POWER_STATE_MOVED_FOR_STRRCL */ + { + status = A_ERROR; + break; + } +#else + if (A_OK != + wmi_cmd_start(pWmi, &max_performance_power_param, WMI_SET_POWER_MODE_CMDID, sizeof(WMI_POWER_MODE_CMD))) + { + error = QCA_ERROR; + } + pDCxt->userPwrMode = MAX_PERF_POWER; +#endif + +#if 0 + STRRCL_RDY_PARAM.sleep_msec = A_CPU2LE32((*PTR_STRRCL_START)); + STRRCL_RDY_PARAM.store_after_tx_empty = 1; + STRRCL_RDY_PARAM.store_after_fresh_beacon_rx = 1; + + if(pDCxt->strrclState == STRRCL_ST_INIT){ + if(((*PTR_STRRCL_START) >= MIN_STRRCL_MSEC) && + A_OK == wmi_cmd_start(pWmi, &STRRCL_RDY_PARAM, + WMI_STORERECALL_HOST_READY_CMDID, + sizeof(WMI_STORERECALL_HOST_READY_CMD))) + { + pDCxt->strrclState = STRRCL_ST_START; + error = QCA_OK; + } + } +#else + if (pDCxt->strrclState == STRRCL_ST_INIT && ((*PTR_STRRCL_START) >= MIN_STRRCL_MSEC)) + { + /* set strrclBlock before call to wmi_storerecall_ready_cmd to prevent + * any potential race conditions with other tasks calling into the + * driver. + */ + pDCxt->strrclBlock = true; + STRRCL_RDY_PARAM.sleep_msec = A_CPU2LE32((*PTR_STRRCL_START)); + STRRCL_RDY_PARAM.store_after_tx_empty = 1; + STRRCL_RDY_PARAM.store_after_fresh_beacon_rx = 1; + + if (A_OK == wmi_cmd_start(pWmi, &STRRCL_RDY_PARAM, WMI_STORERECALL_HOST_READY_CMDID, + sizeof(WMI_STORERECALL_HOST_READY_CMD))) + { + pDCxt->strrclState = STRRCL_ST_START; + status = A_OK; + error = QCA_OK; + } + else + { + pDCxt->strrclBlock = false; + } + } +#endif + break; +#endif /* DRIVER_CONFIG_ENABLE_STORE_RECALL */ + case ATH_SET_PMK: + if (A_OK != wmi_cmd_start(pWmi, PTR_PMK_SET, WMI_SET_PMK_CMDID, sizeof(WMI_SET_PMK_CMD))) + { + error = QCA_ERROR; + } + break; + case ATH_GET_PMK: + pDCxt->conn[pDCxt->devId].wpaPmkValid = false; + + if (A_OK == wmi_cmd_start(pWmi, NULL, WMI_GET_PMK_CMDID, 0)) + { + /* block here until event arrives from wifi device */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->conn[pDCxt->devId].wpaPmkValid), true, 5000); + + if (pDCxt->conn[pDCxt->devId].wpaPmkValid == false) + { + error = QCA_ERROR; + } + else + { + A_MEMCPY((uint8_t *)param_ptr->data, pDCxt->conn[pDCxt->devId].wpaPmk, WMI_PMK_LEN); + pDCxt->conn[pDCxt->devId].wpaPmkValid = false; + } + } + break; + case ATH_GET_VERSION: + PTR_VERSION->host_ver = pDCxt->hostVersion; + PTR_VERSION->target_ver = pDCxt->targetVersion; + PTR_VERSION->wlan_ver = pDCxt->wlanVersion; + PTR_VERSION->abi_ver = pDCxt->abiVersion; + break; + case ATH_GET_VERSION_STR: +#define PRINT_HOSTFWVERSION(ver) \ + (uint16_t)((ver & 0xF0000000) >> 28), (uint16_t)((ver & 0x0F000000) >> 24), (uint16_t)((ver & 0x00FF0000) >> 16), \ + (uint16_t)(ver & 0x0000FFFF) + sprintf((char *)PTR_VERSION_STR->host_ver, "%u.%u.%u.%u", PRINT_HOSTFWVERSION(pDCxt->hostVersion)); + sprintf((char *)PTR_VERSION_STR->target_ver, "0x%lx", pDCxt->targetVersion); + sprintf((char *)PTR_VERSION_STR->wlan_ver, "%u.%u.%u.%u", PRINT_HOSTFWVERSION(pDCxt->wlanVersion)); + sprintf((char *)PTR_VERSION_STR->abi_ver, "%lu", pDCxt->abiVersion); + break; + case ATH_GET_MACADDR: + A_MEMCPY(param_ptr->data, qca_ptr->ADDRESS, ATH_MAC_LEN); + break; + case ATH_START_WPS: + /* FIXME: there exists the possibility of a race condition if the device has + * sent a WPS event in response to a previous ATH_START_WPS then it becomes + * possible for the driver to misinterpret that event as being the result of + * the most recent ATH_START_WPS. To fix this the wmi command should include + * an ID value that is returned by the WPS event so that the driver can + * accurately match an event from the device to the most recent WPS command. + */ + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + if (pDCxt->wpsBuf) + { + A_NETBUF_FREE(pDCxt->wpsBuf); + pDCxt->wpsBuf = NULL; + } + + pDCxt->wpsEvent = NULL; + + if (pDCxt->wpsState == true) + { + pDCxt->wpsState = false; + } + + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + A_MEMZERO(&WPS_START, sizeof(WMI_WPS_START_CMD)); + WPS_START.timeout = PTR_WPS_START->timeout_seconds; + WPS_START.role = + (AP_NETWORK == pDCxt->conn[pDCxt->devId].networkType) ? WPS_REGISTRAR_ROLE : WPS_ENROLLEE_ROLE; + + if (0x02 == PTR_WPS_START->connect_flag) + { + WPS_START.role = WPS_AP_ENROLLEE_ROLE; + } + if (PTR_WPS_START->wps_mode == ATH_WPS_MODE_PIN) + { + WPS_START.config_mode = WPS_PIN_MODE; + WPS_START.wps_pin.pin_length = PTR_WPS_START->pin_length; + A_MEMCPY(WPS_START.wps_pin.pin, PTR_WPS_START->pin, ATH_WPS_PIN_LEN); + } + else if (PTR_WPS_START->wps_mode == ATH_WPS_MODE_PUSHBUTTON) + { + WPS_START.config_mode = WPS_PBC_MODE; + } + else + { + error = A_ERROR; + break; /* early break */ + } + if (AP_NETWORK != pDCxt->conn[pDCxt->devId].networkType) + { + if (0x08 == PTR_WPS_START->connect_flag) + { + /* WPS Request from P2P Module */ + WPS_START.ctl_flag |= 0x1; + } + if (PTR_WPS_START->ssid_info.ssid_len != 0) + { + A_MEMCPY(WPS_START.ssid_info.ssid, PTR_WPS_START->ssid_info.ssid, + PTR_WPS_START->ssid_info.ssid_len); + A_MEMCPY(WPS_START.ssid_info.macaddress, PTR_WPS_START->ssid_info.macaddress, 6); + WPS_START.ssid_info.channel = PTR_WPS_START->ssid_info.channel; + WPS_START.ssid_info.ssid_len = PTR_WPS_START->ssid_info.ssid_len; + } + + /* prevent background scan during WPS */ + A_MEMCPY(&scan_param_cmd, &default_scan_param, sizeof(WMI_SCAN_PARAMS_CMD)); + scan_param_cmd.bg_period = A_CPU2LE16(0xffff); + + if (A_OK != + wmi_cmd_start(pWmi, &scan_param_cmd, WMI_SET_SCAN_PARAMS_CMDID, sizeof(WMI_SCAN_PARAMS_CMD))) + { + error = A_ERROR; + break; + } + } + else + { + WPS_START.ctl_flag |= 0x1; + } + + if (A_OK != wmi_cmd_start(pWmi, &WPS_START, WMI_WPS_START_CMDID, sizeof(WMI_WPS_START_CMD))) + { + error = A_ERROR; + break; + } + + pDCxt->wpsState = true; + pDCxt->wps_in_progress = true; + break; + case ATH_AWAIT_WPS_COMPLETION: + /* await wps completion */ + + if (PTR_WPS_GET->dont_block && pDCxt->wpsState == true) + { + /* the caller does not want to block the task until completion + * so if not yet complete then return immediately with appropriate + * error code. */ + error = A_PENDING; + break; + } + + while (pDCxt->wpsState == true) + { + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->wpsState), false, 1000); + } + + /* reach here means wps_in_progress is done whether wps success or fail */ + pDCxt->wps_in_progress = false; + if (pDCxt->wpsBuf != NULL) + { + if (pDCxt->wpsEvent != NULL) + { + pWpsEv = (WMI_WPS_PROFILE_EVENT *)pDCxt->wpsEvent; + + if (pWpsEv->status == WPS_STATUS_SUCCESS) + { + CRED_PTR = &(pWpsEv->credential); + PTR_WPS_GET->error = ATH_WPS_ERROR_SUCCESS; + A_MEMCPY(PTR_WPS_GET->ssid, CRED_PTR->ssid, CRED_PTR->ssid_len); + PTR_WPS_GET->ssid_len = CRED_PTR->ssid_len; + PTR_WPS_GET->ssid[CRED_PTR->ssid_len] = '\0'; + PTR_WPS_GET->ap_channel = CRED_PTR->ap_channel; + + if (CRED_PTR->key_len) + { + /* the encr_type may have multiple options (bits) set + * therefore the order in which we test for support is + * important. this code tests for AES first and so AES + * will be the default when AES is at least one option. + */ + if (CRED_PTR->encr_type & WPS_CRED_ENCR_AES) + { + PTR_WPS_GET->cipher.ucipher = AES_CRYPT; + PTR_WPS_GET->cipher.mcipher = AES_CRYPT; + } + else if (CRED_PTR->encr_type & WPS_CRED_ENCR_TKIP) + { + PTR_WPS_GET->cipher.ucipher = TKIP_CRYPT; + PTR_WPS_GET->cipher.mcipher = TKIP_CRYPT; + } + else if (CRED_PTR->encr_type & WPS_CRED_ENCR_WEP) + { + PTR_WPS_GET->cipher.ucipher = WEP_CRYPT; + PTR_WPS_GET->cipher.mcipher = WEP_CRYPT; + } + /* as with encr_type the auth_type field may contain multiple options. + * As such we test for options in a preferred order with WPA2 as top + * followed by WPA and lastly by the 2 WEP options. */ + if (CRED_PTR->auth_type & WPS_CRED_AUTH_WPA2PSK) + { + PTR_WPS_GET->sec_type = QCA_MEDIACTL_SECURITY_TYPE_WPA2; + GET_DRIVER_COMMON(pCxt)->securityType = QCA_MEDIACTL_SECURITY_TYPE_WPA2; + A_MEMCPY(PTR_WPS_GET->u.passphrase, CRED_PTR->key, CRED_PTR->key_len); + PTR_WPS_GET->u.passphrase[CRED_PTR->key_len] = '\0'; + } + else if (CRED_PTR->auth_type & WPS_CRED_AUTH_WPAPSK) + { + PTR_WPS_GET->sec_type = QCA_MEDIACTL_SECURITY_TYPE_WPA; + GET_DRIVER_COMMON(pCxt)->securityType = QCA_MEDIACTL_SECURITY_TYPE_WPA; + A_MEMCPY(PTR_WPS_GET->u.passphrase, CRED_PTR->key, CRED_PTR->key_len); + PTR_WPS_GET->u.passphrase[CRED_PTR->key_len] = '\0'; + } + else if ((CRED_PTR->auth_type & WPS_CRED_AUTH_OPEN) || + (CRED_PTR->auth_type & WPS_CRED_AUTH_SHARED)) + { + PTR_WPS_GET->sec_type = QCA_MEDIACTL_SECURITY_TYPE_WEP; + GET_DRIVER_COMMON(pCxt)->securityType = QCA_MEDIACTL_SECURITY_TYPE_WEP; + A_MEMCPY(PTR_WPS_GET->u.wepkey, CRED_PTR->key, CRED_PTR->key_len); + PTR_WPS_GET->u.wepkey[CRED_PTR->key_len] = '\0'; + PTR_WPS_GET->key_index = CRED_PTR->key_idx; + } + else + { + /* this driver does not support these modes: WPS_CRED_AUTH_WPA || WPS_CRED_AUTH_WPA2 */ + error = A_ERROR; + pDCxt->wps_in_progress = false; + break; + } + } + else + { + /* no security */ + PTR_WPS_GET->sec_type = QCA_MEDIACTL_SECURITY_TYPE_NONE; + GET_DRIVER_COMMON(pCxt)->securityType = QCA_MEDIACTL_SECURITY_TYPE_NONE; + PTR_WPS_GET->cipher.ucipher = NONE_CRYPT; + PTR_WPS_GET->cipher.mcipher = NONE_CRYPT; + } + } + else if (pWpsEv->status == WPS_STATUS_FAILURE) + { + if (pWpsEv->error_code < sizeof(const_wps_error_code_translation) / sizeof(uint8_t)) + { + PTR_WPS_GET->error = const_wps_error_code_translation[pWpsEv->error_code]; + } + else + { + //NOTE: Change was demanded by Coverity, set 'error' instead 'return', need to free netbuf + //Former code: PTR_WPS_GET->error = const_wps_error_code_translation[pWpsEv->error_code]; + error = QCA_ERROR; + } + pDCxt->wps_in_progress = false; + } + pDCxt->wpsEvent = NULL; + } + + A_NETBUF_FREE(pDCxt->wpsBuf); + pDCxt->wpsBuf = NULL; + /* ensure that the device is disconnected from the wps session */ + if (AP_NETWORK == pDCxt->conn[pDCxt->devId].networkType) + { + pDCxt->wps_in_progress = false; + break; + } + +#if ENABLE_P2P_MODE + if (1 == pDCxt->p2p_avail) + { + break; + } +#endif + if (wmi_cmd_start(pDCxt->pWmiCxt, NULL, WMI_DISCONNECT_CMDID, 0) != A_OK) + { + pDCxt->wps_in_progress = false; + error = A_ERROR; + break; + } + } + else + { + pDCxt->wps_in_progress = false; + error = A_ERROR; + } + break; + case ATH_MAC_TX_RAW: + /* FIXME: need away to hold the buffer until the transmit is complete. for + * now we block the thread until the transmit completes. */ + if ((PCB_PTR = A_NETBUF_ALLOC(0)) == NULL) + { + error = QCA_ERR_ALLOC_PCB; + break; + } + + A_NETBUF_APPEND_FRAGMENT(PCB_PTR, PTR_MAC_TX->buffer, PTR_MAC_TX->length); + + // ensure there is enough headroom to complete the tx operation + if (A_NETBUF_HEADROOM(PCB_PTR) < (int32_t)(sizeof(WMI_DATA_HDR) + HTC_HDR_LENGTH + WMI_MAX_TX_META_SZ)) + { + error = QCA_ERR_ALLOC_PCB; + A_NETBUF_FREE(PCB_PTR); + break; + } + + if (A_OK != TxRawPacket(pCxt, (void *)PCB_PTR, &(PTR_MAC_TX->params))) + { + A_NETBUF_FREE(PCB_PTR); + error = QCA_ERROR; + break; + } + break; + case ATH_SET_CHANNEL: + pDCxt->conn[pDCxt->devId].channelHint = (uint16_t)(*(PTR_SET_CHAN)); + SET_CHANNEL_PARAM.channel = A_CPU2LE16(pDCxt->conn[pDCxt->devId].channelHint); + + if (A_OK != wmi_cmd_start(pWmi, &SET_CHANNEL_PARAM, WMI_SET_CHANNEL_CMDID, sizeof(uint16_t))) + { + error = QCA_ERROR; + break; + } + break; + case ATH_SET_AGGREGATION: +#if WLAN_CONFIG_11N_AGGR_SUPPORT + pDCxt->txAggrTidMask = PTR_SET_AGGR->txTIDMask; + pDCxt->rxAggrTidMask = PTR_SET_AGGR->rxTIDMask; + AGGR_PARAM.tx_allow_aggr = A_CPU2LE16(pDCxt->txAggrTidMask); + AGGR_PARAM.rx_allow_aggr = A_CPU2LE16(pDCxt->rxAggrTidMask); + wmi_cmd_start(pWmi, &AGGR_PARAM, WMI_ALLOW_AGGR_CMDID, sizeof(WMI_ALLOW_AGGR_CMD)); +#endif /* WLAN_CONFIG_11N_AGGR_SUPPORT */ + break; + case ATH_ASSERT_DUMP: + /* setup driver thread to perform operation on behalf of this thread. + * this will avoid accessing HCD by multiple threads. */ + if (pDCxt->asynchRequest == NULL) + { + pDCxt->asynchRequest = config_dump_target_assert_info; + DRIVER_WAKE_DRIVER(pCxt); + } + break; + case ATH_PROGRAM_FLASH: + status = + BMIWriteMemory(pCxt, PTR_FLASH_CMD->load_addr, (uint8_t *)PTR_FLASH_CMD->buffer, PTR_FLASH_CMD->length); + + if (status == A_OK) + { + PTR_FLASH_CMD->result = 1; + } + else + { + PTR_FLASH_CMD->result = status; + } + break; + case ATH_EXECUTE_FLASH: + + PARAM = A_CPU2LE32(PTR_FLASH_CMD->result); + status = BMIExecute(pCxt, PTR_FLASH_CMD->load_addr, &PARAM); + + if (status == A_OK) + { + PTR_FLASH_CMD->result = PARAM; + } + else + { + PTR_FLASH_CMD->result = 0; + } + break; + case ATH_GET_TX_STATUS: + PTR_TX_STATUS_CMD->status = Api_TxGetStatus(pCxt); + break; + case ATH_GET_RATE: + { + if (A_OK != wmi_cmd_start(pWmi, NULL, WMI_GET_BITRATE_CMDID, 0)) + { + error = QCA_ERROR; + } + } + break; + case ATH_SET_PROMISCUOUS_MODE: + pDCxt->promiscuous_mode = (PTR_PROM_MODE->enable == 0) ? 0 : 1; + GET_DRIVER_CXT(pCxt)->promiscuous_cb = (void *)PTR_PROM_MODE->cb; + SET_PROM_PARAM.enable = pDCxt->promiscuous_mode; + SET_PROM_PARAM.filters = PTR_PROM_MODE->filter_flags; + A_MEMCPY(SET_PROM_PARAM.srcAddr, &(PTR_PROM_MODE->src_mac[0]), ATH_MAC_LEN); + A_MEMCPY(SET_PROM_PARAM.dstAddr, &(PTR_PROM_MODE->dst_mac[0]), ATH_MAC_LEN); + + if (A_OK != wmi_cmd_start(pWmi, &SET_PROM_PARAM, WMI_SET_FILTERED_PROMISCUOUS_MODE_CMDID, + sizeof(WMI_SET_FILTERED_PROMISCUOUS_MODE_CMD))) + { + error = QCA_ERROR; + } + break; + case ATH_GET_REG_DOMAIN: + PTR_REG_DOMAIN_CMD->domain = GET_DRIVER_COMMON(pCxt)->regCode; + break; + case ATH_START_SCAN_EXT: + GET_DRIVER_COMMON(pCxt)->extended_scan = 1; + error = scan_setup(pCxt, pWmi, NULL); + break; + case ATH_GET_SCAN_EXT: + wait_scan_done(pCxt, pWmi); + PTR_EXT_SCAN_CMD->scan_list = (ATH_SCAN_EXT *)GET_DRIVER_COMMON(pCxt)->pScanOut; + PTR_EXT_SCAN_CMD->num_entries = GET_DRIVER_COMMON(pCxt)->scanOutCount; + break; + case ATH_GET_LAST_ERROR: + *PTR_LAST_ERROR = last_driver_error; + break; +#if ENABLE_AP_MODE + // case ATH_SET_EZCONN: + // pDCxt->ezConnectCmd = 1; + // break; + case ATH_CONFIG_AP: + { + ATH_AP_PARAM_STRUCT *ap_param = (ATH_AP_PARAM_STRUCT *)param_ptr->data; + if (AP_SUB_CMD_WPS_FLAG == ap_param->cmd_subset) + { + pDCxt->apmodeWPS = 1; + + break; + } + wmi_ap_set_param(pWmi, (void *)param_ptr->data); + } + break; +#endif /* ENABLE_AP_MODE */ + case ATH_GET_CHANNEL: + *((uint16_t *)param_ptr->data) = pDCxt->conn[pDCxt->devId].bssChannel; + break; + case ATH_GET_CHANNELHINT: + *((uint16_t *)param_ptr->data) = pDCxt->conn[pDCxt->devId].channelHint; + break; +#if ENABLE_P2P_MODE + case ATH_SET_P2P_CALLBACK: + + if (GET_DRIVER_COMMON(pCxt)->p2pEvtState == true) + { + if (DRIVER_WAIT_FOR_CONDITION(pCxt, &(GET_DRIVER_COMMON(pCxt)->p2pEvtState), false, 5000) != A_OK) + { + GET_DRIVER_COMMON(pCxt)->p2pEvtState = false; + status = A_ERROR; + break; + } + GET_DRIVER_COMMON(pCxt)->p2pEvtState = false; + } + A_MEMCPY(param_ptr->data, GET_DRIVER_COMMON(pCxt)->pScanOut, P2P_EVT_BUF_SIZE); + + break; + case ATH_P2P_EVENT_CALLBACK: + if (GET_DRIVER_COMMON(pCxt)->p2pevtflag == true) + { + A_MEMCPY(param_ptr->data, GET_DRIVER_COMMON(pCxt)->pScanOut, 516); + GET_DRIVER_COMMON(pCxt)->p2pevtflag = false; + } + else + { + status = A_ERROR; + } + break; + case ATH_P2P_APMODE: + { + p2pGroup = (WMI_P2P_GRP_INIT_CMD *)param_ptr->data; + + pDCxt->p2p_avail = 1; + pDCxt->conn[pDCxt->devId].networkType = AP_NETWORK; + + if (p2pGroup->group_formation) + { + wmi_cmd_start(pWmi, p2pGroup, WMI_P2P_GRP_INIT_CMDID, sizeof(WMI_P2P_GRP_INIT_CMD)); + } + + if (Api_ConnectWiFi(pCxt) != A_OK) + { + status = A_ERROR; + } + pDCxt->userPwrMode = MAX_PERF_POWER; + } + break; + case ATH_P2P_APMODE_PP: + { +#if 1 + A_MEMCPY(((struct wmi_t *)pWmi)->apPassPhrase.passphrase, PTR_PASS_PHRASE->passphrase, + PTR_PASS_PHRASE->passphrase_len); + ((struct wmi_t *)pWmi)->apPassPhrase.passphrase_len = PTR_PASS_PHRASE->passphrase_len; + A_MEMCPY(((struct wmi_t *)pWmi)->apPassPhrase.ssid, PTR_PASS_PHRASE->ssid, PTR_PASS_PHRASE->ssid_len); + ((struct wmi_t *)pWmi)->apPassPhrase.ssid_len = PTR_PASS_PHRASE->ssid_len; + // if (((struct wmi_t *)pWmi)->apPassPhrase.ssid_len != 0) { + if (A_OK != wmi_cmd_start(pWmi, &((struct wmi_t *)pWmi)->apPassPhrase, WMI_SET_PASSPHRASE_CMDID, + sizeof(WMI_SET_PASSPHRASE_CMD))) + { + status = A_ERROR; + } + +//} +#endif + } + break; + case ATH_P2P_FIND: + { + pDCxt->p2p_avail = 1; + if (wmi_cmd_start(pWmi, (WMI_P2P_FIND_CMD *)param_ptr->data, WMI_P2P_FIND_CMDID, + sizeof(WMI_P2P_FIND_CMD)) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_CONNECT: + { +#if 0 + if(wmi_p2p_go_neg_start(pWmi, (WMI_P2P_GO_NEG_START_CMD *)param_ptr->data) != A_OK) + { + status = A_ERROR; + } +#endif + } + break; + case ATH_P2P_CONNECT_CLIENT: + { + WMI_P2P_FW_CONNECT_CMD_STRUCT p2p_connect_param; + GET_DRIVER_COMMON(pCxt)->p2pEvtState = true; + A_MEMZERO(&p2p_connect_param, sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + A_MEMCPY(&p2p_connect_param, (WMI_P2P_FW_CONNECT_CMD_STRUCT *)param_ptr->data, + sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + if ((p2p_connect_param.go_intent >= 10) || (p2p_connect_param.go_intent == 15)) + { + pDCxt->conn[pDCxt->devId].networkType = AP_NETWORK; + } + if ((p2p_connect_param.go_intent <= 9) || (p2p_connect_param.go_intent == 0)) + { + pDCxt->conn[pDCxt->devId].networkType = INFRA_NETWORK; + } + if (wmi_cmd_start(pWmi, (WMI_P2P_FW_CONNECT_CMD_STRUCT *)param_ptr->data, WMI_P2P_CONNECT_CMDID, + sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_LISTEN: + { + uint32_t time_out_val; + A_MEMCPY(&time_out_val, param_ptr->data, sizeof(uint32_t)); + if (wmi_cmd_start(pWmi, &time_out_val, WMI_P2P_LISTEN_CMDID, sizeof(time_out_val)) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_CANCEL: + { + if (wmi_cmd_start(pWmi, NULL, WMI_P2P_CANCEL_CMDID, 0) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_STOP: + { + if (wmi_cmd_start(pWmi, NULL, WMI_P2P_STOP_FIND_CMDID, 0) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_NODE_LIST: + { + GET_DRIVER_COMMON(pCxt)->p2pEvtState = true; + if (wmi_cmd_start(pWmi, NULL, WMI_P2P_GET_NODE_LIST_CMDID, 0) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_SET_CONFIG: + { + if (wmi_cmd_start(pWmi, (WMI_P2P_FW_SET_CONFIG_CMD *)param_ptr->data, WMI_P2P_SET_CONFIG_CMDID, + sizeof(WMI_P2P_FW_SET_CONFIG_CMD)) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_WPS_CONFIG: + { + if (wmi_cmd_start(pWmi, (WMI_WPS_SET_CONFIG_CMD *)param_ptr->data, WMI_WPS_SET_CONFIG_CMDID, + sizeof(WMI_WPS_SET_CONFIG_CMD)) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_AUTH: + { + if (wmi_cmd_start(pWmi, (WMI_P2P_FW_CONNECT_CMD_STRUCT *)param_ptr->data, WMI_P2P_AUTH_GO_NEG_CMDID, + sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_DISC_REQ: + { + if (wmi_cmd_start(pWmi, (WMI_P2P_FW_PROV_DISC_REQ_CMD *)param_ptr->data, WMI_P2P_FW_PROV_DISC_REQ_CMDID, + sizeof(WMI_P2P_FW_PROV_DISC_REQ_CMD)) != A_OK) + { + status = A_ERROR; + } + GET_DRIVER_COMMON(pCxt)->p2pEvtState = true; + } + break; + case ATH_P2P_SET: + { + if (wmi_cmd_start(pWmi, (WMI_P2P_SET_CMD *)param_ptr->data, WMI_P2P_SET_CMDID, sizeof(WMI_P2P_SET_CMD)) != + A_OK) + { + status = A_ERROR; + } + } + break; +#if 1 + case ATH_P2P_INVITE_AUTH: + { + GET_DRIVER_COMMON(pCxt)->p2pEvtState = true; + if (wmi_cmd_start(pWmi, (WMI_P2P_FW_INVITE_REQ_RSP_CMD *)param_ptr->data, WMI_P2P_INVITE_REQ_RSP_CMDID, + sizeof(WMI_P2P_FW_INVITE_REQ_RSP_CMD)) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_PERSISTENT_LIST: + { + GET_DRIVER_COMMON(pCxt)->p2pEvtState = true; + if (wmi_cmd_start(pWmi, NULL, WMI_P2P_LIST_PERSISTENT_NETWORK_CMDID, 0) != A_OK) + { + status = A_ERROR; + } + } + break; + case ATH_P2P_INVITE: + { + p2pInvite = (WMI_P2P_INVITE_CMD *)param_ptr->data; + // p2pInvite->is_persistent = 1; // for now we do invitation for persistent clients + p2pInvite->dialog_token = 1; + if (wmi_cmd_start(pWmi, (WMI_P2P_INVITE_CMD *)param_ptr->data, WMI_P2P_INVITE_CMDID, + sizeof(WMI_P2P_INVITE_CMD)) != A_OK) + { + status = A_ERROR; + } + } + break; +#endif + case ATH_P2P_JOIN: + { + pP2PConnect = (WMI_P2P_FW_CONNECT_CMD_STRUCT *)param_ptr->data; + A_MEMZERO(&WPS_START, sizeof(WMI_WPS_START_CMD)); + WPS_START.timeout = 30; + WPS_START.role = WPS_ENROLLEE_ROLE; + +#if ENABLE_SCC_MODE + int num_dev = WLAN_NUM_OF_DEVICES; + + if ((num_dev > 1) && (pDCxt->conn[1].isConnected == true) && (pP2PConnect->go_oper_freq == 0)) + { + error = A_ERROR; + break; + } + if ((num_dev > 1) && (pDCxt->conn[1].isConnected == true)) + { + if (pP2PConnect->go_oper_freq != pDCxt->conn[1].channelHint) + { + error = A_ERROR; + break; + } + } +#endif /* ENABLE_SCC_MODE */ + if (pP2PConnect->wps_method == WPS_PBC) + { + WPS_START.config_mode = WPS_PBC_MODE; + } + else if (pP2PConnect->wps_method == WPS_PIN_DISPLAY || pP2PConnect->wps_method == WPS_PIN_KEYPAD) + { + WPS_START.config_mode = WPS_PIN_MODE; + A_MEMCPY(WPS_START.wps_pin.pin, p2p_key_val.wps_pin, WPS_PIN_LEN); + WPS_START.wps_pin.pin_length = WPS_PIN_LEN; + } + else + { + status = A_ERROR; + break; /* early break */ + } + if (pP2PConnect->peer_go_ssid.ssidLength != 0) + { + memcpy(WPS_START.ssid_info.ssid, pP2PConnect->peer_go_ssid.ssid, pP2PConnect->peer_go_ssid.ssidLength); + memcpy(WPS_START.ssid_info.macaddress, pP2PConnect->peer_addr, 6); + WPS_START.ssid_info.ssid_len = pP2PConnect->peer_go_ssid.ssidLength; + } + + /* prevent background scan during WPS */ + A_MEMCPY(&scan_param_cmd, &default_scan_param, sizeof(WMI_SCAN_PARAMS_CMD)); + scan_param_cmd.bg_period = A_CPU2LE16(0xffff); + wmi_cmd_start(pWmi, &scan_param_cmd, WMI_SET_SCAN_PARAMS_CMDID, sizeof(WMI_SCAN_PARAMS_CMD)); + WPS_START.ctl_flag |= 0x1; + wmi_cmd_start(pWmi, &WPS_START, WMI_WPS_START_CMDID, sizeof(WMI_WPS_START_CMD)); + } + break; +#if 0 + case ATH_P2P_INV_CONNECT: + { + pInvitation_connect_param = (WMI_PERSISTENT_MAC_LIST *)param_ptr->data; + + p2p_invite_conn_cmd.ssidLength = strlen(pInvitation_connect_param->ssid); + p2p_invite_conn_cmd.networkType = INFRA_NETWORK; + p2p_invite_conn_cmd.dot11AuthMode = OPEN_AUTH; + p2p_invite_conn_cmd.authMode = WPA2_PSK_AUTH; + p2p_invite_conn_cmd.pairwiseCryptoType = AES_CRYPT; + p2p_invite_conn_cmd.pairwiseCryptoLen = 0; + p2p_invite_conn_cmd.groupCryptoType = AES_CRYPT; + p2p_invite_conn_cmd.groupCryptoLen = 0; + p2p_invite_conn_cmd.channel = 0; + p2p_invite_conn_cmd.ctrl_flags = A_CPU2LE32(DEFAULT_CONNECT_CTRL_FLAGS |CONNECT_DO_WPA_OFFLOAD | CONNECT_IGNORE_WPAx_GROUP_CIPHER); + + if (pInvitation_connect_param->ssid != NULL) { + A_MEMCPY(p2p_invite_conn_cmd.ssid, pInvitation_connect_param->ssid, strlen(pInvitation_connect_param->ssid)); + } + + status = wmi_cmd_start(pDCxt->pWmiCxt, (void*)&p2p_invite_conn_cmd, + WMI_CONNECT_CMDID, sizeof(WMI_CONNECT_CMD)); + + if(status != A_OK){ + break; + } + + } + break; +#endif + case ATH_P2P_JOIN_PROFILE: + { + pP2PConnect = (WMI_P2P_FW_CONNECT_CMD_STRUCT *)param_ptr->data; + A_MEMZERO(&JOIN_CONN_PROF, sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + A_MEMCPY(&JOIN_CONN_PROF, pP2PConnect, sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + wmi_cmd_start(pWmi, &JOIN_CONN_PROF, WMI_P2P_SET_JOIN_PROFILE_CMDID, sizeof(WMI_P2P_FW_CONNECT_CMD_STRUCT)); + } + break; + case ATH_P2P_SWITCH: + { + wmi_cmd_start(pWmi, (WMI_P2P_SET_PROFILE_CMD *)param_ptr->data, WMI_P2P_SET_PROFILE_CMDID, + sizeof(WMI_P2P_SET_PROFILE_CMD)); + GET_DRIVER_COMMON(pCxt)->p2pEvtState = false; + GET_DRIVER_COMMON(pCxt)->p2pevtflag = false; + // TODO: p2p_avail need to set to 0 after p2p off + } + break; +#if 1 + case ATH_P2P_SET_NOA: + { + wmi_p2p_set_noa(pWmi, (WMI_NOA_INFO_STRUCT *)param_ptr->data); + } + break; + case ATH_P2P_SET_OPPPS: + { + wmi_p2p_set_oppps(pWmi, (WMI_OPPPS_INFO_STRUCT *)param_ptr->data); + } + break; + case ATH_P2P_SDPD: + { + wmi_sdpd_send_cmd(pWmi, (WMI_P2P_SDPD_TX_CMD *)param_ptr->data); + } + break; +#endif +#endif + case ATH_ONOFF_GTX: + { + A_MEMZERO(>X_PARAM,sizeof(GTX_PARAM)); + GTX_PARAM.enable = *((uint8_t *)param_ptr->data); + GTX_PARAM.nextProbeCount = 5; // if 5 packets are successfully transmitted reduce the power level + GTX_PARAM.forceBackOff = 0; + if (A_OK != wmi_cmd_start(pWmi, >X_PARAM, WMI_GREENTX_PARAMS_CMDID, sizeof(WMI_GREENTX_PARAMS_CMD))) + { + error = QCA_ERROR; + } + } + break; + + case ATH_ONOFF_LPL: + { + // WMI_LPL_FORCE_ENABLE_CMD lplParams = {0}; + LPL_PARAM.lplPolicy = *((uint8_t *)PTR_LPL); + + if (A_OK != wmi_cmd_start(pWmi, &LPL_PARAM, WMI_LPL_FORCE_ENABLE_CMDID, sizeof(WMI_LPL_FORCE_ENABLE_CMD))) + { + error = QCA_ERROR; + } + } + break; + case ATH_SET_TX_PWR_SCALE: + { + if (A_OK != wmi_cmd_start(pWmi, (WMI_SET_TX_POWER_SCALE_CMD *)param_ptr->data, WMI_SET_TX_POWER_SCALE_CMDID, + sizeof(WMI_SET_TX_POWER_SCALE_CMD))) + { + error = QCA_ERROR; + } + } + break; + case ATH_SET_PROBEREQ_EV_ENABLE: + { + if (A_OK != wmi_cmd_start(pWmi, (WMI_PROBE_REQ_REPORT_CMD_STRUCT *)param_ptr->data, + WMI_WLAN_SET_PROBEREQ_ENABLE_CMDID, sizeof(WMI_PROBE_REQ_REPORT_CMD_STRUCT))) + { + error = QCA_ERROR; + } + } + break; + + case ATH_SET_RATE: + { + if (A_OK != wmi_cmd_start(pWmi, (WMI_BIT_RATE_CMD *)param_ptr->data, WMI_SET_BITRATE_CMDID, + sizeof(WMI_BIT_RATE_CMD))) + { + error = QCA_ERROR; + } + } + break; + case ATH_PROGRAM_MAC_ADDR: + { + if (PTR_MAC_ADDR == NULL) + { + error = QCA_ERROR; + } + else + { +#if DRIVER_CONFIG_PROGRAM_MAC_ADDR + if (A_OK != Api_ProgramMacAddress(pCxt, PTR_MAC_ADDR->addr, param_ptr->length, &PTR_MAC_ADDR->result)) + { + error = QCA_ERROR; + } +#else + PTR_MAC_ADDR->result = ATH_PROGRAM_MAC_RESULT_DRIVER_FAILED; + error = QCA_ERROR; // command not supported by this build +#endif + } + } + break; + + case ATH_GPIO_CMD: + { + if (A_OK != wmi_cmd_start(pWmi, param_ptr->data, WMI_EXTENSION_CMDID, param_ptr->length)) + { + status = A_ERROR; + } + break; + } + + case ATH_PFM_CMD: + pDCxt->pfmDone = false; + + if (A_OK != wmi_cmd_start(pWmi, param_ptr->data, WMI_PFM_GET_CMDID, param_ptr->length)) + { + status = A_ERROR; + } + /* block until data return */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->pfmDone), true, 5000); + break; + case ATH_SET_POWER: + if (A_OK != Api_SetPowerMode(pCxt, (POWER_MODE *)param_ptr->data)) + { + status = A_ERROR; + } + break; + case ATH_DSET_READ_CMD: + if (A_OK != wmi_cmd_start(pWmi, param_ptr->data, WMI_HOST_DSET_LARGE_READ_CMDID, param_ptr->length)) + { + status = A_ERROR; + } + break; + case ATH_DSET_WRITE_CMD: + if (A_OK != wmi_cmd_start(pWmi, param_ptr->data, WMI_HOST_DSET_LARGE_WRITE_CMDID, param_ptr->length)) + { + status = A_ERROR; + } + break; + case ATH_DSET_OP_CMD: + { + struct WMIX_DSET_OP_SET_CMD + { + WMIX_DSET_CMD_HDR cmd; + uint32_t dset_id; + } * pCmd; + HOST_DSET_HANDLE *pDsetHandle; + + pDCxt->dset_op_done = false; + + if (A_OK != wmi_cmd_start(pWmi, param_ptr->data, WMI_DSET_OP_CMDID, param_ptr->length)) + { + error = A_ERROR; + } + + pCmd = (struct WMIX_DSET_OP_SET_CMD *)param_ptr->data; + pDsetHandle = dset_find_handle(pCmd->dset_id); + + //NOTE: coverity fix + if (NULL == pDsetHandle) + { + error = A_ERROR; + } + else if (pDsetHandle->cb == NULL) + { + if (pDCxt->dset_op_done == false) + /* block until data return */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->dset_op_done), true, 5000); + if (pDCxt->dset_op_done == true && pDCxt->setparamStatus == 0) + error = A_OK; + else + error = A_ERROR; + } + else + status = A_PENDING; + } + break; + case ATH_SET_WEPKEY: + /* copy wep keys to driver context for use later during connect */ + if (((PTR_WEP_IN->defKeyIndex - 1) < WMI_MIN_KEY_INDEX) || + ((PTR_WEP_IN->defKeyIndex - 1) > WMI_MAX_KEY_INDEX) || (PTR_WEP_IN->numKeys > WMI_MAX_KEY_INDEX + 1) || + /* user passes in num digits as keyLength */ + ((PTR_WEP_IN->keyLength != WEP_SHORT_KEY * 2) && (PTR_WEP_IN->keyLength != WEP_LONG_KEY * 2) && + /* user passes in num digits as keyLength */ + (PTR_WEP_IN->keyLength != WEP_SHORT_KEY) && (PTR_WEP_IN->keyLength != WEP_LONG_KEY))) + { + return A_ERROR; + } + + pDCxt->conn[devId].wepDefTxKeyIndex = (uint8_t)(PTR_WEP_IN->defKeyIndex - 1); + + for (i = 0; i < PTR_WEP_IN->numKeys; i++) + { + if ((PTR_WEP_IN->keyLength == WEP_SHORT_KEY) || (PTR_WEP_IN->keyLength == WEP_LONG_KEY)) + { + A_MEMCPY(pDCxt->conn[devId].wepKeyList[i].key, PTR_WEP_IN->keys[i], PTR_WEP_IN->keyLength); + pDCxt->conn[devId].wepKeyList[i].keyLen = (uint8_t)PTR_WEP_IN->keyLength; + } + else + { + pDCxt->conn[devId].wepKeyList[i].keyLen = (uint8_t)(PTR_WEP_IN->keyLength >> 1); + A_MEMZERO(pDCxt->conn[devId].wepKeyList[i].key, MAX_WEP_KEY_SZ); + /* convert key data from string to bytes */ + for (ii = 0; ii < PTR_WEP_IN->keyLength; ii++) + { + if ((val = Util_Ascii2Hex(PTR_WEP_IN->keys[i][ii])) == 0xff) + { + return A_ERROR; + } + if ((ii & 1) == 0) + { + val <<= 4; + } + pDCxt->conn[devId].wepKeyList[i].key[ii >> 1] |= val; + } + } + } + break; + case ATH_GET_WEPKEY: + if ((PTR_WEP_IN->defKeyIndex - 1) < 1 || (PTR_WEP_IN->defKeyIndex - 1) > WMI_MAX_KEY_INDEX + 1) + return A_ERROR; + + // NOTE: Change was demanded by Coverity + // 'defKeyIndex' is in range of 'wepKeyList' + if (PTR_WEP_IN->defKeyIndex <= (sizeof(pDCxt->conn[devId].wepKeyList) / sizeof(pDCxt->conn[devId].wepKeyList[0]))) + { + A_WEPKEY_T *conn_key = &pDCxt->conn[devId].wepKeyList[PTR_WEP_IN->defKeyIndex - 1]; + // 'conn_key->keyLen' does not exceed 'keys[0]' + if (sizeof(PTR_WEP_IN->keys[0]) >= conn_key->keyLen) + { + A_MEMCPY(PTR_WEP_IN->keys[0], conn_key->key, conn_key->keyLen); + } + else + { + error = QCA_ERROR; + } + } + else + { + error = QCA_ERROR; + } + + break; + case ATH_SET_WEPINDEX: + { + uint32_t index = *(uint32_t *)PTR_WEP_INDEX; + + if (index < 1 || index > WMI_MAX_KEY_INDEX + 1) + return A_ERROR; + + pDCxt->conn[devId].wepDefTxKeyIndex = (uint8_t)(index - 1); + } + break; + case ATH_GET_WEPINDEX: + *(uint32_t *)PTR_WEP_INDEX = pDCxt->conn[devId].wepDefTxKeyIndex; + break; + case ATH_PROGRAM_COUNTRY_CODE: + if (PTR_COUNTRY_CODE == NULL) + { + error = QCA_ERROR; + } + else + { + if (A_OK != Api_ProgramCountryCode(pCxt, PTR_COUNTRY_CODE->countryCode, param_ptr->length, + &PTR_COUNTRY_CODE->result)) + { + error = QCA_ERROR; + } + QCADRV_PRINTF("the set country code is %c, %c\n", PTR_COUNTRY_CODE->countryCode[0], + PTR_COUNTRY_CODE->countryCode[1]); + } + break; + + case ATH_SET_APPIE: + if (A_OK != wmi_set_appie_cmd(pWmi, (void *)param_ptr->data)) + { + status = A_ERROR; + } + break; + + case ATH_WLAN_WPS_INIT_KEY: + pDCxt->wps_init_key = (boolean)A_ERROR; + if (A_OK == wmi_cmd_start(pWmi, NULL, WMI_WLAN_WPS_INIT_KEY_CMDID, 0)) + { + /* block here until event arrives from wifi device */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->wps_init_key), true, 4000); + } + if (pDCxt->wps_init_key != A_OK){ + error = A_ERROR; + printf("wps init failed\n"); + } + else + { + error = A_OK; + printf("wps init done\n"); + } + break; + + case ATH_HEARTBEAT_CHALLEANGE: + pDCxt->hb_challenge_done = false; + #define HB_MAGIC 0x63825363L + pDCxt->hb_sequence = HB_MAGIC ; + if(A_OK == wmi_cmd_start(pWmi, param_ptr->data, WMI_EXTENSION_CMDID, param_ptr->length)) + { + /* block until data return */ + DRIVER_WAIT_FOR_CONDITION(pCxt, &(pDCxt->hb_challenge_done), true, 5000); + } + if (pDCxt->hb_challenge_done != true) + { + error = A_ERROR; + printf("heart beat challenge failed\n"); + } + else + { + error = A_OK; + printf("heart beat challenge done\n"); + } + break; + + default: + if (ath_custom_mediactl.ath_ioctl_handler_ext != NULL) + { + error = ath_custom_mediactl.ath_ioctl_handler_ext(qca_ptr, param_ptr); + } + else + { + error = QCA_ERROR; + } + break; + } + + return error; +} + +uint32_t Custom_Api_Mediactl(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t command_id, void *inout_param) +{ + uint8_t devId; + uint32_t error = QCA_OK; + void *pCxt, *pWmi; + A_DRIVER_CONTEXT *pDCxt; + QCA_MEDIACTL_PARAM_PTR param_ptr = (QCA_MEDIACTL_PARAM_PTR)inout_param; +#define PTR_DEV_MODE ((uint32_t *)inout_param) +#define PTR_ESSID ((QCA_ESSID *)inout_param) +#define PTR_SECTYPE ((uint32_t *)inout_param) +#define PTR_FREQ (uint32_t *)(param_ptr->data) +#define PTR_RTS ((uint32_t *)inout_param) +#define PTR_PASSPHRASE ((QCA_MEDIACTL_PARAM *)inout_param) +#define PTR_SCAN_OUT ((QCA_SCAN_LIST *)inout_param) +#define PTR_POWER_IN ((QCA_MEDIACTL_PARAM *)inout_param) +#define PTR_POWER_OUT ((QCA_MEDIACTL_PARAM *)inout_param) +#define PTR_ATH_IOCTL ((ATH_IOCTL_PARAM_STRUCT_PTR)inout_param) +#define PTR_START_SCAN ((WMI_START_SCAN_CMD *)inout_param) + + union + { + WMI_SET_PASSPHRASE_CMD passCmd; + WMI_SET_RTS_CMD rtsCmd; + } local; + + if (qca_ptr == NULL) + { + error = QCA_ERROR; + goto MEDIACTL_DONE; + } + /* ATH_CHIP_STATE is a special command to bring + * driver + wifi device + * up or down without officially shutting down the + * driver. This allows a task to shutdown the chip + * but prevents other tasks from having invalid qca_ptr's + */ + if (command_id == QCA_MEDIACTL_VENDOR_SPECIFIC && PTR_ATH_IOCTL->cmd_id == ATH_CHIP_STATE) + { + error = chip_state_ctrl(qca_ptr, *((uint32_t *)PTR_ATH_IOCTL->data)); + + if (error != QCA_OK) + { + config_dump_target_assert_info(qca_ptr->MAC_CONTEXT_PTR); + } + + goto MEDIACTL_DONE; + } + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + error = QCA_ERROR; + goto MEDIACTL_DONE; + } + + pDCxt = GET_DRIVER_COMMON(pCxt); + pWmi = pDCxt->pWmiCxt; + devId = pDCxt->devId; + // devId = qca_ptr->PARAM_PTR->QCA_IF->PHY_NUMBER; + + if (command_id == QCA_MEDIACTL_IS_INITIALIZED) + { + *((uint32_t *)inout_param) = (uint32_t)((pDCxt->wmiReady == true) ? 1 : 0); + goto MEDIACTL_DONE; + } + else if (pDCxt->wmiReady == false && ath_custom_init.skipWmi == 0) + { + /* no other ioctl's allowed until driver is properly initialized */ + error = QCA_ERR_INIT_FAILED; + goto MEDIACTL_DONE; + } + + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return QCA_ERROR; + } + + switch (command_id) + { + case QCA_MEDIACTL_VENDOR_SPECIFIC: + error = ath_ioctl_handler(qca_ptr, PTR_ATH_IOCTL); + break; + case QCA_SET_MEDIACTL_COMMIT: + if (pDCxt->conn[devId].ssidLen == 0) + { + /* a zero length ssid + a COMMIT command is interpreted as a + * request from the caller to disconnect. + */ + Api_DisconnectWiFi(pCxt); + GET_DRIVER_COMMON(pCxt)->securityType = QCA_MEDIACTL_SECURITY_TYPE_NONE; + } + else + { + if (Api_ConnectWiFi(pCxt) != A_OK) + { + error = QCA_ERROR; + } + } + pDCxt->wps_in_progress = false; + break; + case QCA_SET_MEDIACTL_MODE: + switch (*PTR_DEV_MODE) + { + case QCA_MEDIACTL_MODE_INFRA: + pDCxt->conn[devId].networkType = INFRA_NETWORK; + break; + case QCA_MEDIACTL_MODE_ADHOC: + pDCxt->conn[devId].networkType = ADHOC_NETWORK; + break; +#if ENABLE_AP_MODE + case QCA_MEDIACTL_MODE_MASTER: + pDCxt->conn[devId].networkType = AP_NETWORK; + break; +#endif + default: + error = QCA_ERR_INVALID_INIT_PARAM; + break; + } + break; + case QCA_SET_MEDIACTL_ESSID: + if (PTR_ESSID->length < 33) + { + pDCxt->conn[devId].ssidLen = (int32_t)PTR_ESSID->length; + if (pDCxt->conn[devId].ssidLen) + { + A_MEMCPY(pDCxt->conn[devId].ssid, PTR_ESSID->essid, (uint32_t)pDCxt->conn[devId].ssidLen); + } + else + { + // clear ssid; this is the first step to disconnect + A_MEMZERO(pDCxt->conn[devId].ssid, 32); + } + } + else + { + error = QCA_ERR_INVALID_INIT_PARAM; + } + + break; + case QCA_SET_MEDIACTL_SEC_TYPE: + GET_DRIVER_COMMON(pCxt)->securityType = (uint8_t)(*PTR_SECTYPE); + switch (*PTR_SECTYPE) + { + case QCA_MEDIACTL_SECURITY_TYPE_NONE: + pDCxt->conn[devId].wpaAuthMode = NONE_AUTH; + pDCxt->conn[devId].wpaPairwiseCrypto = NONE_CRYPT; + pDCxt->conn[devId].wpaGroupCrypto = NONE_CRYPT; + pDCxt->conn[devId].dot11AuthMode = OPEN_AUTH; + pDCxt->conn[devId].connectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD; + break; + case QCA_MEDIACTL_SECURITY_TYPE_WEP: + pDCxt->conn[devId].wpaAuthMode = NONE_AUTH; + pDCxt->conn[devId].wpaPairwiseCrypto = WEP_CRYPT; + pDCxt->conn[devId].wpaGroupCrypto = WEP_CRYPT; + /* allow either form of auth for WEP */ + pDCxt->conn[devId].dot11AuthMode = (OPEN_AUTH | SHARED_AUTH); + pDCxt->conn[devId].connectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD; + break; + case QCA_MEDIACTL_SECURITY_TYPE_WPA: + /* FIXME: need t allow WPA with AES */ + pDCxt->conn[devId].wpaAuthMode = WPA_PSK_AUTH; + pDCxt->conn[devId].dot11AuthMode = OPEN_AUTH; + /* by ignoring the group cipher the wifi can connect to mixed mode AP's */ + pDCxt->conn[devId].connectCtrlFlags |= CONNECT_DO_WPA_OFFLOAD | CONNECT_IGNORE_WPAx_GROUP_CIPHER; + break; + case QCA_MEDIACTL_SECURITY_TYPE_WPA2: + /* FIXME: need to allow WPA2 with TKIP */ + pDCxt->conn[devId].wpaAuthMode = WPA2_PSK_AUTH; + pDCxt->conn[devId].dot11AuthMode = OPEN_AUTH; + /* by ignoring the group cipher the wifi can connect to mixed mode AP's */ + pDCxt->conn[devId].connectCtrlFlags |= CONNECT_DO_WPA_OFFLOAD | CONNECT_IGNORE_WPAx_GROUP_CIPHER; + break; + default: + error = QCA_ERR_INVALID_INIT_PARAM; + break; + } + break; + case QCA_SET_MEDIACTL_FREQ: + /* Normally only used for starting a new Ad-hoc network */ + /* In Infrastructure mode the wifi device will scan for the + * SSID on allowed channels. */ + /* arChannelHint is used in connect command to wifi device */ + if (ATH_IOCTL_FREQ_1 <= *PTR_FREQ && ATH_IOCTL_FREQ_14 >= *PTR_FREQ) + { + pDCxt->conn[devId].channelHint = (uint16_t)(*PTR_FREQ); + } + else + { + error = QCA_ERR_INVALID_INIT_PARAM; + } + break; + case QCA_SET_MEDIACTL_RTS: + local.rtsCmd.threshold = A_CPU2LE16((uint16_t)(*PTR_RTS)); + if (A_OK != wmi_cmd_start(pWmi, &local.rtsCmd, WMI_SET_RTS_CMDID, sizeof(WMI_SET_RTS_CMD))) + { + error = QCA_ERROR; + } + break; + case QCA_SET_MEDIACTL_PASSPHRASE: + /* must have already set SSID prior to this call */ + if (PTR_PASSPHRASE->length > WMI_PASSPHRASE_LEN) + { + error = QCA_ERR_INVALID_INIT_PARAM; + } + else if (pDCxt->conn[devId].ssidLen == 0) + { + error = QCA_ERR_INIT_FAILED; + } + else + { + local.passCmd.ssid_len = (uint8_t)pDCxt->conn[devId].ssidLen; + A_MEMCPY(local.passCmd.ssid, pDCxt->conn[devId].ssid, (uint32_t)pDCxt->conn[devId].ssidLen); + local.passCmd.passphrase_len = (uint8_t)PTR_PASSPHRASE->length; + A_MEMCPY(local.passCmd.passphrase, PTR_PASSPHRASE->data, local.passCmd.passphrase_len); + + if (A_OK != + wmi_cmd_start(pWmi, &local.passCmd, WMI_SET_PASSPHRASE_CMDID, sizeof(WMI_SET_PASSPHRASE_CMD))) + { + error = QCA_ERROR; + } + } + break; + case QCA_SET_MEDIACTL_SCAN: + GET_DRIVER_COMMON(pCxt)->extended_scan = 0; + error = scan_setup(pCxt, pWmi, PTR_START_SCAN); + break; + case QCA_SET_MEDIACTL_POWER: + /* atheros wifi allows for 2 power modes; + * 1) MAX_PERF - the radio is always on either transmitting, receiving or listening + * 2) REC_MODE - the wifi device will according to its built in rules enter/exit sleep + * mode with the Access point. + */ + if (PTR_POWER_IN->value) + { + /* a non-zero value implies REC_MODE */ + pDCxt->userPwrMode = REC_POWER; + } + else + { + pDCxt->userPwrMode = MAX_PERF_POWER; + } + + wmi_cmd_start(pWmi, &pDCxt->userPwrMode, WMI_SET_POWER_MODE_CMDID, sizeof(WMI_POWER_MODE_CMD)); + break; + case QCA_GET_MEDIACTL_POWER: + if (pDCxt->userPwrMode == REC_POWER) + { + PTR_POWER_OUT->value = 1; + } + else + { + PTR_POWER_OUT->value = 0; + } + + break; + case QCA_GET_MEDIACTL_SCAN: + wait_scan_done(pCxt, pWmi); + PTR_SCAN_OUT->scan_info_list = (QCA_SCAN_INFO *)GET_DRIVER_COMMON(pCxt)->pScanOut; + PTR_SCAN_OUT->num_scan_entries = GET_DRIVER_COMMON(pCxt)->scanOutCount; + break; + case QCA_GET_MEDIACTL_ESSID: + ((QCA_MEDIACTL_PARAM *)inout_param)->length = (uint32_t)pDCxt->conn[devId].ssidLen; + A_MEMCPY(((QCA_MEDIACTL_PARAM *)inout_param)->data, pDCxt->conn[devId].ssid, + (uint32_t)pDCxt->conn[devId].ssidLen + 1); + break; + case QCA_GET_MEDIACTL_SEC_TYPE: + *((uint32_t *)inout_param) = GET_DRIVER_COMMON(pCxt)->securityType; + break; + case QCA_GET_MEDIACTL_MODE: + *((uint32_t *)inout_param) = (uint32_t)pDCxt->conn[devId].networkType; + switch (pDCxt->conn[devId].networkType) + { + case INFRA_NETWORK: + *((uint32_t *)inout_param) = QCA_MEDIACTL_MODE_INFRA; + break; + case ADHOC_NETWORK: + *((uint32_t *)inout_param) = QCA_MEDIACTL_MODE_ADHOC; + break; +#if ENABLE_AP_MODE + case AP_NETWORK: + *((uint32_t *)inout_param) = QCA_MEDIACTL_MODE_MASTER; + break; +#endif + default: + error = QCA_ERR_INVALID_INIT_PARAM; + break; + } + break; +#if 0 /* currently unsupported MEDIACTLS */ + case QCA_SET_MEDIACTL_ENCODE: + error = + break; + case QCA_GET_MEDIACTL_PASSPHRASE: + error = + break; + case QCA_GET_MEDIACTL_NAME: + error = + break; + case QCA_GET_MEDIACTL_FREQ: + error = + break; + case QCA_GET_MEDIACTL_RANGE: + break; + case QCA_GET_MEDIACTL_WAP: + break; + case QCA_GET_MEDIACTL_RATE: + error = + break; + case QCA_GET_MEDIACTL_RTS: + error = + break; + case QCA_GET_MEDIACTL_RETRY: + error = + break; +#endif + default: + QCADRV_PRINTF("Atheros ERROR: mediactl command not valid. command_id=0x%x\n", command_id); + error = QCA_ERROR; + break; + // while(1){}; + } /* Swtich*/ + +MEDIACTL_DONE: + + return error; +} + +/* EOF */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_txrx.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_txrx.c new file mode 100644 index 00000000000..cf3929e205b --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_txrx.c @@ -0,0 +1,173 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include + +#if (!ENABLE_STACK_OFFLOAD) + +uint32_t Custom_Api_Send( + QCA_CONTEXT_STRUCT_PTR qca_ptr, PCB_PTR pcb_ptr, uint32_t size, uint32_t frags, uint32_t flags); + +/*****************************************************************************/ +/* Custom_DeliverFrameToNetworkStack - Called by API_RxComplete to + * deliver a data frame to the network stack. This code will perform + * platform specific operations. + * void *pCxt - the driver context. + * void *pReq - the packet. + *****************************************************************************/ +void Custom_DeliverFrameToNetworkStack(void *pCxt, void *pReq) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)pReq; + QCA_CONTEXT_STRUCT_PTR qca_ptr = (QCA_CONTEXT_STRUCT_PTR)GET_DRIVER_CXT(pCxt)->pUpperCxt[0]; + QCA_ECB_STRUCT_PTR RxECB; + uint32_t len; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + ATH_PROMISCUOUS_CB prom_cb = (ATH_PROMISCUOUS_CB)(GET_DRIVER_CXT(pCxt)->promiscuous_cb); + + if (a_netbuf_ptr) + { + len = A_NETBUF_LEN(pReq); + _DCACHE_INVALIDATE_MBYTES(A_NETBUF_DATA(pReq), len); + + if (pDCxt->promiscuous_mode) + { + if (prom_cb) + { + /* send frame to callback function rather than an QCA_receiver */ + a_netbuf_ptr->native.FRAG[0].LENGTH = len; + a_netbuf_ptr->native.FRAG[0].FRAGMENT = A_NETBUF_DATA(pReq); + prom_cb((void *)&(a_netbuf_ptr->native)); + } + else + { + A_NETBUF_FREE(pReq); + } + } + else if ((RxECB = QCA_find_receiver(qca_ptr, (QCA_HEADER_PTR)A_NETBUF_DATA(pReq), &len)) != NULL) + { + // Call the receiver's service function to pass the PCB to the receiver + a_netbuf_ptr->native.FRAG[0].LENGTH = len; + a_netbuf_ptr->native.FRAG[0].FRAGMENT = A_NETBUF_DATA(pReq); + RxECB->SERVICE((PCB_PTR) & (a_netbuf_ptr->native), RxECB->PRIVATE); + } + else + { + /* failed to find a receiver for this data packet. */ + A_NETBUF_FREE(pReq); + } + } +} + +/*****************************************************************************/ +/* Custom_Api_Send - Entry point for MQX driver interface to send a packet. + * This is specific to MQX. This function is NOT called from within the + * driver. + * QCA_CONTEXT_STRUCT_PTR qca_ptr - the MQX driver context. + * PCB_PTR pcb_ptr - the MQX packet object. + * uint32_t size - the length in bytes of pcb_ptr. + * uint32_t frags - the number of fragments in pcb_ptr. + * uint32_t flags - optional flags for transmit. + *****************************************************************************/ +uint32_t Custom_Api_Send(QCA_CONTEXT_STRUCT_PTR qca_ptr, + /* [IN] the Ethernet state structure */ + PCB_PTR pcb_ptr, + /* [IN] the packet to send */ + uint32_t size, + /* [IN] total size of the packet */ + uint32_t frags, + /* [IN] total fragments in the packet */ + uint32_t flags + /* [IN] optional flags, zero = default */ + ) +{ + uint32_t error = QCA_OK; + A_NETBUF *a_netbuf_ptr; + UNUSED_ARGUMENT(flags); + UNUSED_ARGUMENT(size); +#if 0 +if(g_sampleTotAlloc != g_totAlloc){ + A_PRINTF("send alloc: %d\n", g_totAlloc); + g_sampleTotAlloc = g_totAlloc; +} +#endif + /* create an atheros pcb and continue or fail. */ + do + { + /* provide enough space in the top buffer to store the 14 byte + * header which will be copied from its position in the original + * buffer. this will allow wmi_dix_2_dot3() to function properly. + */ + if ((a_netbuf_ptr = (A_NETBUF *)A_NETBUF_ALLOC(sizeof(ATH_MAC_HDR))) == NULL) + { + error = ENETERR_ALLOC_PCB; + break; + } + + a_netbuf_ptr->num_frags = (uint8_t)frags; + /* HACK: copy the first part of the fragment to the new buf in order to allow + * wmi_dix_2_dot3() to function properly. */ + A_ASSERT(pcb_ptr->FRAG[0].LENGTH >= sizeof(ATH_MAC_HDR)); + A_NETBUF_PUT_DATA(a_netbuf_ptr, (uint8_t *)pcb_ptr->FRAG[0].FRAGMENT, sizeof(ATH_MAC_HDR)); + /*(char*)pcb_ptr->FRAG[0].FRAGMENT += sizeof(ATH_MAC_HDR);*/ + pcb_ptr->FRAG[0].FRAGMENT = (uint8_t *)((uint32_t)pcb_ptr->FRAG[0].FRAGMENT + sizeof(ATH_MAC_HDR)); + pcb_ptr->FRAG[0].LENGTH -= sizeof(ATH_MAC_HDR); + + // ensure there is enough headroom to complete the tx operation + if (A_NETBUF_HEADROOM(a_netbuf_ptr) < + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HDR_LENGTH + WMI_MAX_TX_META_SZ) + { + error = ENETERR_ALLOC_PCB; + break; + } + // carry the original around until completion. + // it is freed by A_NETBUF_FREE + a_netbuf_ptr->native_orig = pcb_ptr; + + if (A_OK != Api_DataTxStart((void *)qca_ptr->MAC_CONTEXT_PTR, (void *)a_netbuf_ptr)) + { + error = QCA_ERROR; + break; + } + + } while (0); + + if (error != QCA_OK) + { + /* in the event of api failure, the original pcb should be returned to the caller un-touched + * and the a_netbuf_ptr should be freed */ + a_netbuf_ptr->native_orig = NULL; + A_NETBUF_FREE((void *)a_netbuf_ptr); + } + + return error; +} + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_wmi_rx.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_wmi_rx.c new file mode 100644 index 00000000000..290aafabc11 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/api_interface/cust_api_wmi_rx.c @@ -0,0 +1,481 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include + +//TODO: mixin different layers, need to fix +// introduced by on_connect events enum +// need to specify connections between layers +#include "qcom_api.h" + +#if ENABLE_P2P_MODE +#include "p2p.h" +#include "wmi.h" +#include "wmi_api.h" +#include "wmi_host.h" +#endif + +#include +#include +#if ENABLE_P2P_MODE +extern const WMI_SCAN_PARAMS_CMD default_scan_param; +extern const uint8_t max_performance_power_param; +#endif +static void fill_scan_info(void *pCxt, QCA_SCAN_INFO *pScanInfo, WMI_BSS_INFO_HDR *bih, int32_t len) +{ + A_SCAN_SUMMARY scan_summary; + + if (A_OK == Api_ParseInfoElem(pCxt, bih, len, &scan_summary)) + { + pScanInfo->channel = scan_summary.channel; + pScanInfo->rssi = scan_summary.rssi; + A_MEMCPY(pScanInfo->bssid, scan_summary.bssid, ATH_MAC_LEN); + pScanInfo->ssid_len = scan_summary.ssid_len; + + A_MEMCPY(pScanInfo->ssid, &(scan_summary.ssid[0]), scan_summary.ssid_len); + pScanInfo->security_enabled = (uint8_t)((scan_summary.caps & IEEE80211_CAPINFO_PRIVACY) ? 1 : 0); + pScanInfo->preamble = (uint8_t)((scan_summary.caps & IEEE80211_CAPINFO_SHORT_PREAMBLE) ? 1 : 0); + + if ((scan_summary.caps & (IEEE80211_CAPINFO_ESS | IEEE80211_CAPINFO_IBSS)) == IEEE80211_CAPINFO_ESS) + { + pScanInfo->bss_type = QCA_MEDIACTL_MODE_INFRA; + } + else if ((scan_summary.caps & (IEEE80211_CAPINFO_ESS | IEEE80211_CAPINFO_IBSS)) == IEEE80211_CAPINFO_IBSS) + { + pScanInfo->bss_type = QCA_MEDIACTL_MODE_ADHOC; + } + else + { + /* error condition report it as ad-hoc in this case*/ + pScanInfo->bss_type = QCA_MEDIACTL_MODE_ADHOC; + } + + pScanInfo->beacon_period = scan_summary.beacon_period; + + if (scan_summary.rsn_cipher & TKIP_CRYPT) + { + pScanInfo->rsn_cipher |= ATH_CIPHER_TYPE_TKIP; + } + + if (scan_summary.rsn_cipher & AES_CRYPT) + { + pScanInfo->rsn_cipher |= ATH_CIPHER_TYPE_CCMP; + } + + if (scan_summary.rsn_cipher & WEP_CRYPT) + { + pScanInfo->rsn_cipher |= ATH_CIPHER_TYPE_WEP; + } + + if (scan_summary.wpa_cipher & TKIP_CRYPT) + { + pScanInfo->wpa_cipher |= ATH_CIPHER_TYPE_TKIP; + } + + if (scan_summary.wpa_cipher & AES_CRYPT) + { + pScanInfo->wpa_cipher |= ATH_CIPHER_TYPE_CCMP; + } + + if (scan_summary.wpa_cipher & WEP_CRYPT) + { + pScanInfo->wpa_cipher |= ATH_CIPHER_TYPE_WEP; + } + + if (scan_summary.rsn_auth & WPA2_AUTH) + { + pScanInfo->rsn_auth |= SECURITY_AUTH_1X; + } + + if (scan_summary.rsn_auth & WPA2_PSK_AUTH) + { + pScanInfo->rsn_auth |= SECURITY_AUTH_PSK; + } + + if (scan_summary.wpa_auth & WPA_AUTH) + { + pScanInfo->wpa_auth |= SECURITY_AUTH_1X; + } + + if (scan_summary.wpa_auth & WPA_PSK_AUTH) + { + pScanInfo->wpa_auth |= SECURITY_AUTH_PSK; + } + } +} + +static void fill_ext_scan_info(void *pCxt, ATH_SCAN_EXT *pExtScanInfo, WMI_BSS_INFO_HDR *bih, int32_t len) +{ + A_SCAN_SUMMARY scan_summary; + + if (A_OK == Api_ParseInfoElem(pCxt, bih, len, &scan_summary)) + { + A_MEMZERO(pExtScanInfo, sizeof(ATH_SCAN_EXT)); + pExtScanInfo->channel = scan_summary.channel; + pExtScanInfo->rssi = scan_summary.rssi; + A_MEMCPY(pExtScanInfo->bssid, scan_summary.bssid, ATH_MAC_LEN); + pExtScanInfo->ssid_len = scan_summary.ssid_len; + + A_MEMCPY(pExtScanInfo->ssid, &(scan_summary.ssid[0]), scan_summary.ssid_len); + pExtScanInfo->security_enabled = (uint8_t)((scan_summary.caps & IEEE80211_CAPINFO_PRIVACY) ? 1 : 0); + pExtScanInfo->preamble = (uint8_t)((scan_summary.caps & IEEE80211_CAPINFO_SHORT_PREAMBLE) ? 1 : 0); + + if ((scan_summary.caps & (IEEE80211_CAPINFO_ESS | IEEE80211_CAPINFO_IBSS)) == IEEE80211_CAPINFO_ESS) + { + pExtScanInfo->bss_type = QCA_MEDIACTL_MODE_INFRA; + } + else if ((scan_summary.caps & (IEEE80211_CAPINFO_ESS | IEEE80211_CAPINFO_IBSS)) == IEEE80211_CAPINFO_IBSS) + { + pExtScanInfo->bss_type = QCA_MEDIACTL_MODE_ADHOC; + } + else + { + /* error condition report it as ad-hoc in this case*/ + pExtScanInfo->bss_type = QCA_MEDIACTL_MODE_ADHOC; + } + + pExtScanInfo->beacon_period = scan_summary.beacon_period; + + if (scan_summary.rsn_cipher & TKIP_CRYPT) + { + pExtScanInfo->rsn_cipher |= ATH_CIPHER_TYPE_TKIP; + } + + if (scan_summary.rsn_cipher & AES_CRYPT) + { + pExtScanInfo->rsn_cipher |= ATH_CIPHER_TYPE_CCMP; + } + + if (scan_summary.rsn_cipher & WEP_CRYPT) + { + pExtScanInfo->rsn_cipher |= ATH_CIPHER_TYPE_WEP; + } + + if (scan_summary.wpa_cipher & TKIP_CRYPT) + { + pExtScanInfo->wpa_cipher |= ATH_CIPHER_TYPE_TKIP; + } + + if (scan_summary.wpa_cipher & AES_CRYPT) + { + pExtScanInfo->wpa_cipher |= ATH_CIPHER_TYPE_CCMP; + } + + if (scan_summary.wpa_cipher & WEP_CRYPT) + { + pExtScanInfo->wpa_cipher |= ATH_CIPHER_TYPE_WEP; + } + + if (scan_summary.rsn_auth & WPA2_AUTH) + { + pExtScanInfo->rsn_auth |= SECURITY_AUTH_1X; + } + + if (scan_summary.rsn_auth & WPA2_PSK_AUTH) + { + pExtScanInfo->rsn_auth |= SECURITY_AUTH_PSK; + } + + if (scan_summary.wpa_auth & WPA_AUTH) + { + pExtScanInfo->wpa_auth |= SECURITY_AUTH_1X; + } + + if (scan_summary.wpa_auth & WPA_PSK_AUTH) + { + pExtScanInfo->wpa_auth |= SECURITY_AUTH_PSK; + } + } +} + +void Custom_Api_BssInfoEvent(void *pCxt, uint8_t *datap, int32_t len) +{ + WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap; + QCA_SCAN_INFO_PTR pScanInfo; + ATH_SCAN_EXT *pExtScanInfo; + uint16_t i; + uint8_t worst_snr_idx = 0; + uint8_t worst_snr = 0xff; + uint16_t scanCount; + + /* add/replace entry in application scan results */ + if (GET_DRIVER_COMMON(pCxt)->extended_scan) + { + pExtScanInfo = (ATH_SCAN_EXT *)(GET_DRIVER_COMMON(pCxt)->pScanOut); + scanCount = GET_DRIVER_COMMON(pCxt)->scanOutCount; + // look for previous match + for (i = 0; i < scanCount; i++) + { + if (0 == A_MEMCMP(bih->bssid, pExtScanInfo[i].bssid, ATH_MAC_LEN)) + { + fill_ext_scan_info(pCxt, &pExtScanInfo[i], bih, len); + break; + } + /* keep worst rssi entry for optional use below */ + if (worst_snr > pExtScanInfo[i].rssi) + { + worst_snr = pExtScanInfo[i].rssi; + worst_snr_idx = i; + } + } + + if (i >= scanCount) + { + if (GET_DRIVER_COMMON(pCxt)->scanOutSize <= scanCount) + { + /* replace other non-matching entry based on rssi */ + if (bih->snr > worst_snr) + { + fill_ext_scan_info(pCxt, &pExtScanInfo[worst_snr_idx], bih, len); + } + } + else + { + /* populate new entry */ + fill_ext_scan_info(pCxt, &pExtScanInfo[scanCount], bih, len); + scanCount++; + GET_DRIVER_COMMON(pCxt)->scanOutCount = scanCount; + } + } + } + else + { + pScanInfo = (QCA_SCAN_INFO_PTR)(GET_DRIVER_COMMON(pCxt)->pScanOut); + scanCount = GET_DRIVER_COMMON(pCxt)->scanOutCount; + // look for previous match + for (i = 0; i < scanCount; i++) + { + if (0 == A_MEMCMP(bih->bssid, pScanInfo[i].bssid, ATH_MAC_LEN)) + { + fill_scan_info(pCxt, &pScanInfo[i], bih, len); + break; + } + /* keep worst rssi entry for optional use below */ + if (worst_snr > pScanInfo[i].rssi) + { + worst_snr = pScanInfo[i].rssi; + worst_snr_idx = i; + } + } + + if (i >= scanCount) + { + if (GET_DRIVER_COMMON(pCxt)->scanOutSize <= scanCount) + { + /* replace other non-matching entry based on rssi */ + if (bih->snr > worst_snr) + { + fill_scan_info(pCxt, &pScanInfo[worst_snr_idx], bih, len); + } + } + else + { + /* populate new entry */ + fill_scan_info(pCxt, &pScanInfo[scanCount], bih, len); + scanCount++; + GET_DRIVER_COMMON(pCxt)->scanOutCount = scanCount; + } + } + } +} + +void Custom_Api_ConnectEvent(void *pCxt, uint8_t devId, uint16_t channel, uint8_t *bssid) +{ + ATH_CONNECT_CB cb = NULL; + boolean bssConn = false; + + /* Update connect & link status atomically */ + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + if (GET_DRIVER_CXT(pCxt)->connectStateCB != NULL) + { + cb = (ATH_CONNECT_CB)GET_DRIVER_CXT(pCxt)->connectStateCB; + /* call this later from outside the spinlock */ + } + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + DRIVER_WAKE_USER(pCxt); + QCA_CONTEXT_STRUCT_PTR qca_ptr = (QCA_CONTEXT_STRUCT_PTR)GET_DRIVER_CXT(pCxt)->pUpperCxt[devId]; + bssConn = !A_MEMCMP(qca_ptr->ADDRESS, bssid, ATH_MAC_LEN); + + /* call the callback function provided by application to + * indicate connection state */ + if (cb != NULL) + { + cb(QCOM_ONCONNECT_EVENT_SUCCESS, devId, bssid, bssConn); + } +} + +void Custom_Api_DisconnectEvent(void *pCxt, + uint8_t devId, + uint8_t reason, + uint8_t *bssid, + uint8_t assocRespLen, + uint8_t *assocInfo, + uint16_t protocolReasonStatus) +{ + ATH_CONNECT_CB cb = NULL; + boolean bssConn = false; + uint8_t bssMac[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + /* Update connect & link status atomically */ + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + if (GET_DRIVER_CXT(pCxt)->connectStateCB != NULL) + { + cb = (ATH_CONNECT_CB)GET_DRIVER_CXT(pCxt)->connectStateCB; + /* call this later from outside the spinlock */ + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + /* call the callback function provided by application to + * indicate connection state */ + if (cb != NULL) + { + QCA_CONTEXT_STRUCT_PTR qca_ptr = (QCA_CONTEXT_STRUCT_PTR)GET_DRIVER_CXT(pCxt)->pUpperCxt[devId]; + bssConn = !A_MEMCMP(qca_ptr->ADDRESS, bssid, ATH_MAC_LEN); + bssConn = !A_MEMCMP(bssMac, bssid, ATH_MAC_LEN); + + if (reason == INVALID_PROFILE) + { + cb(INVALID_PROFILE, devId, bssid, bssConn); + } + else + { + cb(QCOM_ONCONNECT_EVENT_DISCONNECT, devId, bssid, bssConn); + } + } +} + +void Custom_Api_ReadyEvent(void *pCxt, uint8_t *datap, uint8_t phyCap, uint32_t sw_ver, uint32_t abi_ver) +{ + QCA_CONTEXT_STRUCT_PTR qca_ptr = (QCA_CONTEXT_STRUCT_PTR)GET_DRIVER_CXT(pCxt)->pUpperCxt[0]; + /* this custom implementation sets an event after setting CXT_WMI_READY + * so as to allow the blocked user thread to wake up. */ + A_MEMCPY(qca_ptr->ADDRESS, datap, ATH_MAC_LEN); + DRIVER_WAKE_USER(pCxt); + UNUSED_ARGUMENT(phyCap); + UNUSED_ARGUMENT(sw_ver); + UNUSED_ARGUMENT(abi_ver); +} + +void Custom_Api_GpioDataEvent(void *wmip, uint8_t *datap, int32_t len) +{ + if (ath_custom_init.Api_GpioDataEventRx != NULL) + { + ath_custom_init.Api_GpioDataEventRx(datap, len); + } +} + +void Custom_Api_PfmDataEvent(void *wmip, uint8_t *datap, int32_t len) +{ + if (ath_custom_init.Custom_Api_PfmDataEventRx != NULL) + { + ath_custom_init.Custom_Api_PfmDataEventRx(datap, len); + } +} + +void Custom_Api_PfmDataDoneEvent(void *wmip, uint8_t *datap, int32_t len) +{ + if (ath_custom_init.Custom_Api_PfmDataDoneEventRx != NULL) + { + ath_custom_init.Custom_Api_PfmDataDoneEventRx(((struct wmi_t *)wmip)->wmi_devt, datap, len); + } +} + +void Custom_Api_RSNASuccessEvent(void *pCxt, uint8_t devId, uint8_t code) +{ + ATH_CONNECT_CB cb = NULL; + /* this is the event that the customer has to use to send a callback + * to the application so that it will print the success event */ + + /* get the callback handler from the device context */ + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + if (GET_DRIVER_CXT(pCxt)->connectStateCB != NULL) + { + cb = (ATH_CONNECT_CB)GET_DRIVER_CXT(pCxt)->connectStateCB; + /* call this later from outside the spinlock */ + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + /* call the callback function provided by application to + * indicate 4 way handshake status */ + if (cb != NULL) + { + cb(code, devId, NULL, false); + } +} + +void Custom_Api_BitRateEvent_tx(void *pCxt, uint8_t devId, int8_t rateIndex) +{ + ATH_CONNECT_CB cb = NULL; + /* the driver will get the index of the last tx rate from chip + * based on this index we get the rate tx from the array */ + + /* get the callback handler from the device context */ + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + if (GET_DRIVER_CXT(pCxt)->connectStateCB != NULL) + { + cb = (ATH_CONNECT_CB)GET_DRIVER_CXT(pCxt)->connectStateCB; + /* call this later from outside the spinlock */ + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + /* call the callback function provided by application to + * indicate last transmitted rate */ + + if (cb != NULL) + { + cb(wmi_rateTable[rateIndex][0], devId, NULL, false); + } +} + +void Custom_Api_ProbeReq_Event(void *pCxt, uint8_t *datap, uint32_t len) +{ + ATH_PROBEREQ_CB cb = NULL; + WMI_P2P_RX_PROBE_REQ_EVENT_STRUCT *buf = (WMI_P2P_RX_PROBE_REQ_EVENT_STRUCT *)datap; + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + { + if (GET_DRIVER_CXT(pCxt)->probeReqCB != NULL) + { + cb = (ATH_PROBEREQ_CB)GET_DRIVER_CXT(pCxt)->probeReqCB; + /* call this later from outside the spinlock */ + } + } + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + /* call the callback function provided by application to + * indicate Probe request message to the application */ + if (cb != NULL) + { + cb(buf->data, buf->len, buf->freq); + } +} + +/* EOF */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/driver/cust_driver_main.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/driver/cust_driver_main.c new file mode 100644 index 00000000000..f7e46095d23 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/driver/cust_driver_main.c @@ -0,0 +1,216 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include + +#include +#include +#include + +#include "atheros_wifi.h" +#include "atheros_wifi_api.h" +#include "atheros_wifi_internal.h" + +ATH_CUSTOM_INIT_T ath_custom_init = { + NULL, NULL, NULL, NULL, NULL, NULL, NULL, false, false, +}; + +ATH_CUSTOM_MEDIACTL_T ath_custom_mediactl = {NULL}; + +ATH_CUSTOM_HTC_T ath_custom_htc = {NULL, NULL}; + +static void Custom_FreeRxRequest(A_NATIVE_NETBUF *native_ptr) +{ +#if (!ENABLE_STACK_OFFLOAD) + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)native_ptr; +#if DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE + A_CUSTOM_DRIVER_CONTEXT *pCxt = (A_CUSTOM_DRIVER_CONTEXT *)a_netbuf_ptr->native.PRIVATE; + + if (_mem_get_type(a_netbuf_ptr) == MEM_TYPE_ATHEROS_PERSIST_RX_PCB) + { + RXBUFFER_ACCESS_ACQUIRE((void *)pCxt); + A_NETBUF_ENQUEUE(&(GET_DRIVER_COMMON(pCxt)->rxFreeQueue), a_netbuf_ptr); + Driver_ReportRxBuffStatus((void *)pCxt, true); + RXBUFFER_ACCESS_RELEASE((void *)pCxt); + } + else + { + A_ASSERT(0); + } +#else + default_native_free_fn((PCB_PTR)a_netbuf_ptr); +#endif +#endif +} + +/*****************************************************************************/ +/* Custom_GetRxRequest - Attempts to get an RX Buffer + RX Request object + * for a pending RX packet. If an Rx Request cannot be acquired then this + * function calls Driver_ReportRxBuffStatus(pCxt, false) to prevent the + * driver from repeating the request until a buffer becomes available. + * void *pCxt - the driver context. + * uint16_t length - length of request in bytes. + *****************************************************************************/ +void *Custom_GetRxRequest(void *pCxt, uint16_t length) +{ + void *pReq; + + do + { + RXBUFFER_ACCESS_ACQUIRE(pCxt); + { +#if DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE + pReq = A_NETBUF_DEQUEUE(&(GET_DRIVER_COMMON(pCxt)->rxFreeQueue)); + + if (A_NETBUF_QUEUE_EMPTY(&(GET_DRIVER_COMMON(pCxt)->rxFreeQueue))) + { + Driver_ReportRxBuffStatus(pCxt, false); + } +#else + pReq = A_NETBUF_ALLOC(length); + if (pReq == NULL) + { + Driver_ReportRxBuffStatus(pCxt, false); + } +#endif + } + RXBUFFER_ACCESS_RELEASE(pCxt); + + if (pReq != NULL) + { + /* init pcb */ + A_NETBUF_INIT(pReq, (void *)Custom_FreeRxRequest, pCxt); + A_ASSERT(length <= A_NETBUF_TAILROOM(pReq)); + } + else + { + // should never happen thanks to HW_ReportRxBuffStatus + A_ASSERT(0); + } + } while (0); + + return pReq; +} + +/*****************************************************************************/ +/* Custom_Driver_ContextDeInit - Frees any allocations performed by + * Custom_Driver_ContextInit. + * void *pCxt - the driver context. + *****************************************************************************/ +void Custom_Driver_ContextDeInit(void *pCxt) +{ + void *pReq; + + while (GET_DRIVER_COMMON(pCxt)->rxBufferStatus == true) + { + pReq = Custom_GetRxRequest(pCxt, 10); + /* call default free function */ + default_native_free_fn((PCB_PTR)pReq); + } + + if (GET_DRIVER_COMMON(pCxt)->tempStorage != NULL) + { + A_FREE(GET_DRIVER_COMMON(pCxt)->tempStorage, 0); + GET_DRIVER_COMMON(pCxt)->tempStorage = NULL; + } +} + +/*****************************************************************************/ +/* Custom_Driver_ContextInit - Allocates and initializes driver context + * elements including pre-allocated rx buffers. This function will call + * A_ASSERT for any failure. Look to Custom_Driver_ContextDeInit to undo + * any allocations performed by this function. + * void *pCxt - the driver context. + *****************************************************************************/ +A_STATUS +Custom_Driver_ContextInit(void *pCxt) +{ + uint32_t tempStorageLen = 0; + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); + + /*Allocate the temporary storage buffer. This may be shared by multiple modules. + If store recall is enabled, it may use this buffer for storing target data. + Will also be shared by scan module to store scan results*/ + tempStorageLen = max((STORE_RECALL_BUF_SIZE), (ATH_MAX_SCAN_BUFFERS * sizeof(QCA_SCAN_INFO))); + tempStorageLen = max(tempStorageLen, (ATH_MAX_SCAN_BUFFERS * sizeof(ATH_SCAN_EXT))); + + if (tempStorageLen) + { + if (NULL == (pDCxt->tempStorage = A_MALLOC(tempStorageLen, 0))) + { + return A_NO_MEMORY; + } + pDCxt->tempStorageLength = tempStorageLen; + } + else + { + pDCxt->tempStorage = NULL; + pDCxt->tempStorageLength = 0; + } + + /* Prepare buffer for the scan results, reuse tempStorage. */ + GET_DRIVER_COMMON(pCxt)->pScanOut = pDCxt->tempStorage; + if (NULL == (GET_DRIVER_COMMON(pCxt)->pScanOut)) { + return A_ERROR; + } + + GET_DRIVER_COMMON(pCxt)->securityType = QCA_MEDIACTL_SECURITY_TYPE_NONE; +#if DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE + { + QCA_CONTEXT_STRUCT_PTR qca_ptr = (QCA_CONTEXT_STRUCT_PTR)GET_DRIVER_CXT(pCxt)->pUpperCxt[0]; + uint16_t numRxBuffers, i; + void *pReq; + /* allocate rx objects and buffers */ + A_NETBUF_QUEUE_INIT(&GET_DRIVER_COMMON(pCxt)->rxFreeQueue); + /* NUM_RX_PCBS should be == BSP_CONFIG_ATHEROS_PCB which + * is defined in atheros_wifi.h + */ + numRxBuffers = qca_ptr->PARAM_PTR->NUM_RX_PCBS; + // pre-allocate rx buffers + for (i = 0; i < numRxBuffers; i++) + { + pReq = A_NETBUF_ALLOC_RAW(AR4100_MAX_RX_MESSAGE_SIZE); + + if (NULL == pReq) { + return A_ERROR; + } +#if ENABLE_STACK_OFFLOAD + /*Set rx pool ID so that the buffer is freed to the RX pool*/ + A_NETBUF_SET_RX_POOL(pReq); +#endif + A_NETBUF_ENQUEUE(&GET_DRIVER_COMMON(pCxt)->rxFreeQueue, pReq); + } + } +#endif + + /* init the common->rxBufferStatus to true to indicate that rx buffers are + * ready for use. */ + pDCxt->rxBufferStatus = true; + GET_DRIVER_COMMON(pCxt)->driverShutdown = false; + + return A_OK; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/driver/cust_driver_netbuf.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/driver/cust_driver_netbuf.c new file mode 100644 index 00000000000..2dcb449060c --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/driver/cust_driver_netbuf.c @@ -0,0 +1,804 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include "atheros_wifi_api.h" + +#define AR6000_DATA_OFFSET 64 + +uint8_t g_driverState = DRIVER_STATE_INVALID; + +#if (!ENABLE_STACK_OFFLOAD) + +void default_native_free_fn(PCB_PTR pcb_ptr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)pcb_ptr; + /* head is guaranteed to always point to the + * start of the original buffer */ + if (a_netbuf_ptr->head) + A_FREE(a_netbuf_ptr->head, MALLOC_ID_NETBUFF); + + if (a_netbuf_ptr->native_orig) + a_netbuf_ptr->native_orig->FREE(a_netbuf_ptr->native_orig); + + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); +} + +typedef void (*_pcb_free_fn)(PCB_PTR pcb_ptr); + +void a_netbuf_init(void *buffptr, void *freefn, void *priv) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)buffptr; + + a_netbuf_ptr->native.FREE = (_pcb_free_fn)freefn; + a_netbuf_ptr->native.PRIVATE = priv; + a_netbuf_ptr->tail = a_netbuf_ptr->data = (pointer)((uint32_t)a_netbuf_ptr->head + AR6000_DATA_OFFSET); + a_netbuf_ptr->native.FRAG[0].FRAGMENT = a_netbuf_ptr->head; + a_netbuf_ptr->native.FRAG[0].LENGTH = (uint32_t)a_netbuf_ptr->end - (uint32_t)a_netbuf_ptr->head; +} + +void *a_netbuf_alloc(int32_t size) +{ + A_NETBUF *a_netbuf_ptr; + + do + { + a_netbuf_ptr = A_MALLOC(sizeof(A_NETBUF), MALLOC_ID_NETBUFF_OBJ); + + if (a_netbuf_ptr == NULL) + { + break; + } + A_MEMZERO(a_netbuf_ptr, sizeof(A_NETBUF)); + + a_netbuf_ptr->native.FREE = default_native_free_fn; + + a_netbuf_ptr->native.FRAG[0].LENGTH = AR6000_DATA_OFFSET + size; + a_netbuf_ptr->native.FRAG[0].FRAGMENT = + A_MALLOC((int32_t)(a_netbuf_ptr->native.FRAG[0].LENGTH), MALLOC_ID_NETBUFF); + + if (a_netbuf_ptr->native.FRAG[0].FRAGMENT == NULL) + { + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); + a_netbuf_ptr = NULL; + break; + } + + a_netbuf_ptr->head = a_netbuf_ptr->native.FRAG[0].FRAGMENT; + a_netbuf_ptr->end = + (pointer)((uint32_t)a_netbuf_ptr->native.FRAG[0].FRAGMENT + a_netbuf_ptr->native.FRAG[0].LENGTH); + // reserve head room + a_netbuf_ptr->tail = a_netbuf_ptr->data = (pointer)((uint32_t)a_netbuf_ptr->head + AR6000_DATA_OFFSET); + A_MEMZERO(&a_netbuf_ptr->trans, sizeof(A_TRANSPORT_OBJ)); + } while (0); + + return ((void *)a_netbuf_ptr); +} + +/* + * Allocate an NETBUF w.o. any encapsulation requirement. + */ +void *a_netbuf_alloc_raw(int32_t size) +{ + A_NETBUF *a_netbuf_ptr = NULL; + + do + { + a_netbuf_ptr = A_MALLOC(sizeof(A_NETBUF), MALLOC_ID_NETBUFF_OBJ); + + if (a_netbuf_ptr == NULL) + { + break; + } + + A_MEMZERO(a_netbuf_ptr, sizeof(A_NETBUF)); + + a_netbuf_ptr->native.FREE = default_native_free_fn; + a_netbuf_ptr->native.FRAG[0].LENGTH = (uint32_t)size; + a_netbuf_ptr->native.FRAG[0].FRAGMENT = + A_MALLOC((int32_t)a_netbuf_ptr->native.FRAG[0].LENGTH, MALLOC_ID_NETBUFF); + + if (a_netbuf_ptr->native.FRAG[0].FRAGMENT == NULL) + { + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); + a_netbuf_ptr = NULL; + break; + } + + a_netbuf_ptr->head = a_netbuf_ptr->tail = a_netbuf_ptr->data = a_netbuf_ptr->native.FRAG[0].FRAGMENT; + a_netbuf_ptr->end = + (pointer)((uint32_t)a_netbuf_ptr->native.FRAG[0].FRAGMENT + (uint32_t)a_netbuf_ptr->native.FRAG[0].LENGTH); + A_MEMZERO(&a_netbuf_ptr->trans, sizeof(A_TRANSPORT_OBJ)); + } while (0); + + return ((void *)a_netbuf_ptr); +} + +void a_netbuf_free(void *buffptr) +{ + ((A_NATIVE_ORIG *)buffptr)->FREE(((A_NATIVE_ORIG *)buffptr)); +} + +/* returns the length in bytes of the entire packet. The packet may + * be composed of multiple fragments or it may be just a single buffer. + */ +uint32_t a_netbuf_to_len(void *bufPtr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + uint32_t len = (uint32_t)a_netbuf_ptr->tail - (uint32_t)a_netbuf_ptr->data; + uint16_t i = 0; + + if (a_netbuf_ptr->num_frags) + { + if (a_netbuf_ptr->native_orig != NULL) + { + /* count up fragments */ + for (i = 0; i < a_netbuf_ptr->num_frags; i++) + { + len += a_netbuf_ptr->native_orig->FRAG[i].LENGTH; + } + } + else + { + /* used for special case native's from ATH_TX_RAW */ + for (i = 1; i <= a_netbuf_ptr->num_frags; i++) + { + len += a_netbuf_ptr->native.FRAG[i].LENGTH; + } + } + } + + return len; +} + +/* returns a buffer fragment of a packet. If the packet is not + * fragmented only index == 0 will return a buffer which will be + * the whole packet. pLen will hold the length of the buffer in + * bytes. + */ +void *a_netbuf_get_fragment(void *bufPtr, uint8_t index, int32_t *pLen) +{ + void *pBuf = NULL; + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + if (0 == index) + { + pBuf = a_netbuf_to_data(bufPtr); + *pLen = (int32_t)((uint32_t)a_netbuf_ptr->tail - (uint32_t)a_netbuf_ptr->data); + } + else if (a_netbuf_ptr->num_frags >= index) + { + if (a_netbuf_ptr->native_orig) + { + /* additional fragments are held in native_orig. this is only + * used for tx packets received from the TCP stack. */ + pBuf = a_netbuf_ptr->native_orig->FRAG[index - 1].FRAGMENT; + *pLen = (int32_t)a_netbuf_ptr->native_orig->FRAG[index - 1].LENGTH; + } + else + { + /* used for special case native's from ATH_TX_RAW */ + pBuf = a_netbuf_ptr->native.FRAG[index].FRAGMENT; + *pLen = (int32_t)a_netbuf_ptr->native.FRAG[index].LENGTH; + } + } + + return pBuf; +} + +/* fills the spare bufFragment position for the net buffer */ +void a_netbuf_append_fragment(void *bufPtr, uint8_t *frag, int32_t len) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + /* the first bufFragment is used to hold the built-in buffer. subsequent + * entries if any can be used to append additional buffers. hence + * deduct 1 from MAX_BUF_FRAGS */ + if (a_netbuf_ptr->num_frags < MAX_BUF_FRAGS - 1) + { + a_netbuf_ptr->num_frags++; + a_netbuf_ptr->native.FRAG[a_netbuf_ptr->num_frags].FRAGMENT = frag; + a_netbuf_ptr->native.FRAG[a_netbuf_ptr->num_frags].LENGTH = len; + } + else + { + return A_ERROR; + } +} + +#else +#include "common_stack_offload.h" +#include "custom_stack_offload.h" + +void a_netbuf_set_tx_pool(void *buffptr); +void a_netbuf_set_rx_pool(void *buffptr); +void a_netbuf_free_tx_pool(void *buffptr); +void a_netbuf_free_rx_pool(void *buffptr); +void Driver_ReportRxBuffStatus(void *pCxt, boolean status); + +void default_native_free_fn(void *pcb_ptr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)pcb_ptr; + /* head is guaranteed to always point to the + * start of the original buffer */ + if (a_netbuf_ptr->head) + { + A_FREE(a_netbuf_ptr->head, MALLOC_ID_NETBUFF); + } + if (a_netbuf_ptr->native_orig) + { + txpkt_free(a_netbuf_ptr->native_orig); + } + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); +} + +void *a_netbuf_dequeue_adv(A_NETBUF_QUEUE_T *q, void *pkt) +{ + A_NETBUF *curr, *prev = NULL; + + if (q->head == NULL) + return (void *)NULL; + + curr = (A_NETBUF *)q->head; + + while (curr != NULL) + { + if ((A_NETBUF *)curr->data == pkt) + { + /*Match found*/ + if (curr == (A_NETBUF *)q->head) + { + /*Match found at head*/ + q->head = curr->queueLink; + break; + } + else + { + /*Match found at intermediate node*/ + prev->queueLink = curr->queueLink; + if (q->tail == curr) + { + /*Last node*/ + q->tail = prev; + } + break; + } + } + prev = curr; + curr = curr->queueLink; + } + + if (curr != NULL) + { + q->count--; + curr->queueLink = NULL; + } + return (void *)curr; +} + +void a_netbuf_purge_queue(uint32_t index) +{ + SOCKET_CONTEXT_PTR pcustctxt; + A_NETBUF_QUEUE_T *q; + A_NETBUF *temp; + + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); + + q = &pcustctxt->rxqueue; + + while (q->count) + { + temp = q->head; + q->head = A_GET_QUEUE_LINK(temp); + A_CLEAR_QUEUE_LINK(temp); + A_NETBUF_FREE(temp); + q->count--; + } + q->head = q->tail = NULL; +} + +void a_netbuf_init(void *buffptr, void *freefn, void *priv) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)buffptr; + + // a_netbuf_ptr->native.FREE = (_pcb_free_fn)freefn; + a_netbuf_ptr->native.context = priv; + a_netbuf_ptr->tail = a_netbuf_ptr->data = (void *)((uint32_t)a_netbuf_ptr->head + AR6000_DATA_OFFSET); + a_netbuf_ptr->native.bufFragment[0].payload = a_netbuf_ptr->head; + a_netbuf_ptr->native.bufFragment[0].length = (uint32_t)a_netbuf_ptr->end - (uint32_t)a_netbuf_ptr->head; +#if DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE + a_netbuf_ptr->rxPoolID = 1; +#endif +} + +void *a_netbuf_alloc(int32_t size) +{ + A_NETBUF *a_netbuf_ptr; + + do + { + a_netbuf_ptr = A_MALLOC(sizeof(A_NETBUF), MALLOC_ID_NETBUFF_OBJ); + + if (a_netbuf_ptr == NULL) + { + break; + } + A_MEMZERO(a_netbuf_ptr, sizeof(A_NETBUF)); + + a_netbuf_ptr->native.bufFragment[0].length = AR6000_DATA_OFFSET + size; + a_netbuf_ptr->native.bufFragment[0].payload = + A_MALLOC((int32_t)(a_netbuf_ptr->native.bufFragment[0].length), MALLOC_ID_NETBUFF); + + if (a_netbuf_ptr->native.bufFragment[0].payload == NULL) + { + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); + a_netbuf_ptr = NULL; + break; + } + + a_netbuf_ptr->head = a_netbuf_ptr->native.bufFragment[0].payload; + a_netbuf_ptr->end = (void *)((uint32_t)a_netbuf_ptr->native.bufFragment[0].payload + + a_netbuf_ptr->native.bufFragment[0].length); + // reserve head room + a_netbuf_ptr->tail = a_netbuf_ptr->data = (void *)((uint32_t)a_netbuf_ptr->head + AR6000_DATA_OFFSET); + A_MEMZERO(&a_netbuf_ptr->trans, sizeof(A_TRANSPORT_OBJ)); + /*Init pool IDs*/ + a_netbuf_ptr->txPoolID = 0; + a_netbuf_ptr->rxPoolID = 0; + } while (0); + + return ((void *)a_netbuf_ptr); +} + +/*****************************************************************************/ +/* a_netbuf_reinit - called from custom free after TX over SPI is completed. + It is only called in "Blocking TX" mode where we reuse the same + netbuf. + Tail, data pointers within netbuf may have moved during previous TX, + reinit the netbuf so it can be used again. No allocation is done here. + + * RETURNS: reinitialized netbuf pointer for success and NULL for failure + *****************************************************************************/ +void *a_netbuf_reinit(void *netbuf_ptr, int32_t size) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)(netbuf_ptr); + + do + { + a_netbuf_ptr->native.bufFragment[0].length = AR6000_DATA_OFFSET + size; + + a_netbuf_ptr->head = a_netbuf_ptr->native.bufFragment[0].payload; + a_netbuf_ptr->end = (void *)((uint32_t)a_netbuf_ptr->native.bufFragment[0].payload + + a_netbuf_ptr->native.bufFragment[0].length); + // reserve head room + a_netbuf_ptr->tail = a_netbuf_ptr->data = (void *)((uint32_t)a_netbuf_ptr->head + AR6000_DATA_OFFSET); + A_MEMZERO(&a_netbuf_ptr->trans, sizeof(A_TRANSPORT_OBJ)); + /*Init pool IDs*/ + a_netbuf_ptr->txPoolID = 0; + a_netbuf_ptr->rxPoolID = 0; + } while (0); + + return ((void *)a_netbuf_ptr); +} + +void a_netbuf_set_rx_pool(void *buffptr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)buffptr; + a_netbuf_ptr->rxPoolID = 1; +} + +void a_netbuf_set_tx_pool(void *buffptr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)buffptr; + a_netbuf_ptr->txPoolID = 1; +} + +/* + * Allocate an NETBUF w.o. any encapsulation requirement. + */ +void *a_netbuf_alloc_raw(int32_t size) +{ + A_NETBUF *a_netbuf_ptr = NULL; + + do + { + a_netbuf_ptr = A_MALLOC(sizeof(A_NETBUF), MALLOC_ID_NETBUFF_OBJ); + + if (a_netbuf_ptr == NULL) + { + break; + } + + A_MEMZERO(a_netbuf_ptr, sizeof(A_NETBUF)); + + // a_netbuf_ptr->native.FREE = default_native_free_fn; + a_netbuf_ptr->native.bufFragment[0].length = (uint32_t)size; + a_netbuf_ptr->native.bufFragment[0].payload = + A_MALLOC((int32_t)a_netbuf_ptr->native.bufFragment[0].length, MALLOC_ID_NETBUFF); + + if (a_netbuf_ptr->native.bufFragment[0].payload == NULL) + { + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); + a_netbuf_ptr = NULL; + break; + } + + a_netbuf_ptr->head = a_netbuf_ptr->tail = a_netbuf_ptr->data = a_netbuf_ptr->native.bufFragment[0].payload; + a_netbuf_ptr->end = (void *)((uint32_t)a_netbuf_ptr->native.bufFragment[0].payload + + (uint32_t)a_netbuf_ptr->native.bufFragment[0].length); + A_MEMZERO(&a_netbuf_ptr->trans, sizeof(A_TRANSPORT_OBJ)); + } while (0); + + return ((void *)a_netbuf_ptr); +} + +void a_netbuf_free(void *buffptr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)buffptr; + if (a_netbuf_ptr->rxPoolID != 0) + { + a_netbuf_free_rx_pool(buffptr); + return; + } + else if (a_netbuf_ptr->txPoolID != 0) + { + a_netbuf_free_tx_pool(buffptr); + return; + } + else + { + if (a_netbuf_ptr->native_orig) + { + /*This was a TX packet, do not free netbuf here as it may be reused*/ + txpkt_free(a_netbuf_ptr); + } + else + { + /*For all other packets, free the netbuf*/ + if (a_netbuf_ptr->head) + { + A_FREE(a_netbuf_ptr->head, MALLOC_ID_NETBUFF); + } + + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); + } + } +} + +void a_netbuf_free_rx_pool(void *buffptr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)buffptr; + A_CUSTOM_DRIVER_CONTEXT *pCxt = (A_CUSTOM_DRIVER_CONTEXT *)a_netbuf_ptr->native.context; + + RXBUFFER_ACCESS_ACQUIRE((void *)pCxt); +// A_NETBUF_ENQUEUE(&(pCxt->rxFreeQueue), a_netbuf_ptr); +#if DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE + A_NETBUF_ENQUEUE(&(GET_DRIVER_COMMON(pCxt)->rxFreeQueue), a_netbuf_ptr); +#endif + Driver_ReportRxBuffStatus((void *)pCxt, true); + RXBUFFER_ACCESS_RELEASE((void *)pCxt); +} + +void a_netbuf_free_tx_pool(void *buffptr) +{ +} +/* returns the length in bytes of the entire packet. The packet may + * be composed of multiple fragments or it may be just a single buffer. + */ +uint32_t a_netbuf_to_len(void *bufPtr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + uint32_t len = (uint32_t)a_netbuf_ptr->tail - (uint32_t)a_netbuf_ptr->data; + uint16_t i = 0; + + if (a_netbuf_ptr->num_frags) + { + if (a_netbuf_ptr->native_orig != NULL) + { + /* count up fragments */ + for (i = 0; i < a_netbuf_ptr->num_frags; i++) + { + len += a_netbuf_ptr->native_orig->bufFragment[i].length; + } + } + else + { + /* used for special case native's from ATH_TX_RAW */ + for (i = 1; i <= a_netbuf_ptr->num_frags; i++) + { + len += a_netbuf_ptr->native.bufFragment[i].length; + } + } + } + + return len; +} + +/* returns a buffer fragment of a packet. If the packet is not + * fragmented only index == 0 will return a buffer which will be + * the whole packet. pLen will hold the length of the buffer in + * bytes. + */ +void *a_netbuf_get_fragment(void *bufPtr, uint8_t index, int32_t *pLen) +{ + void *pBuf = NULL; + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + if (0 == index) + { + pBuf = a_netbuf_to_data(bufPtr); + *pLen = (int32_t)((uint32_t)a_netbuf_ptr->tail - (uint32_t)a_netbuf_ptr->data); + } + else if (a_netbuf_ptr->num_frags >= index) + { + if (a_netbuf_ptr->native_orig) + { + /* additional fragments are held in native_orig. this is only + * used for tx packets received from the TCP stack. */ + pBuf = a_netbuf_ptr->native_orig->bufFragment[index - 1].payload; + *pLen = (int32_t)a_netbuf_ptr->native_orig->bufFragment[index - 1].length; + } + else + { + /* used for special case native's from ATH_TX_RAW */ + pBuf = a_netbuf_ptr->native.bufFragment[index].payload; + *pLen = (int32_t)a_netbuf_ptr->native.bufFragment[index].length; + } + } + + return pBuf; +} + +/* fills the spare bufFragment position for the net buffer */ +int a_netbuf_append_fragment(void *bufPtr, uint8_t *frag, int32_t len) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + /* the first bufFragment is used to hold the built-in buffer. subsequent + * entries if any can be used to append additional buffers. hence + * deduct 1 from MAX_BUF_FRAGS */ + if (a_netbuf_ptr->num_frags < MAX_BUF_FRAGS - 1) + { + a_netbuf_ptr->num_frags++; + a_netbuf_ptr->native.bufFragment[a_netbuf_ptr->num_frags].payload = frag; + a_netbuf_ptr->native.bufFragment[a_netbuf_ptr->num_frags].length = len; + } + else + { + return A_ERROR; + } + + return A_OK; +} + +#endif /*!ENABLE_STACK_OFFLOAD*/ + +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pReq) +{ + // uint8_t i; + + OSA_EnterCritical(kCriticalDisableInt); + if (q->head == NULL) + { + q->head = pReq; + } + else + { + A_ASSIGN_QUEUE_LINK(q->tail, pReq); + //((A_NETBUF*)q->tail)->queueLink = (A_NETBUF*)pReq; + } + + q->tail = pReq; + A_CLEAR_QUEUE_LINK(pReq); + //((A_NETBUF*)pkt)->queueLink = NULL; + q->count++; + OSA_ExitCritical(kCriticalDisableInt); +} + +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pReq) +{ + if (q->head == NULL) + { + q->tail = pReq; + } + A_ASSIGN_QUEUE_LINK(pReq, q->head); + //((A_NETBUF*)pkt)->queueLink = q->head; + q->head = pReq; + q->count++; +} + +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q) +{ + void *pReq; + + if (q->head == NULL) + return (void *)NULL; + OSA_EnterCritical(kCriticalDisableInt); + pReq = q->head; + + if (q->tail == q->head) + { + q->tail = q->head = NULL; + } + else + { + q->head = A_GET_QUEUE_LINK(pReq); + // q->head = (void*)(curr->queueLink); + } + + q->count--; + A_CLEAR_QUEUE_LINK(pReq); + // curr->queueLink = NULL; + OSA_ExitCritical(kCriticalDisableInt); + return (void *)pReq; +} + +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q) +{ + q->head = q->tail = NULL; + q->count = 0; +} + +void a_netbuf_configure(void *buffptr, void *buffer, uint16_t headroom, uint16_t length, uint16_t size) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)buffptr; + + A_MEMZERO(a_netbuf_ptr, sizeof(A_NETBUF)); + + if (buffer != NULL) + { + a_netbuf_ptr->head = buffer; + a_netbuf_ptr->data = &(((uint8_t *)buffer)[headroom]); + a_netbuf_ptr->tail = &(((uint8_t *)buffer)[headroom + length]); + a_netbuf_ptr->end = &(((uint8_t *)buffer)[size]); + } +} + +void *a_netbuf_to_data(void *bufPtr) +{ + return (((A_NETBUF *)bufPtr)->data); +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_push(void *bufPtr, int32_t len) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + if ((uint32_t)a_netbuf_ptr->data - (uint32_t)a_netbuf_ptr->head < (uint32_t)len) + { + return A_ERROR; + } + + a_netbuf_ptr->data = (void *)(((uint32_t)a_netbuf_ptr->data) - len); + + return A_OK; +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_push_data(void *bufPtr, uint8_t *srcPtr, int32_t len) +{ + a_netbuf_push(bufPtr, len); + A_MEMCPY(((A_NETBUF *)bufPtr)->data, srcPtr, (uint32_t)len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_put(void *bufPtr, int32_t len) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + if ((uint32_t)a_netbuf_ptr->end - (uint32_t)a_netbuf_ptr->tail < (uint32_t)len) + { + return A_ERROR; + } + + a_netbuf_ptr->tail = (void *)(((uint32_t)a_netbuf_ptr->tail) + len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_put_data(void *bufPtr, uint8_t *srcPtr, int32_t len) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + void *start = a_netbuf_ptr->tail; + + a_netbuf_put(bufPtr, len); + A_MEMCPY(start, srcPtr, (uint32_t)len); + + return A_OK; +} + +/* + * Returns the number of bytes available to a a_netbuf_push() + */ +int32_t a_netbuf_headroom(void *bufPtr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + return (int32_t)((uint32_t)a_netbuf_ptr->data - (uint32_t)a_netbuf_ptr->head); +} + +int32_t a_netbuf_tailroom(void *bufPtr) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + return (int32_t)((uint32_t)a_netbuf_ptr->end - (uint32_t)a_netbuf_ptr->tail); +} + +/* + * Removes specified number of bytes from the beginning of the buffer + */ +A_STATUS +a_netbuf_pull(void *bufPtr, int32_t len) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + if ((uint32_t)a_netbuf_ptr->tail - (uint32_t)a_netbuf_ptr->data < (uint32_t)len) + { + return A_ERROR; + } + + a_netbuf_ptr->data = (void *)((uint32_t)a_netbuf_ptr->data + len); + + return A_OK; +} + +/* + * Removes specified number of bytes from the end of the buffer + */ +A_STATUS +a_netbuf_trim(void *bufPtr, int32_t len) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)bufPtr; + + if ((uint32_t)a_netbuf_ptr->tail - (uint32_t)a_netbuf_ptr->data < (uint32_t)len) + { + return A_ERROR; + } + + a_netbuf_ptr->tail = (void *)((uint32_t)a_netbuf_ptr->tail - len); + + return A_OK; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/hw_interface/cust_spi_hcd.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/hw_interface/cust_spi_hcd.c new file mode 100644 index 00000000000..87931e4ce74 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/hw_interface/cust_spi_hcd.c @@ -0,0 +1,126 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include "spi_hcd_if.h" +#include +#include "hw20_mbox_host_reg.h" +#include +#include +#include "atheros_wifi_api.h" + +// ============================================================================ +// +// ============================================================================ + +#define SPI_POWER_UP_DELAY (1) +#define SPI_HW_CAPS (HW_SPI_FRAME_WIDTH_8 | HW_SPI_NO_DMA | HW_SPI_INT_EDGE_DETECT) +#define SPI_MAX_ALLOWED_BAUD_RATE 25000000 + +// ============================================================================ +// +// ============================================================================ + +// DROPPED +// void Custom_Hcd_EnableDisableSPIIRQ(void *pCxt, boolean enable) +//{ +// A_CUSTOM_DRIVER_CONTEXT *pCustCxt = (A_CUSTOM_DRIVER_CONTEXT *) pCxt; +// wlan_hardware_config_t *wlanHardwareConfig = (wlan_hardware_config_t *) pCustCxt->pDriverParam; +// IRQn_Type irqNumber = wlanHardwareConfig->wlan_irq_number; +// +// if (enable) { +// INT_SYS_EnableIRQ(irqNumber); +// } +// else { +// INT_SYS_DisableIRQ(irqNumber); +// } +//} + +// A_STATUS Custom_HW_Init(void *pCxt) +//{ +// // TODO: Check endianess of SPI +// +// A_CUSTOM_DRIVER_CONTEXT *pCustCxt = (A_CUSTOM_DRIVER_CONTEXT *) pCxt; +// wlan_hardware_config_t *wlanHardwareConfig = (wlan_hardware_config_t *) pCustCxt->pDriverParam; +// +// A_SPI_CTX *spiCxt = &pCustCxt->customhcdcxt.spi_cxt; +// +// // Copy the SPI instance number from the configuration to the local copy +// spiCxt->spi_instance = wlanHardwareConfig->spi_instance; +// //uint32_t spiClk = CLOCK_SYS_GetSpiFreq(spiCxt->spi_instance); +// +// uint32_t baudrate = wlanHardwareConfig->spi_baudrate; +// //if (baudrate > SPI_MAX_ALLOWED_BAUD_RATE) +// // baudrate = SPI_MAX_ALLOWED_BAUD_RATE; +// +// +// +//// spiCxt->userConfig.isChipSelectContinuous = false; +//// spiCxt->userConfig.isSckContinuous = false; +//// spiCxt->userConfig.pcsPolarity = kDspiPcs_ActiveLow; +//// spiCxt->userConfig.whichCtar = kDspiCtar0; +//// spiCxt->userConfig.whichPcs = wlanHardwareConfig->spi_cs; +// spiCxt->masterDevice.dataBusConfig.bitsPerFrame = 8; +// // spiCxt->masterDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge; +// spiCxt->masterDevice.dataBusConfig.clkPhase = kDspiClockPhase_SecondEdge; +// spiCxt->masterDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveLow; +// spiCxt->masterDevice.dataBusConfig.direction = kDspiMsbFirst; +// +// spiCxt->masterDevice.bitsPerSec = baudrate; +// +// // Initialize master driver +// dspi_status_t res; +// res = DSPI_DRV_MasterInit(spiCxt->spi_instance, +// &spiCxt->masterState, +// &spiCxt->userConfig); +// if (spiCxt->spiResult != kStatus_DSPI_Success) { +// return res; +// } +// +// res = DSPI_DRV_MasterConfigureBus(spiCxt->spi_instance, +// &spiCxt->masterDevice, +// &spiCxt->calculatedBaudRate); +// if (res != kStatus_DSPI_Success) { +// return res; +// } +// +// +// // It is necessary for the custom code to populate the following parameters +// // so that the common code knows what kind of hardware it is working with +// A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(pCxt); +// pDCxt->spi_hcd.OperationalClock = spiCxt->calculatedBaudRate; +// pDCxt->spi_hcd.PowerUpDelay = SPI_POWER_UP_DELAY; +// pDCxt->spi_hcd.SpiHWCapabilitiesFlags = SPI_HW_CAPS; +// pDCxt->spi_hcd.MiscFlags |= MISC_FLAG_RESET_SPI_IF_SHUTDOWN; +// +// return A_OK; +//} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_config.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_config.h new file mode 100644 index 00000000000..7df3ee2db0c --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_config.h @@ -0,0 +1,170 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#include "wifi_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ============================================================================ +// Debug and assert printing +// ============================================================================ + +// KSDK printf defined in fsl_debug_console.h +// extern int debug_printf(const char *fmt_s, ...); + +// Define this to a printf-like function to print asserts via qcadrv_assert_func() +//#define ASSERT_PRINTF(...) +//#define ASSERT_PRINTF(...) debug_printf(__VA_ARGS__) + +// Define these to enable WMI RX event tracing +#define WMI_DEBUG_RX_EVENT(cmdId, pReq) +//#define WMI_DEBUG_RX_EVENT(cmdId, pReq) debug_printf("wmiRx=%x\r\n", id) + +// Define this to enable WMI TX command tracing +#define WMI_DEBUG_TX_COMMAND(cmdId, pReq) +//#define WMI_DEBUG_TX_COMMAND(cmdId, pReq) debug_printf("wmiTx=%x\r\n", cmdId) + +// The original QCA driver developers have sprinkled printf statements at more +// or less random places and if you want to see thes, then define this macro +#define QCADRV_PRINTF(...) +//#define QCADRV_PRINTF(...) debug_printf(__VA_ARGS__) + +// NOTE: wmi.c contains a plethora of debug definitions and they are pretty hard +// to make head or tails out of but if you define AR_DEBUG_PRINTF() in a_debug.h +// to some printf() function then you enable some additional WMI tracing that +// were put in place by the original QCA driver developers. + +// ============================================================================ +// +// ============================================================================ + +#define ENABLE_FPGA_BUILD 0 + +#define USE_4BYTE_REGISTER_ACCESS + +#define TARGET_AR4100_REV2 0x30000582 +#define TARGET_AR400X_REV1 0x31C80997 +#define TARGET_AR400X_REV2 0x31C80002 +#define TARGET_AR400X_REV3 0x31C8270E +#define TARGET_AR400X_REV4 0x32000052 + +#define ATH_FIRMWARE_TARGET TARGET_AR400X_REV1 // TARGET_AR400X_REV2 + +#ifndef SUPPORT_11N +#define SUPPORT_11N 1 +#endif + +/* PORT_NOTE: Set the following DRIVER_CONFIG_... defines according to + * the requirements/attributes of the OS and MCU. */ + +/* DRIVER_CONFIG_INCLUDE_BMI - optionally set to 0 if the driver will + * not be used in BMI mode and code space needs to be saved. + * If the driver will be used in BMI for flash reprogram or other then + * this option must be 1. + */ +#define DRIVER_CONFIG_INCLUDE_BMI 1 // 1 or 0 + +/* DRIVER_CONFIG_DISABLE_ASSERT - set to 1 if assert NOP behavior is + * preferred */ +#define DRIVER_CONFIG_DISABLE_ASSERT 0 // 1 or 0 +/* DRIVER_CONFIG_PROFILE_BOOT - can be used to profile driver boot + * process with GPIO's + logic analyzer */ +#define DRIVER_CONFIG_PROFILE_BOOT 0 // 1 or 0 + +/* DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE - set if driver should + * implement a RX Free Queue */ +#define DRIVER_CONFIG_IMPLEMENT_RX_FREE_QUEUE 1 // 1 or 0 + +/*TCPIP stack offload for AR4001*/ +#define ENABLE_STACK_OFFLOAD 1 // 1 or 0 +#if !ENABLE_STACK_OFFLOAD +# error "WiFi driver works only with ENABLE_STACK_OFFLOAD enabled ! " +#endif + +#define T_SELECT_VER1 1 // 1 or 0 + +/* DRIVER_CONFIG_ENABLE_STORE_RECALL - optionally set to zero to reduce + * driver memory footprint. + */ +#define DRIVER_CONFIG_ENABLE_STORE_RECALL 1 // 1 or 0 + +#define ENABLE_AP_MODE 1 // 1 or 0 + +#define MULTI_SOCKET_SUPPORT 1 // 1 or 0 + +#define MANUFACTURING_SUPPORT 1 +#define ENABLE_P2P_MODE 1 // 1 or 0 + +/* DRIVER_CONFIG_PROGRAM_MAC_ADDR - optionally add code to allow an application + * to program a new mac address to the wifi device. this code should only + * be included when programming a mac address is required such as during + * production. otherwise code space can be saved by setting this to 0. + */ +#define DRIVER_CONFIG_PROGRAM_MAC_ADDR 1 // 1 or 0 + +/* DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD is used to enable Firmware download + from the host. This feature is implemented but kept disable and can be enabled + on need basis. DO NOT EDIT NEXT LINE INCLUDING THE SPACE. BUILD SCRIPT SEARCHES + FOR THIS PATTERN AND UPDATES IT IN BUILD TIME. */ +#define DRIVER_CONFIG_ENABLE_HOST_FW_DOWNLOAD 0 // 1 or 0 + +#define ENABLE_HTTP_SERVER 1 // 1 or 0 + +#define ENABLE_HTTP_CLIENT 1 // 1 or 0 + +#define ENABLE_DNS_SERVER 1 // 1 or 0 + +#define ENABLE_DNS_CLIENT 1 // 1 or 0 + +#define ENABLE_SNTP_CLIENT 1 // 1 or 0 + +#define ENABLE_RAW_SOCKET_DEMO 1 // 1 or 0 + +#define WLAN_NUM_OF_DEVICES 1 // 1 or 2 + +#define ENABLE_ROUTING_CMDS 1 // 1 or 0 +#define ENABLE_HTTPS_SERVER 1 // 1 or 0 + +#define ENABLE_HTTPS_CLIENT 1 // 1 or 0 + +#define ENABLE_SSL 1 // 1 or 0 + +#define ENABLE_SCC_MODE 1 // 1 or 0 +#define ENABLE_KF_PERFORMANCE 1 + +#define ENABLE_LARGE_DSET 1 // 1 or 0 + +#include "wlan_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_osapi.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_osapi.h new file mode 100644 index 00000000000..90e1b4c1de6 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_osapi.h @@ -0,0 +1,208 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_OSAPI_H_ +#define _A_OSAPI_H_ + +/* PORT_NOTE: Include any System header files here to resolve any types used + * in A_CUSTOM_DRIVER_CONTEXT */ +#include + +#include "a_config.h" +#include "a_types.h" +#include +#include +#include "platform/mbed_wait_api.h" +#include "mbed_assert.h" + +#define MEM_TYPE_ATHEROS_PERSIST_RX_PCB 0x2001 + +/* there exist within the common code a few places that make use of the + * inline option. This macro can be used to properly declare inline for the compiler + * or it can be used to disable inlining be leaving the macro blank. + */ +#ifndef INLINE +#define INLINE inline +#endif +/* PREPACK and/or POSTPACK are used with compilers that require each data structure + * that requires single byte alignment be declared individually. these macros typically + * would be used in place of athstartpack.h and athendpack.h which would be used with + * compilers that allow this feature to be invoked through a one-time pre-processor command. + */ + +#if defined(__ICCARM__) +/* IAR compiler */ +# define PREPACK __packed +# define POSTPACK +# define FIELD_PACKED +# define PREWEAK_CODE __weak +# define POSTWEAK_CODE +#elif defined(__GNUC__) +/* GCC */ +# define PREPACK +# define POSTPACK __attribute__ ((__packed__)) +# define FIELD_PACKED +# define PREWEAK_CODE +# define POSTWEAK_CODE __attribute__((weak)) +#elif defined(__CC_ARM) +/* KEIL compiler v5 */ +# define PREPACK __packed +# define POSTPACK +# define FIELD_PACKED +# define PREWEAK_CODE __weak +# define POSTWEAK_CODE +#elif __ARMCC_VERSION +/* KEIL compiler v6 */ +# define PREPACK +# define POSTPACK __attribute__ ((__packed__)) +# define FIELD_PACKED +# define PREWEAK_CODE +# define POSTWEAK_CODE __attribute__((weak)) +#else +# error "Unsupported toolchain" +#endif + +#ifndef min +#define min(a, b) ((a) < (b)) ? (a) : (b) +#endif + +#ifndef max +#define max(a, b) ((a) > (b)) ? (a) : (b) +#endif + +/* unaligned little endian access */ +#define A_LE_READ_2(p) ((uint16_t)((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] << 8))) + +#define A_LE_READ_4(p) \ + ((uint32_t)((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] << 8) | (((uint8_t *)(p))[2] << 16) | \ + (((uint8_t *)(p))[3] << 24))) + +/* + * Endianes macros - Used to achieve proper translation to/from wifi chipset endianess. + * these macros should be directed to OS macros or functions that serve this purpose. the + * naming convention is the direction of translation (BE2CPU == BigEndian to native CPU) + * appended with the bit-size (BE2CPU16 == 16 bit operation BE2CPU32 == 32 bit operation + */ + +#if !defined(A_LITTLE_ENDIAN) && !defined(A_BIG_ENDIAN) +# error "Either A_BIG_ENDIAN or A_LITTLE_ENDIAN must be #defined" +#elif defined(A_LITTLE_ENDIAN) && defined(A_BIG_ENDIAN) +# error "A_BIG_ENDIAN and A_LITTLE_ENDIAN cannot be #defined at the same time" +#elif defined(A_LITTLE_ENDIAN) +# define A_BE2CPU16(x) ((uint16_t)(((x) & 0x00ff) << 8) | (uint16_t)(((x) >> 8) & 0x00ff)) +# define A_BE2CPU32(x) \ + ( (((x)& 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8) | (((x) & 0x00ff0000) >> 8) | (((x) >> 24) & 0x000000ff) ) +# define A_LE2CPU16(x) (x) +# define A_LE2CPU32(x) (x) +# define A_CPU2BE16(x) ((uint16_t)(((x) & 0x00ff) << 8) | (uint16_t)(((x) >> 8) & 0x00ff)) +# define A_CPU2BE32(x) \ + ( (((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8) | (((x) & 0x00ff0000) >> 8) | (((x) >> 24) & 0x000000ff) ) +# define A_CPU2LE32(x) (x) +# define A_CPU2LE16(x) (x) +#elif defined(A_BIG_ENDIAN) +# define A_BE2CPU16(x) (x) +# define A_BE2CPU32(x) (x) +# define A_LE2CPU16(x) ((uint16_t)(((x) & 0x00ff) << 8) | (uint16_t)(((x) >> 8) & 0x00ff)) +# define A_LE2CPU32(x) \ + ((((x) & 0x000000ff) << 24) | (((x)&0x0000ff00) << 8) | (((x)&0x00ff0000) >> 8) | (((x) >> 24) & 0x000000ff)) +# define A_CPU2BE16(x) (x) +# define A_CPU2BE32(x) (x) +# define A_CPU2LE32(x) \ + ((((x) & 0x000000ff) << 24) | (((x)&0x0000ff00) << 8) | (((x)&0x00ff0000) >> 8) | (((x) >> 24) & 0x000000ff)) +# define A_CPU2LE16(x) ((uint16_t)(((x) & 0x00ff) << 8) | (uint16_t)(((x) >> 8) & 0x00ff)) +#endif + +/* A_MEM -- macros that should be mapped to OS/STDLIB equivalent functions */ +#define A_MEMCPY(dst, src, len) memcpy((dst), (src), (len)) +#define A_MEMZERO(addr, len) memset((addr), 0, (len)) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) + +extern uint32_t g_totAlloc; +extern uint32_t g_poolid; + +#define DRIVER_STATE_INVALID 0 +#define DRIVER_STATE_INIT 1 +#define DRIVER_STATE_RUN 2 +#define DRIVER_STATE_SHUTDOWN 3 +extern uint8_t g_driverState; + +inline uint32_t _get_size(void *addr) +{ + uint32_t *ptr = (uint32_t *)addr; + ptr -= 3; + + if (g_poolid == 0xffffffff) + { + g_poolid = ptr[1]; + } + + if (ptr[1] == g_poolid) + { + return ptr[0]; + } + else + { + QCADRV_PRINTF("STUCK\n"); + while (1) + { + }; + } +} + +void *a_malloc(int32_t size, uint8_t id); +void a_free(void *addr, uint8_t id); + +/* Definitions used for ID param in calls to A_MALLOC and A_FREE */ +// NAME VALUE DESCRIPTION +#define MALLOC_ID_CONTEXT 1 // persistent allocation for the life of Driver +#define MALLOC_ID_NETBUFF 2 // buffer used to perform TX/RX SPI transaction +#define MALLOC_ID_NETBUFF_OBJ 3 // NETBUF object +#define MALLOC_ID_TEMPORARY 4 // other temporary allocation +/* Macros used for heap memory allocation and free */ +#define A_MALLOCINIT() +#define A_MALLOC(size, id) a_malloc(size, id) +#define A_FREE(addr, id) a_free(addr, id) + +#define A_PRINTF(args...) QCADRV_PRINTF(args) + +/* + * A_MDELAY - used to delay specified number of milliseconds. + */ +#define A_MDELAY(msecs) wait_us(msecs * 1000); + +#if DRIVER_CONFIG_DISABLE_ASSERT +#define A_ASSERT(expr) +#else /* DRIVER_CONFIG_DISABLE_ASSERT */ +extern void *p_Global_Cxt; +extern void qcadrv_assert_func(const char *, int); +//#define A_ASSERT(expr) if(!(expr)) do { qcadrv_assert_func(__FUNCTION__, __LINE__); } while(0) +#define A_ASSERT(expr) MBED_ASSERT(expr) +#endif /* DRIVER_CONFIG_DISABLE_ASSERT */ + +/* UNUSED_ARGUMENT - used to solve compiler warnings where arguments to functions are not used + * within the function. + */ + +#endif /* _OSAPI_MQX_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_types.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_types.h new file mode 100644 index 00000000000..7a1fd3c5ca3 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/a_types.h @@ -0,0 +1,43 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _A_TYPES_H_ +#define _A_TYPES_H_ + +#include +#include + +#define UNUSED_ARGUMENT(arg) ((void)arg) + +/* NOTE: boolean is a type that is used in various WMI commands and events. + * as such it is a type that is shared between the wifi chipset and the host. + * It is required for that reason that boolean be treated as a 32-bit/4-byte type. + */ + +// TODO: change those types to int +// typedef int32_t boolean; + +#endif /* _A_TYPES_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/cust_netbuf.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/cust_netbuf.h new file mode 100644 index 00000000000..91bf9d505fa --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/cust_netbuf.h @@ -0,0 +1,225 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _CUST_NETBUF_H_ +#define _CUST_NETBUF_H_ + +#include +#include +#include +#include "common_src/include/netbuf.h" + +#if !ENABLE_STACK_OFFLOAD + +#include + +#define MAX_BUF_FRAGS 2 /* must match definition of PCB2 */ + /* A_NATIVE_NETBUF and A_NATIVE_ORIG are used to point to upper-layer + * netbuf structures. They are OS/TCP stack dependant. */ +typedef PCB2 A_NATIVE_NETBUF; +typedef PCB A_NATIVE_ORIG; + +/* A_NETBUF represents the data structure for a pReq object (packet) + * throughout the driver. It is part of the custom implementation + * because there may be more optimal ways to achieve the same results + * in other OS/systems. It is expected that any of the elements except + * for the A_TRANSPORT_OBJ can be replaced by some OS specific construct + * thereby making more efficient use of resources. */ +typedef struct _ath_netbuf +{ + A_NATIVE_NETBUF native; // DO NOT MOVE: must be first struct element + uint8_t num_frags; // number of total fragments representing buffer + A_NATIVE_ORIG *native_orig; // the callers ptr passed in send() or NULL + uint8_t *head; // marks the start of head space + uint8_t *data; // marks the start of data space + uint8_t *tail; // marks the start of tail space + uint8_t *end; // marks the end of packet. + void *queueLink; // used to enqueue packets + A_TRANSPORT_OBJ trans; /* container object for netbuf elements */ +} A_NETBUF, *A_NETBUF_PTR; + +void default_native_free_fn(PCB_PTR pcb_ptr); + +#else + +#define MAX_BUF_FRAGS 2 /* must match definition of PCB2 */ +/*Fragment structure*/ +typedef struct db_frag +{ + uint32_t length; // Length in bytes + uint8_t *payload; // Pointer to data +} DB_FRAG, *DB_FRAG_PTR; + +typedef struct drv_buffer +{ + void *context; // Generic placeholder, can be used to store context + DB_FRAG bufFragment[1]; // data fragment +} DRV_BUFFER, *DRV_BUFFER_PTR; + +typedef struct min_db +{ + void *context; + DB_FRAG bufFragment[MAX_BUF_FRAGS]; +} MIN_DB, *MIN_DB_PTR; + +typedef struct tx_packet +{ + DRV_BUFFER db; + uint8_t hdr[88]; + void *a_netbuf_ptr; +} TX_PACKET, *TX_PACKET_PTR; + +/* A_NATIVE_NETBUF and A_NATIVE_ORIG are used to point to upper-layer + * netbuf structures. They are OS/TCP stack dependant. */ +typedef MIN_DB A_NATIVE_NETBUF; +typedef DRV_BUFFER A_NATIVE_ORIG; + +/* A_NETBUF represents the data structure for a pReq object (packet) + * throughout the driver. It is part of the custom implementation + * because there may be more optimal ways to achieve the same results + * in other OS/systems. It is expected that any of the elements except + * for the A_TRANSPORT_OBJ can be replaced by some OS specific construct + * thereby making more efficient use of resources. */ +typedef struct _ath_netbuf +{ + A_NATIVE_NETBUF native; // DO NOT MOVE: must be first struct element + uint8_t num_frags; // number of total fragments representing buffer + A_NATIVE_ORIG *native_orig; // the callers ptr passed in send() or NULL + uint8_t *head; // marks the start of head space + uint8_t *data; // marks the start of data space + uint8_t *tail; // marks the start of tail space + uint8_t *end; // marks the end of packet. + uint8_t txPoolID; // If TX pools are used, assign ID here + uint8_t rxPoolID; // If rx pools are used, assign ID here + void *queueLink; // used to enqueue packets + A_TRANSPORT_OBJ trans; /* container object for netbuf elements */ +} A_NETBUF, *A_NETBUF_PTR; + +/* A_NETBUF_SET_TX_POOL - Set pool ID to indicate buffer is part of tx pool */ +#define A_NETBUF_SET_TX_POOL(bufPtr) a_netbuf_set_tx_pool(bufPtr) + +/* A_NETBUF_SET_RX_POOL - Set pool ID to indicate buffer is part of RX pool */ +#define A_NETBUF_SET_RX_POOL(bufPtr) a_netbuf_set_rx_pool(bufPtr) + +#define A_NETBUF_DEQUEUE_ADV(q, pkt) a_netbuf_dequeue_adv((q), (pkt)) + +#define CUSTOM_PURGE_QUEUE(index) a_netbuf_purge_queue((index)) + +void default_native_free_fn(void *pcb_ptr); +void a_netbuf_set_tx_pool(void *buffptr); +void a_netbuf_set_rx_pool(void *buffptr); +void *a_netbuf_dequeue_adv(A_NETBUF_QUEUE_T *q, void *pkt); +void a_netbuf_purge_queue(uint32_t index); +void *a_netbuf_reinit(void *netbuf_ptr, int32_t size); + +#endif /*!ENABLE_STACK_OFFLOAD*/ + +/* the A_REQ_... definitions are used in calls to A_NETBUF_GET_ELEM and + * A_NETBUF_SET_ELEM. They identify what element is required. The + * developer can either adopt this implementation or create their + * own more suitable definitions as appropriate. */ +#define A_REQ_ADDRESS trans.address +#define A_REQ_EPID trans.epid +#define A_REQ_STATUS trans.status +#define A_REQ_CREDITS trans.credits +#define A_REQ_CALLBACK trans.cb +#define A_REQ_COMMAND trans.cmd +#define A_REQ_LOOKAHEAD trans.lookahead +#define A_REQ_TRANSFER_LEN trans.transferLength + +#define A_NETBUF_GET_ELEM(_obj, _e) ((A_NETBUF *)(_obj))->_e +#define A_NETBUF_SET_ELEM(_obj, _e, _v) ((A_NETBUF *)(_obj))->_e = (_v) + +/* A_CLEAR_QUEUE_LINK - used by netbuf queue code to clear the link. */ +#define A_CLEAR_QUEUE_LINK(_pReq) ((A_NETBUF *)(_pReq))->queueLink = NULL +/* A_ASSIGN_QUEUE_LINK - used by netbuf queue code to populate/connect the link. */ +#define A_ASSIGN_QUEUE_LINK(_pReq, _pN) ((A_NETBUF *)(_pReq))->queueLink = (_pN) +/* A_GET_QUEUE_LINK - used by netbuf queue code to get the link. */ +#define A_GET_QUEUE_LINK(_pReq) ((A_NETBUF *)(_pReq))->queueLink +/* + * Network buffer support + */ + +/* A_NETBUF_DECLARE - declare a NETBUF object on the stack */ +#define A_NETBUF_DECLARE A_NETBUF +/* A_NETBUF_CONFIGURE - (re-)configure a NETBUF object */ +#define A_NETBUF_CONFIGURE(bufPtr, buffer, headroom, length, size) \ + a_netbuf_configure((bufPtr), (buffer), (headroom), (length), (size)) +/* A_NETBUF_ALLOC - allocate a NETBUF object from the "heap". */ +#define A_NETBUF_ALLOC(size) a_netbuf_alloc(size) +/* A_NETBUF_ALLOC_RAW - allocate a NETBUF object from the "heap". */ +#define A_NETBUF_ALLOC_RAW(size) a_netbuf_alloc_raw(size) +/* A_NETBUF_INIT - (re-)initialize a NETBUF object. */ +#define A_NETBUF_INIT(bufPtr, freefn, priv) a_netbuf_init((bufPtr), (freefn), (priv)) +/* A_NETBUF_FREE - release a NETBUF object back to the "heap". */ +#define A_NETBUF_FREE(bufPtr) a_netbuf_free(bufPtr) +/* A_NETBUF_DATA - Get a pointer to the front of valid/populated NETBUF memory. */ +#define A_NETBUF_DATA(bufPtr) a_netbuf_to_data(bufPtr) +/* A_NETBUF_LEN - Get the length of valid/populated NETBUF memory (total for all fragments). */ +#define A_NETBUF_LEN(bufPtr) a_netbuf_to_len(bufPtr) +/* A_NETBUF_PUSH - Adds #len bytes to the beginning of valid/populated NETBUF memory */ +#define A_NETBUF_PUSH(bufPtr, len) a_netbuf_push(bufPtr, len) +/* A_NETBUF_PUT - Adds #len bytes to the end of valid/populated NETBUF memory */ +#define A_NETBUF_PUT(bufPtr, len) a_netbuf_put(bufPtr, len) +/* A_NETBUF_TRIM - Removes #len bytes from the end of the valid/populated NETBUF memory */ +#define A_NETBUF_TRIM(bufPtr, len) a_netbuf_trim(bufPtr, len) +/* A_NETBUF_PULL - Removes #len bytes from the beginning valid/populated NETBUF memory */ +#define A_NETBUF_PULL(bufPtr, len) a_netbuf_pull(bufPtr, len) +/* A_NETBUF_HEADROOM - return the amount of space remaining to prepend content/headers */ +#define A_NETBUF_HEADROOM(bufPtr) a_netbuf_headroom(bufPtr) +/* A_NETBUF_TAILROOM - return the amount of space remaining to append content/trailers */ +#define A_NETBUF_TAILROOM(bufPtr) a_netbuf_tailroom(bufPtr) +/* A_NETBUF_GET_FRAGMENT - Get the indexed fragment from the netbuf */ +#define A_NETBUF_GET_FRAGMENT(bufPtr, index, pLen) a_netbuf_get_fragment((bufPtr), (index), (pLen)) + +/* A_NETBUF_APPEND_FRAGMENT - Add a fragment to the end of the netbuf fragment list */ +#define A_NETBUF_APPEND_FRAGMENT(bufPtr, frag, len) a_netbuf_append_fragment((bufPtr), (frag), (len)) + +/* A_NETBUF_PUT_DATA - Add data to end of a buffer */ +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) a_netbuf_put_data(bufPtr, srcPtr, len) + +/* + * OS specific network buffer access routines + */ + +void a_netbuf_configure(void *buffptr, void *buffer, uint16_t headroom, uint16_t length, uint16_t size); +void a_netbuf_init(void *buffptr, void *freefn, void *priv); +void *a_netbuf_alloc(int32_t size); +void *a_netbuf_alloc_raw(int32_t size); +void a_netbuf_free(void *bufPtr); +void *a_netbuf_to_data(void *bufPtr); +uint32_t a_netbuf_to_len(void *bufPtr); +A_STATUS a_netbuf_push(void *bufPtr, int32_t len); +A_STATUS a_netbuf_push_data(void *bufPtr, uint8_t *srcPtr, int32_t len); +A_STATUS a_netbuf_put(void *bufPtr, int32_t len); +A_STATUS a_netbuf_put_data(void *bufPtr, uint8_t *srcPtr, int32_t len); +A_STATUS a_netbuf_pull(void *bufPtr, int32_t len); +void *a_netbuf_get_fragment(void *bufPtr, uint8_t index, int32_t *pLen); +int a_netbuf_append_fragment(void *bufPtr, uint8_t *frag, int32_t len); +A_STATUS a_netbuf_trim(void *bufPtr, int32_t len); +int32_t a_netbuf_headroom(void *bufPtr); +int32_t a_netbuf_tailroom(void *bufPtr); + +#endif /* _CUST_NETBUF_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/custom_wlan_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/custom_wlan_api.h new file mode 100644 index 00000000000..27802045f31 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/custom_wlan_api.h @@ -0,0 +1,127 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _CUSTOM_API_H_ +#define _CUSTOM_API_H_ + +#include + +void Custom_HW_PowerUpDown(void *pCxt, uint32_t powerUp); +/*1A_STATUS +Custom_HW_Init(void *pCxt); +A_STATUS +Custom_HW_DeInit(void *pCxt);*/ + +void custom_os_usec_delay(uint32_t uSeconds); + +A_STATUS +Custom_Driver_CreateThread(void *pCxt); +A_STATUS +Custom_Driver_DestroyThread(void *pCxt); +A_STATUS +Custom_Driver_ContextInit(void *pCxt); +void Custom_Driver_ContextDeInit(void *pCxt); +void *Custom_GetRxRequest(void *pCxt, uint16_t length); +void Custom_DeliverFrameToNetworkStack(void *pCxt, void *pReq); +void Custom_Api_BssInfoEvent(void *pCxt, uint8_t *datap, int32_t len); +void Custom_Api_ConnectEvent(void *pCxt, uint8_t devId, uint16_t channel, uint8_t *bssid); +void Custom_Api_DisconnectEvent(void *pCxt, + uint8_t devId, + uint8_t reason, + uint8_t *bssid, + uint8_t assocRespLen, + uint8_t *assocInfo, + uint16_t protocolReasonStatus); +void Custom_Api_RSNASuccessEvent(void *pCxt, uint8_t devid, uint8_t code); +void Custom_Api_ReadyEvent(void *pCxt, uint8_t *datap, uint8_t phyCap, uint32_t sw_ver, uint32_t abi_ver); +void Custom_Api_BitRateEvent_tx(void *pCxt, uint8_t devId, int8_t rateIndex); +void Custom_Api_ProbeReq_Event(void *pCxt, uint8_t *datap, uint32_t len); +void Custom_Api_Wps_Init_Event(void *pCxt, uint8_t devid, uint8_t code); + +A_STATUS Custom_HW_Init(void *pCxt); +A_STATUS Custom_HW_DeInit(void *pCxt); + +void *Custom_Api_GetDriverCxt(uint8_t device_id); + +void Custom_Api_PfmDataEvent(void *wmip, uint8_t *datap, int32_t len); +void Custom_Api_PfmDataDoneEvent(void *wmip, uint8_t *datap, int32_t len); +void Custom_Api_Http_Post_Event(void *pCxt, uint8_t *datap); + +#define CUSTOM_API_WMIX_PFM_DATA_EVENT(wmip, datap, len) Custom_Api_PfmDataEvent((wmip), (datap), (len)) +#define CUSTOM_API_WMIX_PFM_DATA_DONE_EVENT(wmip, datap, len) Custom_Api_PfmDataDoneEvent((wmip), (datap), (len)) + +#if ENABLE_P2P_MODE +// void +// Custom_Api_wps_profile_event_rx(void *pCxt, uint8_t devId, uint8_t *datap, int32_t len, void *pReq); + +void Api_GpioDataEvent(void *wmip, uint8_t *datap, int32_t len); // IGX_UD_CHANGES + +#endif + +/* COMMON -> CUSTOM APIs :: These macros are used by common code to call into custom code. + * For a given system many of these will resolve to function calls however for some it + * may be appropriate to simply define them as A_OK. */ +#define CUSTOM_DELIVER_FRAME(pCxt, pReq) Custom_DeliverFrameToNetworkStack((pCxt), (pReq)) + +void Custom_Api_GpioDataEvent(void *wmip, uint8_t *datap, int32_t len); +#define CUSTOM_API_WMIX_GPIO_DATA_EVENT(wmip, datap, len) Custom_Api_GpioDataEvent((wmip), (datap), (len)) + +#define CUSTOM_API_BSS_INFO_EVENT(pCxt, datap, len) Custom_Api_BssInfoEvent((pCxt), (datap), (len)) + +#define CUSTOM_API_PROBEREQ_EVENT(pCxt, datap, len) Custom_Api_ProbeReq_Event((pCxt), (datap), (len)) + +#define CUSTOM_API_BITRATE_EVENT_TX(pCxt, devId, rateIndex) Custom_Api_BitRateEvent_tx((pCxt), (devId), (rateIndex)) +#define CUSTOM_API_CONNECT_EVENT(pCxt, devId, channel, bssid, c, d, e, f, g, h, i) \ + Custom_Api_ConnectEvent((pCxt), (devId), (channel), (bssid)) +#define CUSTOM_API_DISCONNECT_EVENT(pCxt, devId, a, b, c, d, e) \ + Custom_Api_DisconnectEvent((pCxt), (devId), (a), (b), (c), (d), (e)) +#define CUSTOM_API_RSNA_SUCCESS_EVENT(pCxt, devId, code) Custom_Api_RSNASuccessEvent((pCxt), (devId), (code)) + +#define CUSTOM_API_READY_EVENT(pCxt, datap, phyCap, sw_ver, abi_ver) \ + Custom_Api_ReadyEvent((pCxt), (datap), (phyCap), (sw_ver), (abi_ver)) + +//#define CUSTOM_HW_POWER_UP_DOWN(pCxt, powerup) Custom_HW_PowerUpDown((pCxt), (powerup)) +//#define CUSTOM_HW_INIT(pCxt) Custom_HW_Init((pCxt)) +//#define CUSTOM_HW_DEINIT(pCxt) Custom_HW_DeInit((pCxt)) + +#define CUSTOM_DRIVER_CXT_INIT(pCxt) Custom_Driver_ContextInit((pCxt)) +#define CUSTOM_DRIVER_CXT_DEINIT(pCxt) Custom_Driver_ContextDeInit((pCxt)) +#define CUSTOM_DRIVER_GET_RX_REQ(pCxt, l) Custom_GetRxRequest((pCxt), (l)) +#define CUSTOM_API_HTTP_POST_EVENT(pCxt, datap) Custom_Api_Http_Post_Event((pCxt), (datap)) +void Custom_Api_Ota_Resp_Result(void *pCxt, uint32_t cmd, uint32_t resp_code, uint32_t result); +int32_t Custom_Api_Dhcps_Success_Callback_Event(void *pCxt, uint8_t *datap); +int32_t Custom_Api_Dhcpc_Success_Callback_Event(void *pCxt, uint8_t *datap); + +#if ENABLE_P2P_MODE +//#define CUSTOM_API_WPS_PROFILE_EVENT_RX(pCxt, datap, len, pReq) Custom_Api_wps_profile_event_rx((pCxt), (datap), +//(len), (pReq)) +//#define CUSTOM_API_P2P_SAVE_WPS_CRED(pCxt) Custom_Api_p2p_save_wps_credentials((pCxt)) +#endif + +typedef void (*CUSTOM_HW_INTR_CB)(void *); + +void Custom_HW_InterruptHandler(CUSTOM_HW_INTR_CB pHcdCallback, void *pHcdContext); + +#endif /* _CUSTOM_API_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/wlan_config.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/wlan_config.h new file mode 100644 index 00000000000..903aa5a25b3 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/include/wlan_config.h @@ -0,0 +1,158 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_WLAN_CONFIG_H_ +#define _HOST_WLAN_CONFIG_H_ + +/* Include definitions here that can be used to tune the WLAN module behavior. + * Different customers can tune the behavior as per their needs, here. + */ + +/* This configuration item when defined will consider the barker preamble + * mentioned in the ERP IE of the beacons from the AP to determine the short + * preamble support sent in the (Re)Assoc request frames. + */ +#define WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP 0 + +/* This config item when defined will not send the power module state transition + * failure events that happen during scan, to the host. + */ +#define WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN 0 + +/* + * This configuration item enable/disable keepalive support. + * Keepalive support: In the absence of any data traffic to AP, null + * frames will be sent to the AP at periodic interval, to keep the association + * active. This configuration item defines the periodic interval. + * Use value of zero to disable keepalive support + * Default: 60 seconds + */ +#define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 + +/* + * This configuration item disables 11n support. + * The wifi device will connect using 11g, 11b + * or 11a(if supported by chipset) only. + * The consequence of allowing + * 11n is that aggregate packets must be + * supported by the host which requires more + * RAM for received buffers. Because + * throughput will anyways be limited by the + * SPI interface 11n support will not provide + * greater throughput on slower host systems. However some + * access points can be configured for 11n only connections + * in which case disabling 11n would prevent the system from + * being able to connect to such AP's. + * 0 - Enable + * 1 - Disable + */ +#define WLAN_CONFIG_DISABLE_11N 0 + +/* + * This configuration is used to support 11N aggregation + * inside the driver. If aggregation is intended + * to be used then this must be set to 1. The code + * and RAM footprints for the driver will increase + * by enabling this feature. This feature can + * improve throughput performance if the RF is + * the throughput bottle-neck for the system. + * + */ +#define WLAN_CONFIG_11N_AGGR_SUPPORT 1 + +/* + * This configuration controls whether statistics + * from the wifi device are stored in the driver. + * This takes a fair amount of RAM and so should + * only be activated if needed. + */ +#define WLAN_CONFIG_CAPTURE_TARGET_STATS 0 + +/* + * This configuration controls whether the + * wifi driver accepts 802.11 frames from + * the stack. If 0 then 802.3 frames + * are required. + * ****** DO NOT ADJUST ****** + */ +#define WLAN_CONFIG_TX_DOT11_HDR 0 + +/* + * This configuration enables/disables internal + * driver stat tracking using the AR_SOFTC_T. + * Storage cost is ~100 bytes. + */ +#define WLAN_CONFIG_NET_STATS 0 + +/* + * This configuration reduces the number of + * virtual endpoints managed by the driver + * to what would be used if WMM were active + * rather than what the device is capable + * of supporting. enabling this configuration + * saves some RAM and reduces execution time + * modestly. + * ****** DO NOT ADJUST ****** + */ +#define WLAN_CONFIG_TRUNCATED_ENDPOINTS 1 + +/* + * This configuration enables/disables use + * of a GPIO to reset/power down the WiFi device. + * If this value is 0 then the wifi board should + * be configured (via jumpers) so that the PWD line + * is asserted low through some other appropriate + * method. + */ +#define WLAN_CONFIG_ENABLE_CHIP_PWD_GPIO 1 + +/* + * This configuration enable/disables use of + * WMI command synchronization. It is only + * needed if wmi commands which use a flag + * other than NO_SYNC_WMIFLAG are introduced. + * ****** DO NOT ADJUST ****** + */ +#define WLAN_CONFIG_ENABLE_WMI_SYNC 0 + +/* + * This configuration should be set to 1 when + * it is desired to allow AMSDU's to be sliced + * by the host system. This should only be + * enabled (set to 1) by Atheros. + * ****** DO NOT ADJUST ****** + */ +#define WLAN_CONFIG_AMSDU_ON_HOST 0 + +#define WLAN_CONFIG_REDUCE_CREDIT_DRIBBLE 1 + +#define WLAN_CONFIG_NUM_PRE_ALLOC_RX_BUFFERS 2 + +/* compile time test to ensure a valid 11N configuration */ +#if WLAN_CONFIG_DISABLE_11N +#if (WLAN_CONFIG_11N_AGGR_SUPPORT || WLAN_CONFIG_AMSDU_ON_HOST) +#error INVALID 11N COMPILE CONFIGURATION +#endif +#endif + +#endif /* _HOST_WLAN_CONFIG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/qapi/custom_qcom_api.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/qapi/custom_qcom_api.c new file mode 100644 index 00000000000..6388042bf52 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/qapi/custom_qcom_api.c @@ -0,0 +1,204 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if ENABLE_P2P_MODE +#include +#include "p2p.h" +#endif +#include "atheros_wifi.h" +#include "atheros_wifi_api.h" +#include "atheros_wifi_internal.h" +#include "atheros_stack_offload.h" +#include "dset_api.h" +#include "common_stack_offload.h" +#include "qcom_api.h" +//------------------------------------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------------------------------------ + +extern uint32_t Custom_Api_Mediactl(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t command_id, void *inout_param); + +/*FUNCTION*----------------------------------------------------------------- +* +* Function Name : custom_qapi +* Returned Value : A_ERROR on error else A_OK +* Comments : Custom part of QAPI layer. This function will implement the +* custom portion of different QAPIs (OS specific). +* PORTING NOTE: Engineer should rewrite this function based on +* the OS framework. +*END------------------------------------------------------------------*/ +A_STATUS custom_qapi(uint8_t device_id, uint32_t cmd, void *param) +{ + uint32_t result; + //TODO: check param against NULL ! + switch (cmd) + { + case ATH_SET_SCAN: + result = Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_SET_MEDIACTL_SCAN, NULL); + return QCA_OK == result ? A_OK : A_ERROR; + case ATH_GET_SCAN_RESULTS: + { + QCA_SCAN_LIST scan_param; + if (Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_GET_MEDIACTL_SCAN, &scan_param) != A_OK) + { + return A_ERROR; + } + ((ATH_SCAN_LIST *)param)->scan_list = scan_param.scan_info_list; + ((ATH_SCAN_LIST *)param)->num_scan_entries = scan_param.num_scan_entries; + return A_OK; + } + case ATH_SET_SSID: + { + QCA_ESSID ssid_param; + char *pssid = ((ATH_IOCTL_PARAM_STRUCT *)param)->data; + + //NOTE: lower layer does not use 'ssid_param.flags' at all. The decision actually depends on 'ssid_param.length'. + //TODO: remove ssid_param.flags ?? + if (NULL == pssid) + { + ssid_param.flags = 0; + ssid_param.essid = pssid; + ssid_param.length = 0; + } + else + { + ssid_param.flags = 1; + ssid_param.essid = pssid; + ssid_param.length = strlen(pssid); + } + + result = Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_SET_MEDIACTL_ESSID, &ssid_param); + return QCA_OK == result ? A_OK : A_ERROR; + } + case ATH_GET_ESSID: + { + QCA_MEDIACTL_PARAM ssid_param; + ssid_param.data = ((ATH_IOCTL_PARAM_STRUCT *)param)->data; + if (Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_GET_MEDIACTL_ESSID, &ssid_param) != A_OK) + return A_ERROR; + + ((ATH_IOCTL_PARAM_STRUCT *)param)->length = ssid_param.length; + } + break; + case ATH_SET_COMMIT: + result = Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_SET_MEDIACTL_COMMIT, param); + return QCA_OK == result ? A_OK : A_ERROR; + case ATH_GET_POWER: + { + QCA_MEDIACTL_PARAM inout_param; + if (Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_GET_MEDIACTL_POWER, &inout_param) != A_OK) + { + return A_ERROR; + } + *(uint32_t *)param = inout_param.value; + return A_OK; + } + case ATH_SET_SEC_TYPE: + switch (*(uint32_t *)param) + { + case WLAN_AUTH_NONE: + *(uint32_t *)param = QCA_MEDIACTL_SECURITY_TYPE_NONE; + break; + case WLAN_AUTH_WPA_PSK: + *(uint32_t *)param = QCA_MEDIACTL_SECURITY_TYPE_WPA; + break; + case WLAN_AUTH_WPA2_PSK: + *(uint32_t *)param = QCA_MEDIACTL_SECURITY_TYPE_WPA2; + break; + case WLAN_AUTH_WEP: + *(uint32_t *)param = QCA_MEDIACTL_SECURITY_TYPE_WEP; + break; + default: + return (A_ERROR); + } + result = Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_SET_MEDIACTL_SEC_TYPE, param); + return QCA_OK == result ? A_OK : A_ERROR; + + case ATH_SET_OP_MODE: + if (*(uint32_t *)param == QCOM_WLAN_DEV_MODE_STATION) + { + *(uint32_t *)param = QCA_MEDIACTL_MODE_INFRA; + } + else if (*(uint32_t *)param == QCOM_WLAN_DEV_MODE_ADHOC) + { + *(uint32_t *)param = QCA_MEDIACTL_MODE_ADHOC; + } + else if (*(uint32_t *)param == QCOM_WLAN_DEV_MODE_AP) + { + *(uint32_t *)param = QCA_MEDIACTL_MODE_MASTER; + } + else + { + return A_ERROR; + } + result = Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_SET_MEDIACTL_MODE, param); + return QCA_OK == result ? A_OK : A_ERROR; + + case ATH_GET_OP_MODE: + if (Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_GET_MEDIACTL_MODE, param) != A_OK) + { + return A_ERROR; + } + + switch (*(uint32_t *)param) + { + case QCA_MEDIACTL_MODE_INFRA: + *(uint32_t *)param = QCOM_WLAN_DEV_MODE_STATION; + break; + case QCA_MEDIACTL_MODE_ADHOC: + *(uint32_t *)param = QCOM_WLAN_DEV_MODE_ADHOC; + break; + case QCA_MEDIACTL_MODE_MASTER: + *(uint32_t *)param = QCOM_WLAN_DEV_MODE_AP; + break; + default: + break; + } + break; + case ATH_SET_PASSPHRASE: + { + QCA_MEDIACTL_PARAM enet_param; + enet_param.data = ((ATH_IOCTL_PARAM_STRUCT *)param)->data; + enet_param.length = ((ATH_IOCTL_PARAM_STRUCT *)param)->length; + result = Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_SET_MEDIACTL_PASSPHRASE, &enet_param); + return QCA_OK == result ? A_OK : A_ERROR; + } + default: + result = Custom_Api_Mediactl(Custom_Api_GetDriverCxt(device_id), QCA_MEDIACTL_VENDOR_SPECIFIC, param); + return QCA_OK == result ? A_OK : A_ERROR; + } + return A_OK; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/cust_api_stack_offload.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/cust_api_stack_offload.c new file mode 100644 index 00000000000..7b5c938dd0f --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/cust_api_stack_offload.c @@ -0,0 +1,2262 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +#include +#include +#include +#include +#include +#include +#include +#include +#include "atheros_wifi.h" +#include "atheros_wifi_api.h" +#include "atheros_wifi_internal.h" +#include "cust_netbuf.h" + +#if ENABLE_STACK_OFFLOAD +#include "atheros_stack_offload.h" +#include "common_stack_offload.h" +#include "custom_stack_offload.h" + +#if ZERO_COPY +A_NETBUF_QUEUE_T zero_copy_free_queue; +#endif + +#if ENABLE_SSL +extern void *sslhandle; +int32_t find_socket_context_from_ssl(SSL *ssl); +#endif + +#define DEFAULT_DNS_TIMEOUT 25000 /* 25 seconds */ +uint32_t dns_block_time = DEFAULT_DNS_TIMEOUT; +uint32_t (*dhcps_success_callback)(uint8_t *mac, uint32_t ip) = NULL; +uint32_t (*dhcpc_success_callback)(uint32_t ip, uint32_t mask, uint32_t gw) = NULL; + +/*****************************************************************************/ +/* t_socket - Custom version of socket API- please see Api_socket for details + * RETURNS: socket handle or A_ERROR + *****************************************************************************/ +int32_t t_socket(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t domain, uint32_t type, uint32_t protocol) +{ + void *pCxt; + int32_t result = -1; + uint32_t delay_ms = 0; + volatile uint32_t timeout_idx = 0; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + for (timeout_idx = 0; timeout_idx < 8; timeout_idx++) + { + result = Api_socket(pCxt, domain, type, protocol); + /* WiFi cannot allocate more resorces, let's try it again in 100ms */ + if (A_RESOURCES == result || A_ERROR == result) + { + delay_ms = 100 << (timeout_idx); + A_MDELAY(delay_ms); + } + else + { + break; + } + } + + /* Report last A_RESOURCES error as generic error to keep compatible API */ + result = result == A_RESOURCES ? A_ERROR : result; + + return (result); +} + +/*****************************************************************************/ +/* t_shutdown - Custom version of socket shutdown API- please see Api_shutdown for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_shutdown(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_shutdown(pCxt, handle)); +} + +/*****************************************************************************/ +/* t_connect - Custom version of socket connect API- please see Api_connect for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_connect(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, uint16_t length) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_connect(pCxt, handle, name, length)); +} + +/*****************************************************************************/ +/* t_bind - Custom version of socket bind API- please see Api_bind for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_bind(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, uint16_t length) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_bind(pCxt, handle, name, length)); +} + +/*****************************************************************************/ +/* t_listen - Custom version of socket listen API- please see Api_listen for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_listen(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint32_t backlog) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_listen(pCxt, handle, backlog)); +} + +/*****************************************************************************/ +/* t_accept - Custom version of socket accept API- please see Api_accept for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_accept(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, socklen_t length) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_accept(pCxt, handle, name, length)); +} + +#if T_SELECT_VER1 +int32_t t_accept_nb(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *name, socklen_t length) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_accept_ver1(pCxt, handle, name, length)); +} + +int32_t t_select_ver1( + QCA_CONTEXT_STRUCT_PTR qca_ptr, int32_t num, uint32_t *r_fd, uint32_t *w_fd, uint32_t *e_fd, uint32_t tv) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_RX)) + { + return A_ERROR; + } + + return (Api_select_ver1(pCxt, num, r_fd, w_fd, e_fd, tv)); +} + +#endif + +/*****************************************************************************/ +/* t_select - Custom version of socket select API- please see Api_select for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_select(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint32_t tv) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_RX)) + { + return A_ERROR; + } + + return (Api_select(pCxt, handle, tv)); +} + +/*****************************************************************************/ +/* t_errno - Custom version of socket errno API- please see Api_errno for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_errno(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_errno(pCxt, handle)); +} + +/*****************************************************************************/ +/* t_setsockopt - Custom version of socket setsockopt API- please see Api_setsockopt for details + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_setsockopt( + QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint32_t level, uint32_t optname, uint8_t *optval, uint32_t optlen) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_setsockopt(pCxt, handle, level, optname, optval, optlen)); +} + +/*****************************************************************************/ +/* t_getsockopt - Custom version of socket getsockopt API- please see + * Api_getsockopt for details. + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_getsockopt( + QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint32_t level, uint32_t optname, uint8_t *optval, uint32_t optlen) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_getsockopt(pCxt, handle, level, optname, optval, optlen)); +} + +/*****************************************************************************/ +/* t_ipconfig - Custom version of ipconfig API- please see + * Api_ipconfig for details. + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +// int32_t t_ipconfig(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t mode,uint32_t* ipv4_addr, uint32_t* subnetMask, uint32_t* +// gateway4) +A_STATUS t_ipconfig(void *handle, + uint32_t mode, + uint32_t *ipv4_addr, + uint32_t *subnetMask, + uint32_t *gateway4, + IP46ADDR *dnsaddr, + char *hostname) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + int32_t result; + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ipconfig(pCxt, mode, ipv4_addr, subnetMask, gateway4, dnsaddr, hostname); + return result == 0 ? A_OK : A_ERROR; +} + +/*****************************************************************************/ +/* t_ip6config - Custom version of ipconfig API- please see + * Api_ip6config for details. + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +A_STATUS t_ip6config(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t mode, + IP6_ADDR_T *v6Global, + IP6_ADDR_T *v6Local, + IP6_ADDR_T *v6DefGw, + IP6_ADDR_T *v6GlobalExtd, + int32_t *LinkPrefix, + int32_t *GlbPrefix, + int32_t *DefGwPrefix, + int32_t *GlbPrefixExtd) +{ + void *pCxt; + int32_t result; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ip6config(pCxt, mode, v6Global, v6Local, v6DefGw, v6GlobalExtd, LinkPrefix, GlbPrefix, DefGwPrefix, + GlbPrefixExtd); + return 0 == result ? A_OK : A_ERROR; +} + +/*****************************************************************************/ +/* t_ipconfig_dhcp_pool - Function to create DHCP Pool + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_ipconfig_dhcp_pool(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t *start_ipv4_addr, + uint32_t *end_ipv4_addr, + int32_t leasetime) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ipconfig_dhcp_pool(pCxt, start_ipv4_addr, end_ipv4_addr, leasetime)); +} + +/*****************************************************************************/ +/* t_ipconfig_dhcps_cb_enable - Function to register DHCP Server Callback + Callback is invoked with the client MAC Addr + and the IP address assigned + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_ipconfig_dhcps_cb_enable(QCA_CONTEXT_STRUCT_PTR qca_ptr, void *callback) +{ + if (qca_ptr->MAC_CONTEXT_PTR == NULL) + { + return A_ERROR; + } + /*Register the dhcp callback*/ + dhcps_success_callback = (uint32_t (*)(uint8_t *, uint32_t))callback; + return A_OK; +} + +/*****************************************************************************/ +/* t_ipconfig_dhcpc_cb_enable - Function to register DHCP Client Callback + Callback is invoked with the client's IP, + Mask and the Gateway Address + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +int32_t t_ipconfig_dhcpc_cb_enable(QCA_CONTEXT_STRUCT_PTR qca_ptr, void *callback) +{ + if (qca_ptr->MAC_CONTEXT_PTR == NULL) + { + return A_ERROR; + } + /*Register the dhcp callback*/ + dhcpc_success_callback = (uint32_t (*)(uint32_t, uint32_t, uint32_t))callback; + return A_OK; +} + +A_STATUS t_ip6config_router_prefix( + QCA_CONTEXT_STRUCT_PTR qca_ptr, IP6_ADDR_T *v6addr, int32_t prefixlen, int32_t prefix_lifetime, int32_t valid_lifetime) +{ + void *pCxt; + int32_t result; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ip6config_router_prefix(pCxt, v6addr, prefixlen, prefix_lifetime, valid_lifetime); + return 0 == result ? A_OK : A_ERROR; +} + +/*****************************************************************************/ +/* custom_ipbridgemode - Custom version of bridgemode API- please see + * Api_ipbridgemode for details. + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +A_STATUS custom_ipbridgemode(void *handle, uint16_t status) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + int32_t result; + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ipbridgemode(pCxt, status); + return 0 == result ? A_OK : A_ERROR; +} + +A_STATUS custom_ipconfig_set_tcp_exponential_backoff_retry(QCA_CONTEXT_STRUCT_PTR qca_ptr, int32_t retry) +{ + void *pCxt; + int32_t result; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ipconfig_set_tcp_exponential_backoff_retry(pCxt, retry); + return 0 == result ? A_OK : A_ERROR; +} + +int32_t custom_ipconfig_set_ip6_status(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint16_t status) +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ipconfig_set_ip6_status(pCxt, status)); +} + +A_STATUS custom_ipconfig_dhcp_release(QCA_CONTEXT_STRUCT_PTR qca_ptr) +{ + void *pCxt; + int32_t result; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ipconfig_dhcp_release(pCxt); + return 0 == result ? A_OK : A_ERROR; +} +int32_t Custom_Api_Dhcps_Success_Callback_Event(void *pCxt, uint8_t *datap) +{ + SOCK_DHCPS_SUCCESS_CALLBACK_T *dhcps_cb_info = (SOCK_DHCPS_SUCCESS_CALLBACK_T *)datap; + if (dhcps_success_callback) + { + dhcps_success_callback(dhcps_cb_info->mac, dhcps_cb_info->ip); + } + return A_OK; +} + +int32_t Custom_Api_Dhcpc_Success_Callback_Event(void *pCxt, uint8_t *datap) +{ + SOCK_DHCPC_SUCCESS_CALLBACK_T *dhcpc_cb_info = (SOCK_DHCPC_SUCCESS_CALLBACK_T *)datap; + if (dhcpc_success_callback) + { + dhcpc_success_callback(dhcpc_cb_info->ip, dhcpc_cb_info->mask, dhcpc_cb_info->gw); + } + return A_OK; +} + +A_STATUS custom_ipconfig_set_tcp_rx_buffer(QCA_CONTEXT_STRUCT_PTR qca_ptr, int32_t rxbuf) +{ + void *pCxt; + int32_t result; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ipconfig_set_tcp_rx_buffer(pCxt, rxbuf); + return 0 == result ? A_OK : A_ERROR; +} + +#if ENABLE_HTTP_SERVER +A_STATUS custom_ip_http_server(void *handle, int32_t command) +{ + int32_t result; +#if 0 /* keviny */ + void *pCxt = handle; +#else + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; +#endif + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ip_http_server(pCxt, command); + return 0 == result ? A_OK : A_ERROR; +} + +A_STATUS custom_ip_http_server_method( + void *handle, int32_t command, uint8_t *pagename, uint8_t *objname, int32_t objtype, int32_t objlen, uint8_t *value) +{ + int32_t result; +#if 0 /* keviny */ + void *pCxt = handle; +#else + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; +#endif + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ip_http_server_method(pCxt, command, pagename, objname, objtype, objlen, value); + return 0 == result ? A_OK : A_ERROR; +} + +void Custom_Api_Http_Post_Event(void *pCxt, uint8_t *datap) +{ + WMI_HTTP_POST_EVENT_CB cb = NULL; + + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + + cb = (WMI_HTTP_POST_EVENT_CB)(GET_DRIVER_CXT(pCxt)->httpPostCb); + + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + if (cb) + { + cb(GET_DRIVER_CXT(pCxt)->httpPostCbCxt, (void *)datap); + } +} + +int32_t custom_http_set_post_cb(void *handle, void *cxt, void *callback) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + GET_DRIVER_CXT(pCxt)->httpPostCb = callback; + GET_DRIVER_CXT(pCxt)->httpPostCbCxt = cxt; + return A_OK; +} +#endif + +#if ENABLE_HTTP_CLIENT + +/*****************************************************************************/ +/* cust_httpc_method - Custom version of httpc API- please see Api_httpc_connect for details +* RETURNS: A_OK or A_ERROR +*****************************************************************************/ +A_STATUS custom_httpc_method(void *handle, uint32_t command, uint8_t *url, uint8_t *data, uint8_t **output) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + int32_t result; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_httpc_method(pCxt, command, url, data, output); + return 0 == result ? A_OK : A_ERROR; +} + +/*****************************************************************************/ +/* zero_copy_http_free - ZERO_COPY free API.It will find and remove rx buffer + * for HTTP client. + * RETURNS: Nothing + *****************************************************************************/ +void zero_copy_http_free(void *buffer) +{ + uint32_t *length; + + length = (uint32_t *)buffer; + buffer = (void *)(length - 3); + // printf("Deleting from Q %p\n", buffer); + zero_copy_free(buffer); +} +#endif /* ENABLE_HTTP_CLIENT */ + +int32_t custom_ip_hostname(void *handle, char *domain_name) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_hostname(pCxt, domain_name)); +} + +#if ENABLE_DNS_SERVER +int32_t custom_ip_dns_local_domain(void *handle, char *domain_name) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_dns_local_domain(pCxt, domain_name)); +} + +int32_t custom_ipdns(void *handle, int32_t command, char *domain_name, IP46ADDR *dnsaddr) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ipdns(pCxt, command, domain_name, dnsaddr)); +} + +int32_t custom_ip_dns_server(void *handle, uint32_t command) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ip_dns_server(pCxt, command)); +} + +#endif /* ENABLE_DNS_SERVER */ + +#if ENABLE_DNS_CLIENT +int32_t custom_ip_set_dns_block_time(void *handle, int32_t blockSec) +{ + if (blockSec <= 0) + { + dns_block_time = DEFAULT_DNS_TIMEOUT; + } + else + { + dns_block_time = (blockSec > 0xFF ? 0xFF : blockSec) * 1000; + } + return A_OK; +} + +int32_t custom_ip_resolve_hostname(void *handle, DNC_CFG_CMD *DncCfg, DNC_RESP_INFO *DncRespInfo) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_resolve_host_name(pCxt, DncCfg, DncRespInfo)); +} + +int32_t custom_ip_dns_server_addr(void *handle, IP46ADDR *addr) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_dns_server_addr(pCxt, addr)); +} + +int32_t custom_ip_dns_client(void *handle, int32_t command) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_dns_client(pCxt, command)); +} +#endif /* ENABLE_DNS_CLIENT */ + +#if ENABLE_SNTP_CLIENT +int32_t custom_ip_sntp_srvr_addr(void *handle, int32_t command, char *sntp_srvr_addr) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_sntp_srvr_addr(pCxt, command, sntp_srvr_addr)); +} + +int32_t custom_ip_sntp_get_time(void *handle, tSntpTime *SntpTime) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_sntp_get_time(pCxt, SntpTime)); +} +int32_t custom_ip_sntp_get_time_of_day(void *handle, tSntpTM *SntpTm) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_sntp_get_time_of_day(pCxt, SntpTm)); +} +int32_t custom_ip_sntp_modify_zone_dse(void *handle, uint8_t hour, uint8_t min, uint8_t add_sub, uint8_t dse) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_sntp_modify_zone_dse(pCxt, hour, min, add_sub, dse)); +} + +int32_t custom_ip_sntp_query_srvr_address(void *handle, tSntpDnsAddr SntpDnsAddr[MAX_SNTP_SERVERS]) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_sntp_query_srvr_address(pCxt, SntpDnsAddr)); +} + +int32_t custom_ip_sntp_client(void *handle, int32_t command) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_ip_sntp_client(pCxt, command)); +} +#endif /* ENABLE_SNTP_CLIENT */ + +#if ENABLE_ROUTING_CMDS +A_STATUS custom_ipv4_route(void *handle, + uint32_t command, + IP_ADDR_T *ipv4_addr, + IP_ADDR_T *subnetMask, + IP_ADDR_T *gateway, + uint32_t *ifIndex, + IPV4_ROUTE_LIST_T *routelist) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + int32_t result; + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ipv4_route(pCxt, command, ipv4_addr, subnetMask, gateway, ifIndex, routelist); + return 0 == result ? A_OK : A_ERROR; +} + +A_STATUS custom_ipv6_route(void *handle, + uint32_t command, + IP6_ADDR_T *ipv6_addr, + uint32_t *prefixLen, + IP6_ADDR_T *gateway, + uint32_t *ifIndex, + IPV6_ROUTE_LIST_T *routelist) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + int32_t result; + + if (pCxt == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ipv6_route(pCxt, command, ipv6_addr, prefixLen, gateway, ifIndex, routelist); + return 0 == result ? A_OK : A_ERROR; +} +#endif /* ENABLE_ROUTING_CMDS */ +A_STATUS custom_tcp_connection_timeout(void *handle, uint32_t timeout_val) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + int32_t result; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_tcp_connection_timeout(pCxt, timeout_val); + return 0 == result ? A_OK : A_ERROR; +} +int32_t custom_ota_upgrade(void *handle, + uint32_t addr, + char *filename, + uint8_t mode, + uint8_t preserve_last, + uint8_t protocol, + uint32_t *resp_code, + uint32_t *ret_len) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ota_upgrade(pCxt, addr, filename, mode, preserve_last, protocol, resp_code, ret_len)); +} +int32_t custom_ota_read_area(void *handle, uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *ret_len) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ota_read_area(pCxt, offset, size, buffer, ret_len)); +} + +int32_t custom_ota_done(void *handle, boolean good_image) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ota_done(pCxt, good_image)); +} + +int32_t custom_ota_session_start(void *handle, uint32_t flags, uint32_t partition_index) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ota_session_start(pCxt, flags, partition_index)); +} + +uint32_t custom_ota_partition_get_size(void *handle) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return 0; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return 0; + } + + return (Api_ota_partition_get_size(pCxt)); +} + +int32_t custom_ota_partition_erase(void *handle) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ota_partition_erase(pCxt)); +} + +int32_t custom_ota_partition_verify_checksum(void *handle) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ota_partition_verify_checksum(pCxt)); +} + +int32_t custom_ota_parse_image_hdr(void *handle, uint8_t *header, uint32_t *offset) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + return (Api_ota_parse_image_hdr(pCxt, header, offset)); +} + +int32_t custom_ota_partition_write_data(void *handle, uint32_t offset, uint8_t *buf, uint32_t size, uint32_t *ret_size) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + if (pCxt == NULL) + { + return 0; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return 0; + } + + return (Api_ota_partition_write_data(pCxt, offset, buf, size, ret_size)); +} + +int32_t custom_ota_set_response_cb(void *handle, void *callback) +{ + void *pCxt = ((QCA_CONTEXT_STRUCT_PTR)handle)->MAC_CONTEXT_PTR; + + GET_DRIVER_CXT(pCxt)->otaCB = callback; + return A_OK; +} + +void Custom_Api_Ota_Resp_Result(void *pCxt, uint32_t cmd, uint32_t resp_code, uint32_t result) +{ + ATH_OTA_CB cb = NULL; + DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt); + cb = (ATH_OTA_CB)(GET_DRIVER_CXT(pCxt)->otaCB); + DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt); + + if (cb) + { + cb(cmd, resp_code, result); + } +} + +/*****************************************************************************/ +/* t_ping - Custom version of ping API- please see + * Api_ping for details. + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +A_STATUS t_ping(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t ipv4_addr, uint32_t size, uint32_t ms_interval) +{ + void *pCxt; + int32_t result; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ping(pCxt, ipv4_addr, size, ms_interval); + return result == 0 ? A_OK : A_ERROR; +} + +/*****************************************************************************/ +/* t_ping6 - Custom version of ping API- please see + * Api_ping6 for details. + * RETURNS: A_OK or A_ERROR + *****************************************************************************/ +A_STATUS t_ping6(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint8_t *ip6addr, uint32_t size, uint32_t ms_interval) +{ + void *pCxt; + int32_t result; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + + result = Api_ping6(pCxt, ip6addr, size, ms_interval); + return 0 == result ? A_OK : A_ERROR; +} + +/*****************************************************************************/ +/* t_send - Custom version of socket send API. Used for stream based sockets. + * Sends provided buffer to target. + * RETURNS: Number of bytes sent to target + *****************************************************************************/ +int32_t t_send(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, uint8_t *buffer, uint32_t length, uint32_t flags) +{ + int32_t index; + int32_t result = 0; + + /* This function is dedicated to TCP sockets, so transfer *should* pass without an error. + * Perform several attempts before give up on DEADLOCK state. */ + for (int deadlock_attempts = 0; deadlock_attempts < 50; deadlock_attempts++) + { + /* Find socket context */ + if((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + return A_SOCK_INVALID; + } + + if( ath_sock_context[index]->TCPCtrFlag == TCP_FIN ) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + return A_SOCK_INVALID; + } + + /* Send data to 'driver_task' */ + result = t_sendto(qca_ptr, handle, buffer, length, flags, NULL, 0); + + /* If 'driver_task' refuses to send data in case of 'deadlock' state, + * then put API task to sleep and try to send data later */ + if (A_DEADLOCK == result) + { + A_MDELAY(70); + continue; + } + else + { + break; + } + } + + return result; +} + +/*****************************************************************************/ +/* t_sendto - Custom version of socket send API. Used for datagram sockets. + * Sends provided buffer to target. Creates space for headroom at + * the begining of the packet. The headroom is used by the stack to + * fill in the TCP-IP header. + * RETURNS: Number of bytes sent to target + *****************************************************************************/ +int32_t t_sendto(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + uint8_t *buffer, + uint32_t length, + uint32_t flags, + void *name, + uint32_t socklength) +{ + uint8_t custom_hdr[TCP6_HEADROOM]; + int32_t index = 0; + uint16_t custom_hdr_length = 0; + DRV_BUFFER_PTR db_ptr; + uint16_t hdr_length = sizeof(ATH_MAC_HDR); + uint8_t *hdr = NULL, *bufPtr = buffer; + void *pCxt; +#if NON_BLOCKING_TX + SOCKET_CONTEXT_PTR pcustctxt; +#endif + int32_t result = 0, block_result = 0; + A_STATUS status = A_OK; + uint16_t rem_len = length; + uint16_t offset = 0; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Find socket context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + return A_SOCK_INVALID; + } + + /* If socket is TCP and not connected, report error */ + if ( + ((ath_sock_context[index]->domain == ATH_AF_INET) && + (ath_sock_context[index]->type == SOCK_STREAM_TYPE) && + (ath_sock_context[index]->TCPCtrFlag != TCP_CONNECTED)) || + ((ath_sock_context[index]->domain == ATH_AF_INET6) && + (ath_sock_context[index]->type == SOCK_STREAM_TYPE) && + (ath_sock_context[index]->TCPCtrFlag != TCP_CONNECTED)) + ) + return A_ERROR; + + /* Get expected size of header */ + /* TODO: fix for raw socket domain */ + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + if (ath_sock_context[index]->type == SOCK_STREAM_TYPE) + hdr_length = TCP_HEADROOM; + else + hdr_length = UDP_HEADROOM; + } + else + { + if (ath_sock_context[index]->type == SOCK_STREAM_TYPE) + hdr_length = TCP6_HEADROOM_WITH_NO_OPTION; + else + hdr_length = UDP6_HEADROOM; + } + + while (rem_len != 0) + { + length = rem_len; + A_MEMZERO(custom_hdr, TCP6_HEADROOM); + + /*Calculate fragmentation threshold. We cannot send packets greater that HTC credit size + over HTC, Bigger packets need to be fragmented. Thresholds are different for IP v4 vs v6*/ + if (ath_sock_context[index]->domain == ATH_AF_INET6) + { + custom_hdr_length = sizeof(SOCK_SEND6_T); + SOCK_SEND6_T *tmp_ipv6 = (SOCK_SEND6_T*)custom_hdr; + if (name != NULL) + { + tmp_ipv6->name6.sin6_port = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_port); + tmp_ipv6->name6.sin6_family = A_CPU2LE16(((SOCKADDR_6_T *)name)->sin6_family); + tmp_ipv6->name6.sin6_flowinfo = A_CPU2LE32(((SOCKADDR_6_T *)name)->sin6_flowinfo); + A_MEMCPY((uint8_t *)&(tmp_ipv6->name6.sin6_addr), + (uint8_t *)&((SOCKADDR_6_T *)name)->sin6_addr, sizeof(IP6_ADDR_T)); + tmp_ipv6->socklength = A_CPU2LE32(socklength); + } + else + { + memset((uint8_t *)(&tmp_ipv6->name6), 0, sizeof(name)); + } + } + else + { + custom_hdr_length = sizeof(SOCK_SEND_T); + SOCK_SEND_T *tmp_ipv4 = (SOCK_SEND_T*)custom_hdr; + if (name != NULL) + { + tmp_ipv4->name.sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + tmp_ipv4->name.sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + tmp_ipv4->name.sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + tmp_ipv4->socklength = A_CPU2LE32(socklength); + } + else + { + memset((uint8_t *)(&tmp_ipv4->name), 0, sizeof(name)); + } + } + + /*Populate common fields of custom header, these are the same for IP v4/v6*/ + SOCK_SEND_T *tmp_sock = (SOCK_SEND_T*)custom_hdr; + tmp_sock->handle = A_CPU2LE32(handle); + tmp_sock->flags = A_CPU2LE32(flags); + + if (offset != 0) + { + memmove(bufPtr, (bufPtr + offset), rem_len); + } + + db_ptr = &((TX_PACKET_PTR)(bufPtr - TX_PKT_OVERHEAD))->db; + hdr = ((TX_PACKET_PTR)(bufPtr - TX_PKT_OVERHEAD))->hdr; + + A_MEMZERO(hdr, hdr_length); + +#if NON_BLOCKING_TX + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); + /*In non blocking TX case, Enqueue the packet so that it can be freed later when + TX over SPI is successful. Application should not free this buffer*/ + + A_MUTEX_ACQUIRE(&pcustctxt->nb_tx_mutex); + A_NETBUF_ENQUEUE(&(pcustctxt->non_block_queue), bufPtr); + A_MUTEX_RELEASE(&pcustctxt->nb_tx_mutex); +#endif + + if ((length == 0) || (length > IPV4_FRAGMENTATION_THRESHOLD)) + { + /*Host fragmentation is not allowed, application must send payload + below IPV4_FRAGMENTATION_THRESHOLD size*/ + A_ASSERT(0); + } + + tmp_sock->length = A_CPU2LE32(length); + + A_MEMCPY(hdr, custom_hdr, custom_hdr_length); + + db_ptr->context = (void *)ath_sock_context[index]; + if ((ath_sock_context[index]->type == SOCK_STREAM_TYPE) && (length > TCP_MSS)) + { + offset = TCP_MSS; + length = TCP_MSS; + } + + rem_len -= length; + + db_ptr->bufFragment[0].payload = bufPtr; + db_ptr->bufFragment[0].length = length; + result += length; + status = custom_send_tcpip(pCxt, db_ptr, length, 1, hdr, hdr_length); + if (status != A_OK) + { + goto END_TX; + } + +#if !NON_BLOCKING_TX + /*Wait till packet is sent to target*/ + if ((block_result = BLOCK(pCxt, ath_sock_context[index], TRANSMIT_BLOCK_TIMEOUT, TX_DIRECTION)) != A_OK) + { + result = block_result; + goto END_TX; + } +#endif + } +END_TX: + + if (status != A_OK) + { + result = A_SOCK_INVALID; + } + + return result; +} + +#if ZERO_COPY +int32_t t_recvfrom(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + void **buffer, + uint32_t length, + uint32_t flags, + void *name, + socklen_t *socklength) +#else +int32_t t_recvfrom(QCA_CONTEXT_STRUCT_PTR qca_ptr, + uint32_t handle, + void *buffer, + uint32_t length, + uint32_t flags, + void *name, + socklen_t *socklength) +#endif +{ + void *pCxt; + + if ((pCxt = qca_ptr->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_RX)) + { + return A_ERROR; + } + + return (Api_recvfrom(pCxt, handle, buffer, length, flags, name, socklength)); +} + +#if ZERO_COPY +int32_t t_recv(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void **buffer, uint32_t length, uint32_t flags) +#else +int32_t t_recv(QCA_CONTEXT_STRUCT_PTR qca_ptr, uint32_t handle, void *buffer, uint32_t length, uint32_t flags) +#endif +{ + return (t_recvfrom(qca_ptr, handle, buffer, length, flags, NULL, NULL)); +} + +#if ZERO_COPY + +/*****************************************************************************/ +/* zero_copy_free - ZERO_COPY free API.It will find and remove rx buffer from + * a common queue. + * RETURNS: Number of bytes received or A_ERROR in case of failure + *****************************************************************************/ +void zero_copy_free(void *buffer) +{ + A_NETBUF *a_netbuf_ptr = NULL; + + /*find buffer in zero copy queue*/ + a_netbuf_ptr = A_NETBUF_DEQUEUE_ADV(&zero_copy_free_queue, buffer); + + if (a_netbuf_ptr != NULL) + A_NETBUF_FREE(a_netbuf_ptr); + // else + // printf("Error: buffer not found\n"); +} + +/*****************************************************************************/ +/* Api_recvfrom - ZERO_COPY version of receive API.It will check socket's + * receive quese for pending packets. If a packet is available, + * it will be passed to the application without a memcopy. The + * application must call a zero_copy_free API to free this buffer. + * RETURNS: Number of bytes received or A_ERROR in case of failure + *****************************************************************************/ +int32_t Api_recvfrom( + void *pCxt, uint32_t handle, void **buffer, uint32_t length, uint32_t flags, void *name, socklen_t *socklength) +{ + int32_t index; + uint32_t len = 0, hdrlen = 0; + A_NETBUF *a_netbuf_ptr = NULL; + uint8_t *data = NULL; + SOCKET_CONTEXT_PTR pcustctxt; + + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + return A_SOCK_INVALID; + } + + if (ath_sock_context[index]->TCPCtrFlag == TCP_FIN) + { + QCADRV_PRINTF("fin in recv \r\n"); + return A_SOCK_INVALID; + } + + /* If socket is TCP and not connected, report error */ + if ( + ((ath_sock_context[index]->domain == ATH_AF_INET) && + (ath_sock_context[index]->type == SOCK_STREAM_TYPE) && + (ath_sock_context[index]->TCPCtrFlag != TCP_CONNECTED)) || + ((ath_sock_context[index]->domain == ATH_AF_INET6) && + (ath_sock_context[index]->type == SOCK_STREAM_TYPE) && + (ath_sock_context[index]->TCPCtrFlag != TCP_CONNECTED)) + ) + return A_ERROR; + + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); + /*Check if a packet is available*/ + /*Check if a packet is available*/ + if ((ath_sock_context[index]->type == SOCK_STREAM_TYPE) && (ath_sock_context[index]->remaining_bytes != 0) && + (ath_sock_context[index]->old_netbuf != NULL)) + { + a_netbuf_ptr = ath_sock_context[index]->old_netbuf; + data = (uint8_t *)A_NETBUF_DATA(a_netbuf_ptr); + } + else + { + while ((a_netbuf_ptr = A_NETBUF_DEQUEUE(&(pcustctxt->rxqueue))) == NULL) + { +#if NON_BLOCKING_RX + /*No packet is available, return -1*/ + return -1; +#else + if (ath_sock_context[index]->TCPCtrFlag == TCP_FIN) + { + if (queue_empty(index)) + { + QCADRV_PRINTF("fin in recv \r\n"); + clear_socket_context(index); + return A_SOCK_INVALID; + } + } + /*No packet available, block*/ + if (BLOCK(pCxt, ath_sock_context[index], 0, RX_DIRECTION) != A_OK) + { + /*Check if Peer closed socket while we were waiting*/ + if (ath_sock_context[index]->handle == 0) + { + return A_SOCK_INVALID; + } + if (ath_sock_context[index]->TCPCtrFlag == TCP_FIN) + { + QCADRV_PRINTF("clr sock in recv \r\n"); + clear_socket_context(index); + return A_SOCK_INVALID; + } + return A_ERROR; + } +#endif + } + data = (uint8_t *)A_NETBUF_DATA(a_netbuf_ptr); + } + + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + hdrlen = sizeof(SOCK_RECV_T); + /*If we are receiving data for a UDP socket, extract sockaddr info*/ + if ((ath_sock_context[index]->type == SOCK_DGRAM_TYPE) || (ath_sock_context[index]->type == SOCK_RAW_TYPE)) + { + A_MEMCPY(name, &((SOCK_RECV_T *)data)->name, sizeof(SOCKADDR_T)); + ((SOCKADDR_T *)name)->sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + ((SOCKADDR_T *)name)->sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + ((SOCKADDR_T *)name)->sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + *socklength = sizeof(SOCKADDR_T); + } + } + else if (ath_sock_context[index]->domain == ATH_AF_INET6) + { + hdrlen = sizeof(SOCK_RECV6_T); + /*If we are receiving data for a UDP socket, extract sockaddr info*/ + if ((ath_sock_context[index]->type == SOCK_DGRAM_TYPE) || (ath_sock_context[index]->type == SOCK_RAW_TYPE)) + { + A_MEMCPY(name, &((SOCK_RECV6_T *)data)->name6, sizeof(SOCKADDR_6_T)); + *socklength = sizeof(SOCKADDR_6_T); + } + } + else + { + A_ASSERT(0); + } + + if (!((ath_sock_context[index]->type == SOCK_STREAM_TYPE) && (ath_sock_context[index]->remaining_bytes != 0) && + (ath_sock_context[index]->old_netbuf != NULL))) + { + /*Remove custom header from payload*/ + A_NETBUF_PULL(a_netbuf_ptr, hdrlen); + } + + len = A_NETBUF_LEN(a_netbuf_ptr); + if (ath_sock_context[index]->type == SOCK_STREAM_TYPE) + { + if (len > length) + { + ath_sock_context[index]->remaining_bytes = (len - length); + len = length; + } + else + { + ath_sock_context[index]->remaining_bytes = 0; + ath_sock_context[index]->old_netbuf = NULL; + } + } + else + { + if (len > length) + { + len = length; // Discard excess bytes + } + } + + *buffer = (uint8_t *)A_NETBUF_DATA(a_netbuf_ptr); + if (ath_sock_context[index]->type == SOCK_STREAM_TYPE) + { + if (ath_sock_context[index]->remaining_bytes == 0) + { + A_NETBUF_ENQUEUE(&zero_copy_free_queue, a_netbuf_ptr); + } + else + { + A_NETBUF_PULL(a_netbuf_ptr, len); + ath_sock_context[index]->old_netbuf = a_netbuf_ptr; + } + } + else + { + A_NETBUF_ENQUEUE(&zero_copy_free_queue, a_netbuf_ptr); + } + return len; +} +#else + +/*****************************************************************************/ +/* Api_recvfrom - Non ZERO_COPY version of receive API.It will check socket's + * receive quese for pending packets. If a packet is available, + * it will be copied into user provided buffer. + * RETURNS: Number of bytes received or A_ERROR in case of failure + *****************************************************************************/ +int32_t Api_recvfrom( + void *pCxt, uint32_t handle, void *buffer, uint32_t length, uint32_t flags, void *name, socklen_t *socklength) +{ + int32_t index; + uint32_t len = 0, hdrlen = 0; + A_NETBUF *a_netbuf_ptr = NULL; + uint8_t *data = NULL; + SOCKET_CONTEXT_PTR pcustctxt; + + /*Find context*/ + if ((index = find_socket_context(handle, true)) == SOCKET_NOT_FOUND) + { + return A_SOCK_INVALID; + } + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); + + while ((a_netbuf_ptr = A_NETBUF_DEQUEUE(&(pcustctxt->rxqueue))) == NULL) + { +#if NON_BLOCKING_RX + /*No packet is available, return -1*/ + return A_ERROR; +#else + /*No packet available, block*/ + if (CUSTOM_BLOCK(pCxt, ath_sock_context[index], 0, RX_DIRECTION) != A_OK) + { + /*Check if Peer closed socket while we were waiting*/ + if (ath_sock_context[index]->handle == 0) + { + return A_SOCK_INVALID; + } + return A_ERROR; + } +#endif + } + + /*Extract custom header*/ + data = (uint8_t *)A_NETBUF_DATA(a_netbuf_ptr); + if (ath_sock_context[index]->domain == ATH_AF_INET) + { + hdrlen = sizeof(SOCK_RECV_T); + /*If we are receiving data for a UDP socket, extract sockaddr info*/ + if (ath_sock_context[index]->type == SOCK_DGRAM_TYPE) + { + A_MEMCPY(name, &((SOCK_RECV_T *)data)->name, sizeof(SOCKADDR_T)); + ((SOCKADDR_T *)name)->sin_port = A_CPU2LE16(((SOCKADDR_T *)name)->sin_port); + ((SOCKADDR_T *)name)->sin_family = A_CPU2LE16(((SOCKADDR_T *)name)->sin_family); + ((SOCKADDR_T *)name)->sin_addr = A_CPU2LE32(((SOCKADDR_T *)name)->sin_addr); + *socklength = sizeof(SOCKADDR_T); + } + } + else if (ath_sock_context[index]->domain == ATH_AF_INET6) + { + hdrlen = sizeof(SOCK_RECV6_T); + /*If we are receiving data for a UDP socket, extract sockaddr info*/ + if (ath_sock_context[index]->type == SOCK_DGRAM_TYPE) + { + A_MEMCPY(name, &((SOCK_RECV6_T *)data)->name6, sizeof(SOCKADDR_6_T)); + *socklength = sizeof(SOCKADDR_6_T); + } + } + else + { + A_ASSERT(0); + } + + /*Remove custom header from payload*/ + A_NETBUF_PULL(a_netbuf_ptr, hdrlen); + + len = A_NETBUF_LEN(a_netbuf_ptr); + + if (len > length) + len = length; // Discard excess bytes + + A_MEMCPY((uint8_t *)buffer, (uint8_t *)A_NETBUF_DATA(a_netbuf_ptr), len); + A_NETBUF_FREE(a_netbuf_ptr); + + return len; +} +#endif + +/*****************************************************************************/ +/* txpkt_free - function to free driver buffers that are allocated during send + * operations. The function is called from a_netbuf_free, after tx + * has successfully completed. + * If NON_BLOCKING_TX is defined, the user buffer is freed here + * as well. + * Note 1- called from driver thread. + * Note 2- should not be called from application + * RETURNS: none + *****************************************************************************/ +void txpkt_free(void *buffPtr) +{ + A_NETBUF_PTR a_netbuf_ptr = (A_NETBUF *)buffPtr; + DRV_BUFFER_PTR db_ptr = a_netbuf_ptr->native_orig; + +#if NON_BLOCKING_TX + SOCKET_CONTEXT_PTR pcustctxt = GET_SOCKET_CONTEXT((ATH_SOCKET_CONTEXT_PTR)db_ptr->context); + void *bufPtr = NULL; + /*In case of non blocking TX, driver should free the payload buffer*/ + A_MUTEX_ACQUIRE(&pcustctxt->nb_tx_mutex); + bufPtr = A_NETBUF_DEQUEUE(&(pcustctxt->non_block_queue)); + A_MUTEX_RELEASE(&pcustctxt->nb_tx_mutex); + + if (bufPtr != NULL) + { + A_FREE(((uint8_t *)bufPtr - TX_PKT_OVERHEAD), MALLOC_ID_CONTEXT); + bufPtr = NULL; + } + + /*We are done with netbuf, free Netbuf structure here*/ + A_FREE(a_netbuf_ptr->head, MALLOC_ID_NETBUFF); + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); +#else + /*Tail, data pointers within netbuf may have moved during previous TX, + reinit the netbuf so it can be used again*/ + a_netbuf_ptr = a_netbuf_reinit((void *)a_netbuf_ptr, TCP6_HEADROOM); + + /*Unblock the application thread*/ + UNBLOCK(db_ptr->context, TX_DIRECTION); +#endif +} + +/*****************************************************************************/ +/* custom_alloc - API for application to allocate a TX buffer. Here we ensure that + enough resources are available for a packet TX. All allocations + for a TX operation are made here. This includes Headroom, DB and netbuf. + If any allocation fails, this API returns NULL, and the host must + wait for some time to allow memory to be freed. + Note 1- Allocation may fail if too many packets are queued up for Transmission, + e.g. in the the non-blocking TX case. + Note 2- This API should ONLY be used for TX packets. + + * RETURNS: pointer to payload buffer for success and NULL for failure + *****************************************************************************/ +void *custom_alloc(uint32_t size) +{ + uint32_t total_size = 0; + uint8_t *buffer, *payload; + + /*Allocate TX buffer that will include- payload + headroom + Driver buffer + pointer to netbuf*/ + total_size = size + TX_PKT_OVERHEAD; + + /*Round off to 4 byte boundary*/ + if ((total_size % 4) != 0) + { + total_size += 4 - total_size % 4; + } + if ((buffer = A_MALLOC(total_size, MALLOC_ID_CONTEXT)) == NULL) + { + return NULL; + } + + /*Allocate netbuf with max possible headroom here so that there is no need to do it during TX*/ + if ((((TX_PACKET_PTR)buffer)->a_netbuf_ptr = A_NETBUF_ALLOC(TCP6_HEADROOM)) == NULL) + { + A_FREE(buffer, MALLOC_ID_CONTEXT); + return NULL; + } + /*Obtain pointer to start of payload*/ + payload = buffer + TX_PKT_OVERHEAD; + return payload; +} + +/*****************************************************************************/ +/* custom_free - API for application to free TX buffer. It should ONLY be called + * by the app if Blocking TX mode is enabled. It will free all allocations + * made during the custom_alloc + * RETURNS: none + *****************************************************************************/ +void custom_free(void *buf) +{ +#if (!NON_BLOCKING_TX) + uint8_t *buffer; + A_NETBUF_PTR a_netbuf_ptr; + + /*Move the the begining of TX buffer*/ + buffer = (uint8_t *)buf - TX_PKT_OVERHEAD; + + /*Get pointer to netbuf from TX buffer*/ + a_netbuf_ptr = ((TX_PACKET_PTR)buffer)->a_netbuf_ptr; + + if (a_netbuf_ptr) + { + /*We are done with netbuf, free Netbuf structure here*/ + A_FREE(a_netbuf_ptr->head, MALLOC_ID_NETBUFF); + A_FREE(a_netbuf_ptr, MALLOC_ID_NETBUFF_OBJ); + } + A_FREE(buffer, MALLOC_ID_CONTEXT); +#endif +} + +/*****************************************************************************/ +/* get_total_pkts_buffered - Returns number of packets buffered across all + * socket queues. + * RETURNS: number of packets + *****************************************************************************/ +uint32_t get_total_pkts_buffered(void) +{ + uint32_t index; + uint32_t totalPkts = 0; + + SOCKET_CONTEXT_PTR pcustctxt; + + for (index = 0; index < MAX_SOCKETS_SUPPORTED; index++) + { + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); + totalPkts += A_NETBUF_QUEUE_SIZE(&(pcustctxt->rxqueue)); + } + return totalPkts; +} + +#if ENABLE_SSL +/*****************************************************************************/ +/* SSL_ctx_new - Create new SSL context. This function must be called before + * using any other SSL functions. It needs to be called as either + * server or client + * Sslrole role - 1 = server, 2 = client + * int32_t inbufSize - initial inBuf size: Can grow + * int32_t outbufSize - outBuf size: Fixed + * int32_t reserved - currently not used (must be zero) + * Returns - SSL context handle on success or NULL on error (out of memory) + *****************************************************************************/ +SSL_CTX *SSL_ctx_new(SSL_ROLE_T role, int32_t inbufSize, int32_t outbufSize, int32_t reserved) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return NULL; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return NULL; + } + return ((SSL_CTX *)Api_SSL_ctx_new(pCxt, role, inbufSize, outbufSize, reserved)); +} + +/*****************************************************************************/ +/* SSL_ctx_free - Free the SSL context + * SSL_CTX *ctx - sslContext + *****************************************************************************/ +int32_t SSL_ctx_free(SSL_CTX *ctx) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_ctx_free(pCxt, ctx)); +} + +/*****************************************************************************/ +/* SSL_new - Create SSL connection object. When SSL transaction is done, close + * it with ssl_shutdown(). + * Note that the socket should subsequently also be closed. + * SSL_CTX *ctx - sslContext + * Return - SSL object handle on success or NULL on error (out of memory) + *****************************************************************************/ +SSL *SSL_new(SSL_CTX *ctx) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return NULL; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return NULL; + } + return (Api_SSL_new(pCxt, ctx)); +} + +/*****************************************************************************/ +/* SSL_set_fd - Attach given socket descriptor to the SSL connection + * SSL *ssl - SSL connection + * uint32_t fd - Socket descriptor + * Return - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t SSL_set_fd(SSL *ssl, uint32_t fd) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_set_fd(pCxt, ssl, fd)); +} + +/*****************************************************************************/ +/* SSL_accept - Initiate SSL handshake. + * SSL *ssl - SSL connection + * Returns - 1 on success, ESSL_HSDONE if handshake has already been performed. + * Negative error code otherwise. + *****************************************************************************/ +int32_t SSL_accept(SSL *ssl) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_accept(pCxt, ssl)); +} + +/*****************************************************************************/ +/* SSL_connect - Initiate SSL handshake. + * SSL *ssl - SSL connection + * Returns - 1 on success, ESSL_HSDONE if handshake has already been performed. + * Negative error code otherwise. + *****************************************************************************/ +int32_t SSL_connect(SSL *ssl) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_connect(pCxt, ssl)); +} + +/*****************************************************************************/ +/* SSL_shutdown - Close SSL connection. + * The socket must be closed by other means. + * SSL *ssl - SSL connection + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t SSL_shutdown(SSL *ssl) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_shutdown(pCxt, ssl)); +} + +/*****************************************************************************/ +/* SSL_configure - Configure a SSL connection. + * SSL *ssl - SSL connection + * SSL_CONFIG *cfg - pointer to struct holding the SSL configuration. + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t SSL_configure(SSL *ssl, SSL_CONFIG *cfg) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_configure(pCxt, ssl, cfg)); +} + +/*****************************************************************************/ +/* SSL_setCaList - Set a Certificate Authority (CA) list so SSL can perform + * certificate validation on the peer's certificate. + * You can only set one CA list, thus the CA list must include + * all root certificates required for the session. + * SSL *ssl - SSL connection + * SslCert cert -address of array of binary data + * uint32_t size - size of array + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t SSL_setCaList(SSL_CTX *ctx, SslCAList caList, uint32_t size) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_addCert(pCxt, ctx, SSL_CA_LIST, (uint8_t *)caList, size)); +} + +/*****************************************************************************/ +/* SSL_addCert - Add a certificate to the SharkSsl object. A SharkSsl object + * in server mode is required to have at least one certificate. + * SSL *ssl - SSL connection + * SslCert cert -address of array of binary data + * uint32_t size - size of array + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t SSL_addCert(SSL_CTX *ctx, SslCert cert, uint32_t size) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_addCert(pCxt, ctx, SSL_CERTIFICATE, (uint8_t *)cert, size)); +} + +/*****************************************************************************/ +/* SSL_storeCert - Store a certificate or CA list in FLASH. + * char *name - the name + * SslCert cert -address of array of binary data + * uint32_t size - size of array + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t SSL_storeCert(char *name, SslCert cert, uint32_t size) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_storeCert(pCxt, name, (uint8_t *)cert, size)); +} + +/*****************************************************************************/ +/* SSL_loadCert - Load a certificate or CA list from FLASH and store it in the + * sharkSs object. + * SSL_CERT_TYPE_T type - certificate or CA list + * char *name - the name + * Returns - 1 on success or negative error code on error (see SslErrors) + *****************************************************************************/ +int32_t SSL_loadCert(SSL_CTX *ctx, SSL_CERT_TYPE_T type, char *name) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_loadCert(pCxt, ctx, type, name)); +} + +int32_t SSL_listCert(SSL_FILE_NAME_LIST *fileNames) +{ + void *pCxt; + + if ((pCxt = ((QCA_CONTEXT_STRUCT_PTR)sslhandle)->MAC_CONTEXT_PTR) == NULL) + { + return A_ERROR; + } + + /*Wait for chip to be up*/ + if (A_OK != Api_DriverAccessCheck(pCxt, 1, ACCESS_REQUEST_IOCTL)) + { + return A_ERROR; + } + return (Api_SSL_listCert(pCxt, fileNames)); +} + +#if ZERO_COPY +/*****************************************************************************/ +/* SSL_read - ZERO_COPY version of SSL read function. It uses the ssl pointer + * to find the socket to read from.It will check socket's receive + * queues for pending packets. If a packet is available, it will be + * passed to the application without a memcopy. The application must + * call a zero_copy_free API to free this buffer. + * SSL *ssl - pointer to SSL connection object. + * void **buf - pointer to pointer holding the address of the receive buffer. + * int32_t num - The max number of bytes to read. + * Returns - Number of bytes received or A_ERROR in case of failure + *****************************************************************************/ +int32_t SSL_read(SSL *ssl, void **buf, int32_t num) +#else +int32_t SSL_read(SSL *ssl, void *buf, int32_t num) +#endif +{ + /* Find the socket used with this SSL connection */ + int32_t index = find_socket_context_from_ssl(ssl); + if (index == SOCKET_NOT_FOUND) + { + return A_ERROR; + } + + /* Read data from the socket */ + return t_recv(sslhandle, ath_sock_context[index]->handle, buf, num, 0); +} + +/*****************************************************************************/ +/* SSL_write - Encrypt and send data in buf and send them on the associated + * socket. The ssl pointer is sued to find the socket to send on. + * SSL *ssl - pointer to SSL connection object. + * void *buf - pointer to buffer holding the data to send. + * int32_t num - The number of bytes to send. + * Returns - Number of bytes sent on success or negative error code on error + *****************************************************************************/ +int32_t SSL_write(SSL *ssl, const void *buf, int32_t num) +{ + /* Find the socket used with this SSL connection */ + int32_t index = find_socket_context_from_ssl(ssl); + if (index == SOCKET_NOT_FOUND) + { + return A_ERROR; + } + + /* Send the data */ + return t_send(sslhandle, ath_sock_context[index]->handle, (uint8_t *)buf, num, 0); +} + +#endif // ENABLE_SSL +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/cust_api_stack_txrx.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/cust_api_stack_txrx.c new file mode 100644 index 00000000000..c50ede29e63 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/cust_api_stack_txrx.c @@ -0,0 +1,206 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include +#include "cust_netbuf.h" + +#if ENABLE_STACK_OFFLOAD +#include "atheros_stack_offload.h" +#include "common_stack_offload.h" +#include "custom_stack_offload.h" +#include "atheros_wifi.h" + +uint32_t Custom_Api_Send( + QCA_CONTEXT_STRUCT_PTR qca_ptr, PCB_PTR pcb_ptr, uint32_t size, uint32_t frags, uint32_t flags); + +uint32_t Custom_Api_Send(QCA_CONTEXT_STRUCT_PTR qca_ptr, PCB_PTR pcb_ptr, uint32_t size, uint32_t frags, uint32_t flags) +{ + return A_OK; +} + +uint32_t custom_sock_is_pending(ATH_SOCKET_CONTEXT *sock_context) +{ + uint32_t i, rtn; + for (rtn = 0, i = 0; i < (SOCK_CMD_LAST / 32 + 1); i++) + { + rtn |= sock_context->sock_st_mask[i]; + } + + return rtn; +} + +/*****************************************************************************/ +/* custom_receive_tcpip - Called by Custom_DeliverFrameToNetworkStack to + * deliver a data frame to the application thread. It unblocks a waiting + * application thread and queues the packet in the queue of the corresponding + * socket. If socket is not valid, the packet is dropped. + * void *pCxt - the driver context. + * void *pReq - the packet. + *****************************************************************************/ +A_STATUS custom_receive_tcpip(void *pCxt, void *pReq) +{ + A_NETBUF *a_netbuf_ptr = (A_NETBUF *)pReq; + int32_t index = 0, handle = 0; + uint8_t *data; + + SOCKET_CONTEXT_PTR pcustctxt = NULL; + + if (a_netbuf_ptr) + { + data = (uint8_t *)A_NETBUF_DATA(a_netbuf_ptr); + + /*Extract socket handle from custom header*/ + handle = A_CPU2LE32(*((uint32_t *)data)); + + /*Get index*/ + index = find_socket_context(handle, true); + if (index < 0 || index > MAX_SOCKETS_SUPPORTED) + { + last_driver_error = A_SOCKCXT_NOT_FOUND; + A_NETBUF_FREE(pReq); + return A_ERROR; + } + + if (custom_sock_is_pending(ath_sock_context[index]) != 0) + { + /* socket is pending a socket event so it cannot + * receive data packets */ + last_driver_error = A_SOCK_UNAVAILABLE; + A_NETBUF_FREE(pReq); + return A_ERROR; + } + + UNBLOCK_SELECT(pCxt); + pcustctxt = GET_SOCKET_CONTEXT(ath_sock_context[index]); + + // if(!IS_SOCKET_BLOCKED(ath_sock_context[index])) + /*To-Do- Remove this once drop ligic is implemented in firmware*/ + if (get_total_pkts_buffered() >= WLAN_CONFIG_NUM_PRE_ALLOC_RX_BUFFERS /*- 1*/) + { + QCADRV_PRINTF("%s dropping packets for %x\n", __FUNCTION__, handle); + A_NETBUF_FREE(pReq); + } + else + { + A_NETBUF_ENQUEUE(&(pcustctxt->rxqueue), a_netbuf_ptr); + UNBLOCK(ath_sock_context[index], RX_DIRECTION); + } + } + return A_OK; +} + +/*****************************************************************************/ +/* Custom_DeliverFrameToNetworkStack - Called by API_RxComplete to + * deliver a data frame to the network stack. This code will perform + * platform specific operations. + * void *pCxt - the driver context. + * void *pReq - the packet. + *****************************************************************************/ +void Custom_DeliverFrameToNetworkStack(void *pCxt, void *pReq) +{ + ATH_PROMISCUOUS_CB prom_cb = (ATH_PROMISCUOUS_CB)(GET_DRIVER_CXT(pCxt)->promiscuous_cb); + + if (GET_DRIVER_COMMON(pCxt)->promiscuous_mode) + { + prom_cb(pReq); + } + else + { + custom_receive_tcpip(pCxt, pReq); + } +} + +/*****************************************************************************/ +/* Custom_Api_Send - Entry point for MQX driver interface to send a packet. + * This is specific to MQX. This function is NOT called from within the + * driver. + * QCA_CONTEXT_STRUCT_PTR qca_ptr - the MQX driver context. + * PCB_PTR pcb_ptr - the MQX packet object. + * uint32_t size - the length in bytes of pcb_ptr. + * uint32_t frags - the number of fragments in pcb_ptr. + * uint32_t flags - optional flags for transmit. + *****************************************************************************/ +A_STATUS custom_send_tcpip(void *pCxt, + DRV_BUFFER_PTR db_ptr, + /* [IN] the packet to send */ + uint32_t size, + /* [IN] total size of the packet */ + uint32_t frags, + /* [IN] total fragments in the packet */ + uint8_t *header, + uint32_t header_size + + ) +{ + A_STATUS error = A_OK; + A_NETBUF *a_netbuf_ptr; + uint32_t total_hdr_size = header_size; + uint8_t *payloadPtr = db_ptr->bufFragment[0].payload; + + /* create an atheros pcb and continue or fail. */ + do + { + /*Get the netbuf pointer from TX packet*/ + a_netbuf_ptr = ((TX_PACKET_PTR)(payloadPtr - TX_PKT_OVERHEAD))->a_netbuf_ptr; + + a_netbuf_ptr->num_frags = (uint8_t)frags; + + A_NETBUF_PUT_DATA(a_netbuf_ptr, (uint8_t *)header, total_hdr_size); + // ensure there is enough headroom to complete the tx operation + if (A_NETBUF_HEADROOM(a_netbuf_ptr) < (int32_t)(sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR) + + sizeof(WMI_DATA_HDR) + HTC_HDR_LENGTH + WMI_MAX_TX_META_SZ)) + { + error = A_NO_MEMORY; + A_NETBUF_FREE(a_netbuf_ptr); + break; + } + // carry the original around until completion. + // it is freed by A_NETBUF_FREE + a_netbuf_ptr->native_orig = db_ptr; + + if (A_OK != Api_DataTxStart(pCxt, (void *)a_netbuf_ptr)) + { + error = A_ERROR; + break; + } + } while (0); + + if (error != A_OK) + { + /* in the event of api failure, the original pcb should be returned to the caller un-touched + * and the a_netbuf_ptr should be freed */ + if (error != A_NO_MEMORY) + A_NETBUF_FREE((void *)a_netbuf_ptr); + } + return error; +} + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/custom_stack_offload.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/custom_stack_offload.h new file mode 100644 index 00000000000..63fb067f085 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/custom_stack_offload.h @@ -0,0 +1,70 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _CUSTOM_STACK_OFFLOAD_H_ +#define _CUSTOM_STACK_OFFLOAD_H_ + +#if ENABLE_STACK_OFFLOAD + +#include + +#define IS_SOCKET_BLOCKED(index) isSocketBlocked((index)) + +/* Headroom definitions*/ +#define UDP_HEADROOM 44 +#define TCP_HEADROOM 64 +#define UDP6_HEADROOM 64 +#define TCP6_HEADROOM 88 +#define TCP6_HEADROOM_WITH_NO_OPTION 84 + +#define TX_PKT_OVERHEAD (TCP6_HEADROOM + sizeof(DRV_BUFFER) + sizeof(uint32_t)) + +#if ZERO_COPY +extern A_NETBUF_QUEUE_T zero_copy_free_queue; +#endif + +uint32_t isSocketBlocked(void *ctxt); + +A_STATUS custom_receive_tcpip(void *pCxt, void *pReq); +void txpkt_free(void *buffPtr); +A_STATUS custom_send_tcpip(void *pCxt, + /* [IN] the Ethernet state structure */ + DRV_BUFFER_PTR db_ptr, + /* [IN] the packet to send */ + uint32_t size, + /* [IN] total size of the packet */ + uint32_t frags, + /* [IN] total fragments in the packet */ + uint8_t *header, + uint32_t header_size + + ); + +void custom_free(void *buf); +void *custom_alloc(uint32_t size); +uint32_t get_total_pkts_buffered(void); +#endif // ENABLE_STACK_OFFLOAD +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/qca_structs.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/qca_structs.h new file mode 100644 index 00000000000..a3057c42b33 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/custom_src/stack_custom/qca_structs.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __qca_structs_h__ +#define __qca_structs_h__ + +/* Error codes */ +#define QCA_ERROR_BASE (0) +#define QCA_OK (0) +#define QCA_ERROR (QCA_ERROR_BASE | 0xff) /* general error */ + +#define QCA_ERR_INVALID_DEVICE (QCA_ERROR_BASE | 0x00) /* Device number out of range */ +#define QCA_ERR_ALLOC_PCB (QCA_ERROR_BASE | 0x03) /* Alloc PCBs failed */ +#define QCA_ERR_INIT_FAILED (QCA_ERROR_BASE | 0x12) /* Device failed to initialize */ +#define QCA_ERR_INVALID_INIT_PARAM (QCA_ERROR_BASE | 0x17) /* Invalid init. parameter */ + +typedef void *PCB_PTR; + +/* MODES */ +#define QCA_HALF_DUPLEX 0x1 +#define QCA_FULL_DUPLEX 0x0 +#define QCA_DUPLEX_MASK 0x1 +#define QCA_10M 0x02 +#define QCA_100M 0x04 +#define QCA_1G 0x06 +#define QCA_SPEED_MASK 0x0e +#define QCA_AUTONEGOTIATE 0x10 + +/* Security types */ +#define QCA_MEDIACTL_SECURITY_TYPE_NONE (0x00) +#define QCA_MEDIACTL_SECURITY_TYPE_WEP (0x01) +#define QCA_MEDIACTL_SECURITY_TYPE_WPA (0x02) +#define QCA_MEDIACTL_SECURITY_TYPE_WPA2 (0x03) + +/* Single cell network */ +#define QCA_MEDIACTL_MODE_ADHOC (1) +/* Multi cell network, roaming, ... */ +#define QCA_MEDIACTL_MODE_INFRA (2) +/* Synchronisation master or Access Point */ +#define QCA_MEDIACTL_MODE_MASTER (3) + +/* Media control definition types */ +#define IO_TYPE_MEDIACTL_WIFI 0x00 + +#define QCA_SET_MEDIACTL_COMMIT (IO_TYPE_MEDIACTL_WIFI | 0x01) +#define QCA_SET_MEDIACTL_FREQ (IO_TYPE_MEDIACTL_WIFI | 0x02) +#define QCA_SET_MEDIACTL_MODE (IO_TYPE_MEDIACTL_WIFI | 0x03) +#define QCA_SET_MEDIACTL_SCAN (IO_TYPE_MEDIACTL_WIFI | 0x04) +#define QCA_SET_MEDIACTL_ESSID (IO_TYPE_MEDIACTL_WIFI | 0x05) +#define QCA_SET_MEDIACTL_RTS (IO_TYPE_MEDIACTL_WIFI | 0x07) +#define QCA_SET_MEDIACTL_POWER (IO_TYPE_MEDIACTL_WIFI | 0x0A) +#define QCA_SET_MEDIACTL_SEC_TYPE (IO_TYPE_MEDIACTL_WIFI | 0x0B) +#define QCA_SET_MEDIACTL_PASSPHRASE (IO_TYPE_MEDIACTL_WIFI | 0x0C) +/* IOCTL's to get various features of WIFI device. */ +#define QCA_GET_MEDIACTL_MODE (IO_TYPE_MEDIACTL_WIFI | 0x10) +#define QCA_GET_MEDIACTL_SCAN (IO_TYPE_MEDIACTL_WIFI | 0x13) +#define QCA_GET_MEDIACTL_ESSID (IO_TYPE_MEDIACTL_WIFI | 0x14) +#define QCA_GET_MEDIACTL_POWER (IO_TYPE_MEDIACTL_WIFI | 0x19) +#define QCA_GET_MEDIACTL_SEC_TYPE (IO_TYPE_MEDIACTL_WIFI | 0x20) +#define QCA_MEDIACTL_IS_INITIALIZED (IO_TYPE_MEDIACTL_WIFI | 0x21) +#define QCA_MEDIACTL_VENDOR_SPECIFIC (IO_TYPE_MEDIACTL_WIFI | 0x81) + +typedef struct _scan_info +{ + uint8_t channel; + uint8_t ssid_len; + uint8_t rssi; + uint8_t security_enabled; + uint16_t beacon_period; + uint8_t preamble; + uint8_t bss_type; + uint8_t bssid[6]; + uint8_t ssid[32]; + uint8_t rsn_cipher; + uint8_t rsn_auth; + uint8_t wpa_cipher; + uint8_t wpa_auth; +} QCA_SCAN_INFO, *QCA_SCAN_INFO_PTR; + +typedef struct _scan_list +{ + int32_t num_scan_entries; + QCA_SCAN_INFO_PTR scan_info_list; +} QCA_SCAN_LIST, *QCA_SCAN_LIST_PTR; + +/* + * Generic format for most parameters that fit in an int + */ +typedef struct _param +{ + int32_t value; /* The value of the parameter itself */ + void *data; + uint32_t length; +} QCA_MEDIACTL_PARAM, *QCA_MEDIACTL_PARAM_PTR; + +typedef struct __essid +{ + char *essid; + uint16_t flags; + uint32_t length; +} QCA_ESSID, *QCA_ESSID_PTR; + +typedef unsigned char _qca_address[6]; + +/* Joined multicast groups */ +typedef struct qca_mcb_struct +{ + _qca_address GROUP; + uint32_t HASH; + struct qca_mcb_struct *NEXT; +} QCA_MCB_STRUCT, *QCA_MCB_STRUCT_PTR; + +/* The Ethernet state structure */ +struct qca_context_struct; + +typedef struct +{ + uint32_t (*INIT)(struct qca_context_struct *); + uint32_t (*STOP)(struct qca_context_struct *); + uint32_t (*SEND)(struct qca_context_struct *, PCB_PTR, uint32_t, uint32_t, uint32_t); + uint32_t (*PHY_READ)(struct qca_context_struct *, uint32_t, uint32_t *, uint32_t); + uint32_t (*PHY_WRITE)(struct qca_context_struct *, uint32_t, uint32_t, uint32_t); + uint32_t (*JOIN)(struct qca_context_struct *, struct qca_mcb_struct *); + uint32_t (*REJOIN)(struct qca_context_struct *); + uint32_t (*MEDIACTL)(struct qca_context_struct *, uint32_t command_id, void *inout_param); +} QCA_MAC_IF_STRUCT, *QCA_MAC_IF_STRUCT_PTR; + +typedef struct qca_if_struct +{ + const QCA_MAC_IF_STRUCT *MAC_IF; /* pointer to MAC interface struct */ + unsigned char MAC_NUMBER; /* MAC device number */ + unsigned char PHY_NUMBER; /* MAC device number for communication with PHY */ + unsigned char PHY_ADDRESS; /* PHY address */ +} QCA_IF_STRUCT, *QCA_IF_STRUCT_PTR; + +typedef void *_qca_handle; + +typedef enum +{ + Half_Duplex_10M = (QCA_HALF_DUPLEX | QCA_10M), + Full_Duplex_10M = (QCA_FULL_DUPLEX | QCA_10M), + Half_Duplex_100M = (QCA_HALF_DUPLEX | QCA_100M), + Full_Duplex_100M = (QCA_FULL_DUPLEX | QCA_100M), + Half_Duplex_1G = (QCA_HALF_DUPLEX | QCA_1G), + Full_Duplex_1G = (QCA_FULL_DUPLEX | QCA_1G), + Auto_Negotiate = QCA_AUTONEGOTIATE +} QCA_mode; + +typedef struct qca_param_struct +{ + const QCA_IF_STRUCT *QCA_IF; + QCA_mode MODE; + uint32_t OPTIONS; + uint16_t NUM_RX_PCBS; + void *MAC_PARAM; + +} QCA_PARAM_STRUCT; + +typedef struct qca_context_struct +{ + const QCA_PARAM_STRUCT *PARAM_PTR; + _qca_address ADDRESS; + void *MAC_CONTEXT_PTR; +} QCA_CONTEXT_STRUCT, *QCA_CONTEXT_STRUCT_PTR; +#endif +/* EOF */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/AR6K_version.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/AR6K_version.h new file mode 100644 index 00000000000..f2a2305b5ae --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/AR6K_version.h @@ -0,0 +1,64 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 3 // corresponds to release X._._._._ +#define __VER_MINOR_ 3 // corresponds to release _.X._._._ +#define __VER_PATCH_ 0 // corresponds to release _._.X._. +#define __VER_REV_ 0 // corresponds to release _._._.X._ <-- Increment This field manually for every build + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 0 + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bite 18-23: Patch number + * Bits 8-17: Revision number (Increment this every build) + * Bits 0-7: build number which is automatically updated + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION \ + ((__VER_MAJOR_ << VER_MAJOR_BIT_OFFSET) + (__VER_MINOR_ << VER_MINOR_BIT_OFFSET) + \ + ((__VER_PATCH_ & 0xFF) << VER_PATCH_BIT_OFFSET) + (((__BUILD_NUMBER_)&0xFFFF) << VER_BUILD_NUM_BIT_OFFSET)) + +/* ABI Version. Reflects the version of binary interface exposed by AR6K target firmware. Needs to be incremented by 1 + * for any change in the firmware that requires upgrade of the driver on the host side for the change to work correctly + */ +#define ABI_VERSION_MAJOR (1) +#define ABI_VERSION_MINOR (0) +#define ABI_MAJOR_OFFSET (16) +#define ABI_MAJOR_MASK (0xffff0000) +#define ABI_MINOR_OFFSET (0) +#define ABI_MINOR_MASK (0x0000ffff) +#define AR6K_ABI_VERSION ((ABI_VERSION_MAJOR << ABI_MAJOR_OFFSET) | (ABI_VERSION_MINOR << ABI_MINOR_OFFSET)) diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_apb_map.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_apb_map.h new file mode 100644 index 00000000000..50400389594 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_apb_map.h @@ -0,0 +1,38 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _APB_MAP_H_ +#define _APB_MAP_H_ + +#define RTC_BASE_ADDRESS 0x00004000 +#define VMC_BASE_ADDRESS 0x00008000 +#define UART_BASE_ADDRESS 0x0000c000 +#define SI_BASE_ADDRESS 0x00010000 +#define GPIO_BASE_ADDRESS 0x00014000 +#define MBOX_BASE_ADDRESS 0x00018000 +#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define MAC_BASE_ADDRESS 0x00020000 + +#endif /* _APB_MAP_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_gpio_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_gpio_reg.h new file mode 100644 index 00000000000..5b7b6ff94c8 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_gpio_reg.h @@ -0,0 +1,1001 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _GPIO_REG_REG_H_ +#define _GPIO_REG_REG_H_ + +#define GPIO_OUT_ADDRESS 0x00000000 +#define GPIO_OUT_OFFSET 0x00000000 +#define GPIO_OUT_DATA_MSB 17 +#define GPIO_OUT_DATA_LSB 0 +#define GPIO_OUT_DATA_MASK 0x0003ffff +#define GPIO_OUT_DATA_GET(x) (((x)&GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB) +#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK) + +#define GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define GPIO_OUT_W1TS_OFFSET 0x00000004 +#define GPIO_OUT_W1TS_DATA_MSB 17 +#define GPIO_OUT_W1TS_DATA_LSB 0 +#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TS_DATA_GET(x) (((x)&GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB) +#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK) + +#define GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define GPIO_OUT_W1TC_OFFSET 0x00000008 +#define GPIO_OUT_W1TC_DATA_MSB 17 +#define GPIO_OUT_W1TC_DATA_LSB 0 +#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TC_DATA_GET(x) (((x)&GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB) +#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK) + +#define GPIO_ENABLE_ADDRESS 0x0000000c +#define GPIO_ENABLE_OFFSET 0x0000000c +#define GPIO_ENABLE_DATA_MSB 17 +#define GPIO_ENABLE_DATA_LSB 0 +#define GPIO_ENABLE_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_DATA_GET(x) (((x)&GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB) +#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK) + +#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define GPIO_ENABLE_W1TS_DATA_MSB 17 +#define GPIO_ENABLE_W1TS_DATA_LSB 0 +#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x)&GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB) +#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK) + +#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define GPIO_ENABLE_W1TC_DATA_MSB 17 +#define GPIO_ENABLE_W1TC_DATA_LSB 0 +#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x)&GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB) +#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK) + +#define GPIO_IN_ADDRESS 0x00000018 +#define GPIO_IN_OFFSET 0x00000018 +#define GPIO_IN_DATA_MSB 17 +#define GPIO_IN_DATA_LSB 0 +#define GPIO_IN_DATA_MASK 0x0003ffff +#define GPIO_IN_DATA_GET(x) (((x)&GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB) +#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK) + +#define GPIO_STATUS_ADDRESS 0x0000001c +#define GPIO_STATUS_OFFSET 0x0000001c +#define GPIO_STATUS_INTERRUPT_MSB 17 +#define GPIO_STATUS_INTERRUPT_LSB 0 +#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_INTERRUPT_GET(x) (((x)&GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB) +#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x)&GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x)&GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define GPIO_PIN0_ADDRESS 0x00000028 +#define GPIO_PIN0_OFFSET 0x00000028 +#define GPIO_PIN0_CONFIG_MSB 12 +#define GPIO_PIN0_CONFIG_LSB 11 +#define GPIO_PIN0_CONFIG_MASK 0x00001800 +#define GPIO_PIN0_CONFIG_GET(x) (((x)&GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define GPIO_PIN0_INT_TYPE_MSB 9 +#define GPIO_PIN0_INT_TYPE_LSB 7 +#define GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN0_INT_TYPE_GET(x) (((x)&GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB) +#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK) +#define GPIO_PIN0_PAD_DRIVER_MSB 2 +#define GPIO_PIN0_PAD_DRIVER_LSB 2 +#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x)&GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB) +#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK) +#define GPIO_PIN0_SOURCE_MSB 0 +#define GPIO_PIN0_SOURCE_LSB 0 +#define GPIO_PIN0_SOURCE_MASK 0x00000001 +#define GPIO_PIN0_SOURCE_GET(x) (((x)&GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB) +#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK) + +#define GPIO_PIN1_ADDRESS 0x0000002c +#define GPIO_PIN1_OFFSET 0x0000002c +#define GPIO_PIN1_CONFIG_MSB 12 +#define GPIO_PIN1_CONFIG_LSB 11 +#define GPIO_PIN1_CONFIG_MASK 0x00001800 +#define GPIO_PIN1_CONFIG_GET(x) (((x)&GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB) +#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define GPIO_PIN1_INT_TYPE_MSB 9 +#define GPIO_PIN1_INT_TYPE_LSB 7 +#define GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN1_INT_TYPE_GET(x) (((x)&GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB) +#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK) +#define GPIO_PIN1_PAD_DRIVER_MSB 2 +#define GPIO_PIN1_PAD_DRIVER_LSB 2 +#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x)&GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB) +#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK) +#define GPIO_PIN1_SOURCE_MSB 0 +#define GPIO_PIN1_SOURCE_LSB 0 +#define GPIO_PIN1_SOURCE_MASK 0x00000001 +#define GPIO_PIN1_SOURCE_GET(x) (((x)&GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB) +#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK) + +#define GPIO_PIN2_ADDRESS 0x00000030 +#define GPIO_PIN2_OFFSET 0x00000030 +#define GPIO_PIN2_CONFIG_MSB 12 +#define GPIO_PIN2_CONFIG_LSB 11 +#define GPIO_PIN2_CONFIG_MASK 0x00001800 +#define GPIO_PIN2_CONFIG_GET(x) (((x)&GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB) +#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define GPIO_PIN2_INT_TYPE_MSB 9 +#define GPIO_PIN2_INT_TYPE_LSB 7 +#define GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN2_INT_TYPE_GET(x) (((x)&GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB) +#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK) +#define GPIO_PIN2_PAD_DRIVER_MSB 2 +#define GPIO_PIN2_PAD_DRIVER_LSB 2 +#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x)&GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB) +#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK) +#define GPIO_PIN2_SOURCE_MSB 0 +#define GPIO_PIN2_SOURCE_LSB 0 +#define GPIO_PIN2_SOURCE_MASK 0x00000001 +#define GPIO_PIN2_SOURCE_GET(x) (((x)&GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB) +#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK) + +#define GPIO_PIN3_ADDRESS 0x00000034 +#define GPIO_PIN3_OFFSET 0x00000034 +#define GPIO_PIN3_CONFIG_MSB 12 +#define GPIO_PIN3_CONFIG_LSB 11 +#define GPIO_PIN3_CONFIG_MASK 0x00001800 +#define GPIO_PIN3_CONFIG_GET(x) (((x)&GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB) +#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define GPIO_PIN3_INT_TYPE_MSB 9 +#define GPIO_PIN3_INT_TYPE_LSB 7 +#define GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN3_INT_TYPE_GET(x) (((x)&GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB) +#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK) +#define GPIO_PIN3_PAD_DRIVER_MSB 2 +#define GPIO_PIN3_PAD_DRIVER_LSB 2 +#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x)&GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB) +#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK) +#define GPIO_PIN3_SOURCE_MSB 0 +#define GPIO_PIN3_SOURCE_LSB 0 +#define GPIO_PIN3_SOURCE_MASK 0x00000001 +#define GPIO_PIN3_SOURCE_GET(x) (((x)&GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB) +#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK) + +#define GPIO_PIN4_ADDRESS 0x00000038 +#define GPIO_PIN4_OFFSET 0x00000038 +#define GPIO_PIN4_CONFIG_MSB 12 +#define GPIO_PIN4_CONFIG_LSB 11 +#define GPIO_PIN4_CONFIG_MASK 0x00001800 +#define GPIO_PIN4_CONFIG_GET(x) (((x)&GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB) +#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define GPIO_PIN4_INT_TYPE_MSB 9 +#define GPIO_PIN4_INT_TYPE_LSB 7 +#define GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN4_INT_TYPE_GET(x) (((x)&GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB) +#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK) +#define GPIO_PIN4_PAD_DRIVER_MSB 2 +#define GPIO_PIN4_PAD_DRIVER_LSB 2 +#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x)&GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB) +#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK) +#define GPIO_PIN4_SOURCE_MSB 0 +#define GPIO_PIN4_SOURCE_LSB 0 +#define GPIO_PIN4_SOURCE_MASK 0x00000001 +#define GPIO_PIN4_SOURCE_GET(x) (((x)&GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB) +#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK) + +#define GPIO_PIN5_ADDRESS 0x0000003c +#define GPIO_PIN5_OFFSET 0x0000003c +#define GPIO_PIN5_CONFIG_MSB 12 +#define GPIO_PIN5_CONFIG_LSB 11 +#define GPIO_PIN5_CONFIG_MASK 0x00001800 +#define GPIO_PIN5_CONFIG_GET(x) (((x)&GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB) +#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define GPIO_PIN5_INT_TYPE_MSB 9 +#define GPIO_PIN5_INT_TYPE_LSB 7 +#define GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN5_INT_TYPE_GET(x) (((x)&GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB) +#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK) +#define GPIO_PIN5_PAD_DRIVER_MSB 2 +#define GPIO_PIN5_PAD_DRIVER_LSB 2 +#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x)&GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB) +#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK) +#define GPIO_PIN5_SOURCE_MSB 0 +#define GPIO_PIN5_SOURCE_LSB 0 +#define GPIO_PIN5_SOURCE_MASK 0x00000001 +#define GPIO_PIN5_SOURCE_GET(x) (((x)&GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB) +#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK) + +#define GPIO_PIN6_ADDRESS 0x00000040 +#define GPIO_PIN6_OFFSET 0x00000040 +#define GPIO_PIN6_CONFIG_MSB 12 +#define GPIO_PIN6_CONFIG_LSB 11 +#define GPIO_PIN6_CONFIG_MASK 0x00001800 +#define GPIO_PIN6_CONFIG_GET(x) (((x)&GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB) +#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define GPIO_PIN6_INT_TYPE_MSB 9 +#define GPIO_PIN6_INT_TYPE_LSB 7 +#define GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN6_INT_TYPE_GET(x) (((x)&GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB) +#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK) +#define GPIO_PIN6_PAD_DRIVER_MSB 2 +#define GPIO_PIN6_PAD_DRIVER_LSB 2 +#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x)&GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB) +#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK) +#define GPIO_PIN6_SOURCE_MSB 0 +#define GPIO_PIN6_SOURCE_LSB 0 +#define GPIO_PIN6_SOURCE_MASK 0x00000001 +#define GPIO_PIN6_SOURCE_GET(x) (((x)&GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB) +#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK) + +#define GPIO_PIN7_ADDRESS 0x00000044 +#define GPIO_PIN7_OFFSET 0x00000044 +#define GPIO_PIN7_CONFIG_MSB 12 +#define GPIO_PIN7_CONFIG_LSB 11 +#define GPIO_PIN7_CONFIG_MASK 0x00001800 +#define GPIO_PIN7_CONFIG_GET(x) (((x)&GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB) +#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define GPIO_PIN7_INT_TYPE_MSB 9 +#define GPIO_PIN7_INT_TYPE_LSB 7 +#define GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN7_INT_TYPE_GET(x) (((x)&GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB) +#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK) +#define GPIO_PIN7_PAD_DRIVER_MSB 2 +#define GPIO_PIN7_PAD_DRIVER_LSB 2 +#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x)&GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB) +#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK) +#define GPIO_PIN7_SOURCE_MSB 0 +#define GPIO_PIN7_SOURCE_LSB 0 +#define GPIO_PIN7_SOURCE_MASK 0x00000001 +#define GPIO_PIN7_SOURCE_GET(x) (((x)&GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB) +#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK) + +#define GPIO_PIN8_ADDRESS 0x00000048 +#define GPIO_PIN8_OFFSET 0x00000048 +#define GPIO_PIN8_CONFIG_MSB 12 +#define GPIO_PIN8_CONFIG_LSB 11 +#define GPIO_PIN8_CONFIG_MASK 0x00001800 +#define GPIO_PIN8_CONFIG_GET(x) (((x)&GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB) +#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define GPIO_PIN8_INT_TYPE_MSB 9 +#define GPIO_PIN8_INT_TYPE_LSB 7 +#define GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN8_INT_TYPE_GET(x) (((x)&GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB) +#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK) +#define GPIO_PIN8_PAD_DRIVER_MSB 2 +#define GPIO_PIN8_PAD_DRIVER_LSB 2 +#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x)&GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB) +#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK) +#define GPIO_PIN8_SOURCE_MSB 0 +#define GPIO_PIN8_SOURCE_LSB 0 +#define GPIO_PIN8_SOURCE_MASK 0x00000001 +#define GPIO_PIN8_SOURCE_GET(x) (((x)&GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB) +#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK) + +#define GPIO_PIN9_ADDRESS 0x0000004c +#define GPIO_PIN9_OFFSET 0x0000004c +#define GPIO_PIN9_CONFIG_MSB 12 +#define GPIO_PIN9_CONFIG_LSB 11 +#define GPIO_PIN9_CONFIG_MASK 0x00001800 +#define GPIO_PIN9_CONFIG_GET(x) (((x)&GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB) +#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define GPIO_PIN9_INT_TYPE_MSB 9 +#define GPIO_PIN9_INT_TYPE_LSB 7 +#define GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN9_INT_TYPE_GET(x) (((x)&GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB) +#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK) +#define GPIO_PIN9_PAD_DRIVER_MSB 2 +#define GPIO_PIN9_PAD_DRIVER_LSB 2 +#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x)&GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB) +#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK) +#define GPIO_PIN9_SOURCE_MSB 0 +#define GPIO_PIN9_SOURCE_LSB 0 +#define GPIO_PIN9_SOURCE_MASK 0x00000001 +#define GPIO_PIN9_SOURCE_GET(x) (((x)&GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB) +#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK) + +#define GPIO_PIN10_ADDRESS 0x00000050 +#define GPIO_PIN10_OFFSET 0x00000050 +#define GPIO_PIN10_CONFIG_MSB 12 +#define GPIO_PIN10_CONFIG_LSB 11 +#define GPIO_PIN10_CONFIG_MASK 0x00001800 +#define GPIO_PIN10_CONFIG_GET(x) (((x)&GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB) +#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define GPIO_PIN10_INT_TYPE_MSB 9 +#define GPIO_PIN10_INT_TYPE_LSB 7 +#define GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN10_INT_TYPE_GET(x) (((x)&GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB) +#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK) +#define GPIO_PIN10_PAD_DRIVER_MSB 2 +#define GPIO_PIN10_PAD_DRIVER_LSB 2 +#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x)&GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB) +#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK) +#define GPIO_PIN10_SOURCE_MSB 0 +#define GPIO_PIN10_SOURCE_LSB 0 +#define GPIO_PIN10_SOURCE_MASK 0x00000001 +#define GPIO_PIN10_SOURCE_GET(x) (((x)&GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB) +#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK) + +#define GPIO_PIN11_ADDRESS 0x00000054 +#define GPIO_PIN11_OFFSET 0x00000054 +#define GPIO_PIN11_CONFIG_MSB 12 +#define GPIO_PIN11_CONFIG_LSB 11 +#define GPIO_PIN11_CONFIG_MASK 0x00001800 +#define GPIO_PIN11_CONFIG_GET(x) (((x)&GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB) +#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define GPIO_PIN11_INT_TYPE_MSB 9 +#define GPIO_PIN11_INT_TYPE_LSB 7 +#define GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN11_INT_TYPE_GET(x) (((x)&GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB) +#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK) +#define GPIO_PIN11_PAD_DRIVER_MSB 2 +#define GPIO_PIN11_PAD_DRIVER_LSB 2 +#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x)&GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB) +#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK) +#define GPIO_PIN11_SOURCE_MSB 0 +#define GPIO_PIN11_SOURCE_LSB 0 +#define GPIO_PIN11_SOURCE_MASK 0x00000001 +#define GPIO_PIN11_SOURCE_GET(x) (((x)&GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB) +#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK) + +#define GPIO_PIN12_ADDRESS 0x00000058 +#define GPIO_PIN12_OFFSET 0x00000058 +#define GPIO_PIN12_CONFIG_MSB 12 +#define GPIO_PIN12_CONFIG_LSB 11 +#define GPIO_PIN12_CONFIG_MASK 0x00001800 +#define GPIO_PIN12_CONFIG_GET(x) (((x)&GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB) +#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define GPIO_PIN12_INT_TYPE_MSB 9 +#define GPIO_PIN12_INT_TYPE_LSB 7 +#define GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN12_INT_TYPE_GET(x) (((x)&GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB) +#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK) +#define GPIO_PIN12_PAD_DRIVER_MSB 2 +#define GPIO_PIN12_PAD_DRIVER_LSB 2 +#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x)&GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB) +#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK) +#define GPIO_PIN12_SOURCE_MSB 0 +#define GPIO_PIN12_SOURCE_LSB 0 +#define GPIO_PIN12_SOURCE_MASK 0x00000001 +#define GPIO_PIN12_SOURCE_GET(x) (((x)&GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB) +#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK) + +#define GPIO_PIN13_ADDRESS 0x0000005c +#define GPIO_PIN13_OFFSET 0x0000005c +#define GPIO_PIN13_CONFIG_MSB 12 +#define GPIO_PIN13_CONFIG_LSB 11 +#define GPIO_PIN13_CONFIG_MASK 0x00001800 +#define GPIO_PIN13_CONFIG_GET(x) (((x)&GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB) +#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define GPIO_PIN13_INT_TYPE_MSB 9 +#define GPIO_PIN13_INT_TYPE_LSB 7 +#define GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN13_INT_TYPE_GET(x) (((x)&GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB) +#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK) +#define GPIO_PIN13_PAD_DRIVER_MSB 2 +#define GPIO_PIN13_PAD_DRIVER_LSB 2 +#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x)&GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB) +#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK) +#define GPIO_PIN13_SOURCE_MSB 0 +#define GPIO_PIN13_SOURCE_LSB 0 +#define GPIO_PIN13_SOURCE_MASK 0x00000001 +#define GPIO_PIN13_SOURCE_GET(x) (((x)&GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB) +#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK) + +#define GPIO_PIN14_ADDRESS 0x00000060 +#define GPIO_PIN14_OFFSET 0x00000060 +#define GPIO_PIN14_CONFIG_MSB 12 +#define GPIO_PIN14_CONFIG_LSB 11 +#define GPIO_PIN14_CONFIG_MASK 0x00001800 +#define GPIO_PIN14_CONFIG_GET(x) (((x)&GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB) +#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define GPIO_PIN14_INT_TYPE_MSB 9 +#define GPIO_PIN14_INT_TYPE_LSB 7 +#define GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN14_INT_TYPE_GET(x) (((x)&GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB) +#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK) +#define GPIO_PIN14_PAD_DRIVER_MSB 2 +#define GPIO_PIN14_PAD_DRIVER_LSB 2 +#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x)&GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB) +#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK) +#define GPIO_PIN14_SOURCE_MSB 0 +#define GPIO_PIN14_SOURCE_LSB 0 +#define GPIO_PIN14_SOURCE_MASK 0x00000001 +#define GPIO_PIN14_SOURCE_GET(x) (((x)&GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB) +#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK) + +#define GPIO_PIN15_ADDRESS 0x00000064 +#define GPIO_PIN15_OFFSET 0x00000064 +#define GPIO_PIN15_CONFIG_MSB 12 +#define GPIO_PIN15_CONFIG_LSB 11 +#define GPIO_PIN15_CONFIG_MASK 0x00001800 +#define GPIO_PIN15_CONFIG_GET(x) (((x)&GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB) +#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define GPIO_PIN15_INT_TYPE_MSB 9 +#define GPIO_PIN15_INT_TYPE_LSB 7 +#define GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN15_INT_TYPE_GET(x) (((x)&GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB) +#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK) +#define GPIO_PIN15_PAD_DRIVER_MSB 2 +#define GPIO_PIN15_PAD_DRIVER_LSB 2 +#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x)&GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB) +#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK) +#define GPIO_PIN15_SOURCE_MSB 0 +#define GPIO_PIN15_SOURCE_LSB 0 +#define GPIO_PIN15_SOURCE_MASK 0x00000001 +#define GPIO_PIN15_SOURCE_GET(x) (((x)&GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB) +#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK) + +#define GPIO_PIN16_ADDRESS 0x00000068 +#define GPIO_PIN16_OFFSET 0x00000068 +#define GPIO_PIN16_CONFIG_MSB 12 +#define GPIO_PIN16_CONFIG_LSB 11 +#define GPIO_PIN16_CONFIG_MASK 0x00001800 +#define GPIO_PIN16_CONFIG_GET(x) (((x)&GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB) +#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define GPIO_PIN16_INT_TYPE_MSB 9 +#define GPIO_PIN16_INT_TYPE_LSB 7 +#define GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN16_INT_TYPE_GET(x) (((x)&GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB) +#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK) +#define GPIO_PIN16_PAD_DRIVER_MSB 2 +#define GPIO_PIN16_PAD_DRIVER_LSB 2 +#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x)&GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB) +#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK) +#define GPIO_PIN16_SOURCE_MSB 0 +#define GPIO_PIN16_SOURCE_LSB 0 +#define GPIO_PIN16_SOURCE_MASK 0x00000001 +#define GPIO_PIN16_SOURCE_GET(x) (((x)&GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB) +#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK) + +#define GPIO_PIN17_ADDRESS 0x0000006c +#define GPIO_PIN17_OFFSET 0x0000006c +#define GPIO_PIN17_CONFIG_MSB 12 +#define GPIO_PIN17_CONFIG_LSB 11 +#define GPIO_PIN17_CONFIG_MASK 0x00001800 +#define GPIO_PIN17_CONFIG_GET(x) (((x)&GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB) +#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x)&GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define GPIO_PIN17_INT_TYPE_MSB 9 +#define GPIO_PIN17_INT_TYPE_LSB 7 +#define GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN17_INT_TYPE_GET(x) (((x)&GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB) +#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK) +#define GPIO_PIN17_PAD_DRIVER_MSB 2 +#define GPIO_PIN17_PAD_DRIVER_LSB 2 +#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x)&GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB) +#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK) +#define GPIO_PIN17_SOURCE_MSB 0 +#define GPIO_PIN17_SOURCE_LSB 0 +#define GPIO_PIN17_SOURCE_MASK 0x00000001 +#define GPIO_PIN17_SOURCE_GET(x) (((x)&GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB) +#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK) + +#define SDIO_PIN_ADDRESS 0x00000070 +#define SDIO_PIN_OFFSET 0x00000070 +#define SDIO_PIN_PAD_PULL_MSB 3 +#define SDIO_PIN_PAD_PULL_LSB 2 +#define SDIO_PIN_PAD_PULL_MASK 0x0000000c +#define SDIO_PIN_PAD_PULL_GET(x) (((x)&SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB) +#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK) +#define SDIO_PIN_PAD_STRENGTH_MSB 1 +#define SDIO_PIN_PAD_STRENGTH_LSB 0 +#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x)&SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB) +#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK) + +#define CLK_REQ_PIN_ADDRESS 0x00000074 +#define CLK_REQ_PIN_OFFSET 0x00000074 +#define CLK_REQ_PIN_PAD_PULL_MSB 3 +#define CLK_REQ_PIN_PAD_PULL_LSB 2 +#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c +#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x)&CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB) +#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK) +#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 +#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 +#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 +#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x)&CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) +#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) + +#define SIGMA_DELTA_ADDRESS 0x00000078 +#define SIGMA_DELTA_OFFSET 0x00000078 +#define SIGMA_DELTA_ENABLE_MSB 16 +#define SIGMA_DELTA_ENABLE_LSB 16 +#define SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define SIGMA_DELTA_ENABLE_GET(x) (((x)&SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB) +#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK) +#define SIGMA_DELTA_PRESCALAR_MSB 15 +#define SIGMA_DELTA_PRESCALAR_LSB 8 +#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define SIGMA_DELTA_PRESCALAR_GET(x) (((x)&SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB) +#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK) +#define SIGMA_DELTA_TARGET_MSB 7 +#define SIGMA_DELTA_TARGET_LSB 0 +#define SIGMA_DELTA_TARGET_MASK 0x000000ff +#define SIGMA_DELTA_TARGET_GET(x) (((x)&SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB) +#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK) + +#define DEBUG_CONTROL_ADDRESS 0x0000007c +#define DEBUG_CONTROL_OFFSET 0x0000007c +#define DEBUG_CONTROL_OBS_OE_L_MSB 1 +#define DEBUG_CONTROL_OBS_OE_L_LSB 1 +#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 +#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x)&DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) +#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) +#define DEBUG_CONTROL_ENABLE_MSB 0 +#define DEBUG_CONTROL_ENABLE_LSB 0 +#define DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define DEBUG_CONTROL_ENABLE_GET(x) (((x)&DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB) +#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK) + +#define DEBUG_INPUT_SEL_ADDRESS 0x00000080 +#define DEBUG_INPUT_SEL_OFFSET 0x00000080 +#define DEBUG_INPUT_SEL_SRC_MSB 3 +#define DEBUG_INPUT_SEL_SRC_LSB 0 +#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define DEBUG_INPUT_SEL_SRC_GET(x) (((x)&DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB) +#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK) + +#define DEBUG_OUT_ADDRESS 0x00000084 +#define DEBUG_OUT_OFFSET 0x00000084 +#define DEBUG_OUT_DATA_MSB 17 +#define DEBUG_OUT_DATA_LSB 0 +#define DEBUG_OUT_DATA_MASK 0x0003ffff +#define DEBUG_OUT_DATA_GET(x) (((x)&DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB) +#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK) + +#define LA_CONTROL_ADDRESS 0x00000088 +#define LA_CONTROL_OFFSET 0x00000088 +#define LA_CONTROL_RUN_MSB 1 +#define LA_CONTROL_RUN_LSB 1 +#define LA_CONTROL_RUN_MASK 0x00000002 +#define LA_CONTROL_RUN_GET(x) (((x)&LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB) +#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK) +#define LA_CONTROL_TRIGGERED_MSB 0 +#define LA_CONTROL_TRIGGERED_LSB 0 +#define LA_CONTROL_TRIGGERED_MASK 0x00000001 +#define LA_CONTROL_TRIGGERED_GET(x) (((x)&LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB) +#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK) + +#define LA_CLOCK_ADDRESS 0x0000008c +#define LA_CLOCK_OFFSET 0x0000008c +#define LA_CLOCK_DIV_MSB 7 +#define LA_CLOCK_DIV_LSB 0 +#define LA_CLOCK_DIV_MASK 0x000000ff +#define LA_CLOCK_DIV_GET(x) (((x)&LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB) +#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK) + +#define LA_STATUS_ADDRESS 0x00000090 +#define LA_STATUS_OFFSET 0x00000090 +#define LA_STATUS_INTERRUPT_MSB 0 +#define LA_STATUS_INTERRUPT_LSB 0 +#define LA_STATUS_INTERRUPT_MASK 0x00000001 +#define LA_STATUS_INTERRUPT_GET(x) (((x)&LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB) +#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK) + +#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 +#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 +#define LA_TRIGGER_SAMPLE_COUNT_MSB 15 +#define LA_TRIGGER_SAMPLE_COUNT_LSB 0 +#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff +#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x)&LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) +#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) + +#define LA_TRIGGER_POSITION_ADDRESS 0x00000098 +#define LA_TRIGGER_POSITION_OFFSET 0x00000098 +#define LA_TRIGGER_POSITION_VALUE_MSB 15 +#define LA_TRIGGER_POSITION_VALUE_LSB 0 +#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff +#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x)&LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) +#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) + +#define LA_PRE_TRIGGER_ADDRESS 0x0000009c +#define LA_PRE_TRIGGER_OFFSET 0x0000009c +#define LA_PRE_TRIGGER_COUNT_MSB 15 +#define LA_PRE_TRIGGER_COUNT_LSB 0 +#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_PRE_TRIGGER_COUNT_GET(x) (((x)&LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB) +#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK) + +#define LA_POST_TRIGGER_ADDRESS 0x000000a0 +#define LA_POST_TRIGGER_OFFSET 0x000000a0 +#define LA_POST_TRIGGER_COUNT_MSB 15 +#define LA_POST_TRIGGER_COUNT_LSB 0 +#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_POST_TRIGGER_COUNT_GET(x) (((x)&LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB) +#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK) + +#define LA_FILTER_CONTROL_ADDRESS 0x000000a4 +#define LA_FILTER_CONTROL_OFFSET 0x000000a4 +#define LA_FILTER_CONTROL_DELTA_MSB 0 +#define LA_FILTER_CONTROL_DELTA_LSB 0 +#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 +#define LA_FILTER_CONTROL_DELTA_GET(x) (((x)&LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) +#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK) + +#define LA_FILTER_DATA_ADDRESS 0x000000a8 +#define LA_FILTER_DATA_OFFSET 0x000000a8 +#define LA_FILTER_DATA_MATCH_MSB 17 +#define LA_FILTER_DATA_MATCH_LSB 0 +#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff +#define LA_FILTER_DATA_MATCH_GET(x) (((x)&LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB) +#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK) + +#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac +#define LA_FILTER_WILDCARD_OFFSET 0x000000ac +#define LA_FILTER_WILDCARD_MATCH_MSB 17 +#define LA_FILTER_WILDCARD_MATCH_LSB 0 +#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x)&LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) +#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 +#define LA_TRIGGERA_DATA_OFFSET 0x000000b0 +#define LA_TRIGGERA_DATA_MATCH_MSB 17 +#define LA_TRIGGERA_DATA_MATCH_LSB 0 +#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x)&LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) +#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) + +#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 +#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 +#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x)&LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) +#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 +#define LA_TRIGGERB_DATA_OFFSET 0x000000b8 +#define LA_TRIGGERB_DATA_MATCH_MSB 17 +#define LA_TRIGGERB_DATA_MATCH_LSB 0 +#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x)&LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) +#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) + +#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc +#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc +#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x)&LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) +#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) + +#define LA_TRIGGER_ADDRESS 0x000000c0 +#define LA_TRIGGER_OFFSET 0x000000c0 +#define LA_TRIGGER_EVENT_MSB 2 +#define LA_TRIGGER_EVENT_LSB 0 +#define LA_TRIGGER_EVENT_MASK 0x00000007 +#define LA_TRIGGER_EVENT_GET(x) (((x)&LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB) +#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK) + +#define LA_FIFO_ADDRESS 0x000000c4 +#define LA_FIFO_OFFSET 0x000000c4 +#define LA_FIFO_FULL_MSB 1 +#define LA_FIFO_FULL_LSB 1 +#define LA_FIFO_FULL_MASK 0x00000002 +#define LA_FIFO_FULL_GET(x) (((x)&LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB) +#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK) +#define LA_FIFO_EMPTY_MSB 0 +#define LA_FIFO_EMPTY_LSB 0 +#define LA_FIFO_EMPTY_MASK 0x00000001 +#define LA_FIFO_EMPTY_GET(x) (((x)&LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB) +#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK) + +#define LA_ADDRESS 0x000000c8 +#define LA_OFFSET 0x000000c8 +#define LA_DATA_MSB 17 +#define LA_DATA_LSB 0 +#define LA_DATA_MASK 0x0003ffff +#define LA_DATA_GET(x) (((x)&LA_DATA_MASK) >> LA_DATA_LSB) +#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK) + +#define ANT_PIN_ADDRESS 0x000000d0 +#define ANT_PIN_OFFSET 0x000000d0 +#define ANT_PIN_PAD_PULL_MSB 3 +#define ANT_PIN_PAD_PULL_LSB 2 +#define ANT_PIN_PAD_PULL_MASK 0x0000000c +#define ANT_PIN_PAD_PULL_GET(x) (((x)&ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB) +#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK) +#define ANT_PIN_PAD_STRENGTH_MSB 1 +#define ANT_PIN_PAD_STRENGTH_LSB 0 +#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define ANT_PIN_PAD_STRENGTH_GET(x) (((x)&ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB) +#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK) + +#define ANTD_PIN_ADDRESS 0x000000d4 +#define ANTD_PIN_OFFSET 0x000000d4 +#define ANTD_PIN_PAD_PULL_MSB 1 +#define ANTD_PIN_PAD_PULL_LSB 0 +#define ANTD_PIN_PAD_PULL_MASK 0x00000003 +#define ANTD_PIN_PAD_PULL_GET(x) (((x)&ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB) +#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK) + +#define GPIO_PIN_ADDRESS 0x000000d8 +#define GPIO_PIN_OFFSET 0x000000d8 +#define GPIO_PIN_PAD_PULL_MSB 3 +#define GPIO_PIN_PAD_PULL_LSB 2 +#define GPIO_PIN_PAD_PULL_MASK 0x0000000c +#define GPIO_PIN_PAD_PULL_GET(x) (((x)&GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB) +#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK) +#define GPIO_PIN_PAD_STRENGTH_MSB 1 +#define GPIO_PIN_PAD_STRENGTH_LSB 0 +#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x)&GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB) +#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK) + +#define GPIO_H_PIN_ADDRESS 0x000000dc +#define GPIO_H_PIN_OFFSET 0x000000dc +#define GPIO_H_PIN_PAD_PULL_MSB 1 +#define GPIO_H_PIN_PAD_PULL_LSB 0 +#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 +#define GPIO_H_PIN_PAD_PULL_GET(x) (((x)&GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB) +#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK) + +#define BT_PIN_ADDRESS 0x000000e0 +#define BT_PIN_OFFSET 0x000000e0 +#define BT_PIN_PAD_PULL_MSB 3 +#define BT_PIN_PAD_PULL_LSB 2 +#define BT_PIN_PAD_PULL_MASK 0x0000000c +#define BT_PIN_PAD_PULL_GET(x) (((x)&BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB) +#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK) +#define BT_PIN_PAD_STRENGTH_MSB 1 +#define BT_PIN_PAD_STRENGTH_LSB 0 +#define BT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define BT_PIN_PAD_STRENGTH_GET(x) (((x)&BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB) +#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK) + +#define BT_WLAN_PIN_ADDRESS 0x000000e4 +#define BT_WLAN_PIN_OFFSET 0x000000e4 +#define BT_WLAN_PIN_PAD_PULL_MSB 1 +#define BT_WLAN_PIN_PAD_PULL_LSB 0 +#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 +#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x)&BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB) +#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK) + +#define SI_UART_PIN_ADDRESS 0x000000e8 +#define SI_UART_PIN_OFFSET 0x000000e8 +#define SI_UART_PIN_PAD_PULL_MSB 3 +#define SI_UART_PIN_PAD_PULL_LSB 2 +#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c +#define SI_UART_PIN_PAD_PULL_GET(x) (((x)&SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB) +#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK) +#define SI_UART_PIN_PAD_STRENGTH_MSB 1 +#define SI_UART_PIN_PAD_STRENGTH_LSB 0 +#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x)&SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) +#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) + +#define CLK32K_PIN_ADDRESS 0x000000ec +#define CLK32K_PIN_OFFSET 0x000000ec +#define CLK32K_PIN_PAD_PULL_MSB 1 +#define CLK32K_PIN_PAD_PULL_LSB 0 +#define CLK32K_PIN_PAD_PULL_MASK 0x00000003 +#define CLK32K_PIN_PAD_PULL_GET(x) (((x)&CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB) +#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK) + +#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 +#define RESET_TUPLE_STATUS_OFFSET 0x000000f0 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) \ + (((x)&RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) \ + (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) \ + (((x)&RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) \ + (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct gpio_reg_reg_s +{ + volatile unsigned int gpio_out; + volatile unsigned int gpio_out_w1ts; + volatile unsigned int gpio_out_w1tc; + volatile unsigned int gpio_enable; + volatile unsigned int gpio_enable_w1ts; + volatile unsigned int gpio_enable_w1tc; + volatile unsigned int gpio_in; + volatile unsigned int gpio_status; + volatile unsigned int gpio_status_w1ts; + volatile unsigned int gpio_status_w1tc; + volatile unsigned int gpio_pin0; + volatile unsigned int gpio_pin1; + volatile unsigned int gpio_pin2; + volatile unsigned int gpio_pin3; + volatile unsigned int gpio_pin4; + volatile unsigned int gpio_pin5; + volatile unsigned int gpio_pin6; + volatile unsigned int gpio_pin7; + volatile unsigned int gpio_pin8; + volatile unsigned int gpio_pin9; + volatile unsigned int gpio_pin10; + volatile unsigned int gpio_pin11; + volatile unsigned int gpio_pin12; + volatile unsigned int gpio_pin13; + volatile unsigned int gpio_pin14; + volatile unsigned int gpio_pin15; + volatile unsigned int gpio_pin16; + volatile unsigned int gpio_pin17; + volatile unsigned int sdio_pin; + volatile unsigned int clk_req_pin; + volatile unsigned int sigma_delta; + volatile unsigned int debug_control; + volatile unsigned int debug_input_sel; + volatile unsigned int debug_out; + volatile unsigned int la_control; + volatile unsigned int la_clock; + volatile unsigned int la_status; + volatile unsigned int la_trigger_sample; + volatile unsigned int la_trigger_position; + volatile unsigned int la_pre_trigger; + volatile unsigned int la_post_trigger; + volatile unsigned int la_filter_control; + volatile unsigned int la_filter_data; + volatile unsigned int la_filter_wildcard; + volatile unsigned int la_triggera_data; + volatile unsigned int la_triggera_wildcard; + volatile unsigned int la_triggerb_data; + volatile unsigned int la_triggerb_wildcard; + volatile unsigned int la_trigger; + volatile unsigned int la_fifo; + volatile unsigned int la[2]; + volatile unsigned int ant_pin; + volatile unsigned int antd_pin; + volatile unsigned int gpio_pin; + volatile unsigned int gpio_h_pin; + volatile unsigned int bt_pin; + volatile unsigned int bt_wlan_pin; + volatile unsigned int si_uart_pin; + volatile unsigned int clk32k_pin; + volatile unsigned int reset_tuple_status; +} gpio_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_mbox_host_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_mbox_host_reg.h new file mode 100644 index 00000000000..49c8055718b --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_mbox_host_reg.h @@ -0,0 +1,421 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x)&HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x)&HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x)&HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x)&HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x)&HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x)&CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x)&ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x)&ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ + (((x)&ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) \ + (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ + (((x)&ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) \ + (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x)&COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x)&MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x)&MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x)&RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x)&RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x)&RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x)&RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x)&RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x)&INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x)&INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) \ + (((x)&INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) \ + (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x)&INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x)&INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x)&CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x)&ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) \ + (((x)&ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ + (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) \ + (((x)&ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \ + (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) \ + (((x)&COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ + (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x)&COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x)&COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x)&SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x)&FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x)&FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x)&DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x)&DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x)&LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x)&INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x)&WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x)&WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x)&WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x)&SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x)&SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x)&SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x)&SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x)&SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x)&SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x)&SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x)&SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x)&NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x)&CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s +{ + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_mbox_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_mbox_reg.h new file mode 100644 index 00000000000..da805b1a719 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_mbox_reg.h @@ -0,0 +1,540 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _MBOX_REG_REG_H_ +#define _MBOX_REG_REG_H_ + +#define MBOX_FIFO_ADDRESS 0x00000000 +#define MBOX_FIFO_OFFSET 0x00000000 +#define MBOX_FIFO_DATA_MSB 19 +#define MBOX_FIFO_DATA_LSB 0 +#define MBOX_FIFO_DATA_MASK 0x000fffff +#define MBOX_FIFO_DATA_GET(x) (((x)&MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB) +#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK) + +#define MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x)&MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK) +#define MBOX_FIFO_STATUS_FULL_MSB 15 +#define MBOX_FIFO_STATUS_FULL_LSB 12 +#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define MBOX_FIFO_STATUS_FULL_GET(x) (((x)&MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB) +#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK) + +#define MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define MBOX_DMA_POLICY_OFFSET 0x00000014 +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x)&MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x)&MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x)&MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x)&MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x)&MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x)&MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x)&MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x)&MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x)&MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x)&MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x)&MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x)&MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x)&MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x)&MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x)&MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x)&MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x)&MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x)&MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x)&MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x)&MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x)&MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x)&MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x)&MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x)&MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x)&MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) \ + (((x)&MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) \ + (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x)&MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x)&MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x)&MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX_INT_STATUS_ADDRESS 0x00000058 +#define MBOX_INT_STATUS_OFFSET 0x00000058 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) \ + (((x)&MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) \ + (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) \ + (((x)&MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) \ + (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) \ + (((x)&MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) \ + (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x)&MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) \ + (((x)&MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) \ + (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) \ + (((x)&MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) \ + (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x)&MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define MBOX_INT_STATUS_HOST_MSB 7 +#define MBOX_INT_STATUS_HOST_LSB 0 +#define MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define MBOX_INT_STATUS_HOST_GET(x) (((x)&MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB) +#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK) + +#define MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define MBOX_INT_ENABLE_OFFSET 0x0000005c +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) \ + (((x)&MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) \ + (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) \ + (((x)&MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) \ + (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) \ + (((x)&MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) \ + (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x)&MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) \ + (((x)&MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) \ + (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) \ + (((x)&MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) \ + (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x)&MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define MBOX_INT_ENABLE_HOST_MSB 7 +#define MBOX_INT_ENABLE_HOST_LSB 0 +#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define MBOX_INT_ENABLE_HOST_GET(x) (((x)&MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB) +#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK) + +#define INT_HOST_ADDRESS 0x00000060 +#define INT_HOST_OFFSET 0x00000060 +#define INT_HOST_VECTOR_MSB 7 +#define INT_HOST_VECTOR_LSB 0 +#define INT_HOST_VECTOR_MASK 0x000000ff +#define INT_HOST_VECTOR_GET(x) (((x)&INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB) +#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK) + +#define LOCAL_COUNT_ADDRESS 0x00000080 +#define LOCAL_COUNT_OFFSET 0x00000080 +#define LOCAL_COUNT_VALUE_MSB 7 +#define LOCAL_COUNT_VALUE_LSB 0 +#define LOCAL_COUNT_VALUE_MASK 0x000000ff +#define LOCAL_COUNT_VALUE_GET(x) (((x)&LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB) +#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK) + +#define COUNT_INC_ADDRESS 0x000000a0 +#define COUNT_INC_OFFSET 0x000000a0 +#define COUNT_INC_VALUE_MSB 7 +#define COUNT_INC_VALUE_LSB 0 +#define COUNT_INC_VALUE_MASK 0x000000ff +#define COUNT_INC_VALUE_GET(x) (((x)&COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB) +#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK) + +#define LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define LOCAL_SCRATCH_OFFSET 0x000000c0 +#define LOCAL_SCRATCH_VALUE_MSB 7 +#define LOCAL_SCRATCH_VALUE_LSB 0 +#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define LOCAL_SCRATCH_VALUE_GET(x) (((x)&LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB) +#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK) + +#define USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define USE_LOCAL_BUS_OFFSET 0x000000e0 +#define USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x)&USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK) + +#define SDIO_CONFIG_ADDRESS 0x000000e4 +#define SDIO_CONFIG_OFFSET 0x000000e4 +#define SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x)&SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK) + +#define MBOX_DEBUG_ADDRESS 0x000000e8 +#define MBOX_DEBUG_OFFSET 0x000000e8 +#define MBOX_DEBUG_SEL_MSB 2 +#define MBOX_DEBUG_SEL_LSB 0 +#define MBOX_DEBUG_SEL_MASK 0x00000007 +#define MBOX_DEBUG_SEL_GET(x) (((x)&MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB) +#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK) + +#define MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define MBOX_FIFO_RESET_OFFSET 0x000000ec +#define MBOX_FIFO_RESET_INIT_MSB 0 +#define MBOX_FIFO_RESET_INIT_LSB 0 +#define MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define MBOX_FIFO_RESET_INIT_GET(x) (((x)&MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB) +#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK) + +#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define MBOX_TXFIFO_POP_DATA_MSB 0 +#define MBOX_TXFIFO_POP_DATA_LSB 0 +#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_TXFIFO_POP_DATA_GET(x) (((x)&MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB) +#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK) + +#define MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define MBOX_RXFIFO_POP_DATA_MSB 0 +#define MBOX_RXFIFO_POP_DATA_LSB 0 +#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_RXFIFO_POP_DATA_GET(x) (((x)&MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB) +#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK) + +#define SDIO_DEBUG_ADDRESS 0x00000110 +#define SDIO_DEBUG_OFFSET 0x00000110 +#define SDIO_DEBUG_SEL_MSB 3 +#define SDIO_DEBUG_SEL_LSB 0 +#define SDIO_DEBUG_SEL_MASK 0x0000000f +#define SDIO_DEBUG_SEL_GET(x) (((x)&SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB) +#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK) + +#define HOST_IF_WINDOW_ADDRESS 0x00002000 +#define HOST_IF_WINDOW_OFFSET 0x00002000 +#define HOST_IF_WINDOW_DATA_MSB 7 +#define HOST_IF_WINDOW_DATA_LSB 0 +#define HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define HOST_IF_WINDOW_DATA_GET(x) (((x)&HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB) +#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct mbox_reg_reg_s +{ + volatile unsigned int mbox_fifo[4]; + volatile unsigned int mbox_fifo_status; + volatile unsigned int mbox_dma_policy; + volatile unsigned int mbox0_dma_rx_descriptor_base; + volatile unsigned int mbox0_dma_rx_control; + volatile unsigned int mbox0_dma_tx_descriptor_base; + volatile unsigned int mbox0_dma_tx_control; + volatile unsigned int mbox1_dma_rx_descriptor_base; + volatile unsigned int mbox1_dma_rx_control; + volatile unsigned int mbox1_dma_tx_descriptor_base; + volatile unsigned int mbox1_dma_tx_control; + volatile unsigned int mbox2_dma_rx_descriptor_base; + volatile unsigned int mbox2_dma_rx_control; + volatile unsigned int mbox2_dma_tx_descriptor_base; + volatile unsigned int mbox2_dma_tx_control; + volatile unsigned int mbox3_dma_rx_descriptor_base; + volatile unsigned int mbox3_dma_rx_control; + volatile unsigned int mbox3_dma_tx_descriptor_base; + volatile unsigned int mbox3_dma_tx_control; + volatile unsigned int mbox_int_status; + volatile unsigned int mbox_int_enable; + volatile unsigned int int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int local_count[8]; + volatile unsigned int count_inc[8]; + volatile unsigned int local_scratch[8]; + volatile unsigned int use_local_bus; + volatile unsigned int sdio_config; + volatile unsigned int mbox_debug; + volatile unsigned int mbox_fifo_reset; + volatile unsigned int mbox_txfifo_pop[4]; + volatile unsigned int mbox_rxfifo_pop[4]; + volatile unsigned int sdio_debug; + unsigned char pad1[7916]; /* pad to 0x2000 */ + volatile unsigned int host_if_window[2048]; +} mbox_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_rtc_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_rtc_reg.h new file mode 100644 index 00000000000..501cbb64d8c --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_rtc_reg.h @@ -0,0 +1,1216 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#define RESET_CONTROL_ADDRESS 0x00000000 +#define RESET_CONTROL_OFFSET 0x00000000 +#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) \ + (((x)&RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) \ + (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) \ + (((x)&RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) \ + (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define RESET_CONTROL_RST_OUT_MSB 9 +#define RESET_CONTROL_RST_OUT_LSB 9 +#define RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define RESET_CONTROL_RST_OUT_GET(x) (((x)&RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) +#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) +#define RESET_CONTROL_COLD_RST_MSB 8 +#define RESET_CONTROL_COLD_RST_LSB 8 +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_COLD_RST_GET(x) (((x)&RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) +#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) +#define RESET_CONTROL_WARM_RST_MSB 7 +#define RESET_CONTROL_WARM_RST_LSB 7 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CONTROL_WARM_RST_GET(x) (((x)&RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) +#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) +#define RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x)&RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) +#define RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x)&RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) +#define RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x)&RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) +#define RESET_CONTROL_MBOX_RST_MSB 2 +#define RESET_CONTROL_MBOX_RST_LSB 2 +#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define RESET_CONTROL_MBOX_RST_GET(x) (((x)&RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) +#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) +#define RESET_CONTROL_UART_RST_MSB 1 +#define RESET_CONTROL_UART_RST_LSB 1 +#define RESET_CONTROL_UART_RST_MASK 0x00000002 +#define RESET_CONTROL_UART_RST_GET(x) (((x)&RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) +#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) +#define RESET_CONTROL_SI0_RST_MSB 0 +#define RESET_CONTROL_SI0_RST_LSB 0 +#define RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define RESET_CONTROL_SI0_RST_GET(x) (((x)&RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) +#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) + +#define XTAL_CONTROL_ADDRESS 0x00000004 +#define XTAL_CONTROL_OFFSET 0x00000004 +#define XTAL_CONTROL_TCXO_MSB 0 +#define XTAL_CONTROL_TCXO_LSB 0 +#define XTAL_CONTROL_TCXO_MASK 0x00000001 +#define XTAL_CONTROL_TCXO_GET(x) (((x)&XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) +#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) + +#define TCXO_DETECT_ADDRESS 0x00000008 +#define TCXO_DETECT_OFFSET 0x00000008 +#define TCXO_DETECT_PRESENT_MSB 0 +#define TCXO_DETECT_PRESENT_LSB 0 +#define TCXO_DETECT_PRESENT_MASK 0x00000001 +#define TCXO_DETECT_PRESENT_GET(x) (((x)&TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) +#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) + +#define XTAL_TEST_ADDRESS 0x0000000c +#define XTAL_TEST_OFFSET 0x0000000c +#define XTAL_TEST_NOTCXODET_MSB 0 +#define XTAL_TEST_NOTCXODET_LSB 0 +#define XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define XTAL_TEST_NOTCXODET_GET(x) (((x)&XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) +#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) + +#define QUADRATURE_ADDRESS 0x00000010 +#define QUADRATURE_OFFSET 0x00000010 +#define QUADRATURE_ADC_MSB 5 +#define QUADRATURE_ADC_LSB 4 +#define QUADRATURE_ADC_MASK 0x00000030 +#define QUADRATURE_ADC_GET(x) (((x)&QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) +#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) +#define QUADRATURE_SEL_MSB 2 +#define QUADRATURE_SEL_LSB 2 +#define QUADRATURE_SEL_MASK 0x00000004 +#define QUADRATURE_SEL_GET(x) (((x)&QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) +#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) +#define QUADRATURE_DAC_MSB 1 +#define QUADRATURE_DAC_LSB 0 +#define QUADRATURE_DAC_MASK 0x00000003 +#define QUADRATURE_DAC_GET(x) (((x)&QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) +#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) + +#define PLL_CONTROL_ADDRESS 0x00000014 +#define PLL_CONTROL_OFFSET 0x00000014 +#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x)&PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) +#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x)&PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) +#define PLL_CONTROL_NOPWD_MSB 18 +#define PLL_CONTROL_NOPWD_LSB 18 +#define PLL_CONTROL_NOPWD_MASK 0x00040000 +#define PLL_CONTROL_NOPWD_GET(x) (((x)&PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) +#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) +#define PLL_CONTROL_UPDATING_MSB 17 +#define PLL_CONTROL_UPDATING_LSB 17 +#define PLL_CONTROL_UPDATING_MASK 0x00020000 +#define PLL_CONTROL_UPDATING_GET(x) (((x)&PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) +#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) +#define PLL_CONTROL_BYPASS_MSB 16 +#define PLL_CONTROL_BYPASS_LSB 16 +#define PLL_CONTROL_BYPASS_MASK 0x00010000 +#define PLL_CONTROL_BYPASS_GET(x) (((x)&PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) +#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) +#define PLL_CONTROL_REFDIV_MSB 15 +#define PLL_CONTROL_REFDIV_LSB 12 +#define PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define PLL_CONTROL_REFDIV_GET(x) (((x)&PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) +#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) +#define PLL_CONTROL_DIV_MSB 9 +#define PLL_CONTROL_DIV_LSB 0 +#define PLL_CONTROL_DIV_MASK 0x000003ff +#define PLL_CONTROL_DIV_GET(x) (((x)&PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) +#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) + +#define PLL_SETTLE_ADDRESS 0x00000018 +#define PLL_SETTLE_OFFSET 0x00000018 +#define PLL_SETTLE_TIME_MSB 11 +#define PLL_SETTLE_TIME_LSB 0 +#define PLL_SETTLE_TIME_MASK 0x00000fff +#define PLL_SETTLE_TIME_GET(x) (((x)&PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) +#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) + +#define XTAL_SETTLE_ADDRESS 0x0000001c +#define XTAL_SETTLE_OFFSET 0x0000001c +#define XTAL_SETTLE_TIME_MSB 7 +#define XTAL_SETTLE_TIME_LSB 0 +#define XTAL_SETTLE_TIME_MASK 0x000000ff +#define XTAL_SETTLE_TIME_GET(x) (((x)&XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) +#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) + +#define CPU_CLOCK_ADDRESS 0x00000020 +#define CPU_CLOCK_OFFSET 0x00000020 +#define CPU_CLOCK_STANDARD_MSB 1 +#define CPU_CLOCK_STANDARD_LSB 0 +#define CPU_CLOCK_STANDARD_MASK 0x00000003 +#define CPU_CLOCK_STANDARD_GET(x) (((x)&CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) +#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) + +#define CLOCK_OUT_ADDRESS 0x00000024 +#define CLOCK_OUT_OFFSET 0x00000024 +#define CLOCK_OUT_SELECT_MSB 3 +#define CLOCK_OUT_SELECT_LSB 0 +#define CLOCK_OUT_SELECT_MASK 0x0000000f +#define CLOCK_OUT_SELECT_GET(x) (((x)&CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) +#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) + +#define CLOCK_CONTROL_ADDRESS 0x00000028 +#define CLOCK_CONTROL_OFFSET 0x00000028 +#define CLOCK_CONTROL_LF_CLK32_MSB 2 +#define CLOCK_CONTROL_LF_CLK32_LSB 2 +#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x)&CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) +#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) +#define CLOCK_CONTROL_UART_CLK_MSB 1 +#define CLOCK_CONTROL_UART_CLK_LSB 1 +#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 +#define CLOCK_CONTROL_UART_CLK_GET(x) (((x)&CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) +#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) +#define CLOCK_CONTROL_SI0_CLK_MSB 0 +#define CLOCK_CONTROL_SI0_CLK_LSB 0 +#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x)&CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) +#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) + +#define BIAS_OVERRIDE_ADDRESS 0x0000002c +#define BIAS_OVERRIDE_OFFSET 0x0000002c +#define BIAS_OVERRIDE_ON_MSB 0 +#define BIAS_OVERRIDE_ON_LSB 0 +#define BIAS_OVERRIDE_ON_MASK 0x00000001 +#define BIAS_OVERRIDE_ON_GET(x) (((x)&BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) +#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) + +#define WDT_CONTROL_ADDRESS 0x00000030 +#define WDT_CONTROL_OFFSET 0x00000030 +#define WDT_CONTROL_ACTION_MSB 2 +#define WDT_CONTROL_ACTION_LSB 0 +#define WDT_CONTROL_ACTION_MASK 0x00000007 +#define WDT_CONTROL_ACTION_GET(x) (((x)&WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) +#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) + +#define WDT_STATUS_ADDRESS 0x00000034 +#define WDT_STATUS_OFFSET 0x00000034 +#define WDT_STATUS_INTERRUPT_MSB 0 +#define WDT_STATUS_INTERRUPT_LSB 0 +#define WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WDT_STATUS_INTERRUPT_GET(x) (((x)&WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) +#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) + +#define WDT_ADDRESS 0x00000038 +#define WDT_OFFSET 0x00000038 +#define WDT_TARGET_MSB 21 +#define WDT_TARGET_LSB 0 +#define WDT_TARGET_MASK 0x003fffff +#define WDT_TARGET_GET(x) (((x)&WDT_TARGET_MASK) >> WDT_TARGET_LSB) +#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) + +#define WDT_COUNT_ADDRESS 0x0000003c +#define WDT_COUNT_OFFSET 0x0000003c +#define WDT_COUNT_VALUE_MSB 21 +#define WDT_COUNT_VALUE_LSB 0 +#define WDT_COUNT_VALUE_MASK 0x003fffff +#define WDT_COUNT_VALUE_GET(x) (((x)&WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) +#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) + +#define WDT_RESET_ADDRESS 0x00000040 +#define WDT_RESET_OFFSET 0x00000040 +#define WDT_RESET_VALUE_MSB 0 +#define WDT_RESET_VALUE_LSB 0 +#define WDT_RESET_VALUE_MASK 0x00000001 +#define WDT_RESET_VALUE_GET(x) (((x)&WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) +#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) + +#define INT_STATUS_ADDRESS 0x00000044 +#define INT_STATUS_OFFSET 0x00000044 +#define INT_STATUS_RTC_POWER_MSB 14 +#define INT_STATUS_RTC_POWER_LSB 14 +#define INT_STATUS_RTC_POWER_MASK 0x00004000 +#define INT_STATUS_RTC_POWER_GET(x) (((x)&INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) +#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) +#define INT_STATUS_MAC_MSB 13 +#define INT_STATUS_MAC_LSB 13 +#define INT_STATUS_MAC_MASK 0x00002000 +#define INT_STATUS_MAC_GET(x) (((x)&INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) +#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) +#define INT_STATUS_MAILBOX_MSB 12 +#define INT_STATUS_MAILBOX_LSB 12 +#define INT_STATUS_MAILBOX_MASK 0x00001000 +#define INT_STATUS_MAILBOX_GET(x) (((x)&INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) +#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) +#define INT_STATUS_RTC_ALARM_MSB 11 +#define INT_STATUS_RTC_ALARM_LSB 11 +#define INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define INT_STATUS_RTC_ALARM_GET(x) (((x)&INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) +#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) +#define INT_STATUS_HF_TIMER_MSB 10 +#define INT_STATUS_HF_TIMER_LSB 10 +#define INT_STATUS_HF_TIMER_MASK 0x00000400 +#define INT_STATUS_HF_TIMER_GET(x) (((x)&INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) +#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) +#define INT_STATUS_LF_TIMER3_MSB 9 +#define INT_STATUS_LF_TIMER3_LSB 9 +#define INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define INT_STATUS_LF_TIMER3_GET(x) (((x)&INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) +#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) +#define INT_STATUS_LF_TIMER2_MSB 8 +#define INT_STATUS_LF_TIMER2_LSB 8 +#define INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define INT_STATUS_LF_TIMER2_GET(x) (((x)&INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) +#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) +#define INT_STATUS_LF_TIMER1_MSB 7 +#define INT_STATUS_LF_TIMER1_LSB 7 +#define INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define INT_STATUS_LF_TIMER1_GET(x) (((x)&INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) +#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) +#define INT_STATUS_LF_TIMER0_MSB 6 +#define INT_STATUS_LF_TIMER0_LSB 6 +#define INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define INT_STATUS_LF_TIMER0_GET(x) (((x)&INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) +#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) +#define INT_STATUS_KEYPAD_MSB 5 +#define INT_STATUS_KEYPAD_LSB 5 +#define INT_STATUS_KEYPAD_MASK 0x00000020 +#define INT_STATUS_KEYPAD_GET(x) (((x)&INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) +#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) +#define INT_STATUS_SI_MSB 4 +#define INT_STATUS_SI_LSB 4 +#define INT_STATUS_SI_MASK 0x00000010 +#define INT_STATUS_SI_GET(x) (((x)&INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) +#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) +#define INT_STATUS_GPIO_MSB 3 +#define INT_STATUS_GPIO_LSB 3 +#define INT_STATUS_GPIO_MASK 0x00000008 +#define INT_STATUS_GPIO_GET(x) (((x)&INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) +#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) +#define INT_STATUS_UART_MSB 2 +#define INT_STATUS_UART_LSB 2 +#define INT_STATUS_UART_MASK 0x00000004 +#define INT_STATUS_UART_GET(x) (((x)&INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) +#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) +#define INT_STATUS_ERROR_MSB 1 +#define INT_STATUS_ERROR_LSB 1 +#define INT_STATUS_ERROR_MASK 0x00000002 +#define INT_STATUS_ERROR_GET(x) (((x)&INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) +#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) +#define INT_STATUS_WDT_INT_MSB 0 +#define INT_STATUS_WDT_INT_LSB 0 +#define INT_STATUS_WDT_INT_MASK 0x00000001 +#define INT_STATUS_WDT_INT_GET(x) (((x)&INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) +#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) + +#define LF_TIMER0_ADDRESS 0x00000048 +#define LF_TIMER0_OFFSET 0x00000048 +#define LF_TIMER0_TARGET_MSB 31 +#define LF_TIMER0_TARGET_LSB 0 +#define LF_TIMER0_TARGET_MASK 0xffffffff +#define LF_TIMER0_TARGET_GET(x) (((x)&LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) +#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) + +#define LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define LF_TIMER_COUNT0_OFFSET 0x0000004c +#define LF_TIMER_COUNT0_VALUE_MSB 31 +#define LF_TIMER_COUNT0_VALUE_LSB 0 +#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT0_VALUE_GET(x) (((x)&LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) +#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) + +#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x)&LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) \ + (((x)&LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) \ + (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL0_RESET_MSB 0 +#define LF_TIMER_CONTROL0_RESET_LSB 0 +#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL0_RESET_GET(x) (((x)&LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) +#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) + +#define LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define LF_TIMER_STATUS0_OFFSET 0x00000054 +#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x)&LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define LF_TIMER1_ADDRESS 0x00000058 +#define LF_TIMER1_OFFSET 0x00000058 +#define LF_TIMER1_TARGET_MSB 31 +#define LF_TIMER1_TARGET_LSB 0 +#define LF_TIMER1_TARGET_MASK 0xffffffff +#define LF_TIMER1_TARGET_GET(x) (((x)&LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) +#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) + +#define LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define LF_TIMER_COUNT1_OFFSET 0x0000005c +#define LF_TIMER_COUNT1_VALUE_MSB 31 +#define LF_TIMER_COUNT1_VALUE_LSB 0 +#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT1_VALUE_GET(x) (((x)&LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) +#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) + +#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x)&LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) \ + (((x)&LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) \ + (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL1_RESET_MSB 0 +#define LF_TIMER_CONTROL1_RESET_LSB 0 +#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL1_RESET_GET(x) (((x)&LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) +#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) + +#define LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define LF_TIMER_STATUS1_OFFSET 0x00000064 +#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x)&LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define LF_TIMER2_ADDRESS 0x00000068 +#define LF_TIMER2_OFFSET 0x00000068 +#define LF_TIMER2_TARGET_MSB 31 +#define LF_TIMER2_TARGET_LSB 0 +#define LF_TIMER2_TARGET_MASK 0xffffffff +#define LF_TIMER2_TARGET_GET(x) (((x)&LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) +#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) + +#define LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define LF_TIMER_COUNT2_OFFSET 0x0000006c +#define LF_TIMER_COUNT2_VALUE_MSB 31 +#define LF_TIMER_COUNT2_VALUE_LSB 0 +#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT2_VALUE_GET(x) (((x)&LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) +#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) + +#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x)&LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) \ + (((x)&LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) \ + (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL2_RESET_MSB 0 +#define LF_TIMER_CONTROL2_RESET_LSB 0 +#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL2_RESET_GET(x) (((x)&LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) +#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) + +#define LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define LF_TIMER_STATUS2_OFFSET 0x00000074 +#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x)&LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define LF_TIMER3_ADDRESS 0x00000078 +#define LF_TIMER3_OFFSET 0x00000078 +#define LF_TIMER3_TARGET_MSB 31 +#define LF_TIMER3_TARGET_LSB 0 +#define LF_TIMER3_TARGET_MASK 0xffffffff +#define LF_TIMER3_TARGET_GET(x) (((x)&LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) +#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) + +#define LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define LF_TIMER_COUNT3_OFFSET 0x0000007c +#define LF_TIMER_COUNT3_VALUE_MSB 31 +#define LF_TIMER_COUNT3_VALUE_LSB 0 +#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT3_VALUE_GET(x) (((x)&LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) +#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) + +#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x)&LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) \ + (((x)&LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) \ + (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL3_RESET_MSB 0 +#define LF_TIMER_CONTROL3_RESET_LSB 0 +#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL3_RESET_GET(x) (((x)&LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) +#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) + +#define LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define LF_TIMER_STATUS3_OFFSET 0x00000084 +#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x)&LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define HF_TIMER_ADDRESS 0x00000088 +#define HF_TIMER_OFFSET 0x00000088 +#define HF_TIMER_TARGET_MSB 31 +#define HF_TIMER_TARGET_LSB 12 +#define HF_TIMER_TARGET_MASK 0xfffff000 +#define HF_TIMER_TARGET_GET(x) (((x)&HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) +#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) + +#define HF_TIMER_COUNT_ADDRESS 0x0000008c +#define HF_TIMER_COUNT_OFFSET 0x0000008c +#define HF_TIMER_COUNT_VALUE_MSB 31 +#define HF_TIMER_COUNT_VALUE_LSB 12 +#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define HF_TIMER_COUNT_VALUE_GET(x) (((x)&HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) +#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) + +#define HF_LF_COUNT_ADDRESS 0x00000090 +#define HF_LF_COUNT_OFFSET 0x00000090 +#define HF_LF_COUNT_VALUE_MSB 31 +#define HF_LF_COUNT_VALUE_LSB 0 +#define HF_LF_COUNT_VALUE_MASK 0xffffffff +#define HF_LF_COUNT_VALUE_GET(x) (((x)&HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) +#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) + +#define HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define HF_TIMER_CONTROL_OFFSET 0x00000094 +#define HF_TIMER_CONTROL_ENABLE_MSB 3 +#define HF_TIMER_CONTROL_ENABLE_LSB 3 +#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x)&HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) +#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) +#define HF_TIMER_CONTROL_ON_MSB 2 +#define HF_TIMER_CONTROL_ON_LSB 2 +#define HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define HF_TIMER_CONTROL_ON_GET(x) (((x)&HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) +#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) \ + (((x)&HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) \ + (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define HF_TIMER_CONTROL_RESET_MSB 0 +#define HF_TIMER_CONTROL_RESET_LSB 0 +#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define HF_TIMER_CONTROL_RESET_GET(x) (((x)&HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) +#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) + +#define HF_TIMER_STATUS_ADDRESS 0x00000098 +#define HF_TIMER_STATUS_OFFSET 0x00000098 +#define HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x)&HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) + +#define RTC_CONTROL_ADDRESS 0x0000009c +#define RTC_CONTROL_OFFSET 0x0000009c +#define RTC_CONTROL_ENABLE_MSB 2 +#define RTC_CONTROL_ENABLE_LSB 2 +#define RTC_CONTROL_ENABLE_MASK 0x00000004 +#define RTC_CONTROL_ENABLE_GET(x) (((x)&RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) +#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) +#define RTC_CONTROL_LOAD_RTC_MSB 1 +#define RTC_CONTROL_LOAD_RTC_LSB 1 +#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define RTC_CONTROL_LOAD_RTC_GET(x) (((x)&RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) +#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) +#define RTC_CONTROL_LOAD_ALARM_MSB 0 +#define RTC_CONTROL_LOAD_ALARM_LSB 0 +#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x)&RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) +#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) + +#define RTC_TIME_ADDRESS 0x000000a0 +#define RTC_TIME_OFFSET 0x000000a0 +#define RTC_TIME_WEEK_DAY_MSB 26 +#define RTC_TIME_WEEK_DAY_LSB 24 +#define RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_TIME_WEEK_DAY_GET(x) (((x)&RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) +#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) +#define RTC_TIME_HOUR_MSB 21 +#define RTC_TIME_HOUR_LSB 16 +#define RTC_TIME_HOUR_MASK 0x003f0000 +#define RTC_TIME_HOUR_GET(x) (((x)&RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) +#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) +#define RTC_TIME_MINUTE_MSB 14 +#define RTC_TIME_MINUTE_LSB 8 +#define RTC_TIME_MINUTE_MASK 0x00007f00 +#define RTC_TIME_MINUTE_GET(x) (((x)&RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) +#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) +#define RTC_TIME_SECOND_MSB 6 +#define RTC_TIME_SECOND_LSB 0 +#define RTC_TIME_SECOND_MASK 0x0000007f +#define RTC_TIME_SECOND_GET(x) (((x)&RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) +#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) + +#define RTC_DATE_ADDRESS 0x000000a4 +#define RTC_DATE_OFFSET 0x000000a4 +#define RTC_DATE_YEAR_MSB 23 +#define RTC_DATE_YEAR_LSB 16 +#define RTC_DATE_YEAR_MASK 0x00ff0000 +#define RTC_DATE_YEAR_GET(x) (((x)&RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) +#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) +#define RTC_DATE_MONTH_MSB 12 +#define RTC_DATE_MONTH_LSB 8 +#define RTC_DATE_MONTH_MASK 0x00001f00 +#define RTC_DATE_MONTH_GET(x) (((x)&RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) +#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) +#define RTC_DATE_MONTH_DAY_MSB 5 +#define RTC_DATE_MONTH_DAY_LSB 0 +#define RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_DATE_MONTH_DAY_GET(x) (((x)&RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) +#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) + +#define RTC_SET_TIME_ADDRESS 0x000000a8 +#define RTC_SET_TIME_OFFSET 0x000000a8 +#define RTC_SET_TIME_WEEK_DAY_MSB 26 +#define RTC_SET_TIME_WEEK_DAY_LSB 24 +#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x)&RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) +#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) +#define RTC_SET_TIME_HOUR_MSB 21 +#define RTC_SET_TIME_HOUR_LSB 16 +#define RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define RTC_SET_TIME_HOUR_GET(x) (((x)&RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) +#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) +#define RTC_SET_TIME_MINUTE_MSB 14 +#define RTC_SET_TIME_MINUTE_LSB 8 +#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define RTC_SET_TIME_MINUTE_GET(x) (((x)&RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) +#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) +#define RTC_SET_TIME_SECOND_MSB 6 +#define RTC_SET_TIME_SECOND_LSB 0 +#define RTC_SET_TIME_SECOND_MASK 0x0000007f +#define RTC_SET_TIME_SECOND_GET(x) (((x)&RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) +#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) + +#define RTC_SET_DATE_ADDRESS 0x000000ac +#define RTC_SET_DATE_OFFSET 0x000000ac +#define RTC_SET_DATE_YEAR_MSB 23 +#define RTC_SET_DATE_YEAR_LSB 16 +#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define RTC_SET_DATE_YEAR_GET(x) (((x)&RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) +#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) +#define RTC_SET_DATE_MONTH_MSB 12 +#define RTC_SET_DATE_MONTH_LSB 8 +#define RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define RTC_SET_DATE_MONTH_GET(x) (((x)&RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) +#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) +#define RTC_SET_DATE_MONTH_DAY_MSB 5 +#define RTC_SET_DATE_MONTH_DAY_LSB 0 +#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x)&RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) +#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) + +#define RTC_SET_ALARM_ADDRESS 0x000000b0 +#define RTC_SET_ALARM_OFFSET 0x000000b0 +#define RTC_SET_ALARM_HOUR_MSB 21 +#define RTC_SET_ALARM_HOUR_LSB 16 +#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define RTC_SET_ALARM_HOUR_GET(x) (((x)&RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) +#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) +#define RTC_SET_ALARM_MINUTE_MSB 14 +#define RTC_SET_ALARM_MINUTE_LSB 8 +#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define RTC_SET_ALARM_MINUTE_GET(x) (((x)&RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) +#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) +#define RTC_SET_ALARM_SECOND_MSB 6 +#define RTC_SET_ALARM_SECOND_LSB 0 +#define RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define RTC_SET_ALARM_SECOND_GET(x) (((x)&RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) +#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) + +#define RTC_CONFIG_ADDRESS 0x000000b4 +#define RTC_CONFIG_OFFSET 0x000000b4 +#define RTC_CONFIG_BCD_MSB 2 +#define RTC_CONFIG_BCD_LSB 2 +#define RTC_CONFIG_BCD_MASK 0x00000004 +#define RTC_CONFIG_BCD_GET(x) (((x)&RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) +#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) +#define RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x)&RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) +#define RTC_CONFIG_DSE_MSB 0 +#define RTC_CONFIG_DSE_LSB 0 +#define RTC_CONFIG_DSE_MASK 0x00000001 +#define RTC_CONFIG_DSE_GET(x) (((x)&RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) +#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) + +#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define RTC_ALARM_STATUS_ENABLE_MSB 1 +#define RTC_ALARM_STATUS_ENABLE_LSB 1 +#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x)&RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) +#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) +#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x)&RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define UART_WAKEUP_ADDRESS 0x000000bc +#define UART_WAKEUP_OFFSET 0x000000bc +#define UART_WAKEUP_ENABLE_MSB 0 +#define UART_WAKEUP_ENABLE_LSB 0 +#define UART_WAKEUP_ENABLE_MASK 0x00000001 +#define UART_WAKEUP_ENABLE_GET(x) (((x)&UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) +#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) + +#define RESET_CAUSE_ADDRESS 0x000000c0 +#define RESET_CAUSE_OFFSET 0x000000c0 +#define RESET_CAUSE_LAST_MSB 2 +#define RESET_CAUSE_LAST_LSB 0 +#define RESET_CAUSE_LAST_MASK 0x00000007 +#define RESET_CAUSE_LAST_GET(x) (((x)&RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) +#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) + +#define SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x)&SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) +#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) +#define SYSTEM_SLEEP_MBOX_MSB 3 +#define SYSTEM_SLEEP_MBOX_LSB 3 +#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SYSTEM_SLEEP_MBOX_GET(x) (((x)&SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) +#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) +#define SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x)&SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) +#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) +#define SYSTEM_SLEEP_LIGHT_MSB 1 +#define SYSTEM_SLEEP_LIGHT_LSB 1 +#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SYSTEM_SLEEP_LIGHT_GET(x) (((x)&SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) +#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) +#define SYSTEM_SLEEP_DISABLE_MSB 0 +#define SYSTEM_SLEEP_DISABLE_LSB 0 +#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SYSTEM_SLEEP_DISABLE_GET(x) (((x)&SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) + +#define SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SDIO_WRAPPER_OFFSET 0x000000c8 +#define SDIO_WRAPPER_SLEEP_MSB 3 +#define SDIO_WRAPPER_SLEEP_LSB 3 +#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SDIO_WRAPPER_SLEEP_GET(x) (((x)&SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) +#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) +#define SDIO_WRAPPER_WAKEUP_MSB 2 +#define SDIO_WRAPPER_WAKEUP_LSB 2 +#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SDIO_WRAPPER_WAKEUP_GET(x) (((x)&SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) +#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) +#define SDIO_WRAPPER_SOC_ON_MSB 1 +#define SDIO_WRAPPER_SOC_ON_LSB 1 +#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SDIO_WRAPPER_SOC_ON_GET(x) (((x)&SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) +#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) +#define SDIO_WRAPPER_ON_MSB 0 +#define SDIO_WRAPPER_ON_LSB 0 +#define SDIO_WRAPPER_ON_MASK 0x00000001 +#define SDIO_WRAPPER_ON_GET(x) (((x)&SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) +#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) + +#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x)&MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define KEEP_AWAKE_ADDRESS 0x000000d0 +#define KEEP_AWAKE_OFFSET 0x000000d0 +#define KEEP_AWAKE_COUNT_MSB 7 +#define KEEP_AWAKE_COUNT_LSB 0 +#define KEEP_AWAKE_COUNT_MASK 0x000000ff +#define KEEP_AWAKE_COUNT_GET(x) (((x)&KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) +#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) + +#define LPO_CAL_TIME_ADDRESS 0x000000d4 +#define LPO_CAL_TIME_OFFSET 0x000000d4 +#define LPO_CAL_TIME_LENGTH_MSB 13 +#define LPO_CAL_TIME_LENGTH_LSB 0 +#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define LPO_CAL_TIME_LENGTH_GET(x) (((x)&LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) +#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) + +#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x)&LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) \ + (((x)&LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) \ + (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define LPO_CAL_ADDRESS 0x000000e0 +#define LPO_CAL_OFFSET 0x000000e0 +#define LPO_CAL_ENABLE_MSB 20 +#define LPO_CAL_ENABLE_LSB 20 +#define LPO_CAL_ENABLE_MASK 0x00100000 +#define LPO_CAL_ENABLE_GET(x) (((x)&LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) +#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) +#define LPO_CAL_COUNT_MSB 19 +#define LPO_CAL_COUNT_LSB 0 +#define LPO_CAL_COUNT_MASK 0x000fffff +#define LPO_CAL_COUNT_GET(x) (((x)&LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) +#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) + +#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x)&LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) \ + (((x)&LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) \ + (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define LPO_CAL_TEST_STATUS_READY_MSB 16 +#define LPO_CAL_TEST_STATUS_READY_LSB 16 +#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x)&LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) +#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) +#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x)&LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define CHIP_ID_ADDRESS 0x000000ec +#define CHIP_ID_OFFSET 0x000000ec +#define CHIP_ID_DEVICE_ID_MSB 31 +#define CHIP_ID_DEVICE_ID_LSB 16 +#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define CHIP_ID_DEVICE_ID_GET(x) (((x)&CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) +#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) +#define CHIP_ID_CONFIG_ID_MSB 15 +#define CHIP_ID_CONFIG_ID_LSB 4 +#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define CHIP_ID_CONFIG_ID_GET(x) (((x)&CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) +#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) +#define CHIP_ID_VERSION_ID_MSB 3 +#define CHIP_ID_VERSION_ID_LSB 0 +#define CHIP_ID_VERSION_ID_MASK 0x0000000f +#define CHIP_ID_VERSION_ID_GET(x) (((x)&CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) +#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) + +#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) \ + (((x)&DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) \ + (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) \ + (((x)&DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) \ + (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define DERIVED_RTC_CLK_FORCE_MSB 17 +#define DERIVED_RTC_CLK_FORCE_LSB 16 +#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define DERIVED_RTC_CLK_FORCE_GET(x) (((x)&DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) +#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) +#define DERIVED_RTC_CLK_PERIOD_MSB 15 +#define DERIVED_RTC_CLK_PERIOD_LSB 1 +#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x)&DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) +#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) \ + (((x)&MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) \ + (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) \ + (((x)&MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) \ + (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x)&MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x)&MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x)&MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x)&MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x)&MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x)&MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c +#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) \ + (((x)&MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) \ + (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) \ + (((x)&MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) \ + (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) + +#define POWER_REG_ADDRESS 0x00000110 +#define POWER_REG_OFFSET 0x00000110 +#define POWER_REG_VLVL_MSB 11 +#define POWER_REG_VLVL_LSB 8 +#define POWER_REG_VLVL_MASK 0x00000f00 +#define POWER_REG_VLVL_GET(x) (((x)&POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) +#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) +#define POWER_REG_CPU_INT_ENABLE_MSB 7 +#define POWER_REG_CPU_INT_ENABLE_LSB 7 +#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x)&POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) +#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) +#define POWER_REG_WLAN_ISO_DIS_MSB 6 +#define POWER_REG_WLAN_ISO_DIS_LSB 6 +#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x)&POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) +#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) +#define POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x)&POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) +#define POWER_REG_RADIO_PWD_EN_MSB 4 +#define POWER_REG_RADIO_PWD_EN_LSB 4 +#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define POWER_REG_RADIO_PWD_EN_GET(x) (((x)&POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) +#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) +#define POWER_REG_SOC_SCALE_EN_MSB 3 +#define POWER_REG_SOC_SCALE_EN_LSB 3 +#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 +#define POWER_REG_SOC_SCALE_EN_GET(x) (((x)&POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) +#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) +#define POWER_REG_WLAN_SCALE_EN_MSB 2 +#define POWER_REG_WLAN_SCALE_EN_LSB 2 +#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 +#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x)&POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) +#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) +#define POWER_REG_WLAN_PWD_EN_MSB 1 +#define POWER_REG_WLAN_PWD_EN_LSB 1 +#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define POWER_REG_WLAN_PWD_EN_GET(x) (((x)&POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) +#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) +#define POWER_REG_POWER_EN_MSB 0 +#define POWER_REG_POWER_EN_LSB 0 +#define POWER_REG_POWER_EN_MASK 0x00000001 +#define POWER_REG_POWER_EN_GET(x) (((x)&POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) +#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) + +#define CORE_CLK_CTRL_ADDRESS 0x00000114 +#define CORE_CLK_CTRL_OFFSET 0x00000114 +#define CORE_CLK_CTRL_DIV_MSB 2 +#define CORE_CLK_CTRL_DIV_LSB 0 +#define CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define CORE_CLK_CTRL_DIV_GET(x) (((x)&CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) +#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) + +#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 +#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 +#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 +#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 +#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x)&SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) +#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) + +#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 +#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 +#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x)&SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) +#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) +#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x)&SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) +#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 +#define CPU_SETUP_CONFIG_OFFSET 0x00000144 +#define CPU_SETUP_CONFIG_ENABLE_MSB 1 +#define CPU_SETUP_CONFIG_ENABLE_LSB 1 +#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x)&CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) +#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) +#define CPU_SETUP_CONFIG_CLEAR_MSB 0 +#define CPU_SETUP_CONFIG_CLEAR_LSB 0 +#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x)&CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) +#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 +#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 +#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 +#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 +#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x)&CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) +#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) + +#define BB_SETUP_CONFIG_ADDRESS 0x00000180 +#define BB_SETUP_CONFIG_OFFSET 0x00000180 +#define BB_SETUP_CONFIG_ENABLE_MSB 1 +#define BB_SETUP_CONFIG_ENABLE_LSB 1 +#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x)&BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) +#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) +#define BB_SETUP_CONFIG_CLEAR_MSB 0 +#define BB_SETUP_CONFIG_CLEAR_LSB 0 +#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x)&BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) +#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) + +#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 +#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 +#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 +#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 +#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x)&BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) +#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) + +#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 +#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x)&GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct rtc_reg_reg_s +{ + volatile unsigned int reset_control; + volatile unsigned int xtal_control; + volatile unsigned int tcxo_detect; + volatile unsigned int xtal_test; + volatile unsigned int quadrature; + volatile unsigned int pll_control; + volatile unsigned int pll_settle; + volatile unsigned int xtal_settle; + volatile unsigned int cpu_clock; + volatile unsigned int clock_out; + volatile unsigned int clock_control; + volatile unsigned int bias_override; + volatile unsigned int wdt_control; + volatile unsigned int wdt_status; + volatile unsigned int wdt; + volatile unsigned int wdt_count; + volatile unsigned int wdt_reset; + volatile unsigned int int_status; + volatile unsigned int lf_timer0; + volatile unsigned int lf_timer_count0; + volatile unsigned int lf_timer_control0; + volatile unsigned int lf_timer_status0; + volatile unsigned int lf_timer1; + volatile unsigned int lf_timer_count1; + volatile unsigned int lf_timer_control1; + volatile unsigned int lf_timer_status1; + volatile unsigned int lf_timer2; + volatile unsigned int lf_timer_count2; + volatile unsigned int lf_timer_control2; + volatile unsigned int lf_timer_status2; + volatile unsigned int lf_timer3; + volatile unsigned int lf_timer_count3; + volatile unsigned int lf_timer_control3; + volatile unsigned int lf_timer_status3; + volatile unsigned int hf_timer; + volatile unsigned int hf_timer_count; + volatile unsigned int hf_lf_count; + volatile unsigned int hf_timer_control; + volatile unsigned int hf_timer_status; + volatile unsigned int rtc_control; + volatile unsigned int rtc_time; + volatile unsigned int rtc_date; + volatile unsigned int rtc_set_time; + volatile unsigned int rtc_set_date; + volatile unsigned int rtc_set_alarm; + volatile unsigned int rtc_config; + volatile unsigned int rtc_alarm_status; + volatile unsigned int uart_wakeup; + volatile unsigned int reset_cause; + volatile unsigned int system_sleep; + volatile unsigned int sdio_wrapper; + volatile unsigned int mac_sleep_control; + volatile unsigned int keep_awake; + volatile unsigned int lpo_cal_time; + volatile unsigned int lpo_init_dividend_int; + volatile unsigned int lpo_init_dividend_fraction; + volatile unsigned int lpo_cal; + volatile unsigned int lpo_cal_test_control; + volatile unsigned int lpo_cal_test_status; + volatile unsigned int chip_id; + volatile unsigned int derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int mac_pcu_slp_beacon; + volatile unsigned int power_reg; + volatile unsigned int core_clk_ctrl; + unsigned char pad0[8]; /* pad to 0x120 */ + volatile unsigned int sdio_setup_circuit[8]; + volatile unsigned int sdio_setup_config; + volatile unsigned int cpu_setup_config; + unsigned char pad1[24]; /* pad to 0x160 */ + volatile unsigned int cpu_setup_circuit[8]; + volatile unsigned int bb_setup_config; + unsigned char pad2[28]; /* pad to 0x1a0 */ + volatile unsigned int bb_setup_circuit[8]; + volatile unsigned int gpio_wakeup_control; +} rtc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_si_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_si_reg.h new file mode 100644 index 00000000000..950f63560ef --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_si_reg.h @@ -0,0 +1,209 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x)&SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x)&SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x)&SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x)&SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x)&SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x)&SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x)&SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x)&SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x)&SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x)&SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x)&SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x)&SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x)&SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x)&SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x)&SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x)&SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x)&SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x)&SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x)&SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x)&SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x)&SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x)&SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x)&SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x)&SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x)&SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x)&SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x)&SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x)&SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x)&SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x)&SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s +{ + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_uart_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_uart_reg.h new file mode 100644 index 00000000000..0c75ab2a700 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_uart_reg.h @@ -0,0 +1,350 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define RBR_ADDRESS 0x00000000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x)&RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00000000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x)&THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00000000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x)&DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00000004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x)&DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00000004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x)&IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x)&IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x)&IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x)&IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00000008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x)&IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x)&IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00000008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x)&FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x)&FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x)&FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x)&FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x)&FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0000000c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x)&LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x)&LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x)&LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x)&LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x)&LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x)&LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00000010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x)&MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x)&MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x)&MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x)&MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x)&MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00000014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x)&LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x)&LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x)&LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x)&LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x)&LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x)&LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x)&LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x)&LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00000018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x)&MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x)&MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x)&MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x)&MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x)&MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x)&MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x)&MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x)&MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + +#define SCR_ADDRESS 0x0000001c +#define SCR_OFFSET 0x0000001c +#define SCR_SCR_MSB 7 +#define SCR_SCR_LSB 0 +#define SCR_SCR_MASK 0x000000ff +#define SCR_SCR_GET(x) (((x)&SCR_SCR_MASK) >> SCR_SCR_LSB) +#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) + +#define SRBR_ADDRESS 0x00000020 +#define SRBR_OFFSET 0x00000020 +#define SRBR_SRBR_MSB 7 +#define SRBR_SRBR_LSB 0 +#define SRBR_SRBR_MASK 0x000000ff +#define SRBR_SRBR_GET(x) (((x)&SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) +#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) + +#define SIIR_ADDRESS 0x00000028 +#define SIIR_OFFSET 0x00000028 +#define SIIR_SIIR_MSB 7 +#define SIIR_SIIR_LSB 0 +#define SIIR_SIIR_MASK 0x000000ff +#define SIIR_SIIR_GET(x) (((x)&SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) +#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) + +#define MWR_ADDRESS 0x0000002c +#define MWR_OFFSET 0x0000002c +#define MWR_MWR_MSB 31 +#define MWR_MWR_LSB 0 +#define MWR_MWR_MASK 0xffffffff +#define MWR_MWR_GET(x) (((x)&MWR_MWR_MASK) >> MWR_MWR_LSB) +#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) + +#define SLSR_ADDRESS 0x00000034 +#define SLSR_OFFSET 0x00000034 +#define SLSR_SLSR_MSB 7 +#define SLSR_SLSR_LSB 0 +#define SLSR_SLSR_MASK 0x000000ff +#define SLSR_SLSR_GET(x) (((x)&SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) +#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) + +#define SMSR_ADDRESS 0x00000038 +#define SMSR_OFFSET 0x00000038 +#define SMSR_SMSR_MSB 7 +#define SMSR_SMSR_LSB 0 +#define SMSR_SMSR_MASK 0x000000ff +#define SMSR_SMSR_GET(x) (((x)&SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) +#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) + +#define MRR_ADDRESS 0x0000003c +#define MRR_OFFSET 0x0000003c +#define MRR_MRR_MSB 31 +#define MRR_MRR_LSB 0 +#define MRR_MRR_MASK 0xffffffff +#define MRR_MRR_GET(x) (((x)&MRR_MRR_MASK) >> MRR_MRR_LSB) +#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s +{ + volatile unsigned int rbr; + volatile unsigned int dlh; + volatile unsigned int iir; + volatile unsigned int lcr; + volatile unsigned int mcr; + volatile unsigned int lsr; + volatile unsigned int msr; + volatile unsigned int scr; + volatile unsigned int srbr; + unsigned char pad0[4]; /* pad to 0x28 */ + volatile unsigned int siir; + volatile unsigned int mwr; + unsigned char pad1[4]; /* pad to 0x34 */ + volatile unsigned int slsr; + volatile unsigned int smsr; + volatile unsigned int mrr; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_vmc_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_vmc_reg.h new file mode 100644 index 00000000000..53d25f29862 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw2.0/hw/hw20_vmc_reg.h @@ -0,0 +1,101 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _VMC_REG_REG_H_ +#define _VMC_REG_REG_H_ + +#define MC_TCAM_VALID_ADDRESS 0x00000000 +#define MC_TCAM_VALID_OFFSET 0x00000000 +#define MC_TCAM_VALID_BIT_MSB 0 +#define MC_TCAM_VALID_BIT_LSB 0 +#define MC_TCAM_VALID_BIT_MASK 0x00000001 +#define MC_TCAM_VALID_BIT_GET(x) (((x)&MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB) +#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK) + +#define MC_TCAM_MASK_ADDRESS 0x00000080 +#define MC_TCAM_MASK_OFFSET 0x00000080 +#define MC_TCAM_MASK_SIZE_MSB 2 +#define MC_TCAM_MASK_SIZE_LSB 0 +#define MC_TCAM_MASK_SIZE_MASK 0x00000007 +#define MC_TCAM_MASK_SIZE_GET(x) (((x)&MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB) +#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK) + +#define MC_TCAM_COMPARE_ADDRESS 0x00000100 +#define MC_TCAM_COMPARE_OFFSET 0x00000100 +#define MC_TCAM_COMPARE_KEY_MSB 21 +#define MC_TCAM_COMPARE_KEY_LSB 5 +#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 +#define MC_TCAM_COMPARE_KEY_GET(x) (((x)&MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB) +#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK) + +#define MC_TCAM_TARGET_ADDRESS 0x00000180 +#define MC_TCAM_TARGET_OFFSET 0x00000180 +#define MC_TCAM_TARGET_ADDR_MSB 21 +#define MC_TCAM_TARGET_ADDR_LSB 5 +#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 +#define MC_TCAM_TARGET_ADDR_GET(x) (((x)&MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB) +#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK) + +#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 +#define ADDR_ERROR_CONTROL_OFFSET 0x00000200 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) \ + (((x)&ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) \ + (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x)&ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define ADDR_ERROR_STATUS_ADDRESS 0x00000204 +#define ADDR_ERROR_STATUS_OFFSET 0x00000204 +#define ADDR_ERROR_STATUS_WRITE_MSB 25 +#define ADDR_ERROR_STATUS_WRITE_LSB 25 +#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x)&ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) +#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) +#define ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x)&ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) +#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct vmc_reg_reg_s +{ + volatile unsigned int mc_tcam_valid[32]; + volatile unsigned int mc_tcam_mask[32]; + volatile unsigned int mc_tcam_compare[32]; + volatile unsigned int mc_tcam_target[32]; + volatile unsigned int addr_error_control; + volatile unsigned int addr_error_status; +} vmc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw4.0/hw/hw40_rtc_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw4.0/hw/hw40_rtc_reg.h new file mode 100644 index 00000000000..3db97b7b327 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw4.0/hw/hw40_rtc_reg.h @@ -0,0 +1,968 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#include "hw40_rtc_wlan_reg.h" + +#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS +#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET +#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB +#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB +#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK +#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) +#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) +#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB +#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB +#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK +#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) +#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) +#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB +#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB +#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK +#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) +#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB +#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB +#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB +#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB +#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) +#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB +#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB +#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK +#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x) +#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x) +#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB +#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB +#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK +#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x) +#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x) +#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB +#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB +#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK +#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x) +#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB +#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB +#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK +#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) +#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB +#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB +#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK +#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) +#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB +#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB +#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK +#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) +#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB +#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB +#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK +#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x) +#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x) +#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB +#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB +#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK +#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x) +#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x) +#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB +#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB +#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK +#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x) +#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x) +#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS +#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET +#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB +#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB +#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK +#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x) +#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x) +#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS +#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET +#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB +#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB +#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK +#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x) +#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x) +#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS +#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET +#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB +#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB +#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK +#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x) +#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x) +#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS +#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET +#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB +#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB +#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK +#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x) +#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x) +#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB +#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB +#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK +#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x) +#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x) +#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB +#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB +#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK +#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x) +#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x) +#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS +#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET +#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB +#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB +#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) +#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB +#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB +#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) +#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB +#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB +#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK +#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x) +#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x) +#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB +#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB +#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK +#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x) +#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x) +#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB +#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB +#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK +#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x) +#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x) +#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB +#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB +#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK +#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x) +#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x) +#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB +#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB +#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK +#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x) +#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x) +#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS +#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET +#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB +#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB +#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK +#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x) +#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x) +#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS +#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET +#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB +#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB +#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK +#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x) +#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x) +#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS +#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET +#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB +#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK +#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x) +#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x) +#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS +#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET +#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB +#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB +#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK +#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x) +#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x) +#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB +#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB +#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK +#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) +#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) +#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB +#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB +#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK +#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) +#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) +#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS +#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET +#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB +#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB +#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK +#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x) +#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x) +#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS +#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET +#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB +#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB +#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK +#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x) +#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x) +#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS +#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET +#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB +#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB +#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK +#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x) +#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x) +#define WDT_ADDRESS WLAN_WDT_ADDRESS +#define WDT_OFFSET WLAN_WDT_OFFSET +#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB +#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB +#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK +#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x) +#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x) +#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS +#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET +#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB +#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB +#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK +#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x) +#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x) +#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS +#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET +#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB +#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB +#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK +#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x) +#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x) +#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS +#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET +#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB +#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB +#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK +#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x) +#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x) +#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB +#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB +#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK +#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x) +#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x) +#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB +#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB +#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK +#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) +#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) +#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB +#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB +#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK +#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x) +#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x) +#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB +#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB +#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK +#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x) +#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x) +#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB +#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB +#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK +#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x) +#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x) +#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB +#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB +#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK +#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x) +#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x) +#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB +#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB +#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK +#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x) +#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x) +#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB +#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB +#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK +#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x) +#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x) +#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB +#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB +#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK +#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x) +#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x) +#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB +#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB +#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK +#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x) +#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x) +#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB +#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB +#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK +#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x) +#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x) +#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB +#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB +#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK +#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x) +#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x) +#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB +#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB +#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK +#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x) +#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x) +#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB +#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB +#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK +#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x) +#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x) +#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB +#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB +#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK +#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x) +#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x) +#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB +#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB +#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK +#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x) +#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x) +#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB +#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB +#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK +#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x) +#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x) +#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB +#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB +#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK +#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x) +#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x) +#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB +#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB +#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK +#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x) +#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x) +#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB +#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB +#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK +#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x) +#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x) +#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB +#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB +#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK +#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x) +#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x) +#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS +#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET +#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB +#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB +#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK +#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x) +#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x) +#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS +#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET +#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB +#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB +#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK +#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x) +#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x) +#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS +#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET +#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB +#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB +#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK +#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB +#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB +#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK +#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x) +#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x) +#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS +#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET +#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB +#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB +#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) +#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS +#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET +#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB +#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB +#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK +#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x) +#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x) +#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS +#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET +#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB +#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB +#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK +#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x) +#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x) +#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS +#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET +#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB +#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB +#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK +#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB +#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB +#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK +#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x) +#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x) +#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS +#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET +#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB +#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB +#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) +#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS +#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET +#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB +#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB +#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK +#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x) +#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x) +#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS +#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET +#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB +#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB +#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK +#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x) +#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x) +#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS +#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET +#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB +#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB +#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK +#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB +#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB +#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK +#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x) +#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x) +#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS +#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET +#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB +#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB +#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) +#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS +#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET +#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB +#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB +#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK +#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x) +#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x) +#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS +#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET +#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB +#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB +#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK +#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x) +#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x) +#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS +#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET +#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB +#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB +#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK +#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB +#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB +#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK +#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x) +#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x) +#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS +#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET +#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB +#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB +#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) +#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS +#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET +#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB +#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB +#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK +#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x) +#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x) +#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS +#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET +#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB +#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB +#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK +#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x) +#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x) +#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS +#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET +#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB +#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB +#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK +#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x) +#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x) +#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS +#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET +#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB +#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB +#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK +#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) +#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) +#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB +#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB +#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK +#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x) +#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) +#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB +#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB +#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK +#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x) +#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x) +#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS +#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET +#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB +#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB +#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK +#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) +#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS +#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET +#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB +#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB +#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK +#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x) +#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x) +#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB +#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB +#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK +#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x) +#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x) +#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB +#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB +#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK +#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) +#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) +#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS +#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET +#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB +#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB +#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK +#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x) +#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x) +#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB +#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB +#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK +#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x) +#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x) +#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB +#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB +#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK +#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x) +#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x) +#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB +#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB +#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK +#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x) +#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x) +#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS +#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET +#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB +#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB +#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK +#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x) +#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x) +#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB +#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB +#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK +#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x) +#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x) +#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB +#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB +#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK +#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x) +#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x) +#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS +#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET +#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB +#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB +#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK +#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) +#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) +#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB +#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB +#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK +#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x) +#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x) +#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB +#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB +#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK +#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x) +#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x) +#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB +#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB +#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK +#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x) +#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x) +#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS +#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET +#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB +#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB +#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK +#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x) +#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x) +#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB +#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB +#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK +#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x) +#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x) +#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB +#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB +#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK +#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) +#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) +#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS +#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET +#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB +#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB +#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK +#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x) +#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x) +#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB +#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB +#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK +#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x) +#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x) +#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB +#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB +#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK +#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x) +#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x) +#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS +#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET +#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB +#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB +#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK +#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x) +#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x) +#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB +#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB +#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK +#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) +#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB +#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB +#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK +#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x) +#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x) +#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS +#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET +#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB +#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB +#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK +#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) +#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) +#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB +#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB +#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) +#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS +#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET +#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB +#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB +#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK +#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x) +#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x) +#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS +#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET +#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB +#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB +#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK +#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x) +#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x) +#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS +#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET +#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB +#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB +#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK +#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) +#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) +#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB +#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB +#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK +#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x) +#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x) +#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB +#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB +#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK +#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) +#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) +#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB +#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB +#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK +#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x) +#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x) +#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB +#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB +#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK +#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x) +#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x) +#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS +#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET +#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB +#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB +#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK +#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x) +#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x) +#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB +#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB +#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK +#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x) +#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x) +#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB +#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB +#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK +#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x) +#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x) +#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB +#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB +#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK +#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x) +#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x) +#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS +#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET +#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB +#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB +#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) +#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS +#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET +#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB +#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB +#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK +#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x) +#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x) +#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS +#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET +#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB +#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB +#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK +#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x) +#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x) +#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS +#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) +#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS +#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET +#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB +#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK +#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x) +#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x) +#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB +#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB +#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK +#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x) +#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x) +#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS +#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) +#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS +#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET +#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB +#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB +#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK +#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) +#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) +#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB +#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB +#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) +#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS +#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET +#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB +#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB +#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK +#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x) +#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x) +#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB +#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB +#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK +#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x) +#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x) +#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB +#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB +#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK +#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x) +#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x) +#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS +#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) +#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB +#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB +#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK +#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x) +#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x) +#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB +#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB +#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK +#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) +#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) +#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS +#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) +#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB +#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB +#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK +#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x) +#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x) +#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB +#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB +#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK +#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) +#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB +#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB +#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK +#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) +#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB +#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB +#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK +#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x) +#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x) +#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB +#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB +#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK +#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) +#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) +#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB +#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB +#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK +#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) +#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) +#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB +#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB +#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK +#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) +#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB +#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB +#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK +#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x) +#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x) +#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB +#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB +#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK +#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x) +#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x) +#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB +#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB +#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK +#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x) +#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x) +#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB +#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB +#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK +#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x) +#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x) +#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB +#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB +#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK +#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x) +#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x) +#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS +#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET +#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB +#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB +#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK +#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x) +#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x) +#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS +#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw4.0/hw/hw40_rtc_wlan_reg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw4.0/hw/hw40_rtc_wlan_reg.h new file mode 100644 index 00000000000..ffc1b0595d8 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/AR6002/hw4.0/hw/hw40_rtc_wlan_reg.h @@ -0,0 +1,2212 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _RTC_WLAN_REG_REG_H_ +#define _RTC_WLAN_REG_REG_H_ + +#define WLAN_RESET_CONTROL_ADDRESS 0x00000000 +#define WLAN_RESET_CONTROL_OFFSET 0x00000000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00004000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) \ + (((x)&WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) \ + (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) +#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK 0x00002000 +#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) \ + (((x)&WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) \ + (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK 0x00001000 +#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) \ + (((x)&WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) \ + (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) \ + (((x)&WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) \ + (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) \ + (((x)&WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) \ + (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define WLAN_RESET_CONTROL_RST_OUT_MSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_LSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define WLAN_RESET_CONTROL_RST_OUT_GET(x) (((x)&WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB) +#define WLAN_RESET_CONTROL_RST_OUT_SET(x) (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK) +#define WLAN_RESET_CONTROL_COLD_RST_MSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_LSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define WLAN_RESET_CONTROL_COLD_RST_GET(x) (((x)&WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_WARM_RST_MSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_LSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define WLAN_RESET_CONTROL_WARM_RST_GET(x) (((x)&WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) \ + (((x)&WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) \ + (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) \ + (((x)&WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) \ + (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) \ + (((x)&WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) \ + (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MBOX_RST_MSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_LSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define WLAN_RESET_CONTROL_MBOX_RST_GET(x) (((x)&WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB) +#define WLAN_RESET_CONTROL_MBOX_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK) +#define WLAN_RESET_CONTROL_UART_RST_MSB 1 +#define WLAN_RESET_CONTROL_UART_RST_LSB 1 +#define WLAN_RESET_CONTROL_UART_RST_MASK 0x00000002 +#define WLAN_RESET_CONTROL_UART_RST_GET(x) (((x)&WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB) +#define WLAN_RESET_CONTROL_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK) +#define WLAN_RESET_CONTROL_SI0_RST_MSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_LSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x)&WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB) +#define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK) + +#define WLAN_XTAL_CONTROL_ADDRESS 0x00000004 +#define WLAN_XTAL_CONTROL_OFFSET 0x00000004 +#define WLAN_XTAL_CONTROL_TCXO_MSB 0 +#define WLAN_XTAL_CONTROL_TCXO_LSB 0 +#define WLAN_XTAL_CONTROL_TCXO_MASK 0x00000001 +#define WLAN_XTAL_CONTROL_TCXO_GET(x) (((x)&WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB) +#define WLAN_XTAL_CONTROL_TCXO_SET(x) (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK) + +#define WLAN_TCXO_DETECT_ADDRESS 0x00000008 +#define WLAN_TCXO_DETECT_OFFSET 0x00000008 +#define WLAN_TCXO_DETECT_PRESENT_MSB 0 +#define WLAN_TCXO_DETECT_PRESENT_LSB 0 +#define WLAN_TCXO_DETECT_PRESENT_MASK 0x00000001 +#define WLAN_TCXO_DETECT_PRESENT_GET(x) (((x)&WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB) +#define WLAN_TCXO_DETECT_PRESENT_SET(x) (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK) + +#define WLAN_XTAL_TEST_ADDRESS 0x0000000c +#define WLAN_XTAL_TEST_OFFSET 0x0000000c +#define WLAN_XTAL_TEST_NOTCXODET_MSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_LSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define WLAN_XTAL_TEST_NOTCXODET_GET(x) (((x)&WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB) +#define WLAN_XTAL_TEST_NOTCXODET_SET(x) (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK) + +#define WLAN_QUADRATURE_ADDRESS 0x00000010 +#define WLAN_QUADRATURE_OFFSET 0x00000010 +#define WLAN_QUADRATURE_ADC_MSB 7 +#define WLAN_QUADRATURE_ADC_LSB 4 +#define WLAN_QUADRATURE_ADC_MASK 0x000000f0 +#define WLAN_QUADRATURE_ADC_GET(x) (((x)&WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB) +#define WLAN_QUADRATURE_ADC_SET(x) (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK) +#define WLAN_QUADRATURE_SEL_MSB 2 +#define WLAN_QUADRATURE_SEL_LSB 2 +#define WLAN_QUADRATURE_SEL_MASK 0x00000004 +#define WLAN_QUADRATURE_SEL_GET(x) (((x)&WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB) +#define WLAN_QUADRATURE_SEL_SET(x) (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK) +#define WLAN_QUADRATURE_DAC_MSB 1 +#define WLAN_QUADRATURE_DAC_LSB 0 +#define WLAN_QUADRATURE_DAC_MASK 0x00000003 +#define WLAN_QUADRATURE_DAC_GET(x) (((x)&WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB) +#define WLAN_QUADRATURE_DAC_SET(x) (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK) + +#define WLAN_PLL_CONTROL_ADDRESS 0x00000014 +#define WLAN_PLL_CONTROL_OFFSET 0x00000014 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) \ + (((x)&WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) \ + (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) \ + (((x)&WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) \ + (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) +#define WLAN_PLL_CONTROL_NOPWD_MSB 18 +#define WLAN_PLL_CONTROL_NOPWD_LSB 18 +#define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 +#define WLAN_PLL_CONTROL_NOPWD_GET(x) (((x)&WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) +#define WLAN_PLL_CONTROL_NOPWD_SET(x) (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) +#define WLAN_PLL_CONTROL_UPDATING_MSB 17 +#define WLAN_PLL_CONTROL_UPDATING_LSB 17 +#define WLAN_PLL_CONTROL_UPDATING_MASK 0x00020000 +#define WLAN_PLL_CONTROL_UPDATING_GET(x) (((x)&WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB) +#define WLAN_PLL_CONTROL_UPDATING_SET(x) (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK) +#define WLAN_PLL_CONTROL_BYPASS_MSB 16 +#define WLAN_PLL_CONTROL_BYPASS_LSB 16 +#define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 +#define WLAN_PLL_CONTROL_BYPASS_GET(x) (((x)&WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) +#define WLAN_PLL_CONTROL_BYPASS_SET(x) (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) +#define WLAN_PLL_CONTROL_REFDIV_MSB 15 +#define WLAN_PLL_CONTROL_REFDIV_LSB 12 +#define WLAN_PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define WLAN_PLL_CONTROL_REFDIV_GET(x) (((x)&WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) +#define WLAN_PLL_CONTROL_REFDIV_SET(x) (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) +#define WLAN_PLL_CONTROL_DIV_MSB 9 +#define WLAN_PLL_CONTROL_DIV_LSB 0 +#define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff +#define WLAN_PLL_CONTROL_DIV_GET(x) (((x)&WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) +#define WLAN_PLL_CONTROL_DIV_SET(x) (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) + +#define WLAN_PLL_SETTLE_ADDRESS 0x00000018 +#define WLAN_PLL_SETTLE_OFFSET 0x00000018 +#define WLAN_PLL_SETTLE_TIME_MSB 11 +#define WLAN_PLL_SETTLE_TIME_LSB 0 +#define WLAN_PLL_SETTLE_TIME_MASK 0x00000fff +#define WLAN_PLL_SETTLE_TIME_GET(x) (((x)&WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) +#define WLAN_PLL_SETTLE_TIME_SET(x) (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) + +#define WLAN_XTAL_SETTLE_ADDRESS 0x0000001c +#define WLAN_XTAL_SETTLE_OFFSET 0x0000001c +#define WLAN_XTAL_SETTLE_TIME_MSB 7 +#define WLAN_XTAL_SETTLE_TIME_LSB 0 +#define WLAN_XTAL_SETTLE_TIME_MASK 0x000000ff +#define WLAN_XTAL_SETTLE_TIME_GET(x) (((x)&WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB) +#define WLAN_XTAL_SETTLE_TIME_SET(x) (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK) + +#define WLAN_CPU_CLOCK_ADDRESS 0x00000020 +#define WLAN_CPU_CLOCK_OFFSET 0x00000020 +#define WLAN_CPU_CLOCK_STANDARD_MSB 1 +#define WLAN_CPU_CLOCK_STANDARD_LSB 0 +#define WLAN_CPU_CLOCK_STANDARD_MASK 0x00000003 +#define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x)&WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB) +#define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK) + +#define WLAN_CLOCK_OUT_ADDRESS 0x00000024 +#define WLAN_CLOCK_OUT_OFFSET 0x00000024 +#define WLAN_CLOCK_OUT_SELECT_MSB 3 +#define WLAN_CLOCK_OUT_SELECT_LSB 0 +#define WLAN_CLOCK_OUT_SELECT_MASK 0x0000000f +#define WLAN_CLOCK_OUT_SELECT_GET(x) (((x)&WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB) +#define WLAN_CLOCK_OUT_SELECT_SET(x) (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK) + +#define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028 +#define WLAN_CLOCK_CONTROL_OFFSET 0x00000028 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) (((x)&WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB) +#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) +#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x)&WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB) +#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) + +#define WLAN_BIAS_OVERRIDE_ADDRESS 0x0000002c +#define WLAN_BIAS_OVERRIDE_OFFSET 0x0000002c +#define WLAN_BIAS_OVERRIDE_ON_MSB 0 +#define WLAN_BIAS_OVERRIDE_ON_LSB 0 +#define WLAN_BIAS_OVERRIDE_ON_MASK 0x00000001 +#define WLAN_BIAS_OVERRIDE_ON_GET(x) (((x)&WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB) +#define WLAN_BIAS_OVERRIDE_ON_SET(x) (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK) + +#define WLAN_WDT_CONTROL_ADDRESS 0x00000030 +#define WLAN_WDT_CONTROL_OFFSET 0x00000030 +#define WLAN_WDT_CONTROL_ACTION_MSB 2 +#define WLAN_WDT_CONTROL_ACTION_LSB 0 +#define WLAN_WDT_CONTROL_ACTION_MASK 0x00000007 +#define WLAN_WDT_CONTROL_ACTION_GET(x) (((x)&WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB) +#define WLAN_WDT_CONTROL_ACTION_SET(x) (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK) + +#define WLAN_WDT_STATUS_ADDRESS 0x00000034 +#define WLAN_WDT_STATUS_OFFSET 0x00000034 +#define WLAN_WDT_STATUS_INTERRUPT_MSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_LSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_WDT_STATUS_INTERRUPT_GET(x) (((x)&WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB) +#define WLAN_WDT_STATUS_INTERRUPT_SET(x) (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK) + +#define WLAN_WDT_ADDRESS 0x00000038 +#define WLAN_WDT_OFFSET 0x00000038 +#define WLAN_WDT_TARGET_MSB 21 +#define WLAN_WDT_TARGET_LSB 0 +#define WLAN_WDT_TARGET_MASK 0x003fffff +#define WLAN_WDT_TARGET_GET(x) (((x)&WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB) +#define WLAN_WDT_TARGET_SET(x) (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK) + +#define WLAN_WDT_COUNT_ADDRESS 0x0000003c +#define WLAN_WDT_COUNT_OFFSET 0x0000003c +#define WLAN_WDT_COUNT_VALUE_MSB 21 +#define WLAN_WDT_COUNT_VALUE_LSB 0 +#define WLAN_WDT_COUNT_VALUE_MASK 0x003fffff +#define WLAN_WDT_COUNT_VALUE_GET(x) (((x)&WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB) +#define WLAN_WDT_COUNT_VALUE_SET(x) (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK) + +#define WLAN_WDT_RESET_ADDRESS 0x00000040 +#define WLAN_WDT_RESET_OFFSET 0x00000040 +#define WLAN_WDT_RESET_VALUE_MSB 0 +#define WLAN_WDT_RESET_VALUE_LSB 0 +#define WLAN_WDT_RESET_VALUE_MASK 0x00000001 +#define WLAN_WDT_RESET_VALUE_GET(x) (((x)&WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB) +#define WLAN_WDT_RESET_VALUE_SET(x) (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK) + +#define WLAN_INT_STATUS_ADDRESS 0x00000044 +#define WLAN_INT_STATUS_OFFSET 0x00000044 +#define WLAN_INT_STATUS_HCI_UART_MSB 21 +#define WLAN_INT_STATUS_HCI_UART_LSB 21 +#define WLAN_INT_STATUS_HCI_UART_MASK 0x00200000 +#define WLAN_INT_STATUS_HCI_UART_GET(x) (((x)&WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB) +#define WLAN_INT_STATUS_HCI_UART_SET(x) (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK) +#define WLAN_INT_STATUS_THERM_MSB 20 +#define WLAN_INT_STATUS_THERM_LSB 20 +#define WLAN_INT_STATUS_THERM_MASK 0x00100000 +#define WLAN_INT_STATUS_THERM_GET(x) (((x)&WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB) +#define WLAN_INT_STATUS_THERM_SET(x) (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK 0x00080000 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) \ + (((x)&WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) \ + (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) +#define WLAN_INT_STATUS_UART_MBOX_MSB 18 +#define WLAN_INT_STATUS_UART_MBOX_LSB 18 +#define WLAN_INT_STATUS_UART_MBOX_MASK 0x00040000 +#define WLAN_INT_STATUS_UART_MBOX_GET(x) (((x)&WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB) +#define WLAN_INT_STATUS_UART_MBOX_SET(x) (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK) +#define WLAN_INT_STATUS_GENERIC_MBOX_MSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_LSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_MASK 0x00020000 +#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x) \ + (((x)&WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB) +#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x) \ + (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) +#define WLAN_INT_STATUS_RDMA_MSB 16 +#define WLAN_INT_STATUS_RDMA_LSB 16 +#define WLAN_INT_STATUS_RDMA_MASK 0x00010000 +#define WLAN_INT_STATUS_RDMA_GET(x) (((x)&WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB) +#define WLAN_INT_STATUS_RDMA_SET(x) (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK) +#define WLAN_INT_STATUS_BTCOEX_MSB 15 +#define WLAN_INT_STATUS_BTCOEX_LSB 15 +#define WLAN_INT_STATUS_BTCOEX_MASK 0x00008000 +#define WLAN_INT_STATUS_BTCOEX_GET(x) (((x)&WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB) +#define WLAN_INT_STATUS_BTCOEX_SET(x) (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK) +#define WLAN_INT_STATUS_RTC_POWER_MSB 14 +#define WLAN_INT_STATUS_RTC_POWER_LSB 14 +#define WLAN_INT_STATUS_RTC_POWER_MASK 0x00004000 +#define WLAN_INT_STATUS_RTC_POWER_GET(x) (((x)&WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB) +#define WLAN_INT_STATUS_RTC_POWER_SET(x) (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK) +#define WLAN_INT_STATUS_MAC_MSB 13 +#define WLAN_INT_STATUS_MAC_LSB 13 +#define WLAN_INT_STATUS_MAC_MASK 0x00002000 +#define WLAN_INT_STATUS_MAC_GET(x) (((x)&WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB) +#define WLAN_INT_STATUS_MAC_SET(x) (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK) +#define WLAN_INT_STATUS_MAILBOX_MSB 12 +#define WLAN_INT_STATUS_MAILBOX_LSB 12 +#define WLAN_INT_STATUS_MAILBOX_MASK 0x00001000 +#define WLAN_INT_STATUS_MAILBOX_GET(x) (((x)&WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB) +#define WLAN_INT_STATUS_MAILBOX_SET(x) (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK) +#define WLAN_INT_STATUS_RTC_ALARM_MSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_LSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define WLAN_INT_STATUS_RTC_ALARM_GET(x) (((x)&WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB) +#define WLAN_INT_STATUS_RTC_ALARM_SET(x) (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK) +#define WLAN_INT_STATUS_HF_TIMER_MSB 10 +#define WLAN_INT_STATUS_HF_TIMER_LSB 10 +#define WLAN_INT_STATUS_HF_TIMER_MASK 0x00000400 +#define WLAN_INT_STATUS_HF_TIMER_GET(x) (((x)&WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB) +#define WLAN_INT_STATUS_HF_TIMER_SET(x) (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK) +#define WLAN_INT_STATUS_LF_TIMER3_MSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_LSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define WLAN_INT_STATUS_LF_TIMER3_GET(x) (((x)&WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB) +#define WLAN_INT_STATUS_LF_TIMER3_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK) +#define WLAN_INT_STATUS_LF_TIMER2_MSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_LSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define WLAN_INT_STATUS_LF_TIMER2_GET(x) (((x)&WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB) +#define WLAN_INT_STATUS_LF_TIMER2_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK) +#define WLAN_INT_STATUS_LF_TIMER1_MSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_LSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define WLAN_INT_STATUS_LF_TIMER1_GET(x) (((x)&WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB) +#define WLAN_INT_STATUS_LF_TIMER1_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK) +#define WLAN_INT_STATUS_LF_TIMER0_MSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_LSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define WLAN_INT_STATUS_LF_TIMER0_GET(x) (((x)&WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB) +#define WLAN_INT_STATUS_LF_TIMER0_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK) +#define WLAN_INT_STATUS_KEYPAD_MSB 5 +#define WLAN_INT_STATUS_KEYPAD_LSB 5 +#define WLAN_INT_STATUS_KEYPAD_MASK 0x00000020 +#define WLAN_INT_STATUS_KEYPAD_GET(x) (((x)&WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB) +#define WLAN_INT_STATUS_KEYPAD_SET(x) (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK) +#define WLAN_INT_STATUS_SI_MSB 4 +#define WLAN_INT_STATUS_SI_LSB 4 +#define WLAN_INT_STATUS_SI_MASK 0x00000010 +#define WLAN_INT_STATUS_SI_GET(x) (((x)&WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB) +#define WLAN_INT_STATUS_SI_SET(x) (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK) +#define WLAN_INT_STATUS_GPIO_MSB 3 +#define WLAN_INT_STATUS_GPIO_LSB 3 +#define WLAN_INT_STATUS_GPIO_MASK 0x00000008 +#define WLAN_INT_STATUS_GPIO_GET(x) (((x)&WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB) +#define WLAN_INT_STATUS_GPIO_SET(x) (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK) +#define WLAN_INT_STATUS_UART_MSB 2 +#define WLAN_INT_STATUS_UART_LSB 2 +#define WLAN_INT_STATUS_UART_MASK 0x00000004 +#define WLAN_INT_STATUS_UART_GET(x) (((x)&WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB) +#define WLAN_INT_STATUS_UART_SET(x) (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK) +#define WLAN_INT_STATUS_ERROR_MSB 1 +#define WLAN_INT_STATUS_ERROR_LSB 1 +#define WLAN_INT_STATUS_ERROR_MASK 0x00000002 +#define WLAN_INT_STATUS_ERROR_GET(x) (((x)&WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB) +#define WLAN_INT_STATUS_ERROR_SET(x) (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK) +#define WLAN_INT_STATUS_WDT_INT_MSB 0 +#define WLAN_INT_STATUS_WDT_INT_LSB 0 +#define WLAN_INT_STATUS_WDT_INT_MASK 0x00000001 +#define WLAN_INT_STATUS_WDT_INT_GET(x) (((x)&WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB) +#define WLAN_INT_STATUS_WDT_INT_SET(x) (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK) + +#define WLAN_LF_TIMER0_ADDRESS 0x00000048 +#define WLAN_LF_TIMER0_OFFSET 0x00000048 +#define WLAN_LF_TIMER0_TARGET_MSB 31 +#define WLAN_LF_TIMER0_TARGET_LSB 0 +#define WLAN_LF_TIMER0_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER0_TARGET_GET(x) (((x)&WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB) +#define WLAN_LF_TIMER0_TARGET_SET(x) (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define WLAN_LF_TIMER_COUNT0_OFFSET 0x0000004c +#define WLAN_LF_TIMER_COUNT0_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT0_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x) (((x)&WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL0_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define WLAN_LF_TIMER_STATUS0_OFFSET 0x00000054 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) \ + (((x)&WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) \ + (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define WLAN_LF_TIMER1_ADDRESS 0x00000058 +#define WLAN_LF_TIMER1_OFFSET 0x00000058 +#define WLAN_LF_TIMER1_TARGET_MSB 31 +#define WLAN_LF_TIMER1_TARGET_LSB 0 +#define WLAN_LF_TIMER1_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER1_TARGET_GET(x) (((x)&WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB) +#define WLAN_LF_TIMER1_TARGET_SET(x) (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define WLAN_LF_TIMER_COUNT1_OFFSET 0x0000005c +#define WLAN_LF_TIMER_COUNT1_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT1_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x) (((x)&WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL1_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define WLAN_LF_TIMER_STATUS1_OFFSET 0x00000064 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) \ + (((x)&WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) \ + (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define WLAN_LF_TIMER2_ADDRESS 0x00000068 +#define WLAN_LF_TIMER2_OFFSET 0x00000068 +#define WLAN_LF_TIMER2_TARGET_MSB 31 +#define WLAN_LF_TIMER2_TARGET_LSB 0 +#define WLAN_LF_TIMER2_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER2_TARGET_GET(x) (((x)&WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB) +#define WLAN_LF_TIMER2_TARGET_SET(x) (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define WLAN_LF_TIMER_COUNT2_OFFSET 0x0000006c +#define WLAN_LF_TIMER_COUNT2_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT2_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x) (((x)&WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL2_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define WLAN_LF_TIMER_STATUS2_OFFSET 0x00000074 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) \ + (((x)&WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) \ + (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define WLAN_LF_TIMER3_ADDRESS 0x00000078 +#define WLAN_LF_TIMER3_OFFSET 0x00000078 +#define WLAN_LF_TIMER3_TARGET_MSB 31 +#define WLAN_LF_TIMER3_TARGET_LSB 0 +#define WLAN_LF_TIMER3_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER3_TARGET_GET(x) (((x)&WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB) +#define WLAN_LF_TIMER3_TARGET_SET(x) (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define WLAN_LF_TIMER_COUNT3_OFFSET 0x0000007c +#define WLAN_LF_TIMER_COUNT3_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT3_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x) (((x)&WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL3_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x) \ + (((x)&WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x) \ + (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define WLAN_LF_TIMER_STATUS3_OFFSET 0x00000084 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) \ + (((x)&WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) \ + (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define WLAN_HF_TIMER_ADDRESS 0x00000088 +#define WLAN_HF_TIMER_OFFSET 0x00000088 +#define WLAN_HF_TIMER_TARGET_MSB 31 +#define WLAN_HF_TIMER_TARGET_LSB 12 +#define WLAN_HF_TIMER_TARGET_MASK 0xfffff000 +#define WLAN_HF_TIMER_TARGET_GET(x) (((x)&WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB) +#define WLAN_HF_TIMER_TARGET_SET(x) (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK) + +#define WLAN_HF_TIMER_COUNT_ADDRESS 0x0000008c +#define WLAN_HF_TIMER_COUNT_OFFSET 0x0000008c +#define WLAN_HF_TIMER_COUNT_VALUE_MSB 31 +#define WLAN_HF_TIMER_COUNT_VALUE_LSB 12 +#define WLAN_HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define WLAN_HF_TIMER_COUNT_VALUE_GET(x) (((x)&WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB) +#define WLAN_HF_TIMER_COUNT_VALUE_SET(x) (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK) + +#define WLAN_HF_LF_COUNT_ADDRESS 0x00000090 +#define WLAN_HF_LF_COUNT_OFFSET 0x00000090 +#define WLAN_HF_LF_COUNT_VALUE_MSB 31 +#define WLAN_HF_LF_COUNT_VALUE_LSB 0 +#define WLAN_HF_LF_COUNT_VALUE_MASK 0xffffffff +#define WLAN_HF_LF_COUNT_VALUE_GET(x) (((x)&WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB) +#define WLAN_HF_LF_COUNT_VALUE_SET(x) (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK) + +#define WLAN_HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define WLAN_HF_TIMER_CONTROL_OFFSET 0x00000094 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) \ + (((x)&WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB) +#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) \ + (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) +#define WLAN_HF_TIMER_CONTROL_ON_MSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_LSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define WLAN_HF_TIMER_CONTROL_ON_GET(x) (((x)&WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB) +#define WLAN_HF_TIMER_CONTROL_ON_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) \ + (((x)&WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) \ + (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define WLAN_HF_TIMER_CONTROL_RESET_MSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_LSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define WLAN_HF_TIMER_CONTROL_RESET_GET(x) (((x)&WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB) +#define WLAN_HF_TIMER_CONTROL_RESET_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK) + +#define WLAN_HF_TIMER_STATUS_ADDRESS 0x00000098 +#define WLAN_HF_TIMER_STATUS_OFFSET 0x00000098 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) \ + (((x)&WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) +#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) \ + (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) + +#define WLAN_RTC_CONTROL_ADDRESS 0x0000009c +#define WLAN_RTC_CONTROL_OFFSET 0x0000009c +#define WLAN_RTC_CONTROL_ENABLE_MSB 2 +#define WLAN_RTC_CONTROL_ENABLE_LSB 2 +#define WLAN_RTC_CONTROL_ENABLE_MASK 0x00000004 +#define WLAN_RTC_CONTROL_ENABLE_GET(x) (((x)&WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB) +#define WLAN_RTC_CONTROL_ENABLE_SET(x) (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK) +#define WLAN_RTC_CONTROL_LOAD_RTC_MSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_LSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x) (((x)&WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB) +#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) +#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) (((x)&WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB) +#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) + +#define WLAN_RTC_TIME_ADDRESS 0x000000a0 +#define WLAN_RTC_TIME_OFFSET 0x000000a0 +#define WLAN_RTC_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_TIME_WEEK_DAY_GET(x) (((x)&WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_TIME_HOUR_MSB 21 +#define WLAN_RTC_TIME_HOUR_LSB 16 +#define WLAN_RTC_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_TIME_HOUR_GET(x) (((x)&WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB) +#define WLAN_RTC_TIME_HOUR_SET(x) (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK) +#define WLAN_RTC_TIME_MINUTE_MSB 14 +#define WLAN_RTC_TIME_MINUTE_LSB 8 +#define WLAN_RTC_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_TIME_MINUTE_GET(x) (((x)&WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB) +#define WLAN_RTC_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK) +#define WLAN_RTC_TIME_SECOND_MSB 6 +#define WLAN_RTC_TIME_SECOND_LSB 0 +#define WLAN_RTC_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_TIME_SECOND_GET(x) (((x)&WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB) +#define WLAN_RTC_TIME_SECOND_SET(x) (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK) + +#define WLAN_RTC_DATE_ADDRESS 0x000000a4 +#define WLAN_RTC_DATE_OFFSET 0x000000a4 +#define WLAN_RTC_DATE_YEAR_MSB 23 +#define WLAN_RTC_DATE_YEAR_LSB 16 +#define WLAN_RTC_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_DATE_YEAR_GET(x) (((x)&WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB) +#define WLAN_RTC_DATE_YEAR_SET(x) (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK) +#define WLAN_RTC_DATE_MONTH_MSB 12 +#define WLAN_RTC_DATE_MONTH_LSB 8 +#define WLAN_RTC_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_DATE_MONTH_GET(x) (((x)&WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB) +#define WLAN_RTC_DATE_MONTH_SET(x) (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK) +#define WLAN_RTC_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_DATE_MONTH_DAY_GET(x) (((x)&WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_TIME_ADDRESS 0x000000a8 +#define WLAN_RTC_SET_TIME_OFFSET 0x000000a8 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) (((x)&WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_SET_TIME_HOUR_MSB 21 +#define WLAN_RTC_SET_TIME_HOUR_LSB 16 +#define WLAN_RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_TIME_HOUR_GET(x) (((x)&WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB) +#define WLAN_RTC_SET_TIME_HOUR_SET(x) (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK) +#define WLAN_RTC_SET_TIME_MINUTE_MSB 14 +#define WLAN_RTC_SET_TIME_MINUTE_LSB 8 +#define WLAN_RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_TIME_MINUTE_GET(x) (((x)&WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB) +#define WLAN_RTC_SET_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK) +#define WLAN_RTC_SET_TIME_SECOND_MSB 6 +#define WLAN_RTC_SET_TIME_SECOND_LSB 0 +#define WLAN_RTC_SET_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_TIME_SECOND_GET(x) (((x)&WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB) +#define WLAN_RTC_SET_TIME_SECOND_SET(x) (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK) + +#define WLAN_RTC_SET_DATE_ADDRESS 0x000000ac +#define WLAN_RTC_SET_DATE_OFFSET 0x000000ac +#define WLAN_RTC_SET_DATE_YEAR_MSB 23 +#define WLAN_RTC_SET_DATE_YEAR_LSB 16 +#define WLAN_RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_SET_DATE_YEAR_GET(x) (((x)&WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB) +#define WLAN_RTC_SET_DATE_YEAR_SET(x) (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK) +#define WLAN_RTC_SET_DATE_MONTH_MSB 12 +#define WLAN_RTC_SET_DATE_MONTH_LSB 8 +#define WLAN_RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_SET_DATE_MONTH_GET(x) (((x)&WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB) +#define WLAN_RTC_SET_DATE_MONTH_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK) +#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) (((x)&WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_ALARM_ADDRESS 0x000000b0 +#define WLAN_RTC_SET_ALARM_OFFSET 0x000000b0 +#define WLAN_RTC_SET_ALARM_HOUR_MSB 21 +#define WLAN_RTC_SET_ALARM_HOUR_LSB 16 +#define WLAN_RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_ALARM_HOUR_GET(x) (((x)&WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB) +#define WLAN_RTC_SET_ALARM_HOUR_SET(x) (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK) +#define WLAN_RTC_SET_ALARM_MINUTE_MSB 14 +#define WLAN_RTC_SET_ALARM_MINUTE_LSB 8 +#define WLAN_RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_ALARM_MINUTE_GET(x) (((x)&WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB) +#define WLAN_RTC_SET_ALARM_MINUTE_SET(x) (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK) +#define WLAN_RTC_SET_ALARM_SECOND_MSB 6 +#define WLAN_RTC_SET_ALARM_SECOND_LSB 0 +#define WLAN_RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_ALARM_SECOND_GET(x) (((x)&WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB) +#define WLAN_RTC_SET_ALARM_SECOND_SET(x) (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK) + +#define WLAN_RTC_CONFIG_ADDRESS 0x000000b4 +#define WLAN_RTC_CONFIG_OFFSET 0x000000b4 +#define WLAN_RTC_CONFIG_BCD_MSB 2 +#define WLAN_RTC_CONFIG_BCD_LSB 2 +#define WLAN_RTC_CONFIG_BCD_MASK 0x00000004 +#define WLAN_RTC_CONFIG_BCD_GET(x) (((x)&WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB) +#define WLAN_RTC_CONFIG_BCD_SET(x) (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) (((x)&WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) +#define WLAN_RTC_CONFIG_DSE_MSB 0 +#define WLAN_RTC_CONFIG_DSE_LSB 0 +#define WLAN_RTC_CONFIG_DSE_MASK 0x00000001 +#define WLAN_RTC_CONFIG_DSE_GET(x) (((x)&WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB) +#define WLAN_RTC_CONFIG_DSE_SET(x) (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK) + +#define WLAN_RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) \ + (((x)&WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB) +#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) \ + (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) \ + (((x)&WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) \ + (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define WLAN_UART_WAKEUP_ADDRESS 0x000000bc +#define WLAN_UART_WAKEUP_OFFSET 0x000000bc +#define WLAN_UART_WAKEUP_ENABLE_MSB 0 +#define WLAN_UART_WAKEUP_ENABLE_LSB 0 +#define WLAN_UART_WAKEUP_ENABLE_MASK 0x00000001 +#define WLAN_UART_WAKEUP_ENABLE_GET(x) (((x)&WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB) +#define WLAN_UART_WAKEUP_ENABLE_SET(x) (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK) + +#define WLAN_RESET_CAUSE_ADDRESS 0x000000c0 +#define WLAN_RESET_CAUSE_OFFSET 0x000000c0 +#define WLAN_RESET_CAUSE_LAST_MSB 2 +#define WLAN_RESET_CAUSE_LAST_LSB 0 +#define WLAN_RESET_CAUSE_LAST_MASK 0x00000007 +#define WLAN_RESET_CAUSE_LAST_GET(x) (((x)&WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB) +#define WLAN_RESET_CAUSE_LAST_SET(x) (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK) + +#define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) (((x)&WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB) +#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) +#define WLAN_SYSTEM_SLEEP_MBOX_MSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_LSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define WLAN_SYSTEM_SLEEP_MBOX_GET(x) (((x)&WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB) +#define WLAN_SYSTEM_SLEEP_MBOX_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK) +#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) (((x)&WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB) +#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) +#define WLAN_SYSTEM_SLEEP_LIGHT_MSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_LSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x) (((x)&WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB) +#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) +#define WLAN_SYSTEM_SLEEP_DISABLE_MSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x)&WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB) +#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) + +#define WLAN_SDIO_WRAPPER_ADDRESS 0x000000c8 +#define WLAN_SDIO_WRAPPER_OFFSET 0x000000c8 +#define WLAN_SDIO_WRAPPER_SLEEP_MSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_LSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define WLAN_SDIO_WRAPPER_SLEEP_GET(x) (((x)&WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB) +#define WLAN_SDIO_WRAPPER_SLEEP_SET(x) (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK) +#define WLAN_SDIO_WRAPPER_WAKEUP_MSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_LSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x) (((x)&WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB) +#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x) (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) +#define WLAN_SDIO_WRAPPER_SOC_ON_MSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_LSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x) (((x)&WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB) +#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) +#define WLAN_SDIO_WRAPPER_ON_MSB 0 +#define WLAN_SDIO_WRAPPER_ON_LSB 0 +#define WLAN_SDIO_WRAPPER_ON_MASK 0x00000001 +#define WLAN_SDIO_WRAPPER_ON_GET(x) (((x)&WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB) +#define WLAN_SDIO_WRAPPER_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK) + +#define WLAN_MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) \ + (((x)&WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) \ + (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define WLAN_KEEP_AWAKE_ADDRESS 0x000000d0 +#define WLAN_KEEP_AWAKE_OFFSET 0x000000d0 +#define WLAN_KEEP_AWAKE_COUNT_MSB 7 +#define WLAN_KEEP_AWAKE_COUNT_LSB 0 +#define WLAN_KEEP_AWAKE_COUNT_MASK 0x000000ff +#define WLAN_KEEP_AWAKE_COUNT_GET(x) (((x)&WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB) +#define WLAN_KEEP_AWAKE_COUNT_SET(x) (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK) + +#define WLAN_LPO_CAL_TIME_ADDRESS 0x000000d4 +#define WLAN_LPO_CAL_TIME_OFFSET 0x000000d4 +#define WLAN_LPO_CAL_TIME_LENGTH_MSB 13 +#define WLAN_LPO_CAL_TIME_LENGTH_LSB 0 +#define WLAN_LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define WLAN_LPO_CAL_TIME_LENGTH_GET(x) (((x)&WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB) +#define WLAN_LPO_CAL_TIME_LENGTH_SET(x) (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) \ + (((x)&WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) \ + (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) \ + (((x)&WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) \ + (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define WLAN_LPO_CAL_ADDRESS 0x000000e0 +#define WLAN_LPO_CAL_OFFSET 0x000000e0 +#define WLAN_LPO_CAL_ENABLE_MSB 20 +#define WLAN_LPO_CAL_ENABLE_LSB 20 +#define WLAN_LPO_CAL_ENABLE_MASK 0x00100000 +#define WLAN_LPO_CAL_ENABLE_GET(x) (((x)&WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB) +#define WLAN_LPO_CAL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK) +#define WLAN_LPO_CAL_COUNT_MSB 19 +#define WLAN_LPO_CAL_COUNT_LSB 0 +#define WLAN_LPO_CAL_COUNT_MASK 0x000fffff +#define WLAN_LPO_CAL_COUNT_GET(x) (((x)&WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB) +#define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK) + +#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) \ + (((x)&WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) \ + (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) \ + (((x)&WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) \ + (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) \ + (((x)&WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) \ + (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) \ + (((x)&WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) \ + (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define WLAN_CHIP_ID_ADDRESS 0x000000ec +#define WLAN_CHIP_ID_OFFSET 0x000000ec +#define WLAN_CHIP_ID_DEVICE_ID_MSB 31 +#define WLAN_CHIP_ID_DEVICE_ID_LSB 16 +#define WLAN_CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define WLAN_CHIP_ID_DEVICE_ID_GET(x) (((x)&WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB) +#define WLAN_CHIP_ID_DEVICE_ID_SET(x) (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK) +#define WLAN_CHIP_ID_CONFIG_ID_MSB 15 +#define WLAN_CHIP_ID_CONFIG_ID_LSB 4 +#define WLAN_CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define WLAN_CHIP_ID_CONFIG_ID_GET(x) (((x)&WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB) +#define WLAN_CHIP_ID_CONFIG_ID_SET(x) (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK) +#define WLAN_CHIP_ID_VERSION_ID_MSB 3 +#define WLAN_CHIP_ID_VERSION_ID_LSB 0 +#define WLAN_CHIP_ID_VERSION_ID_MASK 0x0000000f +#define WLAN_CHIP_ID_VERSION_ID_GET(x) (((x)&WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB) +#define WLAN_CHIP_ID_VERSION_ID_SET(x) (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK) + +#define WLAN_DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) \ + (((x)&WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) \ + (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) \ + (((x)&WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) \ + (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define WLAN_DERIVED_RTC_CLK_FORCE_MSB 17 +#define WLAN_DERIVED_RTC_CLK_FORCE_LSB 16 +#define WLAN_DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x) (((x)&WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB) +#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) +#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB 15 +#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB 1 +#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) (((x)&WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB) +#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) \ + (((x)&MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) \ + (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) \ + (((x)&MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) \ + (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK 0x00400000 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x) \ + (((x)&MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x) \ + (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) \ + (((x)&MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) \ + (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_ENABLE_MSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_LSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_MASK 0x00100000 +#define MAC_PCU_SLP32_MODE_ENABLE_GET(x) (((x)&MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB) +#define MAC_PCU_SLP32_MODE_ENABLE_SET(x) (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) \ + (((x)&MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) \ + (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x)&MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x)&MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x)&MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x)&MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x)&MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x)&MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define WLAN_POWER_REG_ADDRESS 0x0000010c +#define WLAN_POWER_REG_OFFSET 0x0000010c +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) \ + (((x)&WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) \ + (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) +#define WLAN_POWER_REG_DEBUG_EN_MSB 14 +#define WLAN_POWER_REG_DEBUG_EN_LSB 14 +#define WLAN_POWER_REG_DEBUG_EN_MASK 0x00004000 +#define WLAN_POWER_REG_DEBUG_EN_GET(x) (((x)&WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB) +#define WLAN_POWER_REG_DEBUG_EN_SET(x) (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK 0x00002000 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) \ + (((x)&WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) \ + (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK 0x00001000 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) \ + (((x)&WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) \ + (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) +#define WLAN_POWER_REG_VLVL_MSB 11 +#define WLAN_POWER_REG_VLVL_LSB 8 +#define WLAN_POWER_REG_VLVL_MASK 0x00000f00 +#define WLAN_POWER_REG_VLVL_GET(x) (((x)&WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB) +#define WLAN_POWER_REG_VLVL_SET(x) (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK) +#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) \ + (((x)&WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB) +#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) \ + (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) +#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) (((x)&WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB) +#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) \ + (((x)&WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) \ + (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) +#define WLAN_POWER_REG_RADIO_PWD_EN_MSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_LSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x) (((x)&WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB) +#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) +#define WLAN_POWER_REG_SOC_ISO_EN_MSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_LSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_MASK 0x00000008 +#define WLAN_POWER_REG_SOC_ISO_EN_GET(x) (((x)&WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB) +#define WLAN_POWER_REG_SOC_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_ISO_EN_MSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_LSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_MASK 0x00000004 +#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x) (((x)&WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB) +#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_PWD_EN_MSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_LSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x) (((x)&WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) +#define WLAN_POWER_REG_POWER_EN_MSB 0 +#define WLAN_POWER_REG_POWER_EN_LSB 0 +#define WLAN_POWER_REG_POWER_EN_MASK 0x00000001 +#define WLAN_POWER_REG_POWER_EN_GET(x) (((x)&WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB) +#define WLAN_POWER_REG_POWER_EN_SET(x) (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK) + +#define WLAN_CORE_CLK_CTRL_ADDRESS 0x00000110 +#define WLAN_CORE_CLK_CTRL_OFFSET 0x00000110 +#define WLAN_CORE_CLK_CTRL_DIV_MSB 2 +#define WLAN_CORE_CLK_CTRL_DIV_LSB 0 +#define WLAN_CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define WLAN_CORE_CLK_CTRL_DIV_GET(x) (((x)&WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB) +#define WLAN_CORE_CLK_CTRL_DIV_SET(x) (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK) + +#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) \ + (((x)&WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) \ + (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) + +#define HT_ADDRESS 0x00000118 +#define HT_OFFSET 0x00000118 +#define HT_MODE_MSB 0 +#define HT_MODE_LSB 0 +#define HT_MODE_MASK 0x00000001 +#define HT_MODE_GET(x) (((x)&HT_MODE_MASK) >> HT_MODE_LSB) +#define HT_MODE_SET(x) (((x) << HT_MODE_LSB) & HT_MODE_MASK) + +#define MAC_PCU_TSF_L32_ADDRESS 0x0000011c +#define MAC_PCU_TSF_L32_OFFSET 0x0000011c +#define MAC_PCU_TSF_L32_VALUE_MSB 31 +#define MAC_PCU_TSF_L32_VALUE_LSB 0 +#define MAC_PCU_TSF_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_L32_VALUE_GET(x) (((x)&MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB) +#define MAC_PCU_TSF_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK) + +#define MAC_PCU_TSF_U32_ADDRESS 0x00000120 +#define MAC_PCU_TSF_U32_OFFSET 0x00000120 +#define MAC_PCU_TSF_U32_VALUE_MSB 31 +#define MAC_PCU_TSF_U32_VALUE_LSB 0 +#define MAC_PCU_TSF_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_U32_VALUE_GET(x) (((x)&MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB) +#define MAC_PCU_TSF_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK) + +#define MAC_PCU_WBTIMER_ADDRESS 0x00000124 +#define MAC_PCU_WBTIMER_OFFSET 0x00000124 +#define MAC_PCU_WBTIMER_VALUE_MSB 31 +#define MAC_PCU_WBTIMER_VALUE_LSB 0 +#define MAC_PCU_WBTIMER_VALUE_MASK 0xffffffff +#define MAC_PCU_WBTIMER_VALUE_GET(x) (((x)&MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB) +#define MAC_PCU_WBTIMER_VALUE_SET(x) (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_ADDRESS 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_OFFSET 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x) (((x)&MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) \ + (((x)&MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) \ + (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) + +#define MAC_PCU_GENERIC_TIMERS2_ADDRESS 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_OFFSET 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x) \ + (((x)&MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x) \ + (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) \ + (((x)&MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) \ + (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) + +#define MAC_PCU_SLP1_ADDRESS 0x00000204 +#define MAC_PCU_SLP1_OFFSET 0x00000204 +#define MAC_PCU_SLP1_ASSUME_DTIM_MSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_LSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_MASK 0x00080000 +#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x) (((x)&MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB) +#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x) (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) +#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB 15 +#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB 0 +#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x) (((x)&MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB) +#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) + +#define MAC_PCU_SLP2_ADDRESS 0x00000208 +#define MAC_PCU_SLP2_OFFSET 0x00000208 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB 15 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB 0 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x) (((x)&MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) +#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) + +#define MAC_PCU_RESET_TSF_ADDRESS 0x0000020c +#define MAC_PCU_RESET_TSF_OFFSET 0x0000020c +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK 0x02000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x) (((x)&MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) +#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK 0x01000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x) (((x)&MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) + +#define MAC_PCU_TSF_ADD_PLL_ADDRESS 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_OFFSET 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB 7 +#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB 0 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK 0x000000ff +#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x) (((x)&MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB) +#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x) (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) + +#define SLEEP_RETENTION_ADDRESS 0x00000214 +#define SLEEP_RETENTION_OFFSET 0x00000214 +#define SLEEP_RETENTION_TIME_MSB 9 +#define SLEEP_RETENTION_TIME_LSB 2 +#define SLEEP_RETENTION_TIME_MASK 0x000003fc +#define SLEEP_RETENTION_TIME_GET(x) (((x)&SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB) +#define SLEEP_RETENTION_TIME_SET(x) (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK) +#define SLEEP_RETENTION_MODE_MSB 1 +#define SLEEP_RETENTION_MODE_LSB 1 +#define SLEEP_RETENTION_MODE_MASK 0x00000002 +#define SLEEP_RETENTION_MODE_GET(x) (((x)&SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB) +#define SLEEP_RETENTION_MODE_SET(x) (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK) +#define SLEEP_RETENTION_ENABLE_MSB 0 +#define SLEEP_RETENTION_ENABLE_LSB 0 +#define SLEEP_RETENTION_ENABLE_MASK 0x00000001 +#define SLEEP_RETENTION_ENABLE_GET(x) (((x)&SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB) +#define SLEEP_RETENTION_ENABLE_SET(x) (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK) + +#define BTCOEXCTRL_ADDRESS 0x00000218 +#define BTCOEXCTRL_OFFSET 0x00000218 +#define BTCOEXCTRL_WBTIMER_ENABLE_MSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_LSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_MASK 0x04000000 +#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x) (((x)&BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB) +#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x) (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK 0x02000000 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x) (((x)&BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x) (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) +#define BTCOEXCTRL_PTA_MODE_MSB 24 +#define BTCOEXCTRL_PTA_MODE_LSB 23 +#define BTCOEXCTRL_PTA_MODE_MASK 0x01800000 +#define BTCOEXCTRL_PTA_MODE_GET(x) (((x)&BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB) +#define BTCOEXCTRL_PTA_MODE_SET(x) (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK) +#define BTCOEXCTRL_FREQ_TIME_MSB 22 +#define BTCOEXCTRL_FREQ_TIME_LSB 18 +#define BTCOEXCTRL_FREQ_TIME_MASK 0x007c0000 +#define BTCOEXCTRL_FREQ_TIME_GET(x) (((x)&BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB) +#define BTCOEXCTRL_FREQ_TIME_SET(x) (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK) +#define BTCOEXCTRL_PRIORITY_TIME_MSB 17 +#define BTCOEXCTRL_PRIORITY_TIME_LSB 12 +#define BTCOEXCTRL_PRIORITY_TIME_MASK 0x0003f000 +#define BTCOEXCTRL_PRIORITY_TIME_GET(x) (((x)&BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB) +#define BTCOEXCTRL_PRIORITY_TIME_SET(x) (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK) +#define BTCOEXCTRL_SYNC_DET_EN_MSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_LSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_MASK 0x00000800 +#define BTCOEXCTRL_SYNC_DET_EN_GET(x) (((x)&BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB) +#define BTCOEXCTRL_SYNC_DET_EN_SET(x) (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK) +#define BTCOEXCTRL_IDLE_CNT_EN_MSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_LSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_MASK 0x00000400 +#define BTCOEXCTRL_IDLE_CNT_EN_GET(x) (((x)&BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB) +#define BTCOEXCTRL_IDLE_CNT_EN_SET(x) (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK) +#define BTCOEXCTRL_FRAME_CNT_EN_MSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_LSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_MASK 0x00000200 +#define BTCOEXCTRL_FRAME_CNT_EN_GET(x) (((x)&BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB) +#define BTCOEXCTRL_FRAME_CNT_EN_SET(x) (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK) +#define BTCOEXCTRL_CLK_CNT_EN_MSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_LSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_MASK 0x00000100 +#define BTCOEXCTRL_CLK_CNT_EN_GET(x) (((x)&BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB) +#define BTCOEXCTRL_CLK_CNT_EN_SET(x) (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK) +#define BTCOEXCTRL_GAP_MSB 7 +#define BTCOEXCTRL_GAP_LSB 0 +#define BTCOEXCTRL_GAP_MASK 0x000000ff +#define BTCOEXCTRL_GAP_GET(x) (((x)&BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB) +#define BTCOEXCTRL_GAP_SET(x) (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK) + +#define WBSYNC_PRIORITY1_ADDRESS 0x0000021c +#define WBSYNC_PRIORITY1_OFFSET 0x0000021c +#define WBSYNC_PRIORITY1_BITMAP_MSB 31 +#define WBSYNC_PRIORITY1_BITMAP_LSB 0 +#define WBSYNC_PRIORITY1_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY1_BITMAP_GET(x) (((x)&WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB) +#define WBSYNC_PRIORITY1_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK) + +#define WBSYNC_PRIORITY2_ADDRESS 0x00000220 +#define WBSYNC_PRIORITY2_OFFSET 0x00000220 +#define WBSYNC_PRIORITY2_BITMAP_MSB 31 +#define WBSYNC_PRIORITY2_BITMAP_LSB 0 +#define WBSYNC_PRIORITY2_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY2_BITMAP_GET(x) (((x)&WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB) +#define WBSYNC_PRIORITY2_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK) + +#define WBSYNC_PRIORITY3_ADDRESS 0x00000224 +#define WBSYNC_PRIORITY3_OFFSET 0x00000224 +#define WBSYNC_PRIORITY3_BITMAP_MSB 31 +#define WBSYNC_PRIORITY3_BITMAP_LSB 0 +#define WBSYNC_PRIORITY3_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY3_BITMAP_GET(x) (((x)&WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB) +#define WBSYNC_PRIORITY3_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK) + +#define BTCOEX0_ADDRESS 0x00000228 +#define BTCOEX0_OFFSET 0x00000228 +#define BTCOEX0_SYNC_DUR_MSB 7 +#define BTCOEX0_SYNC_DUR_LSB 0 +#define BTCOEX0_SYNC_DUR_MASK 0x000000ff +#define BTCOEX0_SYNC_DUR_GET(x) (((x)&BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB) +#define BTCOEX0_SYNC_DUR_SET(x) (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK) + +#define BTCOEX1_ADDRESS 0x0000022c +#define BTCOEX1_OFFSET 0x0000022c +#define BTCOEX1_CLK_THRES_MSB 20 +#define BTCOEX1_CLK_THRES_LSB 0 +#define BTCOEX1_CLK_THRES_MASK 0x001fffff +#define BTCOEX1_CLK_THRES_GET(x) (((x)&BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB) +#define BTCOEX1_CLK_THRES_SET(x) (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK) + +#define BTCOEX2_ADDRESS 0x00000230 +#define BTCOEX2_OFFSET 0x00000230 +#define BTCOEX2_FRAME_THRES_MSB 7 +#define BTCOEX2_FRAME_THRES_LSB 0 +#define BTCOEX2_FRAME_THRES_MASK 0x000000ff +#define BTCOEX2_FRAME_THRES_GET(x) (((x)&BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB) +#define BTCOEX2_FRAME_THRES_SET(x) (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK) + +#define BTCOEX3_ADDRESS 0x00000234 +#define BTCOEX3_OFFSET 0x00000234 +#define BTCOEX3_CLK_CNT_MSB 20 +#define BTCOEX3_CLK_CNT_LSB 0 +#define BTCOEX3_CLK_CNT_MASK 0x001fffff +#define BTCOEX3_CLK_CNT_GET(x) (((x)&BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB) +#define BTCOEX3_CLK_CNT_SET(x) (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK) + +#define BTCOEX4_ADDRESS 0x00000238 +#define BTCOEX4_OFFSET 0x00000238 +#define BTCOEX4_FRAME_CNT_MSB 7 +#define BTCOEX4_FRAME_CNT_LSB 0 +#define BTCOEX4_FRAME_CNT_MASK 0x000000ff +#define BTCOEX4_FRAME_CNT_GET(x) (((x)&BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB) +#define BTCOEX4_FRAME_CNT_SET(x) (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK) + +#define BTCOEX5_ADDRESS 0x0000023c +#define BTCOEX5_OFFSET 0x0000023c +#define BTCOEX5_IDLE_CNT_MSB 15 +#define BTCOEX5_IDLE_CNT_LSB 0 +#define BTCOEX5_IDLE_CNT_MASK 0x0000ffff +#define BTCOEX5_IDLE_CNT_GET(x) (((x)&BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB) +#define BTCOEX5_IDLE_CNT_SET(x) (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK) + +#define BTCOEX6_ADDRESS 0x00000240 +#define BTCOEX6_OFFSET 0x00000240 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB 31 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB 0 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK 0xffffffff +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x) \ + (((x)&BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x) \ + (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) + +#define LOCK_ADDRESS 0x00000244 +#define LOCK_OFFSET 0x00000244 +#define LOCK_TLOCK_SLAVE_MSB 31 +#define LOCK_TLOCK_SLAVE_LSB 24 +#define LOCK_TLOCK_SLAVE_MASK 0xff000000 +#define LOCK_TLOCK_SLAVE_GET(x) (((x)&LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB) +#define LOCK_TLOCK_SLAVE_SET(x) (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK) +#define LOCK_TUNLOCK_SLAVE_MSB 23 +#define LOCK_TUNLOCK_SLAVE_LSB 16 +#define LOCK_TUNLOCK_SLAVE_MASK 0x00ff0000 +#define LOCK_TUNLOCK_SLAVE_GET(x) (((x)&LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB) +#define LOCK_TUNLOCK_SLAVE_SET(x) (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK) +#define LOCK_TLOCK_MASTER_MSB 15 +#define LOCK_TLOCK_MASTER_LSB 8 +#define LOCK_TLOCK_MASTER_MASK 0x0000ff00 +#define LOCK_TLOCK_MASTER_GET(x) (((x)&LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB) +#define LOCK_TLOCK_MASTER_SET(x) (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK) +#define LOCK_TUNLOCK_MASTER_MSB 7 +#define LOCK_TUNLOCK_MASTER_LSB 0 +#define LOCK_TUNLOCK_MASTER_MASK 0x000000ff +#define LOCK_TUNLOCK_MASTER_GET(x) (((x)&LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB) +#define LOCK_TUNLOCK_MASTER_SET(x) (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK) + +#define NOLOCK_PRIORITY_ADDRESS 0x00000248 +#define NOLOCK_PRIORITY_OFFSET 0x00000248 +#define NOLOCK_PRIORITY_BITMAP_MSB 31 +#define NOLOCK_PRIORITY_BITMAP_LSB 0 +#define NOLOCK_PRIORITY_BITMAP_MASK 0xffffffff +#define NOLOCK_PRIORITY_BITMAP_GET(x) (((x)&NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB) +#define NOLOCK_PRIORITY_BITMAP_SET(x) (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK) + +#define WBSYNC_ADDRESS 0x0000024c +#define WBSYNC_OFFSET 0x0000024c +#define WBSYNC_BTCLOCK_MSB 31 +#define WBSYNC_BTCLOCK_LSB 0 +#define WBSYNC_BTCLOCK_MASK 0xffffffff +#define WBSYNC_BTCLOCK_GET(x) (((x)&WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB) +#define WBSYNC_BTCLOCK_SET(x) (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK) + +#define WBSYNC1_ADDRESS 0x00000250 +#define WBSYNC1_OFFSET 0x00000250 +#define WBSYNC1_BTCLOCK_MSB 31 +#define WBSYNC1_BTCLOCK_LSB 0 +#define WBSYNC1_BTCLOCK_MASK 0xffffffff +#define WBSYNC1_BTCLOCK_GET(x) (((x)&WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB) +#define WBSYNC1_BTCLOCK_SET(x) (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK) + +#define WBSYNC2_ADDRESS 0x00000254 +#define WBSYNC2_OFFSET 0x00000254 +#define WBSYNC2_BTCLOCK_MSB 31 +#define WBSYNC2_BTCLOCK_LSB 0 +#define WBSYNC2_BTCLOCK_MASK 0xffffffff +#define WBSYNC2_BTCLOCK_GET(x) (((x)&WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB) +#define WBSYNC2_BTCLOCK_SET(x) (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK) + +#define WBSYNC3_ADDRESS 0x00000258 +#define WBSYNC3_OFFSET 0x00000258 +#define WBSYNC3_BTCLOCK_MSB 31 +#define WBSYNC3_BTCLOCK_LSB 0 +#define WBSYNC3_BTCLOCK_MASK 0xffffffff +#define WBSYNC3_BTCLOCK_GET(x) (((x)&WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB) +#define WBSYNC3_BTCLOCK_SET(x) (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK) + +#define WB_TIMER_TARGET_ADDRESS 0x0000025c +#define WB_TIMER_TARGET_OFFSET 0x0000025c +#define WB_TIMER_TARGET_VALUE_MSB 31 +#define WB_TIMER_TARGET_VALUE_LSB 0 +#define WB_TIMER_TARGET_VALUE_MASK 0xffffffff +#define WB_TIMER_TARGET_VALUE_GET(x) (((x)&WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB) +#define WB_TIMER_TARGET_VALUE_SET(x) (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK) + +#define WB_TIMER_SLOP_ADDRESS 0x00000260 +#define WB_TIMER_SLOP_OFFSET 0x00000260 +#define WB_TIMER_SLOP_VALUE_MSB 9 +#define WB_TIMER_SLOP_VALUE_LSB 0 +#define WB_TIMER_SLOP_VALUE_MASK 0x000003ff +#define WB_TIMER_SLOP_VALUE_GET(x) (((x)&WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB) +#define WB_TIMER_SLOP_VALUE_SET(x) (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK) + +#define BTCOEX_INT_EN_ADDRESS 0x00000264 +#define BTCOEX_INT_EN_OFFSET 0x00000264 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x) \ + (((x)&BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x) \ + (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x) (((x)&BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x) (((x)&BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_EN_ST_MESG_RECV_MSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_LSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x) (((x)&BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB) +#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x) (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) +#define BTCOEX_INT_EN_WB_TIMER_MSB 7 +#define BTCOEX_INT_EN_WB_TIMER_LSB 7 +#define BTCOEX_INT_EN_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_EN_WB_TIMER_GET(x) (((x)&BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB) +#define BTCOEX_INT_EN_WB_TIMER_SET(x) (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK) +#define BTCOEX_INT_EN_NOSYNC_MSB 4 +#define BTCOEX_INT_EN_NOSYNC_LSB 4 +#define BTCOEX_INT_EN_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_EN_NOSYNC_GET(x) (((x)&BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB) +#define BTCOEX_INT_EN_NOSYNC_SET(x) (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK) +#define BTCOEX_INT_EN_SYNC_MSB 3 +#define BTCOEX_INT_EN_SYNC_LSB 3 +#define BTCOEX_INT_EN_SYNC_MASK 0x00000008 +#define BTCOEX_INT_EN_SYNC_GET(x) (((x)&BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB) +#define BTCOEX_INT_EN_SYNC_SET(x) (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK) +#define BTCOEX_INT_EN_END_MSB 2 +#define BTCOEX_INT_EN_END_LSB 2 +#define BTCOEX_INT_EN_END_MASK 0x00000004 +#define BTCOEX_INT_EN_END_GET(x) (((x)&BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB) +#define BTCOEX_INT_EN_END_SET(x) (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK) +#define BTCOEX_INT_EN_FRAME_CNT_MSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_LSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_EN_FRAME_CNT_GET(x) (((x)&BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB) +#define BTCOEX_INT_EN_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK) +#define BTCOEX_INT_EN_CLK_CNT_MSB 0 +#define BTCOEX_INT_EN_CLK_CNT_LSB 0 +#define BTCOEX_INT_EN_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_EN_CLK_CNT_GET(x) (((x)&BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB) +#define BTCOEX_INT_EN_CLK_CNT_SET(x) (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK) + +#define BTCOEX_INT_STAT_ADDRESS 0x00000268 +#define BTCOEX_INT_STAT_OFFSET 0x00000268 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) \ + (((x)&BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) \ + (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x) \ + (((x)&BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x) \ + (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x) \ + (((x)&BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x) \ + (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x) \ + (((x)&BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x) \ + (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) +#define BTCOEX_INT_STAT_WB_TIMER_MSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_LSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_STAT_WB_TIMER_GET(x) (((x)&BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB) +#define BTCOEX_INT_STAT_WB_TIMER_SET(x) (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK 0x00000040 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x) \ + (((x)&BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x) \ + (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_MSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_LSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_MASK 0x00000020 +#define BTCOEX_INT_STAT_BTPRIORITY_GET(x) (((x)&BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK) +#define BTCOEX_INT_STAT_NOSYNC_MSB 4 +#define BTCOEX_INT_STAT_NOSYNC_LSB 4 +#define BTCOEX_INT_STAT_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_STAT_NOSYNC_GET(x) (((x)&BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB) +#define BTCOEX_INT_STAT_NOSYNC_SET(x) (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK) +#define BTCOEX_INT_STAT_SYNC_MSB 3 +#define BTCOEX_INT_STAT_SYNC_LSB 3 +#define BTCOEX_INT_STAT_SYNC_MASK 0x00000008 +#define BTCOEX_INT_STAT_SYNC_GET(x) (((x)&BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB) +#define BTCOEX_INT_STAT_SYNC_SET(x) (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK) +#define BTCOEX_INT_STAT_END_MSB 2 +#define BTCOEX_INT_STAT_END_LSB 2 +#define BTCOEX_INT_STAT_END_MASK 0x00000004 +#define BTCOEX_INT_STAT_END_GET(x) (((x)&BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB) +#define BTCOEX_INT_STAT_END_SET(x) (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK) +#define BTCOEX_INT_STAT_FRAME_CNT_MSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_LSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_STAT_FRAME_CNT_GET(x) (((x)&BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB) +#define BTCOEX_INT_STAT_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK) +#define BTCOEX_INT_STAT_CLK_CNT_MSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_LSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_STAT_CLK_CNT_GET(x) (((x)&BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB) +#define BTCOEX_INT_STAT_CLK_CNT_SET(x) (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK) + +#define BTPRIORITY_INT_EN_ADDRESS 0x0000026c +#define BTPRIORITY_INT_EN_OFFSET 0x0000026c +#define BTPRIORITY_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_EN_BITMAP_GET(x) (((x)&BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB) +#define BTPRIORITY_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_INT_STAT_ADDRESS 0x00000270 +#define BTPRIORITY_INT_STAT_OFFSET 0x00000270 +#define BTPRIORITY_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_STAT_BITMAP_GET(x) (((x)&BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_EN_ADDRESS 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_OFFSET 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x) \ + (((x)&BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x) \ + (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_STAT_ADDRESS 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_OFFSET 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x) \ + (((x)&BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x) \ + (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) + +#define MAC_PCU_BMISS_TIMEOUT_ADDRESS 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_OFFSET 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x) \ + (((x)&MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x) \ + (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB 23 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB 0 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK 0x00ffffff +#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x) (((x)&MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) + +#define MAC_PCU_CAB_AWAKE_ADDRESS 0x00000280 +#define MAC_PCU_CAB_AWAKE_OFFSET 0x00000280 +#define MAC_PCU_CAB_AWAKE_ENABLE_MSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_LSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_MASK 0x00010000 +#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x) (((x)&MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB) +#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x) (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) +#define MAC_PCU_CAB_AWAKE_DURATION_MSB 15 +#define MAC_PCU_CAB_AWAKE_DURATION_LSB 0 +#define MAC_PCU_CAB_AWAKE_DURATION_MASK 0x0000ffff +#define MAC_PCU_CAB_AWAKE_DURATION_GET(x) (((x)&MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB) +#define MAC_PCU_CAB_AWAKE_DURATION_SET(x) (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK) + +#define LP_PERF_COUNTER_ADDRESS 0x00000284 +#define LP_PERF_COUNTER_OFFSET 0x00000284 +#define LP_PERF_COUNTER_EN_MSB 0 +#define LP_PERF_COUNTER_EN_LSB 0 +#define LP_PERF_COUNTER_EN_MASK 0x00000001 +#define LP_PERF_COUNTER_EN_GET(x) (((x)&LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB) +#define LP_PERF_COUNTER_EN_SET(x) (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK) + +#define LP_PERF_LIGHT_SLEEP_ADDRESS 0x00000288 +#define LP_PERF_LIGHT_SLEEP_OFFSET 0x00000288 +#define LP_PERF_LIGHT_SLEEP_CNT_MSB 31 +#define LP_PERF_LIGHT_SLEEP_CNT_LSB 0 +#define LP_PERF_LIGHT_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_LIGHT_SLEEP_CNT_GET(x) (((x)&LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB) +#define LP_PERF_LIGHT_SLEEP_CNT_SET(x) (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK) + +#define LP_PERF_DEEP_SLEEP_ADDRESS 0x0000028c +#define LP_PERF_DEEP_SLEEP_OFFSET 0x0000028c +#define LP_PERF_DEEP_SLEEP_CNT_MSB 31 +#define LP_PERF_DEEP_SLEEP_CNT_LSB 0 +#define LP_PERF_DEEP_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_DEEP_SLEEP_CNT_GET(x) (((x)&LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB) +#define LP_PERF_DEEP_SLEEP_CNT_SET(x) (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK) + +#define LP_PERF_ON_ADDRESS 0x00000290 +#define LP_PERF_ON_OFFSET 0x00000290 +#define LP_PERF_ON_CNT_MSB 31 +#define LP_PERF_ON_CNT_LSB 0 +#define LP_PERF_ON_CNT_MASK 0xffffffff +#define LP_PERF_ON_CNT_GET(x) (((x)&LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB) +#define LP_PERF_ON_CNT_SET(x) (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK) + +#define ST_64_BIT_ADDRESS 0x00000294 +#define ST_64_BIT_OFFSET 0x00000294 +#define ST_64_BIT_TIMEOUT_MSB 26 +#define ST_64_BIT_TIMEOUT_LSB 9 +#define ST_64_BIT_TIMEOUT_MASK 0x07fffe00 +#define ST_64_BIT_TIMEOUT_GET(x) (((x)&ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB) +#define ST_64_BIT_TIMEOUT_SET(x) (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK 0x00000100 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) \ + (((x)&ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) \ + (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) +#define ST_64_BIT_DRIVE_MODE_MSB 7 +#define ST_64_BIT_DRIVE_MODE_LSB 7 +#define ST_64_BIT_DRIVE_MODE_MASK 0x00000080 +#define ST_64_BIT_DRIVE_MODE_GET(x) (((x)&ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB) +#define ST_64_BIT_DRIVE_MODE_SET(x) (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK) +#define ST_64_BIT_CLOCK_GATE_MSB 6 +#define ST_64_BIT_CLOCK_GATE_LSB 6 +#define ST_64_BIT_CLOCK_GATE_MASK 0x00000040 +#define ST_64_BIT_CLOCK_GATE_GET(x) (((x)&ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB) +#define ST_64_BIT_CLOCK_GATE_SET(x) (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB 5 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB 1 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK 0x0000003e +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x) \ + (((x)&ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x) \ + (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) +#define ST_64_BIT_MODE_MSB 0 +#define ST_64_BIT_MODE_LSB 0 +#define ST_64_BIT_MODE_MASK 0x00000001 +#define ST_64_BIT_MODE_GET(x) (((x)&ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB) +#define ST_64_BIT_MODE_SET(x) (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK) + +#define MESSAGE_WR_ADDRESS 0x00000298 +#define MESSAGE_WR_OFFSET 0x00000298 +#define MESSAGE_WR_TYPE_MSB 31 +#define MESSAGE_WR_TYPE_LSB 0 +#define MESSAGE_WR_TYPE_MASK 0xffffffff +#define MESSAGE_WR_TYPE_GET(x) (((x)&MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB) +#define MESSAGE_WR_TYPE_SET(x) (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK) + +#define MESSAGE_WR_P_ADDRESS 0x0000029c +#define MESSAGE_WR_P_OFFSET 0x0000029c +#define MESSAGE_WR_P_PARAMETER_MSB 31 +#define MESSAGE_WR_P_PARAMETER_LSB 0 +#define MESSAGE_WR_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_WR_P_PARAMETER_GET(x) (((x)&MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB) +#define MESSAGE_WR_P_PARAMETER_SET(x) (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK) + +#define MESSAGE_RD_ADDRESS 0x000002a0 +#define MESSAGE_RD_OFFSET 0x000002a0 +#define MESSAGE_RD_TYPE_MSB 31 +#define MESSAGE_RD_TYPE_LSB 0 +#define MESSAGE_RD_TYPE_MASK 0xffffffff +#define MESSAGE_RD_TYPE_GET(x) (((x)&MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB) +#define MESSAGE_RD_TYPE_SET(x) (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK) + +#define MESSAGE_RD_P_ADDRESS 0x000002a4 +#define MESSAGE_RD_P_OFFSET 0x000002a4 +#define MESSAGE_RD_P_PARAMETER_MSB 31 +#define MESSAGE_RD_P_PARAMETER_LSB 0 +#define MESSAGE_RD_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_RD_P_PARAMETER_GET(x) (((x)&MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB) +#define MESSAGE_RD_P_PARAMETER_SET(x) (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK) + +#define CHIP_MODE_ADDRESS 0x000002a8 +#define CHIP_MODE_OFFSET 0x000002a8 +#define CHIP_MODE_BIT_MSB 1 +#define CHIP_MODE_BIT_LSB 0 +#define CHIP_MODE_BIT_MASK 0x00000003 +#define CHIP_MODE_BIT_GET(x) (((x)&CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB) +#define CHIP_MODE_BIT_SET(x) (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK) + +#define CLK_REQ_FALL_EDGE_ADDRESS 0x000002ac +#define CLK_REQ_FALL_EDGE_OFFSET 0x000002ac +#define CLK_REQ_FALL_EDGE_EN_MSB 31 +#define CLK_REQ_FALL_EDGE_EN_LSB 31 +#define CLK_REQ_FALL_EDGE_EN_MASK 0x80000000 +#define CLK_REQ_FALL_EDGE_EN_GET(x) (((x)&CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB) +#define CLK_REQ_FALL_EDGE_EN_SET(x) (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK) +#define CLK_REQ_FALL_EDGE_DELAY_MSB 7 +#define CLK_REQ_FALL_EDGE_DELAY_LSB 0 +#define CLK_REQ_FALL_EDGE_DELAY_MASK 0x000000ff +#define CLK_REQ_FALL_EDGE_DELAY_GET(x) (((x)&CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB) +#define CLK_REQ_FALL_EDGE_DELAY_SET(x) (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK) + +#define OTP_ADDRESS 0x000002b0 +#define OTP_OFFSET 0x000002b0 +#define OTP_LDO25_EN_MSB 1 +#define OTP_LDO25_EN_LSB 1 +#define OTP_LDO25_EN_MASK 0x00000002 +#define OTP_LDO25_EN_GET(x) (((x)&OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB) +#define OTP_LDO25_EN_SET(x) (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK) +#define OTP_VDD12_EN_MSB 0 +#define OTP_VDD12_EN_LSB 0 +#define OTP_VDD12_EN_MASK 0x00000001 +#define OTP_VDD12_EN_GET(x) (((x)&OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB) +#define OTP_VDD12_EN_SET(x) (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK) + +#define OTP_STATUS_ADDRESS 0x000002b4 +#define OTP_STATUS_OFFSET 0x000002b4 +#define OTP_STATUS_LDO25_EN_READY_MSB 1 +#define OTP_STATUS_LDO25_EN_READY_LSB 1 +#define OTP_STATUS_LDO25_EN_READY_MASK 0x00000002 +#define OTP_STATUS_LDO25_EN_READY_GET(x) (((x)&OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB) +#define OTP_STATUS_LDO25_EN_READY_SET(x) (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK) +#define OTP_STATUS_VDD12_EN_READY_MSB 0 +#define OTP_STATUS_VDD12_EN_READY_LSB 0 +#define OTP_STATUS_VDD12_EN_READY_MASK 0x00000001 +#define OTP_STATUS_VDD12_EN_READY_GET(x) (((x)&OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB) +#define OTP_STATUS_VDD12_EN_READY_SET(x) (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK) + +#define PMU_ADDRESS 0x000002b8 +#define PMU_OFFSET 0x000002b8 +#define PMU_REG_WAKEUP_TIME_SEL_MSB 1 +#define PMU_REG_WAKEUP_TIME_SEL_LSB 0 +#define PMU_REG_WAKEUP_TIME_SEL_MASK 0x00000003 +#define PMU_REG_WAKEUP_TIME_SEL_GET(x) (((x)&PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB) +#define PMU_REG_WAKEUP_TIME_SEL_SET(x) (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK) + +#define PMU_CONFIG_ADDRESS 0x000002c0 +#define PMU_CONFIG_OFFSET 0x000002c0 +#define PMU_CONFIG_VALUE_MSB 15 +#define PMU_CONFIG_VALUE_LSB 0 +#define PMU_CONFIG_VALUE_MASK 0x0000ffff +#define PMU_CONFIG_VALUE_GET(x) (((x)&PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB) +#define PMU_CONFIG_VALUE_SET(x) (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK) + +#define PMU_BYPASS_ADDRESS 0x000002c8 +#define PMU_BYPASS_OFFSET 0x000002c8 +#define PMU_BYPASS_SWREG_MSB 2 +#define PMU_BYPASS_SWREG_LSB 2 +#define PMU_BYPASS_SWREG_MASK 0x00000004 +#define PMU_BYPASS_SWREG_GET(x) (((x)&PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB) +#define PMU_BYPASS_SWREG_SET(x) (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK) +#define PMU_BYPASS_DREG_MSB 1 +#define PMU_BYPASS_DREG_LSB 1 +#define PMU_BYPASS_DREG_MASK 0x00000002 +#define PMU_BYPASS_DREG_GET(x) (((x)&PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB) +#define PMU_BYPASS_DREG_SET(x) (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK) +#define PMU_BYPASS_PAREG_MSB 0 +#define PMU_BYPASS_PAREG_LSB 0 +#define PMU_BYPASS_PAREG_MASK 0x00000001 +#define PMU_BYPASS_PAREG_GET(x) (((x)&PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB) +#define PMU_BYPASS_PAREG_SET(x) (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK) + +#define MAC_PCU_TSF2_L32_ADDRESS 0x000002cc +#define MAC_PCU_TSF2_L32_OFFSET 0x000002cc +#define MAC_PCU_TSF2_L32_VALUE_MSB 31 +#define MAC_PCU_TSF2_L32_VALUE_LSB 0 +#define MAC_PCU_TSF2_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_L32_VALUE_GET(x) (((x)&MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB) +#define MAC_PCU_TSF2_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK) + +#define MAC_PCU_TSF2_U32_ADDRESS 0x000002d0 +#define MAC_PCU_TSF2_U32_OFFSET 0x000002d0 +#define MAC_PCU_TSF2_U32_VALUE_MSB 31 +#define MAC_PCU_TSF2_U32_VALUE_LSB 0 +#define MAC_PCU_TSF2_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_U32_VALUE_GET(x) (((x)&MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB) +#define MAC_PCU_TSF2_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) \ + (((x)&MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) \ + (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB 19 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) \ + (((x)&MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) \ + (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) + +#define MAC_PCU_DIRECT_CONNECT_ADDRESS 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_OFFSET 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) \ + (((x)&MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) \ + (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) \ + (((x)&MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) \ + (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) \ + (((x)&MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) \ + (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) + +#define THERM_CTRL1_ADDRESS 0x000002dc +#define THERM_CTRL1_OFFSET 0x000002dc +#define THERM_CTRL1_BYPASS_MSB 16 +#define THERM_CTRL1_BYPASS_LSB 16 +#define THERM_CTRL1_BYPASS_MASK 0x00010000 +#define THERM_CTRL1_BYPASS_GET(x) (((x)&THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB) +#define THERM_CTRL1_BYPASS_SET(x) (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK) +#define THERM_CTRL1_WIDTH_ARBITOR_MSB 15 +#define THERM_CTRL1_WIDTH_ARBITOR_LSB 12 +#define THERM_CTRL1_WIDTH_ARBITOR_MASK 0x0000f000 +#define THERM_CTRL1_WIDTH_ARBITOR_GET(x) (((x)&THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB) +#define THERM_CTRL1_WIDTH_ARBITOR_SET(x) (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK) +#define THERM_CTRL1_WIDTH_MSB 11 +#define THERM_CTRL1_WIDTH_LSB 5 +#define THERM_CTRL1_WIDTH_MASK 0x00000fe0 +#define THERM_CTRL1_WIDTH_GET(x) (((x)&THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB) +#define THERM_CTRL1_WIDTH_SET(x) (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK) +#define THERM_CTRL1_TYPE_MSB 4 +#define THERM_CTRL1_TYPE_LSB 3 +#define THERM_CTRL1_TYPE_MASK 0x00000018 +#define THERM_CTRL1_TYPE_GET(x) (((x)&THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB) +#define THERM_CTRL1_TYPE_SET(x) (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK) +#define THERM_CTRL1_MEASURE_MSB 2 +#define THERM_CTRL1_MEASURE_LSB 2 +#define THERM_CTRL1_MEASURE_MASK 0x00000004 +#define THERM_CTRL1_MEASURE_GET(x) (((x)&THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB) +#define THERM_CTRL1_MEASURE_SET(x) (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK) +#define THERM_CTRL1_INT_EN_MSB 1 +#define THERM_CTRL1_INT_EN_LSB 1 +#define THERM_CTRL1_INT_EN_MASK 0x00000002 +#define THERM_CTRL1_INT_EN_GET(x) (((x)&THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB) +#define THERM_CTRL1_INT_EN_SET(x) (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK) +#define THERM_CTRL1_INT_STATUS_MSB 0 +#define THERM_CTRL1_INT_STATUS_LSB 0 +#define THERM_CTRL1_INT_STATUS_MASK 0x00000001 +#define THERM_CTRL1_INT_STATUS_GET(x) (((x)&THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB) +#define THERM_CTRL1_INT_STATUS_SET(x) (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK) + +#define THERM_CTRL2_ADDRESS 0x000002e0 +#define THERM_CTRL2_OFFSET 0x000002e0 +#define THERM_CTRL2_ADC_OFF_MSB 25 +#define THERM_CTRL2_ADC_OFF_LSB 25 +#define THERM_CTRL2_ADC_OFF_MASK 0x02000000 +#define THERM_CTRL2_ADC_OFF_GET(x) (((x)&THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB) +#define THERM_CTRL2_ADC_OFF_SET(x) (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK) +#define THERM_CTRL2_ADC_ON_MSB 24 +#define THERM_CTRL2_ADC_ON_LSB 24 +#define THERM_CTRL2_ADC_ON_MASK 0x01000000 +#define THERM_CTRL2_ADC_ON_GET(x) (((x)&THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB) +#define THERM_CTRL2_ADC_ON_SET(x) (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK) +#define THERM_CTRL2_SAMPLE_MSB 23 +#define THERM_CTRL2_SAMPLE_LSB 16 +#define THERM_CTRL2_SAMPLE_MASK 0x00ff0000 +#define THERM_CTRL2_SAMPLE_GET(x) (((x)&THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB) +#define THERM_CTRL2_SAMPLE_SET(x) (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK) +#define THERM_CTRL2_HIGH_MSB 15 +#define THERM_CTRL2_HIGH_LSB 8 +#define THERM_CTRL2_HIGH_MASK 0x0000ff00 +#define THERM_CTRL2_HIGH_GET(x) (((x)&THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB) +#define THERM_CTRL2_HIGH_SET(x) (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK) +#define THERM_CTRL2_LOW_MSB 7 +#define THERM_CTRL2_LOW_LSB 0 +#define THERM_CTRL2_LOW_MASK 0x000000ff +#define THERM_CTRL2_LOW_GET(x) (((x)&THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB) +#define THERM_CTRL2_LOW_SET(x) (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK) + +#define THERM_CTRL3_ADDRESS 0x000002e4 +#define THERM_CTRL3_OFFSET 0x000002e4 +#define THERM_CTRL3_ADC_GAIN_MSB 16 +#define THERM_CTRL3_ADC_GAIN_LSB 8 +#define THERM_CTRL3_ADC_GAIN_MASK 0x0001ff00 +#define THERM_CTRL3_ADC_GAIN_GET(x) (((x)&THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB) +#define THERM_CTRL3_ADC_GAIN_SET(x) (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK) +#define THERM_CTRL3_ADC_OFFSET_MSB 7 +#define THERM_CTRL3_ADC_OFFSET_LSB 0 +#define THERM_CTRL3_ADC_OFFSET_MASK 0x000000ff +#define THERM_CTRL3_ADC_OFFSET_GET(x) (((x)&THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB) +#define THERM_CTRL3_ADC_OFFSET_SET(x) (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK) + +#ifndef __ASSEMBLER__ + +typedef struct rtc_wlan_reg_reg_s +{ + volatile unsigned int wlan_reset_control; + volatile unsigned int wlan_xtal_control; + volatile unsigned int wlan_tcxo_detect; + volatile unsigned int wlan_xtal_test; + volatile unsigned int wlan_quadrature; + volatile unsigned int wlan_pll_control; + volatile unsigned int wlan_pll_settle; + volatile unsigned int wlan_xtal_settle; + volatile unsigned int wlan_cpu_clock; + volatile unsigned int wlan_clock_out; + volatile unsigned int wlan_clock_control; + volatile unsigned int wlan_bias_override; + volatile unsigned int wlan_wdt_control; + volatile unsigned int wlan_wdt_status; + volatile unsigned int wlan_wdt; + volatile unsigned int wlan_wdt_count; + volatile unsigned int wlan_wdt_reset; + volatile unsigned int wlan_int_status; + volatile unsigned int wlan_lf_timer0; + volatile unsigned int wlan_lf_timer_count0; + volatile unsigned int wlan_lf_timer_control0; + volatile unsigned int wlan_lf_timer_status0; + volatile unsigned int wlan_lf_timer1; + volatile unsigned int wlan_lf_timer_count1; + volatile unsigned int wlan_lf_timer_control1; + volatile unsigned int wlan_lf_timer_status1; + volatile unsigned int wlan_lf_timer2; + volatile unsigned int wlan_lf_timer_count2; + volatile unsigned int wlan_lf_timer_control2; + volatile unsigned int wlan_lf_timer_status2; + volatile unsigned int wlan_lf_timer3; + volatile unsigned int wlan_lf_timer_count3; + volatile unsigned int wlan_lf_timer_control3; + volatile unsigned int wlan_lf_timer_status3; + volatile unsigned int wlan_hf_timer; + volatile unsigned int wlan_hf_timer_count; + volatile unsigned int wlan_hf_lf_count; + volatile unsigned int wlan_hf_timer_control; + volatile unsigned int wlan_hf_timer_status; + volatile unsigned int wlan_rtc_control; + volatile unsigned int wlan_rtc_time; + volatile unsigned int wlan_rtc_date; + volatile unsigned int wlan_rtc_set_time; + volatile unsigned int wlan_rtc_set_date; + volatile unsigned int wlan_rtc_set_alarm; + volatile unsigned int wlan_rtc_config; + volatile unsigned int wlan_rtc_alarm_status; + volatile unsigned int wlan_uart_wakeup; + volatile unsigned int wlan_reset_cause; + volatile unsigned int wlan_system_sleep; + volatile unsigned int wlan_sdio_wrapper; + volatile unsigned int wlan_mac_sleep_control; + volatile unsigned int wlan_keep_awake; + volatile unsigned int wlan_lpo_cal_time; + volatile unsigned int wlan_lpo_init_dividend_int; + volatile unsigned int wlan_lpo_init_dividend_fraction; + volatile unsigned int wlan_lpo_cal; + volatile unsigned int wlan_lpo_cal_test_control; + volatile unsigned int wlan_lpo_cal_test_status; + volatile unsigned int wlan_chip_id; + volatile unsigned int wlan_derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int wlan_power_reg; + volatile unsigned int wlan_core_clk_ctrl; + volatile unsigned int wlan_gpio_wakeup_control; + volatile unsigned int ht; + volatile unsigned int mac_pcu_tsf_l32; + volatile unsigned int mac_pcu_tsf_u32; + volatile unsigned int mac_pcu_wbtimer; + unsigned char pad0[24]; /* pad to 0x140 */ + volatile unsigned int mac_pcu_generic_timers[16]; + volatile unsigned int mac_pcu_generic_timers_mode; + unsigned char pad1[60]; /* pad to 0x1c0 */ + volatile unsigned int mac_pcu_generic_timers2[16]; + volatile unsigned int mac_pcu_generic_timers_mode2; + volatile unsigned int mac_pcu_slp1; + volatile unsigned int mac_pcu_slp2; + volatile unsigned int mac_pcu_reset_tsf; + volatile unsigned int mac_pcu_tsf_add_pll; + volatile unsigned int sleep_retention; + volatile unsigned int btcoexctrl; + volatile unsigned int wbsync_priority1; + volatile unsigned int wbsync_priority2; + volatile unsigned int wbsync_priority3; + volatile unsigned int btcoex0; + volatile unsigned int btcoex1; + volatile unsigned int btcoex2; + volatile unsigned int btcoex3; + volatile unsigned int btcoex4; + volatile unsigned int btcoex5; + volatile unsigned int btcoex6; + volatile unsigned int lock; + volatile unsigned int nolock_priority; + volatile unsigned int wbsync; + volatile unsigned int wbsync1; + volatile unsigned int wbsync2; + volatile unsigned int wbsync3; + volatile unsigned int wb_timer_target; + volatile unsigned int wb_timer_slop; + volatile unsigned int btcoex_int_en; + volatile unsigned int btcoex_int_stat; + volatile unsigned int btpriority_int_en; + volatile unsigned int btpriority_int_stat; + volatile unsigned int btpriority_stomp_int_en; + volatile unsigned int btpriority_stomp_int_stat; + volatile unsigned int mac_pcu_bmiss_timeout; + volatile unsigned int mac_pcu_cab_awake; + volatile unsigned int lp_perf_counter; + volatile unsigned int lp_perf_light_sleep; + volatile unsigned int lp_perf_deep_sleep; + volatile unsigned int lp_perf_on; + volatile unsigned int st_64_bit; + volatile unsigned int message_wr; + volatile unsigned int message_wr_p; + volatile unsigned int message_rd; + volatile unsigned int message_rd_p; + volatile unsigned int chip_mode; + volatile unsigned int clk_req_fall_edge; + volatile unsigned int otp; + volatile unsigned int otp_status; + volatile unsigned int pmu; + unsigned char pad2[4]; /* pad to 0x2c0 */ + volatile unsigned int pmu_config[2]; + volatile unsigned int pmu_bypass; + volatile unsigned int mac_pcu_tsf2_l32; + volatile unsigned int mac_pcu_tsf2_u32; + volatile unsigned int mac_pcu_generic_timers_mode3; + volatile unsigned int mac_pcu_direct_connect; + volatile unsigned int therm_ctrl1; + volatile unsigned int therm_ctrl2; + volatile unsigned int therm_ctrl3; +} rtc_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_WLAN_REG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/athdefs.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/athdefs.h new file mode 100644 index 00000000000..dec4b513591 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/athdefs.h @@ -0,0 +1,108 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +#include +typedef uint32_t boolean; + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum +{ + A_RESOURCES = -5, /*TODO: fix later*/ + A_DEADLOCK = -4, /*TODO: fix later*/ + A_TIMEOUT = -3, /*TODO: fix later*/ + A_SOCK_INVALID = -2, + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results later (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED, /* Object was consumed */ + A_SOCKCXT_NOT_FOUND, /*Socket context not found*/ + A_UNKNOWN_CMD, /*Unknown socket ocmmand*/ + A_SOCK_UNAVAILABLE, /*Socket limit reached*/ + A_MEMFREE_ERROR /*Error while freeing resource*/ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +typedef enum +{ + USER, /* Max Perf set by user */ + WPS, /* Max Perf set by WPS */ + P2P, /* Max Perf set by P2P */ + SOFTAP, + SRCALL, + DHCP, + TCPL1, + TCPL2, + TKIP, + RAWMODE, + PWR_MAX = 32, +} A_PWR_MODULE; + +#define EXPECTED_REF_CLK_AR4100 26000000 +#define EXPECTED_REF_CLK_AR400X 40000000 + +#endif /* __ATHDEFS_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/bmi_msg.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/bmi_msg.h new file mode 100644 index 00000000000..c3def0cefd9 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/bmi_msg.h @@ -0,0 +1,271 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 +/* + * Semantics: Host is done using BMI + * Request format: + * uint32_t command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 +/* + * Semantics: Host reads AR6K memory + * Request format: + * uint32_t command (BMI_READ_MEMORY) + * uint32_t address + * uint32_t length, at most BMI_DATASZ_MAX + * Response format: + * uint8_t data[length] + */ + +#define BMI_WRITE_MEMORY 3 +/* + * Semantics: Host writes AR6K memory + * Request format: + * uint32_t command (BMI_WRITE_MEMORY) + * uint32_t address + * uint32_t length, at most BMI_DATASZ_MAX + * uint8_t data[length] + * Response format: none + */ + +#define BMI_EXECUTE 4 +/* + * Semantics: Causes AR6K to execute code + * Request format: + * uint32_t command (BMI_EXECUTE) + * uint32_t address + * uint32_t parameter + * Response format: + * uint32_t return value + */ + +#define BMI_SET_APP_START 5 +/* + * Semantics: Set Target application starting address + * Request format: + * uint32_t command (BMI_SET_APP_START) + * uint32_t address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 +/* + * Semantics: Read a 32-bit Target SOC register. + * Request format: + * uint32_t command (BMI_READ_REGISTER) + * uint32_t address + * Response format: + * uint32_t value + */ + +#define BMI_WRITE_SOC_REGISTER 7 +/* + * Semantics: Write a 32-bit Target SOC register. + * Request format: + * uint32_t command (BMI_WRITE_REGISTER) + * uint32_t address + * uint32_t value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 +/* + * Semantics: Fetch the 4-byte Target information + * Request format: + * uint32_t command (BMI_GET_TARGET_ID/INFO) + * Response format1 (old firmware): + * uint32_t TargetVersionID + * Response format2 (newer firmware): + * uint32_t TARGET_VERSION_SENTINAL + * struct bmi_target_info; + */ + +struct bmi_target_info +{ + uint32_t target_info_byte_count; /* size of this structure */ + uint32_t target_ver; /* Target Version ID */ + uint32_t target_type; /* Target type */ +}; + +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_AR4100 3 +#define TARGET_TYPE_AR400X 6 + +#if ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 +#define TARGET_TYPE TARGET_TYPE_AR4100 +#elif ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1 +#define TARGET_TYPE TARGET_TYPE_AR400X +#endif + +#define BMI_ROMPATCH_INSTALL 9 +/* + * Semantics: Install a ROM Patch. + * Request format: + * uint32_t command (BMI_ROMPATCH_INSTALL) + * uint32_t Target ROM Address + * uint32_t Target RAM Address or Value (depending on Target Type) + * uint32_t Size, in bytes + * uint32_t Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * uint32_t PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 +/* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * uint32_t command (BMI_ROMPATCH_UNINSTALL) + * uint32_t PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 +/* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * uint32_t command (BMI_ROMPATCH_ACTIVATE) + * uint32_t rompatch_count + * uint32_t PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 +/* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * uint32_t command (BMI_ROMPATCH_DEACTIVATE) + * uint32_t rompatch_count + * uint32_t PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_LZ_STREAM_START 13 +/* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * uint32_t command (BMI_LZ_STREAM_START) + * uint32_t address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 +/* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * uint32_t command (BMI_LZ_DATA) + * uint32_t length (of compressed data), + * at most BMI_DATASZ_MAX + * uint8_t CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_NVRAM_PROCESS 15 +#define BMI_NVRAM_SEG_NAME_SZ 16 +/* + * Semantics: Cause Target to search NVRAM (if any) for a + * segment with the specified name and process it according + * to NVRAM metadata. + * Request format: + * uint32_t command (BMI_NVRAM_PROCESS) + * uint8_t name[BMI_NVRAM_SEG_NAME_SZ] name (LE format) + * Response format: + * uint32_t 0, if nothing was executed; + * otherwise the value returned from the + * last NVRAM segment that was executed + */ + +#define BMI_SEGMENTED_WRITE_ADDR 0x1234 +/* + * Semantics: This is not a command but just the write memory address + * that should be used by hosted systems while downloading segmented + * firmware binary file to the target while target is in BMI mode. + * Target in BMI mode interprets stream and loads the various segments + * being downloaded onto appropriate target RAM locations. + * Request format: + * uint32_t command (BMI_WRITE_MEMORY) + * uint32_t address + * uint32_t length, at most BMI_DATASZ_MAX + * uint8_t data[length] + * Response format: none + */ +#endif /* __BMI_MSG_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/dbglog.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/dbglog.h new file mode 100644 index 00000000000..9daaf9ee3ba --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/dbglog.h @@ -0,0 +1,136 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_H_ +#define _DBGLOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DBGLOG_TIMESTAMP_OFFSET 0 +#define DBGLOG_TIMESTAMP_MASK \ + 0x0000FFFF /* Bit 0-15. Contains bit \ + 8-23 of the LF0 timer */ +#define DBGLOG_DBGID_OFFSET 16 +#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ +#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_MODULEID_OFFSET 26 +#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ +#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ + +/* + * Please ensure that the definition of any new module intrduced is captured + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The + * structure is required for the parser to correctly pick up the values for + * different modules. + */ +#define DBGLOG_MODULEID_START +#define DBGLOG_MODULEID_INF 0 +#define DBGLOG_MODULEID_WMI 1 +#define DBGLOG_MODULEID_MISC 2 +#define DBGLOG_MODULEID_PM 3 +#define DBGLOG_MODULEID_TXRX_MGMTBUF 4 +#define DBGLOG_MODULEID_TXRX_TXBUF 5 +#define DBGLOG_MODULEID_TXRX_RXBUF 6 +#define DBGLOG_MODULEID_WOW 7 +#define DBGLOG_MODULEID_WHAL 8 +#define DBGLOG_MODULEID_DC 9 +#define DBGLOG_MODULEID_CO 10 +#define DBGLOG_MODULEID_RO 11 +#define DBGLOG_MODULEID_CM 12 +#define DBGLOG_MODULEID_MGMT 13 +#define DBGLOG_MODULEID_TMR 14 +#define DBGLOG_MODULEID_BTCOEX 15 +#define DBGLOG_MODULEID_TLPM 2 +#define DBGLOG_MODULEID_END + +#define DBGLOG_NUM_ARGS_OFFSET 30 +#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ +#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ + +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 +#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF + +#define DBGLOG_REPORTING_ENABLED_OFFSET 16 +#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 + +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 + +#define DBGLOG_REPORT_SIZE_OFFSET 20 +#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 + +struct dbglog_buf_s +{ + struct dbglog_buf_s *next; + uint8_t *buffer; + uint32_t bufsize; + uint32_t length; + uint32_t count; + uint32_t free; +}; + +struct dbglog_hdr_s +{ + struct dbglog_buf_s *dbuf; + uint32_t dropped; +}; + +struct dbglog_config_s +{ + uint32_t cfgvalid; /* Mask with valid config bits */ + union + { + /* TODO: Take care of endianness */ + struct + { + uint32_t mmask : 16; /* Mask of modules with logging on */ + uint32_t rep : 1; /* Reporting enabled or not */ + uint32_t tsr : 3; /* Time stamp resolution. Def: 1 ms */ + uint32_t size : 10; /* Report size in number of messages */ + uint32_t reserved : 2; + } dbglog_config; + + uint32_t value; + } u; +}; + +#define cfgmmask u.dbglog_config.mmask +#define cfgrep u.dbglog_config.rep +#define cfgtsr u.dbglog_config.tsr +#define cfgsize u.dbglog_config.size +#define cfgvalue u.value + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/dbglog_id.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/dbglog_id.h new file mode 100644 index 00000000000..2c720b4387c --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/dbglog_id.h @@ -0,0 +1,562 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_ID_H_ +#define _DBGLOG_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION. + * Please ensure that the definition of any new debugid introduced is captured + * between the _DBGID_DEFINITION_START and + * _DBGID_DEFINITION_END defines. The structure is required for the + * parser to correctly pick up the values for different debug identifiers. + */ + +/* INF debug identifier definitions */ +#define INF_DBGID_DEFINITION_START +#define INF_ASSERTION_FAILED 1 +#define INF_TARGET_ID 2 +#define INF_DBGID_DEFINITION_END + +/* WMI debug identifier definitions */ +#define WMI_DBGID_DEFINITION_START +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1 +#define WMI_EXTENDED_CMD_NOT_HANDLED 2 +#define WMI_CMD_RX_PKT_TOO_SHORT 3 +#define WMI_CALLING_WMI_EXTENSION_FN 4 +#define WMI_CMD_NOT_HANDLED 5 +#define WMI_IN_SYNC 6 +#define WMI_TARGET_WMI_SYNC_CMD 7 +#define WMI_SET_SNR_THRESHOLD_PARAMS 8 +#define WMI_SET_RSSI_THRESHOLD_PARAMS 9 +#define WMI_SET_LQ_TRESHOLD_PARAMS 10 +#define WMI_TARGET_CREATE_PSTREAM_CMD 11 +#define WMI_WI_DTM_INUSE 12 +#define WMI_TARGET_DELETE_PSTREAM_CMD 13 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14 +#define WMI_TARGET_GET_BIT_RATE_CMD 15 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17 +#define WMI_TARGET_GET_TX_PWR_CMD 18 +#define WMI_FREE_EVBUF_WMIBUF 19 +#define WMI_FREE_EVBUF_DATABUF 20 +#define WMI_FREE_EVBUF_BADFLAG 21 +#define WMI_HTC_RX_ERROR_DATA_PACKET 22 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24 +#define WMI_SENDING_READY_EVENT 25 +#define WMI_SETPOWER_MDOE_TO_MAXPERF 26 +#define WMI_SETPOWER_MDOE_TO_REC 27 +#define WMI_BSSINFO_EVENT_FROM 28 +#define WMI_TARGET_GET_STATS_CMD 29 +#define WMI_SENDING_SCAN_COMPLETE_EVENT 30 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33 +#define WMI_SENDING_ERROR_REPORT_EVENT 34 +#define WMI_SENDING_CAC_EVENT 35 +#define WMI_TARGET_GET_ROAM_TABLE_CMD 36 +#define WMI_TARGET_GET_ROAM_DATA_CMD 37 +#define WMI_SENDING_GPIO_INTR_EVENT 38 +#define WMI_SENDING_GPIO_ACK_EVENT 39 +#define WMI_SENDING_GPIO_DATA_EVENT 40 +#define WMI_CMD_RX 41 +#define WMI_CMD_RX_XTND 42 +#define WMI_EVENT_SEND 43 +#define WMI_EVENT_SEND_XTND 44 +#define WMI_CMD_PARAMS_DUMP_START 45 +#define WMI_CMD_PARAMS_DUMP_END 46 +#define WMI_CMD_PARAMS 47 +#define WMI_DBGID_DEFINITION_END + +/* MISC debug identifier definitions */ +#define MISC_DBGID_DEFINITION_START +#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1 +#define MISC_DBGID_DEFINITION_END + +/* TXRX debug identifier definitions */ +#define TXRX_TXBUF_DBGID_DEFINITION_START +#define TXRX_TXBUF_ALLOCATE_BUF 1 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3 +#define TXRX_TXBUF_TXQ_DEPTH 4 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6 +#define TXRX_TXBUF_INITIALIZE_TIMER 7 +#define TXRX_TXBUF_ARM_TIMER 8 +#define TXRX_TXBUF_DISARM_TIMER 9 +#define TXRX_TXBUF_UNINITIALIZE_TIMER 10 +#define TXRX_TXBUF_DBGID_DEFINITION_END + +#define TXRX_RXBUF_DBGID_DEFINITION_START +#define TXRX_RXBUF_ALLOCATE_BUF 1 +#define TXRX_RXBUF_QUEUE_TO_HOST 2 +#define TXRX_RXBUF_QUEUE_TO_WLAN 3 +#define TXRX_RXBUF_ZERO_LEN_BUF 4 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9 +#define TXRX_RXBUF_REQUEUE_ERROR 10 +#define TXRX_RXBUF_DBGID_DEFINITION_END + +#define TXRX_MGMTBUF_DBGID_DEFINITION_START +#define TXRX_MGMTBUF_ALLOCATE_BUF 1 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3 +#define TXRX_MGMTBUF_GET_BUF 4 +#define TXRX_MGMTBUF_GET_SM_BUF 5 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6 +#define TXRX_MGMTBUF_REAPED_BUF 7 +#define TXRX_MGMTBUF_REAPED_SM_BUF 8 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10 +#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11 +#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12 +#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13 +#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15 +#define TXRX_MGMTBUF_DRAINQ 16 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17 +#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18 +#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19 +#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20 +#define TXRX_MGMTBUF_RESUME_HW_TXQ 21 +#define TXRX_MGMTBUF_TEAR_DOWN_BA 22 +#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23 +#define TXRX_MGMTBUF_PROCESS_DELBA 24 +#define TXRX_MGMTBUF_PERFORM_BA 25 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END + +/* PM (Power Module) debug identifier definitions */ +#define PM_DBGID_DEFINITION_START +#define PM_INIT 1 +#define PM_ENABLE 2 +#define PM_SET_STATE 3 +#define PM_SET_POWERMODE 4 +#define PM_CONN_NOTIFY 5 +#define PM_REF_COUNT_NEGATIVE 6 +#define PM_INFRA_STA_APSD_ENABLE 7 +#define PM_INFRA_STA_UPDATE_APSD_STATE 8 +#define PM_CHAN_OP_REQ 9 +#define PM_SET_MY_BEACON_POLICY 10 +#define PM_SET_ALL_BEACON_POLICY 11 +#define PM_INFRA_STA_SET_PM_PARAMS1 12 +#define PM_INFRA_STA_SET_PM_PARAMS2 13 +#define PM_ADHOC_SET_PM_CAPS_FAIL 14 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15 +#define PM_ADHOC_SET_PM_PARAMS 16 +#define PM_ADHOC_STATE1 18 +#define PM_ADHOC_STATE2 19 +#define PM_ADHOC_CONN_MAP 20 +#define PM_FAKE_SLEEP 21 +#define PM_AP_STATE1 22 +#define PM_AP_SET_PM_PARAMS 23 +#define PM_DBGID_DEFINITION_END + +/* Wake on Wireless debug identifier definitions */ +#define WOW_DBGID_DEFINITION_START +#define WOW_INIT 1 +#define WOW_GET_CONFIG_DSET 2 +#define WOW_NO_CONFIG_DSET 3 +#define WOW_INVALID_CONFIG_DSET 4 +#define WOW_USE_DEFAULT_CONFIG 5 +#define WOW_SETUP_GPIO 6 +#define WOW_INIT_DONE 7 +#define WOW_SET_GPIO_PIN 8 +#define WOW_CLEAR_GPIO_PIN 9 +#define WOW_SET_WOW_MODE_CMD 10 +#define WOW_SET_HOST_MODE_CMD 11 +#define WOW_ADD_WOW_PATTERN_CMD 12 +#define WOW_NEW_WOW_PATTERN_AT_INDEX 13 +#define WOW_DEL_WOW_PATTERN_CMD 14 +#define WOW_LIST_CONTAINS_PATTERNS 15 +#define WOW_GET_WOW_LIST_CMD 16 +#define WOW_INVALID_FILTER_ID 17 +#define WOW_INVALID_FILTER_LISTID 18 +#define WOW_NO_VALID_FILTER_AT_ID 19 +#define WOW_NO_VALID_LIST_AT_ID 20 +#define WOW_NUM_PATTERNS_EXCEEDED 21 +#define WOW_NUM_LISTS_EXCEEDED 22 +#define WOW_GET_WOW_STATS 23 +#define WOW_CLEAR_WOW_STATS 24 +#define WOW_WAKEUP_HOST 25 +#define WOW_EVENT_WAKEUP_HOST 26 +#define WOW_EVENT_DISCARD 27 +#define WOW_PATTERN_MATCH 28 +#define WOW_PATTERN_NOT_MATCH 29 +#define WOW_PATTERN_NOT_MATCH_OFFSET 30 +#define WOW_DISABLED_HOST_ASLEEP 31 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33 +#define WOW_DBGID_DEFINITION_END + +/* WHAL debug identifier definitions */ +#define WHAL_DBGID_DEFINITION_START +#define WHAL_ERROR_ANI_CONTROL 1 +#define WHAL_ERROR_CHIP_TEST1 2 +#define WHAL_ERROR_CHIP_TEST2 3 +#define WHAL_ERROR_EEPROM_CHECKSUM 4 +#define WHAL_ERROR_EEPROM_MACADDR 5 +#define WHAL_ERROR_INTERRUPT_HIU 6 +#define WHAL_ERROR_KEYCACHE_RESET 7 +#define WHAL_ERROR_KEYCACHE_SET 8 +#define WHAL_ERROR_KEYCACHE_TYPE 9 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11 +#define WHAL_ERROR_PHY_INVALID_CHANNEL 12 +#define WHAL_ERROR_POWER_AWAKE 13 +#define WHAL_ERROR_POWER_SET 14 +#define WHAL_ERROR_RECV_STOPDMA 15 +#define WHAL_ERROR_RECV_STOPPCU 16 +#define WHAL_ERROR_RESET_CHANNF1 17 +#define WHAL_ERROR_RESET_CHANNF2 18 +#define WHAL_ERROR_RESET_PM 19 +#define WHAL_ERROR_RESET_OFFSETCAL 20 +#define WHAL_ERROR_RESET_RFGRANT 21 +#define WHAL_ERROR_RESET_RXFRAME 22 +#define WHAL_ERROR_RESET_STOPDMA 23 +#define WHAL_ERROR_RESET_RECOVER 24 +#define WHAL_ERROR_XMIT_COMPUTE 25 +#define WHAL_ERROR_XMIT_NOQUEUE 26 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27 +#define WHAL_ERROR_XMIT_BADTYPE 28 +#define WHAL_ERROR_XMIT_STOPDMA 29 +#define WHAL_ERROR_INTERRUPT_BB_PANIC 30 +#define WHAL_ERROR_RESET_TXIQCAL 31 +#define WHAL_ERROR_PAPRD_MAXGAIN_ABOVE_WINDOW 32 +#define WHAL_DBGID_DEFINITION_END + +/* DC debug identifier definitions */ +#define DC_DBGID_DEFINITION_START +#define DC_SCAN_CHAN_START 1 +#define DC_SCAN_CHAN_FINISH 2 +#define DC_BEACON_RECEIVE7 3 +#define DC_SSID_PROBE_CB 4 +#define DC_SEND_NEXT_SSID_PROBE 5 +#define DC_START_SEARCH 6 +#define DC_CANCEL_SEARCH_CB 7 +#define DC_STOP_SEARCH 8 +#define DC_END_SEARCH 9 +#define DC_MIN_CHDWELL_TIMEOUT 10 +#define DC_START_SEARCH_CANCELED 11 +#define DC_SET_POWER_MODE 12 +#define DC_INIT 13 +#define DC_SEARCH_OPPORTUNITY 14 +#define DC_RECEIVED_ANY_BEACON 15 +#define DC_RECEIVED_MY_BEACON 16 +#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17 +#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18 +#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19 +#define DC_SET_BEACON_UPDATE 20 +#define DC_BEACON_UPDATE_COMPLETE 21 +#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22 +#define DC_BSSINFO_EVENT_DROPPED 23 +#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24 +#define DC_DBGID_DEFINITION_END + +/* CO debug identifier definitions */ +#define CO_DBGID_DEFINITION_START +#define CO_INIT 1 +#define CO_ACQUIRE_LOCK 2 +#define CO_START_OP1 3 +#define CO_START_OP2 4 +#define CO_DRAIN_TX_COMPLETE_CB 5 +#define CO_CHANGE_CHANNEL_CB 6 +#define CO_RETURN_TO_HOME_CHANNEL 7 +#define CO_FINISH_OP_TIMEOUT 8 +#define CO_OP_END 9 +#define CO_CANCEL_OP 10 +#define CO_CHANGE_CHANNEL 11 +#define CO_RELEASE_LOCK 12 +#define CO_CHANGE_STATE 13 +#define CO_DBGID_DEFINITION_END + +/* RO debug identifier definitions */ +#define RO_DBGID_DEFINITION_START +#define RO_REFRESH_ROAM_TABLE 1 +#define RO_UPDATE_ROAM_CANDIDATE 2 +#define RO_UPDATE_ROAM_CANDIDATE_CB 3 +#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4 +#define RO_REFRESH_ROAM_TABLE_DONE 5 +#define RO_PERIODIC_SEARCH_CB 6 +#define RO_PERIODIC_SEARCH_TIMEOUT 7 +#define RO_INIT 8 +#define RO_BMISS_STATE1 9 +#define RO_BMISS_STATE2 10 +#define RO_SET_PERIODIC_SEARCH_ENABLE 11 +#define RO_SET_PERIODIC_SEARCH_DISABLE 12 +#define RO_ENABLE_SQ_THRESHOLD 13 +#define RO_DISABLE_SQ_THRESHOLD 14 +#define RO_ADD_BSS_TO_ROAM_TABLE 15 +#define RO_SET_PERIODIC_SEARCH_MODE 16 +#define RO_CONFIGURE_SQ_THRESHOLD1 17 +#define RO_CONFIGURE_SQ_THRESHOLD2 18 +#define RO_CONFIGURE_SQ_PARAMS 19 +#define RO_LOW_SIGNAL_QUALITY_EVENT 20 +#define RO_HIGH_SIGNAL_QUALITY_EVENT 21 +#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22 +#define RO_UPDATE_CONNECTION_STATE_METRIC 23 +#define RO_DBGID_DEFINITION_END + +/* CM debug identifier definitions */ +#define CM_DBGID_DEFINITION_START +#define CM_INITIATE_HANDOFF 1 +#define CM_INITIATE_HANDOFF_CB 2 +#define CM_CONNECT_EVENT 3 +#define CM_DISCONNECT_EVENT 4 +#define CM_INIT 5 +#define CM_HANDOFF_SOURCE 6 +#define CM_SET_HANDOFF_TRIGGERS 7 +#define CM_CONNECT_REQUEST 8 +#define CM_CONNECT_REQUEST_CB 9 +#define CM_CONTINUE_SCAN_CB 10 +#define CM_DBGID_DEFINITION_END + +/* mgmt debug identifier definitions */ +#define MGMT_DBGID_DEFINITION_START +#define KEYMGMT_CONNECTION_INIT 1 +#define KEYMGMT_CONNECTION_COMPLETE 2 +#define KEYMGMT_CONNECTION_CLOSE 3 +#define KEYMGMT_ADD_KEY 4 +#define MLME_NEW_STATE 5 +#define MLME_CONN_INIT 6 +#define MLME_CONN_COMPLETE 7 +#define MLME_CONN_CLOSE 8 +#define MGMT_DBGID_DEFINITION_END + +/* TMR debug identifier definitions */ +#define TMR_DBGID_DEFINITION_START +#define TMR_HANG_DETECTED 1 +#define TMR_WDT_TRIGGERED 2 +#define TMR_WDT_RESET 3 +#define TMR_HANDLER_ENTRY 4 +#define TMR_HANDLER_EXIT 5 +#define TMR_SAVED_START 6 +#define TMR_SAVED_END 7 +#define TMR_DBGID_DEFINITION_END + +/* BTCOEX debug identifier definitions */ +#define BTCOEX_DBGID_DEFINITION_START +#define BTCOEX_STATUS_CMD 1 +#define BTCOEX_PARAMS_CMD 2 +#define BTCOEX_ANT_CONFIG 3 +#define BTCOEX_COLOCATED_BT_DEVICE 4 +#define BTCOEX_CLOSE_RANGE_SCO_ON 5 +#define BTCOEX_CLOSE_RANGE_SCO_OFF 6 +#define BTCOEX_CLOSE_RANGE_A2DP_ON 7 +#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8 +#define BTCOEX_A2DP_PROTECT_ON 9 +#define BTCOEX_A2DP_PROTECT_OFF 10 +#define BTCOEX_SCO_PROTECT_ON 11 +#define BTCOEX_SCO_PROTECT_OFF 12 +#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13 +#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14 +#define BTCOEX_CLOSE_RANGE_TOGGLE 15 +#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16 +#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17 +#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18 +#define BTCOEX_PTA_PRI_INTR_HANDLER 19 +#define BTCOEX_PSPOLL_QUEUED 20 +#define BTCOEX_PSPOLL_COMPLETE 21 +#define BTCOEX_DBG_PM_AWAKE 22 +#define BTCOEX_DBG_PM_SLEEP 23 +#define BTCOEX_DBG_SCO_COEX_ON 24 +#define BTCOEX_SCO_DATARECEIVE 25 +#define BTCOEX_INTR_INIT 26 +#define BTCOEX_PTA_PRI_DIFF 27 +#define BTCOEX_TIM_NOTIFICATION 28 +#define BTCOEX_SCO_WAKEUP_ON_DATA 29 +#define BTCOEX_SCO_SLEEP 30 +#define BTCOEX_SET_WEIGHTS 31 +#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32 +#define BTCOEX_SCO_MEASURE_TIME_DIFF 33 +#define BTCOEX_SET_EOL_VAL 34 +#define BTCOEX_OPT_DETECT_HANDLER 35 +#define BTCOEX_SCO_TOGGLE_STATE 36 +#define BTCOEX_SCO_STOMP 37 +#define BTCOEX_NULL_COMP_CALLBACK 38 +#define BTCOEX_RX_INCOMING 39 +#define BTCOEX_RX_INCOMING_CTL 40 +#define BTCOEX_RX_INCOMING_MGMT 41 +#define BTCOEX_RX_INCOMING_DATA 42 +#define BTCOEX_RTS_RECEPTION 43 +#define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44 +#define BTCOEX_PM_FAKE_SLEEP 45 +#define BTCOEX_ACL_COEX_STATUS 46 +#define BTCOEX_ACL_COEX_DETECTION 47 +#define BTCOEX_A2DP_COEX_STATUS 48 +#define BTCOEX_SCO_STATUS 49 +#define BTCOEX_WAKEUP_ON_DATA 50 +#define BTCOEX_DATARECEIVE 51 +#define BTCOEX_GET_MAX_AGGR_SIZE 53 +#define BTCOEX_MAX_AGGR_AVAIL_TIME 54 +#define BTCOEX_DBG_WBTIMER_INTR 55 +#define BTCOEX_DBG_SCO_SYNC 57 +#define BTCOEX_UPLINK_QUEUED_RATE 59 +#define BTCOEX_DBG_UPLINK_ENABLE_EOL 60 +#define BTCOEX_UPLINK_FRAME_DURATION 61 +#define BTCOEX_UPLINK_SET_EOL 62 +#define BTCOEX_DBG_EOL_EXPIRED 63 +#define BTCOEX_DBG_DATA_COMPLETE 64 +#define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65 +#define BTCOEX_DBG_DATA_COMPLETE_TIME 66 +#define BTCOEX_DBG_A2DP_ROLE_IS_SLAVE 67 +#define BTCOEX_DBG_A2DP_ROLE_IS_MASTER 68 +#define BTCOEX_DBG_UPLINK_SEQ_NUM 69 +#define BTCOEX_UPLINK_AGGR_SEQ 70 +#define BTCOEX_DBG_TX_COMP_SEQ_NO 71 +#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72 +#define BTCOEX_DBG_ACL_TRAFFIC 73 +#define BTCOEX_CURR_AGGR_PROP 74 +#define BTCOEX_DBG_SCO_GET_PER_TIME_DIFF 75 +#define BTCOEX_PSPOLL_PROCESS 76 +#define BTCOEX_RETURN_FROM_MAC 77 +#define BTCOEX_FREED_REQUEUED_CNT 78 +#define BTCOEX_DBG_TOGGLE_LOW_RATES 79 +#define BTCOEX_MAC_GOES_TO_SLEEP 80 +#define BTCOEX_DBG_A2DP_NO_SYNC 81 +#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82 +#define BTCOEX_RETURN_FROM_MAC_AC 83 +#define BTCOEX_DBG_DTIM_RECV 84 +#define BTCOEX_IS_PRE_UPDATE 86 +#define BTCOEX_ENQUEUED_BIT_MAP 87 +#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88 +#define BTCOEX_UPLINK_DESC 89 +#define BTCOEX_SCO_GET_PER_FIRST_FRM_TIMESTAMP 90 +#define BTCOEX_DBG_RECV_ACK 94 +#define BTCOEX_DBG_ADDBA_INDICATION 95 +#define BTCOEX_TX_COMPLETE_EOL_FAILED 96 +#define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97 +#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98 +#define BTCOEX_DBG_A2DP_SYNC_INTR 99 +#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100 +#define BTCOEX_FORM_AGGR_CURR_AGGR 101 +#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102 +#define BTCOEX_DBG_BT_TRAFFIC 103 +#define BTCOEX_DBG_STOMP_BT_TRAFFIC 104 +#define BTCOEX_RECV_NULL 105 +#define BTCOEX_DBG_A2DP_MASTER_BT_END 106 +#define BTCOEX_DBG_A2DP_BT_START 107 +#define BTCOEX_DBG_A2DP_SLAVE_BT_END 108 +#define BTCOEX_DBG_A2DP_STOMP_BT 109 +#define BTCOEX_DBG_GO_TO_SLEEP 110 +#define BTCOEX_DBG_A2DP_PKT 111 +#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112 +#define BTCOEX_DBG_A2DP_NULL 113 +#define BTCOEX_DBG_UPLINK_DATA 114 +#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115 +#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116 +#define BTCOEX_DBG_TXQ_STATE 117 +#define BTCOEX_DBG_ALLOW_SCAN 118 +#define BTCOEX_DBG_SCAN_REQUEST 119 +#define BTCOEX_A2DP_SLEEP 127 +#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128 +#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129 +#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130 +#define BTCOEX_DATARECEIVE_AGGR 131 +#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132 +#define BTCOEX_DBG_DATARESP_TIMEOUT 133 +#define BTCOEX_BDG_BMISS 134 +#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135 +#define BTCOEX_DBG_SECOND_BMISS 136 +#define BTCOEX_DBG_SET_WLAN_STATE 138 +#define BTCOEX_BDG_FIRST_BMISS 139 +#define BTCOEX_DBG_A2DP_CHAN_OP 140 +#define BTCOEX_DBG_A2DP_INTR 141 +#define BTCOEX_DBG_BT_INQUIRY 142 +#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143 +#define BTCOEX_DBG_POST_INQUIRY_FINISH 144 +#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145 +#define BTCOEX_DBG_NULL_FRAME_SLEEP 146 +#define BTCOEX_DBG_NULL_FRAME_AWAKE 147 +#define BTCOEX_DBG_SET_AGGR_SIZE 152 +#define BTCOEX_DBG_TEAR_BA_TIMEOUT 153 +#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154 +#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155 +#define BTCOEX_DBG_COLOCATED_BT_DEV 156 +#define BTCOEX_DBG_FE_ANT_TYPE 157 +#define BTCOEX_DBG_BT_INQUIRY_CMD 158 +#define BTCOEX_DBG_SCO_CONFIG 159 +#define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160 +#define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161 +#define BTCOEX_DBG_A2DP_CONFIG 162 +#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163 +#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164 +#define BTCOEX_DBG_ACLCOEX_CONFIG 165 +#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166 +#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167 +#define BTCOEX_DBG_DEBUG_CMD 168 +#define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169 +#define BTCOEX_DBG_GET_CONFIG 170 +#define BTCOEX_DBG_GET_STATS 171 +#define BTCOEX_DBG_BT_OPERATING_STATUS 172 +#define BTCOEX_DBG_PERFORM_RECONNECT 173 +#define BTCOEX_DBG_ACL_WLAN_MED 175 +#define BTCOEX_DBG_ACL_BT_MED 176 +#define BTCOEX_DBG_WLAN_CONNECT 177 +#define BTCOEX_DBG_A2DP_DUAL_START 178 +#define BTCOEX_DBG_PMAWAKE_NOTIFY 179 +#define BTCOEX_DBG_BEACON_SCAN_ENABLE 180 +#define BTCOEX_DBG_BEACON_SCAN_DISABLE 181 +#define BTCOEX_DBG_RX_NOTIFY 182 +#define BTCOEX_SCO_GET_PER_SECOND_FRM_TIMESTAMP 183 +#define BTCOEX_DBG_TXQ_DETAILS 184 +#define BTCOEX_DBG_SCO_STOMP_LOW_PRI 185 +#define BTCOEX_DBG_A2DP_FORCE_SCAN 186 +#define BTCOEX_DBG_DTIM_STOMP_COMP 187 +#define BTCOEX_ACL_PRESENCE_TIMER 188 +#define BTCOEX_DBGID_DEFINITION_END + +#define TLPM_DBGID_DEFINITION_START +#define TLPM_INIT 1 +#define TLPM_FILTER_POWER_STATE 2 +#define TLPM_NOTIFY_NOT_IDLE 3 +#define TLPM_TIMEOUT_IDLE_HANDLER 4 +#define TLPM_TIMEOUT_WAKEUP_HANDLER 5 +#define TLPM_WAKEUP_SIGNAL_HANDLER 6 +#define TLPM_UNEXPECTED_GPIO_INTR_ERROR 7 +#define TLPM_BREAK_ON_NOT_RECEIVED_ERROR 8 +#define TLPM_BREAK_OFF_NOT_RECIVED_ERROR 9 +#define TLPM_ACK_GPIO_INTR 10 +#define TLPM_ON 11 +#define TLPM_OFF 12 +#define TLPM_WAKEUP_FROM_HOST 13 +#define TLPM_WAKEUP_FROM_BT 14 +#define TLPM_TX_BREAK_RECIVED 15 +#define TLPM_IDLE_TIMER_NOT_RUNNING 16 +#define TLPM_DBGID_DEFINITION_END + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_ID_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/htc.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/htc.h new file mode 100644 index 00000000000..7f95066e649 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/htc.h @@ -0,0 +1,241 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_H__ +#define __HTC_H__ + +#define A_OFFSETOF(type, field) (int)(&(((type *)0)->field)) + +#define ASSEMBLE_UNALIGNED_UINT16(p, highbyte, lowbyte) \ + (((uint16_t)(((uint8_t *)(p))[(highbyte)])) << 8 | (uint16_t)(((uint8_t *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p, type, field) \ + ASSEMBLE_UNALIGNED_UINT16(p, A_OFFSETOF(type, field) + 1, A_OFFSETOF(type, field)) + +#define A_SET_UINT16_FIELD(p, type, field, value) \ + \ +{ \ + ((uint8_t *)(p))[A_OFFSETOF(type, field)] = (uint8_t)(value); \ + ((uint8_t *)(p))[A_OFFSETOF(type, field) + 1] = (uint8_t)((value) >> 8); \ + \ +} + +#define A_GET_UINT8_FIELD(p, type, field) ((uint8_t *)(p))[A_OFFSETOF(type, field)] + +#define A_SET_UINT8_FIELD(p, type, field, value) ((uint8_t *)(p))[A_OFFSETOF(type, field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR +{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + uint8_t EndpointID FIELD_PACKED; + uint8_t Flags FIELD_PACKED; + uint16_t PayloadLen FIELD_PACKED; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + uint8_t ControlBytes[2] FIELD_PACKED; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ + +/* send direction */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */ +#define HTC_FLAGS_SEND_TRAILER (1 << 2) /* send trailer data */ + +/* receive direction */ +#define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */ +#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */ +#define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */ +#define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4 + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ + +#define HTC_MSG_READY_ID 1 +#define HTC_MSG_CONNECT_SERVICE_ID 2 +#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3 +#define HTC_MSG_SETUP_COMPLETE_ID 4 +#define HTC_MSG_SETUP_COMPLETE_EX_ID 5 + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct +{ + uint16_t MessageID FIELD_PACKED; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct +{ + uint16_t MessageID FIELD_PACKED; /* ID */ + uint16_t CreditCount FIELD_PACKED; /* number of credits the target can offer */ + uint16_t CreditSize FIELD_PACKED; /* size of each credit */ + uint8_t MaxEndpoints FIELD_PACKED; /* maximum number of endpoints the target has resources for */ + uint8_t _Pad1 FIELD_PACKED; +} POSTPACK HTC_READY_MSG; + +/* extended HTC ready message */ +typedef PREPACK struct +{ + HTC_READY_MSG Version2_0_Info FIELD_PACKED; /* legacy version 2.0 information at the front... */ + /* extended information */ + uint8_t HTCVersion FIELD_PACKED; + uint8_t MaxMsgsPerHTCBundle FIELD_PACKED; +} POSTPACK HTC_READY_EX_MSG; + +#define HTC_VERSION_2P0 0x00 +#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */ + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct +{ + uint16_t MessageID FIELD_PACKED; + uint16_t ServiceID FIELD_PACKED; /* service ID of the service to connect to */ + uint16_t ConnectionFlags FIELD_PACKED; /* connection flags */ + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE \ + (1 << 2) /* reduce credit dribbling when \ + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + uint8_t ServiceMetaLength; /* length of meta data that follows */ + uint8_t _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct +{ + uint16_t MessageID FIELD_PACKED; + uint16_t ServiceID FIELD_PACKED; /* service ID that the connection request was made */ + uint8_t Status FIELD_PACKED; /* service connection status */ + uint8_t EndpointID FIELD_PACKED; /* assigned endpoint ID */ + uint16_t MaxMsgSize FIELD_PACKED; /* maximum expected message size on this endpoint */ + uint8_t ServiceMetaLength FIELD_PACKED; /* length of meta data that follows */ + uint8_t _Pad1 FIELD_PACKED; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct +{ + uint16_t MessageID FIELD_PACKED; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + +/* extended setup completion message */ +typedef PREPACK struct +{ + uint16_t MessageID FIELD_PACKED; + uint32_t SetupFlags FIELD_PACKED; + uint8_t MaxMsgsPerBundledRecv FIELD_PACKED; + uint8_t Rsvd[3] FIELD_PACKED; +} POSTPACK HTC_SETUP_COMPLETE_EX_MSG; + +#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP \ + 4 /* specific service is not allowing any more \ + endpoints */ + +/* report record IDs */ + +#define HTC_RECORD_NULL 0 +#define HTC_RECORD_CREDITS 1 +#define HTC_RECORD_LOOKAHEAD 2 +#define HTC_RECORD_LOOKAHEAD_BUNDLE 3 + +typedef PREPACK struct +{ + uint8_t RecordID FIELD_PACKED; /* Record ID */ + uint8_t Length FIELD_PACKED; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct +{ + uint8_t EndpointID FIELD_PACKED; /* Endpoint that owns these credits */ + uint8_t Credits FIELD_PACKED; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct +{ + uint8_t PreValid FIELD_PACKED; /* pre valid guard */ + uint8_t LookAhead[4] FIELD_PACKED; /* 4 byte lookahead */ + uint8_t PostValid FIELD_PACKED; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +typedef PREPACK struct +{ + uint8_t LookAhead[4] FIELD_PACKED; /* 4 byte lookahead */ +} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT; + +#endif /* __HTC_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/htc_services.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/htc_services.h new file mode 100644 index 00000000000..a21e8347a46 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/htc_services.h @@ -0,0 +1,53 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum +{ + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +} HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group, index) (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP, 1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP, 0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP, 1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP, 2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP, 3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP, 4) +#define WMI_MAX_SERVICES 5 + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP, 0) + +#endif /*HTC_SERVICES_H_*/ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/p2p.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/p2p.h new file mode 100644 index 00000000000..3df01b7b919 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/p2p.h @@ -0,0 +1,470 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +/* + * This file has the shared declarations between the host & target P2P modules. + */ +#ifndef _P2P_H_ +#define _P2P_H_ + +#define WPS_NONCE_LEN 16 +#define WPS_DEV_TYPE_LEN 8 +#define WPS_AUTHENTICATOR_LEN 8 +#define WPS_HASH_LEN 32 +#define WPS_SECRET_NONCE_LEN 16 +#define WPS_KWA_LEN 8 +#define WPS_MAX_PIN_LEN 8 +#define P2P_MAX_SSID_LEN 32 + +#define WPS_DEV_OUI_WFA 0x0050f204 +#define P2P_IE_VENDOR_TYPE 0x506f9a09 + +#define WLAN_EID_VENDOR_SPECIFIC 221 + +#define P2P_DEV_CAPAB_SERVICE_DISCOVERY BIT(0) + +/* Config Methods */ +#define WPS_CONFIG_USBA 0x0001 +#define WPS_CONFIG_ETHERNET 0x0002 +#define WPS_CONFIG_LABEL 0x0004 +#define WPS_CONFIG_DISPLAY 0x0008 +#define WPS_CONFIG_EXT_NFC_TOKEN 0x0010 +#define WPS_CONFIG_INT_NFC_TOKEN 0x0020 +#define WPS_CONFIG_NFC_INTERFACE 0x0040 +#define WPS_CONFIG_PUSHBUTTON 0x0080 +#define WPS_CONFIG_KEYPAD 0x0100 + +/* Attribute Types */ +enum wps_attribute +{ + ATTR_AP_CHANNEL = 0x1001, + ATTR_ASSOC_STATE = 0x1002, + ATTR_AUTH_TYPE = 0x1003, + ATTR_AUTH_TYPE_FLAGS = 0x1004, + ATTR_AUTHENTICATOR = 0x1005, + ATTR_CONFIG_METHODS = 0x1008, + ATTR_CONFIG_ERROR = 0x1009, + ATTR_CONFIRM_URL4 = 0x100a, + ATTR_CONFIRM_URL6 = 0x100b, + ATTR_CONN_TYPE = 0x100c, + ATTR_CONN_TYPE_FLAGS = 0x100d, + ATTR_CRED = 0x100e, + ATTR_ENCR_TYPE = 0x100f, + ATTR_ENCR_TYPE_FLAGS = 0x1010, + ATTR_DEV_NAME = 0x1011, + ATTR_DEV_PASSWORD_ID = 0x1012, + ATTR_E_HASH1 = 0x1014, + ATTR_E_HASH2 = 0x1015, + ATTR_E_SNONCE1 = 0x1016, + ATTR_E_SNONCE2 = 0x1017, + ATTR_ENCR_SETTINGS = 0x1018, + ATTR_ENROLLEE_NONCE = 0x101a, + ATTR_FEATURE_ID = 0x101b, + ATTR_IDENTITY = 0x101c, + ATTR_IDENTITY_PROOF = 0x101d, + ATTR_KEY_WRAP_AUTH = 0x101e, + ATTR_KEY_ID = 0x101f, + ATTR_MAC_ADDR = 0x1020, + ATTR_MANUFACTURER = 0x1021, + ATTR_MSG_TYPE = 0x1022, + ATTR_MODEL_NAME = 0x1023, + ATTR_MODEL_NUMBER = 0x1024, + ATTR_NETWORK_INDEX = 0x1026, + ATTR_NETWORK_KEY = 0x1027, + ATTR_NETWORK_KEY_INDEX = 0x1028, + ATTR_NEW_DEVICE_NAME = 0x1029, + ATTR_NEW_PASSWORD = 0x102a, + ATTR_OOB_DEVICE_PASSWORD = 0x102c, + ATTR_OS_VERSION = 0x102d, + ATTR_POWER_LEVEL = 0x102f, + ATTR_PSK_CURRENT = 0x1030, + ATTR_PSK_MAX = 0x1031, + ATTR_PUBLIC_KEY = 0x1032, + ATTR_RADIO_ENABLE = 0x1033, + ATTR_REBOOT = 0x1034, + ATTR_REGISTRAR_CURRENT = 0x1035, + ATTR_REGISTRAR_ESTABLISHED = 0x1036, + ATTR_REGISTRAR_LIST = 0x1037, + ATTR_REGISTRAR_MAX = 0x1038, + ATTR_REGISTRAR_NONCE = 0x1039, + ATTR_REQUEST_TYPE = 0x103a, + ATTR_RESPONSE_TYPE = 0x103b, + ATTR_RF_BANDS = 0x103c, + ATTR_R_HASH1 = 0x103d, + ATTR_R_HASH2 = 0x103e, + ATTR_R_SNONCE1 = 0x103f, + ATTR_R_SNONCE2 = 0x1040, + ATTR_SELECTED_REGISTRAR = 0x1041, + ATTR_SERIAL_NUMBER = 0x1042, + ATTR_WPS_STATE = 0x1044, + ATTR_SSID = 0x1045, + ATTR_TOTAL_NETWORKS = 0x1046, + ATTR_UUID_E = 0x1047, + ATTR_UUID_R = 0x1048, + ATTR_VENDOR_EXT = 0x1049, + ATTR_VERSION = 0x104a, + ATTR_X509_CERT_REQ = 0x104b, + ATTR_X509_CERT = 0x104c, + ATTR_EAP_IDENTITY = 0x104d, + ATTR_MSG_COUNTER = 0x104e, + ATTR_PUBKEY_HASH = 0x104f, + ATTR_REKEY_KEY = 0x1050, + ATTR_KEY_LIFETIME = 0x1051, + ATTR_PERMITTED_CFG_METHODS = 0x1052, + ATTR_SELECTED_REGISTRAR_CONFIG_METHODS = 0x1053, + ATTR_PRIMARY_DEV_TYPE = 0x1054, + ATTR_SECONDARY_DEV_TYP_ELIST = 0x1055, + ATTR_PORTABLE_DEV = 0x1056, + ATTR_AP_SETUP_LOCKED = 0x1057, + ATTR_APPLICATION_EXT = 0x1058, + ATTR_EAP_TYPE = 0x1059, + ATTR_IV = 0x1060, + ATTR_KEY_PROVIDED_AUTO = 0x1061, + ATTR_802_1X_ENABLED = 0x1062, + ATTR_APPSESSIONKEY = 0x1063, + ATTR_WEPTRANSMITKEY = 0x1064, + ATTR_REQUESTED_DEV_TYPE = 0x106a +}; + +enum p2p_wps_method +{ + WPS_NOT_READY, + WPS_PIN_LABEL, + WPS_PIN_DISPLAY, + WPS_PIN_KEYPAD, + WPS_PBC +}; + +enum p2p_status_code +{ + P2P_SC_SUCCESS = 0, + P2P_SC_FAIL_INFO_CURRENTLY_UNAVAILABLE = 1, + P2P_SC_FAIL_INCOMPATIBLE_PARAMS = 2, + P2P_SC_FAIL_LIMIT_REACHED = 3, + P2P_SC_FAIL_INVALID_PARAMS = 4, + P2P_SC_FAIL_UNABLE_TO_ACCOMMODATE = 5, + P2P_SC_FAIL_PREV_PROTOCOL_ERROR = 6, + P2P_SC_FAIL_NO_COMMON_CHANNELS = 7, + P2P_SC_FAIL_UNKNOWN_GROUP = 8, + P2P_SC_FAIL_BOTH_GO_INTENT_15 = 9, + P2P_SC_FAIL_INCOMPATIBLE_PROV_METHOD = 10, + P2P_SC_FAIL_REJECTED_BY_USER = 11 +}; + +struct wps_parse_attr +{ + /* fixed length fields */ + const uint8_t *version; /* 1 octet */ + const uint8_t *msg_type; /* 1 octet */ + const uint8_t *enrollee_nonce; /* WPS_NONCE_LEN (16) octets */ + const uint8_t *registrar_nonce; /* WPS_NONCE_LEN (16) octets */ + const uint8_t *uuid_r; /* WPS_UUID_LEN (16) octets */ + const uint8_t *uuid_e; /* WPS_UUID_LEN (16) octets */ + const uint8_t *auth_type_flags; /* 2 octets */ + const uint8_t *encr_type_flags; /* 2 octets */ + const uint8_t *conn_type_flags; /* 1 octet */ + const uint8_t *config_methods; /* 2 octets */ + const uint8_t *sel_reg_config_methods; /* 2 octets */ + const uint8_t *primary_dev_type; /* 8 octets */ + const uint8_t *rf_bands; /* 1 octet */ + const uint8_t *assoc_state; /* 2 octets */ + const uint8_t *config_error; /* 2 octets */ + const uint8_t *dev_password_id; /* 2 octets */ + const uint8_t *oob_dev_password; /* WPS_OOB_DEVICE_PASSWORD_ATTR_LEN (54) + * octets */ + const uint8_t *os_version; /* 4 octets */ + const uint8_t *wps_state; /* 1 octet */ + const uint8_t *authenticator; /* WPS_AUTHENTICATOR_LEN (8) octets */ + const uint8_t *r_hash1; /* WPS_HASH_LEN (32) octets */ + const uint8_t *r_hash2; /* WPS_HASH_LEN (32) octets */ + const uint8_t *e_hash1; /* WPS_HASH_LEN (32) octets */ + const uint8_t *e_hash2; /* WPS_HASH_LEN (32) octets */ + const uint8_t *r_snonce1; /* WPS_SECRET_NONCE_LEN (16) octets */ + const uint8_t *r_snonce2; /* WPS_SECRET_NONCE_LEN (16) octets */ + const uint8_t *e_snonce1; /* WPS_SECRET_NONCE_LEN (16) octets */ + const uint8_t *e_snonce2; /* WPS_SECRET_NONCE_LEN (16) octets */ + const uint8_t *key_wrap_auth; /* WPS_KWA_LEN (8) octets */ + const uint8_t *auth_type; /* 2 octets */ + const uint8_t *encr_type; /* 2 octets */ + const uint8_t *network_idx; /* 1 octet */ + const uint8_t *network_key_idx; /* 1 octet */ + const uint8_t *mac_addr; /* ETH_ALEN (6) octets */ + const uint8_t *key_prov_auto; /* 1 octet (Bool) */ + const uint8_t *dot1x_enabled; /* 1 octet (Bool) */ + const uint8_t *selected_registrar; /* 1 octet (Bool) */ + const uint8_t *request_type; /* 1 octet */ + const uint8_t *response_type; /* 1 octet */ + const uint8_t *ap_setup_locked; /* 1 octet */ + + /* variable length fields */ + const uint8_t *manufacturer; + uint32_t manufacturer_len; + const uint8_t *model_name; + uint32_t model_name_len; + const uint8_t *model_number; + uint32_t model_number_len; + const uint8_t *serial_number; + uint32_t serial_number_len; + const uint8_t *dev_name; + uint32_t dev_name_len; + const uint8_t *public_key; + uint32_t public_key_len; + const uint8_t *encr_settings; + uint32_t encr_settings_len; + const uint8_t *ssid; /* <= 32 octets */ + uint32_t ssid_len; + const uint8_t *network_key; /* <= 64 octets */ + uint32_t network_key_len; + const uint8_t *eap_type; /* <= 8 octets */ + uint32_t eap_type_len; + const uint8_t *eap_identity; /* <= 64 octets */ + uint32_t eap_identity_len; + +/* attributes that can occur multiple times */ +#define MAX_CRED_COUNT 10 + const uint8_t *cred[MAX_CRED_COUNT]; + uint32_t cred_len[MAX_CRED_COUNT]; + uint32_t num_cred; + +#define MAX_REQ_DEV_TYPE_COUNT 10 + const uint8_t *req_dev_type[MAX_REQ_DEV_TYPE_COUNT]; + uint32_t num_req_dev_type; +}; + +#define P2P_WPS_PIN_LEN 9 +#define P2P_CHANNEL_LEN 3 +// char p2p_wps_pin_val[P2P_WPS_PIN_LEN]; + +enum p2p_sublem_id +{ + P2P_ATTR_STATUS = 0, + P2P_ATTR_MINOR_REASON_CODE = 1, + P2P_ATTR_CAPABILITY = 2, + P2P_ATTR_DEVICE_ID = 3, + P2P_ATTR_GROUP_OWNER_INTENT = 4, + P2P_ATTR_CONFIGURATION_TIMEOUT = 5, + P2P_ATTR_LISTEN_CHANNEL = 6, + P2P_ATTR_GROUP_BSSID = 7, + P2P_ATTR_EXT_LISTEN_TIMING = 8, + P2P_ATTR_INTENDED_INTERFACE_ADDR = 9, + P2P_ATTR_MANAGEABILITY = 10, + P2P_ATTR_CHANNEL_LIST = 11, + P2P_ATTR_NOTICE_OF_ABSENCE = 12, + P2P_ATTR_DEVICE_INFO = 13, + P2P_ATTR_GROUP_INFO = 14, + P2P_ATTR_GROUP_ID = 15, + P2P_ATTR_INTERFACE = 16, + P2P_ATTR_OPERATING_CHANNEL = 17, + P2P_ATTR_INVITATION_FLAGS = 18, + P2P_ATTR_VENDOR_SPECIFIC = 221 +}; + +#define P2P_MAX_REG_CLASSES 10 +#define P2P_MAX_REG_CLASS_CHANNELS 20 + +#define P2P_WILDCARD_SSID "DIRECT-" +#define P2P_WILDCARD_SSID_LEN 7 + +struct p2p_channels +{ + struct p2p_reg_class + { + uint8_t reg_class; + uint8_t channel[P2P_MAX_REG_CLASS_CHANNELS]; + uint8_t channels; + } reg_class[P2P_MAX_REG_CLASSES]; + uint8_t reg_classes; +}; + +#define P2P_NOA_DESCRIPTOR_LEN 13 +struct p2p_noa_descriptor +{ + uint8_t type_count; /* 255: continuous schedule, 0: reserved */ + uint32_t duration; /* Absent period duration in micro seconds */ + uint32_t interval; /* Absent period interval in micro seconds */ + uint32_t start_time; /* 32 bit tsf time when in starts */ +}; + +#define P2P_MAX_NOA_DESCRIPTORS 4 +/* + * Length = (2 octets for Index and CTWin/Opp PS) and + * (13 octets for each NOA Descriptors) + */ +#define P2P_NOA_IE_SIZE(num_desc) (2 + (13 * (num_desc))) + +#define P2P_NOE_IE_OPP_PS_SET (0x80) +#define P2P_NOE_IE_CTWIN_MASK (0x7F) + +struct p2p_sub_element_noa +{ + uint8_t p2p_sub_id; + uint8_t p2p_sub_len; + uint8_t index; /* identifies instance of NOA su element */ + uint8_t oppPS : 1, /* oppPS state of the AP */ + ctwindow : 7; /* ctwindow in TUs */ + uint8_t num_descriptors; /* number of NOA descriptors */ + struct p2p_noa_descriptor noa_descriptors[P2P_MAX_NOA_DESCRIPTORS]; +}; + +#define ETH_ALEN 6 + +struct p2p_ie +{ + uint8_t dialog_token; + const uint8_t *capability; + const uint8_t *go_intent; + const uint8_t *status; + const uint8_t *listen_channel; + const uint8_t *operating_channel; + const uint8_t *channel_list; + uint8_t channel_list_len; + const uint8_t *config_timeout; + const uint8_t *intended_addr; + const uint8_t *group_bssid; + const uint8_t *invitation_flags; + + const uint8_t *group_info; + uint32_t group_info_len; + const uint8_t *group_id; + uint32_t group_id_len; + + const uint8_t *device_id; + const uint8_t *manageability; + + const uint8_t *noa; + uint32_t noa_len; + const uint8_t *ext_listen_timing; + + const uint8_t *minor_reason_code; + + /* P2P Device Info */ + const uint8_t *p2p_device_info; + uint32_t p2p_device_info_len; + const uint8_t *p2p_device_addr; + const uint8_t *pri_dev_type; + uint8_t num_sec_dev_types; + char device_name[33]; + uint8_t dev_name_len; + uint16_t config_methods; + + /* WPS IE */ + uint16_t dev_password_id; + uint16_t wps_config_methods; + + /* SSID IE */ + const uint8_t *ssid; +}; + +struct p2p_device +{ + uint16_t listen_freq; + uint32_t wps_pbc; + char wps_pin[WPS_MAX_PIN_LEN]; + uint8_t pin_len; + uint32_t wps_method; + + uint8_t p2p_device_addr[ETH_ALEN]; + uint8_t pri_dev_type[8]; + char device_name[33]; + uint16_t config_methods; + uint8_t dev_capab; + uint8_t group_capab; + + uint8_t interface_addr[ETH_ALEN]; + + /* Dev. Discoverability data */ + uint8_t dev_disc_dialog_token; + uint8_t member_in_go_dev[ETH_ALEN]; + uint8_t member_in_go_iface[ETH_ALEN]; + uint8_t dev_disc_go_oper_ssid[WMI_MAX_SSID_LEN]; + uint8_t dev_disc_go_oper_ssid_len; + uint16_t dev_disc_go_oper_freq; + + uint32_t go_neg_req_sent; + + uint32_t go_state; + uint8_t dialog_token; + uint8_t intended_addr[ETH_ALEN]; + + struct p2p_channels channels; + uint16_t oper_freq; + uint8_t oper_ssid[P2P_MAX_SSID_LEN]; + uint8_t oper_ssid_len; + + uint16_t req_config_methods; + +#define P2P_DEV_PROBE_REQ_ONLY BIT(0) +#define P2P_DEV_REPORTED BIT(1) +#define P2P_DEV_NOT_YET_READY BIT(2) +#define P2P_DEV_SD_INFO BIT(3) +#define P2P_DEV_SD_SCHEDULE BIT(4) +#define P2P_DEV_PD_PEER_DISPLAY BIT(5) +#define P2P_DEV_PD_PEER_KEYPAD BIT(6) +#define P2P_DEV_USER_REJECTED BIT(7) +#define P2P_DEV_PEER_WAITING_RESPONSE BIT(8) +#define P2P_DEV_PREFER_PERSISTENT_GROUP BIT(9) +#define P2P_DEV_WAIT_GO_NEG_RESPONSE BIT(10) +#define P2P_DEV_WAIT_GO_NEG_CONFIRM BIT(11) +#define P2P_DEV_GROUP_CLIENT_ONLY BIT(12) +#define P2P_DEV_FORCE_FREQ BIT(13) + + uint32_t flags; + + uint32_t status; + uint8_t wait_count; + uint32_t invitation_reqs; + + uint16_t ext_listen_period; + uint16_t ext_listen_interval; + + uint8_t go_timeout; + uint8_t client_timeout; + uint8_t persistent_grp; +}; + +typedef PREPACK struct +{ + uint32_t wps_method; + uint16_t config_methods; + uint16_t oper_freq; + uint8_t pri_dev_type[8]; + uint8_t p2p_device_addr[ETH_ALEN]; + uint8_t interface_addr[ETH_ALEN]; + uint8_t dev_capab; + uint8_t group_capab; + uint8_t persistent_grp; + char device_name[33]; +} POSTPACK P2P_DEVICE_LITE; +#if 0 +struct p2p_default_profile { + char wps_pin[WPS_MAX_PIN_LEN]; + uint8_t pin_len; +#define P2P_WPS_PUSH (1 << 0) +#define P2P_WPS_PIN (1 << 1) +#define P2P_WPS_PIN_MY_PIN (1 << 2) + uint8_t default_wps_method; + uint32_t default_find_to; + uint8_t ssid_postfix[WMI_MAX_SSID_LEN-9]; + uint8_t ssid_postfix_len; + +} +#endif +// struct p2p_device p2p_persistent_device; +#endif /* _P2P_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/pkt_log.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/pkt_log.h new file mode 100644 index 00000000000..b5c17efad19 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/pkt_log.h @@ -0,0 +1,55 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __PKT_LOG_H__ +#define __PKT_LOG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* Pkt log info */ +typedef PREPACK struct pkt_log_t +{ + struct info_t + { + uint16_t st FIELD_PACKED; + uint16_t end FIELD_PACKED; + uint16_t cur FIELD_PACKED; + } info[4096] FIELD_PACKED; + uint16_t last_idx FIELD_PACKED; +} POSTPACK PACKET_LOG; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __PKT_LOG_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/pmu.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/pmu.h new file mode 100644 index 00000000000..9eb3e9bd29a --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/pmu.h @@ -0,0 +1,42 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _PMU_H_ +#define _PMU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define WAKE_MGR_WAKE_EVENT_TIMER 0X00000001 +#define WAKE_MGR_WAKE_EVENT_GPIO30_HIGH 0x00000002 +#define WAKE_MGR_WAKE_EVENT_GPIO30_LOW 0x00000004 +#define WAKE_MGR_WAKE_EVENT_GPIO31_HIGH 0x00000008 +#define WAKE_MGR_WAKE_EVENT_GPIO31_LOW 0x00000010 + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/targaddrs.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/targaddrs.h new file mode 100644 index 00000000000..cd2b60bc643 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/targaddrs.h @@ -0,0 +1,658 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __TARGADDRS_H__ +#define __TARGADDRS_H__ + +#include "bmi_msg.h" + +/* + * AR6K option bits, to enable/disable various features. + * By default, all option bits are 0. + * These bits can be set in LOCAL_SCRATCH register 0. + */ +#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ + +/* + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the + * host_interest structure. It must match the address of the _host_interest + * symbol (see linker script). + * + * Host Interest is shared between Host and Target in order to coordinate + * between the two, and is intended to remain constant (with additions only + * at the end) across software releases. + * + * All addresses are available here so that it's possible to + * write a single binary that works with all Target Types. + * May be used in assembler code as well as C. + */ + +#define AR4100_HOST_INTEREST_ADDRESS 0x00540600 +#define AR4002_HOST_INTEREST_ADDRESS 0x00428800 + +#if ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 +#define HOST_INTEREST ((uint32_t *)AR4100_HOST_INTEREST_ADDRESS) +#define HOST_INTEREST_MAX_SIZE 0x100 +#elif ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1 +#define HOST_INTEREST ((uint32_t *)AR4002_HOST_INTEREST_ADDRESS) +#define HOST_INTEREST_MAX_SIZE 0x200 +#endif + +#if !defined(__ASSEMBLER__) +struct register_dump_s; +struct dbglog_hdr_s; + +/* + * These are items that the Host may need to access + * via BMI or via the Diagnostic Window. The position + * of items in this structure must remain constant + * across firmware revisions! + * + * Types for each item must be fixed size across + * target and host platforms. + * + * More items may be added at the end. + */ +struct host_interest_s +{ + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + uint32_t hi_app_host_interest; /* 0x00 */ + + /* Pointer to register dump area, valid after Target crash. */ + uint32_t hi_failure_state; /* 0x04 */ + + /* Pointer to debug logging header */ + uint32_t hi_dbglog_hdr; /* 0x08 */ + + /* Indicates whether or not flash is present on Target. + * NB: flash_is_present indicator is here not just + * because it might be of interest to the Host; but + * also because it's set early on by Target's startup + * asm code and we need it to have a special RAM address + * so that it doesn't get reinitialized with the rest + * of data. + */ + uint32_t hi_flash_is_present; /* 0x0c */ + + /* + * General-purpose flag bits, similar to AR6000_OPTION_* flags. + * Can be used by application rather than by OS. + */ + uint32_t hi_option_flag; /* 0x10 */ + + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + uint32_t hi_serial_enable; /* 0x14 */ + + /* Start address of Flash DataSet index, if any */ + uint32_t hi_dset_list_head; /* 0x18 */ + + /* Override Target application start address */ + uint32_t hi_app_start; /* 0x1c */ + + /* Clock and voltage tuning */ + uint32_t hi_skip_clock_init; /* 0x20 */ + uint32_t hi_core_clock_setting; /* 0x24 */ + uint32_t hi_cpu_clock_setting; /* 0x28 */ + uint32_t hi_system_sleep_setting; /* 0x2c */ + uint32_t hi_xtal_control_setting; /* 0x30 */ + uint32_t hi_pll_ctrl_setting_24ghz; /* 0x34 */ + uint32_t hi_pll_ctrl_setting_5ghz; /* 0x38 */ + uint32_t hi_ref_voltage_trim_setting; /* 0x3c */ + uint32_t hi_clock_info; /* 0x40 */ + + /* + * Flash configuration overrides, used only + * when firmware is not executing from flash. + * (When using flash, modify the global variables + * with equivalent names.) + */ + uint32_t hi_bank0_addr_value; /* 0x44 */ + uint32_t hi_bank0_read_value; /* 0x48 */ + uint32_t hi_bank0_write_value; /* 0x4c */ + uint32_t hi_bank0_config_value; /* 0x50 */ + + /* Pointer to Board Data */ + uint32_t hi_board_data; /* 0x54 */ + + /* + * Indication of Board Data state: + * 0: board data is not yet initialized. + * 1: board data is initialized; unknown size + * >1: number of bytes of initialized board data (varies with board type) + */ + uint32_t hi_board_data_initialized; /* 0x58 */ + + uint32_t hi_dset_RAM_index_table; /* 0x5c */ + + uint32_t hi_desired_baud_rate; /* 0x60 */ + uint32_t hi_dbglog_config; /* 0x64 */ + uint32_t hi_end_RAM_reserve_sz; /* 0x68 */ + uint32_t hi_mbox_io_block_sz; /* 0x6c */ + + uint32_t hi_num_bpatch_streams; /* 0x70 -- unused */ + uint32_t hi_mbox_isr_yield_limit; /* 0x74 */ + + uint32_t hi_refclk_hz; /* 0x78 */ + uint32_t hi_ext_clk_detected; /* 0x7c */ + uint32_t hi_dbg_uart_txpin; /* 0x80 */ + uint32_t hi_dbg_uart_rxpin; /* 0x84 */ + uint32_t hi_hci_uart_baud; /* 0x88 */ + uint32_t hi_hci_uart_pin_assignments; /* 0x8C */ + /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ + uint32_t hi_hci_uart_baud_scale_val; /* 0x90 */ + uint32_t hi_hci_uart_baud_step_val; /* 0x94 */ + + uint32_t hi_allocram_start; /* 0x98 */ + uint32_t hi_allocram_sz; /* 0x9c */ + uint32_t hi_hci_bridge_flags; /* 0xa0 */ + uint32_t hi_hci_uart_support_pins; /* 0xa4 */ + /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ + uint32_t hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ + /* 0xa8 - [0]: 1 = enable, 0 = disable + * [1]: 0 = UART FC active low, 1 = UART FC active high + * 0xa9 - [7:0]: wakeup timeout in ms + * 0xaa, 0xab - [15:0]: idle timeout in ms + */ + /* Pointer to extended board Data */ + uint32_t hi_board_ext_data; /* 0xac */ + uint32_t hi_board_ext_data_config; /* 0xb0 */ + /* + * Bit [0] : valid + * Bit[31:16: size + */ + /* + * hi_reset_flag is used to do some stuff when target reset. + * such as restore app_start after warm reset or + * preserve host Interest area, or preserve ROM data, literals etc. + */ + uint32_t hi_reset_flag; /* 0xb4 */ + /* indicate hi_reset_flag is valid */ + uint32_t hi_reset_flag_valid; /* 0xb8 */ + uint32_t hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ + /* 0xbc - [31:0]: idle timeout in ms + */ + /* ACS flags */ + uint32_t hi_acs_flags; /* 0xc0 */ + uint32_t hi_console_flags; /* 0xc4 */ + uint32_t hi_nvram_state; /* 0xc8 */ + uint32_t hi_option_flag2; /* 0xcc */ + + /* If non-zero, override values sent to Host in WMI_READY event. */ + uint32_t hi_sw_version_override; /* 0xd0 */ + uint32_t hi_abi_version_override; /* 0xd4 */ + /* Percentage of high priority RX traffic to total expected RX traffic - + * applicable only to ar6004 */ + uint32_t hi_hp_rx_traffic_ratio; /* 0xd8 */ + + /* test applications flags */ + uint32_t hi_test_apps_related; /* 0xdc */ + /* location of test script */ + uint32_t hi_ota_testscript; /* 0xe0 */ + /* location of CAL data */ + uint32_t hi_cal_data; /* 0xe4 */ + + /* Number of packet log buffers */ + uint32_t hi_pktlog_num_buffers; /* 0xe8 */ + + /* wow extension configuration */ + uint32_t hi_wow_ext_config; /* 0xec */ + + uint32_t hi_pwr_save_flags; /* 0xf0 */ + + /* Spatial Multiplexing Power Save (SMPS) options */ + uint32_t hi_smps_options; /* 0xf4 */ + /* rx coalescing filter configuration */ + uint32_t hi_rx_coalesce_filter_config; /* 0xf8 */ + + uint32_t hi_bt_sharing_info; /* 0xfc */ + +#if (HOST_INTEREST_MAX_SIZE > 0x100) + + uint32_t hi_i2c_slv_cfg; /* 0x100 */ + + uint32_t hi_reserved_3; /* 0x104*/ + uint32_t hi_reserved_4; /* 0x108 */ + uint32_t hi_reserved_5; /* 0x10c */ + uint32_t hi_reserved_6; /* 0x110 */ + + /* RTOS-specific pointer-sized value */ + uint32_t hi_rtos; /* 0x114 */ + + /* Extending General purpose Flags */ + uint32_t hi_option_flag3; /* 0x118 */ +#endif /*HOST_INTEREST_MAX_SIZE*/ +}; + +/* bitmap for hi_test_apps_related */ +#define HI_TEST_APPS_TESTSCRIPT_LOADED 0x00000001 +#define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002 +#define HI_TEST_APPS_ENABLE_WHCK_LOG 0x00000004 + +/* Bits defined in hi_option_flag */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ +#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ +#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */ +#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */ +#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ +#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ +#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ +#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ +#define HI_OPTION_NUM_DEV_LSB 0x200 +#define HI_OPTION_NUM_DEV_MSB 0x800 +#define HI_OPTION_DEV_MODE_LSB 0x1000 +#define HI_OPTION_ATTUNNEL_MODE 0x2000 +#define HI_OPTION_DEV_MODE_MSB 0x8000000 +#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */ +#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */ +#define HI_OPTION_INIT_REG_SCAN \ + 0x40000000 /* Do regulatory scan during init before \ + * sending WMI ready event to host */ +#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */ + +#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 + +/* 2 bits of hi_option_flag are used to represent 3 modes */ +#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ +#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ +#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ +#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ + +/* 2 bits of hi_option flag are usedto represent 4 submodes */ +#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ +#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ +#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ +#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ + +/* Num dev Mask */ +#define HI_OPTION_NUM_DEV_MASK 0x7 +#define HI_OPTION_NUM_DEV_SHIFT 0x9 + +/* firmware bridging */ +#define HI_OPTION_FW_BRIDGE_SHIFT 0x04 + +/* Fw Mode/SubMode Mask +|-------------------------------------------------------------------------------| +| SUB | SUB | SUB | SUB | | | | | +| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] | +| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | +|-------------------------------------------------------------------------------| +*/ +#define HI_OPTION_FW_MODE_BITS 0x2 +#define HI_OPTION_FW_MODE_MASK 0x3 +#define HI_OPTION_FW_MODE_SHIFT 0xC +#define HI_OPTION_ALL_FW_MODE_MASK 0xFF + +#define HI_OPTION_FW_SUBMODE_BITS 0x2 +#define HI_OPTION_FW_SUBMODE_MASK 0x3 +#define HI_OPTION_FW_SUBMODE_SHIFT 0x14 +#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 +#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 + +/* hi_option_flag2 options */ +#define HI_OPTION_OFFLOAD_AMSDU 0x01 +#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ +#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/ +#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ +#define HI_OPTION_ENABLE_REALTIME_DEBUGGING 0x10 /* Enable realtime debugging */ +#define HI_OPTION_DISABLE_RTT 0x20 /* Disable RTT Feature */ +#define HI_OPTION_DISABLE_MAC_OTP 0x40 /* Disable MAC address overwrite via OTP Feature */ +#define HI_OPTION_USE_MBOX_CREDIT_REPORT 0x80 /* Enable MBOX Credit report mechanism */ +#define HI_OPTION_DISABLE_P2P_DEDICATE 0x100 /* Disable p2p dedicate device */ +#define HI_OPTION_INCREASE_TXBUF 0x200 /* Increase txbuf flag for host */ +#define HI_OPTION_AP_CLIENT_CNT 0x3c00 /* alternate number of clients in apmode */ +#define HI_OPTION_AP_DTIM_VAL 0x3c000 /* alternate dtim val in apmode */ +#define HI_OPTION_IOE_STA_OFFLOAD 0x40000 /* provision to enable station switching in apmode */ +#define HI_OPTION_EXT_FW_DOWNLOAD_DONE 0x80000 /* ext patch download finished after WMI ready*/ +#define HI_OPTION_ENABLE_NDIS_WAKE_WAR 0x100000 /* Enable NDIS wake WAR */ +#define HI_OPTION_ENABLE_LTE_COEX 0x200000 /* enable ltecoex hook up function in ROM */ +#define HI_OPTION_WOW_ACTIVE_LOW 0x400000 /* WoW in active low manner */ +#define HI_OPTION_BAM2BAM_MODE 0x800000 /* Enable BAM2BAM mode */ +#define HI_OPTION_ENABLE_PANASONIC_WAR 0x1000000 /* Enable Panasonic's WAR */ +#define HI_OPTION_ENABLE_ONE_SHOT_NOA 0x2000000 /* Enable one shot ona */ +#define HI_OPTION_ENABLE_SB_SPECIFIC 0x4000000 /* Enable customer specific function */ +#define HI_OPTION_WOW_SINGLE_CHAIN 0x8000000 /* Enable single chain in wow */ +#define HI_OPTION_ENABLE_WLAN_HB 0x10000000 /* Enable wlan hb function */ +#define HI_OPTION_ENABLE_SOFTAP_CH13 0x20000000 /* Enable Softap in Channel 13 */ +#define HI_OPTION_IGNORE_11D_BEACON 0x40000000 /* Ignore 11d beacon */ +#define HI_OPTION_MCC_ENABLE \ + 0x80000000 /* Disable Multichannel Concurrency (MCC) - used last bit to sync with mainline */ +#define HI_OPTION_RF_KILL_SHIFT 0x2 +#define HI_OPTION_RF_KILL_MASK 0x1 + +#define HI_OPTION_AP_CLIENT_CNT_SHIFT 0x0A +#define HI_OPTION_AP_DTIM_VAL_SHIFT 0x0E +#define HI_OPTION_IOE_STA_OFFLOAD_SHIFT 0x12 + +/* 4-bits(Bit 13 - Bit 10) to notify number of clients in apmode */ +#define HI_OPTION_AP_CLIENT_CNT_MASK 0x0F +/* 4-bits(Bit 17 - Bit 14)) use this 4 bit mask for dtim val in apmode*/ +#define HI_OPTION_AP_DTIM_VAL_MASK 0x0F +/* 1-bit(Bit 18)) use this 1 bit mask to enable sta-sta switching offload in apmode*/ +#define HI_OPTION_IOE_STA_OFFLOAD_MASK 0x01 + +/* hi_option_flag3 options */ +#define HI_OPTION_USE_OFFLOAD_P2P 0x01 +#define HI_OPTION_EN_HOST_PROXY_FW_DLOAD_MODE 0x02 /* Controls host proxy boot mode */ + +/* hi_reset_flag */ +#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */ +#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */ +#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */ +#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 +#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 +#define HI_RESET_FLAG_WARM_RESET 0x20 + +#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */ + +#define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */ +#define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */ +#define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */ +#define HI_ACS_FLAGS_ATTUNNEL_MODE (1 << 3) /* Use at tunnel mode */ +#define HI_ACS_FLAGS_RADIO_OFF (1 << 4) /* WWAN radio off */ +#define HI_ACS_FLAGS_USE_VAP (1 << 5) /* Use VAP as a client */ + +/* Bits defined in hi_customer_flags */ +#define HI_CE_FLAG_SPCIFIC_ENABLE 0x01 + +#define ON_RESET_FLAGS_VALID() (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID) + +#define RESET_FLAGS_VALIDATE() (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID) + +#define RESET_FLAGS_INVALIDATE() (HOST_INTEREST->hi_reset_flag_valid = 0) + +#define ON_RESET_PRESERVE_APP_START() (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START) + +#define ON_RESET_PRESERVE_NVRAM_STATE() (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE) + +#define ON_RESET_PRESERVE_HOST_INTEREST() (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST) + +#define ON_RESET_PRESERVE_ROMDATA() (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA) + +#define ON_RESET_PRESERVE_BOOT_INFO() (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO) + +#define ON_RESET_WARM_RESET() (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET) + +#define IS_ATTUNNEL_MODE_ENABLED() (HOST_INTEREST->hi_acs_flags & HI_ACS_FLAGS_ATTUNNEL_MODE) + +#define IS_WWAN_RADIO_OFF() (HOST_INTEREST->hi_acs_flags & HI_ACS_FLAGS_RADIO_OFF) + +/* CONSOLE FLAGS + * + * Bit Range Meaning + * --------- -------------------------------- + * 2..0 UART ID (0 = Default) + * 3 Baud Select (0 = 9600, 1 = 115200) + * 30..4 Reserved + * 31 Enable Console + * + * */ + +#define HI_CONSOLE_FLAGS_ENABLE (1 << 31) +#define HI_CONSOLE_FLAGS_UART_MASK (0x7) +#define HI_CONSOLE_FLAGS_UART_SHIFT 0 +#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3) + +/* SM power save options */ +#define HI_SMPS_ALLOW_MASK (0x00000001) +#define HI_SMPS_MODE_MASK (0x00000002) +#define HI_SMPS_MODE_STATIC (0x00000000) +#define HI_SMPS_MODE_DYNAMIC (0x00000002) +#define HI_SMPS_DISABLE_AUTO_MODE (0x00000004) +#define HI_SMPS_DATA_THRESH_MASK (0x000007f8) +#define HI_SMPS_DATA_THRESH_SHIFT (3) +#define HI_SMPS_RSSI_THRESH_MASK (0x0007f800) +#define HI_SMPS_RSSI_THRESH_SHIFT (11) +#define HI_SMPS_LOWPWR_CM_MASK (0x00380000) +#define HI_SMPS_LOWPWR_CM_SHIFT (15) +#define HI_SMPS_HIPWR_CM_MASK (0x03c00000) +#define HI_SMPS_HIPWR_CM_SHIFT (19) + +#define HOST_INTEREST_SMPS_GET_MODE() (HOST_INTEREST->hi_smps_options & HI_SMPS_MODE_MASK) +#define HOST_INTEREST_SMPS_GET_DATA_THRESH() \ + ((HOST_INTEREST->hi_smps_options & HI_SMPS_DATA_THRESH_MASK) >> HI_SMPS_DATA_THRESH_SHIFT) +#define HOST_INTEREST_SMPS_SET_DATA_THRESH(x) (((x) << HI_SMPS_DATA_THRESH_SHIFT) & HI_SMPS_DATA_THRESH_MASK) +#define HOST_INTEREST_SMPS_GET_RSSI_THRESH() \ + ((HOST_INTEREST->hi_smps_options & HI_SMPS_RSSI_THRESH_MASK) >> HI_SMPS_RSSI_THRESH_SHIFT) +#define HOST_INTEREST_SMPS_SET_RSSI_THRESH(x) (((x) << HI_SMPS_RSSI_THRESH_SHIFT) & HI_SMPS_RSSI_THRESH_MASK) +#define HOST_INTEREST_SMPS_SET_LOWPWR_CM() \ + ((HOST_INTEREST->hi_smps_options & HI_SMPS_LOWPWR_CM_MASK) >> HI_SMPS_LOWPWR_CM_SHIFT) +#define HOST_INTEREST_SMPS_SET_HIPWR_CM() \ + ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT) +#define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE) + +/* WOW Extension configuration + * + * Bit Range Meaning + * --------- -------------------------------- + * 8..0 Size of each WOW pattern (max 511) + * 15..9 Number of patterns per list (max 127) + * 17..16 Number of lists (max 4) + * 30..18 Reserved + * 31 Enabled + * + * set values (except enable) to zeros for default settings + * + * */ + +#define HI_WOW_EXT_ENABLED_MASK (1 << 31) +#define HI_WOW_EXT_NUM_LIST_SHIFT 16 +#define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT) +#define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9 +#define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT) +#define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0 +#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT) + +#define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) \ + ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \ + (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \ + (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK)) + +#define HI_WOW_EXT_GET_NUM_LISTS(config) (((config)&HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) +#define HI_WOW_EXT_GET_NUM_PATTERNS(config) (((config)&HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT) +#define HI_WOW_EXT_GET_PATTERN_SIZE(config) (((config)&HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT) + +/* RX Coalescing filter configuration + * + * Bit Range Meaning + * --------- -------------------------------- + * 7..0 Number of filters (0 = use default) + * 11..8 Number of tests per filter (0 = use default) + * 15..12 Buffer threshold multiplier (Rx filter threshold = RX buffers * multipler / divisor) + * 19..16 Buffer threshold divisor + * 23..20 RX idle recheck interval (in 25MS increments) + * 31 Enabled + * + * set values (except enable) to zeros for default settings + * + * */ + +#define HI_RX_COALESCE_FILTER_ENABLED_MASK (1 << 31) +#define HI_RX_COALESCE_FILTER_COUNT_SHIFT 0 +#define HI_RX_COALESCE_FILTER_COUNT_MASK (0xFF << HI_RX_COALESCE_FILTER_COUNT_SHIFT) +#define HI_RX_COALESCE_FILTER_TESTS_SHIFT 8 +#define HI_RX_COALESCE_FILTER_TESTS_MASK (0xF << HI_RX_COALESCE_FILTER_TESTS_SHIFT) +#define HI_RX_COALESCE_FILTER_BUF_MULT_SHIFT 12 +#define HI_RX_COALESCE_FILTER_BUF_MULT_MASK (0xF << HI_RX_COALESCE_FILTER_BUF_MULT_SHIFT) +#define HI_RX_COALESCE_FILTER_BUF_DIV_SHIFT 16 +#define HI_RX_COALESCE_FILTER_BUF_DIV_MASK (0xF << HI_RX_COALESCE_FILTER_BUF_DIV_SHIFT) +#define HI_RX_COALESCE_FILTER_REARM_INTVL_SHIFT 20 +#define HI_RX_COALESCE_FILTER_REARM_INTVL_MASK (0xF << HI_RX_COALESCE_FILTER_REARM_INTVL_SHIFT) + +#define HI_GET_RX_COALESCE_FILTER_COUNT(config) \ + (((config)&HI_RX_COALESCE_FILTER_COUNT_MASK) >> HI_RX_COALESCE_FILTER_COUNT_SHIFT) + +#define HI_GET_RX_COALESCE_FILTER_TESTS(config) \ + (((config)&HI_RX_COALESCE_FILTER_TESTS_MASK) >> HI_RX_COALESCE_FILTER_TESTS_SHIFT) + +#define HI_GET_RX_COALESCE_FILTER_BUF_MULTIPLIER(config) \ + (((config)&HI_RX_COALESCE_FILTER_BUF_MULT_MASK) >> HI_RX_COALESCE_FILTER_BUF_MULT_SHIFT) + +#define HI_GET_RX_COALESC_FILTER_BUF_DIVIDER(config) \ + (((config)&HI_RX_COALESCE_FILTER_BUF_DIV_MASK) >> HI_RX_COALESCE_FILTER_BUF_DIV_SHIFT) + +#define HI_GET_RX_COALESCE_FILTER_REARM_INTERVAL(config) \ + (((config)&HI_RX_COALESCE_FILTER_REARM_INTVL_MASK) >> HI_RX_COALESCE_FILTER_REARM_INTVL_SHIFT) + +#define HI_RX_COALESCE_FILTER_MAKE_CONFIG(nfilt, tpf, mult, div, rx_check) \ + \ +((((nfilt) << HI_RX_COALESCE_FILTER_COUNT_SHIFT) & HI_RX_COALESCE_FILTER_COUNT_MASK) | \ + (((tpf) << HI_RX_COALESCE_FILTER_TESTS_SHIFT) & HI_RX_COALESCE_FILTER_TESTS_MASK) | \ + (((mult) << HI_RX_COALESCE_FILTER_BUF_MULT_SHIFT) & HI_RX_COALESCE_FILTER_BUF_MULT_MASK) | \ + (((div) << HI_RX_COALESCE_FILTER_BUF_DIV_SHIFT) & HI_RX_COALESCE_FILTER_BUF_DIV_MASK) | \ + (((rx_check) << HI_RX_COALESCE_FILTER_REARM_INTVL_SHIFT) & HI_RX_COALESCE_FILTER_REARM_INTVL_MASK)\ +) + +/* input values for hi_i2c_slv_cfg */ +#define HI_SET_I2C_SLV_CFG(_sda, _sck) (((_sda) << 16) & 0xffff0000) | ((_sck)&0x0000ffff) +#define HI_GET_I2C_SLV_CFG_SDA() ((HOST_INTEREST->hi_i2c_slv_cfg >> 16) & 0x0000ffff) +#define HI_GET_I2C_SLV_CFG_SCK() ((HOST_INTEREST->hi_i2c_slv_cfg) & 0x0000ffff) + +/* + * Intended for use by Host software, this macro returns the Target RAM + * address of any item in the host_interest structure. + * Example: target_addr = AR4100_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); + */ +#define AR4100_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((uint32_t) & ((((struct host_interest_s *)(AR4100_HOST_INTEREST_ADDRESS))->item))) + +#define AR4002_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((uint32_t) & ((((struct host_interest_s *)(AR4002_HOST_INTEREST_ADDRESS))->item))) + +#define HOST_INTEREST_DBGLOG_IS_ENABLED() (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) + +#define HOST_INTEREST_PKTLOG_IS_ENABLED() ((HOST_INTEREST->hi_pktlog_num_buffers)) + +#define HOST_INTEREST_PROFILE_IS_ENABLED() (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) + +#define LF_TIMER_STABILIZATION_IS_ENABLED() (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL)) + +#define IS_AMSDU_OFFLAOD_ENABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU)) + +#define HOST_INTEREST_DFS_IS_ENABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT)) + +#define HOST_INTEREST_REALTIME_DEBUGGING_IS_ENABLED() \ + ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_REALTIME_DEBUGGING)) + +#define HOST_INTEREST_RTT_IS_DISABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_RTT)) + +#define HOST_INTEREST_MAC_OTP_IS_DISABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_MAC_OTP)) + +#define HOST_INTEREST_DISABLE_P2P_DEDICATE() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_P2P_DEDICATE)) + +#define HOST_INTEREST_INCREASE_TXBUF_IS_ENABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_INCREASE_TXBUF)) + +#define HOST_INTEREST_PANASONIC_WAR_ENABLE() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_PANASONIC_WAR)) + +#define HOST_INTEREST_ONE_SHOT_NOA_ENABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_ONE_SHOT_NOA)) + +#define HOST_INTEREST_SB_SPECIFIC_ENABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_SB_SPECIFIC)) + +#define HOST_INTEREST_EXT_FW_DOWNLOAD_DONE() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EXT_FW_DOWNLOAD_DONE)) +#define HOST_INTEREST_WOW_ACTIVE_IS_LOW() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_WOW_ACTIVE_LOW)) + +#define HOST_INTEREST_NDIS_WAKE_WAR_IS_ENABLEED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_NDIS_WAKE_WAR)) +#define HOST_INTEREST_LTECOEX_ENABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_LTE_COEX)) + +#define HOST_INTEREST_IS_BAM2BAM_MODE() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_BAM2BAM_MODE)) + +#define HOST_INTEREST_WLAN_HB_ENABLED() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_WLAN_HB)) + +#define HOST_INTEREST_MCC_ENABLE() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_MCC_ENABLE)) + +#define HOST_INTEREST_IGNORE_11D_BEACON() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_IGNORE_11D_BEACON)) + +#define HOST_INTEREST_ENABLE_SOFTAP_CH13() ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_ENABLE_SOFTAP_CH13)) + +#define HOST_INTEREST_OFFLOAD_P2P_IS_ENABLED() ((HOST_INTEREST->hi_option_flag3 & HI_OPTION_USE_OFFLOAD_P2P)) + +/*power save flag bit definitions*/ +#define HI_PWR_SAVE_LPL_ENABLED 0x1 +/*b1-b3 reserved*/ +/*b4-b5 : dev0 LPL type : 0 - none + 1- Reduce Pwr Search + 2- Reduce Pwr Listen*/ +/*b6-b7 : dev1 LPL type and so on for Max 8 devices*/ +#define HI_PWR_SAVE_LPL_DEV0_LSB 4 +#define HI_PWR_SAVE_LPL_DEV_MASK 0x3 +/*power save related utility macros*/ +#define HI_LPL_ENABLED() ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) +#define HI_DEV_LPL_TYPE_GET(_devix) \ + (HOST_INTEREST->hi_pwr_save_flags & ((HI_PWR_SAVE_LPL_DEV_MASK) << (HI_PWR_SAVE_LPL_DEV0_LSB + (_devix)*2))) + +#define HOST_INTEREST_SMPS_IS_ALLOWED() ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) + +/* Convert a Target virtual address into a Target physical address */ + +#define AR4100_VTOP(vaddr) ((vaddr)&0x001fffff) +#define AR4002_VTOP(vaddr) (vaddr) + +#if ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 +#define EXPECTED_MAX_WRITE_BUFFER_SPACE 3163 +#define TARG_VTOP(vaddr) AR4100_VTOP(vaddr) +#define HOST_INTEREST_ITEM_ADDRESS(item) AR4100_HOST_INTEREST_ITEM_ADDRESS(item) +#elif ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1 +#define EXPECTED_MAX_WRITE_BUFFER_SPACE 3163 // FIXME: confirm this value +#define TARG_VTOP(vaddr) AR4002_VTOP(vaddr) +#define HOST_INTEREST_ITEM_ADDRESS(item) AR4002_HOST_INTEREST_ITEM_ADDRESS(item) +#define AR400X_BOARD_DATA_ADDRESS 0x46B800 +#define AR400X_BOARD_DATA_SIZE 6144 +#define AR400X_EXT_BOARD_DATA_SIZE 0 +#define AR400X_RAM_RESERVE_SIZE 18432 +#else +#error Must have defined value for ATH_FIRMWARE_TARGET +#endif + +/* # of uint32_t entries in targregs, used by DIAG_FETCH_TARG_REGS */ +#define AR4100_FETCH_TARG_REGS_COUNT 64 + +#define AR4100_CONFIGFOUND_ADDR 0x540720 +#define AR4100_CONFIGFOUND_VAL 0 +#define AR4100_CONFIGFOUND_STK_ADDR 0x544239 +#define AR4100_NVRAM_SAMPLE_VAL 0x1e0104 +#define AR4100_NVRAM_SAMPLE_ADDR 0x54070c + +/* hi_flash_is_present value definition */ + +#define HOST_PROXY_INIT 0x01 +#define HOST_PROXY_NORMAL_BOOT 0x02 +#define HOST_PROXY_BMI_BOOT 0x03 +#define HOST_PROXY_BOOTCTL_MASK 0x03 + +#endif /* !__ASSEMBLER__ */ + +#endif /* __TARGADDRS_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/wlan_defs.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/wlan_defs.h new file mode 100644 index 00000000000..bdc9da22a74 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/wlan_defs.h @@ -0,0 +1,78 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __WLAN_DEFS_H__ +#define __WLAN_DEFS_H__ + +/* + * This file contains WLAN definitions that may be used across both + * Host and Target software. + */ + +typedef enum +{ + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11b/g Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ +#ifdef SUPPORT_11N + MODE_11NA_HT20 = 4, /* 11a HT20 mode */ + MODE_11NG_HT20 = 5, /* 11g HT20 mode */ + MODE_11NA_HT40 = 6, /* 11a HT40 mode */ + MODE_11NG_HT40 = 7, /* 11g HT40 mode */ + MODE_UNKNOWN = 8, + MODE_MAX = 8 +#else + MODE_UNKNOWN = 4, + MODE_MAX = 4 +#endif +} WLAN_PHY_MODE; + +typedef enum +{ + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3 +} WLAN_CAPABILITY; + +#ifdef SUPPORT_11N +typedef unsigned long A_RATEMASK; +#else +typedef unsigned short A_RATEMASK; +#endif + +#ifdef SUPPORT_11N +#define IS_MODE_11A(mode) (((mode) == MODE_11A) || ((mode) == MODE_11NA_HT20) || ((mode) == MODE_11NA_HT40)) +#define IS_MODE_11B(mode) ((mode) == MODE_11B) +#define IS_MODE_11G(mode) \ + (((mode) == MODE_11G) || ((mode) == MODE_11GONLY) || ((mode) == MODE_11NG_HT20) || ((mode) == MODE_11NG_HT40)) +#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) +#else +#define IS_MODE_11A(mode) ((mode) == MODE_11A) +#define IS_MODE_11B(mode) ((mode) == MODE_11B) +#define IS_MODE_11G(mode) (((mode) == MODE_11G) || ((mode) == MODE_11GONLY)) +#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) +#endif /* SUPPORT_11N */ + +#endif /* __WLANDEFS_H__ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/wmi.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/wmi.h new file mode 100644 index 00000000000..70403ebe8ca --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/include/wmi.h @@ -0,0 +1,3082 @@ +//------------------------------------------------------------------------------ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// · Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// · Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// · Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to commands + * belongs to the host driver and the WMI is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +//#include "wmix.h" +#include "wlan_defs.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define MAX_EVENT_SIZE 1200 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI \ + { \ + 0x00, 0x00, 0x00 \ + } + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +#define WOW_MAX_PATTERN_LEN 64 + +#ifdef AR6002_REV2 +#define IBSS_MAX_NUM_STA 4 +#else +#define IBSS_MAX_NUM_STA 8 +#endif + +struct host_app_area_s +{ + uint32_t wmi_protocol_ver; +}; + +typedef PREPACK struct +{ + uint8_t a FIELD_PACKED; + uint8_t b FIELD_PACKED; + uint8_t c FIELD_PACKED; +} POSTPACK MY_TEST; + +/* + * Data Path + */ +typedef PREPACK struct +{ + uint8_t dstMac[ATH_MAC_LEN] FIELD_PACKED; + uint8_t srcMac[ATH_MAC_LEN] FIELD_PACKED; + uint16_t typeOrLen FIELD_PACKED; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct +{ + uint8_t dsap FIELD_PACKED; + uint8_t ssap FIELD_PACKED; + uint8_t cntl FIELD_PACKED; + uint8_t orgCode[3] FIELD_PACKED; + uint16_t etherType FIELD_PACKED; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum +{ + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE +} WMI_MSG_TYPE; + +/* + * Macros for operating on WMI_DATA_HDR (info) field + */ + +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +/* In AP mode, the same bit (b5) is used to indicate Power save state in + * the Rx dir and More data bit state in the tx direction. + */ +#define WMI_DATA_HDR_PS_MASK 0x1 +#define WMI_DATA_HDR_PS_SHIFT 5 + +#define WMI_DATA_HDR_MORE_MASK 0x1 +#define WMI_DATA_HDR_MORE_SHIFT 5 + +typedef enum +{ + WMI_DATA_HDR_DATA_TYPE_802_3 = 0, + WMI_DATA_HDR_DATA_TYPE_802_11, + WMI_DATA_HDR_DATA_TYPE_ACL +} WMI_DATA_HDR_DATA_TYPE; + +#define WMI_DATA_HDR_DATA_TYPE_MASK 0x3 +#define WMI_DATA_HDR_DATA_TYPE_SHIFT 6 + +#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT)) + +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) \ + (h)->info = (uint8_t)(((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | \ + (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_GET_UP(h) (((h)->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK) +#define WMI_DATA_HDR_SET_UP(h, p) \ + (h)->info = (uint8_t)(((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +#define WMI_DATA_HDR_GET_DATA_TYPE(h) (((h)->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) & WMI_DATA_HDR_DATA_TYPE_MASK) +#define WMI_DATA_HDR_SET_DATA_TYPE(h, p) \ + (h)->info = (uint8_t)(((h)->info & ~(WMI_DATA_HDR_DATA_TYPE_MASK << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | \ + ((p) << WMI_DATA_HDR_DATA_TYPE_SHIFT)) + +#define WMI_DATA_HDR_GET_DOT11(h) (WMI_DATA_HDR_GET_DATA_TYPE((h)) == WMI_DATA_HDR_DATA_TYPE_802_11) +#define WMI_DATA_HDR_SET_DOT11(h, p) WMI_DATA_HDR_SET_DATA_TYPE((h), (p)) + +/* Macros for operating on WMI_DATA_HDR (info2) field */ +#define WMI_DATA_HDR_SEQNO_MASK 0xFFF +#define WMI_DATA_HDR_SEQNO_SHIFT 0 + +#define WMI_DATA_HDR_AMSDU_MASK 0x1 +#define WMI_DATA_HDR_AMSDU_SHIFT 12 + +#define WMI_DATA_HDR_META_MASK 0x7 +#define WMI_DATA_HDR_META_SHIFT 13 + +#define GET_SEQ_NO(_v) ((_v)&WMI_DATA_HDR_SEQNO_MASK) +#define GET_ISMSDU(_v) ((_v)&WMI_DATA_HDR_AMSDU_MASK) + +#define WMI_DATA_HDR_GET_SEQNO(h) GET_SEQ_NO((h)->info2 >> WMI_DATA_HDR_SEQNO_SHIFT) +#define WMI_DATA_HDR_SET_SEQNO(h, _v) \ + ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_SEQNO_MASK << WMI_DATA_HDR_SEQNO_SHIFT)) | \ + (GET_SEQ_NO(_v) << WMI_DATA_HDR_SEQNO_SHIFT)) + +#define WMI_DATA_HDR_IS_AMSDU(h) GET_ISMSDU((h)->info2 >> WMI_DATA_HDR_AMSDU_SHIFT) +#define WMI_DATA_HDR_SET_AMSDU(h, _v) \ + ((h)->info2 = (uint16_t)((h)->info2 & ~(WMI_DATA_HDR_AMSDU_MASK << WMI_DATA_HDR_AMSDU_SHIFT)) | \ + (GET_ISMSDU(_v) << WMI_DATA_HDR_AMSDU_SHIFT)) + +#define WMI_DATA_HDR_GET_META(h) (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK) +#define WMI_DATA_HDR_SET_META(h, _v) \ + ((h)->info2 = (uint16_t)(((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | \ + ((_v) << WMI_DATA_HDR_META_SHIFT))) + +/* Macros for operating on WMI_DATA_HDR (info3) field */ +#define WMI_DATA_HDR_DEVID_MASK 0xF +#define WMI_DATA_HDR_DEVID_SHIFT 0 +#define GET_DEVID(_v) ((_v)&WMI_DATA_HDR_DEVID_MASK) + +#define WMI_DATA_HDR_GET_DEVID(h) (((h)->info3 >> WMI_DATA_HDR_DEVID_SHIFT) & WMI_DATA_HDR_DEVID_MASK) +#define WMI_DATA_HDR_SET_DEVID(h, _v) \ + ((h)->info3 = ((h)->info3 & ~(WMI_DATA_HDR_DEVID_MASK << WMI_DATA_HDR_DEVID_SHIFT)) | \ + (GET_DEVID(_v) << WMI_DATA_HDR_DEVID_SHIFT)) + +#define WMI_DATA_HDR_RXFILT_SHIFT 4 +#define WMI_DATA_HDR_RXFILT_MASK (0x1 << WMI_DATA_HDR_RXFILT_SHIFT) + +#define WMI_DATA_HDR_IS_RXFILTERED(h) ((h)->info3 & WMI_DATA_HDR_RXFILT_MASK) +#define SET_WMI_DATA_HDR_RXFILTERED(h) (h)->info3 |= WMI_DATA_HDR_RXFILT_MASK + +#define WMI_DATA_HDR_TRIGGER_MASK 0x1 +#define WMI_DATA_HDR_TRIGGER_SHIFT 4 +#define WMI_DATA_HDR_SET_TRIGGER(h, _v) \ + ((h)->info3 = ((h)->info3 & ~(WMI_DATA_HDR_TRIGGER_MASK << WMI_DATA_HDR_TRIGGER_SHIFT)) | \ + ((_v) << WMI_DATA_HDR_TRIGGER_SHIFT)) +#define WMI_DATA_HDR_IS_TRIGGER(h) \ + ((((h)->info3 >> WMI_DATA_HDR_TRIGGER_SHIFT) & WMI_DATA_HDR_TRIGGER_MASK) == WMI_DATA_HDR_TRIGGER_MASK) + +#define WMI_DATA_HDR_EOSP_MASK WMI_DATA_HDR_TRIGGER_MASK +#define WMI_DATA_HDR_EOSP_SHIFT WMI_DATA_HDR_TRIGGER_SHIFT + +#define WMI_DATA_HDR_SET_EOSP_BIT(h) ((h)->info3 |= (WMI_DATA_HDR_EOSP_MASK << WMI_DATA_HDR_EOSP_SHIFT)) +#define WMI_DATA_HDR_HAS_EOSP_BIT(h) ((h)->info3 & (WMI_DATA_HDR_EOSP_MASK << WMI_DATA_HDR_EOSP_SHIFT)) + +#define WMI_DATA_HDR_CCX_LINKTEST_MASK 0x1 +#define WMI_DATA_HDR_CCX_LINKTEST_SHIFT 5 +#define WMI_DATA_HDR_SET_CCX_LINKTEST_BIT(h) \ + ((h)->info3 |= (WMI_DATA_HDR_CCX_LINKTEST_MASK << WMI_DATA_HDR_CCX_LINKTEST_SHIFT)) +#define WMI_DATA_HDR_HAS_CCX_LINKTEST_BIT(h) \ + ((h)->info3 & (WMI_DATA_HDR_CCX_LINKTEST_MASK << WMI_DATA_HDR_CCX_LINKTEST_SHIFT)) + +#define WMI_DATA_HDR_PAD_BEFORE_DATA_MASK 0xFF +#define WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT 0x8 +#define GET_PAD_BEFORE_DATA_START(_v) ((_v)&WMI_DATA_HDR_PAD_BEFORE_DATA_MASK) + +#define WMI_DATA_HDR_GET_PAD_BEFORE_DATA_START(h) \ + (((h)->info3 >> WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT) & WMI_DATA_HDR_PAD_BEFORE_DATA_MASK) +#define WMI_DATA_HDR_SET_PAD_BEFORE_DATA_START(h, _v) \ + ((h)->info3 = ((h)->info3 & ~(WMI_DATA_HDR_PAD_BEFORE_DATA_MASK << WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT)) | \ + (GET_PAD_BEFORE_DATA_START(_v) << WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT)) + +#define WMI_DATA_HDR_TRIGGERED_MASK 0x1 +#define WMI_DATA_HDR_TRIGGERED_SHIFT 6 +#define WMI_DATA_HDR_SET_TRIGGERED_BIT(h) ((h)->info3 |= (WMI_DATA_HDR_TRIGGERED_MASK << WMI_DATA_HDR_TRIGGERED_SHIFT)) +#define WMI_DATA_HDR_HAS_TRIGGERED_BIT(h) ((h)->info3 & (WMI_DATA_HDR_TRIGGERED_MASK << WMI_DATA_HDR_TRIGGERED_SHIFT)) + +#define WMI_DATA_HDR_PSPOLLED_MASK 0x1 +#define WMI_DATA_HDR_PSPOLLED_SHIFT 7 +#define WMI_DATA_HDR_SET_PSPOLLED_BIT(h) ((h)->info3 |= (WMI_DATA_HDR_PSPOLLED_MASK << WMI_DATA_HDR_PSPOLLED_SHIFT)) +#define WMI_DATA_HDR_HAS_PSPOLLED_BIT(h) ((h)->info3 & (WMI_DATA_HDR_PSPOLLED_MASK << WMI_DATA_HDR_PSPOLLED_SHIFT)) + +#define WMI_DATA_HDR_PAD_BEFORE_DATA_MASK 0xFF +#define WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT 0x8 +#define GET_PAD_BEFORE_DATA_START(_v) ((_v)&WMI_DATA_HDR_PAD_BEFORE_DATA_MASK) + +#define WMI_DATA_HDR_HOST_RETRY_MASK 0x1 +#define WMI_DATA_HDR_GET_HOST_RETRY(h) (WMI_DATA_HDR_GET_PAD_BEFORE_DATA_START(h) & WMI_DATA_HDR_HOST_RETRY_MASK) + +#define WMI_DATA_HDR_GET_PAD_BEFORE_DATA_START(h) \ + (((h)->info3 >> WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT) & WMI_DATA_HDR_PAD_BEFORE_DATA_MASK) +#define WMI_DATA_HDR_SET_PAD_BEFORE_DATA_START(h, _v) \ + ((h)->info3 = ((h)->info3 & ~(WMI_DATA_HDR_PAD_BEFORE_DATA_MASK << WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT)) | \ + (GET_PAD_BEFORE_DATA_START(_v) << WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT)) + +#define WMI_DATA_HDR_EXCEPTION_BIT_MASK 0x1 +#define WMI_DATA_HDR_EXCEPTION_BIT_SHIFT 8 +#define WMI_DATA_HDR_SET_EXCEPTION_BIT(h) \ + ((h)->info3 |= (WMI_DATA_HDR_EXCEPTION_BIT_MASK << WMI_DATA_HDR_EXCEPTION_BIT_SHIFT)) + +#define WMI_DATA_HDR_AMPDU_FLUSH_BIT_MASK 0x1 +#define WMI_DATA_HDR_AMPDU_FLUSH_BIT_SHIFT 9 +#define WMI_DATA_HDR_SET_AMPDU_FLUSH_BIT(h) \ + ((h)->info3 |= (WMI_DATA_HDR_AMPDU_FLUSH_BIT_MASK << WMI_DATA_HDR_AMPDU_FLUSH_BIT_SHIFT)) + +#define WMI_DATA_HDR_WLAN_BIT_MASK 0x0 +#define WMI_DATA_HDR_WLAN_BIT_SHIFT 10 +#define WMI_DATA_HDR_SET_WLAN_BIT(h) ((h)->info3 |= (WMI_DATA_HDR_WLAN_BIT_MASK << WMI_DATA_HDR_WLAN_BIT_SHIFT)) + +#define WMI_DATA_HDR_WAN_BIT_MASK 0x1 +#define WMI_DATA_HDR_WAN_BIT_SHIFT 10 +#define WMI_DATA_HDR_SET_WAN_BIT(h) ((h)->info3 |= (WMI_DATA_HDR_WAN_BIT_MASK << WMI_DATA_HDR_WAN_BIT_SHIFT)) + +#define WMI_DATA_HDR_OUT_OF_ORDER_BIT_MASK 0x1 +#define WMI_DATA_HDR_OUT_OF_ORDER_BIT_SHIFT 11 +#define WMI_DATA_HDR_SET_OUT_OF_ORDER_BIT(h) \ + ((h)->info3 |= (WMI_DATA_HDR_OUT_OF_ORDER_BIT_MASK << WMI_DATA_HDR_OUT_OF_ORDER_BIT_SHIFT)) + +#define WMI_DATA_HDR_FLUSH_ALL_BIT_MASK 0x1 +#define WMI_DATA_HDR_FLUSH_ALL_BIT_SHIFT 12 +#define WMI_DATA_HDR_SET_FLUSH_ALL_BIT(h) \ + ((h)->info3 |= (WMI_DATA_HDR_FLUSH_ALL_BIT_MASK << WMI_DATA_HDR_FLUSH_ALL_BIT_SHIFT)) + +#define WMI_DATA_HDR_PARTIAL_FLUSH_BIT_MASK 0x1 +#define WMI_DATA_HDR_PARTIAL_FLUSH_BIT_SHIFT 13 +#define WMI_DATA_HDR_SET_PARTIAL_FLUSH_BIT(h) \ + ((h)->info3 |= (WMI_DATA_HDR_PARTIAL_FLUSH_BIT_MASK << WMI_DATA_HDR_PARTIAL_FLUSH_BIT_SHIFT)) + +typedef PREPACK struct +{ + int8_t rssi FIELD_PACKED; + uint8_t info FIELD_PACKED; /* usage of 'info' field(8-bit): + * b1:b0 - WMI_MSG_TYPE + * b4:b3:b2 - UP(tid) + * b5 - Used in AP mode. More-data in tx dir, PS in rx. + * b7:b6 - Dot3 header(0), + * Dot11 Header(1), + * ACL data(2) + */ + + uint16_t info2 FIELD_PACKED; /* usage of 'info2' field(16-bit): + * b11:b0 - seq_no + * b12 - A-MSDU? + * b15:b13 - META_DATA_VERSION 0 - 7 + */ + uint16_t info3 FIELD_PACKED; /* b3:b2:b1:b0 - device id + * b4 - Used in AP mode. uAPSD trigger in rx, EOSP in tx + * b5 - Used by CCX. + * b6 - Used in AP mode. uAPSD triggered frame in tx, + * meaningless in rx + * b7 - Used in AP mode. PS-POLL triggered frame in tx, + * meaningless in rx + * b15:b8 - pad before data start(irrespective of meta version) + */ +} POSTPACK WMI_DATA_HDR; + +/* + * TX META VERSION DEFINITIONS + */ +#define WMI_MAX_TX_META_SZ (12) +#define WMI_MAX_TX_META_VERSION (7) +#define WMI_META_VERSION_1 (0x01) +#define WMI_META_VERSION_2 (0x02) +#define WMI_META_VERSION_3 (0x03) +#define WMI_META_VERSION_4 (0x04) +#define WMI_META_VERSION_5 (0x05) // USed for stack offload packets + +#define WMI_ACL_TO_DOT11_HEADROOM 36 + +#if 0 /* removed to prevent compile errors for WM.. */ +typedef PREPACK struct { +/* intentionally empty. Default version is no meta data. */ +} POSTPACK WMI_TX_META_V0; +#endif + +typedef PREPACK struct +{ + uint8_t pktID FIELD_PACKED; /* The packet ID to identify the tx request */ + uint8_t ratePolicyID FIELD_PACKED; /* The rate policy to be used for the tx of this frame */ +} POSTPACK WMI_TX_META_V1; + +#define WMI_CSUM_DIR_TX (0x1) +#define TX_CSUM_CALC_FILL (0x1) +typedef PREPACK struct +{ + uint8_t csumStart FIELD_PACKED; /*Offset from start of the WMI header for csum calculation to begin */ + uint8_t csumDest FIELD_PACKED; /*Offset from start of WMI header where final csum goes*/ + uint8_t csumFlags FIELD_PACKED; /*number of bytes over which csum is calculated*/ +} POSTPACK WMI_TX_META_V2; + +/* WMI_META_TX_FLAG... are used as TX qualifiers for frames containing WMI_TX_RATE_SCHEDULE in the + * meta data. 0 or more of these flags should be assigned to the flags member of the schedule. */ +#define WMI_META_TX_FLAG_ACK 0x01 // frame needs ACK response from receiver +#define WMI_META_TX_FLAG_SET_RETRY_BIT 0x02 // device will set retry bit in MAC header for retried frames. +#define WMI_META_TX_FLAG_SET_DURATION 0x04 // device will fill duration field in MAC header +/* NOTE: If WMI_META_TX_FLAG_USE_PREFIX == 0 device will NOT use prefix frame. + * If WMI_META_TX_FLAG_USE_PREFIX == 1 && WMI_META_TX_FLAG_PREFIX_RTS == 0 device will use CTS prefix. + * If WMI_META_TX_FLAG_USE_PREFIX == 1 && WMI_META_TX_FLAG_PREFIX_RTS == 1 device will use RTS prefix. + */ +#define WMI_META_TX_FLAG_USE_PREFIX 0x08 // device will send either RTS or CTS frame prior to subject frame. +#define WMI_META_TX_FLAG_PREFIX_RTS 0x10 // device will send RTS and wait for CTS prior to sending subject frame. +#define WMI_META_TX_LOAD_TSF 0x20 // device will fill the TSF field during transmit procedure. + +/* WMI_TX_RATE_SCHEDULE - Acts as a host-provided rate schedule to replace what would be normally determined + * by firmware. This allows the host to specify what rates and attempts should be used to transmit the + * frame. */ +typedef PREPACK struct +{ +#define WMI_TX_MAX_RATE_SERIES (4) + uint8_t rateSeries[WMI_TX_MAX_RATE_SERIES] FIELD_PACKED; // rate index for each series. first invalid rate + // terminates series. + uint8_t trySeries[WMI_TX_MAX_RATE_SERIES] FIELD_PACKED; // number of tries for each series. + uint8_t flags FIELD_PACKED; // combination of WMI_META_TX_FLAG... + uint8_t accessCategory FIELD_PACKED; // should be WMM_AC_BE for managment frames and multicast frames. + // uint8_t keyIndex FIELD_PACKED; + // +} POSTPACK WMI_TX_RATE_SCHEDULE; + +typedef PREPACK struct +{ + WMI_TX_RATE_SCHEDULE rateSched FIELD_PACKED; + uint8_t pktID FIELD_PACKED; /* The packet ID to identify the tx request */ +} POSTPACK WMI_TX_META_V3; + +typedef PREPACK struct +{ + uint8_t reserved FIELD_PACKED; +} POSTPACK WMI_TX_META_V5; + +/* + * RX META VERSION DEFINITIONS + */ +/* if RX meta data is present at all then the meta data field + * will consume WMI_MAX_RX_META_SZ bytes of space between the + * WMI_DATA_HDR and the payload. How much of the available + * Meta data is actually used depends on which meta data + * version is active. */ +#define WMI_MAX_RX_META_SZ (12) +#define WMI_MAX_RX_META_VERSION (7) + +#define WMI_RX_STATUS_OK 0 /* success */ +#define WMI_RX_STATUS_DECRYPT_ERR 1 /* decrypt error */ +#define WMI_RX_STATUS_MIC_ERR 2 /* tkip MIC error */ +#define WMI_RX_STATUS_ERR 3 /* undefined error */ + +#define WMI_RX_FLAGS_AGGR 0x0001 /* part of AGGR */ +#define WMI_RX_FlAGS_STBC 0x0002 /* used STBC */ +#define WMI_RX_FLAGS_SGI 0x0004 /* used SGI */ +#define WMI_RX_FLAGS_HT 0x0008 /* is HT packet */ + /* the flags field is also used to store the CRYPTO_TYPE of the frame + * that value is shifted by WMI_RX_FLAGS_CRYPTO_SHIFT */ +#define WMI_RX_FLAGS_CRYPTO_SHIFT 4 +#define WMI_RX_FLAGS_CRYPTO_MASK 0x1f +#define WMI_RX_META_GET_CRYPTO(flags) (((flags) >> WMI_RX_FLAGS_CRYPTO_SHIFT) & WMI_RX_FLAGS_CRYPTO_MASK) + +#if 0 /* removed to prevent compile errors for WM.. */ +typedef PREPACK struct { +/* intentionally empty. Default version is no meta data. */ +} POSTPACK WMI_RX_META_VERSION_0; +#endif + +typedef PREPACK struct +{ + uint8_t status FIELD_PACKED; /* one of WMI_RX_STATUS_... */ + uint8_t rix FIELD_PACKED; /* rate index mapped to rate at which this packet was received. */ + uint8_t rssi FIELD_PACKED; /* rssi of packet */ + uint8_t channel FIELD_PACKED; /* rf channel during packet reception */ + uint16_t flags FIELD_PACKED; /* a combination of WMI_RX_FLAGS_... */ +} POSTPACK WMI_RX_META_V1; + +#define RX_CSUM_VALID_FLAG (0x1) +typedef PREPACK struct +{ + uint16_t csum FIELD_PACKED; + uint8_t csumFlags FIELD_PACKED; /* bit 0 set -partial csum valid + bit 1 set -test mode */ +} POSTPACK WMI_RX_META_V2; + +/* Macros for operating on WMI_CMD_HDR (info1) field */ +#define WMI_CMD_HDR_DEVID_MASK 0xF +#define WMI_CMD_HDR_DEVID_SHIFT 0 + +#define WMI_GET_DEVICE_ID(info1) ((info1)&0xF) +#define WMI_SET_DEVICE_ID(h, _v) \ + ((h)->info1 = ((h)->info1 & ~(WMI_CMD_HDR_DEVID_MASK << WMI_CMD_HDR_DEVID_SHIFT)) | \ + (WMI_GET_DEVICE_ID(_v) << WMI_CMD_HDR_DEVID_SHIFT)) + +/* + * Control Path + */ +typedef PREPACK struct +{ + uint16_t commandId FIELD_PACKED; + /* + * info1 - 16 bits + * b03:b00 - id + * b15:b04 - unused + */ + uint16_t info1 FIELD_PACKED; + + uint16_t reserved FIELD_PACKED; /* For alignment */ +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum +{ + WMI_CONNECT_CMDID = 0x0001, + WMI_RECONNECT_CMDID = 0x0002, + WMI_DISCONNECT_CMDID = 0x0003, + WMI_SYNCHRONIZE_CMDID = 0x0004, + WMI_START_SCAN_CMDID = 0x0007, + WMI_SET_SCAN_PARAMS_CMDID = 0x0008, + WMI_SET_BSS_FILTER_CMDID = 0x0009, + WMI_SET_PROBED_SSID_CMDID = 0x000a, /* 10 */ + WMI_SET_LISTEN_INT_CMDID = 0x000b, + WMI_GET_CHANNEL_LIST_CMDID = 0x000e, + WMI_SET_BEACON_INT_CMDID = 0x000f, + WMI_GET_STATISTICS_CMDID = 0x0010, + WMI_SET_CHANNEL_PARAMS_CMDID = 0x0011, + WMI_SET_POWER_MODE_CMDID = 0x0012, + WMI_SET_POWER_PARAMS_CMDID = 0x0014, /* 20 */ + WMI_ADD_CIPHER_KEY_CMDID = 0x0016, + WMI_DELETE_CIPHER_KEY_CMDID = 0x0017, + WMI_SET_TX_PWR_CMDID = 0x001b, + WMI_GET_TX_PWR_CMDID = 0x001c, + WMI_TARGET_ERROR_REPORT_BITMASK_CMDID = 0x0022, + WMI_SET_ROAM_CTRL_CMDID = 0x0029, + WMI_EXTENSION_CMDID = 0x002e, + WMI_SET_RTS_CMDID = 0x0032, /* 50 */ +#if MANUFACTURING_SUPPORT + WMI_TEST_CMDID = 0x003a, +#endif + WMI_SET_KEEPALIVE_CMDID = 0x003d, + WMI_GET_KEEPALIVE_CMDID = 0x003e, + WMI_SET_APPIE_CMDID = 0x003f, +#if ENABLE_AP_MODE + WMI_AP_SET_NUM_STA_CMDID = 0xf00c, + WMI_AP_HIDDEN_SSID_CMDID = 0xf00b, + WMI_AP_CONFIG_COMMIT_CMDID = 0xf00f, + WMI_AP_CONN_INACT_CMDID = 0xf012, + RESERVED = 0xf014, + WMI_AP_SET_DTIM_CMDID = 0xf015, + WMI_AP_PSBUF_OFFLOAD_CMDID = 0xf0AF, +#endif + WMI_ALLOW_AGGR_CMDID = 0xf01b, /* F01B */ + WMI_SET_HT_CAP_CMDID = 0xf01e, + WMI_SET_PMK_CMDID = 0xf028, +#if ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 + WMI_SET_CHANNEL_CMDID = 0xf042, + WMI_GET_PMK_CMDID = 0xf047, + WMI_SET_PASSPHRASE_CMDID = 0xf048, + WMI_STORERECALL_CONFIGURE_CMDID = 0xf04e, + WMI_STORERECALL_RECALL_CMDID = 0xf04f, + WMI_STORERECALL_HOST_READY_CMDID = 0xf050, + + /* WPS Commands */ + WMI_WPS_START_CMDID = 0xf053, + WMI_GET_WPS_STATUS_CMDID = 0xf054, + /*Socket commands*/ + WMI_SOCKET_CMDID = 0xf055, + WMI_SET_FILTERED_PROMISCUOUS_MODE_CMDID = 0xf056, +#elif ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1 + WMI_SET_CHANNEL_CMDID = 0xf042, + WMI_GET_PMK_CMDID = 0xf047, + WMI_SET_PASSPHRASE_CMDID = 0xf048, + WMI_STORERECALL_CONFIGURE_CMDID = 0xf05e, + WMI_STORERECALL_RECALL_CMDID = 0xf05f, + WMI_STORERECALL_HOST_READY_CMDID = 0xf060, + /* WPS Commands */ + WMI_WPS_START_CMDID = 0xf07a, + WMI_GET_WPS_STATUS_CMDID = 0xf07b, + /*Socket commands*/ + WMI_SOCKET_CMDID = 0xf08d, + WMI_SET_FILTERED_PROMISCUOUS_MODE_CMDID = 0xf099, +#endif + +#if ENABLE_P2P_MODE +/* P2P CMDS */ + +#if ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 /* Jade */ + WMI_P2P_SET_CONFIG_CMDID = 0xF038, + WMI_WPS_SET_CONFIG_CMDID = 0xF039, + WMI_SET_REQ_DEV_ATTR_CMDID = 0xF03A, + WMI_P2P_FIND_CMDID = 0xF03B, + WMI_P2P_STOP_FIND_CMDID = 0xF03C, + WMI_P2P_LISTEN_CMDID = 0xF03D, + + WMI_P2P_SET_CMDID = 0xF057, + + WMI_P2P_SDPD_TX_CMDID = 0xF058, /* F058 */ + WMI_P2P_STOP_SDPD_CMDID = 0xF059, + WMI_P2P_CANCEL_CMDID = 0xF05a, + WMI_P2P_CONNECT_CMDID = 0xf05b, + WMI_P2P_GET_NODE_LIST_CMDID = 0xf05c, + WMI_P2P_AUTH_GO_NEG_CMDID = 0xf05d, + WMI_P2P_FW_PROV_DISC_REQ_CMDID = 0xf05e, + WMI_P2P_PERSISTENT_PROFILE_CMDID = 0xf05f, + WMI_P2P_SET_JOIN_PROFILE_CMDID = 0xf060, + WMI_P2P_GRP_INIT_CMDID = 0xf061, + WMI_P2P_SET_PROFILE_CMDID = 0xf065, + WMI_P2P_INVITE_CMDID = 0xF070, + WMI_P2P_INVITE_REQ_RSP_CMDID = 0xF071, + WMI_P2P_FW_SET_NOA_CMDID = 0xf072, + WMI_P2P_FW_GET_NOA_CMDID = 0xf073, + WMI_P2P_FW_SET_OPPPS_CMDID = 0xf074, + WMI_P2P_FW_GET_OPPPS_CMDID = 0xf075, + +#elif ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1 + WMI_P2P_SET_CONFIG_CMDID = 0xF038, + WMI_WPS_SET_CONFIG_CMDID = 0xF039, + WMI_SET_REQ_DEV_ATTR_CMDID = 0xF03A, + WMI_P2P_FIND_CMDID = 0xF03B, + WMI_P2P_STOP_FIND_CMDID = 0xF03C, + WMI_P2P_LISTEN_CMDID = 0xF03E, + + WMI_P2P_GRP_INIT_CMDID = 0xF051, + WMI_P2P_GRP_FORMATION_DONE_CMDID = 0xF052, + WMI_P2P_INVITE_CMDID = 0xF053, + WMI_P2P_INVITE_REQ_RSP_CMDID = 0xF054, + WMI_P2P_SET_CMDID = 0xF056, + + WMI_P2P_SDPD_TX_CMDID = 0xF05B, /* F058 */ + WMI_P2P_STOP_SDPD_CMDID = 0xF05C, + WMI_P2P_CANCEL_CMDID = 0xF05D, + WMI_P2P_CONNECT_CMDID = 0xf091, + WMI_P2P_GET_NODE_LIST_CMDID = 0xf092, + WMI_P2P_AUTH_GO_NEG_CMDID = 0xf093, + WMI_P2P_FW_PROV_DISC_REQ_CMDID = 0xf094, + WMI_P2P_PERSISTENT_PROFILE_CMDID = 0xf09D, + WMI_P2P_SET_JOIN_PROFILE_CMDID = 0xf09E, + WMI_P2P_SET_PROFILE_CMDID = 0xf0A8, + WMI_P2P_FW_SET_NOA_CMDID = 0xf0A9, + WMI_P2P_FW_GET_NOA_CMDID = 0xf0AA, + WMI_P2P_FW_SET_OPPPS_CMDID = 0xf0AB, + WMI_P2P_FW_GET_OPPPS_CMDID = 0xf0AC, + WMI_P2P_LIST_PERSISTENT_NETWORK_CMDID = 0xf0D7, +#endif + +#endif + WMI_SET_BITRATE_CMDID = 0xf000, + WMI_GET_BITRATE_CMDID = 0xf001, + /*GreenTx specific commands*/ + WMI_GREENTX_PARAMS_CMDID = 0xF079, + WMI_LPL_FORCE_ENABLE_CMDID = 0xF072, + WMI_ARGOS_CMDID = 0xf0B1, + WMI_SET_CREDIT_REVERSE_CMDID = 0xF0B6, + WMI_SET_RCV_DATA_CLASSIFIER_CMDID, + WMI_SET_TX_POWER_SCALE_CMDID = 0xF0D6, + + WMI_PFM_GET_CMDID = 0xF0DC, + + WMI_DSET_HOST_CFG_CMDID = 0xF0DE, + WMI_DSET_HOST_READ_CMDID = 0xF0DF, + + WMI_HOST_DSET_LARGE_READ_CMDID = 0xF0EA, + WMI_HOST_DSET_LARGE_WRITE_CMDID = 0xF0EB, + WMI_HOST_DSET_RESP_CREATE_CMDID = 0xF0EC, + WMI_HOST_DSET_SYNC_CMDID = 0xF0ED, + WMI_HOST_DSET_READBACK_CMDID = 0xF0EE, + WMI_HOST_DSET_RESP_WRITE_CMDID = 0xF0EF, + + WMI_DSET_OP_CMDID = 0xF0F0, + WMI_GET_TEMPERATURE_CMDID = 0xF0F1, + WMI_PARAM_SET_CMDID = 0xF0F3, + WMI_WLAN_SET_PROBEREQ_ENABLE_CMDID = 0xF0F5, + WMI_GET_COUNTRY_CODE_CMDID = 0xF0F6, + WMI_WLAN_WPS_INIT_KEY_CMDID = 0xF0F7, + WMI_HEATBEAT_CHALLENGE = 0xF0F8, +} WMI_COMMAND_ID; + +typedef PREPACK struct +{ + uint8_t enable; +} POSTPACK WMI_PROBE_REQ_REPORT_CMD_STRUCT; + +typedef PREPACK struct +{ + int32_t param_val; +} POSTPACK WMI_SET_TX_POWER_SCALE_CMD; + +/* + * Frame Types + */ +typedef enum +{ + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum +{ + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + AP_NETWORK = 0x10, + NETWORK_CONNECTED_USING_WPS = 0x20 +} NETWORK_TYPE; + +typedef enum +{ + SUBTYPE_NONE, + SUBTYPE_BT, + SUBTYPE_P2PDEV, + SUBTYPE_P2PCLIENT, + SUBTYPE_P2PGO +} NETWORK_SUBTYPE; + +typedef enum +{ + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04 /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum +{ + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA2_AUTH = 0x04, + WPA_PSK_AUTH = 0x08, + WPA2_PSK_AUTH = 0x10, + WPA_AUTH_CCKM = 0x20, + WPA2_AUTH_CCKM = 0x40 +} AUTH_MODE; + +typedef enum +{ + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x04, + AES_CRYPT = 0x08 +#ifdef WAPI_ENABLE + , + WAPI_CRYPT = 0x10 +#endif /*WAPI_ENABLE*/ +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) + +#ifdef WAPI_ENABLE +#undef WMI_MAX_CRYPTO_TYPE +#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) +#endif /* WAPI_ENABLE */ + +#ifdef WAPI_ENABLE +#define IW_ENCODE_ALG_SM4 0x20 +#define IW_AUTH_WAPI_ENABLED 0x20 +#endif + +#define WMI_MIN_KEY_INDEX 0 +#define WMI_MAX_KEY_INDEX 3 + +#ifdef WAPI_ENABLE +#undef WMI_MAX_KEY_INDEX +#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ +#endif /* WAPI_ENABLE */ + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum +{ + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, + CONNECT_DO_WPA_OFFLOAD = 0x0040, + CONNECT_DO_NOT_DEAUTH = 0x0080, + CONNECT_WPS_FLAG = 0x0100 +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +typedef PREPACK struct +{ + uint8_t networkType FIELD_PACKED; + uint8_t dot11AuthMode FIELD_PACKED; + uint8_t authMode FIELD_PACKED; + uint8_t pairwiseCryptoType FIELD_PACKED; + uint8_t pairwiseCryptoLen FIELD_PACKED; + uint8_t groupCryptoType FIELD_PACKED; + uint8_t groupCryptoLen FIELD_PACKED; + uint8_t ssidLength FIELD_PACKED; + uint8_t ssid[WMI_MAX_SSID_LEN] FIELD_PACKED; + uint16_t channel FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint32_t ctrl_flags FIELD_PACKED; +} POSTPACK WMI_CONNECT_CMD; + +#if ENABLE_AP_MODE +/* + * Used with WMI_AP_HIDDEN_SSID_CMDID + */ +#define HIDDEN_SSID_FALSE 0 +#define HIDDEN_SSID_TRUE 1 + +typedef PREPACK struct +{ + uint8_t hidden_ssid FIELD_PACKED; +} POSTPACK WMI_AP_HIDDEN_SSID_CMD; + +typedef PREPACK struct +{ + uint32_t period FIELD_PACKED; +} POSTPACK WMI_AP_CONN_INACT_CMD; + +typedef PREPACK struct +{ + uint16_t beaconInterval FIELD_PACKED; +} POSTPACK WMI_BEACON_INT_CMD; + +typedef PREPACK struct +{ + uint8_t dtim FIELD_PACKED; +} POSTPACK WMI_AP_SET_DTIM_CMD; + +typedef PREPACK struct +{ + uint8_t enable FIELD_PACKED; /* enable/disable IoE AP PS Offload */ + uint8_t psBufCount FIELD_PACKED; /* PS Buf count per PS Client */ +} POSTPACK WMI_AP_PSBUF_OFFLOAD_CMD; +#endif + +/* + * WMI_RECONNECT_CMDID + */ +typedef PREPACK struct +{ + uint16_t channel FIELD_PACKED; /* hint */ + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; /* mandatory if set */ +} POSTPACK WMI_RECONNECT_CMD; + +#define WMI_PMK_LEN 32 +typedef PREPACK struct +{ + uint8_t pmk[WMI_PMK_LEN] FIELD_PACKED; + uint8_t pmk_len FIELD_PACKED; +} POSTPACK WMI_SET_PMK_CMD, WMI_GET_PMK_REPLY; + +#define WMI_PASSPHRASE_LEN 64 +typedef PREPACK struct +{ + uint8_t ssid[WMI_MAX_SSID_LEN] FIELD_PACKED; + uint8_t passphrase[WMI_PASSPHRASE_LEN] FIELD_PACKED; + uint8_t ssid_len FIELD_PACKED; + uint8_t passphrase_len FIELD_PACKED; +} POSTPACK WMI_SET_PASSPHRASE_CMD; + +/* + * WMI_ADD_CIPHER_KEY_CMDID + */ +typedef enum +{ + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02 /* default Tx Key - Static WEP only */ +} KEY_USAGE; + +/* + * Bit Flag + * Bit 0 - Initialise TSC - default is Initialize + */ +#define KEY_OP_INIT_TSC 0x01 +#define KEY_OP_INIT_RSC 0x02 +#ifdef WAPI_ENABLE +#define KEY_OP_INIT_WAPIPN 0x10 +#endif /* WAPI_ENABLE */ + +#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ +#define KEY_OP_VALID_MASK 0x03 + +typedef PREPACK struct +{ + uint8_t keyIndex FIELD_PACKED; + uint8_t keyType FIELD_PACKED; + uint8_t keyUsage FIELD_PACKED; /* KEY_USAGE */ + uint8_t keyLength FIELD_PACKED; + uint8_t keyRSC[8] FIELD_PACKED; /* key replay sequence counter */ + uint8_t key[WMI_MAX_KEY_LEN] FIELD_PACKED; + uint8_t key_op_ctrl FIELD_PACKED; /* Additional Key Control information */ + uint8_t key_macaddr[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_ADD_CIPHER_KEY_CMD; + +/* + * WMI_DELETE_CIPHER_KEY_CMDID + */ +typedef PREPACK struct +{ + uint8_t keyIndex FIELD_PACKED; +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD; + +/* + * WMI_START_SCAN_CMD + */ +typedef enum +{ + WMI_LONG_SCAN = 0, + WMI_SHORT_SCAN = 1 +} WMI_SCAN_TYPE; + +typedef PREPACK struct +{ + boolean forceFgScan FIELD_PACKED; + boolean isLegacy FIELD_PACKED; /* For Legacy Cisco AP compatibility */ + uint32_t homeDwellTime FIELD_PACKED; /* Maximum duration in the home channel(milliseconds) */ + uint32_t forceScanInterval FIELD_PACKED; /* Time interval between scans (milliseconds)*/ + uint8_t scanType FIELD_PACKED; /* WMI_SCAN_TYPE */ + uint8_t numChannels FIELD_PACKED; /* how many channels follow */ + uint16_t channelList[1] FIELD_PACKED; /* channels in Mhz */ +} POSTPACK WMI_START_SCAN_CMD; + +/* + * WMI_SET_SCAN_PARAMS_CMDID + */ +#define WMI_SHORTSCANRATIO_DEFAULT 3 +/* + * Warning: ScanCtrlFlag value of 0xFF is used to disable all flags in WMI_SCAN_PARAMS_CMD + * Do not add any more flags to WMI_SCAN_CTRL_FLAG_BITS + */ +typedef enum +{ + CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ + SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ + /* already connected to */ + ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ + ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ + REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ + ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't + scan after a disconnect event */ + ENABLE_SCAN_ABORT_EVENT = + 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets + completed */ +} WMI_SCAN_CTRL_FLAGS_BITS; + +#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) +#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) +#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) +#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) +#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) +#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) + +#define DEFAULT_SCAN_CTRL_FLAGS \ + (CONNECT_SCAN_CTRL_FLAGS | SCAN_CONNECTED_CTRL_FLAGS | ACTIVE_SCAN_CTRL_FLAGS | ROAM_SCAN_CTRL_FLAGS | \ + ENABLE_AUTO_CTRL_FLAGS) + +typedef PREPACK struct +{ + uint16_t fg_start_period FIELD_PACKED; /* seconds */ + uint16_t fg_end_period FIELD_PACKED; /* seconds */ + uint16_t bg_period FIELD_PACKED; /* seconds */ + uint16_t maxact_chdwell_time FIELD_PACKED; /* msec */ + uint16_t pas_chdwell_time FIELD_PACKED; /* msec */ + uint8_t shortScanRatio FIELD_PACKED; /* how many shorts scan for one long */ + uint8_t scanCtrlFlags FIELD_PACKED; + uint16_t minact_chdwell_time FIELD_PACKED; /* msec */ + uint16_t maxact_scan_per_ssid FIELD_PACKED; /* max active scans per ssid */ + uint32_t max_dfsch_act_time FIELD_PACKED; /* msecs */ +} POSTPACK WMI_SCAN_PARAMS_CMD; + +/* + * WMI_SET_BSS_FILTER_CMDID + */ +typedef enum +{ + NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ + ALL_BSS_FILTER, /* all beacons forwarded */ + PROFILE_FILTER, /* only beacons matching profile */ + ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ + CURRENT_BSS_FILTER, /* only beacons matching current BSS */ + ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ + PROBED_SSID_FILTER, /* beacons matching probed ssid */ + LAST_BSS_FILTER /* marker only */ +} WMI_BSS_FILTER; + +typedef PREPACK struct +{ + uint8_t bssFilter FIELD_PACKED; /* see WMI_BSS_FILTER */ + uint8_t reserved1 FIELD_PACKED; /* For alignment */ + uint16_t reserved2 FIELD_PACKED; /* For alignment */ + uint32_t ieMask FIELD_PACKED; +} POSTPACK WMI_BSS_FILTER_CMD; + +/* + * WMI_SET_PROBED_SSID_CMDID + */ +#define MAX_PROBED_SSID_INDEX 9 + +typedef enum +{ + DISABLE_SSID_FLAG = 0, /* disables entry */ + SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ + ANY_SSID_FLAG = 0x02 /* probes for any ssid */ +} WMI_SSID_FLAG; + +typedef PREPACK struct +{ + uint8_t entryIndex FIELD_PACKED; /* 0 to MAX_PROBED_SSID_INDEX */ + uint8_t flag FIELD_PACKED; /* WMI_SSID_FLG */ + uint8_t ssidLength FIELD_PACKED; + uint8_t ssid[32] FIELD_PACKED; +} POSTPACK WMI_PROBED_SSID_CMD; + +/* + * WMI_SET_LISTEN_INT_CMDID + * The Listen interval is between 15 and 3000 TUs + */ +#define MIN_LISTEN_INTERVAL 15 +#define MAX_LISTEN_INTERVAL 5000 +#define MIN_LISTEN_BEACONS 1 +#define MAX_LISTEN_BEACONS 50 + +typedef PREPACK struct +{ + uint16_t listenInterval FIELD_PACKED; + uint16_t numBeacons FIELD_PACKED; +} POSTPACK WMI_LISTEN_INT_CMD; + +/* + * WMI_SET_BMISS_TIME_CMDID + * valid values are between 1000 and 5000 TUs + */ + +#define MIN_BMISS_TIME 1000 +#define MAX_BMISS_TIME 5000 +#define MIN_BMISS_BEACONS 1 +#define MAX_BMISS_BEACONS 50 + +typedef PREPACK struct +{ + uint16_t bmissTime FIELD_PACKED; + uint16_t numBeacons FIELD_PACKED; +} POSTPACK WMI_BMISS_TIME_CMD; + +/* + * WMI_SET_POWER_MODE_CMDID + */ +typedef enum +{ + REC_POWER = 0x01, + MAX_PERF_POWER +} WMI_POWER_MODE; + +typedef PREPACK struct +{ + uint8_t powerMode FIELD_PACKED; /* WMI_POWER_MODE */ +} POSTPACK WMI_POWER_MODE_CMD; + +typedef PREPACK struct +{ + int8_t status FIELD_PACKED; /* WMI_SET_PARAMS_REPLY */ +} POSTPACK WMI_SET_PARAMS_REPLY; + +/* + * WMI_SET_POWER_PARAMS_CMDID + */ +typedef enum +{ + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, + AUTO_DTIM = 0x04 +} WMI_DTIM_POLICY; + +/* Policy to determnine whether TX should wakeup WLAN if sleeping */ +typedef enum +{ + TX_WAKEUP_UPON_SLEEP = 1, + TX_DONT_WAKEUP_UPON_SLEEP = 2 +} WMI_TX_WAKEUP_POLICY_UPON_SLEEP; + +/* + * Policy to determnine whether power save failure event should be sent to + * host during scanning + */ +typedef enum +{ + SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1, + IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2 +} POWER_SAVE_FAIL_EVENT_POLICY; + +typedef PREPACK struct +{ + uint16_t idle_period FIELD_PACKED; /* msec */ + uint16_t pspoll_number FIELD_PACKED; + uint16_t dtim_policy FIELD_PACKED; + uint16_t tx_wakeup_policy FIELD_PACKED; + uint16_t num_tx_to_wakeup FIELD_PACKED; + uint16_t ps_fail_event_policy FIELD_PACKED; +} POSTPACK WMI_POWER_PARAMS_CMD; + +/* Adhoc power save types */ +typedef enum +{ + ADHOC_PS_DISABLE = 1, + ADHOC_PS_ATH = 2, + ADHOC_PS_IEEE = 3, + ADHOC_PS_OTHER = 4 +} WMI_ADHOC_PS_TYPE; + +/* + * WMI_SET_DISC_TIMEOUT_CMDID + */ +typedef PREPACK struct +{ + uint8_t disconnectTimeout FIELD_PACKED; /* seconds */ +} POSTPACK WMI_DISC_TIMEOUT_CMD; + +typedef enum +{ + UPLINK_TRAFFIC = 0, + DNLINK_TRAFFIC = 1, + BIDIR_TRAFFIC = 2 +} DIR_TYPE; + +typedef enum +{ + DISABLE_FOR_THIS_AC = 0, + ENABLE_FOR_THIS_AC = 1, + ENABLE_FOR_ALL_AC = 2 +} VOICEPS_CAP_TYPE; + +typedef enum +{ + TRAFFIC_TYPE_APERIODIC = 0, + TRAFFIC_TYPE_PERIODIC = 1 +} TRAFFIC_TYPE; + +/* + * WMI_SYNCHRONIZE_CMDID + */ +typedef PREPACK struct +{ + uint8_t dataSyncMap FIELD_PACKED; +} POSTPACK WMI_SYNC_CMD; + +/* + * WMI_CREATE_PSTREAM_CMDID + */ +typedef PREPACK struct +{ + uint32_t minServiceInt FIELD_PACKED; /* in milli-sec */ + uint32_t maxServiceInt FIELD_PACKED; /* in milli-sec */ + uint32_t inactivityInt FIELD_PACKED; /* in milli-sec */ + uint32_t suspensionInt FIELD_PACKED; /* in milli-sec */ + uint32_t serviceStartTime FIELD_PACKED; + uint32_t minDataRate FIELD_PACKED; /* in bps */ + uint32_t meanDataRate FIELD_PACKED; /* in bps */ + uint32_t peakDataRate FIELD_PACKED; /* in bps */ + uint32_t maxBurstSize FIELD_PACKED; + uint32_t delayBound FIELD_PACKED; + uint32_t minPhyRate FIELD_PACKED; /* in bps */ + uint32_t sba FIELD_PACKED; + uint32_t mediumTime FIELD_PACKED; + uint16_t nominalMSDU FIELD_PACKED; /* in octects */ + uint16_t maxMSDU FIELD_PACKED; /* in octects */ + uint8_t trafficClass FIELD_PACKED; + uint8_t trafficDirection FIELD_PACKED; /* DIR_TYPE */ + uint8_t rxQueueNum FIELD_PACKED; + uint8_t trafficType FIELD_PACKED; /* TRAFFIC_TYPE */ + uint8_t voicePSCapability FIELD_PACKED; /* VOICEPS_CAP_TYPE */ + uint8_t tsid FIELD_PACKED; + uint8_t userPriority FIELD_PACKED; /* 802.1D user priority */ + uint8_t nominalPHY FIELD_PACKED; /* nominal phy rate */ +} POSTPACK WMI_CREATE_PSTREAM_CMD; + +/* + * WMI_DELETE_PSTREAM_CMDID + */ +typedef PREPACK struct +{ + uint8_t txQueueNumber FIELD_PACKED; + uint8_t rxQueueNumber FIELD_PACKED; + uint8_t trafficDirection FIELD_PACKED; + uint8_t trafficClass FIELD_PACKED; + uint8_t tsid FIELD_PACKED; +} POSTPACK WMI_DELETE_PSTREAM_CMD; + +/* + * WMI_SET_CHANNEL_PARAMS_CMDID + */ +typedef enum +{ + WMI_11A_MODE = 0x1, + WMI_11G_MODE = 0x2, + WMI_11AG_MODE = 0x3, + WMI_11B_MODE = 0x4, + WMI_11GONLY_MODE = 0x5 +} WMI_PHY_MODE; + +#define WMI_MAX_CHANNELS 32 + +typedef PREPACK struct +{ + uint8_t reserved1 FIELD_PACKED; + uint8_t scanParam FIELD_PACKED; /* set if enable scan */ + uint8_t phyMode FIELD_PACKED; /* see WMI_PHY_MODE */ + uint8_t numChannels FIELD_PACKED; /* how many channels follow */ + uint16_t channelList[1] FIELD_PACKED; /* channels in Mhz */ +} POSTPACK WMI_CHANNEL_PARAMS_CMD; + +typedef enum +{ + WMI_LPREAMBLE_DISABLED = 0, + WMI_LPREAMBLE_ENABLED +} WMI_LPREAMBLE_STATUS; + +typedef enum +{ + WMI_IGNORE_BARKER_IN_ERP = 0, + WMI_DONOT_IGNORE_BARKER_IN_ERP +} WMI_PREAMBLE_POLICY; + +typedef PREPACK struct +{ + uint16_t threshold FIELD_PACKED; +} POSTPACK WMI_SET_RTS_CMD; + +/* + * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + * Sets the error reporting event bitmask in target. Target clears it + * upon an error. Subsequent errors are counted, but not reported + * via event, unless the bitmask is set again. + */ +typedef PREPACK struct +{ + uint32_t bitmask FIELD_PACKED; +} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; + +/* + * WMI_SET_TX_PWR_CMDID + */ +typedef PREPACK struct +{ + uint8_t dbM FIELD_PACKED; /* in dbM units */ +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; + +/* + * WMI_GET_TX_PWR_CMDID does not take any parameters + */ + +/* + * WMI_SET_ACCESS_PARAMS_CMDID + */ +#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ +#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ +#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ +#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ +#define WMI_DEFAULT_AIFSN_ACPARAM 2 +#define WMI_MAX_AIFSN_ACPARAM 15 +typedef PREPACK struct +{ + uint16_t txop FIELD_PACKED; /* in units of 32 usec */ + uint8_t eCWmin FIELD_PACKED; + uint8_t eCWmax FIELD_PACKED; + uint8_t aifsn FIELD_PACKED; + uint8_t ac FIELD_PACKED; +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD; + +typedef PREPACK struct +{ + uint32_t sleepState FIELD_PACKED; +} WMI_REPORT_SLEEP_STATE_EVENT; + +/* + * Command Replies + */ + +/* + * WMI_GET_CHANNEL_LIST_CMDID reply + */ +typedef PREPACK struct +{ + uint8_t reserved1 FIELD_PACKED; + uint8_t numChannels FIELD_PACKED; /* number of channels in reply */ + uint16_t channelList[1] FIELD_PACKED; /* channel in Mhz */ +} POSTPACK WMI_CHANNEL_LIST_REPLY; + +typedef enum +{ + A_SUCCEEDED = A_OK, + A_FAILED_DELETE_STREAM_DOESNOT_EXIST = 250, + A_SUCCEEDED_MODIFY_STREAM = 251, + A_FAILED_INVALID_STREAM = 252, + A_FAILED_MAX_THINSTREAMS = 253, + A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254 +} PSTREAM_REPLY_STATUS; + +typedef PREPACK struct +{ + uint8_t status FIELD_PACKED; /* PSTREAM_REPLY_STATUS */ + uint8_t txQueueNumber FIELD_PACKED; + uint8_t rxQueueNumber FIELD_PACKED; + uint8_t trafficClass FIELD_PACKED; + uint8_t trafficDirection FIELD_PACKED; /* DIR_TYPE */ +} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct +{ + uint8_t status FIELD_PACKED; /* PSTREAM_REPLY_STATUS */ + uint8_t txQueueNumber FIELD_PACKED; + uint8_t rxQueueNumber FIELD_PACKED; + uint8_t trafficDirection FIELD_PACKED; /* DIR_TYPE */ + uint8_t trafficClass FIELD_PACKED; +} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct +{ + uint32_t tempDegree; + uint8_t tempRegVal; +} POSTPACK WMI_GET_TEMPERATURE_REPLY; + +typedef PREPACK struct +{ + uint32_t status; +} POSTPACK WMI_WLAN_WPS_INIT_KEY_REPLY; + +typedef PREPACK struct +{ + uint8_t country_code[3]; +} POSTPACK WMI_GET_COUNTRY_CODE_REPLY; + +typedef PREPACK struct +{ + uint8_t bssid[ATH_MAC_LEN]; + int8_t bias; +} POSTPACK WMI_BSS_BIAS; + +typedef PREPACK struct +{ + uint8_t numBss; + WMI_BSS_BIAS bssBias[1]; +} POSTPACK WMI_BSS_BIAS_INFO; + +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS +{ + uint16_t lowrssi_scan_period; + int16_t lowrssi_scan_threshold; + int16_t lowrssi_roam_threshold; + uint8_t roam_rssi_floor; + uint8_t reserved[1]; /* For alignment */ +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS; + +typedef PREPACK struct +{ + PREPACK union + { + uint8_t bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ + uint8_t roamMode; /* WMI_SET_ROAM_MODE */ + WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ + uint8_t bias5G; /* WMI_SET_HOST_5G_BIAS */ + WMI_LOWRSSI_SCAN_PARAMS lrScanParams; + } POSTPACK info; + uint8_t roamCtrlType; +} POSTPACK WMI_SET_ROAM_CTRL_CMD; +/* + * List of Events (target to host) + */ +typedef enum +{ + WMI_READY_EVENTID = 0x1001, + WMI_CONNECT_EVENTID = 0x1002, + WMI_DISCONNECT_EVENTID = 0x1003, + WMI_BSSINFO_EVENTID = 0x1004, + WMI_CMDERROR_EVENTID = 0x1005, + WMI_REGDOMAIN_EVENTID = 0x1006, + WMI_PSTREAM_TIMEOUT_EVENTID = 0x1007, + WMI_NEIGHBOR_REPORT_EVENTID = 0x1008, + WMI_TKIP_MICERR_EVENTID = 0x1009, + WMI_SCAN_COMPLETE_EVENTID = 0x100a, /* 0x100a */ + WMI_REPORT_STATISTICS_EVENTID = 0x100b, + WMI_RSSI_THRESHOLD_EVENTID = 0x100c, + WMI_ERROR_REPORT_EVENTID = 0x100d, + WMI_REPORT_ROAM_TBL_EVENTID = 0x100f, + WMI_EXTENSION_EVENTID = 0x1010, + WMI_SNR_THRESHOLD_EVENTID = 0x1012, + WMI_LQ_THRESHOLD_EVENTID = 0x1013, + WMI_TX_RETRY_ERR_EVENTID = 0x1014, /* 0x1014 */ + WMI_REPORT_ROAM_DATA_EVENTID = 0x1015, +#if MANUFACTURING_SUPPORT + WMI_TEST_EVENTID = 0x1016, +#endif + WMI_APLIST_EVENTID = 0x1017, + WMI_GET_PMKID_LIST_EVENTID = 0x1019, + WMI_CHANNEL_CHANGE_EVENTID = 0x101a, + WMI_PEER_NODE_EVENTID = 0x101b, + WMI_DTIMEXPIRY_EVENTID = 0x101d, + WMI_WLAN_VERSION_EVENTID = 0x101e, + WMI_SET_PARAMS_REPLY_EVENTID = 0x101f, + WMI_ADDBA_REQ_EVENTID = 0x1020, /*0x1020 */ + WMI_ADDBA_RESP_EVENTID = 0x1021, + WMI_DELBA_REQ_EVENTID = 0x1022, + WMI_REPORT_SLEEP_STATE_EVENTID = 0x1026, + WMI_GET_PMK_EVENTID = 0x102a, + WMI_SET_CHANNEL_EVENTID = 0x9000, + WMI_RX_PROBE_REQ_EVENTID = 0x900a, + +#if ATH_FIRMWARE_TARGET == TARGET_AR4100_REV2 + WMI_STORERECALL_STORE_EVENTID = 0x9004, + WMI_WPS_GET_STATUS_EVENTID = 0x9005, + WMI_WPS_PROFILE_EVENTID = 0x9006, + WMI_SOCKET_RESPONSE_EVENTID = 0x9007, + + /* P2P Events */ + WMI_P2P_GO_NEG_RESULT_EVENTID = 0x1036, /* 1035 */ + WMI_P2P_INVITE_REQ_EVENTID = 0x103C, + WMI_P2P_INVITE_RCVD_RESULT_EVENTID = 0x103d, + WMI_P2P_INVITE_SENT_RESULT_EVENTID = 0x103e, + WMI_P2P_PROV_DISC_RESP_EVENTID = 0x103f, + WMI_P2P_PROV_DISC_REQ_EVENTID = 0x1040, + WMI_P2P_START_SDPD_EVENTID = 0x1045, + WMI_P2P_SDPD_RX_EVENTID = 0x1046, + WMI_P2P_NODE_LIST_EVENTID = 0x901a, + WMI_P2P_REQ_TO_AUTH_EVENTID = 0x901b, +#elif ATH_FIRMWARE_TARGET == TARGET_AR400X_REV1 + WMI_STORERECALL_STORE_EVENTID = 0x9003, + WMI_WPS_GET_STATUS_EVENTID = 0x900e, + WMI_WPS_PROFILE_EVENTID = 0x900f, + WMI_SOCKET_RESPONSE_EVENTID = 0x9016, + WMI_P2P_GO_NEG_RESULT_EVENTID = 0x1036, + WMI_P2P_INVITE_REQ_EVENTID = 0x103E, + WMI_P2P_INVITE_RCVD_RESULT_EVENTID = 0x103F, + WMI_P2P_INVITE_SENT_RESULT_EVENTID = 0x1040, + WMI_P2P_PROV_DISC_RESP_EVENTID = 0x1041, + WMI_P2P_PROV_DISC_REQ_EVENTID = 0x1042, + WMI_P2P_START_SDPD_EVENTID = 0x1045, + WMI_P2P_SDPD_RX_EVENTID = 0x1046, + WMI_P2P_NODE_LIST_EVENTID = 0x901a, + WMI_P2P_REQ_TO_AUTH_EVENTID = 0x901b, + WMI_P2P_LIST_PERSISTENT_NETWORK_EVENTID = 0x9030, + +#endif + WMI_ARGOS_EVENTID = 0x901f, + WMI_HOST_DSET_STORE_EVENTID = 0x9031, + WMI_HOST_DSET_READ_EVENTID = 0x9032, + WMI_STORERECALL_START_EVENTID = 0x9033, + WMI_HOST_DSET_CREATE_EVENTID = 0x9038, + WMI_HOST_DSET_LARGE_WRITE_EVENTID = 0x9039, + WMI_HOST_DSET_LARGE_READ_EVENTID = 0x903A, + WMI_HOST_DSET_SYNC_EVENTID = 0x903B, + + WMI_DSET_OP_EVENTID = 0x903C, + WMI_GET_TEMPERATURE_REPLY_EVENTID = 0x903D, + WMI_PARAM_SET_REPLY_EVENTID = 0x903E, + WMI_GET_COUNTRY_CODE_REPLY_EVENTID = 0x9040, + WMI_WLAN_WPS_INIT_KEY_EVENTID = 0x9041, +} WMI_EVENT_ID; + +#if ENABLE_P2P_MODE +#define P2P_EVT_BUF_SIZE 512 +typedef PREPACK struct +{ + uint32_t EVENT_ID FIELD_PACKED; + uint8_t data[P2P_EVT_BUF_SIZE] FIELD_PACKED; +} POSTPACK WMI_EVT_TO_APP; +#endif + +typedef struct +{ + uint8_t pwr_module; + boolean pwr_mode; +} POWER_MODE; + +typedef enum +{ + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, + WMI_11NA_CAPABILITY = 4, + WMI_11NG_CAPABILITY = 5, + WMI_11NAG_CAPABILITY = 6, + // END CAPABILITY + WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY) +} WMI_PHY_CAPABILITY; + +typedef PREPACK struct +{ + uint8_t macaddr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t phyCapability FIELD_PACKED; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_1; + +typedef PREPACK struct +{ + uint32_t sw_version FIELD_PACKED; + uint32_t abi_version FIELD_PACKED; + uint8_t macaddr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t phyCapability FIELD_PACKED; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_2; + +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ + +typedef PREPACK struct +{ + uint32_t freq; + uint16_t len; + uint8_t data[1]; +} POSTPACK WMI_P2P_RX_PROBE_REQ_EVENT_STRUCT; + +/* + * Connect Event + */ +typedef PREPACK struct +{ + uint16_t channel FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint16_t listenInterval FIELD_PACKED; + uint16_t beaconInterval FIELD_PACKED; + uint32_t networkType FIELD_PACKED; + uint8_t beaconIeLen FIELD_PACKED; + uint8_t assocReqLen FIELD_PACKED; + uint8_t assocRespLen FIELD_PACKED; + uint8_t assocInfo[1] FIELD_PACKED; +} POSTPACK WMI_CONNECT_EVENT; + +/* + * Disconnect Event + */ +typedef enum +{ + NO_NETWORK_AVAIL = 0x01, + LOST_LINK = 0x02, /* bmiss */ + DISCONNECT_CMD = 0x03, + BSS_DISCONNECTED = 0x04, + AUTH_FAILED = 0x05, + ASSOC_FAILED = 0x06, + NO_RESOURCES_AVAIL = 0x07, + CSERV_DISCONNECT = 0x08, + INVALID_PROFILE = 0x0a, + DOT11H_CHANNEL_SWITCH = 0x0b, + PROFILE_MISMATCH = 0x0c, + CONNECTION_EVICTED = 0x0d, + IBSS_MERGE = 0xe +} WMI_DISCONNECT_REASON; + +typedef PREPACK struct +{ + uint16_t protocolReasonStatus FIELD_PACKED; /* reason code, see 802.11 spec. */ + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; /* set if known */ + uint8_t disconnectReason FIELD_PACKED; /* see WMI_DISCONNECT_REASON */ + uint8_t assocRespLen FIELD_PACKED; + uint8_t assocInfo[1] FIELD_PACKED; +} POSTPACK WMI_DISCONNECT_EVENT; + +/* + * BSS Info Event. + * Mechanism used to inform host of the presence and characteristic of + * wireless networks present. Consists of bss info header followed by + * the beacon or probe-response frame body. The 802.11 header is not included. + */ +typedef enum +{ + BEACON_FTYPE = 0x1, + PROBERESP_FTYPE, + ACTION_MGMT_FTYPE, + PROBEREQ_FTYPE +} WMI_BI_FTYPE; + +enum +{ + BSS_ELEMID_CHANSWITCH = 0x01, + BSS_ELEMID_ATHEROS = 0x02 +}; + +typedef PREPACK struct +{ + uint16_t channel FIELD_PACKED; + uint8_t frameType FIELD_PACKED; /* see WMI_BI_FTYPE */ + uint8_t snr FIELD_PACKED; + int16_t rssi FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint32_t ieMask FIELD_PACKED; +} POSTPACK WMI_BSS_INFO_HDR; + +/* + * BSS INFO HDR version 2.0 + * With 6 bytes HTC header and 6 bytes of WMI header + * WMI_BSS_INFO_HDR cannot be accomodated in the removed 802.11 management + * header space. + * - Reduce the ieMask to 2 bytes as only two bit flags are used + * - Remove rssi and compute it on the host. rssi = snr - 95 + */ +typedef PREPACK struct +{ + uint16_t channel FIELD_PACKED; + uint8_t frameType FIELD_PACKED; /* see WMI_BI_FTYPE */ + uint8_t snr FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint16_t ieMask FIELD_PACKED; +} POSTPACK WMI_BSS_INFO_HDR2; + +/* + * Command Error Event + */ +typedef enum +{ + INVALID_PARAM = 0x01, + ILLEGAL_STATE = 0x02, + INTERNAL_ERROR = 0x03, + STACK_ERROR = 0x04 +} WMI_ERROR_CODE; + +typedef PREPACK struct +{ + uint16_t commandId FIELD_PACKED; + uint8_t errorCode FIELD_PACKED; +} POSTPACK WMI_CMD_ERROR_EVENT; + +/* + * New Regulatory Domain Event + */ +typedef PREPACK struct +{ + uint32_t regDomain FIELD_PACKED; +} POSTPACK WMI_REG_DOMAIN_EVENT; + +typedef PREPACK struct +{ + uint8_t txQueueNumber FIELD_PACKED; + uint8_t rxQueueNumber FIELD_PACKED; + uint8_t trafficDirection FIELD_PACKED; + uint8_t trafficClass FIELD_PACKED; +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; + +/* + * TKIP MIC Error Event + */ +typedef PREPACK struct +{ + uint8_t keyid FIELD_PACKED; + uint8_t ismcast FIELD_PACKED; +} POSTPACK WMI_TKIP_MICERR_EVENT; + +/* + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) + */ +typedef PREPACK struct +{ + int32_t status FIELD_PACKED; +} POSTPACK WMI_SCAN_COMPLETE_EVENT; + +#define MAX_OPT_DATA_LEN 1400 + +/* + * Reporting statistics. + */ +typedef PREPACK struct +{ + uint32_t tx_packets FIELD_PACKED; + uint32_t tx_bytes FIELD_PACKED; + uint32_t tx_unicast_pkts FIELD_PACKED; + uint32_t tx_unicast_bytes FIELD_PACKED; + uint32_t tx_multicast_pkts FIELD_PACKED; + uint32_t tx_multicast_bytes FIELD_PACKED; + uint32_t tx_broadcast_pkts FIELD_PACKED; + uint32_t tx_broadcast_bytes FIELD_PACKED; + uint32_t tx_rts_success_cnt FIELD_PACKED; + uint32_t tx_packet_per_ac[4] FIELD_PACKED; + uint32_t tx_errors_per_ac[4] FIELD_PACKED; + + uint32_t tx_errors FIELD_PACKED; + uint32_t tx_failed_cnt FIELD_PACKED; + uint32_t tx_retry_cnt FIELD_PACKED; + uint32_t tx_mult_retry_cnt FIELD_PACKED; + uint32_t tx_rts_fail_cnt FIELD_PACKED; + int32_t tx_unicast_rate FIELD_PACKED; +} POSTPACK tx_stats_t; + +typedef PREPACK struct +{ + uint32_t rx_packets FIELD_PACKED; + uint32_t rx_bytes FIELD_PACKED; + uint32_t rx_unicast_pkts FIELD_PACKED; + uint32_t rx_unicast_bytes FIELD_PACKED; + uint32_t rx_multicast_pkts FIELD_PACKED; + uint32_t rx_multicast_bytes FIELD_PACKED; + uint32_t rx_broadcast_pkts FIELD_PACKED; + uint32_t rx_broadcast_bytes FIELD_PACKED; + uint32_t rx_fragment_pkt FIELD_PACKED; + + uint32_t rx_errors FIELD_PACKED; + uint32_t rx_crcerr FIELD_PACKED; + uint32_t rx_key_cache_miss FIELD_PACKED; + uint32_t rx_decrypt_err FIELD_PACKED; + uint32_t rx_duplicate_frames FIELD_PACKED; + int32_t rx_unicast_rate FIELD_PACKED; +} POSTPACK rx_stats_t; + +typedef PREPACK struct +{ + uint32_t tkip_local_mic_failure FIELD_PACKED; + uint32_t tkip_counter_measures_invoked FIELD_PACKED; + uint32_t tkip_replays FIELD_PACKED; + uint32_t tkip_format_errors FIELD_PACKED; + uint32_t ccmp_format_errors FIELD_PACKED; + uint32_t ccmp_replays FIELD_PACKED; +} POSTPACK tkip_ccmp_stats_t FIELD_PACKED; + +typedef PREPACK struct +{ + uint32_t power_save_failure_cnt FIELD_PACKED; + uint16_t stop_tx_failure_cnt FIELD_PACKED; + uint16_t atim_tx_failure_cnt FIELD_PACKED; + uint16_t atim_rx_failure_cnt FIELD_PACKED; + uint16_t bcn_rx_failure_cnt FIELD_PACKED; +} POSTPACK pm_stats_t; + +typedef PREPACK struct +{ + uint32_t cs_bmiss_cnt FIELD_PACKED; + uint32_t cs_lowRssi_cnt FIELD_PACKED; + uint16_t cs_connect_cnt FIELD_PACKED; + uint16_t cs_disconnect_cnt FIELD_PACKED; + int16_t cs_aveBeacon_rssi FIELD_PACKED; + uint16_t cs_roam_count FIELD_PACKED; + int16_t cs_rssi FIELD_PACKED; + uint8_t cs_snr FIELD_PACKED; + uint8_t cs_aveBeacon_snr FIELD_PACKED; + uint8_t cs_lastRoam_msec FIELD_PACKED; +} POSTPACK cserv_stats_t; + +typedef PREPACK struct +{ + tx_stats_t tx_stats FIELD_PACKED; + rx_stats_t rx_stats FIELD_PACKED; + tkip_ccmp_stats_t tkipCcmpStats FIELD_PACKED; +} POSTPACK wlan_net_stats_t; + +typedef PREPACK struct +{ + uint32_t arp_received FIELD_PACKED; + uint32_t arp_matched FIELD_PACKED; + uint32_t arp_replied FIELD_PACKED; +} POSTPACK arp_stats_t; + +typedef PREPACK struct +{ + uint32_t wow_num_pkts_dropped FIELD_PACKED; + uint16_t wow_num_events_discarded FIELD_PACKED; + uint8_t wow_num_host_pkt_wakeups FIELD_PACKED; + uint8_t wow_num_host_event_wakeups FIELD_PACKED; +} POSTPACK wlan_wow_stats_t; + +typedef PREPACK struct +{ + uint32_t lqVal FIELD_PACKED; + int32_t noise_floor_calibation FIELD_PACKED; + pm_stats_t pmStats FIELD_PACKED; + wlan_net_stats_t txrxStats FIELD_PACKED; + wlan_wow_stats_t wowStats FIELD_PACKED; + arp_stats_t arpStats FIELD_PACKED; + cserv_stats_t cservStats FIELD_PACKED; +} POSTPACK WMI_TARGET_STATS; + +/* + * WMI_ERROR_REPORT_EVENTID + */ +typedef enum +{ + WMI_TARGET_PM_ERR_FAIL = 0x00000001, + WMI_TARGET_KEY_NOT_FOUND = 0x00000002, + WMI_TARGET_DECRYPTION_ERR = 0x00000004, + WMI_TARGET_BMISS = 0x00000008, + WMI_PSDISABLE_NODE_JOIN = 0x00000010, + WMI_TARGET_COM_ERR = 0x00000020, + WMI_TARGET_FATAL_ERR = 0x00000040 +} WMI_TARGET_ERROR_VAL; + +typedef PREPACK struct +{ + uint32_t errorVal FIELD_PACKED; +} POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; + +typedef PREPACK struct +{ + uint8_t retrys FIELD_PACKED; +} POSTPACK WMI_TX_RETRY_ERR_EVENT; + +/* + * developer commands + */ + +#if 1 +static const int32_t wmi_rateTable[][2] = { + //{W/O SGI, with SGI} + {1000, 1000}, {2000, 2000}, {5500, 5500}, {11000, 11000}, {6000, 6000}, {9000, 9000}, + {12000, 12000}, {18000, 18000}, {24000, 24000}, {36000, 36000}, {48000, 48000}, {54000, 54000}, + {6500, 7200}, {13000, 14400}, {19500, 21700}, {26000, 28900}, {39000, 43300}, {52000, 57800}, + {58500, 65000}, {65000, 72200}, {13500, 15000}, {27500, 30000}, {40500, 45000}, {54000, 60000}, + {81500, 90000}, {108000, 120000}, {121500, 135000}, {135000, 150000}}; +#endif + +/* + * WMI_SET_BITRATE_CMDID + * + * Get bit rate cmd uses same definition as set bit rate cmd + */ +typedef enum +{ + RATE_AUTO = -1, + RATE_1Mb = 0, + RATE_2Mb = 1, + RATE_5_5Mb = 2, + RATE_11Mb = 3, + RATE_6Mb = 4, + RATE_9Mb = 5, + RATE_12Mb = 6, + RATE_18Mb = 7, + RATE_24Mb = 8, + RATE_36Mb = 9, + RATE_48Mb = 10, + RATE_54Mb = 11, + RATE_MCS_0_20 = 12, + RATE_MCS_1_20 = 13, + RATE_MCS_2_20 = 14, + RATE_MCS_3_20 = 15, + RATE_MCS_4_20 = 16, + RATE_MCS_5_20 = 17, + RATE_MCS_6_20 = 18, + RATE_MCS_7_20 = 19, + RATE_MCS_0_40 = 20, + RATE_MCS_1_40 = 21, + RATE_MCS_2_40 = 22, + RATE_MCS_3_40 = 23, + RATE_MCS_4_40 = 24, + RATE_MCS_5_40 = 25, + RATE_MCS_6_40 = 26, + RATE_MCS_7_40 = 27 +} WMI_BIT_RATE; + +typedef PREPACK struct +{ + int8_t rateIndex FIELD_PACKED; /* see WMI_BIT_RATE */ + int8_t mgmtRateIndex FIELD_PACKED; + int8_t ctlRateIndex FIELD_PACKED; +} POSTPACK WMI_BIT_RATE_CMD; + +typedef PREPACK struct +{ + int8_t rateIndex FIELD_PACKED; /* see WMI_BIT_RATE */ +} POSTPACK WMI_BIT_RATE_REPLY; + +/* + * WMI_SET_FIXRATES_CMDID + * + * Get fix rates cmd uses same definition as set fix rates cmd + */ +#define FIX_RATE_1Mb ((uint32_t)0x1) +#define FIX_RATE_2Mb ((uint32_t)0x2) +#define FIX_RATE_5_5Mb ((uint32_t)0x4) +#define FIX_RATE_11Mb ((uint32_t)0x8) +#define FIX_RATE_6Mb ((uint32_t)0x10) +#define FIX_RATE_9Mb ((uint32_t)0x20) +#define FIX_RATE_12Mb ((uint32_t)0x40) +#define FIX_RATE_18Mb ((uint32_t)0x80) +#define FIX_RATE_24Mb ((uint32_t)0x100) +#define FIX_RATE_36Mb ((uint32_t)0x200) +#define FIX_RATE_48Mb ((uint32_t)0x400) +#define FIX_RATE_54Mb ((uint32_t)0x800) +#define FIX_RATE_MCS_0_20 ((uint32_t)0x1000) +#define FIX_RATE_MCS_1_20 ((uint32_t)0x2000) +#define FIX_RATE_MCS_2_20 ((uint32_t)0x4000) +#define FIX_RATE_MCS_3_20 ((uint32_t)0x8000) +#define FIX_RATE_MCS_4_20 ((uint32_t)0x10000) +#define FIX_RATE_MCS_5_20 ((uint32_t)0x20000) +#define FIX_RATE_MCS_6_20 ((uint32_t)0x40000) +#define FIX_RATE_MCS_7_20 ((uint32_t)0x80000) +#define FIX_RATE_MCS_0_40 ((uint32_t)0x100000) +#define FIX_RATE_MCS_1_40 ((uint32_t)0x200000) +#define FIX_RATE_MCS_2_40 ((uint32_t)0x400000) +#define FIX_RATE_MCS_3_40 ((uint32_t)0x800000) +#define FIX_RATE_MCS_4_40 ((uint32_t)0x1000000) +#define FIX_RATE_MCS_5_40 ((uint32_t)0x2000000) +#define FIX_RATE_MCS_6_40 ((uint32_t)0x4000000) +#define FIX_RATE_MCS_7_40 ((uint32_t)0x8000000) + +typedef enum +{ + WMI_WMM_DISABLED = 0, + WMI_WMM_ENABLED +} WMI_WMM_STATUS; + +typedef PREPACK struct +{ + uint8_t status FIELD_PACKED; +} POSTPACK WMI_SET_WMM_CMD; + +typedef PREPACK struct +{ + uint8_t status FIELD_PACKED; +} POSTPACK WMI_SET_QOS_SUPP_CMD; + +typedef enum +{ + WMI_TXOP_DISABLED = 0, + WMI_TXOP_ENABLED +} WMI_TXOP_CFG; + +typedef PREPACK struct +{ + uint8_t txopEnable FIELD_PACKED; +} POSTPACK WMI_SET_WMM_TXOP_CMD; + +typedef PREPACK struct +{ + uint8_t keepaliveInterval FIELD_PACKED; +} POSTPACK WMI_SET_KEEPALIVE_CMD; + +typedef PREPACK struct +{ + boolean configured FIELD_PACKED; + uint8_t keepaliveInterval FIELD_PACKED; +} POSTPACK WMI_GET_KEEPALIVE_CMD; + +/* + * Add Application specified IE to a management frame + */ +#define WMI_MAX_IE_LEN 64 + +typedef PREPACK struct { + uint8_t mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ + uint8_t ieLen; /* Length of the IE that should be added to the MGMT frame */ + uint8_t ieInfo[1]; +} POSTPACK WMI_SET_APPIE_CMD; + +typedef PREPACK struct +{ + uint16_t oldChannel FIELD_PACKED; + uint32_t newChannel FIELD_PACKED; +} POSTPACK WMI_CHANNEL_CHANGE_EVENT; + +typedef PREPACK struct +{ + uint32_t version FIELD_PACKED; +} POSTPACK WMI_WLAN_VERSION_EVENT; + +/* WMI_ADDBA_REQ_EVENTID */ +typedef PREPACK struct +{ + uint8_t tid FIELD_PACKED; + uint8_t win_sz FIELD_PACKED; + uint16_t st_seq_no FIELD_PACKED; + uint8_t status FIELD_PACKED; /* f/w response for ADDBA Req; OK(0) or failure(!=0) */ +} POSTPACK WMI_ADDBA_REQ_EVENT; + +/* WMI_ADDBA_RESP_EVENTID */ +typedef PREPACK struct +{ + uint8_t tid FIELD_PACKED; + uint8_t status FIELD_PACKED; /* OK(0), failure (!=0) */ + uint16_t amsdu_sz FIELD_PACKED; /* Three values: Not supported(0), 3839, 8k */ +} POSTPACK WMI_ADDBA_RESP_EVENT; + +/* WMI_DELBA_EVENTID + * f/w received a DELBA for peer and processed it. + * Host is notified of this + */ +typedef PREPACK struct +{ + uint8_t tid FIELD_PACKED; + uint8_t is_peer_initiator FIELD_PACKED; + uint16_t reason_code FIELD_PACKED; +} POSTPACK WMI_DELBA_EVENT; + +/* WMI_ALLOW_AGGR_CMDID + * Configures tid's to allow ADDBA negotiations + * on each tid, in each direction + */ +typedef PREPACK struct +{ + uint16_t tx_allow_aggr FIELD_PACKED; /* 16-bit mask to allow uplink ADDBA negotiation - bit position indicates tid*/ + uint16_t rx_allow_aggr + FIELD_PACKED; /* 16-bit mask to allow donwlink ADDBA negotiation - bit position indicates tid*/ +} POSTPACK WMI_ALLOW_AGGR_CMD; + +/* WMI_ADDBA_REQ_CMDID + * f/w starts performing ADDBA negotiations with peer + * on the given tid + */ +typedef PREPACK struct +{ + uint8_t tid FIELD_PACKED; +} POSTPACK WMI_ADDBA_REQ_CMD; + +/* WMI_DELBA_REQ_CMDID + * f/w would teardown BA with peer. + * is_send_initiator indicates if it's or tx or rx side + */ +typedef PREPACK struct +{ + uint8_t tid FIELD_PACKED; + uint8_t is_sender_initiator FIELD_PACKED; + +} POSTPACK WMI_DELBA_REQ_CMD; + +#define PEER_NODE_JOIN_EVENT 0x00 +#define PEER_NODE_LEAVE_EVENT 0x01 +#define PEER_FIRST_NODE_JOIN_EVENT 0x10 +#define PEER_LAST_NODE_LEAVE_EVENT 0x11 +typedef PREPACK struct +{ + uint8_t eventCode FIELD_PACKED; + uint8_t peerMacAddr[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_PEER_NODE_EVENT; + +#define IEEE80211_FRAME_TYPE_MGT 0x00 +#define IEEE80211_FRAME_TYPE_CTL 0x04 + +typedef PREPACK struct +{ + uint8_t band FIELD_PACKED; /* specifies which band to apply these values */ + uint8_t enable FIELD_PACKED; /* allows 11n to be disabled on a per band basis */ + uint8_t chan_width_40M_supported FIELD_PACKED; + uint8_t short_GI_20MHz FIELD_PACKED; + uint8_t short_GI_40MHz FIELD_PACKED; + uint8_t intolerance_40MHz FIELD_PACKED; + uint8_t max_ampdu_len_exp FIELD_PACKED; +} POSTPACK WMI_SET_HT_CAP_CMD; + +typedef PREPACK struct +{ + uint8_t sta_chan_width FIELD_PACKED; +} POSTPACK WMI_SET_HT_OP_CMD; + +typedef PREPACK struct +{ + uint8_t metaVersion FIELD_PACKED; /* version of meta data for rx packets <0 = default> (0-7 = valid) */ + uint8_t dot11Hdr FIELD_PACKED; /* 1 == leave .11 header intact , 0 == replace .11 header with .3 */ + uint8_t defragOnHost + FIELD_PACKED; /* 1 == defragmentation is performed by host, 0 == performed by target */ + uint8_t reserved[1] FIELD_PACKED; /* alignment */ +} POSTPACK WMI_RX_FRAME_FORMAT_CMD; + +/* STORE / RECALL Commands AND Events DEFINITION START */ + +#define DSET_STORE_RECALL_START 0x00000900 +#define DSET_STORE_RECALL_END 0x000009FF + +#define IS_STRRCL_DSET(a) (((a) >= DSET_STORE_RECALL_START) && ((a) <= DSET_STORE_RECALL_END)) + +typedef PREPACK struct +{ + uint8_t enable FIELD_PACKED; +#define STRRCL_RECIPIENT_HOST 1 + uint8_t recipient FIELD_PACKED; +} POSTPACK WMI_STORERECALL_CONFIGURE_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* number of bytes of data to follow */ + uint32_t length FIELD_PACKED; /* start of data */ +} POSTPACK WMI_STORERECALL_RECALL_DSET; + +typedef PREPACK struct +{ + uint32_t length FIELD_PACKED; /* number of bytes of data to follow */ + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_STORERECALL_RECALL_CMD; + +typedef PREPACK struct +{ + uint32_t sleep_msec FIELD_PACKED; + uint8_t store_after_tx_empty FIELD_PACKED; + uint8_t store_after_fresh_beacon_rx FIELD_PACKED; +} POSTPACK WMI_STORERECALL_HOST_READY_CMD; + +typedef PREPACK struct +{ + uint32_t msec_sleep FIELD_PACKED; /* time between power off/on */ + uint32_t length FIELD_PACKED; /* length of following data */ + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_STORERECALL_STORE_EVENT; + +typedef PREPACK struct +{ + uint32_t length FIELD_PACKED; /* length of following data */ + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_HOST_DSET_STORE_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* length of following data */ + uint32_t length FIELD_PACKED; /* length of following data */ +} POSTPACK WMI_HOST_DSET_CREATE_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* length of following data */ + uint32_t offset FIELD_PACKED; /* length of following data */ + uint32_t length FIELD_PACKED; /* length of following data */ + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_HOST_DSET_WRITE_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* length of following data */ + uint32_t offset FIELD_PACKED; /* length of following data */ + uint32_t length FIELD_PACKED; /* length of following data */ +} POSTPACK WMI_HOST_DSET_READBACK_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_count FIELD_PACKED; /* length of following data */ +} POSTPACK WMI_HOST_DSET_SYNC_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* dset_id */ + uint32_t status FIELD_PACKED; /* status */ +} POSTPACK WMI_DSET_OP_CREATE_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* dset_id */ + uint32_t status FIELD_PACKED; /* status */ +} POSTPACK WMI_DSET_OP_OPEN_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* dset_id */ + uint32_t status FIELD_PACKED; /* status */ + uint32_t offset FIELD_PACKED; /* status */ + uint32_t length FIELD_PACKED; /* status */ + uint8_t data[1]; +} POSTPACK WMI_DSET_OP_READ_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* dset_id */ + uint32_t status FIELD_PACKED; /* status */ +} POSTPACK WMI_DSET_OP_WRITE_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* dset_id */ + uint32_t status FIELD_PACKED; /* status */ +} POSTPACK WMI_DSET_OP_COMMIT_EVENT; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* dset_id */ + uint32_t status FIELD_PACKED; /* status */ +} POSTPACK WMI_DSET_OP_CLOSE_EVENT; + +typedef PREPACK struct +{ + uint32_t length FIELD_PACKED; /* number of bytes of data to follow */ + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_STORERECALL_READ_CMD; + +typedef PREPACK struct +{ + uint32_t dset_count FIELD_PACKED; /* number of bytes of data to follow */ + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_HOST_DSET_SYNC_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* length of following data */ + uint32_t length FIELD_PACKED; /* length of following data */ + uint32_t offset FIELD_PACKED; /* length of following data */ + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_HOST_DSET_READBACK_CMD; + +typedef PREPACK struct +{ + uint32_t flags FIELD_PACKED; /* number of bytes of data to follow */ +} POSTPACK WMI_HOST_DSET_RESP_CREATE_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; /* length of following data */ + uint32_t offset FIELD_PACKED; /* length of following data */ + uint32_t length FIELD_PACKED; /* length of following data */ +} POSTPACK WMI_HOST_DSET_RESP_WRITE_CMD; + +typedef PREPACK struct +{ + uint32_t msec_sleep FIELD_PACKED; /* time between power off/on */ +} POSTPACK WMI_STORERECALL_START_EVENT; + +/* STORE / RECALL Commands AND Events DEFINITION END */ +/* WPS Commands AND Events DEFINITION START */ + +typedef PREPACK struct +{ + uint8_t ssid[WMI_MAX_SSID_LEN] FIELD_PACKED; + uint8_t macaddress[ATH_MAC_LEN] FIELD_PACKED; + uint16_t channel FIELD_PACKED; + uint8_t ssid_len FIELD_PACKED; +} POSTPACK WPS_SCAN_LIST_ENTRY; + +typedef enum +{ + WPS_REGISTRAR_ROLE = 0x1, + WPS_ENROLLEE_ROLE = 0x2, + WPS_AP_ENROLLEE_ROLE = 0x3 +} WPS_OPER_MODE; + +typedef enum +{ + WPS_DO_CONNECT_AFTER_CRED_RECVD = 0x1 +} WPS_START_CTRL_FLAG; + +#define WPS_PIN_LEN (8) + +typedef PREPACK struct +{ + uint8_t pin[WPS_PIN_LEN + 1] FIELD_PACKED; + uint8_t pin_length FIELD_PACKED; +} POSTPACK WPS_PIN; + +typedef enum +{ + WPS_PIN_MODE = 0x1, + WPS_PBC_MODE = 0x2 +} WPS_MODE; + +typedef PREPACK struct +{ + WPS_SCAN_LIST_ENTRY ssid_info FIELD_PACKED; + uint8_t config_mode FIELD_PACKED; /* WPS_MODE */ + WPS_PIN wps_pin FIELD_PACKED; + uint8_t timeout FIELD_PACKED; /* in Seconds */ + uint8_t role FIELD_PACKED; /* WPS_OPER_MOD */ + uint8_t ctl_flag FIELD_PACKED; /* WPS_START_CTRL_FLAG */ +} POSTPACK WMI_WPS_START_CMD; + +typedef enum +{ + WPS_STATUS_SUCCESS = 0x0, + WPS_STATUS_FAILURE = 0x1, + WPS_STATUS_IDLE = 0x2, + WPS_STATUS_IN_PROGRESS = 0x3 +} WPS_STATUS; + +typedef PREPACK struct +{ + uint8_t wps_status FIELD_PACKED; /* WPS_STATUS */ + uint8_t wps_state FIELD_PACKED; +} POSTPACK WMI_WPS_GET_STATUS_EVENT; + +typedef enum +{ + WPS_ERROR_INVALID_START_INFO = 0x1, + WPS_ERROR_MULTIPLE_PBC_SESSIONS, + WPS_ERROR_WALKTIMER_TIMEOUT, + WPS_ERROR_M2D_RCVD, + WPS_ERROR_PWD_AUTH_FAIL, + WPS_ERROR_CANCELLED, + WPS_ERROR_INVALID_PIN +} WPS_ERROR_CODE; + +/* Authentication Type Flags */ +#define WPS_CRED_AUTH_OPEN 0x0001 +#define WPS_CRED_AUTH_WPAPSK 0x0002 +#define WPS_CRED_AUTH_SHARED 0x0004 +#define WPS_CRED_AUTH_WPA 0x0008 +#define WPS_CRED_AUTH_WPA2 0x0010 +#define WPS_CRED_AUTH_WPA2PSK 0x0020 + +/* Encryption Type Flags */ +#define WPS_CRED_ENCR_NONE 0x0001 +#define WPS_CRED_ENCR_WEP 0x0002 +#define WPS_CRED_ENCR_TKIP 0x0004 +#define WPS_CRED_ENCR_AES 0x0008 + +typedef PREPACK struct +{ + uint16_t ap_channel FIELD_PACKED; + uint8_t ssid[WMI_MAX_SSID_LEN] FIELD_PACKED; + uint8_t ssid_len FIELD_PACKED; + uint16_t auth_type FIELD_PACKED; + uint16_t encr_type FIELD_PACKED; + uint8_t key_idx FIELD_PACKED; + uint8_t key[64] FIELD_PACKED; + uint8_t key_len FIELD_PACKED; + uint8_t mac_addr[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WPS_CREDENTIAL; + +typedef PREPACK struct +{ + uint8_t status FIELD_PACKED; /* WPS_STATUS */ + uint8_t error_code FIELD_PACKED; /* WPS_ERROR_CODE */ + WPS_CREDENTIAL credential FIELD_PACKED; + uint8_t peer_dev_addr[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_WPS_PROFILE_EVENT; +/* WPS Commands AND Events DEFINITION END */ + +typedef PREPACK struct +{ + uint8_t enable FIELD_PACKED; /* 1 == device operates in promiscuous mode , 0 == normal mode */ +#define WMI_PROM_FILTER_SRC_ADDR 0x01 +#define WMI_PROM_FILTER_DST_ADDR 0x02 + uint8_t filters FIELD_PACKED; + uint8_t srcAddr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t dstAddr[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_SET_FILTERED_PROMISCUOUS_MODE_CMD; + +typedef PREPACK struct +{ + uint16_t channel FIELD_PACKED; /* frequency in Mhz */ +} POSTPACK WMI_SET_CHANNEL_CMD; + +typedef PREPACK struct +{ + uint32_t cmd_type FIELD_PACKED; /*Socket command type*/ + uint32_t length FIELD_PACKED; /* number of bytes of data to follow */ + // uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_SOCKET_CMD; + +typedef PREPACK struct +{ + uint32_t resp_type FIELD_PACKED; /*Socket command response type*/ + uint32_t sock_handle FIELD_PACKED; /*Socket handle*/ + uint32_t error FIELD_PACKED; /*Return value*/ + uint8_t data[1] FIELD_PACKED; /*data for socket command e.g. select FDs*/ +} POSTPACK WMI_SOCK_RESPONSE_EVENT; + +#if ENABLE_P2P_MODE + +typedef PREPACK struct +{ + uint8_t flag FIELD_PACKED; +} POSTPACK WMI_P2P_SET_CONCURRENT_MODE; + +typedef PREPACK struct +{ + uint8_t value FIELD_PACKED; +} POSTPACK WMI_P2P_SET_GO_INTENT; + +typedef PREPACK struct +{ + uint8_t enable FIELD_PACKED; +} POSTPACK WMI_P2P_SET_CCK_RATES; + +typedef PREPACK struct +{ + uint8_t go_intent FIELD_PACKED; + uint8_t reserved[3] FIELD_PACKED; /* Deprecated 'country' field */ + uint8_t reg_class FIELD_PACKED; + uint8_t listen_channel FIELD_PACKED; + uint8_t op_reg_class FIELD_PACKED; + uint8_t op_channel FIELD_PACKED; + uint32_t node_age_to FIELD_PACKED; + uint8_t max_node_count FIELD_PACKED; +} POSTPACK WMI_P2P_FW_SET_CONFIG_CMD; + +typedef PREPACK struct +{ + uint8_t enable FIELD_PACKED; +} POSTPACK WMI_P2P_SET_PROFILE_CMD; + +typedef PREPACK struct +{ + uint16_t categ FIELD_PACKED; + uint16_t sub_categ FIELD_PACKED; +} POSTPACK device_type_tuple; + +typedef PREPACK struct +{ + device_type_tuple pri_dev_type FIELD_PACKED; + uint8_t pri_device_type[8] FIELD_PACKED; +#define MAX_P2P_SEC_DEVICE_TYPES 5 + device_type_tuple sec_dev_type[MAX_P2P_SEC_DEVICE_TYPES] FIELD_PACKED; +#define WPS_UUID_LEN 16 + uint8_t uuid[WPS_UUID_LEN] FIELD_PACKED; +#define WPS_MAX_DEVNAME_LEN 32 + uint8_t device_name[WPS_MAX_DEVNAME_LEN] FIELD_PACKED; + uint8_t dev_name_len FIELD_PACKED; +} POSTPACK WMI_WPS_SET_CONFIG_CMD; + +typedef PREPACK struct +{ + device_type_tuple pri_dev_type FIELD_PACKED; + device_type_tuple sec_dev_type[MAX_P2P_SEC_DEVICE_TYPES] FIELD_PACKED; + uint8_t device_addr[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_SET_REQ_DEV_ATTR_CMD; + +#define MAX_LIST_COUNT 8 +#define MAX_PASS_LEN 32 + +typedef PREPACK struct +{ + uint8_t data[1]; +} POSTPACK WMI_P2P_PERSISTENT_LIST_NETWORK_EVENT; + +typedef PREPACK struct +{ + uint8_t role; + uint8_t macaddr[ATH_MAC_LEN]; + uint8_t ssid[WMI_MAX_SSID_LEN]; + uint8_t passphrase[MAX_PASS_LEN]; +} POSTPACK WMI_PERSISTENT_MAC_LIST; + +typedef PREPACK struct +{ + uint8_t ssidLength FIELD_PACKED; + uint8_t ssid[WMI_MAX_SSID_LEN] FIELD_PACKED; +} POSTPACK P2P_SSID; + +typedef enum wmi_p2p_discovery_type +{ + WMI_P2P_FIND_START_WITH_FULL, + WMI_P2P_FIND_ONLY_SOCIAL, + WMI_P2P_FIND_PROGRESSIVE +} WMI_P2P_DISC_TYPE; + +typedef PREPACK struct +{ + uint32_t timeout FIELD_PACKED; + uint8_t type FIELD_PACKED; +} POSTPACK WMI_P2P_FIND_CMD; + +typedef PREPACK struct +{ + uint16_t listen_freq FIELD_PACKED; + uint16_t force_freq FIELD_PACKED; + uint16_t go_oper_freq FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t peer_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t own_interface_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t member_in_go_dev[ATH_MAC_LEN] FIELD_PACKED; + uint8_t go_dev_dialog_token FIELD_PACKED; + P2P_SSID peer_go_ssid FIELD_PACKED; + uint8_t wps_method FIELD_PACKED; + uint8_t dev_capab FIELD_PACKED; + int8_t go_intent FIELD_PACKED; + uint8_t persistent_grp FIELD_PACKED; +} POSTPACK WMI_P2P_GO_NEG_START_CMD; + +typedef PREPACK struct +{ + uint8_t persistent_group FIELD_PACKED; + uint8_t group_formation FIELD_PACKED; +} POSTPACK WMI_P2P_GRP_INIT_CMD; + +typedef PREPACK struct +{ + uint8_t peer_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t grp_formation_status FIELD_PACKED; +} POSTPACK WMI_P2P_GRP_FORMATION_DONE_CMD; + +typedef PREPACK struct +{ + uint32_t timeout FIELD_PACKED; +} POSTPACK WMI_P2P_LISTEN_CMD; + +typedef PREPACK struct +{ + uint16_t listen_freq FIELD_PACKED; + uint16_t force_freq FIELD_PACKED; + uint8_t status FIELD_PACKED; + int8_t go_intent FIELD_PACKED; + uint8_t wps_buf[512] FIELD_PACKED; + uint16_t wps_buflen FIELD_PACKED; + uint8_t p2p_buf[512] FIELD_PACKED; + uint16_t p2p_buflen FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t wps_method FIELD_PACKED; + uint8_t persistent_grp FIELD_PACKED; +} POSTPACK WMI_P2P_GO_NEG_REQ_RSP_CMD; + +typedef enum +{ + WMI_P2P_INVITE_ROLE_GO, + WMI_P2P_INVITE_ROLE_ACTIVE_GO, + WMI_P2P_INVITE_ROLE_CLIENT +} WMI_P2P_INVITE_ROLE; + +typedef PREPACK struct +{ + uint8_t role FIELD_PACKED; + uint16_t listen_freq FIELD_PACKED; + uint16_t force_freq FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t peer_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint8_t go_dev_addr[ATH_MAC_LEN] FIELD_PACKED; + P2P_SSID ssid FIELD_PACKED; + uint8_t is_persistent FIELD_PACKED; + uint8_t wps_method FIELD_PACKED; +} POSTPACK WMI_P2P_INVITE_CMD; + +typedef PREPACK struct +{ + uint16_t force_freq FIELD_PACKED; + uint8_t status FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + // uint8_t p2p_buf[512]; + uint16_t p2p_buflen FIELD_PACKED; + uint8_t is_go FIELD_PACKED; + uint8_t group_bssid[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_P2P_INVITE_REQ_RSP_CMD; + +typedef PREPACK struct +{ + uint16_t force_freq FIELD_PACKED; + uint8_t status FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t is_go FIELD_PACKED; + uint8_t group_bssid[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_P2P_FW_INVITE_REQ_RSP_CMD; + +typedef PREPACK struct +{ + uint16_t wps_method FIELD_PACKED; + uint16_t listen_freq FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t peer[ATH_MAC_LEN] FIELD_PACKED; + uint8_t go_dev_addr[ATH_MAC_LEN] FIELD_PACKED; + P2P_SSID go_oper_ssid FIELD_PACKED; +} POSTPACK WMI_P2P_PROV_DISC_REQ_CMD; + +typedef enum +{ + WMI_P2P_CONFID_LISTEN_CHANNEL = 1, + WMI_P2P_CONFID_CROSS_CONNECT = 2, + WMI_P2P_CONFID_SSID_POSTFIX = 3, + WMI_P2P_CONFID_INTRA_BSS = 4, + WMI_P2P_CONFID_CONCURRENT_MODE = 5, + WMI_P2P_CONFID_GO_INTENT = 6, + WMI_P2P_CONFID_DEV_NAME = 7, + WMI_P2P_CONFID_P2P_OPMODE = 8, + WMI_P2P_CONFID_CCK_RATES = 9 +} WMI_P2P_CONF_ID; + +typedef PREPACK struct +{ + uint8_t reg_class FIELD_PACKED; + uint8_t listen_channel FIELD_PACKED; +} POSTPACK WMI_P2P_LISTEN_CHANNEL; + +typedef PREPACK struct +{ + uint8_t flag FIELD_PACKED; +} POSTPACK WMI_P2P_SET_CROSS_CONNECT; + +typedef PREPACK struct +{ + uint8_t ssid_postfix[WMI_MAX_SSID_LEN - 9] FIELD_PACKED; + uint8_t ssid_postfix_len FIELD_PACKED; +} POSTPACK WMI_P2P_SET_SSID_POSTFIX; + +typedef PREPACK struct +{ + uint8_t flag FIELD_PACKED; +} POSTPACK WMI_P2P_SET_INTRA_BSS; + +#define P2P_DEV (1 << 0) +#define P2P_CLIENT (1 << 1) +#define P2P_GO (1 << 2) +#define P2P_PERSISTENT_FLAG 0x80 +typedef PREPACK struct +{ + uint8_t p2pmode FIELD_PACKED; +} POSTPACK WMI_P2P_SET_MODE; + +#define RATECTRL_MODE_DEFAULT 0 +#define RATECTRL_MODE_PERONLY 1 + +typedef PREPACK struct +{ + uint32_t mode FIELD_PACKED; +} POSTPACK WMI_SET_RATECTRL_PARM_CMD; + +#define WMI_P2P_MAX_TLV_LEN 1024 +typedef enum +{ + WMI_P2P_SD_TYPE_GAS_INITIAL_REQ = 0x1, + WMI_P2P_SD_TYPE_GAS_INITIAL_RESP = 0x2, + WMI_P2P_SD_TYPE_GAS_COMEBACK_REQ = 0x3, + WMI_P2P_SD_TYPE_GAS_COMEBACK_RESP = 0x4, + WMI_P2P_PD_TYPE_RESP = 0x5, + WMI_P2P_SD_TYPE_STATUS_IND = 0x6 +} WMI_P2P_SDPD_TYPE; + +typedef enum +{ + WMI_P2P_SDPD_TRANSACTION_PENDING = 0x1, + WMI_P2P_SDPD_TRANSACTION_COMP = 0x2 +} WMI_P2P_SDPD_TRANSACTION_STATUS; + +typedef PREPACK struct +{ + uint8_t type FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t frag_id FIELD_PACKED; + uint8_t reserved1 FIELD_PACKED; /* alignment */ + uint8_t peer_addr[ATH_MAC_LEN] FIELD_PACKED; + uint16_t freq FIELD_PACKED; + uint16_t status_code FIELD_PACKED; + uint16_t comeback_delay FIELD_PACKED; + uint16_t tlv_length FIELD_PACKED; + uint16_t update_indic FIELD_PACKED; + uint16_t total_length FIELD_PACKED; + uint16_t reserved2 FIELD_PACKED; /* future */ + uint8_t tlv[WMI_P2P_MAX_TLV_LEN] FIELD_PACKED; +} POSTPACK WMI_P2P_SDPD_TX_CMD; + +typedef PREPACK struct +{ + uint16_t go_oper_freq FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t peer_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t own_interface_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t go_dev_dialog_token FIELD_PACKED; + P2P_SSID peer_go_ssid FIELD_PACKED; + uint8_t wps_method FIELD_PACKED; + uint8_t dev_capab FIELD_PACKED; + uint8_t dev_auth FIELD_PACKED; + uint8_t go_intent FIELD_PACKED; +} POSTPACK WMI_P2P_FW_CONNECT_CMD_STRUCT; + +typedef PREPACK struct +{ + uint16_t wps_method FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t peer[ATH_MAC_LEN] FIELD_PACKED; +} POSTPACK WMI_P2P_FW_PROV_DISC_REQ_CMD; + +/* P2P module events */ + +typedef PREPACK struct +{ + uint8_t num_p2p_dev FIELD_PACKED; + uint8_t data[1] FIELD_PACKED; +} POSTPACK WMI_P2P_NODE_LIST_EVENT; + +typedef PREPACK struct +{ + uint8_t sa[ATH_MAC_LEN] FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint16_t dev_password_id FIELD_PACKED; +} POSTPACK WMI_P2P_REQ_TO_AUTH_EVENT; + +typedef PREPACK struct +{ + uint8_t sa[ATH_MAC_LEN] FIELD_PACKED; + uint8_t wps_buf[512] FIELD_PACKED; + uint16_t wps_buflen FIELD_PACKED; + uint8_t p2p_buf[512] FIELD_PACKED; + uint16_t p2p_buflen FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; +} POSTPACK WMI_P2P_GO_NEG_REQ_EVENT; + +typedef PREPACK struct +{ + uint16_t freq FIELD_PACKED; + int8_t status FIELD_PACKED; + uint8_t role_go FIELD_PACKED; + uint8_t ssid[WMI_MAX_SSID_LEN] FIELD_PACKED; + uint8_t ssid_len FIELD_PACKED; +#define WMI_MAX_PASSPHRASE_LEN 9 + char pass_phrase[WMI_MAX_PASSPHRASE_LEN] FIELD_PACKED; + uint8_t peer_device_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t peer_interface_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t wps_method FIELD_PACKED; + uint8_t persistent_grp FIELD_PACKED; +} POSTPACK WMI_P2P_GO_NEG_RESULT_EVENT; + +typedef PREPACK struct +{ + uint8_t sa[ATH_MAC_LEN] FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint8_t go_dev_addr[ATH_MAC_LEN] FIELD_PACKED; + P2P_SSID ssid FIELD_PACKED; + uint8_t is_persistent FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; +} POSTPACK WMI_P2P_FW_INVITE_REQ_EVENT; + +typedef PREPACK struct +{ + uint16_t oper_freq FIELD_PACKED; + uint8_t sa[ATH_MAC_LEN] FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint8_t is_bssid_valid FIELD_PACKED; + uint8_t go_dev_addr[ATH_MAC_LEN] FIELD_PACKED; + P2P_SSID ssid FIELD_PACKED; + uint8_t status FIELD_PACKED; +} POSTPACK WMI_P2P_INVITE_RCVD_RESULT_EVENT; + +typedef PREPACK struct +{ + uint8_t status FIELD_PACKED; + uint8_t bssid[ATH_MAC_LEN] FIELD_PACKED; + uint8_t is_bssid_valid FIELD_PACKED; +} POSTPACK WMI_P2P_INVITE_SENT_RESULT_EVENT; + +typedef PREPACK struct +{ + uint8_t sa[ATH_MAC_LEN] FIELD_PACKED; + uint16_t wps_config_method FIELD_PACKED; + uint8_t dev_addr[ATH_MAC_LEN] FIELD_PACKED; +#define WPS_DEV_TYPE_LEN 8 +#define WPS_MAX_DEVNAME_LEN 32 + uint8_t pri_dev_type[WPS_DEV_TYPE_LEN] FIELD_PACKED; + uint8_t device_name[WPS_MAX_DEVNAME_LEN] FIELD_PACKED; + uint8_t dev_name_len FIELD_PACKED; + uint16_t dev_config_methods FIELD_PACKED; + uint8_t device_capab FIELD_PACKED; + uint8_t group_capab FIELD_PACKED; +} POSTPACK WMI_P2P_PROV_DISC_REQ_EVENT; + +typedef PREPACK struct +{ + uint8_t peer[ATH_MAC_LEN] FIELD_PACKED; + uint16_t config_methods FIELD_PACKED; +} POSTPACK WMI_P2P_PROV_DISC_RESP_EVENT; + +typedef PREPACK struct +{ + uint8_t type FIELD_PACKED; + uint8_t transaction_status FIELD_PACKED; + uint8_t dialog_token FIELD_PACKED; + uint8_t frag_id FIELD_PACKED; + uint8_t peer_addr[ATH_MAC_LEN] FIELD_PACKED; + uint16_t freq FIELD_PACKED; + uint16_t status_code FIELD_PACKED; + uint16_t comeback_delay FIELD_PACKED; + uint16_t tlv_length FIELD_PACKED; + uint16_t update_indic FIELD_PACKED; + // Variable length TLV will be placed after the event +} POSTPACK WMI_P2P_SDPD_RX_EVENT; + +typedef PREPACK struct +{ + char wps_pin[WPS_PIN_LEN] FIELD_PACKED; + uint8_t peer_addr[ATH_MAC_LEN] FIELD_PACKED; + uint8_t wps_role FIELD_PACKED; +} POSTPACK WMI_P2P_PROV_INFO; + +typedef PREPACK struct +{ + WPS_CREDENTIAL credential FIELD_PACKED; +} POSTPACK WMI_P2P_PERSISTENT_PROFILE_CMD; + +#endif + +#if ENABLE_P2P_MODE + +typedef PREPACK struct +{ + uint8_t dev_name[WPS_MAX_DEVNAME_LEN] FIELD_PACKED; + uint8_t dev_name_len FIELD_PACKED; +} POSTPACK WMI_P2P_SET_DEV_NAME; + +typedef PREPACK struct +{ + uint8_t config_id; /* set to one of WMI_P2P_CONF_ID */ + PREPACK union + { + WMI_P2P_LISTEN_CHANNEL listen_ch; + WMI_P2P_SET_CROSS_CONNECT cross_conn; + WMI_P2P_SET_SSID_POSTFIX ssid_postfix; + WMI_P2P_SET_INTRA_BSS intra_bss; + WMI_P2P_SET_CONCURRENT_MODE concurrent_mode; + WMI_P2P_SET_GO_INTENT go_intent; + WMI_P2P_SET_DEV_NAME device_name; + WMI_P2P_SET_MODE mode; + WMI_P2P_SET_CCK_RATES cck_rates; + } POSTPACK val; +} POSTPACK WMI_P2P_SET_CMD; + +typedef PREPACK struct +{ + uint32_t duration FIELD_PACKED; + uint32_t interval FIELD_PACKED; + uint32_t start_or_offset FIELD_PACKED; + uint8_t count_or_type FIELD_PACKED; +} POSTPACK P2P_NOA_DESCRIPTOR; + +typedef PREPACK struct +{ + uint8_t enable FIELD_PACKED; + uint8_t count FIELD_PACKED; + uint8_t noas[1] FIELD_PACKED; +} POSTPACK WMI_NOA_INFO_STRUCT; + +typedef PREPACK struct +{ + uint8_t enable FIELD_PACKED; + uint8_t ctwin FIELD_PACKED; +} POSTPACK WMI_OPPPS_INFO_STRUCT; + +#endif + +typedef PREPACK struct +{ + boolean enable FIELD_PACKED; + uint8_t nextProbeCount FIELD_PACKED; + uint8_t maxBackOff FIELD_PACKED; + uint8_t minGtxRssi FIELD_PACKED; + uint8_t forceBackOff FIELD_PACKED; +} POSTPACK WMI_GREENTX_PARAMS_CMD; + +/* LPL commands */ +typedef PREPACK struct +{ + uint8_t lplPolicy FIELD_PACKED; /*0 - force off, 1 force on, 2 dynamic*/ + uint8_t noBlockerDetect FIELD_PACKED; /*don't do blocker detection if lpl policy is set + to dynamic*/ + uint8_t noRfbDetect FIELD_PACKED; /*don't do rate fall back detection if lpl policy is set + to dynamic*/ + uint8_t rsvd FIELD_PACKED; +} POSTPACK WMI_LPL_FORCE_ENABLE_CMD; + +/* + * Extended WMI commands are those that are needed during wireless + * operation, but which are not really wireless commands. This allows, + * for instance, platform-specific commands. Extended WMI commands are + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. + * Extended WMI events are similarly embedded in a WMI event message with + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. + */ +typedef PREPACK struct +{ + uint32_t commandId FIELD_PACKED; +} POSTPACK WMIX_CMD_HDR; + +#define WMIX_GPIO_OUTPUT_SET_CMDID 0x2003 +#define WMIX_GPIO_INPUT_GET_CMDID 0x2004 +#define WMIX_GPIO_REGISTER_SET_CMDID 0x2005 +#define WMIX_GPIO_REGISTER_GET_CMDID 0x2006 +#define WMIX_HB_CHALLENGE_RESP_CMDID 0x2008 +#define WMIX_DBGLOG_CFG_MODULE_CMDID 0x2009 +#define WMIX_GPIO_DATA_EVENTID 0x3005 +#define WMIX_HB_CHALLENGE_RESP_EVENTID 0x3007 +#define WMIX_DBGLOG_EVENTID 0x3008 +#define WMIX_PFM_DATA_EVENTID 0x300C +#define WMIX_PFM_DATA_DONE_EVENTID 0x300D + +/* + * =============GPIO support================= + * NB: Some of the WMIX APIs use a 32-bit mask. On Targets that support + * more than 32 GPIO pins, those APIs only support the first 32 GPIO pins. + */ + +/* + * Set GPIO pin output state. + * In order for output to be driven, a pin must be enabled for output. + * This can be done during initialization through the GPIO Configuration + * DataSet, or during operation with the enable_mask. + * + * If a request is made to simultaneously set/clear or set/disable or + * clear/disable or disable/enable, results are undefined. + */ +typedef PREPACK struct +{ + uint32_t set_mask; /* pins to set */ + uint32_t clear_mask; /* pins to clear */ + uint32_t enable_mask; /* pins to enable for output */ + uint32_t disable_mask; /* pins to disable/tristate */ +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; + +/* + * Set a GPIO register. For debug/exceptional cases. + * Values for gpioreg_id are GPIO_ID_*, defined in a + * platform-dependent header, gpio.h. + */ +typedef PREPACK struct +{ + uint32_t gpioreg_id; /* GPIO register ID */ + uint32_t value; /* value to write */ +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD; + +/* Get a GPIO register. For debug/exceptional cases. */ +typedef PREPACK struct +{ + uint32_t gpioreg_id; /* GPIO register to read */ +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD; + +/* + * Host acknowledges and re-arms GPIO interrupts. A single + * message should be used to acknowledge all interrupts that + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. + */ +typedef PREPACK struct +{ + uint32_t ack_mask; /* interrupts to acknowledge */ +} POSTPACK WMIX_GPIO_INTR_ACK_CMD; + +/* + * Target informs Host of GPIO interrupts that have ocurred since the + * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- + * the current GPIO input values is provided -- in order to support + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. + */ +typedef PREPACK struct +{ + uint32_t intr_mask; /* pending GPIO interrupts */ + uint32_t input_values; /* recent GPIO input values */ +} POSTPACK WMIX_GPIO_INTR_EVENT; + +/* + * WMIX_HB_CHALLENGE_RESP_CMDID + * Heartbeat Challenge Response command + */ +typedef PREPACK struct { + uint32_t cookie; + uint32_t source; +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; + +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD + +/* + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the mask of GPIO pin inputs and + * reg_id set to GPIO_ID_NONE + * + * + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the value of the requested register and + * reg_id identifying the register (reflects the original request) + * NB: reg_id supports the future possibility of unsolicited + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may + * simplify Host GPIO support. + */ +typedef PREPACK struct +{ + uint32_t value; + uint32_t reg_id; +} POSTPACK WMIX_GPIO_DATA_EVENT; + +/*----------------------------------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------------------------------------------------*/ + +typedef PREPACK struct +{ + uint8_t max_queued_buffers FIELD_PACKED; /*don't do blocker detection if lpl policy is set to dynamic*/ + uint8_t endpoint_mapping[8] FIELD_PACKED; /*don't do rate fall back detection if lpl policy is set to dynamic*/ + uint8_t start_credits_per_queue[8] FIELD_PACKED; + uint8_t num_credit_queues FIELD_PACKED; /*0 - force off, 1 force on, 2 dynamic*/ +} POSTPACK WMI_INIT_REVERSE_CREDIT_CMD; + +typedef PREPACK struct +{ + uint8_t offset FIELD_PACKED; + uint8_t shift FIELD_PACKED; + uint32_t mask FIELD_PACKED; + uint8_t count FIELD_PACKED; + uint32_t category_mapping_data[8] FIELD_PACKED; + uint8_t ep_mapping_data[8] FIELD_PACKED; + +} POSTPACK WMI_INIT_RCV_DATA_CLASSIFIER_CMD; + +typedef PREPACK struct +{ + uint32_t log_time; + uint16_t event_id; + uint16_t unused; +} POSTPACK WMIX_PFM_DATA_EVENT; + +typedef PREPACK struct +{ + boolean enable FIELD_PACKED; +} POSTPACK WMID_EVENT_SET_CMD; + +typedef struct ath_pmu_param +{ + uint32_t options; + uint32_t wake_msec; +} ATH_PMU_PARAM; + +typedef struct ath_pfm_param +{ + uint32_t options; +} ATH_PFM_PARAM; + +typedef struct ath_dset_param +{ + uint32_t dset_id; + uint32_t offset; + uint32_t length; + +} ATH_DSET_PARAM; + +#define MAX_TIMESTAMP 32 + +typedef PREPACK struct +{ + uint8_t eventID[MAX_TIMESTAMP] FIELD_PACKED; + uint32_t timestamp[MAX_TIMESTAMP] FIELD_PACKED; +} POSTPACK WMI_PFM_REPORT_EVENT; + +typedef struct +{ + uint16_t dset_id; + uint16_t len; + uint32_t offset; +} POSTPACK WMI_DSET_HOST_CFG_ITEM; + +typedef struct +{ + uint32_t length; + WMI_DSET_HOST_CFG_ITEM dset[2]; +} POSTPACK WMI_DSET_HOST_CFG_CMD; + +/* + * Extended WMIX_DSET commands are those that are needed for host dset + * operation + */ +typedef PREPACK struct +{ + uint32_t commandId FIELD_PACKED; +} POSTPACK WMIX_DSET_CMD_HDR; + +#define WMIX_DSET_CREATE_CMDID 0x1001 +#define WMIX_DSET_OPEN_CMDID 0x1002 +#define WMIX_DSET_READ_CMDID 0x1003 +#define WMIX_DSET_WRITE_CMDID 0x1004 +#define WMIX_DSET_COMMIT_CMDID 0x1005 +#define WMIX_DSET_CLOSE_CMDID 0x1006 +#define WMIX_DSET_SIZE_CMDID 0x1007 +#define WMIX_DSET_DELETE_CMDID 0x1008 + +typedef PREPACK struct +{ + WMIX_DSET_CMD_HDR hdr; + uint8_t data[1] FIELD_PACKED; /* start of data */ +} POSTPACK WMI_DSET_OP_EVENT; + +/* + */ +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; + uint32_t flags FIELD_PACKED; + uint32_t length FIELD_PACKED; +} POSTPACK WMIX_DSET_OP_CREATE_PARAM_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; + uint32_t flags FIELD_PACKED; +} POSTPACK WMIX_DSET_OP_OPEN_PARAM_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; +} POSTPACK WMIX_DSET_OP_COMMIT_PARAM_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; +} POSTPACK WMIX_DSET_OP_CLOSE_PARAM_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; + uint32_t flags FIELD_PACKED; +} POSTPACK WMIX_DSET_OP_DELETE_PARAM_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; + uint32_t flags FIELD_PACKED; + uint32_t offset FIELD_PACKED; + uint32_t length FIELD_PACKED; + uint8_t data[1] FIELD_PACKED; +} POSTPACK WMIX_DSET_OP_WRITE_PARAM_CMD; + +typedef PREPACK struct +{ + uint32_t dset_id FIELD_PACKED; + uint32_t offset FIELD_PACKED; + uint32_t length FIELD_PACKED; +} POSTPACK WMIX_DSET_OP_READ_PARAM_CMD; + +/*Define all SET/GET Param Groups here */ +#define QCOM_GROUPID_OFFSET 16 + +#define QCOM_GROUPID_MASK 0xFFFF + +#define QCOM_PARAMID_MASK 0xFFFF + +#define QCOM_PARAM_MAKE_ID(grpid, paramid) (grpid << QCOM_GROUPID_OFFSET | paramid) + +#define QCOM_PARAM_GET_GROUP_ID(which_param) (which_param >> QCOM_GROUPID_OFFSET && QCOM_GROUPID_MASK) + +#define QCOM_PARAM_GET_PARAM_ID(which_param) (which_param && QCOM_PARAMID_MASK) + +/* WMI_SYS_SET_PARAM_REPLY */ + +typedef PREPACK struct +{ + A_STATUS status; +} POSTPACK WMI_PARAM_SET_REPLY; + +/* WMI_SYS_SET_PARAMS */ + +typedef PREPACK struct +{ + uint32_t length; + uint32_t which_param; + uint8_t data_buffer[1]; +} POSTPACK WMI_PARAM_SET_CMD; + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/hardware_init.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/hardware_init.c new file mode 100644 index 00000000000..9d7723e5746 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/hardware_init.c @@ -0,0 +1,351 @@ +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "wifi_shield_silex2401.h" + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_ASW_DIS_DI 0x0400u /*!<@brief Analog switch is open (disabled), only for A0 version */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_FUNC9 0x09u /*!<@brief Selects pin function 9 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_FAST 0x40u /*!<@brief Fast mode, slew rate control is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +#if MBED_CONF_QCA400X_CONNECTOR_TYPE == ARDUINO +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSilex2401Shield + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitSilex2401Shield(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t gpio0_pin22_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_15 (pin 22) */ + GPIO_PinInit(GPIO, 0U, 15U, &gpio0_pin22_config); + + gpio_pin_config_t gpio1_pin1_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_4 (pin 1) */ + GPIO_PinInit(GPIO, 1U, 4U, &gpio1_pin1_config); + + gpio_pin_config_t gpio1_pin9_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_7 (pin 9) */ + GPIO_PinInit(GPIO, 1U, 7U, &gpio1_pin9_config); + + if (Chip_GetVersion() == 1) { + const uint32_t port0_pin15_config = (/* Pin is configured as PIO0_15 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN15 (coords: 22) is configured as PIO0_15 */ + IOCON_PinMuxSet(IOCON, 0U, 15U, port0_pin15_config); + } else { + const uint32_t port0_pin15_config = (/* Pin is configured as PIO0_15 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled), only for A0 version */ + IOCON_PIO_ASW_DIS_DI); + /* PORT0 PIN15 (coords: 22) is configured as PIO0_15 */ + IOCON_PinMuxSet(IOCON, 0U, 15U, port0_pin15_config); + } + + const uint32_t port0_pin26_config = (/* Pin is configured as HS_SPI_MOSI */ + IOCON_PIO_FUNC9 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN26 (coords: 60) is configured as HS_SPI_MOSI */ + IOCON_PinMuxSet(IOCON, 0U, 26U, port0_pin26_config); + + const uint32_t port1_pin1_config = (/* Pin is configured as HS_SPI_SSEL1 */ + IOCON_PIO_FUNC5 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN1 (coords: 59) is configured as HS_SPI_SSEL1 */ + IOCON_PinMuxSet(IOCON, 1U, 1U, port1_pin1_config); + + const uint32_t port1_pin2_config = (/* Pin is configured as HS_SPI_SCK */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN2 (coords: 61) is configured as HS_SPI_SCK */ + IOCON_PinMuxSet(IOCON, 1U, 2U, port1_pin2_config); + + const uint32_t port1_pin3_config = (/* Pin is configured as HS_SPI_MISO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN3 (coords: 62) is configured as HS_SPI_MISO */ + IOCON_PinMuxSet(IOCON, 1U, 3U, port1_pin3_config); + + const uint32_t port1_pin4_config = (/* Pin is configured as PIO1_4 */ + IOCON_PIO_FUNC0 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN4 (coords: 1) is configured as PIO1_4 */ + IOCON_PinMuxSet(IOCON, 1U, 4U, port1_pin4_config); + + const uint32_t port1_pin7_config = (/* Pin is configured as PIO1_7 */ + IOCON_PIO_FUNC0 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN7 (coords: 9) is configured as PIO1_7 */ + IOCON_PinMuxSet(IOCON, 1U, 7U, port1_pin7_config); +} + +#else // Configuration for mikroe wifi board + +/*! @name PIO0_16 (number 14), KFETON + @{ */ +#define BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_GPIO GPIO /*!<@brief GPIO device name: GPIO */ +#define BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_PORT 0U /*!<@brief PORT device name: 0U */ +#define BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_PIN 16U /*!<@brief 0U pin index: 16 */ + /* @} */ + +/*! @name PIO1_5 (number 31), PWRON + @{ */ +#define BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_GPIO GPIO /*!<@brief GPIO device name: GPIO */ +#define BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_PORT 1U /*!<@brief PORT device name: 1U */ +#define BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_PIN 5U /*!<@brief 1U pin index: 5 */ + /* @} */ + +/*! @name PIO1_18 (number 64), IRQ + @{ */ +#define BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_GPIO GPIO /*!<@brief GPIO device name: GPIO */ +#define BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_PORT 1U /*!<@brief PORT device name: 1U */ +#define BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_PIN 18U /*!<@brief 1U pin index: 18 */ + +void BOARD_InitSilex2401Shield(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + /* Enables the clock for the GPIO0 module */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Enables the clock for the GPIO1 module */ + CLOCK_EnableClock(kCLOCK_Gpio1); + + gpio_pin_config_t KFETON_ID_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO0_16 (pin 14) */ + GPIO_PinInit(BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_GPIO, BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_PORT, BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_PIN, &KFETON_ID_config); + + gpio_pin_config_t PWRON_ID_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_5 (pin 31) */ + GPIO_PinInit(BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_GPIO, BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_PORT, BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_PIN, &PWRON_ID_config); + + gpio_pin_config_t IRQ_ID_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */ + GPIO_PinInit(BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_GPIO, BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_PORT, BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_PIN, &IRQ_ID_config); + + const uint32_t KFETON_ID = (/* Pin is configured as PIO0_16 */ + IOCON_PIO_FUNC0 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is disabled */ + IOCON_PIO_ASW_DIS_DI); + /* PORT0 PIN16 (coords: 14) is configured as PIO0_16 */ + IOCON_PinMuxSet(IOCON, BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_PORT, BOARD_INITWIFI10CLICKSHIELD_KFETON_ID_PIN, KFETON_ID); + + const uint32_t port0_pin26_config = (/* Pin is configured as HS_SPI_MOSI */ + IOCON_PIO_FUNC9 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN26 (coords: 60) is configured as HS_SPI_MOSI */ + IOCON_PinMuxSet(IOCON, 0U, 26U, port0_pin26_config); + + const uint32_t port1_pin1_config = (/* Pin is configured as HS_SPI_SSEL1 */ + IOCON_PIO_FUNC5 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN1 (coords: 59) is configured as HS_SPI_SSEL1 */ + IOCON_PinMuxSet(IOCON, 1U, 1U, port1_pin1_config); + + const uint32_t IRQ_ID = (/* Pin is configured as PIO1_18 */ + IOCON_PIO_FUNC0 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN18 (coords: 64) is configured as PIO1_18 */ + IOCON_PinMuxSet(IOCON, BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_PORT, BOARD_INITWIFI10CLICKSHIELD_IRQ_ID_PIN, IRQ_ID); + + const uint32_t port1_pin2_config = (/* Pin is configured as HS_SPI_SCK */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN2 (coords: 61) is configured as HS_SPI_SCK */ + IOCON_PinMuxSet(IOCON, 1U, 2U, port1_pin2_config); + + const uint32_t port1_pin3_config = (/* Pin is configured as HS_SPI_MISO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Fast mode, slew rate control is disabled */ + IOCON_PIO_SLEW_FAST | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN3 (coords: 62) is configured as HS_SPI_MISO */ + IOCON_PinMuxSet(IOCON, 1U, 3U, port1_pin3_config); + + const uint32_t PWRON_ID = (/* Pin is configured as PIO1_5 */ + IOCON_PIO_FUNC0 | + /* Selects pull-down function */ + IOCON_PIO_MODE_PULLDOWN | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT1 PIN5 (coords: 31) is configured as PIO1_5 */ + IOCON_PinMuxSet(IOCON, BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_PORT, BOARD_INITWIFI10CLICKSHIELD_PWRON_ID_PIN, PWRON_ID); +} + +#endif // MBED_CONF_QCA400X_CONNECTOR_TYPE + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield.c new file mode 100644 index 00000000000..3acadf09841 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2017, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "wifi_common.h" +#include "fsl_gpio.h" +#include "driver_cxt.h" +#include "wifi_spi.h" +#include "wifi_shield.h" +#include "fsl_pint.h" +#include "fsl_inputmux.h" +#include "fsl_inputmux_connections.h" + +static void PINT_callback(pint_pin_int_t pintr, uint32_t pmatch_status); + +/*! + * @brief Low level initialization, RTOS does not have to run yet + */ +A_STATUS WIFISHIELD_Init(void) +{ + gpio_pin_config_t config; + memset(&config, 0, sizeof(config)); + + /* Initialize pinmux */ +#ifdef WIFISHIELD_PINMUX_INIT + WIFISHIELD_PINMUX_INIT(); +#endif + + /* Enable clocks for GPIO */ +// CLOCK_EnableClock(WIFISHIELD_WLAN_PWRON_CLOCKSRC); +// CLOCK_EnableClock(WIFISHIELD_WLAN_IRQ_CLOCKSRC); + + /* Enable clocks for SPI */ + CLOCK_AttachClk(WIFISHIELD_SPI_CLK_CONNECT); //kCLOCK_Hs_Lspi + RESET_PeripheralReset(WIFISHIELD_SPI_IP_RESET);// + + /* Set up WLAN_PWRON signal */ +// config.pinDirection = (gpio_pin_direction_t)WIFISHIELD_WLAN_PWRON_DIRECTION; +// GPIO_PinInit(WIFISHIELD_WLAN_PWRON_GPIO, WIFISHIELD_WLAN_PWRON_PORT, WIFISHIELD_WLAN_PWRON_PIN, &config); + + /* Set up WLAN_IRQ signal */ +// config.pinDirection = (gpio_pin_direction_t)WIFISHIELD_WLAN_IRQ_DIRECTION; +// GPIO_PinInit(WIFISHIELD_WLAN_IRQ_GPIO, WIFISHIELD_WLAN_IRQ_PORT, WIFISHIELD_WLAN_IRQ_PIN, &config); + + /* Set up Inputmux */ + INPUTMUX_Init(INPUTMUX); + INPUTMUX_AttachSignal(INPUTMUX, WIFISHIELD_WLAN_PINT, WIFISHIELD_WLAN_PINT_CONNECT); + INPUTMUX_Deinit(INPUTMUX); + + /* Set up PINT for WLAN_IRQ */ + PINT_Init(PINT); + CLOCK_EnableClock(kCLOCK_Pint); + PINT_PinInterruptConfig(PINT, WIFISHIELD_WLAN_PINT, WIFISHIELD_WLAN_PINT_EDGE, PINT_callback); + PINT_EnableCallback(PINT); + + /* Enable NVIC interrupt for WLAN_IRQ */ + NVIC_EnableIRQ(WIFISHIELD_WLAN_PINT_IRQ); + + /* Set NVIC priority */ + NVIC_SetPriority(WIFISHIELD_WLAN_PINT_IRQ, 0); + + return A_OK; +} + +/*! + * @brief Initialization is maintained by WIFI stack + */ +A_STATUS WIFISHIELD_InitDrivers(void *param) +{ + /* Set up capabilities of SPI transfer, used in upper layer */ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(param); + + /* Force WIFI stack to use this SPI settings */ + pDCxt->spi_hcd.PowerUpDelay = 1; + pDCxt->spi_hcd.SpiHWCapabilitiesFlags = (HW_SPI_FRAME_WIDTH_8 | HW_SPI_NO_DMA | HW_SPI_INT_EDGE_DETECT); + + /* Complex DMAMUX/DMA/SPI config structure */ + WIFIDRVS_SPI_config_t spi_config = {0}; + + /* Load default settings */ + WIFIDRVS_SPI_GetDefaultConfig(&spi_config); + +#if defined(WIFISHIELD_DMA) + /* Configure dma_mode */ + spi_config.dma_mode.enabled = true; + spi_config.dma_mode.dma_base = (void*)WIFISHIELD_DMA; + spi_config.dma_mode.dma_rx_chnl = WIFISHIELD_DMA_RX_CHNL; + spi_config.dma_mode.dma_rx_chnl_prio = kDMA_ChannelPriority3; + spi_config.dma_mode.dma_tx_chnl = WIFISHIELD_DMA_TX_CHNL; + spi_config.dma_mode.dma_tx_chnl_prio = kDMA_ChannelPriority4; + spi_config.dma_mode.dma_irq_prio = 0; + + // Workaround for early prototype + NVIC_DisableIRQ(LSPI_HS_IRQn); + NVIC_DisableIRQ(GINT0_IRQn); + RESET_SetPeripheralReset(kDMA0_RST_SHIFT_RSTn); + RESET_SetPeripheralReset(kHSLSPI_RST_SHIFT_RSTn); + RESET_ClearPeripheralReset(kDMA0_RST_SHIFT_RSTn); + RESET_ClearPeripheralReset(kHSLSPI_RST_SHIFT_RSTn); +#endif + +//#if defined(WIFISHIELD_SPI_IRQ_PRIORITY) +// /* Configure irq_mode */ +// spi_config.irq_mode.enabled = true; +// spi_config.irq_mode.spi_irq_prio = WIFISHIELD_SPI_IRQ_PRIORITY; +//#endif + + /* Configure spi */ + spi_config.spi.base = (void*)WIFISHIELD_SPI; + spi_config.spi.clk_hz = CLOCK_GetFreq(kCLOCK_HsLspi); + spi_config.spi.baudrate = WIFISHIELD_SPI_BAUDRATE; + spi_config.spi.irq_threshold = WIFISHIELD_SPI_THRESHOLD; + + /* Load recommended SPI settings */ + WIFIDRVS_SPI_GetSPIConfig(&spi_config.spi.config, WIFISHIELD_SPI_BAUDRATE, WIFISHIELD_SPI_INIT_CS); + + /* Initialize driver */ + A_STATUS result = WIFIDRVS_SPI_Init(&spi_config); + assert(A_OK == result); + + return result; +} + +/*! + * @brief Deinitialization is maintained by WIFI stack + */ +A_STATUS WIFISHIELD_DeinitDrivers(void *param) +{ + // WIFI_Spi_Deinit(); + return A_OK; +} + +/*! + * @brief Power up WiFi shield, RTOS does not have to run yet + */ +A_STATUS WIFISHIELD_PowerUp(uint32_t enable) +{ + if (enable) + { + GPIO_PinWrite(WIFISHIELD_WLAN_PWRON_GPIO, WIFISHIELD_WLAN_PWRON_PORT, WIFISHIELD_WLAN_PWRON_PIN, 1); + } + else + { + GPIO_PinWrite(WIFISHIELD_WLAN_PWRON_GPIO, WIFISHIELD_WLAN_PWRON_PORT, WIFISHIELD_WLAN_PWRON_PIN, 0); + } + return A_OK; +} + +/*! + * @brief Fn post DriverTask semaphore, can be called only from WLAN_IRQ ISR + */ +void WIFISHIELD_NotifyDriverTask(void *param) +{ + extern QCA_CONTEXT_STRUCT *wlan_get_context(void); + QCA_CONTEXT_STRUCT *wifi_ctx = wlan_get_context();; + void HW_InterruptHandler(void *pCxt); + + void *pCxt = wifi_ctx->MAC_CONTEXT_PTR; + if (pCxt) + { + HW_InterruptHandler(pCxt); + } +} + +/* ISR callback for WLAN_IRQ */ +static void PINT_callback(pint_pin_int_t pintr, uint32_t pmatch_status) +{ + WIFISHIELD_NotifyDriverTask(NULL); +} + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield.h new file mode 100644 index 00000000000..42d8e76ed28 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2017, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WIFI_SHIELD_H__ +#define __WIFI_SHIELD_H__ + +/* Select specific shield support */ +//#define WIFISHIELD_IS_GT202 +#define WIFISHIELD_IS_SILEX2041 + +/* NOTE: Silex is not supported. WLAN_IRQ is routed to P3_2 + * that does not support interrupts */ + +/* Include shields support */ +#if defined(WIFISHIELD_IS_GT202) +#include "wifi_shield_gt202.h" +#elif defined(WIFISHIELD_IS_SILEX2041) +#include "wifi_shield_silex2401.h" +#else +#error "No shield is selected !" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/* Fn prototypes, which need to be implemented */ +A_STATUS WIFISHIELD_Init(void); + +#if defined(__cplusplus) +} +#endif + +A_STATUS WIFISHIELD_InitDrivers(void *param); +A_STATUS WIFISHIELD_DeinitDrivers(void *param); +A_STATUS WIFISHIELD_PowerUp(uint32_t enable); +void WIFISHIELD_NotifyDriverTask(void *param); + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield_silex2401.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield_silex2401.h new file mode 100644 index 00000000000..64e33f4dafe --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/boards/TARGET_LPC55S69/TARGET_LPCXpresso/wifi_shield_silex2401.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2017, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WIFI_SHIELD_SILEX2401_H__ +#define __WIFI_SHIELD_SILEX2401_H__ + +#include "wifi_common.h" + +/* This file cannot be included directly in common code, it must pass through "wifi_shield.h" */ +#ifndef WIFISHIELD_ENABLED +# define WIFISHIELD_ENABLED +#else +# error "Other WiFi shield is already enabled !" +#endif + +#define MIKROE 0x1 // Wifi board connects to the mikroe connector +#define ARDUINO 0x2 // Wifi board connects to the arduino connector + +void BOARD_InitSilex2401Shield(void); + +/* Pinmux function, generated by pinmuxtool */ +#define WIFISHIELD_PINMUX_INIT BOARD_InitSilex2401Shield + +#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO +#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U +#if MBED_CONF_QCA400X_CONNECTOR_TYPE == ARDUINO +#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 7U +#else +#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 5U +#endif + +#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO +#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 0U +#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 15U + +/* WLAN_IRQ PINT */ +#define WIFISHIELD_WLAN_PINT (kPINT_PinInt1) +#define WIFISHIELD_WLAN_PINT_EDGE (kPINT_PinIntEnableFallEdge) +#if MBED_CONF_QCA400X_CONNECTOR_TYPE == ARDUINO +#define WIFISHIELD_WLAN_PINT_CONNECT (kINPUTMUX_GpioPort0Pin15ToPintsel) +#else +#define WIFISHIELD_WLAN_PINT_CONNECT (kINPUTMUX_GpioPort1Pin18ToPintsel) +#endif +#define WIFISHIELD_WLAN_PINT_IRQ (PIN_INT1_IRQn) + +/* WLAN_IRQ signal */ +#define WIFISHIELD_WLAN_IRQ_DIRECTION (BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION) +#define WIFISHIELD_WLAN_IRQ_PORT (BOARD_INITSILEX2401SHIELD_IRQ_PORT) +#define WIFISHIELD_WLAN_IRQ_GPIO (BOARD_INITSILEX2401SHIELD_IRQ_GPIO) +#define WIFISHIELD_WLAN_IRQ_PIN (BOARD_INITSILEX2401SHIELD_IRQ_PIN) +#define WIFISHIELD_WLAN_IRQ_CLOCKSRC (kCLOCK_Gpio1) + +/* WLAN_PWRON (PWRDWN) signal */ +#define WIFISHIELD_WLAN_PWRON_DIRECTION (BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION) +#define WIFISHIELD_WLAN_PWRON_PORT (BOARD_INITSILEX2401SHIELD_PWRON_PORT) +#define WIFISHIELD_WLAN_PWRON_GPIO (BOARD_INITSILEX2401SHIELD_PWRON_GPIO) +#define WIFISHIELD_WLAN_PWRON_PIN (BOARD_INITSILEX2401SHIELD_PWRON_PIN) +#define WIFISHIELD_WLAN_PWRON_CLOCKSRC (kCLOCK_Gpio1) + +/* SPI settings */ +#define WIFISHIELD_SPI (SPI8) +#define WIFISHIELD_SPI_INIT_CS (kSPI_Ssel1) +#define WIFISHIELD_SPI_CLK_CONNECT (kFRO12M_to_HSLSPI) +#define WIFISHIELD_SPI_IP_RESET (kHSLSPI_RST_SHIFT_RSTn) +#define WIFISHIELD_SPI_BAUDRATE (10000000) +#define WIFISHIELD_SPI_THRESHOLD (8) + +/* DMA settings */ +#define WIFISHIELD_DMA (DMA0) +#define WIFISHIELD_DMA_RX_CHNL (2) +#define WIFISHIELD_DMA_TX_CHNL (3) + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/drivers/wifi_spi.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/drivers/wifi_spi.c new file mode 100644 index 00000000000..9d250224684 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/drivers/wifi_spi.c @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "wifi_common.h" +#include "athdefs.h" + +#include "fsl_spi.h" +#include "fsl_spi_dma.h" +//#include "fsl_dmamux.h" +//#include "fsl_edma.h" +//#include "fsl_dspi_edma.h" +#include "wifi_spi.h" +#include "mbed_assert.h" + +static dma_handle_t g_m_tx_handle; +static dma_handle_t g_m_rx_handle; +static spi_dma_handle_t g_m_dma_handle; +static spi_master_handle_t g_m_handle; + +static osMutexId_t mutex; +static osSemaphoreId_t event; + +static mbed_rtos_storage_mutex_t mutex_sem_storage; +static mbed_rtos_storage_semaphore_t event_sem_storage; + +static int32_t g_dma_chunk = 1023; +//static enum IRQn g_dma_irqs[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; +static enum IRQn g_spi_irqs[] = SPI_IRQS; +static spi_master_config_t g_spi_config; + +static SPI_Type *g_spi_base = NULL; +static uint32_t g_xfer_cs = 0; +static uint32_t g_irq_threshold = 0; + +extern uint32_t SPI_GetInstance(SPI_Type *base); + +/*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +static int32_t DMA_GetInstance(DMA_Type *base) +{ + int32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + MBED_ASSERT(instance < ARRAY_SIZE(s_dmaBases)); + return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1; +} + +/* + * DMA handler, release transfer semaphore + */ +static void SPI_DMA_MasterUserCallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) +{ + /* disable DMA requests before invoke callback */ + osSemaphoreRelease(event); +} + +/* + * IRQ handler, release transfer semaphore + */ +static void SPI_MasterUserCallback(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData) +{ + osSemaphoreRelease(event); +} + +/* + * Initialize SPI IRQ mode + */ +static A_STATUS WIFIDRVS_SPI_InitIRQMode(WIFIDRVS_SPI_config_t *config) +{ + uint32_t spi_id = SPI_GetInstance(config->spi.base); + NVIC_SetPriority(g_spi_irqs[spi_id], config->irq_mode.spi_irq_prio); + + /* SPI IRQ non-blocking handle */ + SPI_MasterTransferCreateHandle(config->spi.base, &g_m_handle, SPI_MasterUserCallback, NULL); + + return A_OK; +} + +/* + * Initialize SPI DMA mode + */ +static A_STATUS WIFIDRVS_SPI_InitDMAMode(WIFIDRVS_SPI_config_t *config) +{ + int32_t dmaInstance; + DMA_Init(config->dma_mode.dma_base); + DMA_EnableChannel(config->dma_mode.dma_base, config->dma_mode.dma_rx_chnl); + DMA_EnableChannel(config->dma_mode.dma_base, config->dma_mode.dma_tx_chnl); + DMA_SetChannelPriority(config->dma_mode.dma_base, config->dma_mode.dma_rx_chnl, config->dma_mode.dma_rx_chnl_prio); + DMA_SetChannelPriority(config->dma_mode.dma_base, config->dma_mode.dma_tx_chnl, config->dma_mode.dma_tx_chnl_prio); + DMA_CreateHandle(&g_m_rx_handle, config->dma_mode.dma_base, config->dma_mode.dma_rx_chnl); + DMA_CreateHandle(&g_m_tx_handle, config->dma_mode.dma_base, config->dma_mode.dma_tx_chnl); + SPI_MasterTransferCreateHandleDMA(config->spi.base, &g_m_dma_handle, SPI_DMA_MasterUserCallback, NULL, &g_m_tx_handle, + &g_m_rx_handle); + dmaInstance = DMA_GetInstance(config->dma_mode.dma_base); + NVIC_SetPriority(s_dmaIRQNumber[dmaInstance], config->dma_mode.dma_irq_prio); + return A_OK; +} + +/* + * Initialize SPI peripheral + */ +static A_STATUS WIFIDRVS_SPI_InitPeriph( + SPI_Type *base, + uint32_t src_clk_hz, + uint32_t xfer_cs, + spi_master_config_t *user_config +) +{ + MBED_ASSERT(NULL != base); + MBED_ASSERT(NULL != user_config); + + /* Maximum number of available tokens for a completion semaphore. */ + uint32_t sem_max_count = 1; + /* Initial number of available tokens for a completion semaphore. */ + uint32_t sem_initial_count = 0; + + osMutexAttr_t mutex_attr = { 0 }; + mutex_attr.name = "Wifi SPI Mutex"; + mutex_attr.cb_mem = &mutex_sem_storage; + mutex_attr.cb_size = sizeof(mutex_sem_storage); + mutex_attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; + + mutex = osMutexNew(&mutex_attr); + MBED_ASSERT(NULL != mutex); + + osSemaphoreAttr_t event_sem_attr = { 0 }; + event_sem_attr.cb_mem = &event_sem_storage; + event_sem_attr.cb_size = sizeof(event_sem_storage); + + event = osSemaphoreNew(sem_max_count, sem_initial_count, &event_sem_attr); + MBED_ASSERT(NULL != event); + + /* DSPI init */ + SPI_MasterInit(base, &g_spi_config, src_clk_hz); + + return A_OK; +} + +/* + * Transfer data in DMA mode + */ +static A_STATUS WIFIDRVS_SPI_DMA_Transfer(spi_transfer_t *transfer) +{ + status_t result = SPI_MasterTransferDMA(g_spi_base, &g_m_dma_handle, transfer); + if (kStatus_Success != result) { + MBED_ASSERT(0); + return A_ERROR; + } + + /* semaphore is released in callback fn */ + if (osOK != osSemaphoreAcquire(event, osWaitForever)) { + MBED_ASSERT(0); + return A_ERROR; + } + + SPI_EnableTxDMA(g_spi_base, false); + SPI_EnableRxDMA(g_spi_base, false); + + return A_OK; +} + +/* + * Transfer data in IRQ mode + */ +static A_STATUS WIFIDRVS_SPI_IRQ_Transfer(spi_transfer_t *transfer) +{ + MBED_ASSERT(NULL != transfer); + + status_t result = SPI_MasterTransferNonBlocking(g_spi_base, &g_m_handle, transfer); + if (kStatus_Success != result) { + MBED_ASSERT(0); + return A_ERROR; + } + if (osOK != osSemaphoreAcquire(event, osWaitForever)) { + MBED_ASSERT(0); + result = A_ERROR; + } + return A_OK; +} + +/* + * Transfer data + */ +static A_STATUS WIFIDRVS_SPI_Transfer(spi_transfer_t *transfer) +{ + A_STATUS result = A_OK; + + /* NOTE: following code expects that SDK drivers do not + * modify members of 'transfer' argument */ + for (int32_t to_transfer = transfer->dataSize; to_transfer;) + { + if (to_transfer < g_irq_threshold) { + /* DMA is unefficient for small amount of data, so use IRQ mode. + * IRQ mode can transfer unlimited number of data */ + transfer->dataSize = to_transfer; + transfer->configFlags |= kSPI_FrameAssert; + result = WIFIDRVS_SPI_IRQ_Transfer(transfer); + if (A_OK != result) + break; + to_transfer = 0; + } else { + /* DSPI over EDMA can transfer only limited number of bytes + * so we have to split transfer into chunks */ + //transfer->dataSize = to_transfer < g_dma_chunk ? to_transfer : g_dma_chunk; + // TODO: need to verify behaviour when transfer is splitted in default continuous mode + // TODO: allows CS for every word ? + if (to_transfer < g_dma_chunk) { + transfer->dataSize = to_transfer; + transfer->configFlags |= kSPI_FrameAssert; + } else { + transfer->dataSize = g_dma_chunk; + } + result = WIFIDRVS_SPI_DMA_Transfer(transfer); + if (A_OK != result) + break; + to_transfer -= transfer->dataSize; + /* recalculate rx/rx offsets */ + if (NULL != transfer->txData) { + transfer->txData += transfer->dataSize; + } + if (NULL != transfer->rxData) { + transfer->rxData += transfer->dataSize; + } + } + } + + return result; +} + +/*! + * @brief Initialize SPI driver + */ +A_STATUS WIFIDRVS_SPI_Init(WIFIDRVS_SPI_config_t *config) +{ + /* No SPI base address, invalid config*/ + MBED_ASSERT(!((NULL == config) || (NULL == config->spi.base))); + if ((NULL == config) || (NULL == config->spi.base)) return A_ERROR; + + /* IRQ mode only - set threshold to max value */ + if ((config->irq_mode.enabled) && (!config->dma_mode.enabled)) { + g_irq_threshold = (uint32_t)-1; + } + /* DMA mode only - set threshold to 0 */ + else if ((!config->irq_mode.enabled) && (config->dma_mode.enabled)) { + g_irq_threshold = 0; + } + /* DMA and IRQ mode - set user defined value */ + else if ((config->irq_mode.enabled) && (config->dma_mode.enabled)) { + g_irq_threshold = config->spi.irq_threshold; + } + /* Neither of modes is enabled, return error */ + else { + return A_ERROR; + } + + /* Prepare driver internal context */ + g_spi_base = config->spi.base; + g_xfer_cs = config->spi.xfer_cs; + g_spi_config = config->spi.config; + + /* Initialize SPI peripheral */ + WIFIDRVS_SPI_InitPeriph(config->spi.base, config->spi.clk_hz, config->spi.xfer_cs, &config->spi.config); + + /* Enable IRQ mode */ + if (config->irq_mode.enabled) { + WIFIDRVS_SPI_InitIRQMode(config); + } + + /* Enable DMA mode */ + if (config->dma_mode.enabled) { + WIFIDRVS_SPI_InitDMAMode(config); + } + + return A_OK; +} + +/*! + * @brief Deinitialize SPI driver + */ +A_STATUS WIFIDRVS_SPI_Deinit(WIFIDRVS_SPI_config_t *config) +{ + MBED_ASSERT(!(NULL == config)); + if (NULL == config) return A_ERROR; + + if (NULL == config->spi.base) return A_ERROR; + SPI_Deinit(config->spi.base); + + return A_OK; +} + +/*! + * @brief Return default configuration + */ +A_STATUS WIFIDRVS_SPI_GetDefaultConfig(WIFIDRVS_SPI_config_t *config) +{ + MBED_ASSERT(!(NULL == config)); + if (NULL == config) return A_ERROR; + + memset(config, 0, sizeof(*config)); + config->dma_mode.dma_rx_chnl = -1; + config->dma_mode.dma_tx_chnl = -1; + + return A_OK; +} + +/*! + * @brief Return default SPI peripheral settings + */ +A_STATUS WIFIDRVS_SPI_GetSPIConfig(spi_master_config_t *user_config, uint32_t baudrate, spi_ssel_t cs) +{ + MBED_ASSERT(!(NULL == user_config)); + if (NULL == user_config) return A_ERROR; + + memset(user_config, 0, sizeof(*user_config)); + SPI_MasterGetDefaultConfig(user_config); + + user_config->polarity = kSPI_ClockPolarityActiveLow; + user_config->phase = kSPI_ClockPhaseSecondEdge; + user_config->direction = kSPI_MsbFirst; + user_config->baudRate_Bps = baudrate; + user_config->dataWidth = kSPI_Data8Bits; + user_config->sselNum = cs; + user_config->sselPol = kSPI_SpolActiveAllLow; + + return A_OK; +} + +/*! + * @brief WiFi SPI transfer SPI + */ +A_STATUS WIFIDRVS_SPI_InOutToken(uint32_t OutToken, uint8_t DataSize, uint32_t *pInToken) +{ + A_STATUS result; + spi_transfer_t transfer = {0}; + + transfer.txData = (uint8_t *)&OutToken; + transfer.rxData = (uint8_t *)pInToken; + transfer.dataSize = DataSize; + transfer.configFlags = g_xfer_cs; + + /* Protect transmit by mutex */ + if (osOK != osMutexAcquire(mutex, osWaitForever)) { + return A_ERROR; + } + result = WIFIDRVS_SPI_Transfer(&transfer); + osMutexRelease(mutex); + return result; +} + +/*! + * @brief WiFi SPI transfer SPI + */ +A_STATUS WIFIDRVS_SPI_InOutBuffer(uint8_t *pBuffer, uint16_t length, uint8_t doRead, boolean sync) +{ + A_STATUS result; + spi_transfer_t transfer = {0}; + + if (doRead) + { + transfer.txData = NULL; + transfer.rxData = pBuffer; + } + else + { + transfer.txData = pBuffer; + transfer.rxData = NULL; + } + transfer.dataSize = length; + transfer.configFlags = g_xfer_cs; + + /* Protect transmit by mutex */ + if (osOK != osMutexAcquire(mutex, osWaitForever)) { + return A_ERROR; + } + result = WIFIDRVS_SPI_Transfer(&transfer); + osMutexRelease(mutex); + return result; +} + diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/drivers/wifi_spi.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/drivers/wifi_spi.h new file mode 100644 index 00000000000..ec04b1cd3fa --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/drivers/wifi_spi.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WIFI_SPI_H__ +#define __WIFI_SPI_H__ + +#include +#include "fsl_spi.h" +#include "fsl_dma.h" + +/* can be extended in future */ +typedef struct { + struct { + uint32_t enabled; + DMA_Type *dma_base; + int32_t dma_rx_chnl; + dma_priority_t dma_rx_chnl_prio; + int32_t dma_tx_chnl; + dma_priority_t dma_tx_chnl_prio; + uint32_t dma_irq_prio; + } dma_mode; + struct { + uint32_t enabled; + uint32_t spi_irq_prio; + } irq_mode; + struct { + SPI_Type *base; + uint32_t clk_hz; + uint32_t xfer_cs; + uint32_t baudrate; + uint32_t irq_threshold; + spi_master_config_t config; + } spi; +} WIFIDRVS_SPI_config_t; + +/* prototypes */ +A_STATUS WIFIDRVS_SPI_Init(WIFIDRVS_SPI_config_t *config); +A_STATUS WIFIDRVS_SPI_Deinit(WIFIDRVS_SPI_config_t *config); +A_STATUS WIFIDRVS_SPI_InOutToken(uint32_t OutToken, uint8_t DataSize, uint32_t *pInToken); +A_STATUS WIFIDRVS_SPI_InOutBuffer(uint8_t *pBuffer, uint16_t length, uint8_t doRead, boolean sync); +A_STATUS WIFIDRVS_SPI_GetDefaultConfig(WIFIDRVS_SPI_config_t *config); +A_STATUS WIFIDRVS_SPI_GetSPIConfig(spi_master_config_t *user_config, uint32_t baudrate, spi_ssel_t cs); + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env.c new file mode 100644 index 00000000000..10830091329 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "wifi_common.h" +#include "mbed_assert.h" +#include "mbed_critical.h" + +/*TODO: check return value */ +void a_free(void *addr, uint8_t id) +{ + // UNUSED_ARGUMENT(id); + free(addr); +} + +/* FIXME !! */ +extern uint32_t g_totAlloc; +void *a_malloc(int32_t size, uint8_t id) +{ + void *addr; + + addr = (void *)malloc(size); + + if (addr != NULL) { + /*FIXME: !!!*/ + g_totAlloc += size; + } + // UNUSED_ARGUMENT(id); + + return addr; +} + +A_STATUS a_mutex_init(mutex_t *pMutex) +{ + osMutexAttr_t attr = { 0 }; + attr.name = "qca400x_mutex"; + attr.cb_mem = &pMutex->mutexMem; + attr.cb_size = sizeof(pMutex->mutexMem); + attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; + pMutex->mutexHandler = osMutexNew(&attr); + + if (NULL == pMutex->mutexHandler) { + return A_ERROR; + } else { + return A_OK; + } +} + +A_STATUS a_mutex_acquire(mutex_t *pMutex) +{ + osStatus status = osMutexAcquire(pMutex->mutexHandler, osWaitForever); + + if (status != osOK) { + return A_ERROR; + } else { + return A_OK; + } +} + +A_STATUS a_mutex_release(mutex_t *pMutex) +{ + osStatus status = osMutexRelease(pMutex->mutexHandler); + + if (status != osOK) { + return A_ERROR; + } else { + return A_OK; + } +} + +boolean a_is_mutex_valid(mutex_t *pMutex) +{ + // FIXME: check owner of mutex + return true; +} + +A_STATUS a_mutex_delete(mutex_t *pMutex) +{ + osMutexDelete(pMutex->mutexHandler); + + return A_OK; +} + +A_STATUS a_event_delete(event_t *pEvent) +{ + MBED_ASSERT(pEvent); + osEventFlagsDelete(pEvent->eventHandler); + + return A_OK; +} + +A_STATUS a_event_init(event_t *pEvent, osa_event_clear_mode_t clearMode) +{ + osEventFlagsAttr_t attr = { 0 }; + attr.name = "qca400x_event_flags"; + attr.cb_mem = &pEvent->eventMem; + attr.cb_size = sizeof(pEvent->eventMem); + pEvent->eventHandler = osEventFlagsNew(&attr); + + if (pEvent->eventHandler) { + pEvent->clearMode = clearMode; + return A_OK; + } else { + return A_ERROR; + } +} + +A_STATUS a_event_clear(event_t *pEvent, uint32_t flagsToClear) +{ + MBED_ASSERT(pEvent); + + osEventFlagsClear(pEvent->eventHandler, flagsToClear); + + return A_OK; +} + +A_STATUS a_event_set(event_t *pEvent, uint32_t flagsToSet) +{ + MBED_ASSERT(pEvent); + + osEventFlagsSet(pEvent->eventHandler, flagsToSet); + + return A_OK; +} + +A_STATUS a_event_wait( + event_t *pEvent, uint32_t flagsToWait, boolean waitAll, uint32_t timeout, uint32_t *setFlags) +{ + MBED_ASSERT(pEvent); + uint32_t flagsSave; + uint32_t clearMode; + + if (pEvent->eventHandler == NULL) { + return A_ERROR; + } + + clearMode = (kEventAutoClear == pEvent->clearMode) ? 0 : osFlagsNoClear; + + if (waitAll) { + flagsSave = osEventFlagsWait(pEvent->eventHandler, flagsToWait, osFlagsWaitAll | clearMode, timeout); + } else { + flagsSave = osEventFlagsWait(pEvent->eventHandler, flagsToWait, osFlagsWaitAny | clearMode, timeout); + } + + *setFlags = flagsSave & flagsToWait; + + if ((flagsSave & osFlagsError) || !(flagsSave & flagsToWait)) { + return A_TIMEOUT; // TODO: unify with caller + } else { + return A_OK; + + } +} + +uint32_t a_time_get_msec(void) +{ + uint32_t ticks; + + ticks = osKernelGetTickCount(); + + return TICKS_TO_MSEC(ticks); +} + +void OSA_EnterCritical(osa_critical_section_mode_t mode) +{ + core_util_critical_section_enter(); +} + +void OSA_ExitCritical(osa_critical_section_mode_t mode) +{ + core_util_critical_section_exit(); +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env.h new file mode 100644 index 00000000000..732106c133f --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WIFI_ENV_H__ +#define __WIFI_ENV_H__ + +#include +#include "cmsis_os.h" +#include "mbed_rtos_storage.h" + +/* contains only prototypes and struct. no defines !!! */ +#include "wifi_common.h" //?? + +// TODO: remove +#include "a_config.h" + +/*! @brief The event flags are cleared automatically or manually.*/ +typedef enum _osa_event_clear_mode_t +{ + kEventAutoClear = 0U, /*!< The flags of the event will be cleared automatically. */ + kEventManualClear = 1U /*!< The flags of the event will be cleared manually. */ +} osa_event_clear_mode_t; + +/*! @brief Locks the task scheduler or disables interrupt in critical section. */ +typedef enum _osa_critical_section_mode_t +{ + kCriticalLockSched = 0U, /*!< Lock scheduler in critical section. */ + kCriticalDisableInt = 1U /*!< Disable interrupt in critical selection. */ +} osa_critical_section_mode_t; + +/*! @brief Type for an event group object in mbed OS */ +typedef struct Eventmbedos +{ + osEventFlagsId_t eventHandler; /*!< mbed-OS event handler */ + mbed_rtos_storage_event_flags_t eventMem; + osa_event_clear_mode_t clearMode; /*!< Auto clear or manual clear */ +} event_t; + +/*! @brief Type for an mutex group object in mbed OS */ +typedef struct Mutexmbedos +{ + osMutexId_t mutexHandler; /*!< mbed-OS mutex handler */ + mbed_rtos_storage_mutex_t mutexMem; +} mutex_t; + +typedef struct +{ + uint32_t dummy; +} cust_hw_context_t; + +typedef struct +{ + cust_hw_context_t *hw_context; + + /* PORT_NOTE: utility_mutex is a mutex used to protect resources that + * might be accessed by multiple task/threads in a system. + * It is used by the ACQUIRE/RELEASE macros below. If the target + * system is single threaded then this mutex can be omitted and + * the macros should be blank.*/ + A_MUTEX_T utility_mutex; + /* PORT_NOTE: connectStateCB allows an app to get feedback/notification + * as the WIFI connection state changes. If used it should be populated + * with a function pointer by an IOCTL or system equivalent. */ + void *connectStateCB; + /* PORT_NOTE: pScanOut stores scan results in a buffer so that they + * can be retrieved aysnchronously by a User task. */ + // uint8_t* pScanOut; /* callers buffer to hold results. */ + // uint16_t scanOutSize;/* size of pScanOut buffer */ + // uint16_t scanOutCount;/* current fill count of pScanOut buffer */ + + /* PORT_NOTE: These 2 events are used to block & wake their respective + * tasks. */ + A_EVENT driverWakeEvent; /* wakes the driver thread */ + A_EVENT userWakeEvent; /* wakes blocked user threads */ + //#if T_SELECT_VER1 + A_EVENT sockSelectWakeEvent; /* wakes t_select */ + //#endif //T_SELECT_VER1 + //#endif + /* PORT_NOTE: These 2 elements provide pointers to system context. + * The pDriverParam is intended provide definition for info such as + * which GPIO's to use for the SPI bus. The pUpperCxt should be + * populated with a system specific object that is required when the + * driver calls any system API's. In case of multi interface, the + * different enet pointers are stored in the corresponding array index + */ + void *pDriverParam; /* param struct containing initialization params */ + void *pUpperCxt[WLAN_NUM_OF_DEVICES]; /* back pointer to the MQX enet object. */ + /* PORT_NOTE: pCommonCxt stores the drivers common context. It is + * accessed by the common source via GET_DRIVER_COMMON() below. */ + void *pCommonCxt; /* the common driver context link */ + boolean driverShutdown; /* used to shutdown the driver */ + void *promiscuous_cb; /* used to feed rx frames in promiscuous mode. */ + //#if ENABLE_P2P_MODE + void *p2pevtCB; + boolean p2pEvtState; + boolean p2pevtflag; + //#if MANUFACTURING_SUPPORT + uint32_t testCmdRespBufLen; + //#endif + // A_CUSTOM_HCD_CXT *customhcdcxt; + void *httpPostCb; /*callback handler for http post events*/ + void *httpPostCbCxt; + void *otaCB; /* callback handler for OTA event */ + void *probeReqCB; + +} cust_context_t; + +/*TODO: check return value */ +void a_free(void *addr, uint8_t id); +void *a_malloc(int32_t size, uint8_t id); +A_STATUS a_mutex_init(mutex_t *pMutex); +A_STATUS a_mutex_acquire(mutex_t *pMutex); +A_STATUS a_mutex_release(mutex_t *pMutex); +boolean a_is_mutex_valid(mutex_t *pMutex); +A_STATUS a_mutex_delete(mutex_t *pMutex); +A_STATUS a_event_delete(event_t *pEvent); +A_STATUS a_event_init(event_t *pEvent, osa_event_clear_mode_t clearMode); +A_STATUS a_event_clear(event_t *pEvent, uint32_t flagsToClear); +A_STATUS a_event_set(event_t *pEvent, uint32_t flagsToSet); +A_STATUS a_event_wait( + event_t *pEvent, uint32_t flagsToWait, boolean waitAll, uint32_t timeout, uint32_t *setFlags); +uint32_t a_time_get_msec(void); +void OSA_EnterCritical(osa_critical_section_mode_t mode); +void OSA_ExitCritical(osa_critical_section_mode_t mode); + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env_port.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env_port.h new file mode 100644 index 00000000000..62b9625c869 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_env_port.h @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WIFI_ENV_PORT_H__ +#define __WIFI_ENV_PORT_H__ + +/* + * This file contains definition of environment specific macros. + * This file cannot be included directly, use #include "wifi_common.h" + */ + +#ifndef __WIFI_PORT_H__ +#error "'wifi_env_port.h' cannot be included directly" +#endif + +/* TODO: find better place */ +#define WLAN_NUM_OF_DEVICES 1 + +#define configTICK_RATE_HZ (1000) + +#ifndef MSEC_TO_TICK +#define MSEC_TO_TICK(msec) \ + ((uint32_t)(msec) * (uint32_t)configTICK_RATE_HZ / 1000uL) +#endif + +#ifndef TICKS_TO_MSEC +#define TICKS_TO_MSEC(tick) ((tick)*1000uL / (uint32_t)configTICK_RATE_HZ) +#endif + +#ifndef RXBUFFER_ACCESS_INIT +#define RXBUFFER_ACCESS_INIT(pCxt) A_MUTEX_INIT(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef RXBUFFER_ACCESS_ACQUIRE +#define RXBUFFER_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef RXBUFFER_ACCESS_RELEASE +#define RXBUFFER_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef RXBUFFER_ACCESS_DESTROY +#define RXBUFFER_ACCESS_DESTROY(pCxt) A_MUTEX_DELETE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef TXQUEUE_ACCESS_INIT +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define TXQUEUE_ACCESS_INIT(pCxt) (A_OK) +#endif + +#ifndef TXQUEUE_ACCESS_ACQUIRE +#define TXQUEUE_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef TXQUEUE_ACCESS_RELEASE +#define TXQUEUE_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef TXQUEUE_ACCESS_DESTROY +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define TXQUEUE_ACCESS_DESTROY(pCxt) +#endif + +#ifndef IRQEN_ACCESS_INIT +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define IRQEN_ACCESS_INIT(pCxt) (A_OK) +#endif + +#ifndef IRQEN_ACCESS_ACQUIRE +#define IRQEN_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef IRQEN_ACCESS_RELEASE +#define IRQEN_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef IRQEN_ACCESS_DESTROY +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define IRQEN_ACCESS_DESTROY(pCxt) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_INIT +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define DRIVER_SHARED_RESOURCE_ACCESS_INIT(pCxt) (A_OK) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE +#define DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_RELEASE +#define DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_DESTROY +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define DRIVER_SHARED_RESOURCE_ACCESS_DESTROY(pCxt) +#endif + +#ifndef A_MUTEX_T +#define A_MUTEX_T mutex_t +#endif + +#ifndef A_MUTEX_INIT +#define A_MUTEX_INIT(mutex) a_mutex_init((mutex)) +#endif + +#ifndef A_MUTEX_ACQUIRE +#define A_MUTEX_ACQUIRE(mutex) a_mutex_acquire((mutex)) +#endif + +#ifndef A_MUTEX_RELEASE +#define A_MUTEX_RELEASE(mutex) a_mutex_release((mutex)) +#endif + +#ifndef A_IS_MUTEX_VALID +#define A_IS_MUTEX_VALID(mutex) a_is_mutex_valid((mutex)) +#endif + +#ifndef A_MUTEX_DELETE +#define A_MUTEX_DELETE(mutex) a_mutex_delete((mutex)) +#endif + +#ifndef A_EVENT +#define A_EVENT event_t +#endif + +#ifndef A_EVENT_FLAGS +#define A_EVENT_FLAGS event_t +#endif + +/* OSA replacement */ +#ifndef A_EVENT_DELETE +#define A_EVENT_DELETE(event) a_event_delete((event)) +#endif + +#ifndef A_EVENT_INIT +#define A_EVENT_INIT(event, autoclear) a_event_init((event), (autoclear)) +#endif + +#ifndef A_EVENT_CLEAR +#define A_EVENT_CLEAR(event, flags) a_event_clear((event), (flags)) +#endif + +#ifndef A_EVENT_SET +#define A_EVENT_SET(event, flags) a_event_set((event), (flags)) +#endif + +#ifndef A_EVENT_WAIT +#define A_EVENT_WAIT(event, flagsToWait, waitAll, timeout, setFlags) \ + a_event_wait((event), (flagsToWait), (waitAll), (timeout), (setFlags)) +#endif + +#ifndef A_TIME_GET_MSEC +#define A_TIME_GET_MSEC a_time_get_msec +#endif + +#ifndef A_CUSTOM_DRIVER_CONTEXT +#define A_CUSTOM_DRIVER_CONTEXT cust_context_t +#endif + +#ifndef GET_DRIVER_CXT +#define GET_DRIVER_CXT(pCxt) ((cust_context_t *)(pCxt)) +#endif + +#ifndef GET_DRIVER_COMMON +#define GET_DRIVER_COMMON(pCxt) ((A_DRIVER_CONTEXT *)(((cust_context_t *)(pCxt))->pCommonCxt)) +#endif + +#ifndef RXBUFFER_ACCESS_INIT +#define RXBUFFER_ACCESS_INIT(pCxt) A_MUTEX_INIT(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef RXBUFFER_ACCESS_ACQUIRE +#define RXBUFFER_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef RXBUFFER_ACCESS_RELEASE +#define RXBUFFER_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef RXBUFFER_ACCESS_DESTROY +#define RXBUFFER_ACCESS_DESTROY(pCxt) +A_MUTEX_DELETE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef TXQUEUE_ACCESS_INIT +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define TXQUEUE_ACCESS_INIT(pCxt) (A_OK) +#endif + +#ifndef TXQUEUE_ACCESS_ACQUIRE +#define TXQUEUE_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef TXQUEUE_ACCESS_RELEASE +#define TXQUEUE_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef TXQUEUE_ACCESS_DESTROY +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define TXQUEUE_ACCESS_DESTROY(pCxt) +#endif + +#ifndef IRQEN_ACCESS_INIT +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define IRQEN_ACCESS_INIT(pCxt) (A_OK) +#endif + +#ifndef IRQEN_ACCESS_ACQUIRE +#define IRQEN_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef IRQEN_ACCESS_RELEASE +#define IRQEN_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef IRQEN_ACCESS_DESTROY +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define IRQEN_ACCESS_DESTROY(pCxt) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_INIT +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define DRIVER_SHARED_RESOURCE_ACCESS_INIT(pCxt) (A_OK) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE +#define DRIVER_SHARED_RESOURCE_ACCESS_ACQUIRE(pCxt) A_MUTEX_ACQUIRE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_RELEASE +#define DRIVER_SHARED_RESOURCE_ACCESS_RELEASE(pCxt) A_MUTEX_RELEASE(&(GET_DRIVER_CXT(pCxt)->utility_mutex)) +#endif + +#ifndef DRIVER_SHARED_RESOURCE_ACCESS_DESTROY +/* because its the same mutex as RXBUFFER_ACCESS this is NOP */ +#define DRIVER_SHARED_RESOURCE_ACCESS_DESTROY(pCxt) +#endif + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_port.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_port.h new file mode 100644 index 00000000000..25cdb44fe12 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/env/wifi_port.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WIFI_PORT_H__ +#define __WIFI_PORT_H__ + +/* "wifi_env_port.h" macros can be overloaded here. + * This file can contain only porting macros, nothing else */ + +#include "wifi_env_port.h" + +extern A_STATUS WIFISHIELD_PowerUp(uint32_t enable); +#define CUSTOM_HW_POWER_UP_DOWN(pCxt, powerup) \ + WIFISHIELD_PowerUp(powerup) + +extern A_STATUS WIFIDRVS_SPI_InOutBuffer(uint8_t *pBuffer, uint16_t length, uint8_t doRead, boolean sync); +#define CUSTOM_BUS_INOUT_BUFFER(pCxt, pBuffer, length, doRead, sync) \ + WIFIDRVS_SPI_InOutBuffer((pBuffer), (length), (doRead), (sync)) + +extern A_STATUS WIFIDRVS_SPI_InOutToken(uint32_t OutToken, uint8_t DataSize, uint32_t *pInToken); +#define CUSTOM_BUS_INOUT_TOKEN(pCxt, oT, dS, pInT) \ + WIFIDRVS_SPI_InOutToken((oT), (dS), (pInT)) + +#define CUSTOM_BUS_START_TRANSFER(pCxt, sync) (A_OK) + +#define CUSTOM_BUS_COMPLETE_TRANSFER(pCxt, sync) (A_OK) + +extern A_STATUS WIFISHIELD_InitDrivers(void *param); +#define CUSTOM_HW_INIT(pCxt) WIFISHIELD_InitDrivers((pCxt)) + +extern A_STATUS WIFISHIELD_DeinitDrivers(void *param); +#define CUSTOM_HW_DEINIT(pCxt) WIFISHIELD_DeinitDrivers((pCxt)) + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/wifi_common.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/wifi_common.h new file mode 100644 index 00000000000..6d7effdd1b5 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/port/wifi_common.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __WIFI_COMMON_H__ +#define __WIFI_COMMON_H__ + +#include "athdefs.h" +#include "fsl_common.h" + +/* porting macros only, + * redirected to env, board fn */ +#include "wifi_port.h" + +/* enviroment related code */ +#include "wifi_env.h" + +/* board related code */ +#include "wifi_shield.h" + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/qcom_api.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/qcom_api.h new file mode 100644 index 00000000000..a9b8f4a7518 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/qcom_api.h @@ -0,0 +1,610 @@ +// Copyright (c) Qualcomm Atheros, Inc. +// All rights reserved. +// Redistribution and use in source and binary forms, with or without modification, are permitted (subject to +// the limitations in the disclaimer below) provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, this list of conditions and the +// following disclaimer. +// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the +// following disclaimer in the documentation and/or other materials provided with the distribution. +// - Neither the name of nor the names of its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS +// PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +// BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __QCOM_API_H__ +#define __QCOM_API_H__ + +#include "wmi.h" +#include "atheros_stack_offload.h" +#include "atheros_wifi.h" + + + + +/* NOTE: According 802.11 standard, the SSID can hold max 32B = 32 octets + * of unspecified content. However, the API treats SSID as an ASCII + * NULL terminated string of 32 chars max, so last 33th byte is + * reserved for last NULL char and '\0' won't be included in the + * SSID name. UTF8 encoding probably does not work as well. + * NOTE: 'ssid' member is a dummy array. Using nested struct allows to use + * sizeof() operator on QCOM_SSID pointer */ +typedef struct { + char ssid[33]; +} QCOM_SSID; + +/* EXAMPLE: + * QCOM_SSID ssid = QCOM_SSID_FROM_STR("my_ssid"); */ +#define QCOM_SSID_FROM_STR(str) ((QCOM_SSID){.ssid = (str)}) + +/* EXAMPLE: + * printf("%s", QCOM_SSID_TO_STR(ssid)); */ +#define QCOM_SSID_TO_STR(var) ((var).ssid) + + + + +/* NOTE: Pass-phrase must fit into 64B = 64 octets. The 65th + * byte is reserved for last NULL char. */ +typedef struct { + char passphrase[65]; +} QCOM_PASSPHRASE; + +/* EXAMPLE: + * QCOM_PASSPHRASE pass = QCOM_PASSPHRASE_FROM_STR("my_password"); */ +#define QCOM_PASSPHRASE_FROM_STR(str) ((QCOM_PASSPHRASE){.passphrase = (str)}) + +/* EXAMPLE: + * printf("%s", QCOM_PASSPHRASE_TO_STR(passphrase)); */ +#define QCOM_PASSPHRASE_TO_STR(var) ((var).passphrase) + + + + +/* NOTE: BSSID uses MAC addr */ +typedef struct { + uint8_t bssid[6]; +} QCOM_BSSID; + + +/* NOTE: Values must be shared amongst internals and API + * The name and place is probably not the best */ +typedef enum { + QCOM_ONCONNECT_EVENT_DISCONNECT = 0, + QCOM_ONCONNECT_EVENT_SUCCESS +} QCOM_ONCONNECT_EVENT; + + +/* 'ipconfig' enums */ +typedef enum +{ + QCOM_IPCONFIG_QUERY = IPCFG_QUERY, /*Retrieve IP parameters*/ + QCOM_IPCONFIG_STATIC = IPCFG_STATIC, /*Set static IP parameters*/ + QCOM_IPCONFIG_DHCP = IPCFG_DHCP, /*Run DHCP client*/ + QCOM_IPCONFIG_AUTO = IPCFG_AUTO, /*Run AUTO IP*/ +} QCOM_IPCONFIG_MODE; + + +#define QCOM_WPS_MAX_KEY_LEN 64 +#define WPS_MAX_DEVNAME_LEN 32 +#define MAX_SSID_LEN 32 +#define MAC_LEN 6 +#define MAX_SSID_LENGTH (32 + 1) +#define P2P_WPS_PIN_LEN 9 +#define MAX_PASSPHRASE_SIZE 64 +#define P2P_MAX_NOA_DESCRIPTORS 4 +#define WPS_MAX_PASSPHRASE_LEN 9 +#define P2P_PERSISTENT_FLAG 0x80 +#define MAX_LIST_COUNT 8 +#define P2P_AUTO_CHANNEL 0 +#define P2P_DEFAULT_CHAN 1 + +#define QCOM_PARAM_GROUP_SYSTEM 1 +#define QCOM_PARAM_GROUP_WLAN 2 +#define QCOM_PARAM_GROUP_NETWORK 3 + +/*define new param groups here*/ + +/*QCOM_PARAM_GROUP_SYSTEM Parameters*/ +#define QCOM_PARAM_GROUP_SYSTEM_SLEEP_MAINT_TIMEOUT_MSECS 1 +#define QCOM_PARAM_GROUP_SYSTEM_SLEEP_WATCHDOG_TIMEOUT_SECS 2 +/* Add new system tunables here, at the end */ + +/*QCOM_PARAM_GROUP_WLAN_Parameters*/ +#define QCOM_PARAM_GROUP_WLAN_WOW_ENABLE 1 +#define QCOM_PARAM_GROUP_WLAN_WOW_PATTERN 2 +#define QCOM_PARAM_GROUP_WLAN_WOW_GPIO 3 +#define QCOM_PARAM_GROUP_WLAN_WOW_HOSTSLEEP 4 + +/*QCOM_PARAM_GROUP_NETWORK_Parameters*/ +#define QCOM_PARAM_GROUP_NETWORK_DNS_TIMEOUT_SECS 1 + +#define QCOM_WOW_PATTERN_MAX_SIZE 8 + +typedef void *P2P_DEV_CTXT; +typedef void (*QCOM_PROMISCUOUS_CB)(unsigned char *buf, int length); + +typedef struct _qcom_scan_info +{ + uint8_t channel; + uint8_t ssid_len; + uint8_t rssi; + uint8_t security_enabled; + int16_t beacon_period; + uint8_t preamble; + uint8_t bss_type; + uint8_t bssid[6]; + uint8_t ssid[32]; + uint8_t rsn_cipher; + uint8_t rsn_auth; + uint8_t wpa_cipher; + uint8_t wpa_auth; +} QCOM_BSS_SCAN_INFO, *QCOM_BSS_SCAN_INFO_PTR; + +typedef struct _qcom_scan_params +{ + uint16_t fgStartPeriod; + uint16_t fgEndPeriod; + uint16_t bgPeriod; + uint16_t maxActChDwellTimeInMs; + uint16_t pasChDwellTimeInMs; + uint8_t shortScanRatio; + uint8_t scanCtrlFlags; + uint16_t minActChDwellTimeInMs; + uint16_t maxActScanPerSsid; + uint32_t maxDfsChActTimeInMs; +} qcom_scan_params_t; + +#define QCOM_START_SCAN_PARAMS_CHANNEL_LIST_MAX 12 + +typedef struct _qcom_start_scan_params +{ + boolean forceFgScan; + uint32_t homeDwellTimeInMs; + uint32_t forceScanIntervalInMs; + uint8_t scanType; + uint8_t numChannels; + uint16_t channelList[QCOM_START_SCAN_PARAMS_CHANNEL_LIST_MAX]; +} qcom_start_scan_params_t; + +typedef enum +{ + QCOM_WLAN_DEV_MODE_STATION = 0, + QCOM_WLAN_DEV_MODE_AP, + QCOM_WLAN_DEV_MODE_ADHOC, + QCOM_WLAN_DEV_MODE_INVALID +} QCOM_WLAN_DEV_MODE; + +typedef enum +{ + QCOM_11A_MODE = 0x1, + QCOM_11G_MODE = 0x2, + QCOM_11N_MODE = 0x3, + QCOM_11B_MODE = 0x4, + QCOM_HT40_MODE = 0x5, +} QCOM_WLAN_DEV_PHY_MODE; + +typedef enum +{ + WLAN_AUTH_NONE = 0, + WLAN_AUTH_WPA, + WLAN_AUTH_WPA2, + WLAN_AUTH_WPA_PSK, + WLAN_AUTH_WPA2_PSK, + WLAN_AUTH_WPA_CCKM, + WLAN_AUTH_WPA2_CCKM, + WLAN_AUTH_WPA2_PSK_SHA256, + WLAN_AUTH_WEP, + WLAN_AUTH_INVALID +} WLAN_AUTH_MODE; + +typedef enum +{ + WLAN_CRYPT_NONE = 0, + WLAN_CRYPT_WEP_CRYPT, + WLAN_CRYPT_TKIP_CRYPT, + WLAN_CRYPT_AES_CRYPT, + WLAN_CRYPT_WAPI_CRYPT, + WLAN_CRYPT_BIP_CRYPT, + WLAN_CRYPT_KTK_CRYPT, + WLAN_CRYPT_INVALID +} WLAN_CRYPT_TYPE; + +typedef enum { + WLAN_FRAME_BEACON = 0, + WLAN_FRAME_PROBE_REQ, + WLAN_FRAME_PROBE_RESP, + WLAN_FRAME_ASSOC_REQ, + WLAN_FRAME_ASSOC_RESP, + WLAN_FRAME_INVALID +} WLAN_MGMT_FRAME_TYPE; + +/* WPS credential information */ +typedef struct +{ + uint16_t ap_channel; + QCOM_SSID ssid; + uint8_t ssid_len; + WLAN_AUTH_MODE auth_type; /* WPS_AUTH_TYPE */ + WLAN_CRYPT_TYPE encr_type; /* WPS_ENCR_TYPE */ + uint8_t key_idx; + uint8_t key[QCOM_WPS_MAX_KEY_LEN + 1]; + uint8_t key_len; + uint8_t mac_addr[ATH_MAC_LEN]; +} qcom_wps_credentials_t; + +#if ENABLE_P2P_MODE + +typedef enum +{ + P2P_WPS_NOT_READY, + P2P_WPS_PIN_LABEL, + P2P_WPS_PIN_DISPLAY, + P2P_WPS_PIN_KEYPAD, + P2P_WPS_PBC +} P2P_WPS_METHOD; + +typedef struct +{ + uint8_t enable; + uint8_t count; + P2P_NOA_DESCRIPTOR noas[P2P_MAX_NOA_DESCRIPTORS]; +} P2P_NOA_INFO; + +typedef enum +{ + P2P_INV_ROLE_GO, + P2P_INV_ROLE_ACTIVE_GO, + P2P_INV_ROLE_CLIENT, +} P2P_INV_ROLE; + +typedef enum +{ + P2P_CONFIG_LISTEN_CHANNEL, + P2P_CONFIG_CROSS_CONNECT, + P2P_CONFIG_SSID_POSTFIX, + P2P_CONFIG_INTRA_BSS, + P2P_CONFIG_CONCURRENT_MODE, + P2P_CONFIG_GO_INTENT, + P2P_CONFIG_DEV_NAME, + P2P_CONFIG_P2P_OPMODE, + P2P_CONFIG_CCK_RATES, + P2P_CONFIG_MAX, +} P2P_CONF_ID; + +#endif // ENABLE_P2P_MODE + +typedef struct +{ + uint8_t addr[6]; +} A_MACADDR; + +typedef struct +{ + uint8_t rate_index; + uint8_t tries; + uint32_t size; + uint32_t chan; + uint8_t header_type; + uint16_t seq; + A_MACADDR addr1; + A_MACADDR addr2; + A_MACADDR addr3; + A_MACADDR addr4; + uint8_t *pdatabuf; + uint32_t buflen; +} QCOM_RAW_MODE_PARAM_t; + +typedef enum +{ + GPIO_EDGE_TRIGGER, + GPIO_LEVEL_TRIGGER +} QCOM_WOW_GPIO_TRIGGER; + +typedef struct +{ + uint32_t gpio; + boolean isActiveLow; + uint32_t triggerMechanism; /*0: edge triggered 1: level triggered*/ +} QCOM_WOW_GPIO; + +typedef struct +{ + uint32_t pattern_size; + uint32_t offset; + uint32_t pattern_index; + uint8_t pattern[QCOM_WOW_PATTERN_MAX_SIZE]; +} QCOM_WOW_PATTERN; + +typedef struct +{ + uint32_t enable; +} QCOM_WOW_ENABLE; + +typedef struct +{ + uint32_t awake; +} QCOM_WOW_HOST_SLEEP; + +#if ENABLE_STACK_OFFLOAD + +typedef struct sockaddr +{ + uint16_t sa_family; + char sa_data[32]; +} sockaddr_t; + +/*===================================================================================*/ +/* OTA */ +/* Set to upgrade Target FW. Otherwise, update customer image */ +#define QCOM_OTA_TARGET_FIRMWARE_UPGRADE (1 << 0) +/* Set to preserve the last active FW */ +#define QCOM_OTA_PRESERVE_LAST (1 << 1) +/* Set to erase upgrade partition rw dset */ +#define QCOM_OTA_ERASING_RW_DSET (1 << 2) +/* OTA Upgrade partitions */ +#define PARTITION_AUTO 0 /* Auto-select OTA partition */ + +typedef enum +{ + QCOM_OTA_PROTOCOL_TFTP = 0, + QCOM_OTA_PROTOCOL_FTP, + QCOM_OTA_PROTOCOL_HTTP, + QCOM_OTA_PROTOCOL_HTTPS, + QCOM_OTA_PROTOCOL_MAX = QCOM_OTA_PROTOCOL_TFTP, +} QCOM_OTA_PROTOCOL_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +int qcom_socket(int family, int type, int protocol); +int qcom_connect(int s, struct sockaddr *addr, int addrlen); +int qcom_bind(int s, struct sockaddr *addr, int addrlen); +int qcom_listen(int s, int backlog); +int qcom_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int qcom_setsockopt(int s, int level, int name, void *arg, int arglen); +int qcom_getsockopt(int s, int level, int name, void *arg, int arglen); +#if ZERO_COPY +int qcom_recv(int s, char **buf, int len, int flags); +#else +int qcom_recv(int s, char *buf, int len, int flags); +#endif + +#if ZERO_COPY +int qcom_recvfrom(int s, char **buf, int len, int flags, struct sockaddr *from, socklen_t *fromlen); +#else +int qcom_recvfrom(int s, char *buf, int len, int flags, struct sockaddr *from, socklen_t *fromlen); + +#endif +A_STATUS qcom_ipconfig(uint8_t device_id, QCOM_IPCONFIG_MODE mode, uint32_t *address, uint32_t *submask, uint32_t *gateway); +SSL *qcom_SSL_new(SSL_CTX *ctx); +SSL_CTX *qcom_SSL_ctx_new(SSL_ROLE_T role, int32_t inbufSize, int32_t outbufSize, int32_t reserved); +int32_t qcom_SSL_setCaList(SSL_CTX *ctx, SslCAList caList, uint32_t size); +int32_t qcom_SSL_addCert(SSL_CTX *ctx, SslCert cert, uint32_t size); +int32_t qcom_SSL_storeCert(char *name, SslCert cert, uint32_t size); +int32_t qcom_SSL_loadCert(SSL_CTX *ctx, SSL_CERT_TYPE_T type, char *name); +int32_t qcom_SSL_listCert(SSL_FILE_NAME_LIST *fileNames); +int32_t qcom_SSL_set_fd(SSL *ssl, uint32_t fd); +int32_t qcom_SSL_accept(SSL *ssl); +int32_t qcom_SSL_connect(SSL *ssl); +int32_t qcom_SSL_shutdown(SSL *ssl); +int32_t qcom_SSL_ctx_free(SSL_CTX *ctx); +int32_t qcom_SSL_configure(SSL *ssl, SSL_CONFIG *cfg); +#if ZERO_COPY +int32_t qcom_SSL_read(SSL *ssl, void **buf, int32_t num); +#else +int32_t qcom_SSL_read(SSL *ssl, void *buf, int32_t num); +#endif +int32_t qcom_SSL_write(SSL *ssl, const void *buf, int32_t num); + +int qcom_sendto(int s, char *buffer, int length, int flags, struct sockaddr *to, int tolen); +int qcom_send(int s, char *buffer, int length, int flags); +int qcom_socket_close(int s); +A_STATUS qcom_ip6_address_get(uint8_t device_id, + IP6_ADDR_T *v6Global, + IP6_ADDR_T *v6Link, + IP6_ADDR_T *v6DefGw, + IP6_ADDR_T *v6GlobalExtd, + int32_t *LinkPrefix, + int32_t *GlbPrefix, + int32_t *DefgwPrefix, + int32_t *GlbPrefixExtd); +A_STATUS qcom_ping(uint32_t host, uint32_t size); +A_STATUS qcom_ping_ms(uint32_t host, uint32_t size, uint32_t ms_interval); +A_STATUS qcom_ping6(uint8_t *host, uint32_t size); +A_STATUS qcom_ping6_ms(uint8_t *host, uint32_t size, uint32_t ms_interval); +A_STATUS qcom_ip6config_router_prefix( + uint8_t device_id, IP6_ADDR_T *addr, int32_t prefixlen, int32_t prefix_lifetime, int32_t valid_lifetime); +int32_t qcom_dhcps_set_pool(uint8_t device_id, uint32_t startip, uint32_t endip, int32_t leasetime); +A_STATUS qcom_http_server(int32_t enable); +A_STATUS qcom_http_set_post_cb(void *cxt, void *callback); +A_STATUS qcom_ip_http_server_method( + int32_t cmd, uint8_t *pagename, uint8_t *objname, int32_t objtype, int32_t objlen, uint8_t *value); +#if ENABLE_HTTP_CLIENT +A_STATUS qcom_http_client_method(uint32_t cmd, uint8_t *url, uint8_t *data, uint8_t *value); +#endif +#if ENABLE_ROUTING_CMDS +A_STATUS qcom_ip6_route(uint8_t device_id, + uint32_t cmd, + IP6_ADDR_T *ip6addr, + uint32_t *prefixLen, + IP6_ADDR_T *gw, + uint32_t *ifindex, + IPV6_ROUTE_LIST_T *rtlist); +A_STATUS qcom_ip4_route(uint8_t device_id, + uint32_t cmd, + IP_ADDR_T *addr, + IP_ADDR_T *subnet, + IP_ADDR_T *gw, + uint32_t *ifindex, + IPV4_ROUTE_LIST_T *rtlist); +#endif +A_STATUS qcom_tcp_conn_timeout(uint32_t timeout_val); +A_STATUS qcom_tcp_set_exp_backoff(uint8_t device_id, int32_t retry); +A_STATUS qcom_dhcps_release_pool(uint8_t device_id); +A_STATUS qcom_bridge_mode_enable(uint16_t bridgemode); +int32_t qcom_dhcps_register_cb(uint8_t device_id, void *callback); +int32_t qcom_dhcpc_register_cb(uint8_t device_id, void *callback); +#if ENABLE_DNS_CLIENT +A_STATUS qcom_dnsc_enable(boolean enable); +A_STATUS qcom_dnsc_add_server_address(uint8_t *ipaddress, uint8_t type); +A_STATUS qcom_dnsc_del_server_address(uint8_t *ipaddress, uint8_t type); +A_STATUS qcom_dnsc_get_host_by_name(char *pname, uint32_t *pipaddress); +A_STATUS qcom_dnsc_get_host_by_name2(char *pname, uint32_t *pipaddress, int32_t domain, uint32_t mode); +#endif + +#if ENABLE_DNS_SERVER +A_STATUS qcom_dns_server_address_get(uint32_t pdns[], uint32_t *number); +A_STATUS qcom_dnss_enable(boolean enable); +A_STATUS qcom_dns_local_domain(char *local_domain); +A_STATUS qcom_dns_entry_create(char *hostname, uint32_t ipaddress); +A_STATUS qcom_dns_entry_delete(char *hostname, uint32_t ipaddress); +A_STATUS qcom_dns_6entry_create(char *hostname, IP6_ADDR_T *ip6addr); +A_STATUS qcom_dns_6entry_delete(char *hostname, IP6_ADDR_T *ip6addr); +#endif + +#if ENABLE_SNTP_CLIENT +void qcom_sntp_srvr_addr(int flag, char *srv_addr); +void qcom_sntp_get_time(uint8_t device_id, tSntpTime *time); +void qcom_sntp_get_time_of_day(uint8_t device_id, tSntpTM *time); +void qcom_sntp_zone(int hour, int min, int add_sub, int enable); +void qcom_sntp_query_srvr_address(uint8_t device_id, tSntpDnsAddr *addr); +void qcom_enable_sntp_client(int enable); +#endif + +A_STATUS qcom_ota_upgrade(uint8_t device_id, + uint32_t addr, + char *filename, + uint8_t mode, + uint8_t preserve_last, + uint8_t protocol, + uint32_t *resp_code, + uint32_t *length); +A_STATUS qcom_ota_read_area(uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *ret_len); +A_STATUS qcom_ota_done(boolean good_image); +QCOM_OTA_STATUS_CODE_t qcom_ota_session_start(uint32_t flags, uint32_t partition_index); +uint32_t qcom_ota_partition_get_size(void); +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_erase(void); +QCOM_OTA_STATUS_CODE_t qcom_ota_parse_image_hdr(uint8_t *header, uint32_t *offset); +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_verify_checksum(void); +uint32_t qcom_ota_partition_read_data(uint32_t offset, uint8_t *buf, uint32_t size); +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_write_data(uint32_t offset, uint8_t *buf, uint32_t size, uint32_t *ret_size); +QCOM_OTA_STATUS_CODE_t qcom_ota_session_end(uint32_t good_image); +QCOM_OTA_STATUS_CODE_t qcom_ota_partition_format(uint32_t partition_index); +A_STATUS qcom_ota_set_callback(void *callback); +#endif + +#define qcom_set_scan(device_id, pScanParams) _qcom_set_scan(device_id, pScanParams) +A_STATUS _qcom_set_scan(uint8_t device_id, qcom_start_scan_params_t *pScanParams); +A_STATUS qcom_get_scan(uint8_t device_id, QCOM_BSS_SCAN_INFO **buf, int16_t *numResults); +A_STATUS qcom_set_ssid(uint8_t device_id, QCOM_SSID *pssid); +A_STATUS qcom_get_ssid(uint8_t device_id, QCOM_SSID *pssid); +A_STATUS qcom_scan_set_mode(uint8_t device_id, uint32_t mode); +A_STATUS qcom_set_connect_callback(uint8_t device_id, void *callback); +A_STATUS qcom_set_probe_req_callback(uint8_t device_id, void *callback); +A_STATUS qcom_enable_probe_req_event(uint8_t device_id, uint8_t enable); +A_STATUS qcom_commit(uint8_t device_id); +A_STATUS qcom_sta_get_rssi(uint8_t device_id, uint8_t *prssi); +A_STATUS qcom_sta_set_listen_time(uint8_t device_id, uint32_t listentime); +A_STATUS qcom_ap_set_beacon_interval(uint8_t device_id, uint16_t beacon_interval); +A_STATUS qcom_ap_hidden_mode_enable(uint8_t device_id, boolean enable); +A_STATUS qcom_op_get_mode(uint8_t device_id, QCOM_WLAN_DEV_MODE *pmode); +A_STATUS qcom_op_set_mode(uint8_t device_id, QCOM_WLAN_DEV_MODE mode); +A_STATUS qcom_disconnect(uint8_t device_id); +A_STATUS qcom_set_phy_mode(uint8_t device_id, uint8_t phymode); +A_STATUS qcom_get_phy_mode(uint8_t device_id, char **pphymode); +A_STATUS qcom_get_country_code(uint8_t device_id, uint8_t *countryCode); +A_STATUS qcom_set_country_code(uint8_t device_id, uint8_t *countryCode); +A_STATUS qcom_set_channel(uint8_t device_id, uint16_t channel); +A_STATUS qcom_get_channel(uint8_t device_id, uint16_t *pchannel); +A_STATUS qcom_set_tx_power(uint8_t device_id, uint32_t dbm); +A_STATUS qcom_allow_aggr_set_tid(uint8_t device_id, uint16_t tx_allow_aggr, uint16_t rx_allow_aggr); +A_STATUS qcom_sec_set_wepkey(uint8_t device_id, uint32_t keyindex, char *pkey); +A_STATUS qcom_sec_get_wepkey(uint8_t device_id, uint32_t keyindex, char *pkey); +A_STATUS qcom_sec_set_wepkey_index(uint8_t device_id, uint32_t keyindex); +A_STATUS qcom_sec_get_wepkey_index(uint8_t device_id, uint32_t *pkeyindex); +A_STATUS qcom_sec_set_auth_mode(uint8_t device_id, WLAN_AUTH_MODE mode); +A_STATUS qcom_sec_set_encrypt_mode(uint8_t device_id, WLAN_CRYPT_TYPE mode); +A_STATUS qcom_sec_set_passphrase(uint8_t device_id, QCOM_PASSPHRASE *passphrase); +A_STATUS qcom_sec_set_pmk(uint8_t device_id, char *pmk); + +A_STATUS qcom_power_set_mode(uint8_t device_id, uint32_t powerMode, uint8_t powerModule); +A_STATUS qcom_power_get_mode(uint8_t device_id, uint32_t *powerMode); +A_STATUS qcom_suspend_enable(boolean enable); +A_STATUS qcom_suspend_start(uint32_t susp_time); +A_STATUS qcom_power_set_parameters(uint8_t device_id, + uint16_t idlePeriod, + uint16_t psPollNum, + uint16_t dtimPolicy, + uint16_t tx_wakeup_policy, + uint16_t num_tx_to_wakeup, + uint16_t ps_fail_event_policy); +A_STATUS qcom_get_bssid(uint8_t device_id, uint8_t mac_addr[ATH_MAC_LEN]); + +A_STATUS qcom_sec_get_auth_mode(uint8_t device_id, uint32_t *pmode); +A_STATUS qcom_sec_get_encrypt_mode(uint8_t device_id, uint32_t *pmode); +A_STATUS qcom_sec_get_passphrase(uint8_t device_id, char *passphrase); + +A_STATUS qcom_wps_start(uint8_t device_id, int connect, int use_pinmode, char *pin); +A_STATUS qcom_wps_connect(uint8_t device_id); +A_STATUS qcom_wps_set_credentials(uint8_t device_id, qcom_wps_credentials_t *pwps_prof); + +#if ENABLE_P2P_MODE +A_STATUS qcom_p2p_func_init(uint8_t device_id, int32_t enable); +A_STATUS qcom_p2p_func_cancel(uint8_t device_id); +A_STATUS qcom_p2p_func_set_pass_ssid(uint8_t device_id, QCOM_PASSPHRASE *ppass, QCOM_SSID *pssid); +A_STATUS qcom_p2p_func_auth( + uint8_t device_id, int32_t dev_auth, P2P_WPS_METHOD wps_method, uint8_t *peer_mac, boolean persistent); +A_STATUS qcom_p2p_func_connect(uint8_t device_id, P2P_WPS_METHOD wps_method, uint8_t *peer_mac, boolean persistent); +A_STATUS qcom_p2p_func_set_config(uint8_t device_id, + uint32_t uigo_intent, + uint32_t uiclisten_ch, + uint32_t uiop_ch, + uint32_t uiage, + uint32_t reg_class, + uint32_t op_reg_class, + uint32_t max_node_count); +A_STATUS qcom_p2p_func_set_oppps(uint8_t device_id, uint8_t enable, uint8_t ctwin); +A_STATUS qcom_p2p_func_set_noa( + uint8_t device_id, uint8_t uccount, uint32_t uistart, uint32_t uiduration, uint32_t uiinterval); +A_STATUS qcom_p2p_func_invite( + uint8_t device_id, char *pssid, P2P_WPS_METHOD wps_method, uint8_t *pmac, boolean persistent, P2P_INV_ROLE role); +A_STATUS qcom_p2p_func_find(uint8_t device_id, void *dev, uint8_t type, uint32_t timeout); +A_STATUS qcom_p2p_func_stop_find(uint8_t device_id); +A_STATUS qcom_p2p_func_get_node_list(uint8_t device_id, void *app_buf, uint32_t buf_size); +A_STATUS qcom_p2p_func_get_network_list(uint8_t device_id, void *app_buf, uint32_t buf_size); +A_STATUS qcom_p2p_func_invite_auth(uint8_t device_id, uint8_t *inv); +A_STATUS qcom_p2p_func_listen(uint8_t device_id, uint32_t timeout); +A_STATUS qcom_p2p_func_join_profile(uint8_t device_id, uint8_t *pmac); +A_STATUS qcom_p2p_set(uint8_t device_id, P2P_CONF_ID config_id, void *data, uint32_t data_length); +A_STATUS qcom_p2p_func_prov(uint8_t device_id, P2P_WPS_METHOD wps_method, uint8_t *pmac); +A_STATUS qcom_p2p_func_join(uint8_t device_id, P2P_WPS_METHOD wps_method, uint8_t *pmac, char *ppin, uint16_t channel); +A_STATUS qcom_p2p_func_start_go( + uint8_t device_id, QCOM_SSID *pssid, QCOM_PASSPHRASE *ppass, int32_t channel, boolean ucpersistent); +#endif // ENABLE_P2P_MODE +A_STATUS qcom_raw_mode_send_pkt(QCOM_RAW_MODE_PARAM_t *ppara); +A_STATUS qcom_scan_params_set(uint8_t device_id, qcom_scan_params_t *pParam); +A_STATUS qcom_param_set( + uint8_t device_id, uint16_t grp_id, uint16_t param_id, void *data, uint32_t data_length, boolean wait_for_status); + +A_STATUS qcom_get_versionstr(ATH_VERSION_STR *versionstr); + +/* Workaround for 32 chars limitation of qcom_dns */ +A_STATUS qcom_dns_resolver(IP_ADDR_T dns_ip, char * hostname, IP_ADDR_T *host_ip, uint32_t timeout_ms); + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qca400x.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qca400x.c new file mode 100644 index 00000000000..8cfbe39ecd9 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qca400x.c @@ -0,0 +1,120 @@ +/**HEADER******************************************************************** +* +* Copyright (c) 2008 Freescale Semiconductor; +* All Rights Reserved +* +*************************************************************************** +* SPDX-License-Identifier: BSD-3-Clause +* +************************************************************************** +* +* $FileName: wlan_qca400x.c$ +* $Version : $ +* $Date : $ +* +* Comments: +* +* This file contains the function that reads the timer and returns +* the number of nanoseconds elapsed since the last interrupt. +* +*END************************************************************************/ + +#include +#include +#include "qcom_api.h" +#include "wlan_qcom.h" + +// ============================================================================ +// Definitions +// ============================================================================ + +//// SPI bus instance number used for WLAN chip communication +//#define SPI_INSTANCE_NUMBER SPI1_IDX +//// IRQ number for the WLAN chip interrupt +//#define WLAN_IRQ_NUMBER PORTC_IRQn +//// GPIO pin for the WLAN chip interrupt +//#define WLAN_IRQ_PIN GPIO_MAKE_PIN(GPIOC_IDX, 6) +//// GPIO pin for the WLAN power enable +//#define WLAN_CHIP_POWER_PIN GPIO_MAKE_PIN(GPIOB_IDX, 19) + +// ============================================================================ +// Globals +// ============================================================================ + +// This is the structure passed on to the QCA WIFI driver. +// It contains primarily SPI hardware configuration and little else +QCA_CONTEXT_STRUCT wifiCtx; + +// This is the WIFI function pointer struct defined in QCA driver file cust_api_init.c +extern const QCA_MAC_IF_STRUCT ATHEROS_WIFI_IF; + +/// SPI hardware configuration that is used by cust_spi_hcd.c - the QCA SPI driver +// struct wlan_hardware_config_s wlanHardwareConfig = { +// .spi_instance = SPI_INSTANCE_NUMBER, +// .spi_cs = kDspiPcs0, +// .wlan_irq_number = WLAN_IRQ_NUMBER, +// .wlan_power_pin = WLAN_CHIP_POWER_PIN, +//}; + +const QCA_IF_STRUCT ENET_0 = { + .MAC_IF = &ATHEROS_WIFI_IF, .MAC_NUMBER = 0, .PHY_NUMBER = 0, .PHY_ADDRESS = 0, +}; + +const QCA_PARAM_STRUCT ENET_default_params = { + .QCA_IF = &ENET_0, + .MODE = Auto_Negotiate, + .OPTIONS = 0, + .NUM_RX_PCBS = WLAN_CONFIG_NUM_PRE_ALLOC_RX_BUFFERS, // # Number of RX PCBs (Packet Control Blocks) + + // cust_spi_hcd.c - the QCA hardware specific SPI driver uses this config + // .MAC_PARAM = &wlanHardwareConfig, +}; + +// ============================================================================ +// WIFI Interrupt handler and Initialization +// ============================================================================ + +int numIrqs = 0; +int initTime = 0; + +/** Initialize the QCA400x WLAN driver and start the associated driver task + * This function MUST be called from a task/thread context + */ +int wlan_driver_start(void) +{ + uint32_t result = A_OK; + uint32_t time = 0; + + // Power off the WLAN and wait 30ms + CUSTOM_HW_POWER_UP_DOWN(NULL, false); + wait_us(30 * 1000); + + // Initialize WIFI driver by calling Custom_Api_Initialize() which + // allocates memory for various structures and starts the driver RTOS task + // represented by Atheros_Driver_Task() function. + // The driver task establishes SPI communication with the QCA400x chip and sets + // up various registers of the WLAN chip. + // Note that this initialization involves the currently running task to wait + // for the ready signal from the Atheros_Driver_Task() where upon we return + // from the function call. This process takes approximately 60ms. + time = A_TIME_GET_MSEC(); + wifiCtx.PARAM_PTR = &ENET_default_params; + result = ATHEROS_WIFI_IF.INIT(&wifiCtx); + if (A_OK != result) + { + return result; + } + + // Print init time + initTime = time = A_TIME_GET_MSEC() - time; + + // avoid SPI bus flood + qcom_power_set_mode(0, MAX_PERF_POWER, USER); + + return result; +} + +QCA_CONTEXT_STRUCT *wlan_get_context(void) +{ + return &wifiCtx; +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qcom.c b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qcom.c new file mode 100644 index 00000000000..c3a586d6939 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qcom.c @@ -0,0 +1,672 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// SDK Included Files +#include +#include +#include "qcom_api.h" +#include "wlan_qcom.h" + +// devId used for first argument of all the qcom API functions +static int devId = 0; + +// Values used by qcom_ipconfig() +struct network_ipv4_s +{ + uint32_t addr; + uint32_t mask; + uint32_t gateway; +} ipv4; + +static int _traceQcomApi = 0; + +// ============================================================================ +// Defines +// ============================================================================ + +// Convert IP address in uint32_t to comma separated bytes +#define UINT32_IPADDR_TO_CSV_BYTES(a) ((uint8_t)((a) >> 24) & 0xFF), (uint8_t)(((a) >> 16) & 0xFF), (uint8_t)(((a) >> 8) & 0xFF), (uint8_t)((a)&0xFF) +// Convert comma separated bytes to a uint32_t IP address +#define CSV_BYTES_TO_UINT32_IPADDR(a0, a1, a2, a3) \ + (((uint32_t)(a0)&0xFF) << 24) | (((uint32_t)(a1)&0xFF) << 16) | (((uint32_t)(a2)&0xFF) << 8) | ((uint32_t)(a3)&0xFF) +#define CONSTSTR_LEN(variable) (sizeof(variable) - 1) + +// ============================================================================ +// Utility Functions +// ============================================================================ + +static void printError(uint32_t value, const char *funcName) +{ + printf("ERROR: %s() returned %d\r\n", funcName, value); +} + +static int isQcomError(A_STATUS status, const char *funcName) +{ + if (status != A_OK) + { + printError(status, funcName); + } + else if (_traceQcomApi) + { + printf("%s() OK\r\n", funcName); + } + return (status != A_OK); +} + +static int isValueFailed(int32_t value, int32_t failValue, const char *funcName) +{ + if (value == failValue) + { + printError(value, funcName); + } + else if (_traceQcomApi) + { + printf("%s() OK\r\n", funcName); + } + return (value == failValue); +} + +/** Enable printing/tracing of QCOM functions calls + * @param enable 0 = disable + * 1 = enable + * -1 = toggle + * @return previous value + */ +int traceQcomApi(int enable) +{ + int oldValue = _traceQcomApi; + if (enable == -1) + _traceQcomApi = !_traceQcomApi; + else + _traceQcomApi = enable; + return oldValue; +} + +// ============================================================================ +// IP config and DHCP +// ============================================================================ + +// Although indicated in the QCA 80-Y9106-1 doc, this enum is unfortunately not defined +enum ipconfigActions +{ + IP_CONFIG_QUERY = 0, + IP_CONFIG_SET = 1, + IP_CONFIG_DHCP = 2, +}; + +int getDhcp(void) +{ + A_STATUS status; + + printf("Getting DHCP address...\r\n"); + + for (int32_t i = 20; i > 0; i--) + { + status = qcom_ipconfig(devId, QCOM_IPCONFIG_DHCP, &ipv4.addr, &ipv4.mask, &ipv4.gateway); + A_MDELAY(50); + status = qcom_ipconfig(devId, QCOM_IPCONFIG_QUERY, &ipv4.addr, &ipv4.mask, &ipv4.gateway); + if (ipv4.addr != 0) + { + break; + } + } + + if (isQcomError(status, "qcom_ipconfig")) + return A_ERROR; + + // Print the DNS servers we got from the DHCP server + uint32_t dnsServers[3]; + uint32_t num; + status = qcom_dns_server_address_get(dnsServers, &num); + if (isQcomError(status, "qcom_dns_server_address_get")) + { + printf("WARNING: No DNS servers returned by DHCP\r\n"); + printf(" You will NOT be able to resolve domain names\r\n"); + return A_ERROR; + } + + for (uint32_t i = 0; i < num; i++) + { + printf("DNS %d: %d.%d.%d.%d\r\n", i, UINT32_IPADDR_TO_CSV_BYTES(dnsServers[i])); + } + + printIpConfig(); + + return A_OK; +} + +void printIpConfig(void) +{ + A_STATUS status = qcom_ipconfig(devId, QCOM_IPCONFIG_QUERY, &ipv4.addr, &ipv4.mask, &ipv4.gateway); + isQcomError(status, "qcom_ipconfig"); + + printf("addr: %d.%d.%d.%d mask: %d.%d.%d.%d gw: %d.%d.%d.%d\r\n", UINT32_IPADDR_TO_CSV_BYTES(ipv4.addr), + UINT32_IPADDR_TO_CSV_BYTES(ipv4.mask), UINT32_IPADDR_TO_CSV_BYTES(ipv4.gateway)); +} + +// ============================================================================ +// Scanning and Access Point Connect/Disconnect +// ============================================================================ + +char _isConnected = 0; + +static void onConnect(uint8_t event, uint8_t devId, char *bssid, uint8_t bssConn) +{ + printf("EVENT: "); + + switch (event) + { + case 1: + if (devId == 0) + { + printf("%s connected\r\n", bssConn ? "AP" : "CLIENT"); + } + else + { + printf("Connected\r\n"); + } + // NOTE that station is not fully connected until PEER_FIRST_NODE_JOIN_EVENT + break; + case INVALID_PROFILE: + // this event is used to indicate RSNA failure + _isConnected = 0; + printf("4 way handshake failure for device=%d n", devId); + break; + case PEER_FIRST_NODE_JOIN_EVENT: + // this event is used to RSNA success + _isConnected = 1; + printf("4 way handshake success for device=%d\r\n", devId); + break; + case 0: + _isConnected = 0; + if (devId == 0) + { + printf("%s disconnect\r\n", bssConn ? "AP" : "CLIENT"); + } + break; + + default: + printf("code %d\r\n", event); + } +} + +int isConnected(void) +{ + return _isConnected; +} + +static void apConnectParamsPrint(void) +{ + A_STATUS status; + + printf("Reading connection params\r\n"); + + // Get current operational mode + QCOM_WLAN_DEV_MODE opMode = QCOM_WLAN_DEV_MODE_INVALID; + status = qcom_op_get_mode(devId, &opMode); + isQcomError(status, "qcom_op_get_mode"); + printf(" opMode=%d (%s)\r\n", opMode, (opMode == 0 ? "Station" : "AP")); + + char *phyMode = NULL; + status = qcom_get_phy_mode(devId, &phyMode); + isQcomError(status, "qcom_get_phy_mode"); + if (NULL != phyMode) + { + printf(" phyMode=%s\r\n", phyMode); + } + + // NOTE: Listed in QCA 80-Y9106-1 although not implemented by driver + // uint32_t authMode + // status = qcom_sec_get_auth_mode(devId, &authMode); + // checkForError(status, "qcom_sec_get_auth_mode"); + + QCOM_SSID ssidRead = {0}; + status = qcom_get_ssid(devId, &ssidRead); + isQcomError(status, "qcom_get_ssid"); + printf(" ssid=%s\r\n", ssidRead.ssid); +} + +static char *getSecurityStr(uint8_t auth, uint8_t cipher) +{ + static char s[100]; + char *p = s; + s[0] = 0; + + if (auth & SECURITY_AUTH_1X) + p += sprintf(p, "802.1X "); + if (auth & SECURITY_AUTH_PSK) + p += sprintf(p, "PSK "); + + p += sprintf(p, "/ "); + + if (cipher & ATH_CIPHER_TYPE_WEP) + p += sprintf(p, "WEP "); + if (cipher & ATH_CIPHER_TYPE_TKIP) + p += sprintf(p, "TKIP "); + if (cipher & ATH_CIPHER_TYPE_CCMP) + p += sprintf(p, "CCMP "); + + return s; +} + +void apScan(void) +{ + A_STATUS status; + + // NOTE: If scan is initiated when SSID is set to a value then only that SSID is scanned + status = qcom_set_scan(devId, NULL); + isQcomError(status, "qcom_set_scan"); + + // NOTE: calling qcom_get_scan() before qcom_set_scan() is the same as suspending for 5s, + // i.e. nothing happens for 5s where after 0 is returned + // NOTE: A maximum of 12 results are returned + QCOM_BSS_SCAN_INFO *scanResult; + int16_t scanNumResults = 0; + status = qcom_get_scan(devId, &scanResult, &scanNumResults); + isQcomError(status, "qcom_get_scan"); + // printf("qcom_get_scan numResults=%d\r\n", scanNumResults); + + printf(" i Ch RSSI MAC SSID\r\n"); + for (int i = 0; i < scanNumResults; i++) + { + QCOM_BSS_SCAN_INFO *scr = &scanResult[i]; + int ssidLen = scr->ssid_len; + scr->ssid[ssidLen] = 0; + + printf("%2d %2d %4d %02x:%02x:%02x:%02x:%02x:%02x %s\r\n", i, scr->channel, scr->rssi, scr->bssid[0], + scr->bssid[1], scr->bssid[2], scr->bssid[3], scr->bssid[4], scr->bssid[5], scr->ssid); + + if (scr->security_enabled) + { + if (scr->rsn_cipher == 0 && scr->wpa_cipher == 0) + { + printf(" WEP\r\n"); + } + else + { + char *secStr; + secStr = getSecurityStr(scr->rsn_auth, scr->rsn_cipher); + printf(" RSN: %s\r\n", secStr); + secStr = getSecurityStr(scr->wpa_auth, scr->wpa_cipher); + printf(" WPA: %s\r\n", secStr); + } + } + else + { + printf(" open AP\r\n"); + } + } + + printf("--------------------\r\n"); +} + +int apConnect(QCOM_SSID *ssid, QCOM_PASSPHRASE *passphrase, WLAN_AUTH_MODE auth, WLAN_CRYPT_TYPE cipher) +{ + A_STATUS status; + + // Set station mode to station (0) or AP (1) + status = qcom_op_set_mode(devId, QCOM_WLAN_DEV_MODE_STATION); + if (isQcomError(status, "qcom_op_set_mode")) { + return A_ERROR; + } + + // Optionally set the PHY mode + // status = qcom_set_phy_mode(devId, QCOM_11G_MODE); + // checkForError(status, "qcom_set_phy_mode"); + + // NOTE: qcom API requires to first set a valid SSID (before auth, cipher and passphrase) + status = qcom_set_ssid(devId, ssid); + if (isQcomError(status, "qcom_set_ssid")) { + return A_ERROR; + } + + status = qcom_sec_set_encrypt_mode(devId, cipher); + if (isQcomError(status, "qcom_sec_set_encrypt_mode")) { + return A_ERROR; + } + + // Note that only 4 of all modes listed in QCA 80-Y9106-1 are supported! + // The modes are: WLAN_AUTH_NONE, WLAN_AUTH_WPA_PSK, WLAN_AUTH_WPA2_PSK, WLAN_AUTH_WEP + status = qcom_sec_set_auth_mode(devId, auth); + if (isQcomError(status, "qcom_sec_set_auth_mode")) { + return A_ERROR; + } + + // NOTE: The driver insists that the SSID is configured *before* the passphrase + status = qcom_sec_set_passphrase(devId, passphrase); + if (isQcomError(status, "qcom_sec_set_passphrase")) { + return A_ERROR; + } + + + // The connect callback is actually used for four different callbacks: + // onConnect(1 (TRUE), uint8_t devId, uint8_t *ssid, uint8_t bssMac[6]); + // onDisconnect(status, uint8_t devId, uint8_t *ssid, uint8_t bssMac[6]); + // where status = 0x10 (INVALID_PROFILE) on ? + // = 0 on normal disconnect + // onRSNASuccessEvent(uint8_t code, uint8_t devId, NULL, 0) + // onBitRateEvent_tx(wmi_rateTable[rateIndex][0], devId, NULL, 0); + // It is not possible to discern the onBitRateEvent_tx event from the others + status = qcom_set_connect_callback(devId, (void *)onConnect); + if (isQcomError(status, "qcom_set_connect_callback")) { + return A_ERROR; + } + + apConnectParamsPrint(); + + status = qcom_commit(devId); + if (isQcomError(status, "qcom_commit")) { + return A_ERROR; + } + + return A_OK; +} + +int apDisconnect(void) +{ + A_STATUS status = qcom_disconnect(devId); + if (isQcomError(status, "qcom_disconnect")) { + return A_ERROR; + } + + return A_OK; +} + +// ============================================================================ +// Resolving and Pinging +// ============================================================================ + +uint32_t resolveHostname(const char *hostname) +{ + uint32_t addr = 0; + + // NOTE: This function returns the address in reverse byte order + A_STATUS status = qcom_dnsc_get_host_by_name((char *)hostname, &addr); + isQcomError(status, "qcom_dnsc_get_host_by_name"); + if (status == 0) + { + printf("Looked up %s as %d.%d.%d.%d\r\n", hostname, UINT32_IPADDR_TO_CSV_BYTES(addr)); + } + return addr; +} + +/** Ping given hostname + * If hostname is NULL then the gateway is used + */ +uint32_t pingHost(const char *hostname) +{ + // Default is to ping the gateway + uint32_t addr = ipv4.gateway; + + if (hostname != NULL) + { + addr = resolveHostname(hostname); + } + + // NOTE: qcom_ping() is a blocking function and has no timeout so it will + printf("Pinging %d.%d.%d.%d... ", UINT32_IPADDR_TO_CSV_BYTES(addr)); + uint32_t t = A_TIME_GET_MSEC(); + A_STATUS status = qcom_ping(addr, 10); + uint32_t elapsed = status; + if (status == 0) + { + elapsed = A_TIME_GET_MSEC() - t; + printf("OK (%d ms)\r\n", elapsed); + } + isQcomError(status, "qcom_ping"); + return elapsed; +} + +void resolveManyHosts(void) +{ + const char *hostnames[] = { + "google.com", "cr.yp.to", "kernel.org", "nxp.com", + }; + int numHosts = sizeof(hostnames) / sizeof(hostnames[0]); + for (int i = 0; i < numHosts; i++) + { + resolveHostname(hostnames[i]); + } +} + +// ============================================================================ +// UDP example +// ============================================================================ + +static int32_t udpSock = 0; +static char *udpRecvBuf = NULL; +static int udpRecvBufLen = 0; + +// IPv4 address of remote peer +static SOCKADDR_T remAddr; +static socklen_t remAddrLen; + +static void udpHelp(uint16_t port) +{ + printf("\r\n"); + printf("Test UDP echo server from your Unix workstation with the netcat command:\r\n"); + printf(" echo 'hello' | netcat -u -q1 %d.%d.%d.%d %d\r\n", UINT32_IPADDR_TO_CSV_BYTES(ipv4.addr), port); +} + +void udpBind(uint16_t port) +{ + A_STATUS status; + SOCKADDR_T localAddr; + + if (udpSock) + { + printf("UDP echo server socket already created\r\n"); + udpHelp(port); + return; + } + + udpSock = qcom_socket(ATH_AF_INET, SOCK_DGRAM_TYPE, 0); + if (isValueFailed(udpSock, -1, "qcom_socket")) + return; + + memset(&localAddr, 0, sizeof(localAddr)); + localAddr.sin_port = port; + localAddr.sin_family = ATH_AF_INET; + localAddr.sin_addr.s_addr = CSV_BYTES_TO_UINT32_IPADDR(0, 0, 0, 0); + + status = 0 == qcom_bind(udpSock, (struct sockaddr *)(&localAddr), sizeof(localAddr)) ? A_OK : A_ERROR; + if (isQcomError(status, "qcom_bind")) + return; + + printf("UDP echo server listening on port %d\r\n", port); + udpHelp(port); +} + +/** Poll for UDP packet for [timeout] ms + * Return -1 on timeout + * -9 if UDP socket hasn't been opened + * Otherwise, number of bytes received + */ +int udpPollAndRecv(int timeout) +{ + // Return immediately if UDP listen socket hasn't been created yet + if (udpSock == 0) + return -9; + + // NOTE: There is no qcom_select() function, only t_select() that polls only one socket + // NOTE: t_select() does NOT take a devId like all the other functions + QCA_CONTEXT_STRUCT *enetCtx = wlan_get_context(); + int32_t status = t_select(enetCtx, udpSock, timeout); + if (status == -1) + return A_ERROR; + + // Free the ZERO_COPY receive buffer (from previous call of this function) + if (udpRecvBuf != NULL) + { + // printf("Freeing old buffer\r\n"); + zero_copy_free(udpRecvBuf); + udpRecvBuf = NULL; + udpRecvBufLen = 0; + } + + // NOTE: when QCA400x library has been compiled with ZERO_COPY, the recvBuf + // is allocated by the qcom_recv() function and the user must free it afterwards! + // NOTE: qcom_recvfrom() buffer argument is of type char although it should be void + int received = qcom_recvfrom(udpSock, &udpRecvBuf, 500, 0, (struct sockaddr *)&remAddr, &remAddrLen); + if (received <= 0) + { + printf("qcom_recvfrom() ERROR: %d\r\n", received); + } + printf("UDP received %d bytes from %d.%d.%d.%d:%d\r\n", received, + UINT32_IPADDR_TO_CSV_BYTES(remAddr.sin_addr.s_addr), remAddr.sin_port); + + udpRecvBufLen = received; + return received; +} + +int udpSendEcho(void) +{ + // This is how you allocate a send buffer + char *sendBuf = custom_alloc(udpRecvBufLen); + if (sendBuf == NULL) + { + printError(0, "custom_alloc"); + return -1; + } + + // Copy received data into send buffer + memcpy(sendBuf, udpRecvBuf, udpRecvBufLen); + + int sent = qcom_sendto(udpSock, sendBuf, udpRecvBufLen, 0, (struct sockaddr *)&remAddr, remAddrLen); + printf("UDP sent/echoed %d bytes\r\n", sent); + + // After sending the buffer, remember to free it! + custom_free(sendBuf); + + return sent; +} + +// ============================================================================ +// TCP example +// ============================================================================ +const static char header_start[] = + "GET / HTTP/1.0\r\n" + "User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:50.0) Gecko/20100101 Firefox/50.0\r\n" + "Accept-Language: en-us\r\n" + "Host: "; +const static char header_end[] = "\r\n\r\n"; +static char gs_hostname[16] = {0}; + +void httpGet(const char *hostname, int timeout) +{ + int32_t sock = 0; + SOCKADDR_T addr; + A_STATUS status; + char *request_data = NULL; + char *response_data = NULL; + + printf("****************************************\r\n"); + + memset(&addr, 0, sizeof(addr)); + addr.sin_family = ATH_AF_INET; + if (hostname == NULL) + { + addr.sin_addr.s_addr = ipv4.gateway; + } + else + { + addr.sin_addr.s_addr = resolveHostname(hostname); + if (addr.sin_addr.s_addr == 0) + { + printf("ERROR: Failed to resolve %s\r\n", hostname); + return; + } + } + addr.sin_port = 80; + + do + { + /* Create TCP socket */ + sock = qcom_socket(ATH_AF_INET, SOCK_STREAM_TYPE, 0); + if (isValueFailed(sock, -1, "qcom_socket")) + break; + + /* Connect to remote */ + status = (A_STATUS)qcom_connect(sock, (struct sockaddr *)&addr, sizeof(addr)); + if (isQcomError(status, "qcom_connect")) + break; + + /* No explicit hostname, use gateway addr */ + if (hostname == NULL) + { + int32_t result = snprintf(gs_hostname, CONSTSTR_LEN(gs_hostname), "%u.%u.%u.%u", UINT32_IPADDR_TO_CSV_BYTES(ipv4.gateway)); + (void)result; + assert(result > 0); + hostname = gs_hostname; + } + + /* Allocate request_data of size that includes extra '\0' for string functions */ + uint32_t hostname_len = strlen(hostname); + uint32_t request_data_size = CONSTSTR_LEN(header_start) + hostname_len + CONSTSTR_LEN(header_end) + 1; + request_data = custom_alloc(request_data_size); + assert(!(NULL == request_data)); + if (NULL == request_data) + break; + memset(request_data, 0, request_data_size); + + /* Assemble HTTP header*/ + uint32_t request_data_i = 0, request_piece_size = 0; + /* Copy 'header_start' to request_data */ + request_piece_size = CONSTSTR_LEN(header_start); + memcpy(&request_data[request_data_i], header_start, request_piece_size); + request_data_i += request_piece_size; + /* Copy 'hostname' to 'request_data' */ + request_piece_size = hostname_len; + memcpy(&request_data[request_data_i], hostname, request_piece_size); + request_data_i += request_piece_size; + /* Copy 'header_end' to 'request_data' */ + request_piece_size = CONSTSTR_LEN(header_end); + memcpy(&request_data[request_data_i], header_end, request_piece_size); + request_data_i += request_piece_size; + + /* Send HTTP header in TCP request */ + printf("HTTP GET from %u.%u.%u.%u:%u\r\n", UINT32_IPADDR_TO_CSV_BYTES(addr.sin_addr.s_addr), addr.sin_port); + printf("%s\r\n", request_data); + int sent = qcom_send(sock, request_data, request_data_size, 0); + printf("TCP sent %d bytes\r\n", sent); + + /* Free request data */ + custom_free(request_data); + request_data = NULL; + if (sent < 0) + break; + + /* Block wait for response */ + printf("Waiting for response (with t_select)\r\n"); + if (timeout == 0) + timeout = 5000; + QCA_CONTEXT_STRUCT *enetCtx = wlan_get_context(); + status = (A_STATUS)t_select(enetCtx, sock, timeout); + if (status == A_ERROR) + break; + + /* Receive response */ + printf("qcom_recv() receiving response\r\n"); + int recvLen = qcom_recv(sock, &response_data, 1400, 0); + printf("TCP received %d bytes\r\n", recvLen); + if (recvLen >= 0) + { + response_data[recvLen] = 0; + printf("%s\r\n", response_data); + } + + /* Free 'receive_data' */ + if (response_data != NULL) + { + zero_copy_free(response_data); + } + } while (0); + + status = (A_STATUS)qcom_socket_close(sock); + isQcomError(status, "qcom_socket_close"); +} diff --git a/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qcom.h b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qcom.h new file mode 100644 index 00000000000..b70c0c009f8 --- /dev/null +++ b/components/wifi/COMPONENT_QCA400X_WIFI/wifi_qca/wlan_qcom/wlan_qcom.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// wlan_qca400x declarations +#if defined(__cplusplus) +extern "C" { +#endif + +int wlan_driver_start(void); +void wlan_hardware_gt202_init(void); +QCA_CONTEXT_STRUCT *wlan_get_context(void); + +// wlan_qcom declarations +int traceQcomApi(int enable); +void apScan(void); +int apConnect(QCOM_SSID *ssid, QCOM_PASSPHRASE *passphrase, WLAN_AUTH_MODE auth, WLAN_CRYPT_TYPE cipher); +int apDisconnect(void); +int isConnected(void); +void printIpConfig(void); +int getDhcp(void); +void pingGateway(void); +uint32_t pingHost(const char *hostname); +void resolveManyHosts(void); + +void udpBind(uint16_t port); +int udpPollAndRecv(int timeout); +int udpSendEcho(void); +void httpGet(const char *hostname, int timeout); + +#if defined(__cplusplus) +} +#endif + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf index 0034019b6d2..df4a9d70e8d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/device/TOOLCHAIN_IAR/LPC55S69_cm33_core0_flash.icf @@ -59,7 +59,7 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { } define symbol __stack_size__ = MBED_BOOT_STACK_SIZE; -define symbol __heap_size__ = 0x4000; +define symbol __heap_size__ = 0x8000; define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000200 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000001FF : 0; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h index d9e6105a4f7..75c88f54fcf 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core0.h @@ -24746,10 +24746,34 @@ typedef struct { /** OTP API base pointer */ #define OTP_API (ROM_API->otpApiBase) +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion() +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; + + if (0 == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if (1 == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} + /*! * @} */ /* end of group SDK_Compatibility_Symbols */ - #endif /* _LPC55S69_CM33_CORE0_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h index 8a4b751223e..3d7e7dd0e46 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/device/LPC55S69_cm33_core1.h @@ -24748,10 +24748,34 @@ typedef struct { /** OTP API base pointer */ #define OTP_API (ROM_API->otpApiBase) +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion() +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; + + if (0 == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if (1 == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} + /*! * @} */ /* end of group SDK_Compatibility_Symbols */ - #endif /* _LPC55S69_CM33_CORE1_H_ */ diff --git a/targets/targets.json b/targets/targets.json index 91869559ed0..aaacc40d859 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3147,7 +3147,8 @@ "MBED_TICKLESS" ], "components_add": [ - "FLASHIAP" + "FLASHIAP", + "QCA400X_WIFI" ], "extra_labels_add": [ "M33_NS", @@ -3190,6 +3191,9 @@ }, "OUTPUT_EXT": "hex", "bootloader_supported": true, + "overrides": { + "network-default-interface-type" : "WIFI" + }, "detect_code": [ "0236" ]