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Merged
0xc0170 merged 8 commits into from
Mar 11, 2021
Merged

STM32F4 update drivers version to CUBE V1.26.0 #14339

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3d1d3b7
STM32F4: align CMakeLists.txt for all families
jeromecoutant Feb 16, 2021
bccef1a
STM32F4: move TARGET_MTS_DRAGONFLY_F411RE info STM32F411xE
jeromecoutant Feb 18, 2021
82a3178
STM32F4: move TARGET_MTS_MDOT_F411RE info STM32F411xE
jeromecoutant Feb 18, 2021
6e90fd2
STM32F4 : add subfamilies in targets.json
jeromecoutant Feb 18, 2021
de27e83
STM32F4: move common files
jeromecoutant Feb 18, 2021
338e37a
STM32F4: license header alignment
jeromecoutant Feb 19, 2021
021aa00
STM32F4: STM32Cube_FW_F4_V1.26.0 - STM32Cube_FW
jeromecoutant Mar 9, 2021
c41ea5f
STM32F4: STM32Cube_FW_F4_V1.26.0 - Subfamilies
jeromecoutant Feb 18, 2021
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2 changes: 1 addition & 1 deletion targets/TARGET_STM/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
| F1 | 1.8.0 | https://github.com/STMicroelectronics/STM32CubeF1 |
| F2 | 1.6.0 | https://github.com/STMicroelectronics/STM32CubeF2 |
| F3 | 1.9.0 | https://github.com/STMicroelectronics/STM32CubeF3 |
| F4 | 1.25.0 | https://github.com/STMicroelectronics/STM32CubeF4 |
| F4 | 1.26.0 | https://github.com/STMicroelectronics/STM32CubeF4 |
| F7 | 1.16.0 | https://github.com/STMicroelectronics/STM32CubeF7 |
| G0 | 1.3.0 | https://github.com/STMicroelectronics/STM32CubeG0 |
| G4 | 1.1.0 | https://github.com/STMicroelectronics/STM32CubeG4 |
Expand Down
115 changes: 88 additions & 27 deletions ...M32F469xI/TARGET_SDP_K1/PeripheralNames.h → ...RGET_STM/TARGET_STM32F4/PeripheralNames.h
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@@ -1,33 +1,18 @@
/* mbed Microcontroller Library
*******************************************************************************
* SPDX-License-Identifier: BSD-3-Clause
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
******************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Copyright (c) 2015-2021 STMicroelectronics.
* All rights reserved.
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
******************************************************************************
*/

#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H

Expand All @@ -39,68 +24,144 @@ extern "C" {

typedef enum {
ADC_1 = (int)ADC1_BASE,
#if defined ADC2_BASE
ADC_2 = (int)ADC2_BASE,
#endif
#if defined ADC3_BASE
ADC_3 = (int)ADC3_BASE
#endif
} ADCName;

#if defined DAC_BASE
typedef enum {
DAC_1 = (int)DAC_BASE
} DACName;
#endif

typedef enum {
UART_1 = (int)USART1_BASE,
#if defined USART2_BASE
UART_2 = (int)USART2_BASE,
#endif
#if defined USART3_BASE
UART_3 = (int)USART3_BASE,
#endif
#if defined UART4_BASE
UART_4 = (int)UART4_BASE,
#endif
#if defined UART5_BASE
UART_5 = (int)UART5_BASE,
#endif
#if defined USART6_BASE
UART_6 = (int)USART6_BASE,
#endif
#if defined UART7_BASE
UART_7 = (int)UART7_BASE,
UART_8 = (int)UART8_BASE
#endif
#if defined UART8_BASE
UART_8 = (int)UART8_BASE,
#endif
#if defined UART9_BASE
UART_9 = (int)UART9_BASE,
#endif
#if defined UART10_BASE
UART_10 = (int)UART10_BASE,
#endif
} UARTName;

#define DEVICE_SPI_COUNT 6
typedef enum {
SPI_1 = (int)SPI1_BASE,
#if defined SPI2_BASE
SPI_2 = (int)SPI2_BASE,
#endif
#if defined SPI3_BASE
SPI_3 = (int)SPI3_BASE,
#endif
#if defined SPI4_BASE
SPI_4 = (int)SPI4_BASE,
#endif
#if defined SPI5_BASE
SPI_5 = (int)SPI5_BASE,
#endif
#if defined SPI6_BASE
SPI_6 = (int)SPI6_BASE
#endif
} SPIName;

typedef enum {
I2C_1 = (int)I2C1_BASE,
#if defined I2C2_BASE
I2C_2 = (int)I2C2_BASE,
I2C_3 = (int)I2C3_BASE
#endif
#if defined I2C3_BASE
I2C_3 = (int)I2C3_BASE,
#endif
#if defined FMPI2C1_BASE
FMPI2C_1 = (int)FMPI2C1_BASE
#endif
} I2CName;

typedef enum {
PWM_1 = (int)TIM1_BASE,
#if defined TIM2_BASE
PWM_2 = (int)TIM2_BASE,
#endif
#if defined TIM3_BASE
PWM_3 = (int)TIM3_BASE,
#endif
#if defined TIM4_BASE
PWM_4 = (int)TIM4_BASE,
#endif
#if defined TIM5_BASE
PWM_5 = (int)TIM5_BASE,
#endif
#if defined TIM8_BASE
PWM_8 = (int)TIM8_BASE,
#endif
#if defined TIM9_BASE
PWM_9 = (int)TIM9_BASE,
#endif
#if defined TIM10_BASE
PWM_10 = (int)TIM10_BASE,
#endif
#if defined TIM11_BASE
PWM_11 = (int)TIM11_BASE,
#endif
#if defined TIM12_BASE
PWM_12 = (int)TIM12_BASE,
#endif
#if defined TIM13_BASE
PWM_13 = (int)TIM13_BASE,
#endif
#if defined TIM14_BASE
PWM_14 = (int)TIM14_BASE
#endif
} PWMName;

#if DEVICE_CAN
typedef enum {
CAN_1 = (int)CAN1_BASE,
CAN_2 = (int)CAN2_BASE
#if defined CAN2_BASE
CAN_2 = (int)CAN2_BASE,
#endif
#if defined CAN3_BASE
CAN_3 = (int)CAN3_BASE
#endif
} CANName;
#endif

#if defined QSPI_R_BASE
typedef enum {
QSPI_1 = (int)QSPI_R_BASE,
} QSPIName;
#endif

typedef enum {
USB_FS = (int)USB_OTG_FS_PERIPH_BASE,
#if defined USB_OTG_HS_PERIPH_BASE
USB_HS = (int)USB_OTG_HS_PERIPH_BASE
#endif
} USBName;

#ifdef __cplusplus
Expand Down
7 changes: 0 additions & 7 deletions targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/CMakeLists.txt
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This file was deleted.

27 changes: 14 additions & 13 deletions targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xc.h
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Expand Up @@ -2281,17 +2281,18 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U


#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
Expand Down Expand Up @@ -2538,7 +2539,7 @@ typedef struct
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
Expand Down Expand Up @@ -2569,7 +2570,7 @@ typedef struct
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
Expand Down
27 changes: 14 additions & 13 deletions targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xe.h
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Expand Up @@ -2281,17 +2281,18 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U


#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
Expand Down Expand Up @@ -2538,7 +2539,7 @@ typedef struct
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
Expand Down Expand Up @@ -2569,7 +2570,7 @@ typedef struct
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
Expand Down
27 changes: 14 additions & 13 deletions targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f405xx.h
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Expand Up @@ -6373,17 +6373,18 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U


#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
Expand Down Expand Up @@ -7822,7 +7823,7 @@ typedef struct
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
Expand Down Expand Up @@ -7853,7 +7854,7 @@ typedef struct
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
Expand Down
27 changes: 14 additions & 13 deletions targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f407xx.h
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Expand Up @@ -6673,17 +6673,18 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U


#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
Expand Down Expand Up @@ -8122,7 +8123,7 @@ typedef struct
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
Expand Down Expand Up @@ -8153,7 +8154,7 @@ typedef struct
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
Expand Down
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