From b6fe6638f1051042db7035dc4012c774d0f1ee7d Mon Sep 17 00:00:00 2001 From: svastm Date: Wed, 25 May 2016 17:17:49 +0200 Subject: [PATCH 1/4] [STM32L1XX] Update HAL_Cube_L1 to 1.5 --- .../Release_Notes_stm32l1xx_hal.html | 1398 +-- .../TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S | 90 +- .../TOOLCHAIN_ARM_STD/startup_stm32l152xc.S | 88 +- .../TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S | 8 +- .../TOOLCHAIN_IAR/startup_stm32l152xc.S | 8 +- .../TARGET_MOTE_L152RC/stm32l152xc.h | 7291 ++++++++-------- .../TARGET_MOTE_L152RC/stm32l1xx.h | 47 +- .../TARGET_MOTE_L152RC/stm32l1xx_hal_conf.h | 6 +- .../TARGET_MOTE_L152RC/system_stm32l1xx.c | 34 +- .../TARGET_MOTE_L152RC/system_stm32l1xx.h | 11 +- .../TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S | 81 +- .../TOOLCHAIN_ARM_STD/startup_stm32l152xe.S | 81 +- .../TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S | 6 +- .../TOOLCHAIN_IAR/startup_stm32l152xe.S | 8 +- .../TARGET_NUCLEO_L152RE/stm32l152xe.h | 7654 +++++++++-------- .../TARGET_NUCLEO_L152RE/stm32l1xx.h | 46 +- .../TARGET_NUCLEO_L152RE/stm32l1xx_hal_conf.h | 8 +- .../TARGET_NUCLEO_L152RE/system_stm32l1xx.c | 35 +- .../TARGET_NUCLEO_L152RE/system_stm32l1xx.h | 11 +- .../TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S | 85 +- .../TOOLCHAIN_ARM_STD/startup_stm32l151xc.S | 85 +- .../TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S | 6 +- .../TARGET_NZ32_SC151/stm32l151xc.h | 7191 ++++++++-------- .../TARGET_NZ32_SC151/stm32l1xx.h | 45 +- .../TARGET_NZ32_SC151/stm32l1xx_hal_conf.h | 8 +- .../TARGET_NZ32_SC151/system_stm32l1xx.c | 34 +- .../TARGET_NZ32_SC151/system_stm32l1xx.h | 11 +- .../TARGET_STM32L1/stm32_hal_legacy.h | 2984 +++++++ .../TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c | 38 +- .../TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h | 113 +- .../TARGET_STM32L1/stm32l1xx_hal_adc.c | 1285 +-- .../TARGET_STM32L1/stm32l1xx_hal_adc.h | 960 ++- .../TARGET_STM32L1/stm32l1xx_hal_adc_ex.c | 395 +- .../TARGET_STM32L1/stm32l1xx_hal_adc_ex.h | 311 +- .../TARGET_STM32L1/stm32l1xx_hal_comp.c | 205 +- .../TARGET_STM32L1/stm32l1xx_hal_comp.h | 226 +- .../TARGET_STM32L1/stm32l1xx_hal_comp_ex.h | 18 +- .../TARGET_STM32L1/stm32l1xx_hal_cortex.c | 61 +- .../TARGET_STM32L1/stm32l1xx_hal_cortex.h | 322 +- .../TARGET_STM32L1/stm32l1xx_hal_crc.c | 21 +- .../TARGET_STM32L1/stm32l1xx_hal_crc.h | 8 +- .../TARGET_STM32L1/stm32l1xx_hal_cryp.c | 338 +- .../TARGET_STM32L1/stm32l1xx_hal_cryp.h | 77 +- .../TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c | 15 +- .../TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h | 10 +- .../TARGET_STM32L1/stm32l1xx_hal_dac.c | 184 +- .../TARGET_STM32L1/stm32l1xx_hal_dac.h | 119 +- .../TARGET_STM32L1/stm32l1xx_hal_dac_ex.c | 24 +- .../TARGET_STM32L1/stm32l1xx_hal_dac_ex.h | 27 +- .../TARGET_STM32L1/stm32l1xx_hal_def.h | 80 +- .../TARGET_STM32L1/stm32l1xx_hal_dma.c | 280 +- .../TARGET_STM32L1/stm32l1xx_hal_dma.h | 240 +- .../TARGET_STM32L1/stm32l1xx_hal_dma_ex.h | 24 +- .../TARGET_STM32L1/stm32l1xx_hal_flash.c | 536 +- .../TARGET_STM32L1/stm32l1xx_hal_flash.h | 283 +- .../TARGET_STM32L1/stm32l1xx_hal_flash_ex.c | 1016 +-- .../TARGET_STM32L1/stm32l1xx_hal_flash_ex.h | 555 +- .../stm32l1xx_hal_flash_ramfunc.c | 80 +- .../stm32l1xx_hal_flash_ramfunc.h | 21 +- .../TARGET_STM32L1/stm32l1xx_hal_gpio.c | 218 +- .../TARGET_STM32L1/stm32l1xx_hal_gpio.h | 150 +- .../TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h | 177 +- .../TARGET_STM32L1/stm32l1xx_hal_i2c.c | 1753 ++-- .../TARGET_STM32L1/stm32l1xx_hal_i2c.h | 344 +- .../TARGET_STM32L1/stm32l1xx_hal_i2s.c | 76 +- .../TARGET_STM32L1/stm32l1xx_hal_i2s.h | 56 +- .../TARGET_STM32L1/stm32l1xx_hal_irda.c | 280 +- .../TARGET_STM32L1/stm32l1xx_hal_irda.h | 282 +- .../TARGET_STM32L1/stm32l1xx_hal_iwdg.c | 65 +- .../TARGET_STM32L1/stm32l1xx_hal_iwdg.h | 144 +- .../TARGET_STM32L1/stm32l1xx_hal_lcd.c | 83 +- .../TARGET_STM32L1/stm32l1xx_hal_lcd.h | 58 +- .../TARGET_STM32L1/stm32l1xx_hal_nor.c | 452 +- .../TARGET_STM32L1/stm32l1xx_hal_nor.h | 177 +- .../TARGET_STM32L1/stm32l1xx_hal_opamp.c | 517 +- .../TARGET_STM32L1/stm32l1xx_hal_opamp.h | 190 +- .../TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c | 191 +- .../TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h | 73 +- .../TARGET_STM32L1/stm32l1xx_hal_pcd.c | 1406 +-- .../TARGET_STM32L1/stm32l1xx_hal_pcd.h | 117 +- .../TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c | 25 +- .../TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h | 18 +- .../TARGET_STM32L1/stm32l1xx_hal_pwr.c | 78 +- .../TARGET_STM32L1/stm32l1xx_hal_pwr.h | 145 +- .../TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c | 16 +- .../TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h | 11 +- .../TARGET_STM32L1/stm32l1xx_hal_rcc.c | 746 +- .../TARGET_STM32L1/stm32l1xx_hal_rcc.h | 2081 +++-- .../TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c | 322 +- .../TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h | 1002 ++- .../TARGET_STM32L1/stm32l1xx_hal_rtc.c | 86 +- .../TARGET_STM32L1/stm32l1xx_hal_rtc.h | 186 +- .../TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c | 407 +- .../TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h | 504 +- .../TARGET_STM32L1/stm32l1xx_hal_sd.c | 179 +- .../TARGET_STM32L1/stm32l1xx_hal_sd.h | 163 +- .../TARGET_STM32L1/stm32l1xx_hal_smartcard.c | 386 +- .../TARGET_STM32L1/stm32l1xx_hal_smartcard.h | 363 +- .../TARGET_STM32L1/stm32l1xx_hal_spi.c | 185 +- .../TARGET_STM32L1/stm32l1xx_hal_spi.h | 73 +- .../TARGET_STM32L1/stm32l1xx_hal_spi_ex.c | 13 +- .../TARGET_STM32L1/stm32l1xx_hal_spi_ex.h | 20 +- .../TARGET_STM32L1/stm32l1xx_hal_sram.c | 51 +- .../TARGET_STM32L1/stm32l1xx_hal_sram.h | 23 +- .../TARGET_STM32L1/stm32l1xx_hal_tim.c | 679 +- .../TARGET_STM32L1/stm32l1xx_hal_tim.h | 920 +- .../TARGET_STM32L1/stm32l1xx_hal_tim_ex.c | 85 +- .../TARGET_STM32L1/stm32l1xx_hal_tim_ex.h | 118 +- .../TARGET_STM32L1/stm32l1xx_hal_uart.c | 528 +- .../TARGET_STM32L1/stm32l1xx_hal_uart.h | 393 +- .../TARGET_STM32L1/stm32l1xx_hal_usart.c | 254 +- .../TARGET_STM32L1/stm32l1xx_hal_usart.h | 325 +- .../TARGET_STM32L1/stm32l1xx_hal_wwdg.c | 62 +- .../TARGET_STM32L1/stm32l1xx_hal_wwdg.h | 104 +- .../TARGET_STM32L1/stm32l1xx_ll_fsmc.c | 193 +- .../TARGET_STM32L1/stm32l1xx_ll_fsmc.h | 324 +- .../TARGET_STM32L1/stm32l1xx_ll_sdmmc.c | 31 +- .../TARGET_STM32L1/stm32l1xx_ll_sdmmc.h | 111 +- 118 files changed, 31128 insertions(+), 22123 deletions(-) create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32_hal_legacy.h diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/Release_Notes_stm32l1xx_hal.html b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/Release_Notes_stm32l1xx_hal.html index d459edfb289..ec4572157d9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/Release_Notes_stm32l1xx_hal.html +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/Release_Notes_stm32l1xx_hal.html @@ -1,24 +1,652 @@ + + + - - - - - - - - -Release Notes for STM32F4xx HAL Drivers - - - - - - - - + -
-

 

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+ - - - - + + + - +

Copyright +2016 STMicroelectronics

+

+ +
-

Back to Release page

-
+ +

Back to Release page

+

Release Notes for STM32L1xx HAL Drivers

-

Copyright - 2014 STMicroelectronics

-

-
-

 

- +

 

+
- - -
-

Update History

+		 +

Update History

V1.1.3 / 04-March-2016

+ +

Main Changes

  • Maintenance release to fix known defects and enhancements implementation.
  • Generic update:
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers.
    • Improve the update of the SystemCoreClock variable within the HAL Driver.
    • Split aAPBAHBPrescTable into aAHBPrescTable and aAPBPrescTable.
    • Reduce HSE_STARTUP_TIMEOUT from 5s to 100ms.
    • Reduce MSI_TIMEOUT_VALUE from 100ms to 2ms.
    • Reduce HSI_TIMEOUT_VALUE from 100ms to 2ms.
    • Reduce LSI_TIMEOUT_VALUE from 100ms to 2ms.
    • Reduce PLL_TIMEOUT_VALUE from 100ms to 2ms.
  • CORTEX:
    • __HAL_CORTEX_SYSTICKCLK_CONFIG is now deprecated. Prefer using HAL_SYSTICK_CLKSourceConfig function.
  • FLASH:
    • Correct issue preventing Cat.1 devices to write data in EEPROM.
  • I2C:
    • Add NACK management during wait on flag treatment.
    • Update the state machine.
    • It is now possible to use the I2C transmission with a data size of 0.
  • RCC:
    • Optimize HAL_RCC_ClockConfig.
    • LSEON is reset only if required inside HAL_RCC_OscConfig.
    • RCC HSE pre-scaler reconfiguration for LCD/RTC peripherical is now possible.
    • Backup domain are no more reseted when RTC clock source is changed from reset value.
  • SMARTCARD:
    • Update description of GuardTime and Prescaler fields in SMARTCARD_InitTypeDef structure.
  • UART:
    • HAL_LIN_SendBreak() now use IS_UART_LIN_INSTANCE instead of IS_UART_INSTANCE.
    • Correct the UART_BRR_SAMPLING8 macro in the case of cary handling.

V1.1.2 / 09-October-2015

+ +

Main Changes

  • Maintenance release to fix known defects and enhancements implementation.
  • ADC:
    • The ADC internal macro "IS_ADC_RANGE" is modified to take into account the ADC resolution.
    • The function HAL_ADC_PollForEvent, in case of timeout, returns HAL_TIMEOUT instead of HAL_ERROR.
    • HAL_ADC_Init +set the ADC handle in state HAL_ADC_ERROR_INTERNAL if the user try to +initialize the ADC in DiscontinuousConvMode and ContinuousConvMode +simultaneously, which is not possible.
    • Enhance the check for ScanConvMode in HAL_ADC_Init.
  • Cortex:
    • Corrected Misra error (MISRA C 2004 rule 10.5).
  • CRC:
    • Corrected the macro __HAL_CRC_SET_IDR.
  • GPIO:
    • corrected the macro GPIO_GET_INDEX.
    • To insure the same naming accross all STM32 families (F4, F2, F0, F1, L1 etc):
      • Replacing GPIO_SPEED_VERY_LOW by GPIO_SPEED_FREQ_LOW.
      • Replacing GPIO_SPEED_LOW by GPIO_SPEED_FREQ_MEDIUM.
      • Replacing GPIO_SPEED_MEDIUM by GPIO_SPEED_FREQ_HIGH.
      • Replacing GPIO_SPEED_HIGH by GPIO_SPEED_FREQ_VERY_HIGH.
  • IRDA:
    • Corrected the HAL_IRDA_IRQHandler which was preventing to handle 2 simultaneous errors.
  • I2C:
    • Corrected an issue where the STOP bit was not cleared after reading data depending on APB/I2C frequency.
  • I2S:
    • HAL_I2S_Transmit() is updated to keep the check on busy flag only for the slave.
  • PCD
    • Corrected issue when using USB Device double-buffering mode for IN endpoints.
    • do{ ... } while(0) is used for multi statement macros.
  • PWR:
    • Corrected Misra error (MISRA C 2004 rule 14.3).
  • RCC:
    • In HAL_RCCEx_PeriphCLKConfig, the reset of the backup domain occurs only if the RTC clock source has been changed.
    • __HAL_RCC_HSE_CONFIG is updated to remove the transition from RCC_HSE_ON to RCC_HSE_BYPASS.
    • Adding the macro __HAL_RCC_MCO1_CONFIG to configure the MCO clock.
    • Adding the macros and function to handle LSE CSS interrupt.
    • Corrected an error in HAL_RCC_GetSysClockFreq when the PLL is used as system clock. An incorrect sysclockfreq was returned.
  • RTC:
    • RTC_TimeTypeDef.SecondFraction +field is added to specifies the range or granularity of Sub Second +register content.This field will be used only by HAL_RTC_GetTime +function.
    • HAL_RTC_GetTime is updated to take into account the new field RTC_TimeTypeDef.SecondFraction.
    • Corrected error in __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG macro.
    • Add additionnal checks on WUTWF flag in HAL_RTCEx_SetWakeUpTimer_IT.
    • do{ ... } while(0) is used for multi statement macros.
  • USART:
    • Corrected the HAL_USART_IRQHandler which was preventing to handle 2 simultaneous errors.
  • UART:
    • Removed +the activation of  ERR IT  from HAL_UART_Transmit_IT() which +was leading to HAL_UART_IRQ_Handler wrong behavior.
    • Corrected the HAL_UART_IRQHandler which was preventing to handle 2 simultaneous errors.
  • SMARTCARD:
    • Corrected the HAL_SMARTCARD_IRQHandler which was preventing to handle 2 simultaneous errors.

V1.1.1 / 31-March-2015

+ +

Main Changes

  • Include path changes for compilation under Unix environment.
  • Update drivers to be C++ compliant.

Interface Changes

  • CORTEX : 
    • Added interface to access MPU features (refer to stm32l1xx_hal_cortex.h)
  • CRYP : 
    • Added Instance field in CRYP_HandleTypeDef.
      • HAL CRYP driver + updated to support multi instance, so user must ensure that the new + parameter Instance is initialized in his application(CRYPHandle.Instance + = CRYP)
  • FLASH : 
    • Changing field name of NOR_CFITypeDef (CFI1X changed to CFI1_X)
  • PCD :
    • HAL_PCD_ActiveRemoteWakeup renamed HAL_PCD_ActivateRemoteWakeup
    • HAL_PCD_DeActiveRemoteWakeup renamed to HAL_PCD_DeActivateRemoteWakeup
  • PWR :
    • HAL_PWR_PVDConfig renamed HAL_PWR_ConfigPVD
    • Added new interfaces:
  • void HAL_PWR_EnableSleepOnExit(void);
  • void HAL_PWR_DisableSleepOnExit(void);
  • void HAL_PWR_EnableSEVOnPend(void);
  • void HAL_PWR_DisableSEVOnPend(void);
  • void HAL_PWR_EnableSleepOnExit(void);
  • uint32_t HAL_PWREx_GetVoltageRange(void);
  • RCC :
    • HAL_RCC_CCSCallback renamed to HAL_RCC_CSSCallback
    • Adding HAL_RCCEx_GetPeriphCLKFreq interface.
  • PCD: 
    • HAL_PCD_ActiveRemoteWakeup renamed HAL_PCD_ActivateRemoteWakeup
    • HAL_PCD_DeActiveRemoteWakeup renamed to HAL_PCD_DeActivateRemoteWakeup
  • SMARTCARD: 
    • Removal of HAL_SMARTCARD_ReInit interface.
  • SPI: 
    • HAL_SPI_GetError now returns a uint32_t instead of HAL_SPI_ErrorTypeDef.
  • TIMER: 
    • Adding interface HAL_TIM_SlaveConfigSynchronization_IT
  • UART: 
    • The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.
  • USART: 
    • The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.

V1.1.0 / 16-January-2015

+ +

Main Changes

+ + + + -

V1.0.0 / 05-September-2014

+ +
    +
  • Add support of new STM32L1 eXtended devices - STM32l151xDX, STM32l152xDX & STM32l62xDX
  • HAL generic : Add eXtended Devices switchs when needed 
    • STM32L151xDX has same features than STM32L151xE
    • STM32L152xDX has same features than STM32L152xE
    • STM32L162xDX has same features than STM32L162xE
  • HAL FLASH : 
    • add support of new STM32L1 Devices (same as other HAL)
    • stm32l1xx_hal_flash_ex.c +: Specific treatment done in  HAL_FLASHEx_Erase & +HAL_FLASHEx_Erase_IT as memory is not continuous between 2 banks, user +should perform pages erase by bank only

V1.0.0 / 05-September-2014

Main Changes

@@ -929,44 +940,47 @@

-
  • First official release

    • License

    -
    +
    • First official release
    + + + + + + +

    License

    +
    Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
    -     +
    1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
    3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
           from this software without specific prior written permission.
    -
    +
    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    -
    +
    -

    For +

    For complete documentation on STM32 Microcontrollers visit www.st.com/STM32

    -
    -

    -
    +

    +
    -

     

    -
    - \ No newline at end of file diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S index 3ad2ad78151..f2d27c8e07d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S @@ -1,32 +1,47 @@ -; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l152xc.s +;* Author : MCD Application Team +;* Version : V2.1.3 +;* Date : 04-March-2016 +;* Description : STM32L152XC Devices vector for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* COPYRIGHT(c) 2016 STMicroelectronics +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +;******************************************************************************* ; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration @@ -37,7 +52,7 @@ Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 EXPORT __initial_sp - + Stack_Mem SPACE Stack_Size __initial_sp EQU 0x20008000 ; Top of RAM (32 KB) @@ -51,7 +66,7 @@ Heap_Size EQU 0x00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=3 EXPORT __heap_base EXPORT __heap_limit - + __heap_base Heap_Mem SPACE Heap_Size __heap_limit EQU (__initial_sp - Stack_Size) @@ -132,8 +147,8 @@ __Vectors DCD __initial_sp ; Top of Stack DCD 0 ; Reserved DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 + DCD 0 ; Reserved + DCD 0 ; Reserved DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 @@ -141,14 +156,14 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD 0 ; Reserved DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - + __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -229,7 +244,6 @@ Default_Handler PROC EXPORT DAC_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] EXPORT TIM9_IRQHandler [WEAK] EXPORT TIM10_IRQHandler [WEAK] EXPORT TIM11_IRQHandler [WEAK] @@ -250,10 +264,8 @@ Default_Handler PROC EXPORT USB_FS_WKUP_IRQHandler [WEAK] EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] @@ -308,8 +320,6 @@ TIM6_IRQHandler TIM7_IRQHandler TIM5_IRQHandler SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler @@ -323,3 +333,5 @@ COMP_ACQ_IRQHandler ALIGN END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S index 944c7b68129..2d06b6440e2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S @@ -1,31 +1,52 @@ -; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l152xc.s +;* Author : MCD Application Team +;* Version : V2.1.3 +;* Date : 04-March-2016 +;* Description : STM32L152XC Devices vector for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* COPYRIGHT(c) 2016 STMicroelectronics +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +;******************************************************************************* ; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; __initial_sp EQU 0x20008000 ; Top of RAM (32 KB) @@ -105,8 +126,8 @@ __Vectors DCD __initial_sp ; Top of Stack DCD 0 ; Reserved DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 + DCD 0 ; Reserved + DCD 0 ; Reserved DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 @@ -114,14 +135,14 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD 0 ; Reserved DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - + __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -202,7 +223,6 @@ Default_Handler PROC EXPORT DAC_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] EXPORT TIM9_IRQHandler [WEAK] EXPORT TIM10_IRQHandler [WEAK] EXPORT TIM11_IRQHandler [WEAK] @@ -223,10 +243,8 @@ Default_Handler PROC EXPORT USB_FS_WKUP_IRQHandler [WEAK] EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] @@ -281,8 +299,6 @@ TIM6_IRQHandler TIM7_IRQHandler TIM5_IRQHandler SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S index 8ff7570d7b2..6a5363041dd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32l152xc.s * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief STM32L152XC Devices vector table for * Atollic toolchain. * This module performs: @@ -17,7 +17,7 @@ * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -221,7 +221,7 @@ g_pfnVectors: .word 0 .word 0 .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32L152XE devices. */ + STM32L152XC devices. */ /******************************************************************************* * diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.S index 44c8aacb9c8..b4bf00c1968 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.S @@ -1,8 +1,8 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32l152xc.s ;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 5-September-2014 +;* Version : V2.1.3 +;* Date : 04-March-2016 ;* Description : STM32L152XC Devices vector for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -16,7 +16,7 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;*

    © COPYRIGHT(c) 2014 STMicroelectronics

    +;*

    © COPYRIGHT(c) 2016 STMicroelectronics

    ;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h index 7951485466a..fce76dbd30e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l152xc.h * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32L1xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -28,7 +28,7 @@ * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -65,10 +65,10 @@ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} @@ -88,6 +88,7 @@ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ @@ -218,7 +219,9 @@ typedef struct typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; @@ -630,86 +633,88 @@ typedef struct * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define FLASH_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH address for Cat3 */ -#define FLASH_EEPROM_END ((uint32_t)0x08081FFF) /*!< FLASH EEPROM end address (8KB) */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ +#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH address for Cat3 */ +#define FLASH_EEPROM_END ((uint32_t)0x08081FFFU) /*!< FLASH EEPROM end address (8KB) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) -#define LCD_BASE (APB1PERIPH_BASE + 0x00002400) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) +#define LCD_BASE (APB1PERIPH_BASE + 0x00002400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /* USB device FS SRAM */ -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) -#define DAC_BASE (APB1PERIPH_BASE + 0x00007400) -#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00) -#define RI_BASE (APB1PERIPH_BASE + 0x00007C04) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) +#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U) +#define RI_BASE (APB1PERIPH_BASE + 0x00007C04U) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) -#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800) -#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00) -#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400) -#define ADC_BASE (APB2PERIPH_BASE + 0x00002700) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002700U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< AHB peripherals */ -#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define RCC_BASE (AHBPERIPH_BASE + 0x00003800) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */ -#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ -#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058) -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00003800U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U) +#define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ /** * @} @@ -739,21 +744,29 @@ typedef struct #define USB ((USB_TypeDef *) USB_BASE) /* USB device FS SRAM */ #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +/* Legacy defines */ +#define DAC DAC1 + #define COMP ((COMP_TypeDef *) COMP_BASE) #define COMP1 ((COMP_TypeDef *) COMP_BASE) -#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001)) +#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) #define RI ((RI_TypeDef *) RI_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001)) +#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +/* Legacy defines */ +#define ADC ADC1_COMMON + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -804,531 +817,528 @@ typedef struct /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ -#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ -#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ -#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ -#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ +#define ADC_SR_AWD ((uint32_t)0x00000001U) /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOCS ((uint32_t)0x00000002U) /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_SR_JEOS ((uint32_t)0x00000004U) /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008U) /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010U) /*!< ADC group regular conversion start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020U) /*!< ADC group regular overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040U) /*!< ADC ready flag */ +#define ADC_SR_RCNR ((uint32_t)0x00000100U) /*!< ADC group regular not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200U) /*!< ADC group injected not ready flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOCS) +#define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ -#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ - +#define ADC_CR1_AWDCH ((uint32_t)0x0000001FU) /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_CR1_EOCSIE ((uint32_t)0x00000020U) /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040U) /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE ((uint32_t)0x00000080U) /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100U) /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400U) /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800U) /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000U) /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000U) /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000U) /*!< ADC power down during auto delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000U) /*!< ADC power down during idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CR1_RES ((uint32_t)0x03000000U) /*!< ADC resolution */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000U) /*!< ADC group regular overrun interrupt */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + /******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ +#define ADC_CR2_ADON ((uint32_t)0x00000001U) /*!< ADC enable */ +#define ADC_CR2_CONT ((uint32_t)0x00000002U) /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CFG ((uint32_t)0x00000004U) /*!< ADC channels bank selection */ -#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ -#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define ADC_CR2_DELS ((uint32_t)0x00000070U) /*!< ADC auto delay selection */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ +#define ADC_CR2_DMA ((uint32_t)0x00000100U) /*!< ADC DMA transfer enable */ +#define ADC_CR2_DDS ((uint32_t)0x00000200U) /*!< ADC DMA transfer configuration */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400U) /*!< ADC end of unitary or end of sequence conversions selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800U) /*!< ADC data alignement */ -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000U) /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000U) /*!< ADC group injected external trigger polarity */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000U) /*!< ADC group injected conversion start */ -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000U) /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ +#define ADC_CR2_EXTEN ((uint32_t)0x30000000U) /*!< ADC group regular external trigger polarity */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000U) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000U) /*!< Bit 1 */ -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x40000000U) /*!< ADC group regular conversion start */ /****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ -#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ -#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ -#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ -#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ -#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ -#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ -#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ -#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ -#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ -#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007U) /*!< ADC channel 20 sampling time selection */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038U) /*!< ADC channel 21 sampling time selection */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0U) /*!< ADC channel 22 sampling time selection */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00U) /*!< ADC channel 23 sampling time selection */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000U) /*!< ADC channel 24 sampling time selection */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000U) /*!< ADC channel 25 sampling time selection */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000U) /*!< ADC channel 26 sampling time selection */ +#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ -#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000U) /*!< ADC channel 19 sampling time selection */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000U) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR3 register *******************/ -#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ -#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000U) /*!< Bit 2 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ +#define ADC_HTR_HT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ +#define ADC_LTR_LT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ -#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ -#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define ADC_SQR1_L ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR1_L_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 28 */ +#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 27 */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 26 */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 25 */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ -#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ -#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ -#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ -#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ -#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ -#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 19 */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 20 */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 21 */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 22 */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 23 */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 24 */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ -#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ -#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 17 */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 18 */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR4 register *******************/ -#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR5 register *******************/ -#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001FU) /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0U) /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00U) /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000U) /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000U) /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ /******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */ /******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ -#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001U) /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_EOCS1 ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_CSR_JEOS1 ((uint32_t)0x00000004U) /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008U) /*!< ADC multimode master group injected conversion start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010U) /*!< ADC multimode master group regular conversion start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020U) /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040U) /*!< ADC multimode master ready flag */ + +/* Legacy defines */ +#define ADC_CSR_EOC1 (ADC_CSR_EOCS1) +#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000U) /*!< ADC clock source asynchronous prescaler */ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000U) /*!< ADC internal path to VrefInt and temperature sensor enable */ /******************************************************************************/ /* */ @@ -1337,33 +1347,33 @@ typedef struct /******************************************************************************/ /****************** Bit definition for COMP_CSR register ********************/ -#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ -#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ -#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ -#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ -#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ -#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ - -#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ -#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ -#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ -#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ -#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ -#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ -#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ -#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ -#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ - -#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ -#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ -#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ +#define COMP_CSR_10KPU ((uint32_t)0x00000001U) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002U) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004U) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008U) /*!< 400K pull-down resistor */ +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010U) /*!< Comparator 1 enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080U) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000U) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000U) /*!< Comparator 2 ouput */ +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000U) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000U) /*!< Window mode enable */ +#define COMP_CSR_INSEL ((uint32_t)0x001C0000U) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000U) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define COMP_CSR_FCH3 ((uint32_t)0x04000000U) /*!< Bit 26 */ +#define COMP_CSR_FCH8 ((uint32_t)0x08000000U) /*!< Bit 27 */ +#define COMP_CSR_RCH13 ((uint32_t)0x10000000U) /*!< Bit 28 */ + +#define COMP_CSR_CAIE ((uint32_t)0x20000000U) /*!< Bit 29 */ +#define COMP_CSR_CAIF ((uint32_t)0x40000000U) /*!< Bit 30 */ +#define COMP_CSR_TSUSP ((uint32_t)0x80000000U) /*!< Bit 31 */ /******************************************************************************/ /* */ @@ -1371,41 +1381,41 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for OPAMP_CSR register ******************/ -#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ -#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ -#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ -#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ -#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ -#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ -#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ -#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ -#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ -#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ -#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ -#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ -#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ -#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ -#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ -#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ -#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ -#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ +#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001U) /*!< OPAMP1 disable */ +#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002U) /*!< Switch 3 for OPAMP1 Enable */ +#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004U) /*!< Switch 4 for OPAMP1 Enable */ +#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008U) /*!< Switch 5 for OPAMP1 Enable */ +#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010U) /*!< Switch 6 for OPAMP1 Enable */ +#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020U) /*!< OPAMP1 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040U) /*!< OPAMP1 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080U) /*!< OPAMP1 Low power enable */ +#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100U) /*!< OPAMP2 disable */ +#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200U) /*!< Switch 3 for OPAMP2 Enable */ +#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400U) /*!< Switch 4 for OPAMP2 Enable */ +#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800U) /*!< Switch 5 for OPAMP2 Enable */ +#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000U) /*!< Switch 6 for OPAMP2 Enable */ +#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000U) /*!< OPAMP2 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000U) /*!< OPAMP2 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000U) /*!< OPAMP2 Low power enable */ +#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000U) /*!< Switch ANA Enable for OPAMP1 */ +#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000U) /*!< Switch ANA Enable for OPAMP2 */ +#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000U) /*!< Switch 7 for OPAMP2 Enable */ +#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000U) /*!< Power range selection */ +#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000U) /*!< OPAMP1 calibration output */ +#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000U) /*!< OPAMP2 calibration output */ /******************* Bit definition for OPAMP_OTR register ******************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ -#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ +#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000U) /*!< Switch to OPAMP offset user trimmed values */ /******************* Bit definition for OPAMP_LPOTR register ****************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ /******************************************************************************/ /* */ @@ -1414,13 +1424,13 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ +#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET bit */ /******************************************************************************/ /* */ @@ -1429,91 +1439,91 @@ typedef struct /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!
    © COPYRIGHT(c) 2014 STMicroelectronics
    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,14 +64,22 @@ * @{ */ +/** + * @brief STM32 Family + */ +#if !defined (STM32L1) +#define STM32L1 +#endif /* STM32L1 */ + + /* Uncomment the line below according to the target STM32L device used in your application */ #if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE) + !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ + !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ + !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ /* #define STM32L100xC */ /*!< STM32L100RC Devices */ @@ -80,16 +88,19 @@ /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ + /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ #define STM32L152xC /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ + /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ + /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ #endif @@ -107,16 +118,16 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.0.0 + * @brief CMSIS Device version number V2.1.3 */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ - |(__CMSIS_DEVICE_HAL_VERSION_RC)) +#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L1xx_CMSIS_VERSION_RC)) /** * @} @@ -142,6 +153,8 @@ #include "stm32l151xca.h" #elif defined(STM32L151xD) #include "stm32l151xd.h" +#elif defined(STM32L151xDX) + #include "stm32l151xdx.h" #elif defined(STM32L151xE) #include "stm32l151xe.h" #elif defined(STM32L152xB) @@ -154,6 +167,8 @@ #include "stm32l152xca.h" #elif defined(STM32L152xD) #include "stm32l152xd.h" +#elif defined(STM32L152xDX) + #include "stm32l152xdx.h" #elif defined(STM32L152xE) #include "stm32l152xe.h" #elif defined(STM32L162xC) @@ -162,6 +177,8 @@ #include "stm32l162xca.h" #elif defined(STM32L162xD) #include "stm32l162xd.h" +#elif defined(STM32L162xDX) + #include "stm32l162xdx.h" #elif defined(STM32L162xE) #include "stm32l162xe.h" #else diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx_hal_conf.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx_hal_conf.h index 360a2aa6ae9..257721085c7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx_hal_conf.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx_hal_conf.h @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32l1xx_hal_conf_template.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l1xx_hal_conf.h. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c index b0c277141a2..1df88e8f078 100755 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32l1xx.c * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from @@ -40,7 +40,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -146,6 +146,7 @@ uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */ const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -326,6 +327,25 @@ void SystemCoreClockUpdate (void) */ void SystemInit_ExtMemCtl(void) { + __IO uint32_t tmpreg = 0; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+------------------+ @@ -349,6 +369,9 @@ void SystemInit_ExtMemCtl(void) /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHBENR = 0x000080D8; + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); + /* Connect PDx pins to FSMC Alternate function */ GPIOD->AFR[0] = 0x00CC00CC; GPIOD->AFR[1] = 0xCCCCCCCC; @@ -401,6 +424,11 @@ void SystemInit_ExtMemCtl(void) /* Enable the FSMC interface clock */ RCC->AHBENR = 0x400080D8; + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + (void)(tmpreg); + /* Configure and enable Bank1_SRAM3 */ FSMC_Bank1->BTCR[4] = 0x00001011; FSMC_Bank1->BTCR[5] = 0x00000300; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h index 62e216539ae..bd1a46a23a4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l1xx.h * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S index c8427bfbc9c..cc46792371f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S @@ -1,32 +1,47 @@ -; STM32L152RE Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l152xe.s +;* Author : MCD Application Team +;* Version : V2.1.3 +;* Date : 04-March-2016 +;* Description : STM32L152XE Devices vector for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* COPYRIGHT(c) 2016 STMicroelectronics +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +;******************************************************************************* ; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration @@ -37,7 +52,7 @@ Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 EXPORT __initial_sp - + Stack_Mem SPACE Stack_Size __initial_sp EQU 0x20014000 ; Top of RAM (80 KB) @@ -51,7 +66,7 @@ Heap_Size EQU 0x00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=3 EXPORT __heap_base EXPORT __heap_limit - + __heap_base Heap_Mem SPACE Heap_Size __heap_limit EQU (__initial_sp - Stack_Size) @@ -141,14 +156,14 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD 0 ; Reserved DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - + __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -250,7 +265,7 @@ Default_Handler PROC EXPORT USB_FS_WKUP_IRQHandler [WEAK] EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] @@ -323,3 +338,5 @@ COMP_ACQ_IRQHandler ALIGN END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S index d1bf1611a26..5f6076e2f6f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S @@ -1,31 +1,52 @@ -; STM32L152RE Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l152xe.s +;* Author : MCD Application Team +;* Version : V2.1.3 +;* Date : 04-March-2016 +;* Description : STM32L152XE Devices vector for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* COPYRIGHT(c) 2016 STMicroelectronics +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +;******************************************************************************* ; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; __initial_sp EQU 0x20014000 ; Top of RAM (80 KB) @@ -114,14 +135,14 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 DCD 0 ; Reserved DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - + __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -223,7 +244,7 @@ Default_Handler PROC EXPORT USB_FS_WKUP_IRQHandler [WEAK] EXPORT TIM6_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] @@ -296,3 +317,5 @@ COMP_ACQ_IRQHandler ALIGN END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S index 4f4823c3cb5..b73559c9c5c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32l152xe.s * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief STM32L152XE Devices vector table for * Atollic toolchain. * This module performs: @@ -17,7 +17,7 @@ * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/startup_stm32l152xe.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/startup_stm32l152xe.S index 9b956b65e76..44c9f3c72d1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/startup_stm32l152xe.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/startup_stm32l152xe.S @@ -1,8 +1,8 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32l152xe.s ;* Author : MCD Application Team -;* Version : V2.0.0 -;* Date : 5-September-2014 +;* Version : V2.1.3 +;* Date : 04-March-2016 ;* Description : STM32L152XE Devices vector for EWARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -16,7 +16,7 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;*

    © COPYRIGHT(c) 2014 STMicroelectronics

    +;*

    © COPYRIGHT(c) 2016 STMicroelectronics

    ;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h index 127727d3161..2a57c801a60 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l152xe.h * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32L1xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -28,7 +28,7 @@ * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -65,10 +65,10 @@ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} @@ -88,6 +88,7 @@ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ @@ -220,7 +221,9 @@ typedef struct typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; @@ -645,92 +648,94 @@ typedef struct * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define FLASH_BANK2_BASE ((uint32_t)0x08040000) /*!< FLASH BANK2 base address in the alias region */ -#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH BANK1 address */ -#define FLASH_BANK2_END ((uint32_t)0x0807FFFF) /*!< Program end FLASH BANK2 address */ -#define FLASH_EEPROM_END ((uint32_t)0x08083FFF) /*!< FLASH EEPROM end address (16KB) */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ +#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FLASH_BANK2_BASE ((uint32_t)0x08040000U) /*!< FLASH BANK2 base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH BANK1 address */ +#define FLASH_BANK2_END ((uint32_t)0x0807FFFFU) /*!< Program end FLASH BANK2 address */ +#define FLASH_EEPROM_END ((uint32_t)0x08083FFFU) /*!< FLASH EEPROM end address (16KB) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) -#define LCD_BASE (APB1PERIPH_BASE + 0x00002400) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) -#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x00005000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) +#define LCD_BASE (APB1PERIPH_BASE + 0x00002400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /* USB device FS SRAM */ -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) -#define DAC_BASE (APB1PERIPH_BASE + 0x00007400) -#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00) -#define RI_BASE (APB1PERIPH_BASE + 0x00007C04) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) +#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U) +#define RI_BASE (APB1PERIPH_BASE + 0x00007C04U) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) -#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800) -#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00) -#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400) -#define ADC_BASE (APB2PERIPH_BASE + 0x00002700) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002700U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< AHB peripherals */ -#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400) -#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800) -#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define RCC_BASE (AHBPERIPH_BASE + 0x00003800) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */ -#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ -#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058) -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800U) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00003800U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U) +#define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ /** * @} @@ -762,21 +767,29 @@ typedef struct #define USB ((USB_TypeDef *) USB_BASE) /* USB device FS SRAM */ #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +/* Legacy defines */ +#define DAC DAC1 + #define COMP ((COMP_TypeDef *) COMP_BASE) #define COMP1 ((COMP_TypeDef *) COMP_BASE) -#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001)) +#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) #define RI ((RI_TypeDef *) RI_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001)) +#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +/* Legacy defines */ +#define ADC ADC1_COMMON + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -829,542 +842,554 @@ typedef struct /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ -#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ -#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ -#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ -#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ +#define ADC_SR_AWD ((uint32_t)0x00000001U) /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOCS ((uint32_t)0x00000002U) /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_SR_JEOS ((uint32_t)0x00000004U) /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008U) /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010U) /*!< ADC group regular conversion start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020U) /*!< ADC group regular overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040U) /*!< ADC ready flag */ +#define ADC_SR_RCNR ((uint32_t)0x00000100U) /*!< ADC group regular not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200U) /*!< ADC group injected not ready flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOCS) +#define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ -#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ - +#define ADC_CR1_AWDCH ((uint32_t)0x0000001FU) /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_CR1_EOCSIE ((uint32_t)0x00000020U) /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040U) /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE ((uint32_t)0x00000080U) /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100U) /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400U) /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800U) /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000U) /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000U) /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000U) /*!< ADC power down during auto delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000U) /*!< ADC power down during idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CR1_RES ((uint32_t)0x03000000U) /*!< ADC resolution */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000U) /*!< ADC group regular overrun interrupt */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + /******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ +#define ADC_CR2_ADON ((uint32_t)0x00000001U) /*!< ADC enable */ +#define ADC_CR2_CONT ((uint32_t)0x00000002U) /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CFG ((uint32_t)0x00000004U) /*!< ADC channels bank selection */ -#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ -#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define ADC_CR2_DELS ((uint32_t)0x00000070U) /*!< ADC auto delay selection */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ +#define ADC_CR2_DMA ((uint32_t)0x00000100U) /*!< ADC DMA transfer enable */ +#define ADC_CR2_DDS ((uint32_t)0x00000200U) /*!< ADC DMA transfer configuration */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400U) /*!< ADC end of unitary or end of sequence conversions selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800U) /*!< ADC data alignement */ -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000U) /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000U) /*!< ADC group injected external trigger polarity */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000U) /*!< ADC group injected conversion start */ -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000U) /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ +#define ADC_CR2_EXTEN ((uint32_t)0x30000000U) /*!< ADC group regular external trigger polarity */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000U) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000U) /*!< Bit 1 */ -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x40000000U) /*!< ADC group regular conversion start */ /****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ -#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ -#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ -#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ -#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ -#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ -#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ -#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ -#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ -#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ -#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007U) /*!< ADC channel 20 sampling time selection */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038U) /*!< ADC channel 21 sampling time selection */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0U) /*!< ADC channel 22 sampling time selection */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00U) /*!< ADC channel 23 sampling time selection */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000U) /*!< ADC channel 24 sampling time selection */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000U) /*!< ADC channel 25 sampling time selection */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000U) /*!< ADC channel 26 sampling time selection */ +#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000U) /*!< ADC channel 27 sampling time selection */ +#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000U) /*!< ADC channel 28 sampling time selection */ +#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000U) /*!< ADC channel 29 sampling time selection */ +#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000U) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ -#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000U) /*!< ADC channel 19 sampling time selection */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000U) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR3 register *******************/ -#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ -#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000U) /*!< Bit 2 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ +#define ADC_HTR_HT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ +#define ADC_LTR_LT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ -#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ -#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define ADC_SQR1_L ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR1_L_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 28 */ +#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 27 */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 26 */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 25 */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ -#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ -#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ -#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ -#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ -#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ -#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 19 */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 20 */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 21 */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 22 */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 23 */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 24 */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ -#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ -#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 17 */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 18 */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR4 register *******************/ -#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR5 register *******************/ -#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001FU) /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0U) /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00U) /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000U) /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000U) /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ /******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */ /****************** Bit definition for ADC_SMPR0 register *******************/ -#define ADC_SMPR0_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */ -#define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SMPR0_SMP30 ((uint32_t)0x00000007U) /*!< ADC channel 30 sampling time selection */ +#define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ -#define ADC_SMPR0_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */ -#define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */ +#define ADC_SMPR0_SMP31 ((uint32_t)0x00000038U) /*!< ADC channel 31 sampling time selection */ +#define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ /******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ -#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001U) /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_EOCS1 ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_CSR_JEOS1 ((uint32_t)0x00000004U) /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008U) /*!< ADC multimode master group injected conversion start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010U) /*!< ADC multimode master group regular conversion start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020U) /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040U) /*!< ADC multimode master ready flag */ + +/* Legacy defines */ +#define ADC_CSR_EOC1 (ADC_CSR_EOCS1) +#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000U) /*!< ADC clock source asynchronous prescaler */ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000U) /*!< ADC internal path to VrefInt and temperature sensor enable */ /******************************************************************************/ /* */ @@ -1373,34 +1398,34 @@ typedef struct /******************************************************************************/ /****************** Bit definition for COMP_CSR register ********************/ -#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ -#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ -#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ -#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ -#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ -#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */ -#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ - -#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ -#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ -#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ -#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ -#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ -#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ -#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ -#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ -#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ - -#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ -#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ -#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ +#define COMP_CSR_10KPU ((uint32_t)0x00000001U) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002U) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004U) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008U) /*!< 400K pull-down resistor */ +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010U) /*!< Comparator 1 enable */ +#define COMP_CSR_SW1 ((uint32_t)0x00000020U) /*!< SW1 analog switch enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080U) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000U) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000U) /*!< Comparator 2 ouput */ +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000U) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000U) /*!< Window mode enable */ +#define COMP_CSR_INSEL ((uint32_t)0x001C0000U) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000U) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define COMP_CSR_FCH3 ((uint32_t)0x04000000U) /*!< Bit 26 */ +#define COMP_CSR_FCH8 ((uint32_t)0x08000000U) /*!< Bit 27 */ +#define COMP_CSR_RCH13 ((uint32_t)0x10000000U) /*!< Bit 28 */ + +#define COMP_CSR_CAIE ((uint32_t)0x20000000U) /*!< Bit 29 */ +#define COMP_CSR_CAIF ((uint32_t)0x40000000U) /*!< Bit 30 */ +#define COMP_CSR_TSUSP ((uint32_t)0x80000000U) /*!< Bit 31 */ /******************************************************************************/ /* */ @@ -1408,41 +1433,41 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for OPAMP_CSR register ******************/ -#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ -#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ -#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ -#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ -#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ -#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ -#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ -#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ -#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ -#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ -#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ -#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ -#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ -#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ -#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ -#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ -#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ -#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ +#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001U) /*!< OPAMP1 disable */ +#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002U) /*!< Switch 3 for OPAMP1 Enable */ +#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004U) /*!< Switch 4 for OPAMP1 Enable */ +#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008U) /*!< Switch 5 for OPAMP1 Enable */ +#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010U) /*!< Switch 6 for OPAMP1 Enable */ +#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020U) /*!< OPAMP1 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040U) /*!< OPAMP1 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080U) /*!< OPAMP1 Low power enable */ +#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100U) /*!< OPAMP2 disable */ +#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200U) /*!< Switch 3 for OPAMP2 Enable */ +#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400U) /*!< Switch 4 for OPAMP2 Enable */ +#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800U) /*!< Switch 5 for OPAMP2 Enable */ +#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000U) /*!< Switch 6 for OPAMP2 Enable */ +#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000U) /*!< OPAMP2 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000U) /*!< OPAMP2 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000U) /*!< OPAMP2 Low power enable */ +#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000U) /*!< Switch ANA Enable for OPAMP1 */ +#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000U) /*!< Switch ANA Enable for OPAMP2 */ +#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000U) /*!< Switch 7 for OPAMP2 Enable */ +#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000U) /*!< Power range selection */ +#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000U) /*!< OPAMP1 calibration output */ +#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000U) /*!< OPAMP2 calibration output */ /******************* Bit definition for OPAMP_OTR register ******************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ -#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ +#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000U) /*!< Switch to OPAMP offset user trimmed values */ /******************* Bit definition for OPAMP_LPOTR register ****************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ /******************************************************************************/ /* */ @@ -1451,13 +1476,13 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ +#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET bit */ /******************************************************************************/ /* */ @@ -1466,91 +1491,91 @@ typedef struct /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!
    © COPYRIGHT(c) 2014 STMicroelectronics
    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,14 +64,22 @@ * @{ */ +/** + * @brief STM32 Family + */ +#if !defined (STM32L1) +#define STM32L1 +#endif /* STM32L1 */ + + /* Uncomment the line below according to the target STM32L device used in your application */ #if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE) + !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ + !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ + !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ /* #define STM32L100xC */ /*!< STM32L100RC Devices */ @@ -80,6 +88,7 @@ /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ + /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ @@ -90,6 +99,7 @@ /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ + /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ #endif @@ -107,16 +117,16 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.0.0 + * @brief CMSIS Device version number V2.1.3 */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ - |(__CMSIS_DEVICE_HAL_VERSION_RC)) +#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L1xx_CMSIS_VERSION_RC)) /** * @} @@ -142,6 +152,8 @@ #include "stm32l151xca.h" #elif defined(STM32L151xD) #include "stm32l151xd.h" +#elif defined(STM32L151xDX) + #include "stm32l151xdx.h" #elif defined(STM32L151xE) #include "stm32l151xe.h" #elif defined(STM32L152xB) @@ -154,6 +166,8 @@ #include "stm32l152xca.h" #elif defined(STM32L152xD) #include "stm32l152xd.h" +#elif defined(STM32L152xDX) + #include "stm32l152xdx.h" #elif defined(STM32L152xE) #include "stm32l152xe.h" #elif defined(STM32L162xC) @@ -162,6 +176,8 @@ #include "stm32l162xca.h" #elif defined(STM32L162xD) #include "stm32l162xd.h" +#elif defined(STM32L162xDX) + #include "stm32l162xdx.h" #elif defined(STM32L162xE) #include "stm32l162xe.h" #else diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx_hal_conf.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx_hal_conf.h index 360a2aa6ae9..d55af8432e1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx_hal_conf.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx_hal_conf.h @@ -1,16 +1,16 @@ /** ****************************************************************************** - * @file stm32l1xx_hal_conf_template.h + * @file stm32l1xx_hal_conf.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l1xx_hal_conf.h. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c index b5b3a8d48b2..6f51616e879 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32l1xx.c * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from @@ -40,7 +40,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -146,6 +146,7 @@ uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */ const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -326,6 +327,25 @@ void SystemCoreClockUpdate (void) */ void SystemInit_ExtMemCtl(void) { + __IO uint32_t tmpreg = 0; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+------------------+ @@ -349,6 +369,9 @@ void SystemInit_ExtMemCtl(void) /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHBENR = 0x000080D8; + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); + /* Connect PDx pins to FSMC Alternate function */ GPIOD->AFR[0] = 0x00CC00CC; GPIOD->AFR[1] = 0xCCCCCCCC; @@ -401,6 +424,11 @@ void SystemInit_ExtMemCtl(void) /* Enable the FSMC interface clock */ RCC->AHBENR = 0x400080D8; + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + (void)(tmpreg); + /* Configure and enable Bank1_SRAM3 */ FSMC_Bank1->BTCR[4] = 0x00001011; FSMC_Bank1->BTCR[5] = 0x00000300; @@ -558,6 +586,7 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_OFF; RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; // SYSCLK = 32 MHz ((16 MHz * 4) / 2) // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.h index 62e216539ae..bd1a46a23a4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l1xx.h * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S index a0b8161b23a..dabb5f03a4d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S @@ -1,32 +1,47 @@ -; STM32L151RC Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l151xc.s +;* Author : MCD Application Team +;* Version : V2.1.3 +;* Date : 04-March-2016 +;* Description : STM32L151XC Devices vector for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* COPYRIGHT(c) 2016 STMicroelectronics +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +;******************************************************************************* ; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration @@ -37,7 +52,7 @@ Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 EXPORT __initial_sp - + Stack_Mem SPACE Stack_Size __initial_sp EQU 0x20008000 ; Top of RAM (32 KB) @@ -51,7 +66,7 @@ Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 EXPORT __heap_base EXPORT __heap_limit - + __heap_base Heap_Mem SPACE Heap_Size __heap_limit EQU (__initial_sp - Stack_Size) @@ -108,7 +123,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DAC_IRQHandler ; DAC DCD COMP_IRQHandler ; COMP through EXTI Line DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD LCD_IRQHandler ; LCD + DCD 0 ; Reserved DCD TIM9_IRQHandler ; TIM9 DCD TIM10_IRQHandler ; TIM10 DCD TIM11_IRQHandler ; TIM11 @@ -139,16 +154,16 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD AES_IRQHandler ; AES + DCD 0 ; Reserved DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - + __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -229,7 +244,6 @@ Default_Handler PROC EXPORT DAC_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] EXPORT TIM9_IRQHandler [WEAK] EXPORT TIM10_IRQHandler [WEAK] EXPORT TIM11_IRQHandler [WEAK] @@ -257,7 +271,6 @@ Default_Handler PROC EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT DMA2_Channel4_IRQHandler [WEAK] EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] EXPORT COMP_ACQ_IRQHandler [WEAK] WWDG_IRQHandler @@ -284,7 +297,6 @@ USB_LP_IRQHandler DAC_IRQHandler COMP_IRQHandler EXTI9_5_IRQHandler -LCD_IRQHandler TIM9_IRQHandler TIM10_IRQHandler TIM11_IRQHandler @@ -312,7 +324,6 @@ DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler DMA2_Channel4_IRQHandler DMA2_Channel5_IRQHandler -AES_IRQHandler COMP_ACQ_IRQHandler B . diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S index 65af4f44fc6..2ed58cb45a7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S @@ -1,31 +1,52 @@ -; STM32L151RC Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2015, STMicroelectronics -; All rights reserved. +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l151xc.s +;* Author : MCD Application Team +;* Version : V2.1.3 +;* Date : 04-March-2016 +;* Description : STM32L151XC Devices vector for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* COPYRIGHT(c) 2016 STMicroelectronics +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: +;******************************************************************************* ; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; __initial_sp EQU 0x2008000 ; Top of RAM (32 KB) @@ -81,7 +102,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DAC_IRQHandler ; DAC DCD COMP_IRQHandler ; COMP through EXTI Line DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD LCD_IRQHandler ; LCD + DCD 0 ; Reserved DCD TIM9_IRQHandler ; TIM9 DCD TIM10_IRQHandler ; TIM10 DCD TIM11_IRQHandler ; TIM11 @@ -112,16 +133,16 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD AES_IRQHandler ; AES + DCD 0 ; Reserved DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - + __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY -; Reset handler +; Reset handler routine Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT __main @@ -202,7 +223,6 @@ Default_Handler PROC EXPORT DAC_IRQHandler [WEAK] EXPORT COMP_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] EXPORT TIM9_IRQHandler [WEAK] EXPORT TIM10_IRQHandler [WEAK] EXPORT TIM11_IRQHandler [WEAK] @@ -230,7 +250,6 @@ Default_Handler PROC EXPORT DMA2_Channel3_IRQHandler [WEAK] EXPORT DMA2_Channel4_IRQHandler [WEAK] EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] EXPORT COMP_ACQ_IRQHandler [WEAK] WWDG_IRQHandler @@ -257,7 +276,6 @@ USB_LP_IRQHandler DAC_IRQHandler COMP_IRQHandler EXTI9_5_IRQHandler -LCD_IRQHandler TIM9_IRQHandler TIM10_IRQHandler TIM11_IRQHandler @@ -285,7 +303,6 @@ DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler DMA2_Channel4_IRQHandler DMA2_Channel5_IRQHandler -AES_IRQHandler COMP_ACQ_IRQHandler B . diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S index e4c9a0214d1..853e7fb0581 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32l151xc.s * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief STM32L151XC Devices vector table for * Atollic toolchain. * This module performs: @@ -17,7 +17,7 @@ * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * - *

    © COPYRIGHT(c) 2015 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h index 29e3493bc4d..0aae2d7be00 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l151xc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l151xc.h * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32L1xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2015 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -28,7 +28,7 @@ * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -65,10 +65,10 @@ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} @@ -88,6 +88,7 @@ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ @@ -217,7 +218,9 @@ typedef struct typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; @@ -615,85 +618,87 @@ typedef struct * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define FLASH_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH address for Cat3 */ -#define FLASH_EEPROM_END ((uint32_t)0x08081FFF) /*!< FLASH EEPROM end address (8KB) */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ +#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH address for Cat3 */ +#define FLASH_EEPROM_END ((uint32_t)0x08081FFFU) /*!< FLASH EEPROM end address (8KB) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /* USB device FS SRAM */ -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) -#define DAC_BASE (APB1PERIPH_BASE + 0x00007400) -#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00) -#define RI_BASE (APB1PERIPH_BASE + 0x00007C04) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) +#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U) +#define RI_BASE (APB1PERIPH_BASE + 0x00007C04U) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) -#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800) -#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00) -#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400) -#define ADC_BASE (APB2PERIPH_BASE + 0x00002700) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002700U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< AHB peripherals */ -#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define RCC_BASE (AHBPERIPH_BASE + 0x00003800) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */ -#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ -#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058) -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00003800U) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U) +#define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ /** * @} @@ -722,21 +727,29 @@ typedef struct #define USB ((USB_TypeDef *) USB_BASE) /* USB device FS SRAM */ #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +/* Legacy defines */ +#define DAC DAC1 + #define COMP ((COMP_TypeDef *) COMP_BASE) #define COMP1 ((COMP_TypeDef *) COMP_BASE) -#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001)) +#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) #define RI ((RI_TypeDef *) RI_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001)) +#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +/* Legacy defines */ +#define ADC ADC1_COMMON + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) @@ -787,531 +800,528 @@ typedef struct /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ -#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ -#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ -#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ -#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ +#define ADC_SR_AWD ((uint32_t)0x00000001U) /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOCS ((uint32_t)0x00000002U) /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_SR_JEOS ((uint32_t)0x00000004U) /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008U) /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010U) /*!< ADC group regular conversion start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020U) /*!< ADC group regular overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040U) /*!< ADC ready flag */ +#define ADC_SR_RCNR ((uint32_t)0x00000100U) /*!< ADC group regular not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200U) /*!< ADC group injected not ready flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOCS) +#define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ -#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ - +#define ADC_CR1_AWDCH ((uint32_t)0x0000001FU) /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_CR1_EOCSIE ((uint32_t)0x00000020U) /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040U) /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE ((uint32_t)0x00000080U) /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100U) /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400U) /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800U) /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000U) /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000U) /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000U) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000U) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000U) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000U) /*!< ADC power down during auto delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000U) /*!< ADC power down during idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CR1_RES ((uint32_t)0x03000000U) /*!< ADC resolution */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000U) /*!< ADC group regular overrun interrupt */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + /******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ +#define ADC_CR2_ADON ((uint32_t)0x00000001U) /*!< ADC enable */ +#define ADC_CR2_CONT ((uint32_t)0x00000002U) /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CFG ((uint32_t)0x00000004U) /*!< ADC channels bank selection */ -#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ -#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define ADC_CR2_DELS ((uint32_t)0x00000070U) /*!< ADC auto delay selection */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010U) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020U) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040U) /*!< Bit 2 */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ +#define ADC_CR2_DMA ((uint32_t)0x00000100U) /*!< ADC DMA transfer enable */ +#define ADC_CR2_DDS ((uint32_t)0x00000200U) /*!< ADC DMA transfer configuration */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400U) /*!< ADC end of unitary or end of sequence conversions selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800U) /*!< ADC data alignement */ -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000U) /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000U) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000U) /*!< Bit 3 */ -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000U) /*!< ADC group injected external trigger polarity */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000U) /*!< ADC group injected conversion start */ -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000U) /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */ -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ +#define ADC_CR2_EXTEN ((uint32_t)0x30000000U) /*!< ADC group regular external trigger polarity */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000U) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000U) /*!< Bit 1 */ -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x40000000U) /*!< ADC group regular conversion start */ /****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ -#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ -#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ -#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ -#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ -#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ -#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ -#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ -#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ -#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ -#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007U) /*!< ADC channel 20 sampling time selection */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038U) /*!< ADC channel 21 sampling time selection */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0U) /*!< ADC channel 22 sampling time selection */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00U) /*!< ADC channel 23 sampling time selection */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000U) /*!< ADC channel 24 sampling time selection */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000U) /*!< ADC channel 25 sampling time selection */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000U) /*!< ADC channel 26 sampling time selection */ +#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ -#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000U) /*!< ADC channel 19 sampling time selection */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000U) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000U) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000U) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR3 register *******************/ -#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ -#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000U) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000U) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000U) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000U) /*!< Bit 2 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ +#define ADC_HTR_HT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ +#define ADC_LTR_LT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ -#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ -#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define ADC_SQR1_L ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR1_L_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 28 */ +#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 27 */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 26 */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 25 */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ -#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ -#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ -#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ -#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ -#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ -#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 19 */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 20 */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 21 */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 22 */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 23 */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 24 */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ -#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ -#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 17 */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 18 */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR4 register *******************/ -#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR5 register *******************/ -#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000U) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000U) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000U) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000U) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000U) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000U) /*!< Bit 4 */ /******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001FU) /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0U) /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00U) /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000U) /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000U) /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000U) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000U) /*!< Bit 1 */ /******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */ /******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ -#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001U) /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_EOCS1 ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ +#define ADC_CSR_JEOS1 ((uint32_t)0x00000004U) /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008U) /*!< ADC multimode master group injected conversion start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010U) /*!< ADC multimode master group regular conversion start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020U) /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040U) /*!< ADC multimode master ready flag */ + +/* Legacy defines */ +#define ADC_CSR_EOC1 (ADC_CSR_EOCS1) +#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000U) /*!< ADC clock source asynchronous prescaler */ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000U) /*!< ADC internal path to VrefInt and temperature sensor enable */ /******************************************************************************/ /* */ @@ -1320,33 +1330,33 @@ typedef struct /******************************************************************************/ /****************** Bit definition for COMP_CSR register ********************/ -#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ -#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ -#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ -#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ -#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ -#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ - -#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ -#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ -#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ -#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ -#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ -#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ -#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ -#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ -#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ - -#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ -#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ -#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ +#define COMP_CSR_10KPU ((uint32_t)0x00000001U) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002U) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004U) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008U) /*!< 400K pull-down resistor */ +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010U) /*!< Comparator 1 enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080U) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000U) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000U) /*!< Comparator 2 ouput */ +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000U) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000U) /*!< Window mode enable */ +#define COMP_CSR_INSEL ((uint32_t)0x001C0000U) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */ +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000U) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000U) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000U) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000U) /*!< Bit 2 */ + +#define COMP_CSR_FCH3 ((uint32_t)0x04000000U) /*!< Bit 26 */ +#define COMP_CSR_FCH8 ((uint32_t)0x08000000U) /*!< Bit 27 */ +#define COMP_CSR_RCH13 ((uint32_t)0x10000000U) /*!< Bit 28 */ + +#define COMP_CSR_CAIE ((uint32_t)0x20000000U) /*!< Bit 29 */ +#define COMP_CSR_CAIF ((uint32_t)0x40000000U) /*!< Bit 30 */ +#define COMP_CSR_TSUSP ((uint32_t)0x80000000U) /*!< Bit 31 */ /******************************************************************************/ /* */ @@ -1354,41 +1364,41 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for OPAMP_CSR register ******************/ -#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ -#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ -#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ -#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ -#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ -#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ -#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ -#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ -#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ -#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ -#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ -#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ -#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ -#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ -#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ -#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ -#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ -#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ +#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001U) /*!< OPAMP1 disable */ +#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002U) /*!< Switch 3 for OPAMP1 Enable */ +#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004U) /*!< Switch 4 for OPAMP1 Enable */ +#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008U) /*!< Switch 5 for OPAMP1 Enable */ +#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010U) /*!< Switch 6 for OPAMP1 Enable */ +#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020U) /*!< OPAMP1 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040U) /*!< OPAMP1 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080U) /*!< OPAMP1 Low power enable */ +#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100U) /*!< OPAMP2 disable */ +#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200U) /*!< Switch 3 for OPAMP2 Enable */ +#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400U) /*!< Switch 4 for OPAMP2 Enable */ +#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800U) /*!< Switch 5 for OPAMP2 Enable */ +#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000U) /*!< Switch 6 for OPAMP2 Enable */ +#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000U) /*!< OPAMP2 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000U) /*!< OPAMP2 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000U) /*!< OPAMP2 Low power enable */ +#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000U) /*!< Switch ANA Enable for OPAMP1 */ +#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000U) /*!< Switch ANA Enable for OPAMP2 */ +#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000U) /*!< Switch 7 for OPAMP2 Enable */ +#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000U) /*!< Power range selection */ +#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000U) /*!< OPAMP1 calibration output */ +#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000U) /*!< OPAMP2 calibration output */ /******************* Bit definition for OPAMP_OTR register ******************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ -#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ +#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000U) /*!< Switch to OPAMP offset user trimmed values */ /******************* Bit definition for OPAMP_LPOTR register ****************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ /******************************************************************************/ /* */ @@ -1397,13 +1407,13 @@ typedef struct /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ +#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET bit */ /******************************************************************************/ /* */ @@ -1412,91 +1422,91 @@ typedef struct /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!
    © COPYRIGHT(c) 2015 STMicroelectronics
    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,6 +64,12 @@ * @{ */ +/** + * @brief STM32 Family + */ +#if !defined (STM32L1) +#define STM32L1 +#endif /* STM32L1 */ //MODTRONIX BEGIN - HAL Defines /////////////////////////////////////////////// //Provide place for adding HAL defines. Alternative to adding them in IDE project properties. @@ -83,9 +89,9 @@ */ #if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE) + !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ + !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ + !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ /* #define STM32L100xC */ /*!< STM32L100RC Devices */ @@ -94,16 +100,19 @@ #define STM32L151xC /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ + /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ + /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ + /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ #endif @@ -121,16 +130,16 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.0.0 + * @brief CMSIS Device version number V2.1.3 */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ - |(__CMSIS_DEVICE_HAL_VERSION_RC)) +#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L1xx_CMSIS_VERSION_RC)) /** * @} @@ -156,6 +165,8 @@ #include "stm32l151xca.h" #elif defined(STM32L151xD) #include "stm32l151xd.h" +#elif defined(STM32L151xDX) + #include "stm32l151xdx.h" #elif defined(STM32L151xE) #include "stm32l151xe.h" #elif defined(STM32L152xB) @@ -168,6 +179,8 @@ #include "stm32l152xca.h" #elif defined(STM32L152xD) #include "stm32l152xd.h" +#elif defined(STM32L152xDX) + #include "stm32l152xdx.h" #elif defined(STM32L152xE) #include "stm32l152xe.h" #elif defined(STM32L162xC) @@ -176,6 +189,8 @@ #include "stm32l162xca.h" #elif defined(STM32L162xD) #include "stm32l162xd.h" +#elif defined(STM32L162xDX) + #include "stm32l162xdx.h" #elif defined(STM32L162xE) #include "stm32l162xe.h" #else diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx_hal_conf.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx_hal_conf.h index 7a22aa9ffaa..d7d437a6a61 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx_hal_conf.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/stm32l1xx_hal_conf.h @@ -1,16 +1,16 @@ /** ****************************************************************************** - * @file stm32l1xx_hal_conf_template.h + * @file stm32l1xx_hal_conf.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l1xx_hal_conf.h. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c index 9f4049e1d02..f34e8cd014a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32l1xx.c * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from @@ -40,7 +40,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2015 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -146,6 +146,7 @@ uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */ const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -326,6 +327,25 @@ void SystemCoreClockUpdate (void) */ void SystemInit_ExtMemCtl(void) { + __IO uint32_t tmpreg = 0; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+------------------+ @@ -349,6 +369,9 @@ void SystemInit_ExtMemCtl(void) /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHBENR = 0x000080D8; + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); + /* Connect PDx pins to FSMC Alternate function */ GPIOD->AFR[0] = 0x00CC00CC; GPIOD->AFR[1] = 0xCCCCCCCC; @@ -401,6 +424,11 @@ void SystemInit_ExtMemCtl(void) /* Enable the FSMC interface clock */ RCC->AHBENR = 0x400080D8; + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + (void)(tmpreg); + /* Configure and enable Bank1_SRAM3 */ FSMC_Bank1->BTCR[4] = 0x00001011; FSMC_Bank1->BTCR[5] = 0x00000300; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.h index 4ac46ec0759..bd1a46a23a4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l1xx.h * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 + * @version V2.1.3 + * @date 04-March-2016 * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2015 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,11 @@ variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32_hal_legacy.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32_hal_legacy.h new file mode 100644 index 00000000000..522ebc41351 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32_hal_legacy.h @@ -0,0 +1,2984 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @version V1.1.3 + * @date 04-March-2016 + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_HAL_LEGACY +#define __STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE ((uint32_t)0x00000000U) +#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) +#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + + + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#else +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR ((uint32_t)0x00000100U) +#define ETH_MMCRIR ((uint32_t)0x00000104U) +#define ETH_MMCTIR ((uint32_t)0x00000108U) +#define ETH_MMCRIMR ((uint32_t)0x0000010CU) +#define ETH_MMCTIMR ((uint32_t)0x00000110U) +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) +#define ETH_MMCTGFCR ((uint32_t)0x00000168U) +#define ETH_MMCRFCECR ((uint32_t)0x00000194U) +#define ETH_MMCRFAECR ((uint32_t)0x00000198U) +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) + +#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ +#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#if defined(STM32L0) +#define RCC_IT_LSECSS RCC_IT_CSSLSE +#define RCC_IT_CSS RCC_IT_CSSHSE +#endif + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c index 20d0b577f23..c273b5a8b18 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -72,11 +72,11 @@ */ /** - * @brief STM32L1xx HAL Driver version number V1.0.0 + * @brief STM32L1xx HAL Driver version number V1.1.3 */ #define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L1xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\ |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\ @@ -183,14 +183,14 @@ HAL_StatusTypeDef HAL_Init(void) HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ - __APB1_FORCE_RESET(); - __APB1_RELEASE_RESET(); + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); - __APB2_FORCE_RESET(); - __APB2_RELEASE_RESET(); + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); - __AHB_FORCE_RESET(); - __AHB_RELEASE_RESET(); + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); /* De-Init the low level hardware */ HAL_MspDeInit(); @@ -240,7 +240,7 @@ __weak void HAL_MspDeInit(void) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + HAL_SYSTICK_Config(SystemCoreClock /1000); /*Configure the SysTick IRQ priority */ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); @@ -384,7 +384,7 @@ uint32_t HAL_GetDEVID(void) * @brief Enable the Debug Module during SLEEP mode * @retval None */ -void HAL_EnableDBGSleepMode(void) +void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } @@ -393,7 +393,7 @@ void HAL_EnableDBGSleepMode(void) * @brief Disable the Debug Module during SLEEP mode * @retval None */ -void HAL_DisableDBGSleepMode(void) +void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } @@ -402,7 +402,7 @@ void HAL_DisableDBGSleepMode(void) * @brief Enable the Debug Module during STOP mode * @retval None */ -void HAL_EnableDBGStopMode(void) +void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } @@ -411,7 +411,7 @@ void HAL_EnableDBGStopMode(void) * @brief Disable the Debug Module during STOP mode * @retval None */ -void HAL_DisableDBGStopMode(void) +void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } @@ -420,7 +420,7 @@ void HAL_DisableDBGStopMode(void) * @brief Enable the Debug Module during STANDBY mode * @retval None */ -void HAL_EnableDBGStandbyMode(void) +void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } @@ -429,7 +429,7 @@ void HAL_EnableDBGStandbyMode(void) * @brief Disable the Debug Module during STANDBY mode * @retval None */ -void HAL_DisableDBGStandbyMode(void) +void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h index 98a5acfbb11..b6dfb3616ae 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_hal.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -369,114 +369,131 @@ * @brief TIM2 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_FREEZE_TIM2_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_UNFREEZE_TIM2_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) #endif /** * @brief TIM3 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_FREEZE_TIM3_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_UNFREEZE_TIM3_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) #endif /** * @brief TIM4 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#define __HAL_FREEZE_TIM4_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#define __HAL_UNFREEZE_TIM4_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) #endif /** * @brief TIM5 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#define __HAL_FREEZE_TIM5_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#define __HAL_UNFREEZE_TIM5_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) #endif /** * @brief TIM6 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_FREEZE_TIM6_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_UNFREEZE_TIM6_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) #endif /** * @brief TIM7 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_FREEZE_TIM7_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_UNFREEZE_TIM7_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) #endif /** * @brief RTC Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_FREEZE_RTC_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_UNFREEZE_RTC_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) #endif /** * @brief WWDG Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_FREEZE_WWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_UNFREEZE_WWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) #endif /** * @brief IWDG Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_FREEZE_IWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_UNFREEZE_IWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) #endif /** * @brief I2C1 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) #endif /** * @brief I2C2 Peripherals Debug mode */ #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) #endif /** * @brief TIM9 Peripherals Debug mode */ #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#define __HAL_FREEZE_TIM9_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#define __HAL_UNFREEZE_TIM9_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) #endif /** * @brief TIM10 Peripherals Debug mode */ #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#define __HAL_FREEZE_TIM10_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#define __HAL_UNFREEZE_TIM10_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) #endif /** * @brief TIM11 Peripherals Debug mode */ #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#define __HAL_FREEZE_TIM11_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#define __HAL_UNFREEZE_TIM11_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) #endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG + * @{ + */ + +/** @defgroup SYSCFG_VrefInt VREFINT configuration + * @{ + */ + /** * @brief Enables or disables the output of internal reference voltage * (VREFINT) on I/O pin. @@ -488,7 +505,7 @@ * Note: Comparator peripheral clock must be preliminarility enabled, * either in COMP user function "HAL_COMP_MspInit()" (should be * done if comparators are used) or by direct clock enable: - * Refer to macro "__COMP_CLK_ENABLE()". + * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()". * Note: In addition with this macro, Vrefint output buffer must be * connected to the selected I/O pin. Refer to macro * "__HAL_RI_IOSWITCH_CLOSE()". @@ -496,21 +513,13 @@ * @note DISABLE: Internal reference voltage disconnected from I/O group 3 * @retval None */ -#define __HAL_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) -#define __HAL_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) - -/** - * @} - */ +#define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) +#define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) /** * @} */ -/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG - * @{ - */ - /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration * @{ */ @@ -518,20 +527,20 @@ /** * @brief Main Flash memory mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) /** @brief System Flash memory mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) /** @brief Embedded SRAM mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) #if defined(FSMC_R_BASE) /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) +#define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) #endif /* FSMC_R_BASE */ @@ -922,12 +931,12 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); -void HAL_EnableDBGSleepMode(void); -void HAL_DisableDBGSleepMode(void); -void HAL_EnableDBGStopMode(void); -void HAL_DisableDBGStopMode(void); -void HAL_EnableDBGStandbyMode(void); -void HAL_DisableDBGStandbyMode(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c index 3c455c7c950..387cfd51cc3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c @@ -1,9 +1,9 @@ /** ****************************************************************************** * @file stm32l1xx_hal_adc.c - * @author MCD Application conversion - * @version V1.0.0 - * @date 5-September-2014 + * @author MCD Application Team + * @version V1.1.3 + * @date 04-March-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -11,10 +11,11 @@ * ++ Initialization and Configuration of ADC * + Operation functions * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. + * group, using 3 possible modes: polling, interruption or DMA. * + Control functions - * ++ Analog Watchdog configuration * ++ Channels configuration on regular group + * ++ Channels configuration on injected group + * ++ Analog Watchdog configuration * + State functions * ++ ADC state machine management * ++ Interrupts and flags management @@ -23,109 +24,239 @@ * @verbatim ============================================================================== - ##### ADC specific features ##### + ##### ADC peripheral features ##### ============================================================================== - [..] - (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution + [..] + (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution - (#) Interrupt generation at the end of regular conversion, end of injected + (+) Interrupt generation at the end of regular conversion, end of injected conversion, and in case of analog watchdog or overrun events. - (#) Single and continuous conversion modes. + (+) Single and continuous conversion modes. - (#) Scan mode for automatic conversion of channel 0 to channel 'n'. + (+) Scan mode for conversion of several channels sequentially. - (#) Data alignment with in-built data coherency. + (+) Data alignment with in-built data coherency. - (#) Channel-wise programmable sampling time. + (+) Programmable sampling time (channel wise) - (#) ADC conversion Regular or Injected groups. - - (#) External trigger (timer or EXTI) with configurable polarity for both - regular and injected groups. - - (#) DMA request generation for transfer of conversions data of regular group. + (+) ADC conversion of regular group and injected group. - (#) ADC calibration - - (#) ADC offset on injected channels - - (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + (+) External trigger (timer or EXTI) with configurable polarity + for both regular and injected groups. + + (+) DMA request generation for transfer of conversions data of regular group. + + (+) ADC offset on injected channels + + (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed. - (#) ADC input range: from Vref– (connected to Vssa) to Vref+ (connected to + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). - - + + ##### How to use this driver ##### ============================================================================== [..] - (#) Enable the ADC interface - As prerequisite, ADC clock must be configured at RCC top level. - Two clocks settings are mandatory: - - ADC clock (core clock): - Example: - Into HAL_ADC_MspInit() (recommended code location): - __ADC1_CLK_ENABLE(); - - - ADC clock (conversions clock): - Only one possible clock source: derived from HSI RC 16MHz oscillator - (HSI). - Example: - Into HAL_ADC_MspInit() or with main setting of RCC: - RCC_OscInitTypeDef RCC_OscInitStructure; - HAL_RCC_GetOscConfig(&RCC_OscInitStructure); - RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); - RCC_OscInitStructure.HSIState = RCC_HSI_ON; - RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStructure.PLL.PLLSource = ... - RCC_OscInitStructure.PLL... - HAL_RCC_OscConfig(&RCC_OscInitStructure); - - Note: ADC is connected directly to HSI RC 16MHz oscillator. - Therefore, RCC PLL setting has no impact on ADC. - PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or - enabled with HSI16 as clock source - (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device - main clock source SYSCLK. - The only mandatory setting is ".HSIState = RCC_HSI_ON" - - Note: ADC clock prescaler is configured at ADC level with - parameter "ClockPrescaler" using function HAL_ADC_Init(). + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] + + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + Caution: On STM32L1, ADC clock frequency max is 16MHz (refer + to device datasheet). + Therefore, ADC clock prescaler must be configured in + function of ADC clock source frequency to remain below + this maximum frequency. + + (++) Two clock settings are mandatory: + (+++) ADC clock (core clock). + (+++) ADC clock (conversions clock). + Only one possible clock source: derived from HSI RC 16MHz oscillator + (HSI). + ADC is connected directly to HSI RC 16MHz oscillator. + Therefore, RCC PLL setting has no impact on ADC. + PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or + enabled with HSI16 as clock source + (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device + main clock source SYSCLK. + The only mandatory setting is ".HSIState = RCC_HSI_ON" + + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) __HAL_RCC_ADC1_CLK_ENABLE(); + + (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); + (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); + (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON; + (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; + (+++) RCC_OscInitStructure.PLL.PLLSource = ... + (+++) RCC_OscInitStructure.PLL... + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (++) ADC clock prescaler is configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); - - (#) Configure the ADC parameters (conversion resolution, data alignment, - continuous mode, ...) using the HAL_ADC_Init() function. - - (#) Activate the ADC peripheral using one of the start functions: - HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(). - - *** Channels configuration to regular group *** - ================================================ - [..] - (+) To configure the ADC regular group features, use - HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. - (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. - - *** DMA for regular group configuration *** - =========================================== + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). + + *** Configuration of ADC, groups regular/injected, channels parameters *** + ========================================================================== + [..] + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the injected group parameters (conversion trigger, + sequencer, ..., of injected group) + and the channels for injected group parameters (channel number, + channel rank into sequencer, ..., into injected group) + using function HAL_ADCEx_InjectedConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + (#) Optionally, for devices with several ADC instances: configure the + multimode parameters + using function HAL_ADCEx_MultiModeConfigChannel(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (or for injected group: HAL_ADCEx_InjectedGetValue() ) + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (or for injected group: HAL_ADCEx_InjectedGetValue() ) + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + (++) For devices with several ADCs: ADC multimode conversion + with transfer by DMA: + (+++) Activate the ADC peripheral (slave) and start conversions + using function HAL_ADC_Start() + (+++) Activate the ADC peripheral (master) and start conversions + using function HAL_ADCEx_MultiModeStart_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral (master) + using function HAL_ADCEx_MultiModeStop_DMA() + (+++) Stop conversion and disable the ADC peripheral (slave) + using function HAL_ADC_Stop_IT() + [..] - (+) To enable the DMA mode for regular group, use the - HAL_ADC_Start_DMA() function. - (+) To enable the generation of DMA requests continuously at the end of - the last DMA transfer, use the HAL_ADC_Init() function. + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + (+@) HAL_ADCEx_InjectedConvCpltCallback() + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; + (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_Init(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + + [..] @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -172,7 +303,7 @@ * @{ */ - /* Fixed timeout values for ADC calibration, enable settling time. */ + /* Timeout values for ADC enable and disable settling time. */ /* Values defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ @@ -182,13 +313,18 @@ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /* Delay for ADC stabilization time. */ - /* Maximum delay is 3.5us (refer to device datasheet, parameter tSTAB). */ - /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */ - /* have the minimum number of CPU cycles to fulfill this delay. */ - #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)112) + /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ + /* Unit: us */ + #define ADC_STAB_DELAY_US ((uint32_t) 3) + + /* Delay for temperature sensor stabilization time. */ + /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + /* Unit: us */ + #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + /** - * @} - */ + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -200,25 +336,25 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAError(DMA_HandleTypeDef *hdma); /** - * @} - */ + * @} + */ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_Exported_Functions ADC Exported Functions * @{ */ -/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * +/** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions + * @brief ADC Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. - (+) De-initialize the ADC + (+) De-initialize the ADC. @endverbatim * @{ */ @@ -248,12 +384,12 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma); */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_cr1 = 0; uint32_t tmp_cr2 = 0; /* Check ADC handle */ - if(hadc == HAL_NULL) + if(hadc == NULL) { return HAL_ERROR; } @@ -276,7 +412,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); + if(hadc->Init.DiscontinuousConvMode != DISABLE) + { + assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); + } } if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) @@ -294,20 +433,28 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + /* Enable SYSCFG clock to control the routing Interface (RI) */ - __SYSCFG_CLK_ENABLE(); - + __HAL_RCC_SYSCFG_CLK_ENABLE(); + /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - } + } /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ - if (tmpHALStatus != HAL_ERROR) + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; - + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + /* Set ADC parameters */ /* Configuration of common ADC clock: clock source HSI with selectable */ @@ -322,11 +469,11 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - DMA continuous request */ /* - Channels bank (Banks availability depends on devices categories) */ /* - continuous conversion mode */ - tmp_cr2 |= (hadc->Init.DataAlign | - hadc->Init.EOCSelection | - __ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) | - hadc->Init.ChannelsBank | - __ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) ); + tmp_cr2 |= (hadc->Init.DataAlign | + hadc->Init.EOCSelection | + ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) | + hadc->Init.ChannelsBank | + ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) ); /* Enable external trigger if trigger selection is different of software */ /* start. */ @@ -347,22 +494,37 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ - if ((__HAL_ADC_IS_ENABLED(hadc) == RESET)) + if ((ADC_IS_ENABLE(hadc) == RESET)) { tmp_cr2 |= hadc->Init.LowPowerAutoWait; - tmp_cr1 |= (hadc->Init.Resolution | - hadc->Init.LowPowerAutoPowerOff | - __ADC_CR1_SCAN(hadc->Init.ScanConvMode) ); - + tmp_cr1 |= (hadc->Init.Resolution | + hadc->Init.LowPowerAutoPowerOff | + ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) ); + /* Enable discontinuous mode only if continuous mode is disabled */ - if ((hadc->Init.DiscontinuousConvMode == ENABLE) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* Enable discontinuous mode of regular group */ - /* Set the number of channels to be converted in discontinuous mode */ - tmp_cr1 |= ((ADC_CR1_DISCEN) | - __ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)); + /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ + /* discontinuous is set anyway, but has no effect on ADC HW. */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + /* Set the number of channels to be converted in discontinuous mode */ + SET_BIT(tmp_cr1, ADC_CR1_DISCEN | + ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); + } + else + { + /* ADC regular group settings continuous and sequencer discontinuous*/ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } /* Update ADC configuration register CR1 with previous settings */ @@ -372,14 +534,14 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) ADC_CR1_PDD | ADC_CR1_DISCNUM | ADC_CR1_DISCEN | - ADC_CR1_SCAN , - tmp_cr1 ); + ADC_CR1_SCAN , + tmp_cr1 ); } /* Update ADC configuration register CR2 with previous settings */ - MODIFY_REG(hadc->Instance->CR2 , - __ADC_CR2_MASK_ADCINIT() , - tmp_cr2 ); + MODIFY_REG(hadc->Instance->CR2 , + ADC_CR2_MASK_ADCINIT() , + tmp_cr2 ); /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ @@ -390,11 +552,11 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ - if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) { - MODIFY_REG(hadc->Instance->SQR1 , - ADC_SQR1_L , - __ADC_SQR1_L(hadc->Init.NbrOfConversion) ); + MODIFY_REG(hadc->Instance->SQR1 , + ADC_SQR1_L , + ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) ); } else { @@ -413,33 +575,34 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) == tmp_cr2) { /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } } else { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** @@ -452,29 +615,29 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ - if(hadc == HAL_NULL) + if(hadc == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); + tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ @@ -490,17 +653,14 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) ADC_CR1_AWDCH )); /* Reset register CR2 */ - __ADC_CR2_CLEAR(hadc); + ADC_CR2_CLEAR(hadc); /* Reset register SMPR0 */ - __ADC_SMPR0_CLEAR(hadc); + ADC_SMPR0_CLEAR(hadc); /* Reset register SMPR1 */ - CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | - ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | - ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | - ADC_SMPR1_SMP20 )); - + ADC_SMPR1_CLEAR(hadc); + /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | @@ -547,11 +707,6 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )); - /* Reset register JSQR */ - CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | - ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); - /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | @@ -572,27 +727,27 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* If needed, copy-paste and uncomment the following reset code into */ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ /* */ - /* __ADC1_FORCE_RESET() */ - /* __ADC1_RELEASE_RESET() */ + /* __HAL_RCC_ADC1_FORCE_RESET() */ + /* __HAL_RCC_ADC1_RELEASE_RESET() */ /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } - + /** * @brief Initializes the ADC MSP. * @param hadc: ADC handle @@ -600,6 +755,9 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. */ @@ -612,6 +770,9 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. */ @@ -621,8 +782,8 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) * @} */ -/** @defgroup ADC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions + * @brief ADC IO operation functions * @verbatim =============================================================================== @@ -651,60 +812,74 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + /* State machine update: Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); } - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Start conversion of regular group if software start has been selected. */ + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group */ SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); } } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing interruption of potential + * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle @@ -712,34 +887,48 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); + tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status @@ -750,55 +939,76 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } - /* Get timeout */ + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_TIMEOUT; } } } - /* Clear end of conversion flag of regular group if low power feature "Auto */ - /* Wait" is disabled, to not interfere with this feature until data */ - /* register is read using function HAL_ADC_GetValue(). */ + /* Clear end of conversion flag of regular group if low power feature */ + /* "Auto Wait" is disabled, to not interfere with this feature until data */ + /* register is read using function HAL_ADC_GetValue(). */ if (hadc->Init.LowPowerAutoWait == DISABLE) { /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32L1, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - /* Check if a conversion is ready on injected group */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -811,37 +1021,37 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @param hadc: ADC handle * @param EventType: the ADC event type. * This parameter can be one of the following values: - * @arg AWD_EVENT: ADC Analog watchdog event. - * @arg OVR_EVENT: ADC Overrun event + * @arg ADC_AWD_EVENT: ADC Analog watchdog event. + * @arg ADC_OVR_EVENT: ADC Overrun event. * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); - /* Get timeout */ + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Check selected event flag */ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -849,69 +1059,89 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy switch(EventType) { /* Analog watchdog (level out of window) event */ - case AWD_EVENT: - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); break; /* Overrun event */ - default: /* Case OVR_EVENT */ - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to overrun */ - hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + default: /* Case ADC_OVR_EVENT */ + /* Note: On STM32L1, ADC overrun can be set through other parameters */ + /* refer to description of parameter "EOCSelection" for more */ + /* details. */ - /* Clear ADC Overrun flag */ + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); break; } - + /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of regular group with interruption. - * Interruptions enabled in this function: EOC (end of conversion), - * overrun. + * Interruptions enabled in this function: + * - EOC (end of conversion of regular group) + * - overrun * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + /* State machine update: Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); } - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ @@ -920,22 +1150,19 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); - /* Start conversion of regular group if software start has been selected. */ + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group */ SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); - } - + } } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** @@ -947,40 +1174,44 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); + tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Interruptions enabled in this function: - * overrun, DMA half transfer, DMA transfer complete. + * - DMA transfer complete + * - DMA half transfer + * - overrun * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @param pData: The destination Buffer address. @@ -989,35 +1220,50 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + /* State machine update: Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); } - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; @@ -1045,30 +1291,28 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - /* Start conversion of regular group if software start has been selected. */ + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ - if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group */ SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); } } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. - * @note: ADC peripheral disable is forcing interruption of potential + * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle @@ -1076,7 +1320,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1086,42 +1330,61 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); + tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA mode */ hadc->Instance->CR2 &= ~ADC_CR2_DMA; /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ - tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - } + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + } + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Get ADC regular group conversion result. + * @note Reading register DR automatically clears ADC flag EOC + * (ADC group regular end of unitary conversion). + * @note This function does not clear ADC flag EOS + * (ADC group regular end of sequence conversion). + * Occurrence of flag EOS rising: + * - If sequencer is composed of 1 rank, flag EOS is equivalent + * to flag EOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag EOC only is raised, at the end of the scan sequence + * both flags EOC and EOS are raised. + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADC_PollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle - * @retval Converted value + * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { @@ -1135,74 +1398,6 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) return hadc->Instance->DR; } -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - /* Check if a conversion is ready on injected group */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } - } - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Half conversion callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - - /* Error callback */ - HAL_ADC_ErrorCallback(hadc); -} - /** * @brief Handles ADC interrupt request * @param hadc: ADC handle @@ -1222,35 +1417,36 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) { /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - /* Check if a conversion is ready on injected group */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } - } + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - /* Disable interruption if no further conversion upcoming regular */ - /* external trigger or by continuous mode */ - if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32L1, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) { - /* Disable ADC end of single conversion interrupt */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used by */ - /* overrun IRQ process below. */ + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } /* Conversion complete callback */ @@ -1267,36 +1463,33 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) { /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - - if(hadc->State == HAL_ADC_STATE_EOC_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ; - } - } + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } - /* Disable interruption if no further conversion upcoming injected */ - /* external trigger or by automatic injected conversion with regular */ - /* group having no further conversion upcoming (same conditions as */ - /* regular group interruption disabling above). */ - if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) || - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, scan sequence on going or by automatic injected */ + /* conversion from group regular (same conditions as group regular */ + /* interruption disabling above). */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) { - /* Disable ADC end of single conversion interrupt */ + /* Disable ADC end of single conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } /* Conversion complete callback */ @@ -1312,14 +1505,14 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; - - /* Clear the ADCx's Analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD); + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window callback */ HAL_ADC_LevelOutOfWindowCallback(hadc); + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); } } @@ -1328,11 +1521,15 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR)) { - /* Change ADC state to error state */ - hadc->State = HAL_ADC_STATE_ERROR; + /* Note: On STM32L1, ADC overrun can be set through other parameters */ + /* refer to description of parameter "EOCSelection" for more */ + /* details. */ /* Set ADC error code to overrun */ - hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); /* Error callback */ HAL_ADC_ErrorCallback(hadc); @@ -1351,6 +1548,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ @@ -1363,6 +1563,9 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ @@ -1375,6 +1578,9 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ @@ -1388,6 +1594,9 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ @@ -1433,8 +1642,9 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + __IO uint32_t wait_loop_index = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1449,68 +1659,68 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7) - { + { MODIFY_REG(hadc->Instance->SQR5, - __ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), - __ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); + ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), + ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13) - { + { MODIFY_REG(hadc->Instance->SQR4, - __ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), - __ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); + ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), + ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 18 */ else if (sConfig->Rank < 19) { MODIFY_REG(hadc->Instance->SQR3, - __ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), - __ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); + ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), + ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 19 to 24 */ else if (sConfig->Rank < 25) { MODIFY_REG(hadc->Instance->SQR2, - __ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), - __ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); + ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), + ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 25 to 28 */ else { MODIFY_REG(hadc->Instance->SQR1, - __ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), - __ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); + ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), + ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } - + /* Channel sampling time configuration */ /* For channels 0 to 9 */ if (sConfig->Channel < ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR3, - __ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), - __ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); + ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), + ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); } /* For channels 10 to 19 */ else if (sConfig->Channel < ADC_CHANNEL_20) { MODIFY_REG(hadc->Instance->SMPR2, - __ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), - __ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); + ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), + ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ /* For channels 20 to 29 for devices Cat4, Cat.5 */ else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX) { MODIFY_REG(hadc->Instance->SMPR1, - __ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), - __ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); + ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), + ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } /* For channels 30 to 31 for devices Cat4, Cat.5 */ else { - __ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); + ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ @@ -1518,18 +1728,40 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT) ) { - SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); + if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET) + { + SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); + + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + while(wait_loop_index != 0) + { + wait_loop_index--; + } + } + } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Configures the analog watchdog. + * @note Analog watchdog thresholds can be modified while ADC conversion + * is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. * @param hadc: ADC handle * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration * @retval HAL status @@ -1540,8 +1772,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || @@ -1621,7 +1853,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * @param hadc: ADC handle * @retval HAL state */ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) { /* Return ADC state */ return hadc->State; @@ -1653,43 +1885,50 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @note If low power mode AutoPowerOff is enabled, power-on/off phases are + * performed automatically by hardware. + * In this mode, this function is useless and must not be called because + * flag ADC_FLAG_RDY is not usable. + * Therefore, this function must be called under condition of + * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { - uint32_t wait_loop_index = 0; uint32_t tickstart = 0; + __IO uint32_t wait_loop_index = 0; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ - if (__HAL_ADC_IS_ENABLED(hadc) == RESET) + if (ADC_IS_ENABLE(hadc) == RESET) { /* Enable the Peripheral */ - __ADC_ENABLE(hadc); + __HAL_ADC_ENABLE(hadc); - /* Delay for ADC stabilization time. */ - /* Delay fixed to worst case: maximum CPU frequency */ - while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES) + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(wait_loop_index != 0) { - wait_loop_index++; + wait_loop_index--; } - /* Get timeout */ + /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively enabled */ - while(__HAL_ADC_IS_ENABLED(hadc) == RESET) + while(ADC_IS_ENABLE(hadc) == RESET) { if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -1714,25 +1953,25 @@ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0; - /* Verification if ADC is not already disabled: */ - if (__HAL_ADC_IS_ENABLED(hadc) != RESET) + /* Verification if ADC is not already disabled */ + if (ADC_IS_ENABLE(hadc) != RESET) { /* Disable the ADC peripheral */ - __ADC_DISABLE(hadc); + __HAL_ADC_DISABLE(hadc); - /* Get timeout */ + /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively disabled */ - while(__HAL_ADC_IS_ENABLED(hadc) != RESET) + while(ADC_IS_ENABLE(hadc) != RESET) { if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } @@ -1743,6 +1982,92 @@ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) return HAL_OK; } +/** + * @brief DMA transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32L1, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Half conversion callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ + HAL_ADC_ErrorCallback(hadc); +} + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h index 93aeae0c2d5..eae50a3c744 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_adc.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -44,7 +44,8 @@ #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" +#include "stm32l1xx_hal_def.h" + /** @addtogroup STM32L1xx_HAL_Driver * @{ */ @@ -53,7 +54,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ @@ -69,13 +70,13 @@ * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). */ typedef struct { uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler. This parameter can be a value of @ref ADC_ClockPrescaler - Note: In case of usage of channels on injected group, ADC frequency should be low than AHB clock frequency /4 for resolution 12 or 10 bits, + Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */ uint32_t Resolution; /*!< Configures the ADC resolution. @@ -95,14 +96,15 @@ typedef struct Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. - Note: If overrun feature is intending to be used in ADC mode 'interruption' (function HAL_ADC_Start_IT() ), parameter EOCSelection must be set to each conversion (this is not needed for ADC mode 'transfer by DMA', with function HAL_ADC_Start_DMA()) */ + Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). + If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous - conversion (for regular group) or previous sequence (for injected group) has been treated by user software. + conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be a value of @ref ADC_LowPowerAutoWait. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed - and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. + and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */ uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). @@ -114,7 +116,7 @@ typedef struct uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 28. */ @@ -122,7 +124,7 @@ typedef struct uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 27. */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. @@ -132,7 +134,7 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. - If set to external trigger source, triggering is on event rising edge. + If set to external trigger source, triggering is on event rising edge by default. This parameter can be a value of @ref ADC_External_trigger_source_Regular */ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. @@ -140,8 +142,8 @@ typedef struct uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) or in Continuous mode (DMA transfer unlimited, whatever number of conversions). Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */ + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ }ADC_InitTypeDef; /** @@ -160,7 +162,7 @@ typedef struct STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '. Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */ - uint32_t Rank; /*!< Specifies the rank in the regular group sequencer + uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. This parameter can be a value of @ref ADC_regular_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. @@ -196,29 +198,43 @@ typedef struct }ADC_AnalogWDGConfTypeDef; /** - * @brief HAL ADC state machine: ADC States structure definition + * @brief HAL ADC state machine: ADC states definition (bitfields) */ -typedef enum -{ - HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ - HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ - HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ - HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ - HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ - HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ - HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ - HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ - HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ - HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ - HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ - HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32L1xx devices (kept for compatibility with other devices featuring several AWD) */ - HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32l1xx devices (kept for compatibility with other devices featuring several AWD) */ -}HAL_ADC_StateTypeDef; +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32L1 device: End Of Sampling flag raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */ + /** - * @brief ADC handle Structure definition + * @brief ADC handle Structure definition */ typedef struct { @@ -232,7 +248,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ }ADC_HandleTypeDef; @@ -250,13 +266,12 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ - */ + */ #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, enable/disable, erroneous state */ #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ - /** * @} */ @@ -267,10 +282,6 @@ typedef struct #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */ #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */ #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */ - -#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) ) /** * @} */ @@ -278,18 +289,10 @@ typedef struct /** @defgroup ADC_Resolution ADC Resolution * @{ */ -#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ -#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */ -#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */ -#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */ - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ - ((RESOLUTION) == ADC_RESOLUTION10b) || \ - ((RESOLUTION) == ADC_RESOLUTION8b) || \ - ((RESOLUTION) == ADC_RESOLUTION6b) ) - -#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \ - ((RESOLUTION) == ADC_RESOLUTION6b) ) +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */ +#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */ +#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */ /** * @} */ @@ -299,9 +302,6 @@ typedef struct */ #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ - ((ALIGN) == ADC_DATAALIGN_LEFT) ) /** * @} */ @@ -310,26 +310,18 @@ typedef struct * @{ */ #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) -#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) - -#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ - ((SCAN_MODE) == ADC_SCAN_ENABLE) ) +#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /** * @} */ -/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular +/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) -#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) - -#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) /** * @} */ @@ -353,47 +345,7 @@ typedef struct #define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2 #define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 - #define ADC_SOFTWARE_START ((uint32_t)0x00000010) - -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - ((REGTRIG) == ADC_SOFTWARE_START) ) -/** - * @} - */ - -/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular - * @{ - */ - -/* List of external triggers of regular group for ADC1: */ -/* (used internally by HAL driver. To not use into HAL structure parameters) */ - -/* External triggers of regular group for ADC1 */ -#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000) -#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) -#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 )) -#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) -#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 )) -#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 )) -#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) - /** * @} */ @@ -401,11 +353,8 @@ typedef struct /** @defgroup ADC_EOCSelection ADC EOCSelection * @{ */ -#define EOC_SEQ_CONV ((uint32_t)0x00000000) -#define EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS) - -#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == EOC_SEQ_CONV) ) +#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000) +#define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS) /** * @} */ @@ -426,14 +375,6 @@ typedef struct #define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */ #define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */ -#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) ) /** * @} */ @@ -445,11 +386,6 @@ typedef struct #define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */ #define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */ #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */ - -#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \ - ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \ - ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \ - ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) ) /** * @} */ @@ -458,7 +394,7 @@ typedef struct /** @defgroup ADC_ChannelsBank ADC ChannelsBank * @{ */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) #define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) @@ -468,7 +404,7 @@ typedef struct #define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -505,89 +441,25 @@ typedef struct #define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */ #define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ #define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ #define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ #define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ #define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ #define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ #define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */ #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */ #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */ #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_16) || \ - ((CHANNEL) == ADC_CHANNEL_17) || \ - ((CHANNEL) == ADC_CHANNEL_18) || \ - ((CHANNEL) == ADC_CHANNEL_19) || \ - ((CHANNEL) == ADC_CHANNEL_20) || \ - ((CHANNEL) == ADC_CHANNEL_21) || \ - ((CHANNEL) == ADC_CHANNEL_22) || \ - ((CHANNEL) == ADC_CHANNEL_23) || \ - ((CHANNEL) == ADC_CHANNEL_24) || \ - ((CHANNEL) == ADC_CHANNEL_25) || \ - ((CHANNEL) == ADC_CHANNEL_26) ) -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_16) || \ - ((CHANNEL) == ADC_CHANNEL_17) || \ - ((CHANNEL) == ADC_CHANNEL_18) || \ - ((CHANNEL) == ADC_CHANNEL_19) || \ - ((CHANNEL) == ADC_CHANNEL_20) || \ - ((CHANNEL) == ADC_CHANNEL_21) || \ - ((CHANNEL) == ADC_CHANNEL_22) || \ - ((CHANNEL) == ADC_CHANNEL_23) || \ - ((CHANNEL) == ADC_CHANNEL_24) || \ - ((CHANNEL) == ADC_CHANNEL_25) || \ - ((CHANNEL) == ADC_CHANNEL_26) || \ - ((CHANNEL) == ADC_CHANNEL_27) || \ - ((CHANNEL) == ADC_CHANNEL_28) || \ - ((CHANNEL) == ADC_CHANNEL_29) || \ - ((CHANNEL) == ADC_CHANNEL_30) || \ - ((CHANNEL) == ADC_CHANNEL_31) ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -603,15 +475,6 @@ typedef struct #define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */ #define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */ #define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */ - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_9CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_16CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_24CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_48CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_96CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_192CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_384CYCLES) ) /** * @} */ @@ -632,14 +495,14 @@ typedef struct (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \ ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \ ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \ ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \ (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \ (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \ @@ -654,14 +517,14 @@ typedef struct (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \ ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \ ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \ ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \ (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \ (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \ @@ -676,19 +539,19 @@ typedef struct (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \ ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \ ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \ ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \ (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ -/** @defgroup ADC_regular_rank ADC regular rank +/** @defgroup ADC_regular_rank ADC rank into regular group * @{ */ #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) @@ -718,67 +581,9 @@ typedef struct #define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019) #define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A) #define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B) -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C) - -#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_10) || \ - ((CHANNEL) == ADC_REGULAR_RANK_11) || \ - ((CHANNEL) == ADC_REGULAR_RANK_12) || \ - ((CHANNEL) == ADC_REGULAR_RANK_13) || \ - ((CHANNEL) == ADC_REGULAR_RANK_14) || \ - ((CHANNEL) == ADC_REGULAR_RANK_15) || \ - ((CHANNEL) == ADC_REGULAR_RANK_16) || \ - ((CHANNEL) == ADC_REGULAR_RANK_17) || \ - ((CHANNEL) == ADC_REGULAR_RANK_18) || \ - ((CHANNEL) == ADC_REGULAR_RANK_19) || \ - ((CHANNEL) == ADC_REGULAR_RANK_20) || \ - ((CHANNEL) == ADC_REGULAR_RANK_21) || \ - ((CHANNEL) == ADC_REGULAR_RANK_22) || \ - ((CHANNEL) == ADC_REGULAR_RANK_23) || \ - ((CHANNEL) == ADC_REGULAR_RANK_24) || \ - ((CHANNEL) == ADC_REGULAR_RANK_25) || \ - ((CHANNEL) == ADC_REGULAR_RANK_26) || \ - ((CHANNEL) == ADC_REGULAR_RANK_27) || \ - ((CHANNEL) == ADC_REGULAR_RANK_28) ) -#else - -#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_10) || \ - ((CHANNEL) == ADC_REGULAR_RANK_11) || \ - ((CHANNEL) == ADC_REGULAR_RANK_12) || \ - ((CHANNEL) == ADC_REGULAR_RANK_13) || \ - ((CHANNEL) == ADC_REGULAR_RANK_14) || \ - ((CHANNEL) == ADC_REGULAR_RANK_15) || \ - ((CHANNEL) == ADC_REGULAR_RANK_16) || \ - ((CHANNEL) == ADC_REGULAR_RANK_17) || \ - ((CHANNEL) == ADC_REGULAR_RANK_18) || \ - ((CHANNEL) == ADC_REGULAR_RANK_19) || \ - ((CHANNEL) == ADC_REGULAR_RANK_20) || \ - ((CHANNEL) == ADC_REGULAR_RANK_21) || \ - ((CHANNEL) == ADC_REGULAR_RANK_22) || \ - ((CHANNEL) == ADC_REGULAR_RANK_23) || \ - ((CHANNEL) == ADC_REGULAR_RANK_24) || \ - ((CHANNEL) == ADC_REGULAR_RANK_25) || \ - ((CHANNEL) == ADC_REGULAR_RANK_26) || \ - ((CHANNEL) == ADC_REGULAR_RANK_27) ) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -793,14 +598,6 @@ typedef struct #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) - -#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) /** * @} */ @@ -808,13 +605,9 @@ typedef struct /** @defgroup ADC_conversion_group ADC conversion group * @{ */ -#define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) -#define INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) -#define REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) - -#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP) || \ - ((CONVERSION) == INJECTED_GROUP) || \ - ((CONVERSION) == REGULAR_INJECTED_GROUP) ) +#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) +#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) +#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) /** * @} */ @@ -822,11 +615,8 @@ typedef struct /** @defgroup ADC_Event_type ADC Event type * @{ */ -#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ -#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ - -#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ - ((EVENT) == ADC_FLAG_OVR) ) +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ +#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ /** * @} */ @@ -853,115 +643,127 @@ typedef struct #define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */ #define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */ #define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */ -#define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Regular group ready status flag */ - -/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \ - ADC_FLAG_OVR) -/** - * @} - */ - -/** @defgroup ADC_range_verification ADC range verification - * For a unique ADC resolution: 12 bits - * @{ - */ -#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF)) +#define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Injected group ready status flag */ /** * @} */ -/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification - * @{ - */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28))) -#else -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27))) -#endif /** * @} - */ + */ -/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification - * @{ - */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) -/** - * @} - */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADC_Exported_Macros ADC Exported Macros +/** @addtogroup ADC_Private_Constants ADC Private Constants * @{ */ -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ -/** - * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle - * @retval SET (ADC enabled) or RESET (ADC disabled) - */ -#define __HAL_ADC_IS_ENABLED(__HANDLE__) \ - ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ - ) ? SET : RESET) +/* List of external triggers of regular group for ADC1: */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__: ADC handle - * @retval SET (software start) or RESET (external trigger) +/* External triggers of regular group for ADC1 */ +#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000) +#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) +#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 )) +#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) +#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 )) +#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 )) +#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) + +/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \ + ADC_FLAG_OVR) + +/** + * @} */ -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ /** - * @brief Test if conversion trigger of injected group is software start - * or external trigger. + * @brief Enable the ADC peripheral * @param __HANDLE__: ADC handle - * @retval SET (software start) or RESET (external trigger) + * @retval None */ -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) +#define __HAL_ADC_ENABLE(__HANDLE__) \ + (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON -/** @brief Checks if the specified ADC interrupt source is enabled or disabled. +/** + * @brief Disable the ADC peripheral * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC interrupt source to check - * @retval State of interruption (SET or RESET) + * @retval None */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (( ((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__) \ - )? SET : RESET \ - ) - +#define __HAL_ADC_DISABLE(__HANDLE__) \ + (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON + /** * @brief Enable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) - + /** * @brief Disable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC interrupt source to check + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source + * @retval State of interruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) + /** * @brief Get the selected ADC's flag status. * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_STRT: ADC Regular group start flag + * @arg ADC_FLAG_JSTRT: ADC Injected group start flag + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_ADONS: ADC ready status flag + * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag + * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ @@ -971,28 +773,452 @@ typedef struct * @brief Clear the ADC's pending flags * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag + * @arg ADC_FLAG_STRT: ADC Regular group start flag + * @arg ADC_FLAG_JSTRT: ADC Injected group start flag + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_ADONS: ADC ready status flag + * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag + * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag + * @retval None + */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** @brief Reset ADC handle state + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) + +/** + * @} + */ + +/* Private macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +#define ADC_IS_ENABLE(__HANDLE__) \ + ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) + +/** + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) +#define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Clear ADC error code (set it to error code: "no error") * @param __HANDLE__: ADC handle * @retval None */ -#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) \ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) -/** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle +/** + * @brief Set ADC number of ranks into regular channel sequence length. + * @param _NbrOfConversion_: Regular channel sequence length + * @retval None + */ +#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ + (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) + +/** + * @brief Set the ADC's sample time for channel numbers between 10 and 18. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ + ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) + +/** + * @brief Set the ADC's sample time for channel numbers between 0 and 9. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \ + ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) + +/** + * @brief Set the selected regular channel rank for rank between 1 and 6. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) + +/** + * @brief Set the selected regular channel rank for rank between 7 and 12. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) + +/** + * @brief Set the selected regular channel rank for rank between 13 and 18. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) + +/** + * @brief Set the selected regular channel rank for rank between 19 and 24. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. * @retval None */ -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19))) /** - * @} + * @brief Set the selected regular channel rank for rank between 25 and 28. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ + ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25))) + +/** + * @brief Set the injected sequence length. + * @param _JSQR_JL_: Sequence length. + * @retval None */ +#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20) + +/** + * @brief Set the selected injected channel rank + * Note: on STM32L1 devices, channel rank position in JSQR register + * is depending on total number of ranks selected into + * injected sequencer (ranks sequence starting from 4-JL) + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @param _JSQR_JL_: Sequence length. + * @retval None + */ +#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ + ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @retval None + */ +#define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \ + ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS)) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_: Continuous mode. + * @retval None + */ +#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ + ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) + +/** + * @brief Configures the number of discontinuous conversions for the regular group channels. + * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. + * @retval None + */ +#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ + (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) + +/** + * @brief Enable ADC scan mode to convert multiple ranks with sequencer. + * @param _SCAN_MODE_: Scan conversion mode. + * @retval None + */ +/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ +/* is equivalent to ADC_SCAN_ENABLE. */ +#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ + (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ + )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ + ) + + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) ) + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B) ) + +#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B) ) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ + ((SCAN_MODE) == ADC_SCAN_ENABLE) ) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) + +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) + +#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) ) + +#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \ + ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \ + ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \ + ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) ) + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + +#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ + ((BANK) == ADC_CHANNELS_BANK_B) ) +#else + +#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_19) || \ + ((CHANNEL) == ADC_CHANNEL_20) || \ + ((CHANNEL) == ADC_CHANNEL_21) || \ + ((CHANNEL) == ADC_CHANNEL_22) || \ + ((CHANNEL) == ADC_CHANNEL_23) || \ + ((CHANNEL) == ADC_CHANNEL_24) || \ + ((CHANNEL) == ADC_CHANNEL_25) || \ + ((CHANNEL) == ADC_CHANNEL_26) ) +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_19) || \ + ((CHANNEL) == ADC_CHANNEL_20) || \ + ((CHANNEL) == ADC_CHANNEL_21) || \ + ((CHANNEL) == ADC_CHANNEL_22) || \ + ((CHANNEL) == ADC_CHANNEL_23) || \ + ((CHANNEL) == ADC_CHANNEL_24) || \ + ((CHANNEL) == ADC_CHANNEL_25) || \ + ((CHANNEL) == ADC_CHANNEL_26) || \ + ((CHANNEL) == ADC_CHANNEL_27) || \ + ((CHANNEL) == ADC_CHANNEL_28) || \ + ((CHANNEL) == ADC_CHANNEL_29) || \ + ((CHANNEL) == ADC_CHANNEL_30) || \ + ((CHANNEL) == ADC_CHANNEL_31) ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_9CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_16CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_24CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_48CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_96CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_192CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_384CYCLES) ) + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + +#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_10) || \ + ((CHANNEL) == ADC_REGULAR_RANK_11) || \ + ((CHANNEL) == ADC_REGULAR_RANK_12) || \ + ((CHANNEL) == ADC_REGULAR_RANK_13) || \ + ((CHANNEL) == ADC_REGULAR_RANK_14) || \ + ((CHANNEL) == ADC_REGULAR_RANK_15) || \ + ((CHANNEL) == ADC_REGULAR_RANK_16) || \ + ((CHANNEL) == ADC_REGULAR_RANK_17) || \ + ((CHANNEL) == ADC_REGULAR_RANK_18) || \ + ((CHANNEL) == ADC_REGULAR_RANK_19) || \ + ((CHANNEL) == ADC_REGULAR_RANK_20) || \ + ((CHANNEL) == ADC_REGULAR_RANK_21) || \ + ((CHANNEL) == ADC_REGULAR_RANK_22) || \ + ((CHANNEL) == ADC_REGULAR_RANK_23) || \ + ((CHANNEL) == ADC_REGULAR_RANK_24) || \ + ((CHANNEL) == ADC_REGULAR_RANK_25) || \ + ((CHANNEL) == ADC_REGULAR_RANK_26) || \ + ((CHANNEL) == ADC_REGULAR_RANK_27) || \ + ((CHANNEL) == ADC_REGULAR_RANK_28) ) +#else + +#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_10) || \ + ((CHANNEL) == ADC_REGULAR_RANK_11) || \ + ((CHANNEL) == ADC_REGULAR_RANK_12) || \ + ((CHANNEL) == ADC_REGULAR_RANK_13) || \ + ((CHANNEL) == ADC_REGULAR_RANK_14) || \ + ((CHANNEL) == ADC_REGULAR_RANK_15) || \ + ((CHANNEL) == ADC_REGULAR_RANK_16) || \ + ((CHANNEL) == ADC_REGULAR_RANK_17) || \ + ((CHANNEL) == ADC_REGULAR_RANK_18) || \ + ((CHANNEL) == ADC_REGULAR_RANK_19) || \ + ((CHANNEL) == ADC_REGULAR_RANK_20) || \ + ((CHANNEL) == ADC_REGULAR_RANK_21) || \ + ((CHANNEL) == ADC_REGULAR_RANK_22) || \ + ((CHANNEL) == ADC_REGULAR_RANK_23) || \ + ((CHANNEL) == ADC_REGULAR_RANK_24) || \ + ((CHANNEL) == ADC_REGULAR_RANK_25) || \ + ((CHANNEL) == ADC_REGULAR_RANK_26) || \ + ((CHANNEL) == ADC_REGULAR_RANK_27) ) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) + +#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ + ((CONVERSION) == ADC_INJECTED_GROUP) || \ + ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ + ((EVENT) == ADC_FLAG_OVR) ) + +/** + * @brief Verify that a ADC data is within range corresponding to + * ADC resolution. + * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits). + * @param __ADC_DATA__: value checked against the resolution. + * @retval SET: ADC data is within range corresponding to ADC resolution + * RESET: ADC data is not within range corresponding to ADC resolution + * + */ +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \ + ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= ((uint32_t)0x003F))) ) + + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28))) +#else +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27))) +#endif + +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) + +/** + * @} + */ + + /* Include ADC HAL Extension module */ #include "stm32l1xx_hal_adc_ex.h" @@ -1065,7 +1291,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c index 403fb32a2b4..23cfeb8cc6f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c @@ -2,48 +2,30 @@ ****************************************************************************** * @file stm32l1xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: - * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. + * ++ Start, stop, get result of conversions of injected + * group, using 2 possible modes: polling, interruption. + * ++ Calibration (ADC automatic self-calibration) * + Control functions - * ++ Analog Watchdog configuration - * ++ Channels configuration on regular group - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management + * ++ Channels configuration on injected group * Other functions (generic functions) are available in file * "stm32l1xx_hal_adc.c". * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Activate the ADC peripheral using one of the start functions: - HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(). - - *** Channels configuration to injected group *** - ================================================ - [..] - (+) To configure the ADC Injected channels group features, use - HAL_ADCEx_InjectedConfigChannel() functions. - (+) To activate the continuous mode, use the HAL_ADC_Init() function. - (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() - function. - - @endverbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32l1xx_hal_adc.c". + [..] + @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,7 +49,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -78,7 +60,7 @@ */ /** @defgroup ADCEx ADCEx - * @brief ADC HAL module driver + * @brief ADC Extension HAL module driver * @{ */ @@ -101,6 +83,12 @@ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES ((uint32_t)108) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES ((uint32_t)204) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES ((uint32_t)396) + + /* Delay for temperature sensor stabilization time. */ + /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + /* Unit: us */ + #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + /** * @} */ @@ -114,10 +102,10 @@ * @{ */ -/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions - * @brief Extended Initialization and Configuration functions +/** @defgroup ADCEx_Exported_Functions_Group1 ADC Extended IO operation functions + * @brief ADC Extended Input and Output operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -141,7 +129,7 @@ */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -150,63 +138,70 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + /* Check if a regular conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_REG) + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ; + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); } - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - /* Start conversion of injected group if software start has been selected */ - /* and if automatic injected conversion is disabled. */ + /* Enable conversion of injected group. */ + /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ - if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Enable ADC software conversion for injected channels */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); } } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. - * @note If ADC must be disabled with this function and if regular conversion - * is on going, function HAL_ADC_Stop must be used preliminarily. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -220,34 +215,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if((hadc->State != HAL_ADC_STATE_BUSY_REG) && - (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); + tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** @@ -270,7 +266,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Get timeout */ tickstart = HAL_GetTick(); @@ -295,8 +291,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Note: On STM32L1, setting "EOCSelection" is related to regular group */ /* only, by hardware. For compatibility with other STM32 devices, */ /* this setting is related also to injected group by software. */ - if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) || - (hadc->Init.EOCSelection != EOC_SINGLE_CONV) ) + if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) || + (hadc->Init.EOCSelection != ADC_EOC_SINGLE_CONV) ) { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) @@ -304,15 +300,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -322,8 +318,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Computation of CPU cycles corresponding to ADC conversion cycles. */ /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ /* channels. */ - conversion_timeout_cpu_cycles_max = __ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc); - conversion_timeout_cpu_cycles_max *= __ADC_CONVCYCLES_MAX_RANGE(hadc); + conversion_timeout_cpu_cycles_max = ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc); + conversion_timeout_cpu_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc); /* Poll with maximum conversion time */ while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max) @@ -331,15 +327,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_TIMEOUT; } } conversion_timeout_cpu_cycles ++; @@ -355,40 +351,45 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); } - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32L1, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - - if(hadc->State == HAL_ADC_STATE_EOC_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ; - } + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } - + /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of injected group with interruption. - * Interruptions enabled in this function: JEOC (end of conversion). + * - JEOC (end of conversion of injected group) * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -397,25 +398,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + /* Check if a regular conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_REG) + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ; + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); } - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ @@ -424,39 +432,39 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Enable end of conversion interrupt for injected channels */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - /* Start conversion of injected group if software start has been selected */ - /* and if automatic injected conversion is disabled. */ + /* Enable conversion of injected group. */ + /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ - if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Enable ADC software conversion for injected channels */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); } } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. - * @note If ADC must be disabled with this function and if regular conversion - * is on going, function HAL_ADC_Stop must be used preliminarily. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -470,41 +478,59 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if((hadc->State != HAL_ADC_STATE_BUSY_REG) && - (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); + tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Get ADC injected group conversion result. + * @note Reading register JDRx automatically clears ADC flag JEOC + * (ADC group injected end of unitary conversion). + * @note This function does not clear ADC flag JEOS + * (ADC group injected end of sequence conversion) + * Occurrence of flag JEOS rising: + * - If sequencer is composed of 1 rank, flag JEOS is equivalent + * to flag JEOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag JEOC only is raised, at the end of the scan sequence + * both flags JEOC and EOS are raised. + * Flag JEOS must not be cleared by this function because + * it would not be compliant with low power features + * (feature low power auto-wait, not available on all STM32 families). + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADCEx_InjectedPollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc: ADC handle * @param InjectedRank: the converted ADC injected rank. * This parameter can be one of the following values: @@ -512,7 +538,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected - * @retval None + * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { @@ -521,15 +547,11 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - - /* Clear injected group conversion flag to have similar behaviour as */ - /* regular group: reading data register also clears end of conversion flag. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - /* Get ADC converted value */ + /* Get ADC converted value */ switch(InjectedRank) { - case ADC_INJECTED_RANK_4: + case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: @@ -555,6 +577,9 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ @@ -564,8 +589,8 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) * @} */ -/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions + * @brief ADC Extended Peripheral Control functions * @verbatim =============================================================================== @@ -594,7 +619,8 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + __IO uint32_t wait_loop_index = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -602,7 +628,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, sConfigInjected->InjectedOffset)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { @@ -633,24 +659,24 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Clear the old SQx bits for all injected ranks */ - MODIFY_REG(hadc->Instance->JSQR , + MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | - ADC_JSQR_JSQ1 , - __ADC_JSQR_RK(sConfigInjected->InjectedChannel, - ADC_INJECTED_RANK_1, - 0x01) ); + ADC_JSQR_JSQ1 , + ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, + ADC_INJECTED_RANK_1, + 0x01) ); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ else { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } } else @@ -662,29 +688,29 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Clear the old SQx bits for the selected rank */ /* Set the SQx bits for the selected rank */ - MODIFY_REG(hadc->Instance->JSQR , + MODIFY_REG(hadc->Instance->JSQR , - ADC_JSQR_JL | - __ADC_JSQR_RK(ADC_JSQR_JSQ1, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) , + ADC_JSQR_JL | + ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) , - __ADC_JSQR_JL(sConfigInjected->InjectedNbrOfConversion) | - __ADC_JSQR_RK(sConfigInjected->InjectedChannel, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) ); + ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | + ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) ); } else { /* Clear the old SQx bits for the selected rank */ - MODIFY_REG(hadc->Instance->JSQR , + MODIFY_REG(hadc->Instance->JSQR , - ADC_JSQR_JL | - __ADC_JSQR_RK(ADC_JSQR_JSQ1, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) , + ADC_JSQR_JL | + ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) , - 0x00000000 ); + 0x00000000 ); } } @@ -715,7 +741,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Parameters that can be updated only when ADC is disabled: */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ - if ((__HAL_ADC_IS_ENABLED(hadc) == RESET)) + if ((ADC_IS_ENABLE(hadc) == RESET)) { hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO | ADC_CR1_JDISCEN ); @@ -731,9 +757,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } } @@ -748,40 +774,40 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } } } - /* InjectedChannel sampling time configuration */ + /* Channel sampling time configuration */ /* For InjectedChannels 0 to 9 */ if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR3, - __ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel), - __ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel), + ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* For InjectedChannels 10 to 19 */ else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20) { MODIFY_REG(hadc->Instance->SMPR2, - __ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel), - __ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel), + ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */ else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX) { MODIFY_REG(hadc->Instance->SMPR1, - __ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel), - __ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel), + ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */ else { - __ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } @@ -789,7 +815,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I switch(sConfigInjected->InjectedRank) { case 1: - /* Set injected channel 1 offset */ + /* Set injected channel 1 offset */ MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset); @@ -820,13 +846,24 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) { SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); + + if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + while(wait_loop_index != 0) + { + wait_loop_index--; + } + } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h index 187fa12cc5b..d4bc24ebb88 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of ADC HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_HAL_ADC_EX_H @@ -87,7 +87,7 @@ typedef struct If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), @@ -137,34 +137,24 @@ typedef struct * @{ */ -/** @defgroup ADCEx_injected_rank ADCEx injected rank +/** @defgroup ADCEx_injected_rank ADCEx rank into injected group * @{ */ #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) - -#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ - ((CHANNEL) == ADC_INJECTED_RANK_2) || \ - ((CHANNEL) == ADC_INJECTED_RANK_3) || \ - ((CHANNEL) == ADC_INJECTED_RANK_4) ) /** * @} */ -/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx External trigger edge Injected +/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) - -#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) /** * @} */ @@ -185,26 +175,22 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 - #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000010) +/** + * @} + */ -#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - ((REGTRIG) == ADC_SOFTWARE_START) ) /** * @} */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants + * @{ + */ + /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected * @{ */ @@ -223,16 +209,6 @@ typedef struct #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) - -/** - * @} - */ - - -/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification - * @{ - */ -#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) /** * @} */ @@ -240,8 +216,8 @@ typedef struct /** * @} */ - - + + /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros @@ -263,7 +239,7 @@ typedef struct #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Configures the ADC channels speed. * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. @@ -317,7 +293,7 @@ typedef struct ) \ ) \ ) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} @@ -331,24 +307,17 @@ typedef struct /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ -/** - * @brief Set ADC number of ranks into regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length - * @retval None - */ -#define __ADC_SQR1_L(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) - /** * @brief Set ADC ranks available in register SQR1. * Register SQR1 bits availability depends on device category. * @param _NbrOfConversion_: Regular channel sequence length * @retval None */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SQR1_SQXX ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25 +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) #else -#define __ADC_SQR1_SQXX ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25 -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @brief Set the ADC's sample time for channel numbers between 30 and 31. @@ -359,20 +328,23 @@ typedef struct * @param _CHANNELNB_: Channel number. * @retval None */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ + ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) #else -#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((uint32_t)0x00000000) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ + ((uint32_t)0x00000000) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Set the ADC's sample time for channel numbers between 20 and 29. * @param _SAMPLETIME_: Sample time parameter. * @param _CHANNELNB_: Channel number. * @retval None */ -#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) +#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ + ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) #else /** * @brief Set the ADC's sample time for channel numbers between 20 and 26. @@ -380,8 +352,9 @@ typedef struct * @param _CHANNELNB_: Channel number. * @retval None */ -#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ + ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @brief Defines the highest channel available in register SMPR1. Channels @@ -391,99 +364,12 @@ typedef struct * @param None * @retval None */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 #else #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define __ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) - -/** - * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define __ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) - -/** - * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) - -/** - * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) - -/** - * @brief Set the selected regular channel rank for rank between 13 and 18. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) - -/** - * @brief Set the selected regular channel rank for rank between 19 and 24. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19))) - -/** - * @brief Set the selected regular channel rank for rank between 25 and 28. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25))) - -/** - * @brief Set the injected sequence length. - * @param _JSQR_JL_: Sequence length. - * @retval None - */ -#define __ADC_JSQR_JL(_JSQR_JL_) (((_JSQR_JL_) -1) << 20) - -/** - * @brief Set the selected injected Channel rank (channels sequence starting from 4-JL) - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @param _JSQR_JL_: Sequence length. - * @retval None - */ -#define __ADC_JSQR_RK(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ - ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @brief Enable the ADC DMA continuous request. - * @param _DMACONTREQ_MODE_: DMA continuous request mode. - * @retval None - */ -#define __ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS)) - -/** - * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. - * @retval None - */ -#define __ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) /** * @brief Define mask of configuration bits of ADC and regular group in @@ -491,43 +377,27 @@ typedef struct * excluded of this mask). * @retval None */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_CR2_MASK_ADCINIT() \ +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define ADC_CR2_MASK_ADCINIT() \ (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) #else -#define __ADC_CR2_MASK_ADCINIT() \ +#define ADC_CR2_MASK_ADCINIT() \ (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) #endif -/** - * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. - * @retval None - */ -#define __ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) - -/** - * @brief Enable ADC scan mode to convert multiple ranks with sequencer. - * @param _SCAN_MODE_: Scan conversion mode. - * @retval None - */ -#define __ADC_CR1_SCAN(_SCAN_MODE_) \ - ( ( (_SCAN_MODE_) == (ADC_SCAN_ENABLE) \ - )? (ADC_CR1_SCAN) : (0x00000000) \ - ) /** * @brief Get the maximum ADC conversion cycles on all channels. * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) - * Approximation of sampling time within 2 ranges, returns the higher value: + * Approximation of sampling time within 2 ranges, returns the highest value: * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} * Unit: ADC clock cycles * @param __HANDLE__: ADC handle * @retval ADC conversion cycles on all channels */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ @@ -536,21 +406,21 @@ typedef struct ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ ) #else -#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ +#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ \ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @brief Get the ADC clock prescaler from ADC common control register * and convert it to its decimal number setting (refer to reference manual) * @retval None */ -#define __ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ +#define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) /** @@ -560,20 +430,31 @@ typedef struct * @param __HANDLE__: ADC handle * @retval None */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SMPR0_CLEAR(__HANDLE__) \ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define ADC_SMPR1_CLEAR(__HANDLE__) \ + CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \ + ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ + ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ + ADC_SMPR1_SMP20 )) + +#define ADC_SMPR0_CLEAR(__HANDLE__) \ (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) #else -#define __ADC_SMPR0_CLEAR(__HANDLE__) __NOP() -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define ADC_SMPR1_CLEAR(__HANDLE__) \ + CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ + ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ + ADC_SMPR1_SMP20 )) + +#define ADC_SMPR0_CLEAR(__HANDLE__) __NOP() +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @brief Clear register CR2. * @param __HANDLE__: ADC handle * @retval None */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_CR2_CLEAR(__HANDLE__) \ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define ADC_CR2_CLEAR(__HANDLE__) \ (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ @@ -581,15 +462,15 @@ typedef struct ADC_CR2_CONT | ADC_CR2_ADON )) \ ) #else -#define __ADC_CR2_CLEAR(__HANDLE__) \ +#define ADC_CR2_CLEAR(__HANDLE__) \ (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ ADC_CR2_DMA | ADC_CR2_DELS | \ ADC_CR2_CONT | ADC_CR2_ADON )) \ ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + /** * @brief Set the sampling time of selected channel on register SMPR0 * Register SMPR0 availability depends on device category. If register is not @@ -599,31 +480,47 @@ typedef struct * @param __CHANNEL__: Channel number. * @retval None */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ - __ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ - __ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) + ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ + ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) #else -#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @brief Enable the ADC peripheral - * @param __HANDLE__: ADC handle - * @retval None + +#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ + ((CHANNEL) == ADC_INJECTED_RANK_2) || \ + ((CHANNEL) == ADC_INJECTED_RANK_3) || \ + ((CHANNEL) == ADC_INJECTED_RANK_4) ) + +#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) + +#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) + +/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification + * @{ */ -#define __ADC_ENABLE(__HANDLE__) \ - (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON - +#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) /** - * @brief Disable the ADC peripheral - * @param __HANDLE__: ADC handle - * @retval None + * @} */ -#define __ADC_DISABLE(__HANDLE__) \ - (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.c index 9faf26558ed..56ad0f447be 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.c @@ -2,10 +2,9 @@ ****************************************************************************** * @file stm32l1xx_hal_comp.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief COMP HAL module driver. - * * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: * + Initialization and de-initialization functions @@ -17,17 +16,15 @@ ================================================================================ ##### COMP Peripheral features ##### ================================================================================ - [..] The STM32L1xx device family integrates 2 analog comparators COMP1 and COMP2: (#) The non inverting input and inverting input can be set to GPIO pins. - Refer to "table1. COMP Inputs" below. HAL COMP driver configures the Routing Interface (RI) to connect the selected I/O pins to comparator input. Caution: Comparator COMP1 and ADC cannot be used at the same time as ADC since they share the ADC switch matrix: COMP1 non-inverting - input is routed through ADC switch matrix. Except if ADC is intented + input is routed through ADC switch matrix. Except if ADC is intended to measure voltage on COMP1 non-inverting input: it can be performed on ADC channel VCOMP. @@ -36,7 +33,6 @@ (#) The COMP output can be redirected to embedded timers (TIM2, TIM3, TIM4, TIM10). COMP output cannot be redirected to any I/O pin. - Refer to "table 2. COMP Outputs redirection to embedded timers" below. (#) The comparators COMP1 and COMP2 can be combined in window mode. In this mode, COMP2 non inverting input is used as common @@ -47,55 +43,12 @@ (++) COMP1 is internally connected to EXTI Line 21 (++) COMP2 is internally connected to EXTI Line 22 - From the corresponding IRQ handler, the right interrupt source can be - retrieved with macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: - (++) COMP_EXTI_LINE_COMP1_EVENT - (++) COMP_EXTI_LINE_COMP2_EVENT + From the corresponding IRQ handler, the right interrupt source can be retrieved with the + macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG(). - (#) The comparators also offer the possibility to ouput the voltage + (#) The comparators also offer the possibility to output the voltage reference (VrefInt), used on inverting inputs, on I/O pin through - a buffer. To use it, refer to macro "__HAL_VREFINT_OUT_ENABLE()". - - -[..] Table 1. COMP Inputs for the STM32L1xx devices - +----------------------------------------------------------------------+ - | | | COMP1 | COMP2 | - |-----------------|--------------------------------|---------|---------| - | | 1/4 VREFINT | -- | OK | - | | 1/2 VREFINT | -- | OK | - | | 3/4 VREFINT | -- | OK | - | Inverting | VREFINT | OK | OK | - | input | DAC Ch1 OUT (PA4) | -- | OK | - | | DAC Ch2 OUT (PA5) | -- | OK | - | | IO: PB3 | -- | OK | - |-----------------|--------------------------------|---------|---------| - | | IO: | | | - | | PB4, 5, 6*, 7* | --- | OK | - | Non-inverting | PA0*, 1*, 2*, 3*, 4, 5, 6, 7 | OK | --- | - | input | PB0, 1, 12, 13, 14, 15 | OK | --- | - | | PC0, 1, 2, 3, 4, 5 | OK | --- | - | | PE7, 8, 9, 10 | OK | --- | - | | PF6, 7, 8, 9, 10 | OK | --- | - | | OPAMP1 output | OK | --- | - | | OPAMP2 output | OK | --- | - | | OPAMP3 output** | OK | --- | - +----------------------------------------------------------------------+ - *: Available on devices category Cat.3, Cat.4, Cat.5 only. - **: Available on devices category Cat.4 only. - - [..] Table 2. COMP Outputs redirection to embedded timers - +-----------------------------------+ - | COMP1 | COMP2 | - |-----------------|-----------------| - | | TIM2 IC4 | - | | TIM2 OCREF CLR | - | (no redirection | TIM3 IC4 | - | to timers) | TIM3 OCREF CLR | - | | TIM4 IC4 | - | | TIM4 OCREF CLR | - | | TIM10 IC1 | - +-----------------------------------+ - + a buffer. To use it, refer to macro "__HAL_SYSCFG_VREFINT_OUT_ENABLE()". ##### How to use this driver ##### ================================================================================ @@ -109,7 +62,7 @@ - For all inputs: I/O pin in analog mode (Schmitt trigger disabled) - Possible alternate configuration, for non-inverting inputs of comparator 2: I/O pin in floating mode (Schmitt trigger enabled). It is recommended to use analog configuration to avoid any overconsumption around VDD/2. - (++) Enable COMP Peripheral clock using macro __COMP_CLK_ENABLE() + (++) Enable COMP Peripheral clock using macro __HAL_RCC_COMP_CLK_ENABLE() (++) If required enable the COMP interrupt (EXTI line Interrupt): enable the comparator interrupt vector using HAL_NVIC_EnableIRQ(COMP_IRQn) and HAL_NVIC_SetPriority(COMP_IRQn, xxx, xxx) functions. @@ -139,7 +92,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -166,6 +119,48 @@ ****************************************************************************** */ +/* + Additionnal remark: + Table 1. COMP Inputs for the STM32L1xx devices + +----------------------------------------------------------------------+ + | | | COMP1 | COMP2 | + |-----------------|--------------------------------|---------|---------| + | | 1/4 VREFINT | -- | OK | + | | 1/2 VREFINT | -- | OK | + | | 3/4 VREFINT | -- | OK | + | Inverting | VREFINT | OK | OK | + | input | DAC Ch1 OUT (PA4) | -- | OK | + | | DAC Ch2 OUT (PA5) | -- | OK | + | | IO: PB3 | -- | OK | + |-----------------|--------------------------------|---------|---------| + | | IO: | | | + | | PB4, 5, 6*, 7* | --- | OK | + | Non-inverting | PA0*, 1*, 2*, 3*, 4, 5, 6, 7 | OK | --- | + | input | PB0, 1, 12, 13, 14, 15 | OK | --- | + | | PC0, 1, 2, 3, 4, 5 | OK | --- | + | | PE7, 8, 9, 10 | OK | --- | + | | PF6, 7, 8, 9, 10 | OK | --- | + | | OPAMP1 output | OK | --- | + | | OPAMP2 output | OK | --- | + | | OPAMP3 output** | OK | --- | + +----------------------------------------------------------------------+ + *: Available on devices category Cat.3, Cat.4, Cat.5 only. + **: Available on devices category Cat.4 only. + + [..] Table 2. COMP Outputs redirection to embedded timers + +-----------------------------------+ + | COMP1 | COMP2 | + |-----------------|-----------------| + | | TIM2 IC4 | + | | TIM2 OCREF CLR | + | (no redirection | TIM3 IC4 | + | to timers) | TIM3 OCREF CLR | + | | TIM4 IC4 | + | | TIM4 OCREF CLR | + | | TIM10 IC1 | + +-----------------------------------+ +*/ + /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" @@ -186,15 +181,15 @@ /** @defgroup COMP_Private_Constants COMP Private Constants * @{ */ - /* Delay for COMP startup time. */ + /* Delay for COMP start-up time. */ /* Maximum delay is 10us for comparator 1 and 25us for comparator 2 in slow */ /* mode (refer to device datasheet, parameter tSTART). */ /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */ /* have the minimum number of CPU cycles to fulfill this delay. */ - /* - Comparator 1: delay minimum of 320 CPU cyles. Wait loop takes 3 CPU */ + /* - Comparator 1: delay minimum of 320 CPU cycles. Wait loop takes 3 CPU */ /* cycles per iteration, therefore total wait iterations */ /* number must be initialized at 106 iterations. */ - /* - Comparator 2: delay minimum of 800 CPU cyles. Wait loop takes 3 CPU */ + /* - Comparator 2: delay minimum of 800 CPU cycles. Wait loop takes 3 CPU */ /* cycles per iteration, therefore total wait iterations */ /* number must be initialized at 266 iterations. */ #define COMP1_START_DELAY_CPU_CYCLES ((uint32_t)106) @@ -245,7 +240,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -269,8 +264,8 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* In window mode, non-inverting inputs of the 2 comparators are */ /* connected together and are using inputs of COMP2 only. If COMP1 is */ /* selected, this parameter is discarded. */ - if ((hcomp->Init.WindowMode == COMP_WINDOWMODE_DISABLED) || - (hcomp->Instance == COMP2) ) + if ((hcomp->Init.WindowMode == COMP_WINDOWMODE_DISABLE) || + (hcomp->Instance == COMP2) ) { assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput)); } @@ -279,8 +274,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Enable SYSCFG clock and the low level hardware to access comparators */ if(hcomp->State == HAL_COMP_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcomp->Lock = HAL_UNLOCKED; + /* Enable SYSCFG clock to control the routing Interface (RI) */ - __SYSCFG_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); @@ -380,7 +378,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -441,6 +439,9 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) */ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_COMP_MspInit could be implenetd in the user file */ @@ -453,6 +454,9 @@ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) */ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_COMP_MspDeInit could be implenetd in the user file */ @@ -489,7 +493,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) __IO uint32_t wait_loop_index = 0; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -507,7 +511,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* inverting input selection also enables the comparator 2. */ __HAL_COMP_ENABLE(hcomp); - /* Set delay for COMP startup time */ + /* Set delay for COMP start-up time */ if (hcomp->Instance == COMP1) { wait_loop_cycles = COMP1_START_DELAY_CPU_CYCLES; @@ -517,7 +521,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) wait_loop_cycles = COMP2_START_DELAY_CPU_CYCLES; } - /* Delay for COMP startup time. */ + /* Delay for COMP start-up time. */ /* Delay fixed to worst case: maximum CPU frequency */ while(wait_loop_index < wait_loop_cycles) { @@ -547,7 +551,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -590,36 +594,34 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); /* Get the Exti Line output configuration */ - extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + extiline = COMP_GET_EXTI_LINE(hcomp->Instance); - /* Configure the rising edge */ - /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_RISING or */ - /* COMP_TRIGGERMODE_IT_RISING_FALLING. */ + /* Configure the trigger rising edge */ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET) { - __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline); + SET_BIT(EXTI->RTSR, extiline); } else { - __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline); + CLEAR_BIT(EXTI->RTSR, extiline); } - - /* Configure the falling edge */ - /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_FALLING or */ - /* COMP_TRIGGERMODE_IT_RISING_FALLING. */ + + /* Configure the trigger falling edge */ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET) { - __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline); + SET_BIT(EXTI->FTSR, extiline); } else { - __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline); + CLEAR_BIT(EXTI->FTSR, extiline); } - /* Enable Exti interrupt mode */ - __HAL_COMP_EXTI_ENABLE_IT(extiline); - /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + /* Clear COMP EXTI pending bit */ + WRITE_REG(EXTI->PR, extiline); + + /* Enable EXTI interrupt mode */ + SET_BIT(EXTI->IMR, extiline); + } return status; @@ -634,8 +636,8 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - /* Disable the Exti Line interrupt mode */ - __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance)); + /* Disable the EXTI Line interrupt mode */ + CLEAR_BIT(EXTI->IMR, COMP_GET_EXTI_LINE(hcomp->Instance)); status = HAL_COMP_Stop(hcomp); @@ -649,13 +651,13 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) */ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) { - uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance); /* Check COMP Exti flag */ - if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET) + if(READ_BIT(EXTI->PR, extiline) != RESET) { - /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + /* Clear COMP EXTI pending bit */ + WRITE_REG(EXTI->PR, extiline); /* COMP trigger user callback */ HAL_COMP_TriggerCallback(hcomp); @@ -694,7 +696,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -703,8 +705,20 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - /* Set lock flag */ - hcomp->State |= COMP_STATE_BIT_LOCK; + /* Set lock flag on state */ + switch(hcomp->State) + { + case HAL_COMP_STATE_BUSY: + hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; + break; + case HAL_COMP_STATE_READY: + hcomp->State = HAL_COMP_STATE_READY_LOCKED; + break; + default: + /* unexpected state */ + status = HAL_ERROR; + break; + } } return status; @@ -748,6 +762,9 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) */ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_TriggerCallback should be implemented in the user file */ @@ -780,7 +797,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ - if(hcomp == HAL_NULL) + if(hcomp == NULL) { return HAL_COMP_STATE_RESET; } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.h index daf8954e5f3..4ab2a87b88d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_comp.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -194,11 +194,11 @@ typedef struct /** @defgroup COMP_WindowMode COMP WindowMode * @{ */ -#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled: COMP1 non-inverting input is independant */ -#define COMP_WINDOWMODE_ENABLED COMP_CSR_WNDWE /*!< Window mode enabled: COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP) (connected to COMP2 non-inverting input) */ +#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled: COMP1 non-inverting input is independant */ +#define COMP_WINDOWMODE_ENABLE COMP_CSR_WNDWE /*!< Window mode enabled: COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP) (connected to COMP2 non-inverting input) */ -#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \ - ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED)) +#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \ + ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE)) /** * @} */ @@ -236,8 +236,8 @@ typedef struct /** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent * @{ */ -#define COMP_EXTI_LINE_COMP1_EVENT EXTI_RTSR_TR21 /*!< External interrupt line 21 Connected to COMP1 */ -#define COMP_EXTI_LINE_COMP2_EVENT EXTI_RTSR_TR22 /*!< External interrupt line 22 Connected to COMP2 */ +#define COMP_EXTI_LINE_COMP1 EXTI_RTSR_TR21 /*!< External interrupt line 21 Connected to COMP1 */ +#define COMP_EXTI_LINE_COMP2 EXTI_RTSR_TR22 /*!< External interrupt line 22 Connected to COMP2 */ /** * @} @@ -303,8 +303,7 @@ typedef struct : \ CLEAR_BIT(COMP->CSR, COMP_CSR_INSEL) \ ) - - + /** @brief Checks whether the specified COMP flag is set or not. * @param __HANDLE__: specifies the COMP Handle. * @param __FLAG__: specifies the flag to check. @@ -314,91 +313,173 @@ typedef struct */ #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->CSR, (__FLAG__)) == (__FLAG__)) +/** + * @brief Enable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) /** - * @brief Enable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Disable the COMP1 EXTI line rising edge trigger. + * @retval None */ -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->RTSR, (__EXTILINE__))) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) /** - * @brief Disable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Enable the COMP1 EXTI line falling edge trigger. + * @retval None */ -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))) +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) /** - * @brief Enable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Disable the COMP1 EXTI line falling edge trigger. + * @retval None */ -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->FTSR, (__EXTILINE__))) +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) /** - * @brief Disable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Enable the COMP1 EXTI line rising & falling edge trigger. + * @retval None */ -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) /** - * @brief Get the specified EXTI line for a comparator instance - * @param __INSTANCE__: specifies the COMP instance. - * @retval value of @ref COMP_ExtiLineEvent + * @brief Disable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Enable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in interrupt mode. + * @retval None */ -#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) \ - ( ( ((__INSTANCE__) == COMP1) \ - )? \ - (COMP_EXTI_LINE_COMP1_EVENT) \ - : \ - (COMP_EXTI_LINE_COMP2_EVENT) \ - ) - +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) + /** - * @brief Enable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Enable the COMP1 EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Check whether the COMP1 EXTI line flag is set or not. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Clear the the COMP1 EXTI flag. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Generates a Software interrupt on COMP1 EXTI Line. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP2 EXTI line rising edge trigger. + * @retval None */ -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (SET_BIT(EXTI->IMR, (__EXTILINE__))) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) /** - * @brief Disable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Disable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Enable the COMP2 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI Line in event mode. + * @retval None */ -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (CLEAR_BIT(EXTI->IMR, (__EXTILINE__))) +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) /** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __FLAG__: specifies the COMP Exti sources to be checked. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval The state of __FLAG__ (SET or RESET). + * @brief Check whether the COMP2 EXTI line flag is set or not. + * @retval RESET or SET */ -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (READ_BIT(EXTI->PR, (__FLAG__))) +#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2) /** - * @brief Clear the COMP Exti flags. - * @param __FLAG__: specifies the COMP Exti sources to be cleared. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Clear the the COMP2 EXTI flag. + * @retval None */ -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) +#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) /** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTILINE__: specifies the COMP Exti sources to trig. - * This parameter can be a value of @ref COMP_ExtiLineEvent + * @brief Generates a Software interrupt on COMP1 EXTI Line. * @retval None */ -#define __HAL_COMP_EXTI_GENERATE_SWIT(__EXTILINE__) (SET_BIT(EXTI->SWIER, (__EXTILINE__))) +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2) /** * @} @@ -410,6 +491,19 @@ typedef struct * @{ */ +/** + * @brief Get the specified EXTI line for a comparator instance + * @param __INSTANCE__: specifies the COMP instance. + * @retval value of @ref COMP_ExtiLineEvent + */ +#define COMP_GET_EXTI_LINE(__INSTANCE__) \ + ( ( ((__INSTANCE__) == COMP1) \ + )? \ + (COMP_EXTI_LINE_COMP1) \ + : \ + (COMP_EXTI_LINE_COMP2) \ + ) + /** * @brief Select the COMP register CSR bit CMPxOUT corresponding to the * selected COMP instance. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp_ex.h index e6e267eb0f0..a90cf14c7d6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_comp_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of COMP HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,7 +63,7 @@ /** @defgroup COMPEx_NonInvertingInput COMPEx NonInvertingInput * @{ */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Non-inverting inputs specific to COMP2 */ #define COMP_NONINVERTINGINPUT_PB4 RI_IOSWITCH_GR6_1 /*!< I/O pin PB4 connection to COMP2 non-inverting input */ #define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */ @@ -107,7 +107,7 @@ #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) #define COMP_NONINVERTINGINPUT_OPAMP3 COMP_NONINVERTINGINPUT_PC3 /*!< OPAMP3 output connection to COMP1 non-inverting input */ #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) /* Non-inverting inputs specific to COMP2 */ @@ -181,7 +181,7 @@ #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ ((INPUT) == COMP_NONINVERTINGINPUT_PB5) || \ ((INPUT) == COMP_NONINVERTINGINPUT_PB6) || \ @@ -216,7 +216,7 @@ ((INPUT) == COMP_NONINVERTINGINPUT_PF8) || \ ((INPUT) == COMP_NONINVERTINGINPUT_PF9) || \ ((INPUT) == COMP_NONINVERTINGINPUT_PF10) ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) #define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ @@ -301,14 +301,14 @@ * @param __HANDLE__: COMP handle. * @retval None. */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__) \ (((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) && \ (READ_BIT(COMP->CSR, COMP_CSR_SW1) == RESET) ) #else #define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__) \ ((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.c index 3224435662f..dc2b7617c74 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_cortex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief CORTEX HAL module driver. * * This file provides firmware functions to manage the following @@ -93,7 +93,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -227,6 +227,9 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } @@ -240,6 +243,9 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } @@ -278,13 +284,60 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK) functionalities. + (NVIC, SYSTICK, MPU) functionalities. @endverbatim * @{ */ +#if (__MPU_PRESENT == 1) +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} +#endif /* __MPU_PRESENT */ + /** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.h index df69e63f77a..f3708370300 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -52,8 +52,51 @@ /** @addtogroup CORTEX * @{ - */ + */ + /* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants @@ -89,6 +132,136 @@ * @} */ +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ /** * @} */ @@ -111,30 +284,8 @@ #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source_Macro_Exported CORTEX SysTick clock source - * @{ - */ +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) -/** @brief Configures the SysTick clock source. - * @param __CLKSRC__: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \ - do { \ - if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \ - { \ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \ - } \ - else \ - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \ - } while(0) /** * @} */ @@ -157,12 +308,124 @@ * @} */ +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + /** * @} */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Functions CORTEX Private Functions + * @brief CORTEX private functions + * @{ + */ -/* Exported functions --------------------------------------------------------*/ +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +__STATIC_INLINE void HAL_MPU_Disable(void) +{ + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +/** + * @brief Enables the MPU + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +} +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions * @{ */ @@ -185,6 +448,9 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); * @{ */ /* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.c index 3ee4f5604eb..650f86a5b07 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_crc.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -18,7 +18,7 @@ [..] The CRC HAL driver can be used as follows: - (#) Enable CRC AHB clock using __CRC_CLK_ENABLE(); + (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); (#) Use HAL_CRC_Accumulate() function to compute the CRC value of a 32-bit data buffer using combination of the previous CRC value @@ -32,7 +32,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -112,7 +112,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == HAL_NULL) + if(hcrc == NULL) { return HAL_ERROR; } @@ -122,6 +122,9 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) if(hcrc->State == HAL_CRC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } @@ -145,7 +148,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == HAL_NULL) + if(hcrc == NULL) { return HAL_ERROR; } @@ -177,6 +180,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CRC_MspInit could be implemented in the user file */ @@ -190,6 +196,9 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CRC_MspDeInit could be implemented in the user file */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.h index bd192847a44..f8e9cd1bbb5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_crc.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -116,7 +116,7 @@ typedef struct * @param __VALUE__: 8-bit value to be stored in the ID register * @retval None */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)) +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.c index 56b1b61a2c0..9a35facd0db 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_cryp.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief CRYP HAL module driver. * * This file provides firmware functions to manage the following @@ -22,14 +22,14 @@ The CRYP HAL driver can be used as follows: (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE() + (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE() (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT()) (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA()) (+) Enable the DMA2 interface clock using - (++) __DMA2_CLK_ENABLE() + (++) __HAL_RCC_DMA2_CLK_ENABLE() (+) Configure and enable two DMA Channels one for managing data transfer from memory to peripheral (input channel) and another channel for managing data transfer from peripheral to memory (output channel) @@ -70,7 +70,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -111,7 +111,7 @@ * @{ */ -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -181,28 +181,32 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ - if(hcryp == HAL_NULL) + if(hcryp == NULL) { return HAL_ERROR; } /* Check the parameters */ + assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance)); assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); if(hcryp->State == HAL_CRYP_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_CRYP_MspInit(hcryp); } /* Check if AES already enabled */ - if (HAL_IS_BIT_CLR(AES->CR, AES_CR_EN)) + if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN)) { /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; /* Set the data type*/ - MODIFY_REG(AES->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); /* Reset CrypInCount and CrypOutCount */ hcryp->CrypInCount = 0; @@ -237,7 +241,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ - if(hcryp == HAL_NULL) + if(hcryp == NULL) { return HAL_ERROR; } @@ -253,7 +257,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) hcryp->CrypOutCount = 0; /* Disable the CRYP Peripheral Clock */ - __HAL_CRYP_DISABLE(); + __HAL_CRYP_DISABLE(hcryp); /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_CRYP_MspDeInit(hcryp); @@ -276,6 +280,9 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) */ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + /* NOTE : This function should not be modified; when the callback is needed, the HAL_CRYP_MspInit can be implemented in the user file */ } @@ -288,6 +295,9 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) */ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + /* NOTE : This function should not be modified; when the callback is needed, the HAL_CRYP_MspDeInit can be implemented in the user file */ } @@ -354,13 +364,13 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -383,6 +393,9 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP } else { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -427,16 +440,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -459,6 +472,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP } else { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -503,16 +519,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -535,6 +551,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -579,13 +598,13 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -608,6 +627,9 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -652,16 +674,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -684,6 +706,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -725,16 +750,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CTR decryption mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -800,32 +825,32 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; @@ -834,6 +859,9 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -883,10 +911,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -896,22 +924,22 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; @@ -920,6 +948,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -969,10 +1000,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -982,22 +1013,22 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; @@ -1006,6 +1037,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -1055,32 +1089,32 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; @@ -1089,6 +1123,9 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -1138,10 +1175,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -1151,22 +1188,22 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; @@ -1175,6 +1212,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -1224,10 +1264,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CTR decryption mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -1237,22 +1277,22 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; @@ -1261,6 +1301,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + /* Return function status */ return HAL_ERROR; } @@ -1308,7 +1351,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -1323,7 +1366,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t return HAL_OK; } else - { + { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1370,7 +1416,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -1389,6 +1435,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1435,7 +1484,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -1455,6 +1504,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1501,10 +1553,10 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; @@ -1521,6 +1573,9 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1567,10 +1622,10 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -1590,6 +1645,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1636,7 +1694,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -1656,6 +1714,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1688,6 +1749,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + /* NOTE : This function should not be modified; when the callback is needed, the HAL_CRYP_ErrorCallback can be implemented in the user file */ @@ -1701,6 +1765,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + /* NOTE : This function should not be modified; when the callback is needed, the HAL_CRYP_InCpltCallback can be implemented in the user file */ @@ -1714,6 +1781,9 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) */ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + /* NOTE : This function should not be modified; when the callback is needed, the HAL_CRYP_OutCpltCallback can be implemented in the user file */ @@ -1745,27 +1815,27 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { /* Check if error occurred*/ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_ERR) != RESET) + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET) { - if (__HAL_CRYP_GET_FLAG(AES_FLAG_RDERR) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET) { - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_RDERR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR); } - if (__HAL_CRYP_GET_FLAG(AES_FLAG_WRERR) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET) { - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_WRERR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR); } - if (__HAL_CRYP_GET_FLAG(AES_FLAG_CCF) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) { - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF); } hcryp->State= HAL_CRYP_STATE_ERROR; /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - __HAL_CRYP_DISABLE_IT(AES_IT_ERR); + __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC); + __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR); HAL_CRYP_ErrorCallback(hcryp); @@ -1776,10 +1846,10 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } /* Check if computation complete interrupt was enabled*/ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_CC) != RESET) + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET) { /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF); CRYP_EncryptDecrypt_IT(hcryp); } @@ -1840,13 +1910,13 @@ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; /* Read the Output block from the Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; hcryp->pCrypOutBuffPtr += 16; hcryp->CrypOutCount -= 16; @@ -1855,8 +1925,8 @@ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) if(hcryp->CrypOutCount == 0) { /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - __HAL_CRYP_DISABLE_IT(AES_IT_ERR); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CC); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_ERR); /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -1873,13 +1943,13 @@ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; } @@ -1895,7 +1965,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Disable the DMA transfer for input request */ - CLEAR_BIT(AES->CR, AES_CR_DMAINEN); + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); /* Call input data transfer complete callback */ HAL_CRYP_InCpltCallback(hcryp); @@ -1912,13 +1982,13 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit in the DMACR register */ - CLEAR_BIT(AES->CR, AES_CR_DMAOUTEN); + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF); /* Disable CRYP */ - __HAL_CRYP_DISABLE(); + __HAL_CRYP_DISABLE(hcryp); /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; @@ -1956,13 +2026,13 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key) { uint32_t keyaddr = (uint32_t)Key; - AES->KEYR3 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - AES->KEYR2 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - AES->KEYR1 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - AES->KEYR0 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); } /** @@ -1982,13 +2052,13 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) { uint32_t ivaddr = (uint32_t)InitVector; - AES->IVR3 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; - AES->IVR2 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; - AES->IVR1 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; - AES->IVR0 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); } /** @@ -2012,19 +2082,19 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In for(index=0; (index < Ilength); index += 16) { /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(AES->SR, AES_SR_CCF)) + while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -2042,16 +2112,16 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In } } /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF); /* Read the Output block from the Data Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; } /* Return function status */ @@ -2080,23 +2150,23 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&AES->DINR, Size/4); + HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); /* Enable the DMA Out DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&AES->DOUTR, outputaddr, Size/4); + HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); /* Enable In and Out DMA requests */ - SET_BIT(AES->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); + SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); } /** * @} */ -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.h index baa5edca861..291c34cbb05 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_cryp.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" @@ -104,6 +104,8 @@ typedef enum */ typedef struct { + AES_TypeDef *Instance; /*!< Register base address */ + CRYP_InitTypeDef Init; /*!< CRYP required parameters */ uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ @@ -172,8 +174,8 @@ typedef struct /** @defgroup CRYP_AES_Interrupts AES Interrupts * @{ */ -#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */ -#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */ +#define CRYP_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */ +#define CRYP_IT_ERR AES_CR_ERRIE /*!< Error interrupt */ /** * @} @@ -183,9 +185,9 @@ typedef struct /** @defgroup CRYP_AES_Flags AES Flags * @{ */ -#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */ -#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */ -#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */ +#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */ +#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */ +#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */ /** * @} @@ -194,9 +196,9 @@ typedef struct /** @defgroup CRYP_AES_Clear_Flags AES Clear Flags * @{ */ -#define AES_CLEARFLAG_CCF AES_CR_CCFC /*!< Computation Complete Flag Clear */ -#define AES_CLEARFLAG_RDERR AES_CR_ERRC /*!< Read Error Clear */ -#define AES_CLEARFLAG_WRERR AES_CR_ERRC /*!< Write Error Clear */ +#define CRYP_CLEARFLAG_CCF AES_CR_CCFC /*!< Computation Complete Flag Clear */ +#define CRYP_CLEARFLAG_RDERR AES_CR_ERRC /*!< Read Error Clear */ +#define CRYP_CLEARFLAG_WRERR AES_CR_ERRC /*!< Write Error Clear */ /** * @} @@ -213,71 +215,76 @@ typedef struct */ /** @brief Reset CRYP handle state - * @param __HANDLE__: specifies the CRYP Handle. + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) /** * @brief Enable/Disable the CRYP peripheral. + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ -#define __HAL_CRYP_ENABLE() SET_BIT(AES->CR, AES_CR_EN) -#define __HAL_CRYP_DISABLE() CLEAR_BIT(AES->CR, AES_CR_EN) +#define __HAL_CRYP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, AES_CR_EN) +#define __HAL_CRYP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, AES_CR_EN) /** * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,... + * @param __HANDLE__: specifies the CRYP handle. * @param __MODE__: The algorithm mode. * @retval None */ -#define __HAL_CRYP_SET_MODE(__MODE__) SET_BIT(AES->CR, (__MODE__)) +#define __HAL_CRYP_SET_MODE(__HANDLE__,__MODE__) SET_BIT((__HANDLE__)->Instance->CR, (__MODE__)) /** @brief Check whether the specified CRYP flag is set or not. + * @param __HANDLE__: specifies the CRYP handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg AES_FLAG_CCF : Computation Complete Flag - * @arg AES_FLAG_RDERR : Read Error Flag - * @arg AES_FLAG_WRERR : Write Error Flag + * @arg CRYP_FLAG_CCF : Computation Complete Flag + * @arg CRYP_FLAG_RDERR : Read Error Flag + * @arg CRYP_FLAG_WRERR : Write Error Flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_CRYP_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the CRYP pending flag. * @param __HANDLE__: specifies the CRYP handle. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: - * @arg AES_CLEARFLAG_CCF : Computation Complete Clear Flag - * @arg AES_CLEARFLAG_RDERR : Read Error Clear - * @arg AES_CLEARFLAG_WRERR : Write Error Clear + * @arg CRYP_CLEARFLAG_CCF : Computation Complete Clear Flag + * @arg CRYP_CLEARFLAG_RDERR : Read Error Clear + * @arg CRYP_CLEARFLAG_WRERR : Write Error Clear * @retval None */ -#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(AES->CR, (__FLAG__)) +#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__)) /** * @brief Enable the CRYP interrupt. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. * @retval None */ -#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__)) +#define __HAL_CRYP_ENABLE_IT(__HANDLE__,__INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** * @brief Disable the CRYP interrupt. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP interrupt. * @retval None */ -#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(AES->CR, (__INTERRUPT__)) +#define __HAL_CRYP_DISABLE_IT(__HANDLE__,__INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Checks if the specified CRYP interrupt source is enabled or disabled. - * @param __HANDLE__: CRYP handle + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP interrupt source to check * This parameter can be one of the following values: - * @arg AES_IT_CC : Computation Complete interrupt - * @arg AES_IT_ERR : Error interrupt (used for RDERR and WRERR) + * @arg CRYP_IT_CC : Computation Complete interrupt + * @arg CRYP_IT_ERR : Error interrupt (used for RDERR and WRERR) * @retval State of interruption (SET or RESET) */ #define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (( (AES->CR & (__INTERRUPT__)) == (__INTERRUPT__) \ + (( ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__) \ )? SET : RESET \ ) @@ -285,12 +292,12 @@ typedef struct * @param __HANDLE__: specifies the CRYP handle. * @param __IT__: specifies the IT to clear. * This parameter can be one of the following values: - * @arg AES_CLEARFLAG_CCF : Computation Complete Clear Flag - * @arg AES_CLEARFLAG_RDERR : Read Error Clear - * @arg AES_CLEARFLAG_WRERR : Write Error Clear + * @arg CRYP_CLEARFLAG_CCF : Computation Complete Clear Flag + * @arg CRYP_CLEARFLAG_RDERR : Read Error Clear + * @arg CRYP_CLEARFLAG_WRERR : Write Error Clear * @retval None */ -#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT(AES->CR, (__IT__)) +#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT((__HANDLE__)->Instance->CR, (__IT__)) /** * @} @@ -400,7 +407,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/ #ifdef __cplusplus } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c index 82969a8cc05..43a2b46d46d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief CRYPEx HAL module driver. * * This file provides firmware functions to manage the following @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,7 +54,7 @@ * @{ */ -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -90,8 +90,11 @@ */ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ComputationCpltCallback could be implemented in the user file + the HAL_CRYPEx_ComputationCpltCallback could be implemented in the user file */ } @@ -104,7 +107,7 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) * @} */ -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h index 042fba3572e..1db95790ce3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of CRYPEx HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" @@ -79,7 +79,7 @@ void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.c index 59799512fe7..107d1b00d0b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_dac.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -29,17 +29,17 @@ *** DAC Triggers *** ==================== [..] - Digital to Analog conversion can be non-triggered using DAC_Trigger_None + Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. [..] Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. + (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. + The used pin (GPIOx_PIN_9) must be configured in input mode. (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7, TIM9 (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) - (#) Software using DAC_Trigger_Software + (#) Software using DAC_TRIGGER_SOFTWARE *** DAC Buffer mode feature *** =============================== @@ -48,17 +48,35 @@ reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. To enable, the output buffer use - sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; [..] (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. - + + *** DAC connect feature *** + =============================== + [..] + Each DAC channel can be connected internally. + To connect, use + sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE; + + *** GPIO configurations guidelines *** + ===================== + [..] + When a DAC channel is used (ex channel1 on PA4) and the other is not + (ex channel1 on PA5 is configured in Analog and disabled). + Channel1 may disturb channel2 as coupling effect. + Note that there is no coupling on channel2 as soon as channel2 is turned on. + Coupling on adjacent channel could be avoided as follows: + when unused PA5 is configured as INPUT PULL-UP or DOWN. + PA5 is configured in ANALOG just before it is turned on. + *** DAC wave generation feature *** =================================== [..] Both DAC channels can be used to generate - (#) Noise wave - (#) Triangle wave + (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() + (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate() *** DAC data format *** ======================= @@ -68,17 +86,20 @@ (#) 12-bit left alignment using DAC_ALIGN_12B_L (#) 12-bit right alignment using DAC_ALIGN_12B_R - *** DAC data value to voltage correspondence *** + *** DAC data value to voltage correspondance *** ================================================ [..] The analog output voltage on each DAC channel pin is determined - by the following equation: + by the following equation: + [..] DAC_OUTx = VREF+ * DOR / 4095 - with DOR is the Data Output Register + (+) with DOR is the Data Output Register + [..] VEF+ is the input voltage reference (refer to the device datasheet) + [..] e.g. To set DAC_OUT1 to 0.7V, use - Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - + (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + *** DMA requests *** ===================== [..] @@ -87,9 +108,11 @@ HAL_DAC_Start_DMA() [..] DMA1 requests are mapped as following: - (#) DAC channel1 : mapped on DMA1 channel2 which must be + (#) DAC channel1 : + mapped on DMA1 channel2 which must be already configured - (#) DAC channel2 : mapped on DMA1 channel3 which must be + (#) DAC channel2 : + mapped on DMA1 channel3 which must be already configured -@- For Dual mode and specific signal (Triangle and noise) generation please @@ -109,7 +132,7 @@ ================================= [..] (+) Start the DAC peripheral using HAL_DAC_Start() - (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function. + (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. (+) Stop the DAC peripheral using HAL_DAC_Stop() *** DMA mode IO operation *** @@ -117,21 +140,22 @@ [..] (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length of data to be transferred at each end of conversion - (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DAC_ConvHalfCpltCallbackCh2() + (+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 - (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can - add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 - (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. - HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DAC_DMAUnderrunCallbackCh2() + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2 + (+) For STM32F100x devices with specific feature: DMA underrun. + In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. + HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2() function is executed and user can add his own code by customization of function pointer - HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DAC_DMAUnderrunCallbackCh2 + HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() - + *** DAC HAL driver macros list *** ============================================= [..] @@ -149,7 +173,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -237,7 +261,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) { /* Check DAC handle */ - if(hdac == HAL_NULL) + if(hdac == NULL) { return HAL_ERROR; } @@ -246,6 +270,9 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) if(hdac->State == HAL_DAC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hdac->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_DAC_MspInit(hdac); } @@ -272,7 +299,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) { /* Check DAC handle */ - if(hdac == HAL_NULL) + if(hdac == NULL) { return HAL_ERROR; } @@ -307,6 +334,9 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file */ @@ -320,6 +350,9 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file */ @@ -359,8 +392,6 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { - uint32_t tmp1 = 0, tmp2 = 0; - /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -375,10 +406,8 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) if(Channel == DAC_CHANNEL_1) { - tmp1 = hdac->Instance->CR & DAC_CR_TEN1; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); @@ -386,10 +415,8 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) } else { - tmp1 = hdac->Instance->CR & DAC_CR_TEN2; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2)) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); @@ -401,7 +428,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } @@ -451,7 +478,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { uint32_t tmpreg = 0; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); @@ -461,21 +488,21 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + if(Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - + /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - + /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - + /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - + /* Case of use of channel 1 */ switch(Alignment) { @@ -499,16 +526,16 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; - + /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; - + /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - + /* Case of use of channel 2 */ switch(Alignment) { @@ -529,13 +556,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u } } - /* Enable the DMA Stream */ + /* Enable the DMA channel */ if(Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - /* Enable the DMA Stream */ + /* Enable the DMA channel */ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else @@ -543,20 +570,20 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); - /* Enable the DMA Stream */ + /* Enable the DMA channel */ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } - /* Enable the Peripharal */ - __HAL_DAC_ENABLE(hdac, Channel); - /* Process Unlocked */ __HAL_UNLOCK(hdac); + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + /* Return function status */ return HAL_OK; } - + /** * @brief Disables DAC and stop conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -575,24 +602,24 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) assert_param(IS_DAC_CHANNEL(Channel)); /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1 << Channel); /* Disable the Peripharal */ __HAL_DAC_DISABLE(hdac, Channel); /* Disable the DMA Channel */ /* Channel1 is used */ - if(Channel == DAC_CHANNEL_1) - { + if (Channel == DAC_CHANNEL_1) + { status = HAL_DMA_Abort(hdac->DMA_Handle1); } else /* Channel2 is used for */ - { - status = HAL_DMA_Abort(hdac->DMA_Handle2); + { + status = HAL_DMA_Abort(hdac->DMA_Handle2); } - + /* Check if DMA Channel effectively disabled */ - if(status != HAL_OK) + if (status != HAL_OK) { /* Update ADC state machine to error */ hdac->State = HAL_DAC_STATE_ERROR; @@ -602,7 +629,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } - + /* Return function status */ return status; } @@ -688,6 +715,9 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file */ @@ -701,6 +731,9 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file */ @@ -714,6 +747,9 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) */ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file */ @@ -727,6 +763,9 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ @@ -764,7 +803,7 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { - uint32_t tmpreg1 = 0, tmpreg2 = 0; + uint32_t tmpreg1 = 0; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); @@ -777,20 +816,19 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); + SET_BIT(tmpreg1, (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer)); + + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; + MODIFY_REG(hdac->Instance->CR, + ((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel, + tmpreg1 << Channel); + /* Disable wave generation */ - DAC->CR &= ~(DAC_CR_WAVE1 << Channel); + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -830,11 +868,11 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui tmp = (uint32_t)hdac->Instance; if(Channel == DAC_CHANNEL_1) { - tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment); + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } else { - tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment); + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } /* Set the DAC channel selected data holding register */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.h index 8e03a026c27..62304c16369 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_dac.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -113,14 +113,14 @@ typedef struct /** @defgroup DAC_Exported_Constants DAC Exported Constants * @{ - */ + */ /** @defgroup DAC_Error_Code DAC Error Code * @{ */ #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ #define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ /** * @} @@ -139,14 +139,6 @@ typedef struct #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ - ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T9_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) /** * @} */ @@ -157,8 +149,6 @@ typedef struct #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ - ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) /** * @} */ @@ -169,8 +159,6 @@ typedef struct #define DAC_CHANNEL_1 ((uint32_t)0x00000000) #define DAC_CHANNEL_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ - ((CHANNEL) == DAC_CHANNEL_2)) /** * @} */ @@ -182,17 +170,6 @@ typedef struct #define DAC_ALIGN_12B_L ((uint32_t)0x00000004) #define DAC_ALIGN_8B_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ - ((ALIGN) == DAC_ALIGN_12B_L) || \ - ((ALIGN) == DAC_ALIGN_8B_R)) -/** - * @} - */ - -/** @defgroup DAC_data DAC data - * @{ - */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ @@ -249,27 +226,13 @@ typedef struct #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) -/** @brief Set DHR12R1 alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) - -/** @brief Set DHR12R2 alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) - -/** @brief Set DHR12RD alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) /** @brief Enable the DAC interrupt * @param __HANDLE__: specifies the DAC handle * @param __INTERRUPT__: specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt * @retval None */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) @@ -277,20 +240,39 @@ typedef struct /** @brief Disable the DAC interrupt * @param __HANDLE__: specifies the DAC handle * @param __INTERRUPT__: specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt * @retval None */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) +/** @brief Checks if the specified DAC interrupt source is enabled or disabled. + * @param __HANDLE__: DAC handle + * @param __INTERRUPT__: DAC interrupt source to check + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt + * @retval State of interruption (SET or RESET) + */ +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) + /** @brief Get the selected DAC's flag status. * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the FLAG. + * @param __FLAG__: specifies the DAC flag to get. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag * @retval None */ #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the FLAG. + * @param __FLAG__: specifies the DAC flag to clear. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag * @retval None */ #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) @@ -299,6 +281,42 @@ typedef struct * @} */ +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T9_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) + +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) + +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) + +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) + +/** + * @} + */ + /* Include DAC HAL Extension module */ #include "stm32l1xx_hal_dac_ex.h" @@ -311,7 +329,7 @@ typedef struct /** @addtogroup DAC_Exported_Functions_Group1 * @{ - */ + */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); @@ -350,7 +368,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** @addtogroup DAC_Exported_Functions_Group2 * @{ */ -/* Peripheral State functions ***************************************************/ +/* Peripheral State functions *************************************************/ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); @@ -383,3 +401,4 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); #endif /*__STM32L1xx_HAL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.c index 46e61dbf453..419e73daae0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -25,7 +25,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -151,7 +151,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 hdac->State = HAL_DAC_STATE_BUSY; /* Enable the selected wave generation for the selected DAC channel */ - hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel; + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; @@ -199,7 +199,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t hdac->State = HAL_DAC_STATE_BUSY; /* Enable the selected wave generation for the selected DAC channel */ - hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel; + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; @@ -246,7 +246,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align } tmp = (uint32_t)hdac->Instance; - tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment); + tmp += DAC_DHR12RD_ALIGNMENT(Alignment); /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; @@ -264,6 +264,9 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align */ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file */ @@ -277,6 +280,9 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) */ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file */ @@ -290,6 +296,9 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) */ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file */ @@ -303,6 +312,9 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.h index 69692fafae6..2a9b76426ae 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -61,20 +61,6 @@ /** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ */ - -/** @defgroup DACEx_wave_generation DACEx wave generation - * @{ - */ -#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000) -#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) - -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \ - ((WAVE) == DAC_WAVEGENERATION_NOISE) || \ - ((WAVE) == DAC_WAVEGENERATION_TRIANGLE)) -/** - * @} - */ /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude * @{ @@ -138,8 +124,6 @@ #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \ - ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} */ @@ -177,12 +161,13 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); /** * @} */ + /** @addtogroup DACEx_Private_Functions * @{ - */ + */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_def.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_def.h index 903d83773a5..eb696465c0b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_def.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_def.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_hal_def.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. + * @version V1.1.3 + * @date 04-March-2016 + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,13 +46,15 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx.h" +#include "stm32_hal_legacy.h" +#include /* Exported types ------------------------------------------------------------*/ -/** - * @brief HAL Status structures definition - */ -typedef enum +/** + * @brief HAL Status structures definition + */ +typedef enum { HAL_OK = 0x00, HAL_ERROR = 0x01, @@ -60,19 +62,16 @@ typedef enum HAL_TIMEOUT = 0x03 } HAL_StatusTypeDef; -/** - * @brief HAL Lock structures definition +/** + * @brief HAL Lock structures definition */ -typedef enum +typedef enum { HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 + HAL_LOCKED = 0x01 } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ -#ifndef HAL_NULL - #define HAL_NULL (void *) 0 -#endif #define HAL_MAX_DELAY 0xFFFFFFFF @@ -85,13 +84,15 @@ typedef enum (__DMA_HANDLE_).Parent = (__HANDLE__); \ } while(0) +#define UNUSED(x) ((void)(x)) + /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: + * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function + * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling @@ -138,54 +139,71 @@ typedef enum #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) + #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN + #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ -/** +/** * @brief __RAM_FUNC definition - */ + */ #if defined ( __CC_ARM ) /* ARM Compiler ------------ - RAM functions are defined using the toolchain options. + RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' + Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. + dialog. */ -#define __RAM_FUNC HAL_StatusTypeDef +#define __RAM_FUNC HAL_StatusTypeDef #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". + RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc HAL_StatusTypeDef #elif defined ( __GNUC__ ) /* GNU Compiler ------------ - RAM functions are defined using a specific toolchain attribute + RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) #endif +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c index cac71a25c18..6692132a440 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32l1xx_hal_dma.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief DMA HAL module driver. * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions @@ -19,63 +19,61 @@ (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is necessary) please refer to Reference manual for connection between peripherals - and DMA requests . - + and DMA requests. + (#) For a given Channel, program the required configuration through the following parameters: Transfer Direction, Source and Destination data formats, - Circular, Normal or peripheral flow control mode, Channel Priority level, - Source and Destination Increment mode, FIFO mode and its Threshold (if needed), - Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. - + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** ================================= [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + *** Interrupt mode IO operation *** =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. In this - case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + *** DMA HAL driver macros list *** ============================================= [..] Below the list of most used macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. - + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + [..] (@) You can refer to the DMA HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -119,32 +117,31 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup DMA_Private_Constants DMA Private Constants -* @{ -*/ -#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ /** * @} */ - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions -* @{ -*/ + * @{ + */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); /** * @} */ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ /** @defgroup DMA_Exported_Functions DMA Exported Functions * @{ */ -/** @defgroup DMA_Group1 Initialization and de-initialization functions +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim @@ -174,8 +171,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0; - /* Check the DMA peripheral state */ - if(hdma == HAL_NULL) + /* Check the DMA handle allocation */ + if(hdma == NULL) { return HAL_ERROR; } @@ -190,6 +187,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + if(hdma->State == HAL_DMA_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + } + /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -214,11 +217,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; + hdma->State = HAL_DMA_STATE_READY; return HAL_OK; -} - +} + /** * @brief DeInitializes the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -227,13 +230,16 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { - /* Check the DMA peripheral state */ - if(hdma == HAL_NULL) + /* Check the DMA handle allocation */ + if(hdma == NULL) { return HAL_ERROR; } - /* Check the DMA peripheral handle */ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { return HAL_ERROR; @@ -259,7 +265,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Initialise the error code */ + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ @@ -275,7 +281,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup DMA_Group2 I/O operation functions +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions * @brief I/O operation functions * @verbatim @@ -304,27 +310,27 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ +{ /* Process locked */ - __HAL_LOCK(hdma); + __HAL_LOCK(hdma); - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); + __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); + __HAL_DMA_ENABLE(hdma); return HAL_OK; -} +} /** * @brief Start the DMA Transfer with interrupt enabled. @@ -340,8 +346,8 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Process locked */ __HAL_LOCK(hdma); - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); @@ -349,7 +355,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - /* Configure the source, destination address and the data length */ + /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete interrupt */ @@ -362,9 +368,9 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); + __HAL_DMA_ENABLE(hdma); - return HAL_OK; + return HAL_OK; } /** @@ -385,35 +391,35 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - - /* Get timeout */ + + /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA Channel is effectively disabled */ - while((hdma->Instance->CCR & DMA_CCR_EN) != 0) + while((hdma->Instance->CCR & DMA_CCR_EN) != 0) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_TIMEOUT; } } + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdma); - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; + return HAL_OK; } /** @@ -439,9 +445,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp { /* Half Transfer Complete flag */ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); - } - - /* Get timeout */ + } + + /* Get tick */ tickstart = HAL_GetTick(); while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) @@ -455,27 +461,27 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_ERROR; + hdma->State= HAL_DMA_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hdma); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_TIMEOUT; - + hdma->State = HAL_DMA_STATE_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_TIMEOUT; } } @@ -489,9 +495,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); + } else { @@ -499,12 +503,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ + all transfers of half buffer are complete) */ hdma->State = HAL_DMA_STATE_READY_HALF; - /* Process unlocked */ - __HAL_UNLOCK(hdma); } + /* Process unlocked */ + __HAL_UNLOCK(hdma); + return HAL_OK; } @@ -515,34 +520,34 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ +{ /* Transfer Error Interrupt management ***************************************/ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) - { + { /* Disable the transfer error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); - - /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); + + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); - + /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - + hdma->State = HAL_DMA_STATE_ERROR; + /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if (hdma->XferErrorCallback != HAL_NULL) - { + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { /* Transfer error callback */ - hdma->XferErrorCallback(hdma); + hdma->XferErrorCallback(hdma); + } } } - } /* Half Transfer Complete Interrupt management ******************************/ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) @@ -561,7 +566,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF; - if(hdma->XferHalfCpltCallback != HAL_NULL) + if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); @@ -575,9 +580,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the transfer complete interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); + { + /* Disable the transfer complete interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); @@ -586,31 +591,31 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; + hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); - if(hdma->XferCpltCallback != HAL_NULL) - { + if(hdma->XferCpltCallback != NULL) + { /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); + hdma->XferCpltCallback(hdma); + } } } -} -} +} /** * @} */ -/** @defgroup DMA_Group3 Peripheral State functions +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions * @brief Peripheral State functions * @verbatim =============================================================================== ##### State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state @@ -618,7 +623,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) @endverbatim * @{ - */ + */ /** * @brief Returns the DMA state. @@ -650,9 +655,9 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @} */ -/** @addtogroup DMA_Private_Functions -* @{ -*/ +/** @addtogroup DMA_Private_Functions DMA Private Functions + * @{ + */ /** * @brief Sets the DMA Transfer parameter. @@ -664,13 +669,13 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ +{ /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { + { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; @@ -692,10 +697,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t * @} */ - #endif /* HAL_DMA_MODULE_ENABLED */ - - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h index 2ca4ec09a81..77d15f88e78 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_dma.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,13 +54,14 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ - + /** - * @brief DMA Configuration Structure definition + * @brief DMA Configuration Structure definition */ typedef struct { @@ -87,11 +88,10 @@ typedef struct uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ - } DMA_InitTypeDef; /** - * @brief DMA Configuration enumeration values definition + * @brief DMA Configuration enumeration values definition */ typedef enum { @@ -105,32 +105,29 @@ typedef enum */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ + HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ + HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ - }HAL_DMA_StateTypeDef; /** - * @brief HAL DMA Error Code structure definition - */ + * @brief HAL DMA Error Code structure definition + */ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ - }HAL_DMA_LevelCompleteTypeDef; - /** - * @brief DMA handle Structure definition - */ + * @brief DMA handle Structure definition + */ typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_InitTypeDef Init; /*!< DMA communication parameters */ @@ -146,152 +143,112 @@ typedef struct __DMA_HandleTypeDef void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - __IO uint32_t ErrorCode; /*!< DMA Error code */ - + __IO uint32_t ErrorCode; /*!< DMA Error code */ } DMA_HandleTypeDef; /** * @} */ - - /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ -/** @defgroup DMA_Error_Code DMA_Error_Code +/** @defgroup DMA_Error_Code DMA Error Code * @{ - */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ + */ + #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ + #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */ + #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */ + /** * @} */ - -/** @defgroup DMA_Data_transfer_direction DMA_Data_transfer_direction +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) /** * @} */ -/** @defgroup DMA_Data_buffer_size DMA_Data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA_Peripheral_incremented_mode +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) /** * @} */ -/** @defgroup DMA_Memory_incremented_mode DMA_Memory_incremented_mode +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ /** * @} */ -/** @defgroup DMA_Peripheral_data_size DMA_Peripheral_data_size +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} */ - -/** @defgroup DMA_Memory_data_size DMA_Memory_data_size +/** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ /** * @} */ -/** @defgroup DMA_mode DMA_mode +/** @defgroup DMA_mode DMA mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) +#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ /** * @} */ -/** @defgroup DMA_Priority_level DMA_Priority_level +/** @defgroup DMA_Priority_level DMA Priority level * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ /** * @} */ -/** @defgroup DMA_interrupt_enable_definitions DMA_interrupt_enable_definitions +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ - #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) - /** * @} */ -/** @defgroup DMA_flag_definitions DMA_flag_definitions +/** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ - #define DMA_FLAG_GL1 ((uint32_t)0x00000001) #define DMA_FLAG_TC1 ((uint32_t)0x00000002) #define DMA_FLAG_HT1 ((uint32_t)0x00000004) @@ -320,8 +277,6 @@ typedef struct __DMA_HandleTypeDef #define DMA_FLAG_TC7 ((uint32_t)0x02000000) #define DMA_FLAG_HT7 ((uint32_t)0x04000000) #define DMA_FLAG_TE7 ((uint32_t)0x08000000) - - /** * @} */ @@ -329,9 +284,10 @@ typedef struct __DMA_HandleTypeDef /** * @} */ + -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DMA_Exported_macros DMA Exported Macros +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ @@ -340,7 +296,7 @@ typedef struct __DMA_HandleTypeDef * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - + /** * @brief Enable the specified DMA Channel. * @param __HANDLE__: DMA handle @@ -373,7 +329,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -383,7 +339,7 @@ typedef struct __DMA_HandleTypeDef #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) /** - * @brief Checks whether the specified DMA Channel interrupt has occurred or not. + * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt source to check. * This parameter can be one of the following values: @@ -398,27 +354,40 @@ typedef struct __DMA_HandleTypeDef * @} */ - /* Include DMA HAL Extension module */ #include "stm32l1xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions +/** @addtogroup DMA_Exported_Functions DMA Exported Functions * @{ */ - +/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ /* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions + * @{ + */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); @@ -426,6 +395,65 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); * @} */ +/** + * @} + */ + +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma_ex.h index 7f8805332be..e76b100c4f2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_HAL_DMA_EX_H @@ -50,27 +50,25 @@ * @{ */ -/** @addtogroup DMAEx +/** @defgroup DMAEx DMAEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros +/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros * @{ */ - /* Interrupt & Flag management */ #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Returns the current DMA Channel transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified transfer complete flag index. */ - #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ @@ -134,7 +132,6 @@ * Where x can be 1_7 or 1_5 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ - #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ (DMA1->ISR & (__FLAG__))) @@ -224,16 +221,15 @@ */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L152xE || STM32L162xE */ - +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.c index 8b715b9ef26..e4a17f02240 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.c @@ -2,26 +2,25 @@ ****************************************************************************** * @file stm32l1xx_hal_flash.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: - * + FLASH Interface configuration - * + FLASH Memory Programming - * + Interrupts and flags management - * - * @verbatim - + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim ============================================================================== - ##### FLASH peripheral features ##### + ##### FLASH peripheral features ##### ============================================================================== - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. [..] The FLASH main features are: (+) Flash memory read operations @@ -29,46 +28,49 @@ (+) Read / write protections (+) Prefetch on I-Code (+) Option Bytes programming - - ##### How to use this driver ##### + + + ##### How to use this driver ##### ============================================================================== - [..] This driver provides functions to configure and program the Flash - memory of all STM32L1xx devices. - - (#) FLASH Memory Programming functions: this group includes all - needed functions to erase and program the main memory: - (++) Lock and Unlock the Flash interface. - (++) Erase function: Erase Page. - (++) Program functions: Fast Word and Half Page(should be + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32L1xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page + (++) Program functions: Fast Word and Half Page(should be executed from internal SRAM). - (#) DATA EEPROM Programming functions: this group includes all - needed functions to erase and program the DATA EEPROM memory: - (++) Lock and Unlock the DATA EEPROM interface. - (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase - Double Word (should be executed from internal SRAM). - (++) Program functions: Fast Program Byte, Fast Program Half-Word, - FastProgramWord, Program Byte, Program Half-Word, - Program Word and Program Double-Word (should be executed - from internal SRAM). + (#) DATA EEPROM Programming functions: this group includes all + needed functions to erase and program the DATA EEPROM memory: + (++) Lock and Unlock the DATA EEPROM interface. + (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase + Double Word (should be executed from internal SRAM). + (++) Program functions: Fast Program Byte, Fast Program Half-Word, + FastProgramWord, Program Byte, Program Half-Word, + Program Word and Program Double-Word (should be executed + from internal SRAM). - (#) FLASH Option Bytes Programming functions: this group includes - all needed functions to: - (++) Lock and Unlock the Flash Option bytes. - (++) Set/Reset the write protection. - (++) Set the Read protection Level. - (++) Set the BOR level. - (++) Program the user option Bytes. - (++) Launch the Option Bytes loader. - (++) Get the Write protection. - (++) Get the read protection status. - (++) Get the BOR level. - (++) Get the user option bytes. - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Wait for last FLASH operation according to its status - (++) Get error flag status by calling HAL_GetErrorCode() + + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Set/Get the Read protection Level. + (++) Set/Get the BOR level. + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status (#) FLASH Interface configuration functions: this group includes the management of following features: @@ -83,14 +85,13 @@ [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: - (+) Set/Get the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the 64 bit Read Access. - (+) Enable/Disable the Flash power-down - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - - =============================================================================== + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the 64 bit Read Access. + (+) Enable/Disable the Flash power-down + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + ##### Programming operation functions ##### =============================================================================== [..] @@ -110,7 +111,6 @@ (#) Call the HAL_FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). - ============================================================================== ##### Option Bytes Programming functions ##### ============================================================================== @@ -131,12 +131,17 @@ (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended to protect the option Bytes against possible unwanted operations). - * @endverbatim - * + [..] Proprietary code Read Out Protection (PcROP): + (#) The PcROP sector is selected by using the same option bytes as the Write + protection. As a result, these 2 options are exclusive each other. + (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below: + (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE. + + @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -160,8 +165,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" @@ -173,51 +178,71 @@ #ifdef HAL_FLASH_MODULE_ENABLED /** @defgroup FLASH FLASH - * @brief FLASH driver modules + * @brief FLASH HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Internal_Variables FLASH Internal Variables +/** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ - */ - + */ /** - * @brief Variable used for Program/Erase sectors under interruption + * @} */ -FLASH_ProcessTypeDef ProcFlash; +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; /** * @} - */ + */ + /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_SetErrorCode(void); +/** + * @} + */ -/** @defgroup FLASH_Exported_Functions FLASH Exported functions +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim + * @brief Programming operation functions + * +@verbatim @endverbatim * @{ */ + /** * @brief Program word at a specified address * @note To correctly run this function, the HAL_FLASH_Unlock() function * must be called before. * Call the HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation). + * * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -226,36 +251,40 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ - __HAL_LOCK(&ProcFlash); + __HAL_LOCK(&pFlash); /* Check the parameters */ - assert_param(IS_TYPEPROGRAMFLASH(TypeProgram)); + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /*Program word (32-bit) at a specified address.*/ *(__IO uint32_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + __HAL_UNLOCK(&pFlash); return status; } /** * @brief Program word at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -264,46 +293,153 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ - __HAL_LOCK(&ProcFlash); + __HAL_LOCK(&pFlash); /* Check the parameters */ - assert_param(IS_TYPEPROGRAMFLASH(TypeProgram)); + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); + pFlash.Address = Address; + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - ProcFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - ProcFlash.Address = Address; - - if(TypeProgram == TYPEPROGRAM_WORD) + if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { /*Program word (32-bit) at a specified address.*/ *(__IO uint32_t *)Address = Data; } + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0; - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + /* Check FLASH operation error flags */ + if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || +#if defined(FLASH_SR_RDERR) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || +#endif /* FLASH_SR_OPTVERRUSR */ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /*return the faulty sector*/ + addresstmp = pFlash.Page; + pFlash.Page = 0xFFFFFFFF; + } + else + { + /*return the faulty address*/ + addresstmp = pFlash.Address; + } + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase*/ + if(pFlash.NbPagesToErase != 0) + { + addresstmp = pFlash.Page; + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Page + FLASH_PAGE_SIZE; + pFlash.Page = addresstmp; + + /* If the erase operation is completed, disable the ERASE Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + FLASH_PageErase(addresstmp); + } + else + { + /*No more pages to Erase, user callback can be called.*/ + /*Reset Sector and stop Erase pages procedure*/ + pFlash.Page = addresstmp = 0xFFFFFFFF; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else + { + /* If the program operation is completed, disable the PROG Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + + /* Reset Address and stop Program procedure*/ + pFlash.Address = 0xFFFFFFFF; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } - return status; + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PROG and ERASE */ + CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } } + /** * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Pages Erase: Sector which has been erased - * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file */ @@ -312,12 +448,15 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Pagess Erase: Sector number which returned an error + * - Pages Erase: Address of the page which returned an error * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ @@ -325,7 +464,7 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) /** * @} - */ + */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions * @brief management functions @@ -340,113 +479,116 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) @endverbatim * @{ - */ + */ /** * @brief Unlock the FLASH control register access - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) +HAL_StatusTypeDef HAL_FLASH_Unlock(void) { - if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET) + if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) { /* Unlocking FLASH_PECR register access*/ - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) { - FLASH->PEKEYR = FLASH_PEKEY1; - FLASH->PEKEYR = FLASH_PEKEY2; + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); } /* Unlocking the program memory access */ - FLASH->PRGKEYR = FLASH_PRGKEY1; - FLASH->PRGKEYR = FLASH_PRGKEY2; + WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); + WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); } else { return HAL_ERROR; } - + return HAL_OK; } /** * @brief Locks the FLASH control register access - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { - /* Set the PRGLOCK Bit to lock the program memory access */ + /* Set the PRGLOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); - return HAL_OK; + + return HAL_OK; } + /** * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { - if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET) + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) { /* Unlocking FLASH_PECR register access*/ - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) { /* Unlocking FLASH_PECR register access*/ - FLASH->PEKEYR = FLASH_PEKEY1; - FLASH->PEKEYR = FLASH_PEKEY2; + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); } /* Unlocking the option bytes block access */ - FLASH->OPTKEYR = FLASH_OPTKEY1; - FLASH->OPTKEYR = FLASH_OPTKEY2; + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); } else { return HAL_ERROR; } - return HAL_OK; + return HAL_OK; } /** * @brief Lock the FLASH Option Control Registers access. - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Set the OPTLOCK Bit to lock the option bytes block access */ SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); - + return HAL_OK; } - + /** * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { - /* Set the OBL_Launch bit to lauch the option byte loading */ + /* Set the OBL_Launch bit to launch the option byte loading */ SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); } /** * @} - */ + */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions * @verbatim =============================================================================== - ##### Peripheral Errors functions ##### + ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permit to get in run-time Errors of the FLASH peripheral. + This subsection permit to get in run-time the status of the FLASH peripheral. @endverbatim * @{ @@ -455,18 +597,12 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) /** * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode: The returned value can be: - * @arg FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg FLASH_ERROR_SIZE: FLASH Size error flag - * @arg FLASH_ERROR_OPTV: Option validity error flag - * @arg FLASH_ERROR_OPTVUSR: Option UserValidity Error flag (available only Cat.3, Cat.4 and Cat.5 devices) - * @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) - */ -FLASH_ErrorTypeDef HAL_FLASH_GetError(void) + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) { - return ProcFlash.ErrorCode; + return pFlash.ErrorCode; } - /** * @} */ @@ -475,8 +611,102 @@ FLASH_ErrorTypeDef HAL_FLASH_GetError(void) * @} */ -#endif /* HAL_FLASH_MODULE_ENABLED */ +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout: maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || +#if defined(FLASH_SR_RDERR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || +#endif /* FLASH_SR_OPTVERRUSR */ + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is no error flag set */ + return HAL_OK; +} + + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); + } + +#if defined(FLASH_SR_RDERR) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); + } +#endif /* FLASH_SR_RDERR */ + +#if defined(FLASH_SR_OPTVERRUSR) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERRUSR); + } +#endif /* FLASH_SR_OPTVERRUSR */ + + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR); +} /** * @} */ @@ -485,6 +715,10 @@ FLASH_ErrorTypeDef HAL_FLASH_GetError(void) * @} */ +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.h index 0abe80573e6..9d240b56d96 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_flash.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention - * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + * + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,8 +32,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_HAL_FLASH_H @@ -45,44 +45,50 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" - + /** @addtogroup STM32L1xx_HAL_Driver * @{ */ /** @addtogroup FLASH * @{ - */ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ +/** + * @} + */ -/* Exported types ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(_VALUE_) (((_VALUE_) == FLASH_TYPEPROGRAM_WORD)) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) + +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ -/** - * @brief FLASH Error structure definition - */ -typedef enum -{ - FLASH_ERROR_SIZE = 0x01, - FLASH_ERROR_OPTV = 0x02, - FLASH_ERROR_OPTVUSR = 0x04, - FLASH_ERROR_PGA = 0x08, - FLASH_ERROR_WRP = 0x10, - FLASH_ERROR_RD = 0x20, - FLASH_ERROR_OPERATION = 0x40 -}FLASH_ErrorTypeDef; - /** * @brief FLASH Procedure structure definition */ typedef enum { - FLASH_PROC_NONE = 0, - FLASH_PROC_PAGEERASE, - FLASH_PROC_PROGRAM + FLASH_PROC_NONE = 0, + FLASH_PROC_PAGEERASE = 1, + FLASH_PROC_PROGRAM = 2, } FLASH_ProcedureTypeDef; /** @@ -90,70 +96,74 @@ typedef enum */ typedef struct { - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ - - __IO uint32_t NbPagesToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ - - __IO uint32_t Page; /*Internal variable to define the current sector which is erasing*/ - - __IO uint32_t Address; /*Internal variable to save address selected for program*/ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ - HAL_LockTypeDef Lock; /* FLASH locking object */ + __IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/ - __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */ + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ -}FLASH_ProcessTypeDef; + __IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; /** * @} - */ + */ -/** @addtogroup FLASH_Internal_Variables +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ */ -/** - * @brief Variable used for Program/Erase sectors under interruption. - * Put as extern as used also in flash_ex.c. +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ */ -extern FLASH_ProcessTypeDef ProcFlash; + +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_FLASH_ERROR_PGA ((uint32_t)0x01) /*!< Programming alignment error */ +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x04) /*!< Option validity error */ +#define HAL_FLASH_ERROR_SIZE ((uint32_t)0x08) /*!< */ +#define HAL_FLASH_ERROR_OPTVUSR ((uint32_t)0x10) /*!< Option UserValidity Error. */ +#define HAL_FLASH_ERROR_RD ((uint32_t)0x20) /*!< Read protected error */ +#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x40) /*!< Not used */ /** * @} - */ - -/* Exported constants --------------------------------------------------------*/ + */ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants +/** @defgroup FLASH_Page_Size FLASH Page Size * @{ - */ - -#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000) /* 50 s */ + */ #define FLASH_PAGE_SIZE ((uint32_t)256) - + +/** + * @} + */ + /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */ - -#define IS_TYPEPROGRAMFLASH(_VALUE_) (((_VALUE_) == TYPEPROGRAM_WORD)) +#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!PECR) |= (__INTERRUPT__)) +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) ((FLASH->PECR) &= ~(uint32_t)(__INTERRUPT__)) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__)) /** * @brief Get the specified FLASH flag status. - * @param __FLAG__: specifies the FLASH flag to check. + * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY : FLASH Busy flag - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_ENDHV : FLASH End of High Voltage flag - * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error error flag - * @arg FLASH_FLAG_OPTVERRUSR : FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) - * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag + * @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @retval The new state of __FLAG__ (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) /** * @brief Clear the specified FLASH flag. - * @param __FLAG__: specifies the FLASH flags to clear. + * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_BSY : FLASH Busy flag - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_ENDHV : FLASH End of High Voltage flag - * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error error flag - * @arg FLASH_FLAG_OPTVERRUSR : FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) - * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag + * @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) @@ -291,86 +295,74 @@ extern FLASH_ProcessTypeDef ProcFlash; * @} */ -/* Include FLASH HAL Extension module */ -#include "stm32l1xx_hal_flash_ex.h" -#include "stm32l1xx_hal_flash_ramfunc.h" - -/* Exported functions ------------------------------------------------------- */ +/* Include FLASH HAL Extended module */ +#include "stm32l1xx_hal_flash_ex.h" +#include "stm32l1xx_hal_flash_ramfunc.h" +/* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ - + /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ - -/** - * @brief FLASH memory functions that can be executed from FLASH. - */ -/* Program operation functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler function */ -void HAL_FLASH_IRQHandler(void); +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); - /** * @} - */ + */ /** @addtogroup FLASH_Exported_Functions_Group2 * @{ */ - -/* FLASH Memory Programming functions *****************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); - -/* Option Bytes Programming functions *****************************************/ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); /** * @} - */ + */ /** @addtogroup FLASH_Exported_Functions_Group3 * @{ */ - -/* Peripheral State methods **************************************************/ -FLASH_ErrorTypeDef HAL_FLASH_GetError(void); +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); /** * @} - */ + */ /** * @} - */ - -/** @addtogroup FLASH_Internal_Functions - * @{ */ -/** - * @brief Function used internally by HAL FLASH driver. - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +void FLASH_PageErase(uint32_t PageAddress); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} - */ + */ /** * @} - */ + */ /** * @} @@ -382,4 +374,5 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #endif /* __STM32L1xx_HAL_FLASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.c index 1d0b56b1bc1..6edd3065180 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.c @@ -2,9 +2,10 @@ ****************************************************************************** * @file stm32l1xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief FLASH HAL module driver. + * @version V1.1.3 + * @date 04-March-2016 + * @brief Extended FLASH HAL module driver. + * * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + FLASH Interface configuration @@ -13,7 +14,7 @@ * + Option Bytes Programming * + Interrupts management * - * @verbatim + @verbatim ============================================================================== ##### Flash peripheral Extended features ##### ============================================================================== @@ -28,7 +29,7 @@ ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the FLASH memory - of all STM32L1xx. It includes: + of all STM32L1xx. It includes: (+) Full DATA_EEPROM erase and program management (+) Boot activation (+) PCROP protection configuration and control for all pages @@ -37,7 +38,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -70,48 +71,81 @@ /** @addtogroup STM32L1xx_HAL_Driver * @{ */ +#ifdef HAL_FLASH_MODULE_ENABLED +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + /** @defgroup FLASHEx FLASHEx * @brief FLASH HAL Extension module driver * @{ */ -#ifdef HAL_FLASH_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void FLASH_SetErrorCode(void); -static void FLASH_ErasePage(uint32_t PageAddress); - +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState); static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState); -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState); -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState); #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState); -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xE || STM32L152xE || STM32L151xDX || ... */ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR); static uint8_t FLASH_OB_GetRDP(void); static uint8_t FLASH_OB_GetUser(void); static uint8_t FLASH_OB_GetBOR(void); -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState); #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT); #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ @@ -121,14 +155,16 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uin static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data); static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data); +/** + * @} + */ /* Exported functions ---------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported functions +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ -/** @defgroup FLASHEx_Exported_Functions_Group1 FLASH Memory Erasing functions +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions * @brief FLASH Memory Erasing functions * @verbatim @@ -137,15 +173,15 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t ============================================================================== [..] The FLASH Memory Erasing functions, includes the following functions: - (+) HAL_FLASHEx_Erase: return only when erase has been done - (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback is called with parameter - 0xFFFFFFFF + (+) @ref HAL_FLASHEx_Erase: return only when erase has been done + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF [..] Any operation of erase should follow these steps: - (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and program memory access. (#) Call the desired function to erase page. - (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). @endverbatim @@ -154,29 +190,31 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t /** * @brief Erase the specified FLASH memory Pages - * @note To correctly run this function, the HAL_FLASH_Unlock() function + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between + * 2 banks, user should perform pages erase by bank only. + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * - * @param[out] PageError: pointer to variable that - * contains the configuration information on faulty sector in case of error - * (0xFFFFFFFF means that all the sectors have been correctly erased) + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index = 0; + uint32_t address = 0; /* Process Locked */ - __HAL_LOCK(&ProcFlash); + __HAL_LOCK(&pFlash); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { @@ -185,17 +223,49 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Check the parameters */ assert_param(IS_NBPAGES(pEraseInit->NbPages)); - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + +#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX) + /* Check on which bank belongs the 1st address to erase */ + if (pEraseInit->PageAddress < FLASH_BANK2_BASE) + { + /* BANK1 */ + /* Check that last page to erase still belongs to BANK1 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK1_END) + { + /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } + else + { + /* BANK2 */ + /* Check that last page to erase still belongs to BANK2 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK2_END) + { + /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } +#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */ - /* Erase by sector by sector to be done*/ - for(index = pEraseInit->PageAddress; index < ((pEraseInit->NbPages * FLASH_PAGE_SIZE)+ pEraseInit->PageAddress); index += FLASH_PAGE_SIZE) + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) { - FLASH_ErasePage(index); + FLASH_PageErase(address); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the ERASE Bit */ CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); @@ -203,26 +273,28 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t if (status != HAL_OK) { - /* In case of error, stop erase procedure and return the faulty sector*/ - *PageError = index; + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; break; } } } /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + __HAL_UNLOCK(&pFlash); return status; } /** * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled - * @note To correctly run this function, the HAL_FLASH_Unlock() function + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between + * 2 banks, user should perform pages erase by bank only. + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL_StatusTypeDef HAL Status @@ -231,30 +303,60 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { HAL_StatusTypeDef status = HAL_OK; - /* Process Locked */ - __HAL_LOCK(&ProcFlash); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_NBPAGES(pEraseInit->NbPages)); - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + +#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX) + /* Check on which bank belongs the 1st address to erase */ + if (pEraseInit->PageAddress < FLASH_BANK2_BASE) + { + /* BANK1 */ + /* Check that last page to erase still belongs to BANK1 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK1_END) + { + /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } + else + { + /* BANK2 */ + /* Check that last page to erase still belongs to BANK2 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK2_END) + { + /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } +#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */ - ProcFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; - ProcFlash.NbPagesToErase = pEraseInit->NbPages; - ProcFlash.Page = pEraseInit->PageAddress; + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->PageAddress; /*Erase 1st page and wait for IT*/ - FLASH_ErasePage(pEraseInit->PageAddress); + FLASH_PageErase(pEraseInit->PageAddress); return status; } @@ -263,9 +365,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) * @} */ - /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions - * @brief Option Bytes Programming functions + * @brief Option Bytes Programming functions * @verbatim ============================================================================== @@ -273,20 +374,20 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) ============================================================================== [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control + (#) Call the @ref HAL_FLASH_OB_Unlock() function to enable the Flash option control register access. (#) Call following function to program the desired option bytes. - (++) HAL_FLASHEx_OBProgram: + (++) @ref HAL_FLASHEx_OBProgram: - To Enable/Disable the desired sector write protection. - To set the desired read Protection Level. - To configure the user option Bytes: IWDG, STOP and the Standby. - To Set the BOR level. (#) Once all needed option bytes to be programmed are correctly written, call the - HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. - (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended + @ref HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + (#) Call the @ref HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended to protect the option Bytes against possible unwanted operations). - [..] Proprietary code Read Out Protection (PcROP): + [..] Proprietary code Read Out Protection (PcROP): (#) The PcROP sector is selected by using the same option bytes as the Write protection (nWRPi bits). As a result, these 2 options are exclusive each other. (#) In order to activate the PcROP (change the function of the nWRPi option bits), @@ -295,8 +396,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" is read/write protected. (#) To activate PCROP mode for Flash sector(s), you need to call the following function: - (++) HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected - (++) HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection + (++) @ref HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected + (++) @ref HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices. @endverbatim @@ -305,7 +406,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL_StatusTypeDef HAL Status @@ -315,7 +416,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ - __HAL_LOCK(&ProcFlash); + __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); @@ -324,7 +425,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) { assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == WRPSTATE_ENABLE) + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) { /* Enable of Write protection on the selected Sector*/ status = FLASH_OB_WRPConfig(pOBInit, ENABLE); @@ -337,7 +438,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) if (status != HAL_OK) { /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + __HAL_UNLOCK(&pFlash); return status; } } @@ -349,7 +450,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) if (status != HAL_OK) { /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + __HAL_UNLOCK(&pFlash); return status; } } @@ -363,7 +464,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) if (status != HAL_OK) { /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + __HAL_UNLOCK(&pFlash); return status; } } @@ -372,16 +473,22 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) { status = FLASH_OB_BORConfig(pOBInit->BORLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } } /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + __HAL_UNLOCK(&pFlash); return status; } /** * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None @@ -393,29 +500,32 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /*Get WRP1*/ pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1); -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) /*Get WRP2*/ pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2); -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) /*Get WRP3*/ pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3); #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) /*Get WRP4*/ pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4); -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ /*Get RDP Level*/ pOBInit->RDPLevel = FLASH_OB_GetRDP(); @@ -428,15 +538,15 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) } -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) \ + || defined(STM32L152xDX) || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) \ + || defined(STM32L152xE) || defined(STM32L162xE) /** * @brief Program option bytes * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval HAL_StatusTypeDef HAL Status @@ -448,16 +558,16 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO /* Check the parameters */ assert_param(IS_OBEX(pAdvOBInit->OptionType)); -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) /* Cat2 & Cat3 devices only */ /*Program PCROP option byte*/ - if ((pAdvOBInit->OptionType & OBEX_PCROP) == OBEX_PCROP) + if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) { /* Check the parameters */ assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); - if (pAdvOBInit->PCROPState == PCROPSTATE_ENABLE) + if (pAdvOBInit->PCROPState == OB_PCROP_STATE_ENABLE) { /*Enable of Write protection on the selected Sector*/ status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE); @@ -479,12 +589,13 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) /* Cat4 & Cat5 devices only */ /*Program BOOT config option byte*/ - if ((pAdvOBInit->OptionType & OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG) + if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) { status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); } @@ -497,17 +608,17 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO /** * @brief Get the OBEX byte configuration * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval None */ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) { -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) - pAdvOBInit->OptionType = OBEX_PCROP; + pAdvOBInit->OptionType = OPTIONBYTE_PCROP; /*Get PCROP state */ pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD); @@ -515,7 +626,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) /*Get PCROP protected sector from 0 to 31 */ pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1; - #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) /*Get PCROP protected sector from 32 to 63 */ pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2; @@ -524,10 +635,11 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) - pAdvOBInit->OptionType = OBEX_BOOTCONFIG; + pAdvOBInit->OptionType = OPTIONBYTE_BOOTCONFIG; /*Get Boot config OB*/ pAdvOBInit->BootConfig = (FLASH->OBR & 0x80000000) >> 24; @@ -535,10 +647,10 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ } -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) /** * @brief Select the Protection Mode (SPRMOD). @@ -555,7 +667,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) uint8_t optiontmp = 0; uint16_t optiontmp2 = 0; - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Mask RDP Byte */ optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); @@ -569,12 +681,15 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) if(status == HAL_OK) { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* program PCRop */ OB->RDP = tmp2; } /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Return the Read protection operation Status */ return status; @@ -595,7 +710,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) uint8_t optiontmp = 0; uint16_t optiontmp2 = 0; - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Mask RDP Byte */ optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); @@ -609,12 +724,15 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) if(status == HAL_OK) { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* program PCRop */ OB->RDP = tmp2; } /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Return the Read protection operation Status */ return status; @@ -635,10 +753,10 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) =============================================================================== [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access + (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access and Flash program erase control register access. (#) Call the desired function to erase or program data. - (#) Call the HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access + (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access and Flash program erase control register access(recommended to protect the DATA_EEPROM against possible unwanted operation). @@ -679,16 +797,15 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) /** * @brief Erase a word in data memory. - * @param Address: specifies the address to be erased. - * @param TypeErase: Indicate the way to erase at a specified address. + * @param Address specifies the address to be erased. + * @param TypeErase Indicate the way to erase at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @note To correctly run this function, the DATA_EEPROM_Unlock() function * must be called before. * Call the DATA_EEPROM_Lock() to the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address) { @@ -699,23 +816,26 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Addr assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - if(TypeErase == TYPEERASEDATA_WORD) + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + if(TypeErase == FLASH_TYPEERASEDATA_WORD) { /* Write 00000000h to valid address in the data memory */ *(__IO uint32_t *) Address = 0x00000000; } - if(TypeErase == TYPEERASEDATA_HALFWORD) + if(TypeErase == FLASH_TYPEERASEDATA_HALFWORD) { /* Write 0000h to valid address in the data memory */ *(__IO uint16_t *) Address = (uint16_t)0x0000; } - if(TypeErase == TYPEERASEDATA_BYTE) + if(TypeErase == FLASH_TYPEERASEDATA_BYTE) { /* Write 00h to valid address in the data memory */ *(__IO uint8_t *) Address = (uint8_t)0x00; @@ -735,10 +855,10 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Addr * the DATA_EEPROM against possible unwanted operation). * @note The function HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before * this function to configure the Fixed Time Programming. - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASHEx_Type_Program_Data - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -748,58 +868,58 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_ HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ - __HAL_LOCK(&ProcFlash); + __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_TYPEPROGRAMDATA(TypeProgram)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - if(TypeProgram == TYPEPROGRAMDATA_FASTBYTE) + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE) { /*Program word (8-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data); + status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data); } - if(TypeProgram == TYPEPROGRAMDATA_FASTHALFWORD) + if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) { /*Program word (16-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data); + status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data); } - if(TypeProgram == TYPEPROGRAMDATA_FASTWORD) + if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD) { /*Program word (32-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data); + status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data); } - if(TypeProgram == TYPEPROGRAMDATA_WORD) + if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD) { /*Program word (32-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data); + status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data); } - if(TypeProgram == TYPEPROGRAMDATA_HALFWORD) + if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD) { /*Program word (16-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data); + status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data); } - if(TypeProgram == TYPEPROGRAMDATA_BYTE) + if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE) { /*Program word (8-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data); + status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data); } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); } /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); + __HAL_UNLOCK(&pFlash); return status; } @@ -830,85 +950,9 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) * @} */ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private functions - * @{ - */ - -/* -============================================================================== - ##### FLASH STATIC functions ##### -============================================================================== -*/ - -/* -============================================================================== - FLASH -============================================================================== -*/ - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) - { - ProcFlash.ErrorCode = FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_SIZE; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_OPTV; - } - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_RD; - } -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_OPTVUSR; - } -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -} - -/** - * @brief Erases a specified page in program memory. - * @param PageAddress: The page address in program memory to be erased. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 256 bytes). - * @retval None - */ -static void FLASH_ErasePage(uint32_t PageAddress) -{ - /* Set the ERASE bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - /* Set PROG bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* Write 00000000h to the first word of the program page to erase */ - *(__IO uint32_t *)PageAddress = 0x00000000; -} - +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ /* ============================================================================== @@ -919,13 +963,13 @@ static void FLASH_ErasePage(uint32_t PageAddress) * @brief Enables or disables the read out protection. * @note To correctly run this function, the HAL_FLASH_OB_Unlock() function * must be called before. - * @param OB_RDP: specifies the read protection level. + * @param OB_RDP specifies the read protection level. * This parameter can be: - * @arg OB_RDP_LEVEL0: No protection - * @arg OB_RDP_LEVEL1: Read protection of the memory - * @arg OB_RDP_LEVEL2: Chip protection + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Chip protection * - * !!!Warning!!! When enabling OB_RDP_LEVEL2 it's no more possible to go back to level 1 or 0 + * !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0 * * @retval HAL status */ @@ -943,17 +987,20 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) If the current level is Level0 then the RDP register must not be written again with Level0. */ tmp1 = (uint32_t)(OB->RDP & 0x000000FF); - if ((tmp1 == OB_RDP_LEVEL0) && (OB_RDP == OB_RDP_LEVEL0)) + if ((tmp1 == OB_RDP_LEVEL_0) && (OB_RDP == OB_RDP_LEVEL_0)) { /*current level is Level0 then the RDP register must not be written again with Level0. */ status = HAL_ERROR; } else { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Mask SPRMOD bit */ sprmod = (uint32_t)(OB->RDP & 0x00000100); - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* calculate the option byte to write */ tmp1 = (~((uint32_t)(OB_RDP | sprmod))); @@ -966,7 +1013,7 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) } /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } /* Return the Read protection operation Status */ @@ -975,15 +1022,15 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) /** * @brief Programs the FLASH brownout reset threshold level Option Byte. - * @param OB_BOR: Selects the brownout reset threshold level. + * @param OB_BOR Selects the brownout reset threshold level. * This parameter can be one of the following values: - * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD + * @arg @ref OB_BOR_OFF BOR is disabled at power down, the reset is asserted when the VDD * power supply reaches the PDR(Power Down Reset) threshold (1.5V) - * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply - * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply - * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply - * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply - * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply + * @arg @ref OB_BOR_LEVEL1 BOR Reset threshold levels for 1.7V - 1.8V VDD power supply + * @arg @ref OB_BOR_LEVEL2 BOR Reset threshold levels for 1.9V - 2.0V VDD power supply + * @arg @ref OB_BOR_LEVEL3 BOR Reset threshold levels for 2.3V - 2.4V VDD power supply + * @arg @ref OB_BOR_LEVEL4 BOR Reset threshold levels for 2.55V - 2.65V VDD power supply + * @arg @ref OB_BOR_LEVEL5 BOR Reset threshold levels for 2.8V - 2.9V VDD power supply * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) @@ -1002,16 +1049,19 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) tmp |= (OB_BOR | tmp1); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Write the BOR Option Byte */ OB->USER = tmp; } /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Return the Option Byte program Status */ return status; @@ -1029,7 +1079,11 @@ static uint8_t FLASH_OB_GetUser(void) /** * @brief Checks whether the FLASH Read out Protection Status is set or not. - * @retval FLASH ReadOut Protection + * @retval FLASH ReadOut Protection Status: + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection */ static uint8_t FLASH_OB_GetRDP(void) { @@ -1048,9 +1102,9 @@ static uint8_t FLASH_OB_GetBOR(void) /** * @brief Write protects the desired pages of the first 64KB of the Flash. - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains WRP parameters. - * @param NewState: new state of the specified FLASH Pages Wtite protection. + * @param NewState new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval HAL_StatusTypeDef */ @@ -1059,19 +1113,23 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, HAL_StatusTypeDef status = HAL_OK; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* WRP for sector between 0 to 31 */ if (pOBInit->WRPSector0To31 != 0) { FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState); } -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) /* Pages for Cat3, Cat4 & Cat5 devices*/ /* WRP for sector between 32 to 63 */ @@ -1080,10 +1138,11 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState); } -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) /* Pages for devices with FLASH >= 256KB*/ /* WRP for sector between 64 to 95 */ @@ -1094,7 +1153,8 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) /* Pages for Cat5 devices*/ /* WRP for sector between 96 to 127 */ @@ -1103,25 +1163,25 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState); } -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } /* Return the write protection operation Status */ return status; } -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) /** * @brief Enables the read/write protection (PCROP) of the desired * sectors. * @note This function can be used only for Cat2 & Cat3 devices - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains PCROP parameters. - * @param NewState: new state of the specified FLASH Pages read/Write protection. + * @param NewState new state of the specified FLASH Pages read/Write protection. * This parameter can be: ENABLE or DISABLE. * @retval HAL status */ @@ -1131,7 +1191,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd FunctionalState pcropstate = DISABLE; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Invert state to use same function of WRP */ if (NewState == DISABLE) @@ -1141,6 +1201,9 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd if(status == HAL_OK) { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Pages for Cat2 devices*/ /* PCROP for sector between 0 to 31 */ if (pAdvOBInit->PCROPSector0To31 != 0) @@ -1148,7 +1211,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate); } -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) /* Pages for Cat3 devices*/ /* WRP for sector between 32 to 63 */ @@ -1160,7 +1223,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } /* Return the write protection operation Status */ @@ -1170,11 +1233,9 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd /** * @brief Write protects the desired pages of the first 128KB of the Flash. - * @param WRP1OrPCROP1: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP1/PCROP1_PAGES0TO15 and OB_WRP1/PCROP1_PAGES496TO511 - * @arg OB_WRP1/PCROP1_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. + * @param WRP1OrPCROP1 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 + * @param NewState new state of the specified FLASH Pages Write protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -1207,17 +1268,16 @@ static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalStat } } -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) /** * @brief Enable Write protects the desired pages of the second 128KB of the Flash. * @note This function can be used only for Cat3, Cat4 & Cat5 devices. - * @param WRP2OrPCROP2: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP2/PCROP2_PAGES512TO527 and OB_WRP2/PCROP2_PAGES1008TO1023 - * @arg OB_WRP2/PCROP2_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. + * @param WRP2OrPCROP2 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 + * @param NewState new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -1249,18 +1309,17 @@ static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalStat OB->WRP67 = tmp2; } } -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) /** * @brief Enable Write protects the desired pages of the third 128KB of the Flash. * @note This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD & Cat5 devices. - * @param WRP3: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between WRP3_PAGES1024TO1039 and OB_WRP3_PAGES1520TO1535 - * @arg OB_WRP3_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. + * @param WRP3 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 + * @param NewState new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -1294,15 +1353,14 @@ static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState) } #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) /** * @brief Enable Write protects the desired pages of the Fourth 128KB of the Flash. - * @note This function can be used only for Cat5 devices. - * @param WRP4: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP4_PAGES1536TO1551 and OB_WRP4_PAGES2032TO2047 - * @arg OB_WRP4_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. + * @note This function can be used only for Cat5 & STM32L1xxDX devices. + * @param WRP4 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 + * @param NewState new state of the specified FLASH Pages Wtite protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ @@ -1334,22 +1392,22 @@ static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState) OB->WRP1415 = tmp2; } } -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ /** * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the WDG mode. + * @param OB_IWDG Selects the WDG mode. * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software WDG selected - * @arg OB_IWDG_HW: Hardware WDG selected - * @param OB_STOP: Reset event when entering STOP mode. + * @arg @ref OB_IWDG_SW Software WDG selected + * @arg @ref OB_IWDG_HW Hardware WDG selected + * @param OB_STOP Reset event when entering STOP mode. * This parameter can be one of the following values: - * @arg OB_STOP_NORST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. + * @arg @ref OB_STOP_NORST No reset generated when entering in STOP + * @arg @ref OB_STOP_RST Reset generated when entering in STOP + * @param OB_STDBY Reset event when entering Standby mode. * This parameter can be one of the following values: - * @arg OB_STDBY_NORST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @arg @ref OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg @ref OB_STDBY_RST Reset generated when entering in STANDBY * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) @@ -1370,35 +1428,39 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - /* Write the User Option Byte */ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write the User Option Byte */ OB->USER = tmp; } /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Return the Option Byte program Status */ return status; } -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) /** * @brief Configures to boot from Bank1 or Bank2. - * @param OB_BOOT: select the FLASH Bank to boot from. + * @param OB_BOOT select the FLASH Bank to boot from. * This parameter can be one of the following values: - * @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash + * @arg @ref OB_BOOT_BANK2 At startup, if boot pins are set in boot from user Flash * position and this parameter is selected the device will boot from Bank2 or Bank1, * depending on the activation of the bank. The active banks are checked in * the following order: Bank2, followed by Bank1. * The active bank is recognized by the value programmed at the base address * of the respective bank (corresponding to the initial stack pointer value * in the interrupt vector table). - * @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash + * @arg @ref OB_BOOT_BANK1 At startup, if boot pins are set in boot from user Flash * position and this parameter is selected the device will boot from Bank1(Default). * For more information, please refer to AN2606 from www.st.com. * @retval HAL status @@ -1419,16 +1481,19 @@ static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT) tmp |= (OB_BOOT | tmp1); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - /* Write the BOOT Option Byte */ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write the BOOT Option Byte */ OB->USER = tmp; } /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* Return the Option Byte program Status */ return status; @@ -1444,15 +1509,15 @@ static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT) /** * @brief Write a Byte at a specified address in data memory. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. * @note This function assumes that the is data word is already erased. * @retval HAL status */ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) uint32_t tmp = 0, tmpaddr = 0; #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ @@ -1460,14 +1525,14 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clear the FTDW bit */ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) /* Possible only on Cat1 devices */ if(Data != (uint8_t)0x00) { @@ -1475,7 +1540,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } else { @@ -1483,15 +1548,19 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); - } + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + /* Process Locked */ + __HAL_LOCK(&pFlash); + } #else /*!Cat1*/ /* If the previous operation is completed, proceed to write the new Data */ *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ } /* Return the Write Status */ @@ -1500,15 +1569,15 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint /** * @brief Writes a half word at a specified address in data memory. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. * @note This function assumes that the is data word is already erased. * @retval HAL status */ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) { HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) uint32_t tmp = 0, tmpaddr = 0; #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ @@ -1516,14 +1585,14 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clear the FTDW bit */ CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) /* Possible only on Cat1 devices */ if(Data != (uint16_t)0x0000) { @@ -1531,31 +1600,35 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } else { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); if((Address & 0x3) != 0x3) { tmpaddr = Address & 0xFFFFFFFC; tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); } else { - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); } + /* Process Locked */ + __HAL_LOCK(&pFlash); } #else /* !Cat1 */ /* If the previous operation is completed, proceed to write the new data */ *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ } /* Return the Write Status */ @@ -1564,8 +1637,8 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, /** * @brief Programs a word at a specified address in data memory. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. * @note This function assumes that the is data word is already erased. * @retval HAL status */ @@ -1577,7 +1650,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { @@ -1588,7 +1661,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint *(__IO uint32_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } /* Return the Write Status */ return status; @@ -1596,14 +1669,14 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint /** * @brief Write a Byte at a specified address in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. * @retval HAL status */ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) uint32_t tmp = 0, tmpaddr = 0; #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ @@ -1611,17 +1684,17 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) if(Data != (uint8_t) 0x00) { *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } else @@ -1630,14 +1703,18 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + /* Process Locked */ + __HAL_LOCK(&pFlash); } #else /* Not Cat1*/ *(__IO uint8_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ } /* Return the Write Status */ @@ -1646,14 +1723,14 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t /** * @brief Writes a half word at a specified address in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. * @retval HAL status */ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) { HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) uint32_t tmp = 0, tmpaddr = 0; #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ @@ -1661,40 +1738,44 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) if(Data != (uint16_t)0x0000) { *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } else { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); if((Address & 0x3) != 0x3) { tmpaddr = Address & 0xFFFFFFFC; tmp = * (__IO uint32_t *) tmpaddr; tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); } else { - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); } + /* Process Locked */ + __HAL_LOCK(&pFlash); } #else /* Not Cat1*/ *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); #endif /* STM32L100xB || STM32L151xB || STM32L152xB */ } /* Return the Write Status */ @@ -1703,8 +1784,8 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint /** * @brief Programs a word at a specified address in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. * @retval HAL status */ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data) @@ -1715,14 +1796,14 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { *(__IO uint32_t *)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } /* Return the Write Status */ return status; @@ -1737,216 +1818,47 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t */ /** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions * @{ */ -/** @addtogroup FLASH_Exported_Functions_Group1 - * @brief Interrupts functions - * -@verbatim - ============================================================================== - ##### Interrupts functions ##### - ============================================================================== -@endverbatim - * @{ - */ +/** @addtogroup FLASH_Private_Functions + * @{ + */ /** - * @brief This function handles FLASH interrupt request. + * @brief Erases a specified page in program memory. + * @param PageAddress The page address in program memory to be erased. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of 256 bytes). * @retval None */ -void HAL_FLASH_IRQHandler(void) +void FLASH_PageErase(uint32_t PageAddress) { - uint32_t temp; - - /* If the program operation is completed, disable the PROG Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* If the erase operation is completed, disable the ERASE Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - { - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /*Nb of sector to erased can be decreased*/ - ProcFlash.NbPagesToErase--; + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - /* Check if there are still sectors to erase*/ - if(ProcFlash.NbPagesToErase != 0) - { - temp = ProcFlash.Page; - /*Indicate user which sector has been erased*/ - HAL_FLASH_EndOfOperationCallback(temp); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); - - /*Increment sector number*/ - temp = ProcFlash.Page + FLASH_PAGE_SIZE; - ProcFlash.Page = ProcFlash.Page + FLASH_PAGE_SIZE; - FLASH_ErasePage(temp); - } - else - { - /*No more sectors to Erase, user callback can be called.*/ - /*Reset Sector and stop Erase sectors procedure*/ - ProcFlash.Page = temp = 0xFFFFFFFF; - ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(temp); - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - } - else - { - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(ProcFlash.Address); - } - ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - } - - /* Check FLASH operation error flags */ - if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) - { - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /*return the faulty sector*/ - temp = ProcFlash.Page; - ProcFlash.Page = 0xFFFFFFFF; - } - else - { - /*retrun the faulty address*/ - temp = ProcFlash.Address; - } - - /*Save the Error code*/ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(temp); - - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); - - /*Stop the procedure ongoing*/ - ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Disable End of FLASH Operation interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + /* Set the ERASE bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); - /* Disable Error source interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + /* Set PROG bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - } - + /* Write 00000000h to the first word of the program page to erase */ + *(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000; } - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Internal_Functions FLASH Internal function - * @{ - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operationtimeout - * @retval HAL status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* There is no error flag set */ - return HAL_OK; -} - - /** * @} */ -#endif /* HAL_FLASH_MODULE_ENABLED */ - /** * @} */ +#endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h index 80f233cf5b6..55ebef9b587 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_flash.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,9 +54,176 @@ * @{ */ +/** @addtogroup FLASHEx_Private_Defines + * @{ + */ +#if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR) + +#elif defined(FLASH_SR_RDERR) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_RDERR) + +#elif defined(FLASH_SR_OPTVERRUSR) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERRUSR) + +#else + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR) + +#endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */ + +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ + || defined(STM32L151xBA) || defined(STM32L152xBA) + +/******* Devices with FLASH 128K *******/ +#define FLASH_NBPAGES_MAX 512 /* 512 pages from page 0 to page 511 */ + +#elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA) + +/******* Devices with FLASH 256K *******/ +#define FLASH_NBPAGES_MAX 1025 /* 1025 pages from page 0 to page 1024 */ + +#elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) + +/******* Devices with FLASH 384K *******/ +#define FLASH_NBPAGES_MAX 1536 /* 1536 pages from page 0 to page 1535 */ + +#elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + +/******* Devices with FLASH 512K *******/ +#define FLASH_NBPAGES_MAX 2048 /* 2048 pages from page 0 to page 2047 */ + +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ + +/** @defgroup FLASHEx_Option_Bytes_Write_Mask FLASHEx Option Bytes Write Mask + * @{ + */ +#define WRP_MASK_LOW ((uint32_t)0x0000FFFF) +#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000) + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES)) + +#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR))) + +#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ + ((__VALUE__) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_2)) + +#define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \ + ((__LEVEL__) == OB_BOR_LEVEL1) || \ + ((__LEVEL__) == OB_BOR_LEVEL2) || \ + ((__LEVEL__) == OB_BOR_LEVEL3) || \ + ((__LEVEL__) == OB_BOR_LEVEL4) || \ + ((__LEVEL__) == OB_BOR_LEVEL5)) + +#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) + +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) + +#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP) + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) + +#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) + +#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \ + ((__VALUE__) == OB_PCROP_STATE_ENABLE)) + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +#define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \ + ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \ + ((__VALUE__) == FLASH_TYPEERASEDATA_WORD)) + +#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD)) + + +/** @defgroup FLASHEx_Address FLASHEx Address + * @{ + */ + +#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END)) + +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ + || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \ + || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \ + || defined(STM32L162xCA) + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) + +#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) +#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) +#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) + +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */ + +#define IS_NBPAGES(_PAGES_) (((_PAGES_) >= 1) && ((_PAGES_) <= FLASH_NBPAGES_MAX)) + +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) + +#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** + * @} + */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types +/** @defgroup FLASHEx_Exported_Types Exported Types * @{ */ @@ -66,13 +233,13 @@ typedef struct { uint32_t TypeErase; /*!< TypeErase: Page Erase only. - This parameter can be a value of @ref FLASHEx_Type_Erase */ + This parameter can be a value of @ref FLASHEx_Type_Erase */ - uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased - This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ + uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased + This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ - uint32_t NbPages; /*!< NbPages: Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ + uint32_t NbPages; /*!< NbPages: Number of pages to be erased. + This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ } FLASH_EraseInitTypeDef; @@ -81,41 +248,46 @@ typedef struct */ typedef struct { - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASHEx_Option_Type */ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_WRP_State */ + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ - uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ + uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) + uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) + uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or + Sectors 96 to 111 for STM32L1xxxDX devices. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ - uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. - This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ + uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, + @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ } FLASH_OBProgramInitTypeDef; /** @@ -123,28 +295,29 @@ typedef struct */ typedef struct { - uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . - This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ + uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . + This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. - This parameter can be a value of @ref FLASHEx_PCROP_State */ +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) + uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ - uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */ + uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) + uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ #endif /* STM32L151xC || STM32L152xC || STM32L162xC */ #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config - This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L151xE || STM32L152xE || STM32L162xE*/ } FLASH_AdvOBProgramInitTypeDef; /** @@ -154,16 +327,15 @@ typedef struct /* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants +/** @defgroup FLASHEx_Exported_Constants Exported Constants * @{ */ /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase * @{ */ -#define TYPEERASE_PAGES ((uint32_t)0x00) /*!= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END)) - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || \ - defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined (STM32L151xCA) || defined (STM32L152xCA) || defined (STM32L162xCA) - -#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) - -#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) -#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) -#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) - -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L152xCA || STM32L162xCA */ - -#define IS_NBPAGES(_PAGES_) (((_PAGES_) >= 1) && ((_PAGES_) <= FLASH_NBPAGES_MAX)) - -/** - * @} - */ - /** @defgroup FLASHEx_Flags FLASHEx Flags * @{ */ /* Cat2 & Cat3*/ -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(FLASH_SR_RDERR) #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */ -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ +#endif /* FLASH_SR_RDERR */ /* Cat3, Cat4 & Cat5*/ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(FLASH_SR_OPTVERRUSR) #define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/* Cat1*/ -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined (STM32L100xBA) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR) - -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA */ - -/* RDERR only for STM32L151xBA & STM32L152xBA (Cat2)*/ -#if defined (STM32L151xBA) || defined (STM32L152xBA) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_RDERR) - -#endif /* STM32L151xBA || STM32L152xBA */ - -/* FLASH_FLAG_OPTVERRUSR & RDERR only for STM32L151xC, STM32L152xC & STM32L152xBA (Cat3) */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC */ - -/* FLASH_FLAG_OPTVERRUSR only for STM32L100xC (Cat3) */ -#if defined (STM32L100xC) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR) - -#endif /* STM32L100xC */ - -/* Cat4 & Cat5 */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* FLASH_SR_OPTVERRUSR */ /** * @} */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT * @{ @@ -789,7 +837,6 @@ typedef struct or Bank 1, depending on the activation of the bank */ #define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position and this parameter is selected the device will boot from Bank1(Default) */ -#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) /** * @} @@ -802,16 +849,16 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros +/** @defgroup FLASHEx_Exported_Macros Exported Macros * @{ */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__ FLASH Latency * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle - * @arg FLASH_LATENCY_1: FLASH One Latency cycle + * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle * @retval none */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \ @@ -823,8 +870,8 @@ typedef struct * @brief Get the FLASH Latency. * @retval FLASH Latency * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle - * @arg FLASH_LATENCY_1: FLASH One Latency cycle + * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) @@ -916,18 +963,18 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) \ + || defined(STM32L152xDX) || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) \ + || defined(STM32L152xE) || defined(STM32L162xE) HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c index 946b3011758..fd0e1c35e8c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief FLASH RAMFUNC driver. * This file provides a Flash firmware functions which should be * executed from internal SRAM @@ -32,7 +32,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -66,23 +66,32 @@ * @{ */ -/** @defgroup FLASHRamfunc FLASHRamfunc +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC * @brief FLASH functions executed from RAM * @{ */ -#ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_RAMFUNC_Private_Functions Private Functions + * @{ + */ + static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + /* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASHRamfunc_Exported_Functions FLASH RAM Exported Functions +/** @defgroup FLASH_RAMFUNC_Exported_Functions Exported Functions * @verbatim =============================================================================== @@ -96,7 +105,7 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); * @{ */ -/** @defgroup FLASHRamfunc_Exported_Functions_Group1 FLASH RAM Peripheral features functions +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions * @{ */ @@ -131,15 +140,14 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) * @} */ -/** @defgroup FLASHRamfunc_Exported_Functions_Group2 FLASH RAM Programming and erasing operation functions +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions * @verbatim @endverbatim * @{ */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(FLASH_PECR_PARALLBANK) /** * @brief Erases a specified 2 page in program memory in parallel. * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. @@ -163,7 +171,7 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A HAL_StatusTypeDef status = HAL_OK; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { @@ -184,7 +192,7 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A *(__IO uint32_t *)Page_Address2 = 0x00000000; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); @@ -238,7 +246,7 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { @@ -249,7 +257,7 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf FLASH->PECR |= FLASH_PECR_PROG; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Write the first half page directly with 32 different words */ @@ -267,7 +275,7 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf count ++; } /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); @@ -280,7 +288,7 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf /* Return the Write Status */ return status; } -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* FLASH_PECR_PARALLBANK */ /** * @brief Programs a half page in program memory. @@ -319,7 +327,7 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { @@ -335,7 +343,7 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) count ++; } /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* if the write operation is completed, disable the PROG and FPRG bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); @@ -352,10 +360,8 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) * @} */ -/** @defgroup FLASHRamfunc_Exported_Functions_Group3 FLASH RAM DATA EEPROM functions - * -@verbatim -@endverbatim +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 DATA EEPROM functions + * * @{ */ @@ -387,7 +393,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address) SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { @@ -404,7 +410,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address) *(__IO uint32_t *)Address = 0x00000000; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the ERASE and DATA bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); @@ -446,7 +452,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { @@ -460,7 +466,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the write operation is completed, disable the FPRG and DATA bits */ FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); @@ -481,7 +487,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D * @} */ -/** @defgroup FLASHRamfunc_Private_Functions FLASH RAM Private Functions +/** @addtogroup FLASH_RAMFUNC_Private_Functions * @{ */ @@ -506,18 +512,22 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) return HAL_TIMEOUT; } + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined(FLASH_SR_RDERR) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* FLASH_SR_OPTVERRUSR */ (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) { return HAL_ERROR; @@ -527,7 +537,6 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) return HAL_OK; } -#endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} @@ -537,6 +546,7 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) * @} */ +#endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.h index 515defad21a..66162fcb741 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup FLASHRamfunc +/** @addtogroup FLASH_RAMFUNC * @{ */ @@ -59,7 +59,7 @@ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASHRamfunc_Exported_Functions +/** @addtogroup FLASH_RAMFUNC_Exported_Functions * @{ */ @@ -69,7 +69,7 @@ * file. */ -/** @addtogroup FLASHRamfunc_Exported_Functions_Group1 +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 * @{ */ @@ -80,17 +80,16 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); * @} */ -/** @addtogroup FLASHRamfunc_Exported_Functions_Group2 +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2 * @{ */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(FLASH_PECR_PARALLBANK) __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* FLASH_PECR_PARALLBANK */ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); @@ -98,7 +97,7 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); * @} */ -/** @addtogroup FLASHRamfunc_Exported_Functions_Group3 +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3 * @{ */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.c index a2f8340bdb4..a6e2289c53f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.c @@ -2,10 +2,10 @@ ****************************************************************************** * @file stm32l1xx_hal_gpio.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions @@ -37,33 +37,34 @@ [..] The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral’s alternate function (AF) connected + multiplexer that allows only one peripheral s alternate function (AF) connected to an IO pin at a time. In this way, there can be no conflict between peripherals sharing the same IO pin. - + [..] All ports have external interrupt/event capability. To use external interrupt lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. [..] - The external interrupt/event controller consists of up to 23 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### + The external interrupt/event controller consists of up to 28 edge detectors + (depending on products 16 lines are connected to GPIO) for generating event/interrupt + requests (each input line can be independently configured to select the type + (interrupt or event) and the corresponding trigger event (rising or falling or both). + Each line can also be masked independently. + + ##### How to use this driver ##### ============================================================================== - [..] + [..] (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). - + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure + configured through "Speed" member from GPIO_InitTypeDef structure, + the speed is configurable: Low, Medium and High. (++) If alternate mode is selected, the alternate function connected to the IO is configured through "Alternate" member from GPIO_InitTypeDef structure (++) Analog mode is required when a pin is to be used as ADC channel @@ -71,18 +72,23 @@ (++) In case of external interrupt/event selection the "Mode" member from GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). - + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). - + + (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also + recommended to use it to unconfigure pin which was used as an external interrupt + or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG + registers. + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - + (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - + (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). @@ -99,7 +105,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -124,7 +130,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" @@ -133,7 +139,7 @@ * @{ */ -/** @defgroup GPIO GPIO +/** @addtogroup GPIO * @brief GPIO HAL module driver * @{ */ @@ -142,38 +148,38 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants +/** @addtogroup GPIO_Private_Constants * @{ */ - #define GPIO_MODE ((uint32_t)0x00000003) #define EXTI_MODE ((uint32_t)0x10000000) #define GPIO_MODE_IT ((uint32_t)0x00010000) #define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) -#define GPIO_NUMBER ((uint32_t)16) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_NUMBER ((uint32_t)16) + /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions +/** @addtogroup GPIO_Exported_Functions * @{ */ -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup GPIO_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim @@ -188,12 +194,11 @@ * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position; - uint32_t ioposition = 0x00; +{ + uint32_t position = 0x00; uint32_t iocurrent = 0x00; uint32_t temp = 0x00; - + /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); @@ -201,28 +206,28 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ - for (position = 0; position < GPIO_NUMBER; position++) + while (((GPIO_Init->Pin) >> position) != 0) { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - - if (iocurrent == ioposition) + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & ((uint32_t)1 << position); + + if(iocurrent) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) { - /* Check the Alternate function parameter */ + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Configure Alternate function mapped with the current IO */ /* Identify AFRL or AFRH register based on IO position*/ temp = GPIOx->AFR[position >> 3]; CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); GPIOx->AFR[position >> 3] = temp; - } + } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; @@ -254,19 +259,19 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); GPIOx->PUPDR = temp; - + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable SYSCFG Clock */ - __SYSCFG_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2]; CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); - SET_BIT(temp, (GET_GPIO_INDEX(GPIOx)) << (4 * (position & 0x03))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); SYSCFG->EXTICR[position >> 2] = temp; - + /* Clear EXTI line configuration */ temp = EXTI->IMR; CLEAR_BIT(temp, (uint32_t)iocurrent); @@ -283,7 +288,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) SET_BIT(temp, iocurrent); } EXTI->EMR = temp; - + /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; CLEAR_BIT(temp, (uint32_t)iocurrent); @@ -300,9 +305,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) SET_BIT(temp, iocurrent); } EXTI->FTSR = temp; - } + } } - } + + position++; + } } /** @@ -313,55 +320,60 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position; - uint32_t ioposition = 0x00; +{ + uint32_t position = 0x00; uint32_t iocurrent = 0x00; uint32_t tmp = 0x00; - + /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - for (position = 0; position < GPIO_NUMBER; position++) + while ((GPIO_Pin >> position) != 0) { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (GPIO_Pin) & ioposition; + /* Get current io position */ + iocurrent = (GPIO_Pin) & ((uint32_t)1 << position); - if (iocurrent == ioposition) + if (iocurrent) { /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO Direction in Input Floting Mode */ CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); - + /* Configure the default Alternate Function in current IO */ CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - + /* Configure the default value for IO Speed */ CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - + /* Configure the default value IO Output Type */ CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; - + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2)); - - + /*------------------------- EXTI Mode Configuration --------------------*/ - /* Configure the External Interrupt or event for the current IO */ - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); - - /* Clear EXTI line configuration */ - CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2]; + tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) + { + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); + + /* Clear EXTI line configuration */ + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + } } + + position++; } } @@ -369,8 +381,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @} */ -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. * @verbatim =============================================================================== @@ -408,18 +420,16 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Sets or clears the selected data port bit. - * * @note This function uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. - * * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @param PinState: specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_BIT_RESET: to clear the port pin - * @arg GPIO_BIT_SET: to set the port pin + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) @@ -428,20 +438,20 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); - if(PinState != GPIO_PIN_RESET) + if (PinState != GPIO_PIN_RESET) { - GPIOx->BSRR = GPIO_Pin; + GPIOx->BSRR = (uint32_t)GPIO_Pin; } else { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; } } - + /** * @brief Toggles the specified GPIO pin - * @param GPIOx: where x can be (A..Gdepending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin: Specifies the pins to be toggled. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin: specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -458,8 +468,17 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. +* @note Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8 +* depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i]. +* GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8]. +* It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also +* GPIOx_OTYPER[i-8]. +* Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15, +* you must call also HAL_GPIO_LockPin with GPIO_Pin - 8. +* (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding +* GPIO_PIN_0 to GPIO_PIN_7). * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices -* @param GPIO_Pin: specifies the port bit to be locked. +* @param GPIO_Pin: Specifies the port bit to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ @@ -482,7 +501,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Read LCKK bit*/ tmp = GPIOx->LCKR; - if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) { return HAL_OK; } @@ -493,8 +512,8 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) } /** - * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -508,12 +527,15 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) } /** - * @brief EXTI line detection callback - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @brief EXTI line detection callbacks. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.h index 684e3211965..eb122a75f56 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_gpio.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,59 +50,59 @@ * @{ */ -/** @addtogroup GPIO +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ - */ - + */ /** * @brief GPIO Init structure definition - */ + */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ + This parameter can be any value of @ref GPIO_pins */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode_define */ - + This parameter can be a value of @ref GPIO_mode */ + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull_define */ - + This parameter can be a value of @ref GPIO_pull */ + uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed_define */ + This parameter can be a value of @ref GPIO_speed */ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ }GPIO_InitTypeDef; - + /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum -{ +{ GPIO_PIN_RESET = 0, GPIO_PIN_SET }GPIO_PinState; - /** * @} */ - - + /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ - */ + */ + -/** @defgroup GPIO_pins_define GPIO pins define +/** @defgroup GPIO_pins GPIO pins * @{ - */ + */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ @@ -124,10 +124,9 @@ typedef enum #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ /** * @} - */ + */ - -/** @defgroup GPIO_mode_define GPIO mode define +/** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ * - X : GPIO mode or EXTI Mode @@ -148,7 +147,7 @@ typedef enum #define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - + #define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ @@ -156,23 +155,21 @@ typedef enum /** * @} */ - -/** @defgroup GPIO_speed_define GPIO speed define +/** @defgroup GPIO_speed GPIO speed * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_VERY_LOW ((uint32_t)0x00000000) /*!< Very Low speed */ -#define GPIO_SPEED_LOW ((uint32_t)0x00000001) /*!< Low speed */ -#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000002) /*!< Medium speed */ -#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< max: 400 KHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */ /** * @} */ - - /** @defgroup GPIO_pull_define GPIO pull define + /** @defgroup GPIO_pull GPIO pull * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ @@ -183,26 +180,34 @@ typedef enum /** * @} */ - + /** * @} */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @} + */ /* Private macros --------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Macros +/** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) +#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00) #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ ((PULL) == GPIO_PULLDOWN)) -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_VERY_LOW) || ((SPEED) == GPIO_SPEED_LOW) || \ - ((SPEED) == GPIO_SPEED_MEDIUM) || ((SPEED) == GPIO_SPEED_HIGH)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ @@ -221,20 +226,20 @@ typedef enum * @} */ - /* Exported macro ------------------------------------------------------------*/ + /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ - + /** * @brief Checks whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. @@ -249,8 +254,8 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. @@ -267,47 +272,44 @@ typedef enum */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) -/* Include GPIO HAL Extension module */ -#include "stm32l1xx_hal_gpio_ex.h" /** * @} */ - +/* Include GPIO HAL Extension module */ +#include "stm32l1xx_hal_gpio_ex.h" /* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *******************************/ -/** @addtogroup GPIO_Exported_Functions +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions * @{ */ -/** @addtogroup GPIO_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * - * @{ - */ +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} */ -/* IO operation functions *******************************************************/ -/** @addtogroup GPIO_Exported_Functions_Group2 - * @brief Initialization and Configuration functions - * - * @{ - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); -/** - * @} - */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} @@ -321,7 +323,10 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); * @} */ - +/** + * @} + */ + #ifdef __cplusplus } #endif @@ -329,3 +334,4 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* __STM32L1xx_HAL_GPIO_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h index 2cf4ef65016..a8b2b75d81a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,137 +55,103 @@ */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ - /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection * @{ */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_OUT Alternate Function mapping */ +/* AF 0 selection */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /*!< TAMPER Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_OUT Alternate Function mapping */ -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +/* AF 1 selection */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +/* AF 2 selection */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */ #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */ -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +/* AF 3 selection */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +/* AF 4 selection */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +/* AF 5 selection */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */ -/** - * @brief AF 6 selection - */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) ||\ - defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) +/* AF 6 selection */ +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\ + defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */ -#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE || STM32L162xDX */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +/* AF 7 selection */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ -/** - * @brief AF 8 selection - */ -#if defined (STM32L151xD) || defined (STM32L151xE) ||\ - defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xD) || defined (STM32L162xE) +/* AF 8 selection */ +#if defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\ + defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */ -#endif /* STM32L151xD || STM32L151xE || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE */ +#endif /* STM32L151xD || STM32L151xE || STM32L151xDX || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE || STM32L162xDX */ -/** - * @brief AF 9 selection - */ +/* AF 9 selection */ -/** - * @brief AF 10 selection - */ +/* AF 10 selection */ -/** - * @brief AF 11 selection - */ +/* AF 11 selection */ #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) + defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ +#define GPIO_AF11_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */ -#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE */ +#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ -/** - * @brief AF 12 selection - */ +/* AF 12 selection */ #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */ #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -/** - * @brief AF 13 selection - */ +/* AF 13 selection */ -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ +/* AF 14 selection */ +#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +/* AF 15 selection */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ /** * @} @@ -203,32 +169,29 @@ #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOD))? 3U :\ ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) + ((__GPIOx__) == (GPIOH))? 5U :\ + ((__GPIOx__) == (GPIOF))? 6U : 7U) #endif #if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) -#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) + ((__GPIOx__) == (GPIOE))? 4U : 5U) #endif #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) -#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) + ((__GPIOx__) == (GPIOD))? 3U : 5U) #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.c index c2db8e2e192..b7ba2801343 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.c @@ -2,27 +2,26 @@ ****************************************************************************** * @file stm32l1xx_hal_i2c.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * + * + Peripheral State and Errors functions + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] The I2C HAL driver can be used as follows: - + (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; + I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -34,16 +33,16 @@ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Channel - (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx Channel + the DMA Tx or Rx channel (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API. + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() @@ -67,70 +66,70 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** Interrupt mode IO MEM operation *** ======================================= [..] - (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using HAL_I2C_Mem_Write_IT() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using HAL_I2C_Mem_Read_IT() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] - (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO MEM operation *** ================================= [..] - (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using HAL_I2C_Mem_Write_DMA() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using HAL_I2C_Mem_Read_DMA() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -138,12 +137,12 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt [..] (@) You can refer to the I2C HAL driver header file for more useful macros @@ -153,7 +152,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -177,7 +176,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -201,6 +200,7 @@ */ #define I2C_TIMEOUT_FLAG ((uint32_t)35) /* 35 ms */ #define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /* 10 s */ +#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000) /* 10 s */ #define I2C_MIN_PCLK_FREQ ((uint32_t)2000000) /* 2 MHz*/ /** @@ -229,6 +229,10 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); @@ -254,19 +258,19 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the I2Cx peripheral: + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - (+) Call the function HAL_I2C_Init() to configure the selected device with + (+) Call the function HAL_I2C_Init() to configure the selected device with the selected configuration: (++) Communication Speed (++) Duty cycle @@ -277,18 +281,18 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); (++) General call mode (++) Nostretch mode - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx periperal. + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. @endverbatim * @{ */ /** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and create the associated handle. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) @@ -297,11 +301,11 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) uint32_t pclk1 = 0; /* Check the I2C handle allocation */ - if(hi2c == HAL_NULL) + if(hi2c == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); @@ -315,7 +319,10 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) if(hi2c->State == HAL_I2C_STATE_RESET) { - /* Init the low level hardware : GPIO, CLOCK, NVIC */ + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); } @@ -329,12 +336,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) } hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disble the selected I2C peripheral */ + + /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); /* Calculate frequency range */ - freqrange = I2C_FREQRANGE(pclk1); + freqrange = I2C_FREQ_RANGE(pclk1); /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ @@ -362,42 +369,43 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); - + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; return HAL_OK; } /** - * @brief DeInitializes the I2C peripheral. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == HAL_NULL) + if(hi2c == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - + hi2c->State = HAL_I2C_STATE_BUSY; - + /* Disable the I2C Peripheral Clock */ __HAL_I2C_DISABLE(hi2c); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_I2C_MspDeInit(hi2c); - + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Release Lock */ __HAL_UNLOCK(hi2c); @@ -405,54 +413,60 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) } /** - * @brief I2C MSP Init. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspInit could be implemented in the user file - */ + */ } /** - * @brief I2C MSP DeInit - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspDeInit could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup I2C_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the I2C data + This subsection provides a set of functions allowing to manage the I2C data transfers. (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. (#) Blocking mode functions are : @@ -463,7 +477,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Mem_Write() (++) HAL_I2C_Mem_Read() (++) HAL_I2C_IsDeviceReady() - + (#) No-Blocking mode functions with Interrupt are : (++) HAL_I2C_Master_Transmit_IT() (++) HAL_I2C_Master_Receive_IT() @@ -495,32 +509,32 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Send Slave Address */ @@ -528,10 +542,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -542,9 +560,18 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA while(Size > 0) { /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Write data to DR */ @@ -560,22 +587,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Generate Stop */ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; - + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -583,30 +614,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } @@ -614,7 +641,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Process Locked */ __HAL_LOCK(hi2c); + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Send Slave Address */ @@ -622,15 +653,27 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } - if(Size == 1) + if(Size == 0) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if(Size == 1) { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); @@ -669,9 +712,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if(Size == 1) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } } /* Read data from DR */ @@ -735,9 +785,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd else { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } } /* Read data from DR */ @@ -753,55 +810,46 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } } - /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; - + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == HAL_NULL) || (Size == 0)) + { + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ @@ -812,7 +860,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { return HAL_TIMEOUT; } - + /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); @@ -832,9 +880,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData while(Size > 0) { /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Write data to DR */ @@ -861,52 +918,46 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Disable Address Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == HAL_NULL) || (Size == 0)) + { + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ @@ -924,9 +975,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, while(Size > 0) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } } /* Read data from DR */ @@ -942,9 +1002,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Wait until STOP flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK) { - return HAL_TIMEOUT; + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Clear STOP flag */ @@ -953,52 +1023,47 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Disable Address Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ +{ if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; @@ -1010,10 +1075,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -1021,51 +1090,70 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + if(hi2c->XferSize > 0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + else + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } return HAL_OK; } else { return HAL_BUSY; - } + } } /** - * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; @@ -1077,15 +1165,27 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } - if(hi2c->XferCount == 1) + if(hi2c->XferCount == 0) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + else if(hi2c->XferCount == 1) { /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); @@ -1116,16 +1216,23 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De __HAL_I2C_CLEAR_ADDRFLAG(hi2c); } + if(hi2c->XferCount == 0) + { + hi2c->State = HAL_I2C_STATE_READY; + } + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + if(hi2c->XferCount > 0) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } return HAL_OK; } else @@ -1146,20 +1253,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; @@ -1178,41 +1284,40 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; @@ -1236,29 +1341,25 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } @@ -1266,44 +1367,88 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Process Locked */ __HAL_LOCK(hi2c); + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + if(hi2c->XferSize > 0) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); - /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) { - return HAL_ERROR; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } } - else + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) { return HAL_TIMEOUT; } - } - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + hi2c->State = HAL_I2C_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1313,24 +1458,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t } /** - * @brief Receive in master mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == HAL_NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } @@ -1338,55 +1479,93 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + if(hi2c->XferSize > 0) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); - /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) { - return HAL_ERROR; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(Size == 1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); } else { - return HAL_TIMEOUT; + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); } - } - if(Size == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); } else { - /* Enable Last DMA bit */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - } + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1396,38 +1575,37 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D } /** - * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - /* Set the I2C DMA transfert complete callback */ + /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; /* Set the DMA error callback */ @@ -1471,7 +1649,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1481,40 +1659,39 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ + + /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - + /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; @@ -1538,7 +1715,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1548,14 +1725,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -1565,12 +1742,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } @@ -1578,7 +1756,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Send Slave Address and Memory Address */ @@ -1586,10 +1768,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -1597,11 +1783,20 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress while(Size > 0) { /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } - + /* Write data to DR */ hi2c->Instance->DR = (*pData++); Size--; @@ -1615,25 +1810,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Generate Stop */ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1644,14 +1843,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /** * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -1661,31 +1860,40 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -1726,9 +1934,16 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if(Size== 1) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } } /* Read data from DR */ @@ -1792,9 +2007,16 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, else { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + { + return HAL_TIMEOUT; + } + else + { + return HAL_ERROR; + } } /* Read data from DR */ @@ -1810,20 +2032,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } } - /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; - + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -1832,52 +2046,61 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } } /** - * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -1901,52 +2124,61 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /** - * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - + /* Send Slave Address and Memory Address */ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -1985,7 +2217,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ @@ -2000,44 +2232,49 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } } /** - * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - /* Set the I2C DMA transfert complete callback */ + /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; /* Set the DMA error callback */ @@ -2051,10 +2288,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -2074,29 +2315,30 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /** - * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be read + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } @@ -2104,14 +2346,18 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; - /* Set the I2C DMA transfert complete callback */ + /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; /* Set the DMA error callback */ @@ -2125,10 +2371,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -2152,7 +2402,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Unlocked */ __HAL_UNLOCK(hi2c); - + return HAL_OK; } else @@ -2162,13 +2412,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /** - * @brief Checks if target device is ready for communication. + * @brief Checks if target device is ready for communication. * @note This function is used with Memory devices - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param Trials: Number of trials - * @param Timeout: Timeout duration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param Trials Number of trials + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) @@ -2177,13 +2427,17 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if(hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); hi2c->State = HAL_I2C_STATE_BUSY; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2231,7 +2485,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_TIMEOUT; } @@ -2252,7 +2506,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) { return HAL_TIMEOUT; } @@ -2274,14 +2528,15 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /** * @brief This function handles I2C event interrupt request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) { - /* Master mode selected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == SET) + /* Master or Memory mode selected */ + if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \ + (hi2c->Mode == HAL_I2C_MODE_MEM)) { /* I2C in mode Transmitter -----------------------------------------------*/ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET) @@ -2367,12 +2622,12 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) } } } - + /** * @brief This function handles I2C error interrupt request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { @@ -2401,7 +2656,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) && \ (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) { - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == RESET) && \ + if((hi2c->Mode == HAL_I2C_MODE_SLAVE) && \ (hi2c->XferCount == 0) && \ (hi2c->State == HAL_I2C_STATE_BUSY_TX)) { @@ -2428,6 +2683,9 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { hi2c->State = HAL_I2C_STATE_READY; + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + /* Disable EVT, BUF and ERR interrupts */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -2436,90 +2694,111 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /** - * @brief Master Tx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterTxCpltCallback can be implemented in the user file */ } /** - * @brief Master Rx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterRxCpltCallback can be implemented in the user file */ } -/** @brief Slave Tx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file */ } /** - * @brief Slave Rx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file */ } /** - * @brief Memory Tx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemTxCpltCallback can be implemented in the user file */ } /** - * @brief Memory Rx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemRxCpltCallback can be implemented in the user file */ } /** - * @brief I2C error callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback can be implemented in the user file */ @@ -2532,12 +2811,12 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) /** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### +@verbatim =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -2545,21 +2824,33 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) */ /** - * @brief Returns the I2C state. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) { + /* Return I2C handle state */ return hi2c->State; } /** - * @brief Return the I2C error code - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** +* @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. -* @retval I2C Error Code + * @retval I2C Error Code */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { @@ -2572,7 +2863,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @} - */ + */ /** @addtogroup I2C_Private_Functions @@ -2582,28 +2873,30 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @brief Handle TXE flag for Master - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - if(hi2c->XferCount == 0) { /* Disable BUF interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); } + else + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } return HAL_OK; } /** * @brief Handle BTF flag for Master transmitter - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2623,13 +2916,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) /* Generate Stop */ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) + if(hi2c->Mode == HAL_I2C_MODE_MEM) { hi2c->State = HAL_I2C_STATE_READY; @@ -2647,7 +2934,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) /** * @brief Handle RXNE flag for Master - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2676,13 +2963,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) + if(hi2c->Mode == HAL_I2C_MODE_MEM) { hi2c->State = HAL_I2C_STATE_READY; @@ -2700,7 +2981,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) /** * @brief Handle BTF flag for Master receiver - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2731,13 +3012,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /* Disable EVT and ERR interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) + if(hi2c->Mode == HAL_I2C_MODE_MEM) { hi2c->State = HAL_I2C_STATE_READY; @@ -2761,7 +3036,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /** * @brief Handle TXE flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2778,7 +3053,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) /** * @brief Handle BTF flag for Slave transmitter - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2795,7 +3070,7 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) /** * @brief Handle RXNE flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2812,7 +3087,7 @@ static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) /** * @brief Handle BTF flag for Slave receiver - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2829,7 +3104,7 @@ static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) /** * @brief Handle ADD flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2843,7 +3118,7 @@ static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) /** * @brief Handle STOPF flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2858,12 +3133,6 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_SlaveRxCpltCallback(hi2c); @@ -2872,7 +3141,7 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) } /** - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -2887,12 +3156,6 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; HAL_I2C_SlaveTxCpltCallback(hi2c); @@ -2901,10 +3164,10 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) } /** - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param DevAddress: Target device address - * @param Timeout: Timeout duration + * @param DevAddress Target device address + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) @@ -2963,10 +3226,10 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ /** * @brief Master sends target device address for read request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param DevAddress: Target device address - * @param Timeout: Timeout duration + * @param DevAddress Target device address + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) @@ -3056,12 +3319,12 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /** * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) @@ -3095,9 +3358,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* If Memory address size is 8Bit */ @@ -3113,9 +3385,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Send LSB of Memory Address */ @@ -3127,12 +3408,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /** * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) @@ -3169,9 +3450,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* If Memory address size is 8Bit */ @@ -3187,9 +3477,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Send LSB of Memory Address */ @@ -3197,9 +3496,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } /* Generate Restart */ @@ -3232,7 +3540,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /** * @brief DMA I2C master transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) @@ -3253,13 +3561,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->XferCount = 0; - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Check if Errors has been detected during transfer */ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) @@ -3274,7 +3577,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C slave transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) @@ -3298,13 +3601,8 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->XferCount = 0; - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Check if Errors has been detected during transfer */ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) @@ -3319,7 +3617,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C master receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) @@ -3340,13 +3638,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->XferCount = 0; - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Check if Errors has been detected during transfer */ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) @@ -3361,7 +3654,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C slave receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) @@ -3369,9 +3662,16 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } } /* Clear STOPF flag */ @@ -3385,13 +3685,8 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->XferCount = 0; - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Check if Errors has been detected during transfer */ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) @@ -3406,7 +3701,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C Memory Write process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) @@ -3427,13 +3722,8 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->XferCount = 0; - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Check if Errors has been detected during transfer */ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) @@ -3448,34 +3738,29 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C Memory Read process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Generate Stop */ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); /* Disable Last DMA */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - /* Disable DMA Request */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); hi2c->XferCount = 0; - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Check if Errors has been detected during transfer */ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) @@ -3490,7 +3775,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) @@ -3503,6 +3788,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) hi2c->XferCount = 0; hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; @@ -3511,11 +3797,11 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles I2C Communication Timeout. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param Flag: specifies the I2C flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) @@ -3569,10 +3855,10 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /** * @brief This function handles I2C Communication Timeout for Master addressing phase. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param Flag: specifies the I2C flag to check. - * @param Timeout: Timeout duration + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout) @@ -3618,6 +3904,145 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD return HAL_OK; } +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +{ + uint32_t tickstart = 0x00; + tickstart = HAL_GetTick(); + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +{ + uint32_t tickstart = 0x00; + tickstart = HAL_GetTick(); + + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.h index 2c37ae4f956..84dfdaf0663 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_i2c.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,8 +59,9 @@ * @{ */ -/** +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition * @brief I2C Configuration Structure definition + * @{ */ typedef struct { @@ -91,40 +92,65 @@ typedef struct }I2C_InitTypeDef; /** - * @brief HAL State structures definition + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @{ */ typedef enum { - HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ - HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */ - HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */ - HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */ + HAL_I2C_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0 /*!< Error */ }HAL_I2C_StateTypeDef; /** - * @brief HAL I2C Error Code structure definition + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @{ */ typedef enum { - HAL_I2C_ERROR_NONE = 0x00, /*!< No error */ - HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */ - HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */ - HAL_I2C_ERROR_AF = 0x04, /*!< AF error */ - HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */ - HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */ + HAL_I2C_MODE_NONE = 0x00, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40 /*!< I2C communication is in Memory Mode */ -}HAL_I2C_ErrorTypeDef; +}HAL_I2C_ModeTypeDef; +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */ +#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ /** - * @brief I2C handle Structure definition + * @} */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ typedef struct { I2C_TypeDef *Instance; /*!< I2C registers base address */ @@ -145,93 +171,84 @@ typedef struct __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */ + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ }I2C_HandleTypeDef; /** * @} */ - +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2C_Exported_Constants I2C Exported Constants * @{ */ -/** @defgroup I2C_duty_cycle_in_fast_mode I2C_duty_cycle_in_fast_mode - * @{ - */ -#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000) -#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY - -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ - ((CYCLE) == I2C_DUTYCYCLE_16_9)) -/** - * @} - */ -/** @defgroup I2C_addressing_mode I2C_addressing_mode +/** @defgroup I2C_addressing_mode I2C addressing mode * @{ */ #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000) #define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000)) - -#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ - ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) /** * @} */ -/** @defgroup I2C_dual_addressing_mode I2C_dual_addressing_mode +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode * @{ */ -#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000) -#define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL +#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLED)) /** * @} */ -/** @defgroup I2C_general_call_addressing_mode I2C_general_call_addressing_mode +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode * @{ */ -#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000) -#define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \ - ((CALL) == I2C_GENERALCALL_ENABLED)) +#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC /** * @} */ -/** @defgroup I2C_nostretch_mode I2C_nostretch_mode +/** @defgroup I2C_nostretch_mode I2C nostretch mode * @{ */ -#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000) -#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLED)) +#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ -/** @defgroup I2C_Memory_Address_Size I2C_Memory_Address_Size +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size * @{ */ #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010) +/** + * @} + */ -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000) +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /** * @} */ -/** @defgroup I2C_Interrupt_configuration_definition I2C_Interrupt_configuration_definition +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask * @{ */ #define I2C_IT_BUF I2C_CR2_ITBUFEN @@ -241,7 +258,7 @@ typedef struct * @} */ -/** @defgroup I2C_Flag_definition I2C_Flag_definition +/** @defgroup I2C_Flag_definition I2C Flag definition * @{ */ #define I2C_FLAG_OVR ((uint32_t)(1 << 16 | I2C_SR1_OVR)) @@ -268,51 +285,24 @@ typedef struct * @} */ -/** @defgroup I2C_Clock_Speed_definition I2C_Clock_Speed_definition - * @{ - */ -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** @defgroup I2C_Own_Address1_definition I2C_Own_Address1_definition - * @{ - */ -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0) -/** - * @} - */ - -/** @defgroup I2C_Own_Address2_definition I2C_Own_Address2_definition - * @{ - */ -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0) -/** - * @} - */ - - /** * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup I2C_Exported_Macros I2C Exported Macros * @{ */ -/** @brief Reset I2C handle state - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -/** @brief Enable or disable the specified I2C interrupts. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__: specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg I2C_IT_BUF: Buffer interrupt enable * @arg I2C_IT_EVT: Event interrupt enable @@ -321,11 +311,20 @@ typedef struct */ #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * + * @retval None + */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) -/** @brief Checks if the specified I2C interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__: specifies the I2C interrupt source to check. * This parameter can be one of the following values: * @arg I2C_IT_BUF: Buffer interrupt enable @@ -335,10 +334,9 @@ typedef struct */ #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Checks whether the specified I2C flag is set or not. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to check. +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2C_FLAG_OVR: Overrun/Underrun flag * @arg I2C_FLAG_AF: Acknowledge failure flag @@ -362,10 +360,9 @@ typedef struct #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) -/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to clear. +/** @brief Clear the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) * @arg I2C_FLAG_AF: Acknowledge failure flag @@ -380,17 +377,26 @@ typedef struct * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. * @retval None */ - -#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\ - (__HANDLE__)->Instance->SR2;}while(0) +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + }while(0) /** @brief Clears the I2C STOPF pending flag. * @param __HANDLE__: specifies the I2C Handle. * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. * @retval None */ -#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\ - SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);}while(0) +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \ + UNUSED(tmpreg); \ + }while(0) /** @brief Enable the I2C peripheral. * @param __HANDLE__: specifies the I2C Handle. @@ -410,43 +416,15 @@ typedef struct * @} */ -/** @defgroup I2C_Private_Macros I2C Private Macros - * @{ - */ - -#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000) -#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1)) -#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1))) -#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9)) -#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) - -#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) -#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) - -#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) -#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) -#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) - -/** - * @} - */ - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup I2C_Exported_Functions * @{ */ -/* Initialization/de-initialization functions **********************************/ /** @addtogroup I2C_Exported_Functions_Group1 * @{ */ - +/* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); @@ -456,12 +434,10 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); * @} */ - -/* I/O operation functions *****************************************************/ /** @addtogroup I2C_Exported_Functions_Group2 * @{ */ - +/* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -486,7 +462,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +/** + * @} + */ +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -502,23 +484,88 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); * @} */ - -/* Peripheral Control and State functions **************************************/ /** @addtogroup I2C_Exported_Functions_Group3 * @{ */ - +/* Peripheral State, Mode and Error functions *********************************/ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ /** * @} */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + /** * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ */ +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000)) + + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + + +#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__)/1000000) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1))) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) +/** + * @} + */ +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c.c file */ +/** + * @} + */ /** * @} @@ -536,3 +583,4 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32L1xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c index 89857e7045f..258e25e956e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_i2s.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -108,7 +108,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -149,9 +149,9 @@ #ifdef HAL_I2S_MODULE_ENABLED #if defined(STM32L100xC) || \ - defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \ - defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || \ - defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || defined(STM32L151xDX) || \ + defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L152xDX) || \ + defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) uint32_t tmp = 0, i2sclk = 0; /* Check the I2S handle allocation */ - if(hi2s == HAL_NULL) + if(hi2s == NULL) { return HAL_ERROR; } @@ -230,6 +230,9 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) if(hi2s->State == HAL_I2S_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2S_MspInit(hi2s); } @@ -322,7 +325,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) { /* Check the I2S handle allocation */ - if(hi2s == HAL_NULL) + if(hi2s == NULL) { return HAL_ERROR; } @@ -352,6 +355,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_MspInit could be implemented in the user file */ @@ -365,6 +371,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_MspDeInit could be implemented in the user file */ @@ -433,7 +442,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) */ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -483,12 +492,16 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin { return HAL_TIMEOUT; } - /* Wait until Busy flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) + + /* Check if Slave mode is selected */ + if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) { - return HAL_TIMEOUT; + /* Wait until Busy flag is reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } } - hi2s->State = HAL_I2S_STATE_READY; /* Process Unlocked */ @@ -523,7 +536,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin */ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -601,7 +614,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint */ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -668,7 +681,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, */ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -733,7 +746,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u */ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -814,7 +827,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, */ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -967,14 +980,14 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); /* Abort the I2S DMA Channel tx */ - if(hi2s->hdmatx != HAL_NULL) + if(hi2s->hdmatx != NULL) { /* Disable the I2S DMA channel */ __HAL_DMA_DISABLE(hi2s->hdmatx); HAL_DMA_Abort(hi2s->hdmatx); } /* Abort the I2S DMA Channel rx */ - if(hi2s->hdmarx != HAL_NULL) + if(hi2s->hdmarx != NULL) { /* Disable the I2S DMA channel */ __HAL_DMA_DISABLE(hi2s->hdmarx); @@ -1065,6 +1078,9 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_TxHalfCpltCallback could be implemented in the user file */ @@ -1078,6 +1094,9 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_TxCpltCallback could be implemented in the user file */ @@ -1091,6 +1110,9 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_RxHalfCpltCallback could be implemented in the user file */ @@ -1104,6 +1126,9 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_RxCpltCallback could be implemented in the user file */ @@ -1117,6 +1142,9 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) */ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_ErrorCallback could be implemented in the user file */ @@ -1158,7 +1186,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } @@ -1369,9 +1397,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, * @} */ #endif /* STM32L100xC || - STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\ - STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE ||\\ - STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ + STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE || STM32L151xDX ||\\ + STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L152xDX ||\\ + STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ #endif /* HAL_I2S_MODULE_ENABLED */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.h index 1c398e1bc28..6d0dbd90f4d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_i2s.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -44,9 +44,9 @@ #endif #if defined(STM32L100xC) || \ - defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \ - defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L151xE) || \ - defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || defined(STM32L151xDX) || \ + defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L151xE) || defined(STM32L151xDX) || \ + defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" @@ -103,18 +103,6 @@ typedef enum HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ }HAL_I2S_StateTypeDef; -/** - * @brief HAL I2S Error Code structure definition - */ -typedef enum -{ - HAL_I2S_ERROR_NONE = 0x00, /*!< No error */ - HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */ - HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */ - HAL_I2S_ERROR_FRE = 0x04, /*!< I2S Frame format error */ - HAL_I2S_ERROR_DMA = 0x08 /*!< DMA transfer error */ -}HAL_I2S_ErrorTypeDef; - /** * @brief I2S handle Structure definition */ @@ -149,7 +137,7 @@ typedef struct __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ - __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */ + __IO uint32_t ErrorCode; /* I2S Error code */ }I2S_HandleTypeDef; /** @@ -161,6 +149,20 @@ typedef struct * @{ */ +/** @defgroup I2S_Error_Codes I2S Error Codes + * @{ + */ + +#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */ +#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */ +#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */ +#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ + +/** + * @} + */ + /** @defgroup I2S_Mode I2S Mode * @{ */ @@ -194,13 +196,6 @@ typedef struct ((STANDARD) == I2S_STANDARD_LSB) || \ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ ((STANDARD) == I2S_STANDARD_PCM_LONG)) -/** @defgroup I2S_Legacy I2S Legacy - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -/** - * @} - */ /** * @} @@ -360,6 +355,7 @@ typedef struct */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\ tmpreg = (__HANDLE__)->Instance->SR;\ + UNUSED(tmpreg); \ }while(0) /** @brief Clears the I2S UDR pending flag. * @param __HANDLE__: specifies the I2S Handle. @@ -423,7 +419,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); */ /* Peripheral Control and State functions ************************************/ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); /** * @} */ @@ -441,9 +437,9 @@ HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @} */ #endif /* STM32L100xC || - STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\ - STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L151xE ||\\ - STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ + STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE || STM32L151xDX ||\\ + STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L152xDX || STM32L151xE || STM32L151xDX ||\\ + STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ #ifdef __cplusplus } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.c index 9007ff9c19b..285db3cdf48 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_irda.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): @@ -24,7 +24,7 @@ (##) Enable the USARTx interface clock. (##) IRDA pins configuration: (+++) Enable the clock for the IRDA GPIOs. - (+++) Configure these IRDA pins as alternate function pull-up. + (+++) Configure the IRDA pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() and HAL_IRDA_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -37,6 +37,8 @@ (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler and Mode(Receiver/Transmitter) in the hirda Init structure. @@ -92,6 +94,7 @@ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt + (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not [..] (@) You can refer to the IRDA HAL driver header file for more useful macros @@ -100,7 +103,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -146,8 +149,6 @@ /** @defgroup IRDA_Private_Constants IRDA Private Constants * @{ */ -#define IRDA_TIMEOUT_VALUE 22000 -#define IRDA_DR_MASK_U16_7DATABITS (uint16_t)0x007F #define IRDA_DR_MASK_U16_8DATABITS (uint16_t)0x00FF #define IRDA_DR_MASK_U16_9DATABITS (uint16_t)0x01FF @@ -159,7 +160,7 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup IRDA_Private_Functions IRDA Private Functions @@ -185,7 +186,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, * @{ */ -/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions +/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -198,21 +199,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, (+) For the asynchronous mode only these parameters can be configured: (++) Baud Rate (++) Word Length - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible IRDA frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | IRDA frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ + (++) Parity (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may not be rejected. The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and @@ -228,6 +215,25 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, * @{ */ + +/* + Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible IRDA frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | IRDA frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ +*/ + /** * @brief Initializes the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and create the associated handle. @@ -238,7 +244,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == HAL_NULL) + if(hirda == NULL) { return HAL_ERROR; } @@ -250,6 +256,9 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) if(hirda->State == HAL_IRDA_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hirda->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_IRDA_MspInit(hirda); } @@ -296,7 +305,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == HAL_NULL) + if(hirda == NULL) { return HAL_ERROR; } @@ -329,6 +338,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_MspInit can be implemented in the user file */ @@ -342,6 +354,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_MspDeInit can be implemented in the user file */ @@ -378,7 +393,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process + will be executed respectively at the end of the transmit or Receive process The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected @@ -421,12 +436,12 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX)) + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -513,12 +528,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX)) + uint32_t tmp_state = 0; + + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -605,12 +620,12 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t tmp = 0; + uint32_t tmp_state = 0; - tmp = hirda->State; - if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_RX)) + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -631,15 +646,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->State = HAL_IRDA_STATE_BUSY_TX; } - /* Enable the IRDA Parity Error Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); + /* Process Unlocked */ + __HAL_UNLOCK(hirda); /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - /* Enable the IRDA Transmit Data Register Empty Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); @@ -661,12 +673,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t tmp = 0; + uint32_t tmp_state = 0; - tmp = hirda->State; - if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_TX)) + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -688,6 +700,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, hirda->State = HAL_IRDA_STATE_BUSY_RX; } + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + /* Enable the IRDA Data Register not empty Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); @@ -697,9 +712,6 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - return HAL_OK; } else @@ -719,12 +731,12 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { uint32_t *tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX)) + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -759,6 +771,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); @@ -786,12 +801,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { uint32_t *tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX)) + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -852,19 +867,18 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) if(hirda->State == HAL_IRDA_STATE_BUSY_TX) { - /* Disable the UART DMA Tx request */ + /* Disable the IRDA DMA Tx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) { - /* Disable the UART DMA Rx request */ + /* Disable the IRDA DMA Rx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) { - /* Disable the UART DMA Tx & Rx requests */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + /* Disable the IRDA DMA Tx & Rx requests */ + CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); } else { @@ -893,23 +907,22 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) if(hirda->State == HAL_IRDA_STATE_BUSY_TX) { - /* Enable the UART DMA Tx request */ + /* Enable the IRDA DMA Tx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) { /* Clear the Overrun flag before resumming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Enable the UART DMA Rx request */ + /* Enable the IRDA DMA Rx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) { /* Clear the Overrun flag before resumming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Enable the UART DMA Tx & Rx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + /* Enable the IRDA DMA Tx & Rx request */ + SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); } else { @@ -934,22 +947,22 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) { /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() */ - /* Disable the UART Tx/Rx DMA requests */ + /* Disable the IRDA Tx/Rx DMA requests */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - /* Abort the UART DMA tx channel */ - if(hirda->hdmatx != HAL_NULL) + /* Abort the IRDA DMA tx channel */ + if(hirda->hdmatx != NULL) { HAL_DMA_Abort(hirda->hdmatx); } - /* Abort the UART DMA rx channel */ - if(hirda->hdmarx != HAL_NULL) + /* Abort the IRDA DMA rx channel */ + if(hirda->hdmarx != NULL) { HAL_DMA_Abort(hirda->hdmarx); } @@ -967,41 +980,35 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) */ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { - uint32_t tmp1 = 0, tmp2 = 0; + uint32_t tmp_flag = 0, tmp_it_source = 0; - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE); + tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE); + tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE); /* IRDA parity error interrupt occurred -----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_IRDA_CLEAR_PEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_PE; } - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); + tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE); + tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); /* IRDA frame error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_IRDA_CLEAR_FEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_FE; } - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); + tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE); /* IRDA noise error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_IRDA_CLEAR_NEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_NE; } - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); + tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE); /* IRDA Over-Run interrupt occurred ---------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_IRDA_CLEAR_OREFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; } @@ -1013,31 +1020,34 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + /* Clear all the error flag at once */ + __HAL_IRDA_CLEAR_PEFLAG(hirda); + /* Set the IRDA state ready to be able to start again the process */ hirda->State = HAL_IRDA_STATE_READY; HAL_IRDA_ErrorCallback(hirda); } - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE); + tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE); + tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE); /* IRDA in mode Receiver --------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { IRDA_Receive_IT(hirda); } - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE); + tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE); + tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE); /* IRDA in mode Transmitter -----------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { IRDA_Transmit_IT(hirda); } - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC); + tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC); + tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC); /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { IRDA_EndTransmit_IT(hirda); } @@ -1052,6 +1062,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_TxCpltCallback can be implemented in the user file */ @@ -1065,6 +1078,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file */ @@ -1078,6 +1094,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_RxCpltCallback can be implemented in the user file */ @@ -1091,6 +1110,9 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE : This function should not be modified, when the callback is needed, the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file */ @@ -1104,6 +1126,9 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_ErrorCallback can be implemented in the user file */ @@ -1176,7 +1201,7 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { hirda->TxXferCount = 0; @@ -1184,27 +1209,8 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) in the IRDA CR3 register */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - /* Wait for IRDA TC Flag */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - hirda->State = HAL_IRDA_STATE_TIMEOUT; - HAL_IRDA_ErrorCallback(hirda); - } - else - { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - HAL_IRDA_TxCpltCallback(hirda); - } + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); } /* DMA Circular mode */ else @@ -1236,7 +1242,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { hirda->RxXferCount = 0; @@ -1369,10 +1375,10 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { uint16_t* tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_BUSY_TX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX)) { if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { @@ -1430,9 +1436,6 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - hirda->State = HAL_IRDA_STATE_READY; } @@ -1451,10 +1454,10 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { uint16_t* tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) + tmp_state = hirda->State; + if((tmp_state == HAL_IRDA_STATE_BUSY_RX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX)) { if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { @@ -1522,17 +1525,16 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { /* Check the parameters */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); assert_param(IS_IRDA_MODE(hirda->Init.Mode)); - /*-------------------------- IRDA CR2 Configuration ------------------------*/ + /*------- IRDA-associated USART registers setting : CR2 Configuration ------*/ /* Clear STOP[13:12] bits */ CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP); - /*-------------------------- USART CR1 Configuration -----------------------*/ + /*------- IRDA-associated USART registers setting : CR1 Configuration ------*/ /* Configure the USART Word Length, Parity and mode: Set the M bits according to hirda->Init.WordLength value Set PCE and PS bits according to hirda->Init.Parity value @@ -1541,11 +1543,11 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode); - /*-------------------------- USART CR3 Configuration -----------------------*/ + /*------- IRDA-associated USART registers setting : CR3 Configuration ------*/ /* Clear CTSE and RTSE bits */ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); - /*-------------------------- USART BRR Configuration -----------------------*/ + /*------- IRDA-associated USART registers setting : BRR Configuration ------*/ if(hirda->Instance == USART1) { hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.h index cc6cb046e9c..5a0707eb210 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_hal_irda.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief This file contains all the functions prototypes for the IRDA * firmware library. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,8 +67,8 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ + - IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref IRDA_Word_Length */ @@ -84,7 +84,10 @@ typedef struct uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref IRDA_Transfer_Mode */ - uint8_t Prescaler; /*!< Specifies the Prescaler */ + uint8_t Prescaler; /*!< Specifies the Prescaler value prescaler value to be programmed + in the IrDA low-power Baud Register, for defining pulse width on which + burst acceptance/rejection will be decided. This value is used as divisor + of system clock to achieve required pulse width. */ uint32_t IrDAMode; /*!< Specifies the IrDA mode This parameter can be a value of @ref IRDA_Low_Power */ @@ -105,49 +108,37 @@ typedef enum HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ }HAL_IRDA_StateTypeDef; -/** - * @brief HAL IRDA Error Code structure definition - */ -typedef enum -{ - HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */ - HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */ - HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */ - HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */ - HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_IRDA_ErrorTypeDef; /** * @brief IRDA handle Structure definition */ typedef struct { - USART_TypeDef *Instance; /* USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ - IRDA_InitTypeDef Init; /* IRDA communication parameters */ + IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ - uint16_t TxXferSize; /* IRDA Tx Transfer size */ + uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ - uint16_t TxXferCount; /* IRDA Tx Transfer Counter */ + uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ - uint16_t RxXferSize; /* IRDA Rx Transfer size */ + uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ - uint16_t RxXferCount; /* IRDA Rx Transfer Counter */ + uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */ + __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */ - __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */ + __IO uint32_t ErrorCode; /*!< IRDA Error code */ }IRDA_HandleTypeDef; @@ -160,39 +151,46 @@ typedef struct * @{ */ +/** @defgroup IRDA_Error_Codes IRDA Error Codes + * @{ + */ +#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ + +/** + * @} + */ + + /** @defgroup IRDA_Word_Length IRDA Word Length * @{ */ #define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ - ((LENGTH) == IRDA_WORDLENGTH_9B)) /** * @} */ - -/** @defgroup IRDA_Parity IRDA Parity +/** @defgroup IRDA_Parity IRDA Parity * @{ - */ + */ #define IRDA_PARITY_NONE ((uint32_t)0x00000000) #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ - ((PARITY) == IRDA_PARITY_EVEN) || \ - ((PARITY) == IRDA_PARITY_ODD)) /** * @} - */ - + */ -/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode +/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode * @{ - */ + */ #define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) #define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) #define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000)) /** * @} */ @@ -200,10 +198,17 @@ typedef struct /** @defgroup IRDA_Low_Power IRDA Low Power * @{ */ -#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) -#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) -#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ - ((MODE) == IRDA_POWERMODE_NORMAL)) +#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) +#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup IRDA_One_Bit IRDA One Bit Sampling + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /** * @} */ @@ -227,42 +232,35 @@ typedef struct /** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register + * - XXXX : Interrupt mask (16 bits) in the Y register * - Y : Interrupt source register (4 bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register * * @{ */ -#define IRDA_IT_PE ((uint32_t)0x10000100) -#define IRDA_IT_TXE ((uint32_t)0x10000080) -#define IRDA_IT_TC ((uint32_t)0x10000040) -#define IRDA_IT_RXNE ((uint32_t)0x10000020) -#define IRDA_IT_IDLE ((uint32_t)0x10000010) +#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) +#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) +#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) +#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) +#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) -#define IRDA_IT_LBD ((uint32_t)0x20000040) +#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE)) -#define IRDA_IT_CTS ((uint32_t)0x30000400) -#define IRDA_IT_ERR ((uint32_t)0x30000001) +#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE)) +#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE)) /** * @} */ -/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask - * @{ - */ -#define IRDA_IT_MASK ((uint32_t)0x0000FFFF) /** * @} */ -/** - * @} - */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros * @{ @@ -270,23 +268,23 @@ typedef struct /** @brief Reset IRDA handle state * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) -/** @brief Flushs the IRDA DR register +/** @brief Flush the IRDA DR register * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) -/** @brief Checks whether the specified IRDA flag is set or not. +/** @brief Check whether the specified IRDA flag is set or not. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg IRDA_FLAG_TXE: Transmit data register empty flag @@ -301,10 +299,10 @@ typedef struct */ #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -/** @brief Clears the specified IRDA pending flag. +/** @brief Clear the specified IRDA pending flag. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: * @arg IRDA_FLAG_TC: Transmission Complete flag. @@ -325,48 +323,54 @@ typedef struct /** @brief Clear the IRDA PE pending flag. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ -#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + }while(0) \ + /** @brief Clear the IRDA FE pending flag. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the IRDA NE pending flag. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the IRDA ORE pending flag. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the IRDA IDLE pending flag. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) -/** @brief Enables the specified IRDA interrupt. +/** @brief Enable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt @@ -377,14 +381,14 @@ typedef struct * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK))) -/** @brief Disables the specified IRDA interrupt. +/** @brief Disable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt @@ -395,39 +399,51 @@ typedef struct * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK))) +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK))) -/** @brief Checks whether the specified IRDA interrupt has occurred or not. +/** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __IT__: specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt * @arg IRDA_IT_TC: Transmission complete interrupt * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ERR: Error interrupt + * @arg IRDA_IT_ERR: Error interrupt * @arg IRDA_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:((((__IT__) >> 28) == IRDA_CR2_REG_INDEX)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK)) +/** @brief Enables the IRDA one bit sample method + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR3, (USART_CR3_ONEBIT))) + +/** @brief Disables the IRDA one bit sample method + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (USART_CR3_ONEBIT))) + /** @brief Enable UART/USART associated to IRDA Handle * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) /** @brief Disable UART/USART associated to IRDA Handle * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * IRDA Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) @@ -441,17 +457,45 @@ typedef struct * @{ */ +#define IRDA_CR1_REG_INDEX 1 +#define IRDA_CR2_REG_INDEX 2 +#define IRDA_CR3_REG_INDEX 3 + #define IRDA_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) #define IRDA_DIVMANT(__PCLK__, __BAUD__) (IRDA_DIV((__PCLK__), (__BAUD__))/100) #define IRDA_DIVFRAQ(__PCLK__, __BAUD__) (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -#define IRDA_BRR(__PCLK__, __BAUD__) ((IRDA_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(IRDA_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) - -/** @brief Ensure that IRDA Baud rate is less or equal to maximum value - * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. - * @retval True or False +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */ +#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \ + (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \ + (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F)) + +/** Ensure that IRDA Baud rate is less or equal to maximum value + * __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * The maximum Baud Rate is 115200bps + * Returns : True or False */ #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) - + +#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ + ((LENGTH) == IRDA_WORDLENGTH_9B)) + +#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ + ((PARITY) == IRDA_PARITY_EVEN) || \ + ((PARITY) == IRDA_PARITY_ODD)) + +#define IS_IRDA_MODE(MODE) ((((MODE) & (~((uint32_t)IRDA_MODE_TX_RX))) == 0x00) && \ + ((MODE) != (uint32_t)0x00000000)) + +#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ + ((MODE) == IRDA_POWERMODE_NORMAL)) + +/** IRDA interruptions flag mask + * + */ +#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ + USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) + /** * @} */ @@ -463,7 +507,7 @@ typedef struct * @{ */ -/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions +/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.c index 71185be5b6f..c9819a11d82 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.c @@ -2,35 +2,37 @@ ****************************************************************************** * @file stm32l1xx_hal_iwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief IWDG HAL module driver. * * This file provides firmware functions to manage the following - * functionalities of the IWDG peripheral: - * + Initialization and Configuration functions + * functionalities of the Independent Watchdog (IWDG) peripheral: + * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State functions * @verbatim - -================================================================================ - ##### IWDG specific features ##### -================================================================================ + ============================================================================== + ##### IWDG Generic features ##### + ============================================================================== [..] (+) The IWDG can be started by either software or hardware (configurable through option byte). + (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and thus stays active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled + Once the IWDG is started, the LSI is forced ON and cannot be disabled (LSI cannot be disabled too), and the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a system reset is generated. + (+) The IWDG counter should be refreshed at regular intervals, otherwise the watchdog generates an MCU reset when the counter reaches 0. + (+) The IWDG is implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. (+) Min-max timeout value @37KHz (LSI): ~108us / ~28.3s @@ -43,17 +45,18 @@ ##### How to use this driver ##### ============================================================================== [..] - (+) Set the IWDG prescaler and reload value - using HAL_IWDG_Init() function. - (+) Use IWDG using HAL_IWDG_Start() function to: - (++) Enable write access to IWDG_PR and IWDG_RLR registers. - (++) Configure the IWDG prescaler and counter reload values. - (++) Reload IWDG counter with value defined in the IWDG_RLR register. - (++) Start the IWDG, when the IWDG is used in software mode (no need - to enable the LSI, it will be enabled by hardware). + (+) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable write access to IWDG_PR, IWDG_RLR. + (++) Configure the IWDG prescaler, counter reload value. + This reload value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + (+) Use IWDG using HAL_IWDG_Start() function to : + (++) Reload IWDG counter with value defined in the IWDG_RLR register. + (++) Start the IWDG, when the IWDG is used in software mode (no need + to enable the LSI, it will be enabled by hardware). (+) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. + HAL_IWDG_Refresh() function. *** IWDG HAL driver macros list *** ==================================== @@ -62,16 +65,15 @@ (+) __HAL_IWDG_START: Enable the IWDG peripheral (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register - (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers - (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status - (+) __HAL_IWDG_CLEAR_FLAG: Clear the IWDG's pending flags + (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers + (+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -114,7 +116,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ @@ -128,7 +129,7 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Functions IWDG Exported Functions * @{ @@ -161,7 +162,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { /* Check the IWDG handle allocation */ - if(hiwdg == HAL_NULL) + if(hiwdg == NULL) { return HAL_ERROR; } @@ -180,6 +181,9 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) if(hiwdg->State == HAL_IWDG_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hiwdg->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_IWDG_MspInit(hiwdg); } @@ -188,7 +192,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) hiwdg->State = HAL_IWDG_STATE_BUSY; /* Enable write access to IWDG_PR and IWDG_RLR registers */ - __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg); + IWDG_ENABLE_WRITE_ACCESS(hiwdg); /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); @@ -209,7 +213,10 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) */ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* Prevent unused argument(s) compilation warning */ + UNUSED(hiwdg); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_IWDG_MspInit could be implemented in the user file */ } @@ -241,7 +248,7 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) */ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) { - /* Process Locked */ + /* Process locked */ __HAL_LOCK(hiwdg); /* Change IWDG peripheral state */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.h index e3a864a52e9..5a254180edc 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_iwdg.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,7 +55,6 @@ */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup IWDG_Exported_Types IWDG Exported Types * @{ */ @@ -106,41 +105,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup IWDG_Exported_Constants IWDG Exported Constants * @{ */ -/** @defgroup IWDG_Registers_BitMask IWDG_Registers_BitMask - * @brief IWDG registers bit mask - * @{ - */ -/* --- KR Register ---*/ -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ -#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ -#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ -#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ - -#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \ - ((__KR__) == KR_KEY_ENABLE))|| \ - ((__KR__) == KR_KEY_EWA)) || \ - ((__KR__) == KR_KEY_DWA)) -/** - * @} - */ - -/** @defgroup IWDG_Flag_definition IWDG_Flag_definition - * @{ - */ -#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */ -#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */ - -/** - * @} - */ - -/** @defgroup IWDG_Prescaler IWDG_Prescaler +/** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ #define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ @@ -150,24 +119,6 @@ typedef struct #define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ - -#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ - ((__PRESCALER__) == IWDG_PRESCALER_8) || \ - ((__PRESCALER__) == IWDG_PRESCALER_16) || \ - ((__PRESCALER__) == IWDG_PRESCALER_32) || \ - ((__PRESCALER__) == IWDG_PRESCALER_64) || \ - ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ - ((__PRESCALER__) == IWDG_PRESCALER_256)) - -/** - * @} - */ - -/** @defgroup IWDG_Reload_Value IWDG_Reload_Value - * @{ - */ -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) - /** * @} */ @@ -177,7 +128,6 @@ typedef struct */ /* Exported macros -----------------------------------------------------------*/ - /** @defgroup IWDG_Exported_Macros IWDG Exported Macros * @{ */ @@ -193,7 +143,7 @@ typedef struct * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE) +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) /** * @brief Reloads IWDG counter with value defined in the reload register @@ -201,21 +151,7 @@ typedef struct * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD) - -/** - * @brief Enables write access to IWDG_PR and IWDG_RLR registers. - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA) - -/** - * @brief Disables write access to IWDG_PR and IWDG_RLR registers. - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA) +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) /** * @brief Gets the selected IWDG's flag status. @@ -233,7 +169,6 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup IWDG_Exported_Functions * @{ */ @@ -244,7 +179,6 @@ typedef struct /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); - /** * @} */ @@ -255,7 +189,6 @@ void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); /* I/O operation functions ****************************************************/ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); - /** * @} */ @@ -265,7 +198,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); */ /* Peripheral State functions ************************************************/ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); - /** * @} */ @@ -274,6 +206,70 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); * @} */ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup IWDG_Private_Defines + * @{ + */ +/** + * @brief IWDG Key Register BitMask + */ +#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */ + +/** + * @brief IWDG Flag definition + */ +#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */ +#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Macro IWDG Private Macros + * @{ + */ +/** + * @brief Enables write access to IWDG_PR and IWDG_RLR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) + +/** + * @brief Disables write access to IWDG_PR and IWDG_RLR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) + +/** + * @brief Check IWDG prescaler value. + * @param __PRESCALER__: IWDG prescaler value + * @retval None + */ +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)) + +/** + * @brief Check IWDG reload value. + * @param __RELOAD__: IWDG reload value + * @retval None + */ +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) + +/** + * @} + */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.c index db0ee246af6..524b3d57438 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_lcd.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief LCD Controller HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LCD Controller (LCD) peripheral: @@ -21,15 +21,14 @@ (#) Initialize the LCD low level resources by implement the HAL_LCD_MspInit() API: (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows: - (+) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and - selected clock source (HSE, LSI or LSE) - - -@- The frequency generator allows you to achieve various LCD frame rates - starting from an LCD input clock frequency (LCDCLK) which can vary - from 32 kHz up to 1 MHz. + (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and + selected clock source (HSE, LSI or LSE) + (+++) The frequency generator allows you to achieve various LCD frame rates + starting from an LCD input clock frequency (LCDCLK) which can vary + from 32 kHz up to 1 MHz. (##) LCD pins configuration: - (+) Enable the clock for the LCD GPIOs. - (+) Configure these LCD pins as alternate function no-pull. + (+++) Enable the clock for the LCD GPIOs. + (+++) Configure these LCD pins as alternate function no-pull. (##) Enable the LCD interface clock. (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias, @@ -42,11 +41,11 @@ -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared (#) Optionally you can update the LCD configuration using these macros: - (+) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros - (+) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro - (+) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro - (+) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro - (+) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro + (++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros + (++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro + (++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro + (++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro + (++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called more time to update the different LCD RAM registers before calling @@ -64,7 +63,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,8 +100,8 @@ #ifdef HAL_LCD_MODULE_ENABLED #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) + defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) /** @defgroup LCD LCD * @brief LCD HAL module driver @@ -151,7 +150,7 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) { /* Check the LCD handle allocation */ - if(hlcd == HAL_NULL) + if(hlcd == NULL) { return HAL_ERROR; } @@ -159,7 +158,19 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) /* Check the parameters */ assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); + /* Check the LCD peripheral state */ + if(hlcd->State == HAL_LCD_STATE_BUSY) + { + return HAL_BUSY; + } + hlcd->State = HAL_LCD_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_LCD_DISABLE(hlcd); + + /*Disable Highdrive by default*/ + __HAL_LCD_HIGHDRIVER_DISABLE(hlcd); /* DeInit the low level hardware */ HAL_LCD_MspDeInit(hlcd); @@ -177,6 +188,7 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) * @brief Initializes the LCD peripheral according to the specified parameters * in the LCD_InitStruct. * @note This function can be used only when the LCD is disabled. + * The LCD HighDrive can be enabled/disabled using related macros up to user. * @param hlcd: LCD handle * @retval None */ @@ -186,7 +198,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) uint8_t counter = 0; /* Check the LCD handle allocation */ - if(hlcd == HAL_NULL) + if(hlcd == NULL) { return HAL_ERROR; } @@ -199,6 +211,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) assert_param(IS_LCD_BIAS(hlcd->Init.Bias)); assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource)); assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration)); + assert_param(IS_LCD_HIGHDRIVE(hlcd->Init.HighDrive)); assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime)); assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); @@ -207,6 +220,9 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) if(hlcd->State == HAL_LCD_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hlcd->Lock = HAL_UNLOCKED; + /* Initialize the low level hardware (MSP) */ HAL_LCD_MspInit(hlcd); } @@ -223,28 +239,29 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) hlcd->Instance->RAM[counter] = 0; } /* Enable the display request */ - hlcd->Instance->SR |= LCD_SR_UDR; + SET_BIT(hlcd->Instance->SR, LCD_SR_UDR); /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: - Set PS[3:0] bits according to hlcd->Init.Prescaler value + Set PS[3:0] bits according to hlcd->Init.Prescaler value Set DIV[3:0] bits according to hlcd->Init.Divider value Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value Set DEAD[2:0] bits according to hlcd->Init.DeadTime value Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value - Set CC[2:0] bits according to hlcd->Init.Contrast value */ + Set CC[2:0] bits according to hlcd->Init.Contrast value + Set HD[0] bit according to hlcd->Init.HighDrive value */ MODIFY_REG(hlcd->Instance->FCR, \ (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \ LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \ (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ - hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast)); + hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive)); /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register.*/ LCD_WaitForSynchro(hlcd); - /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast: + /* Configure the LCD Duty, Bias, Voltage Source, Dead Time: Set DUTY[2:0] bits according to hlcd->Init.Duty value Set BIAS[1:0] bits according to hlcd->Init.Bias value Set VSEL bit according to hlcd->Init.VoltageSource value @@ -296,6 +313,9 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) */ __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlcd); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_LCD_MspDeInit could be implemented in the user file */ @@ -308,6 +328,9 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) */ __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlcd); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_LCD_MspInit could be implemented in the user file */ @@ -327,19 +350,19 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) [..] Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification. - The application software can access the first buffer level (LCD_RAM) through + (+)The application software can access the first buffer level (LCD_RAM) through the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API, it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API. This UDR flag (update display request) requests the updated information to be moved into the second buffer level (LCD_DISPLAY). - This operation is done synchronously with the frame (at the beginning of the + (+)This operation is done synchronously with the frame (at the beginning of the next frame), until the update is completed, the LCD_RAM is write protected and the UDR flag stays high. - Once the update is completed another flag (UDD - Update Display Done) is set and + (+)Once the update is completed another flag (UDD - Update Display Done) is set and generates an interrupt if the UDDIE bit in the LCD_FCR register is set. The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one even frame. - The update will not occur (UDR = 1 and UDD = 0) until the display is + (+)The update will not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1). @endverbatim @@ -598,7 +621,7 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) * @} */ -#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */ +#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE || STM32L162xDX */ #endif /* HAL_LCD_MODULE_ENABLED */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.h index dc07d459375..5fcb68665ca 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_lcd.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of LCD Controller HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -48,8 +48,8 @@ */ #if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) + defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" @@ -86,6 +86,8 @@ typedef struct This parameter can be one value of @ref LCD_DeadTime */ uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration. This parameter can be one value of @ref LCD_PulseOnDuration */ + uint32_t HighDrive; /*!< Configures the LCD High Drive. + This parameter can be one value of @ref LCD_HighDrive */ uint32_t BlinkMode; /*!< Configures the LCD Blink Mode. This parameter can be one value of @ref LCD_BlinkMode */ uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency. @@ -106,19 +108,6 @@ typedef enum HAL_LCD_STATE_ERROR = 0x04 /*!< Error */ }HAL_LCD_StateTypeDef; -/** - * @brief HAL LCD Error Code structure definition - */ -typedef enum -{ - HAL_LCD_ERROR_NONE = 0x00, /*!< No error */ - HAL_LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag timeout error */ - HAL_LCD_ERROR_UDR = 0x02, /*!< Update display request flag timeout error */ - HAL_LCD_ERROR_UDD = 0x04, /*!< Update display done flag timeout error */ - HAL_LCD_ERROR_ENS = 0x08, /*!< LCD enabled status flag timeout error */ - HAL_LCD_ERROR_RDY = 0x10 /*!< LCD Booster ready timeout error */ -}HAL_LCD_ErrorTypeDef; - /** * @brief UART handle Structure definition */ @@ -132,7 +121,7 @@ typedef struct __IO HAL_LCD_StateTypeDef State; /* LCD communication state */ - __IO HAL_LCD_ErrorTypeDef ErrorCode; /* LCD Error code */ + __IO uint32_t ErrorCode; /* LCD Error code */ }LCD_HandleTypeDef; @@ -146,6 +135,21 @@ typedef struct * @{ */ +/** @defgroup LCD_Error_Codes LCD Error Codes + * @{ + */ + +#define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */ +#define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */ +#define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */ +#define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */ +#define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */ + +/** + * @} + */ + /** @defgroup LCD_Prescaler LCD Prescaler * @{ */ @@ -316,6 +320,18 @@ typedef struct * @} */ +/** @defgroup LCD_HighDrive LCD HighDrive + * @{ + */ + +#define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000) /*!< Low resistance Drive */ +#define LCD_HIGHDRIVE_1 (LCD_FCR_HD) /*!< High resistance Drive */ + +#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \ + ((__HIGHDRIVE__) == LCD_HIGHDRIVE_1)) +/** + * @} + */ /** @defgroup LCD_DeadTime LCD Dead Time * @{ @@ -748,7 +764,7 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); * @} */ -#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */ +#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE || STM32L162xDX */ /** * @} @@ -760,4 +776,4 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); #endif /* __STM32L1xx_HAL_LCD_H */ -/******************* (C) COPYRIGHT 2014 STMicroelectronics *****END OF FILE****/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c index 867342a8c1c..f5e3b727569 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_nor.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -49,13 +49,13 @@ [..] Below the list of most used macros in NOR HAL driver. - (+) __NOR_WRITE : NOR memory write data to specified address + (+) NOR_WRITE : NOR memory write data to specified address @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -89,24 +89,68 @@ * @{ */ +#ifdef HAL_NOR_MODULE_ENABLED +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + /** @defgroup NOR NOR * @brief NOR driver modules * @{ */ -#ifdef HAL_NOR_MODULE_ENABLED -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup NOR_Private_Constants NOR Private Constants + * @{ + */ + +/* Constants to define address to set to write a command */ +#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 +#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA +#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA +#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 + +/* Constants to define data to program a command */ +#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 +#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA +#define NOR_CMD_DATA_SECOND (uint16_t)0x0055 +#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 +#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 +#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 +#define NOR_CMD_DATA_CFI (uint16_t)0x0098 + +#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 +#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 +#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 + +/* Mask on NOR STATUS REGISTER */ +#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 +#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 + +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ +/** @defgroup NOR_Private_Macros NOR Private Macros + * @{ + */ + +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /** @defgroup NOR_Private_Variables NOR Private Variables * @{ */ -static uint32_t uwNORAddress = NOR_MEMORY_ADRESS1; -static uint32_t uwNORMememoryDataWidth = NOR_MEMORY_8B; +static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; /** * @} @@ -145,13 +189,16 @@ static uint32_t uwNORMememoryDataWidth = NOR_MEMORY_8B; HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) { /* Check the NOR handle parameter */ - if(hnor == HAL_NULL) + if(hnor == NULL) { return HAL_ERROR; } if(hnor->State == HAL_NOR_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hnor->Lock = HAL_UNLOCKED; + /* Initialize the low level hardware (MSP) */ HAL_NOR_MspInit(hnor); } @@ -168,34 +215,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeD /* Enable the NORSRAM device */ __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); - /* Initialize NOR address mapped by FSMC */ - if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM1) - { - uwNORAddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM2) - { - uwNORAddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM3) - { - uwNORAddress = NOR_MEMORY_ADRESS3; - } - else - { - uwNORAddress = NOR_MEMORY_ADRESS4; - } - /* Initialize NOR Memory Data Width*/ if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8) { - uwNORMememoryDataWidth = NOR_MEMORY_8B; + uwNORMemoryDataWidth = NOR_MEMORY_8B; } else { - uwNORMememoryDataWidth = NOR_MEMORY_16B; + uwNORMemoryDataWidth = NOR_MEMORY_16B; } - + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -233,6 +262,9 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) */ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnor); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspInit could be implemented in the user file */ @@ -246,13 +278,16 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) */ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnor); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspDeInit could be implemented in the user file */ } /** - * @brief NOR BSP Wait fro Ready/Busy signal + * @brief NOR MSP Wait fro Ready/Busy signal * @param hnor: pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @param Timeout: Maximum timeout value @@ -260,8 +295,12 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) */ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnor); + UNUSED(Timeout); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_BspWait could be implemented in the user file + the HAL_NOR_MspWait could be implemented in the user file */ } @@ -292,6 +331,8 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -300,20 +341,38 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read ID command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0090); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); /* Read the NOR IDs */ - pNOR_ID->ManufacturerCode = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, MC_ADDRESS); - pNOR_ID->DeviceCode1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->DeviceCode2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->DeviceCode3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE3_ADDR); + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -332,6 +391,8 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -341,7 +402,25 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) return HAL_BUSY; } - __NOR_WRITE(uwNORAddress, 0x00F0); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -362,6 +441,8 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -370,17 +451,35 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055); - __NOR_WRITE(*pAddress, 0x00F0); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET); /* Read the data */ - *pData = *(__IO uint32_t *)pAddress; + *pData = *(__IO uint32_t *)(uint32_t)pAddress; /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -401,6 +500,8 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -409,17 +510,35 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send program data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00A0); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); /* Write the data */ - __NOR_WRITE(pAddress, *pData); + NOR_WRITE(pAddress, *pData); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -442,6 +561,8 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -450,14 +571,32 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055); - __NOR_WRITE(uwAddress, 0x00F0); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET); /* Read buffer */ while( uwBufferSize > 0) @@ -482,16 +621,20 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress * @param hnor: pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @param uwAddress: NOR memory internal address from which the data + * @note Some NOR memory need Address aligned to xx bytes (can be aligned to + * 64 bytes boundary for example). * @param pData: pointer to source data buffer. - * @param uwBufferSize: number of Half words to write. The maximum allowed + * @param uwBufferSize: number of Half words to write. + * @note The maximum buffer size allowed is NOR memory dependent + * (can be 64 Bytes max for example). * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { - uint32_t lastloadedaddress = 0; - uint32_t currentaddress = 0; - uint32_t endaddress = 0; - + uint16_t * p_currentaddress = (uint16_t *)NULL; + uint16_t * p_endaddress = (uint16_t *)NULL; + uint32_t lastloadedaddress = 0, deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -500,35 +643,53 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Initialize variables */ - currentaddress = uwAddress; - endaddress = uwAddress + uwBufferSize - 1; - lastloadedaddress = uwAddress; + p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); + p_endaddress = p_currentaddress + (uwBufferSize-1); + lastloadedaddress = (uint32_t)(uwAddress); /* Issue unlock command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); /* Write Buffer Load Command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), 0x25); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), (uwBufferSize - 1)); + NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); /* Load Data into NOR Buffer */ - while(currentaddress <= endaddress) + while(p_currentaddress <= p_endaddress) { /* Store last loaded address & data value (for polling) */ - lastloadedaddress = currentaddress; + lastloadedaddress = (uint32_t)p_currentaddress; - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, currentaddress), *pData++); + NOR_WRITE(p_currentaddress, *pData++); - currentaddress += 1; + p_currentaddress++; } - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, lastloadedaddress), 0x29); + NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -550,6 +711,8 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -558,17 +721,35 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send block erase command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -589,6 +770,8 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -597,17 +780,35 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send NOR chip erase command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0010); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -627,6 +828,8 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); @@ -635,18 +838,36 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR { return HAL_BUSY; } + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; /* Send read CFI query command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0055), 0x0098); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); /* read the NOR CFI information */ - pNOR_CFI->CFI1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI4_ADDRESS); + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -761,56 +982,57 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) * the configuration information for NOR module. * @param Address: Device address * @param Timeout: NOR progamming Timeout - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT + * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR + * or HAL_NOR_STATUS_TIMEOUT */ -NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { - NOR_StatusTypedef status = NOR_ONGOING; - uint16_t tmpSR1 = 0, tmpSR2 = 0; + HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; + uint16_t tmp_sr1 = 0, tmp_sr2 = 0; uint32_t tickstart = 0; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ HAL_NOR_MspWait(hnor, Timeout); - /* Get the NOR memory operation status -------------------------------------*/ - while(status != NOR_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) { - /* Get tick */ - tickstart = HAL_GetTick(); - - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - status = NOR_TIMEOUT; - } - + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + status = HAL_NOR_STATUS_TIMEOUT; + } + } + /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + tmp_sr1 = *(__IO uint16_t *)Address; + tmp_sr2 = *(__IO uint16_t *)Address; /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) + if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) { - return NOR_SUCCESS; + return HAL_NOR_STATUS_SUCCESS; } - if((tmpSR1 & 0x0020) == 0x0020) + if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) { - return NOR_ONGOING; + status = HAL_NOR_STATUS_ONGOING; } - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + tmp_sr1 = *(__IO uint16_t *)Address; + tmp_sr2 = *(__IO uint16_t *)Address; /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) + if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) { - return NOR_SUCCESS; + return HAL_NOR_STATUS_SUCCESS; } - - if((tmpSR1 & 0x0020) == 0x0020) + else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) { - return NOR_ERROR; + return HAL_NOR_STATUS_ERROR; } } @@ -825,11 +1047,11 @@ NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, u /** * @} */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#endif /* HAL_NOR_MODULE_ENABLED */ /** * @} */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +#endif /* HAL_NOR_MODULE_ENABLED */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h index 46bd33c3f26..b005c7b0865 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_nor.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,15 +50,74 @@ * @{ */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) /** @addtogroup NOR * @{ */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +/** @addtogroup NOR_Private_Constants + * @{ + */ -/* Exported typedef ----------------------------------------------------------*/ +/* NOR device IDs addresses */ +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) + +/* NOR CFI IDs addresses */ +#define CFI1_ADDRESS ((uint16_t)0x10) +#define CFI2_ADDRESS ((uint16_t)0x11) +#define CFI3_ADDRESS ((uint16_t)0x12) +#define CFI4_ADDRESS ((uint16_t)0x13) + +/* NOR operation wait timeout */ +#define NOR_TMEOUT ((uint16_t)0xFFFF) + +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x0) +#define NOR_MEMORY_16B ((uint8_t)0x1) + +/* NOR memory device read/write start address */ +#define NOR_MEMORY_ADRESS1 FSMC_BANK1_1 +#define NOR_MEMORY_ADRESS2 FSMC_BANK1_2 +#define NOR_MEMORY_ADRESS3 FSMC_BANK1_3 +#define NOR_MEMORY_ADRESS4 FSMC_BANK1_4 + +/** + * @} + */ + +/** @addtogroup NOR_Private_Macros + * @{ + */ + +/** + * @brief NOR memory address shifting. + * @param __NOR_ADDRESS: NOR base address + * @param __NOR_MEMORY_WIDTH_: NOR memory width + * @param __ADDRESS__: NOR memory address + * @retval NOR shifted address value + */ +#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) + +/** + * @brief NOR memory write data to specified address. + * @param __ADDRESS__: NOR memory address + * @param __DATA__: Data to write + * @retval None + */ +#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) -/** @defgroup NOR_Exported_typedef NOR Exported typedef +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ +/** @defgroup NOR_Exported_Types NOR Exported Types * @{ */ @@ -72,7 +131,6 @@ typedef enum HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ - }HAL_NOR_StateTypeDef; /** @@ -80,32 +138,29 @@ typedef enum */ typedef enum { - NOR_SUCCESS = 0, - NOR_ONGOING, - NOR_ERROR, - NOR_TIMEOUT - -}NOR_StatusTypedef; + HAL_NOR_STATUS_SUCCESS = 0, + HAL_NOR_STATUS_ONGOING, + HAL_NOR_STATUS_ERROR, + HAL_NOR_STATUS_TIMEOUT +}HAL_NOR_StatusTypeDef; /** * @brief FSMC NOR ID typedef */ typedef struct { - uint16_t ManufacturerCode; /*!< Defines the device's manufacturer code used to identify the memory */ + uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ - uint16_t DeviceCode1; + uint16_t Device_Code1; - uint16_t DeviceCode2; + uint16_t Device_Code2; - uint16_t DeviceCode3; /*!< Defines the devices' codes used to identify the memory. + uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. These codes can be accessed by performing read operations with specific control signals and addresses set.They can also be accessed by issuing an Auto Select command */ - }NOR_IDTypeDef; - /** * @brief FSMC NOR CFI typedef */ @@ -115,14 +170,13 @@ typedef struct which contains a description of various electrical and timing parameters, density information and functions supported by the memory */ - uint16_t CFI1; - - uint16_t CFI2; + uint16_t CFI_1; - uint16_t CFI3; + uint16_t CFI_2; - uint16_t CFI4; + uint16_t CFI_3; + uint16_t CFI_4; }NOR_CFITypeDef; /** @@ -130,9 +184,9 @@ typedef struct */ typedef struct { - FSMC_NORSRAM_TYPEDEF *Instance; /*!< Register base address */ + FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended; /*!< Extended mode register base address */ + FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ @@ -147,43 +201,9 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ - -/** @defgroup NOR_Exported_Constants NOR Exported Constants - * @{ - */ - -/* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) - -/* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x10) -#define CFI2_ADDRESS ((uint16_t)0x11) -#define CFI3_ADDRESS ((uint16_t)0x12) -#define CFI4_ADDRESS ((uint16_t)0x13) - -/* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFF) - -/* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) - -/* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) - -/** - * @} - */ - /* Exported macro ------------------------------------------------------------*/ -/** @defgroup NOR_Exported_macro NOR Exported macro +/** @defgroup NOR_Exported_macro NOR Exported Macros * @{ */ @@ -193,34 +213,12 @@ typedef struct */ #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) - -/** - * @brief NOR memory address shifting. - * @param __NOR_ADDRESS: NOR base address - * @param __NOR_MEMORY_WIDTH_: NOR memory width - * @param __ADDRESS__: NOR memory address - * @retval NOR shifted address value - */ -#define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ - ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ - ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) - -/** - * @brief NOR memory write data to specified address. - * @param __ADDRESS__: NOR memory address - * @param __DATA__: Data to write - * @retval None - */ -#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) - /** * @} */ /* Exported functions --------------------------------------------------------*/ - -/** @addtogroup NOR_Exported_Functions +/** @addtogroup NOR_Exported_Functions NOR Exported Functions * @{ */ @@ -243,7 +241,7 @@ void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); * @{ */ -/* I/O operation functions *****************************************************/ +/* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); @@ -264,7 +262,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @{ */ -/* NOR Control functions *******************************************************/ +/* NOR Control functions *****************************************************/ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); @@ -276,9 +274,9 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); * @{ */ -/* NOR State functions **********************************************************/ +/* NOR State functions ********************************************************/ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); -NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); /** * @} @@ -288,12 +286,13 @@ NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @} */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ /** * @} */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.c index 04f11777fce..3dddc36ab7c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.c @@ -2,16 +2,14 @@ ****************************************************************************** * @file stm32l1xx_hal_opamp.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief OPAMP HAL module driver. - * * This file provides firmware functions to manage the following - * functionalities of the operational amplifiers (OPAMP1 ,... ,OPAMP3) + * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) * peripheral: * + OPAMP configuration * + OPAMP calibration - * * Thanks to * + Initialization and de-initialization functions * + IO operation functions @@ -22,86 +20,71 @@ ================================================================================ ##### OPAMP Peripheral Features ##### ================================================================================ - [..] The device integrates up to 3 operational amplifiers OPAMP1, OPAMP2, OPAMP3 (OPAMP3 availability depends on device category) (#) The OPAMP(s) provides several exclusive running modes. - (+) Standalone mode - (+) Follower mode + (++) Standalone mode + (++) Follower mode + + (#) All OPAMP (same for all OPAMPs) can operate in + (++) Either Low range (VDDA < 2.4V) power supply + (++) Or High range (VDDA > 2.4V) power supply + + (#) Each OPAMP(s) can be configured in normal and low power mode. (#) The OPAMP(s) provide(s) calibration capabilities. - (+) Calibration aims at correcting some offset for running mode. - (+) The OPAMP uses either factory calibration settings OR user defined + (++) Calibration aims at correcting some offset for running mode. + (++) The OPAMP uses either factory calibration settings OR user defined calibration (trimming) settings (i.e. trimming mode). - (+) The user defined settings can be figured out using self calibration + (++) The user defined settings can be figured out using self calibration handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll - (+) HAL_OPAMP_SelfCalibrate: - (++) Runs automatically the calibration in 2 steps: for transistors + (++) HAL_OPAMP_SelfCalibrate: + (+++) Runs automatically the calibration in 2 steps: for transistors differential pair high (PMOS) or low (NMOS) - (++) Enables the user trimming mode - (++) Updates the init structure with trimming values with fresh calibration + (+++) Enables the user trimming mode + (+++) Updates the init structure with trimming values with fresh calibration results. The user may store the calibration results for larger (ex monitoring the trimming as a function of temperature for instance) - (++) for devices having several OPAMPs, HAL_OPAMPEx_SelfCalibrateAll - runs calibration of all OPAMPs in parallel to save trimming search - wait time. - + (+++) For devices having several OPAMPs, HAL_OPAMPEx_SelfCalibrateAll + runs calibration of all OPAMPs in parallel to save search time. + (#) Running mode: Standalone mode - (+) Gain is set externally (gain depends on external loads). - (+) Follower mode also possible externally by connecting the inverting input to + (++) Gain is set externally (gain depends on external loads). + (++) Follower mode also possible externally by connecting the inverting input to the output. (#) Running mode: Follower mode - (+) No Inverting Input is connected. - (+) The OPAMP(s) output(s) are internally connected to inverting input + (++) No Inverting Input is connected. + (++) The OPAMP(s) output(s) are internally connected to inverting input. - (#) The OPAMPs inverting input can be selected among the list shown - in table below. - - (#) The OPAMPs non inverting input can be selected among the list shown - in table below. - - [..] Table 1. OPAMPs inverting/non-inverting inputs for STM32L1 devices: - - +--------------------------------------------------------------------------+ - | | HAL param | OPAMP1 | OPAMP2 | OPAMP3(4) | - | | name | | | | - |----------------|------------|--------------|--------------|--------------| - | Inverting | VM0 | PA2 | PA7 | PC2 | - | input (1) | VM1 | VINM pin (2) | VINM pin (2) | VINM pin (2) | - |----------------|------------|--------------|--------------|--------------| - | Non Inverting | VP0 | PA1 | PA6 | PC1 | - | input | DAC_CH1 (3)| DAC_CH1 | DAC_CH1 | --- | - | | DAC_CH2 (3)| --- | DAC_CH2 | DAC_CH2 | - +--------------------------------------------------------------------------+ - (1): NA in follower mode. - (2): OPAMP input OPAMPx_VINM are dedicated OPAMP pins, their availability - depends on device package. - (3): DAC channels 1 and 2 are connected internally to OPAMP. Nevertheless, - I/O pins connected to DAC can still be used as DAC output (pins PA4 - and PA5). - (4): OPAMP3 availability depends on device category. + ##### How to use this driver ##### +================================================================================ + [..] + *** power supply range *** + ============================================ + [..] + To run in low power mode: - [..] Table 2. OPAMPs outputs for STM32L1 devices: + (#) Configure the opamp using HAL_OPAMP_Init() function: + (++) Select OPAMP_POWERSUPPLY_LOW (VDDA lower than 2.4V) + (++) Otherwise select OPAMP_POWERSUPPLY_HIGH (VDDA higher than 2.4V) - +--------------------------------------------------------+ - | | OPAMP1 | OPAMP2 | OPAMP3(4) | - |-----------------|------------|------------|------------| - | Output | PA3 | PB0 | PC3 | - +--------------------------------------------------------+ - (4) : OPAMP3 availability depends on device category + *** low / normal power mode *** + ============================================ + [..] + To run in low power mode: + (#) Configure the opamp using HAL_OPAMP_Init() function: + (++) Select OPAMP_POWERMODE_LOWPOWER + (++) Otherwise select OPAMP_POWERMODE_NORMAL - ##### How to use this driver ##### -================================================================================ - [..] - *** Calibration *** ============================================ + [..] To run the opamp calibration self calibration: (#) Start calibration using HAL_OPAMP_SelfCalibrate. @@ -109,20 +92,21 @@ *** Running mode *** ============================================ + [..] To use the opamp, perform the following steps: (#) Fill in the HAL_OPAMP_MspInit() to - (+) Enable the OPAMP Peripheral clock using macro "__OPAMP_CLK_ENABLE()" + (++) Enable the OPAMP Peripheral clock using macro "__HAL_RCC_OPAMP_CLK_ENABLE()" (++) Configure the opamp input AND output in analog mode using HAL_GPIO_Init() to map the opamp output to the GPIO pin. (#) Configure the opamp using HAL_OPAMP_Init() function: - (+) Select the mode - (+) Select the inverting input - (+) Select the non-inverting input - (+) Select either factory or user defined trimming mode. - (+) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values + (++) Select the mode + (++) Select the inverting input + (++) Select the non-inverting input + (++) Select either factory or user defined trimming mode. + (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values (typ. settings returned by HAL_OPAMP_SelfCalibrate function). (#) Enable the opamp using HAL_OPAMP_Start() function. @@ -137,18 +121,24 @@ *** Running mode: change of configuration while OPAMP ON *** ============================================ + [..] To Re-configure OPAMP when OPAMP is ON (change on the fly) (#) If needed, Fill in the HAL_OPAMP_MspInit() - (+) This is the case for instance if you wish to use new OPAMP I/O + (++) This is the case for instance if you wish to use new OPAMP I/O (#) Configure the opamp using HAL_OPAMP_Init() function: - (+) As in configure case, selects first the parameters you wish to modify. + (++) As in configure case, selects first the parameters you wish to modify. + (#) Change from low power mode to normal power mode (& vice versa) requires + first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). + In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode + alone. + @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -175,6 +165,40 @@ ****************************************************************************** */ +/* + Additionnal remark: + The OPAMPs inverting input can be selected among the list shown by table below. + The OPAMPs non inverting input can be selected among the list shown by table below. + + Table 1. OPAMPs inverting/non-inverting inputs for STM32L1 devices: + +--------------------------------------------------------------------------+ + | | HAL param | OPAMP1 | OPAMP2 | OPAMP3(4) | + | | name | | | | + |----------------|------------|--------------|--------------|--------------| + | Inverting | VM0 | PA2 | PA7 | PC2 | + | input (1) | VM1 | VINM pin (2) | VINM pin (2) | VINM pin (2) | + |----------------|------------|--------------|--------------|--------------| + | Non Inverting | VP0 | PA1 | PA6 | PC1 | + | input | DAC_CH1 (3)| DAC_CH1 | DAC_CH1 | --- | + | | DAC_CH2 (3)| --- | DAC_CH2 | DAC_CH2 | + +--------------------------------------------------------------------------+ + (1): NA in follower mode. + (2): OPAMP input OPAMPx_VINM are dedicated OPAMP pins, their availability + depends on device package. + (3): DAC channels 1 and 2 are connected internally to OPAMP. Nevertheless, + I/O pins connected to DAC can still be used as DAC output (pins PA4 + and PA5). + (4): OPAMP3 availability depends on device category. + + Table 2. OPAMPs outputs for STM32L1 devices: + +--------------------------------------------------------+ + | | OPAMP1 | OPAMP2 | OPAMP3(4) | + |-----------------|------------|------------|------------| + | Output | PA3 | PB0 | PC3 | + +--------------------------------------------------------+ + (4) : OPAMP3 availability depends on device category +*/ + /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" @@ -183,20 +207,22 @@ */ /** @defgroup OPAMP OPAMP - * @brief OPAMP HAL module driver + * @brief OPAMP module driver * @{ */ #ifdef HAL_OPAMP_MODULE_ENABLED -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions * @{ @@ -206,10 +232,10 @@ * @brief Initialization and Configuration functions * @verbatim - =============================================================================== + ============================================================================== ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: + ============================================================================== + [..] This section provides functions allowing to: @endverbatim * @{ @@ -230,7 +256,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) /* Check the OPAMP handle allocation and lock status */ /* Init not allowed if calibration is ongoing */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) ) { status = HAL_ERROR; @@ -241,10 +267,10 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); /* Set OPAMP parameters */ - assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); - assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput)); - assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange)); + assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); + assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); + assert_param(IS_OPAMP_NONINVERTING_INPUT_CHECK_INSTANCE(hopamp, hopamp->Init.NonInvertingInput)); assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); if (hopamp->Init.Mode != OPAMP_FOLLOWER_MODE) @@ -266,10 +292,15 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) } } + if(hopamp->State == HAL_OPAMP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hopamp->Lock = HAL_UNLOCKED; + } + /* Call MSP init function */ HAL_OPAMP_MspInit(hopamp); - /* Set OPAMP parameters */ /* - Set internal switches in function of: */ /* - OPAMP selected mode: standalone or follower. */ @@ -279,11 +310,16 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) /* - Set power mode and associated calibration parameters */ /* Get OPAMP CSR register into temporary variable */ + /* Note: OPAMP register CSR is written directly, independently of OPAMP */ + /* instance, because all OPAMP settings are dispatched in the same */ + /* register. */ + /* Settings of bits for each OPAMP instances are managed case by */ + /* case using macro (OPAMP_CSR_S3SELX(), OPAMP_CSR_ANAWSELX(), ...) */ tmp_csr = OPAMP->CSR; /* Open all switches on non-inverting input, inverting input and output */ /* feedback. */ - CLEAR_BIT(tmp_csr, __OPAMP_CSR_ALL_SWITCHES(hopamp)); + CLEAR_BIT(tmp_csr, OPAMP_CSR_ALL_SWITCHES(hopamp)); /* Set internal switches in function of OPAMP mode selected: standalone */ /* or follower. */ @@ -294,36 +330,36 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE) { /* Follower mode: Close switches S3 and SanB */ - SET_BIT(tmp_csr, __OPAMP_CSR_S3SELX(hopamp)); + SET_BIT(tmp_csr, OPAMP_CSR_S3SELX(hopamp)); } else { /* Set internal switches in function of inverting input selected: */ - /* Close switch to connect comparator inverting input to the selected */ + /* Close switch to connect OPAMP inverting input to the selected */ /* input: dedicated IO pin or alternative IO pin available on some */ /* device packages. */ - if (hopamp->Init.InvertingInput == OPAMP_INVERTINGINPUT_VM0) + if (hopamp->Init.InvertingInput == OPAMP_INVERTINGINPUT_IO0) { - /* Close switch to connect comparator non-inverting input to */ + /* Close switch to connect OPAMP non-inverting input to */ /* dedicated IO pin low-leakage. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S4SELX(hopamp)); + SET_BIT(tmp_csr, OPAMP_CSR_S4SELX(hopamp)); } else { - /* Close switch to connect comparator inverting input to alternative */ + /* Close switch to connect OPAMP inverting input to alternative */ /* IO pin available on some device packages. */ - SET_BIT(tmp_csr, __OPAMP_CSR_ANAWSELX(hopamp)); + SET_BIT(tmp_csr, OPAMP_CSR_ANAWSELX(hopamp)); } } /* Set internal switches in function of non-inverting input selected: */ - /* Close switch to connect comparator non-inverting input to the selected */ + /* Close switch to connect OPAMP non-inverting input to the selected */ /* input: dedicated IO pin or DAC channel. */ - if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_VP0) + if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_IO0) { - /* Close switch to connect comparator non-inverting input to */ + /* Close switch to connect OPAMP non-inverting input to */ /* dedicated IO pin low-leakage. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S5SELX(hopamp)); + SET_BIT(tmp_csr, OPAMP_CSR_S5SELX(hopamp)); } else if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_DAC_CH1) { @@ -333,9 +369,9 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) /* (OPAMP3 availability depends on device category). */ if ((hopamp->Instance == OPAMP1) || (hopamp->Instance == OPAMP2)) { - /* Close switch to connect comparator non-inverting input to */ + /* Close switch to connect OPAMP non-inverting input to */ /* DAC channel 1. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); + SET_BIT(tmp_csr, OPAMP_CSR_S6SELX(hopamp)); } else { @@ -352,16 +388,16 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) /* (OPAMP3 availability depends on device category). */ if (hopamp->Instance == OPAMP2) { - /* Close switch to connect comparator non-inverting input to */ + /* Close switch to connect OPAMP non-inverting input to */ /* DAC channel 2. */ SET_BIT(tmp_csr, OPAMP_CSR_S7SEL2); } /* If OPAMP3 is selected (if available) */ else if (hopamp->Instance != OPAMP1) { - /* Close switch to connect comparator non-inverting input to */ + /* Close switch to connect OPAMP non-inverting input to */ /* DAC channel 2. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); + SET_BIT(tmp_csr, OPAMP_CSR_S6SELX(hopamp)); } else { @@ -378,7 +414,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) { /* Set normal mode */ - CLEAR_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); + CLEAR_BIT(tmp_csr, OPAMP_CSR_OPAXLPM(hopamp)); if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) { @@ -386,11 +422,11 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) /* transistors differential pair high (PMOS) and low (NMOS) for */ /* normal mode. */ MODIFY_REG(OPAMP->OTR, OPAMP_OTR_OT_USER | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | + OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , hopamp->Init.UserTrimming | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueN) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValueP) ); + OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueN) | + OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValueP) ); } else { @@ -402,7 +438,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) else { /* Set low power mode */ - SET_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); + SET_BIT(tmp_csr, OPAMP_CSR_OPAXLPM(hopamp)); if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) { @@ -411,10 +447,10 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) /* Set values for transistors differential pair high (PMOS) and low */ /* (NMOS) for low power mode. */ - MODIFY_REG(OPAMP->LPOTR, __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueNLowPower) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValuePLowPower) ); + MODIFY_REG(OPAMP->LPOTR, OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | + OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueNLowPower) | + OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValuePLowPower) ); } else { @@ -440,22 +476,21 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) /* Update the OPAMP state */ /* If coming from state reset: Update from state RESET to state READY */ - /* else: remain in state READY or BUSY (no update) */ if (hopamp->State == HAL_OPAMP_STATE_RESET) { hopamp->State = HAL_OPAMP_STATE_READY; } + /* else: OPAMP state remains READY or BUSY state (no update) */ } } return status; } - /** * @brief DeInitializes the OPAMP peripheral - * @note Deinitialization can't be performed if the OPAMP configuration is locked. - * To unlock the configuration, perform a system reset. + * @note Deinitialization can be performed if the OPAMP configuration is locked. + * (the OPAMP lock is SW in STM32L1) * @param hopamp: OPAMP handle * @retval HAL status */ @@ -464,27 +499,38 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef* hopamp) HAL_StatusTypeDef status = HAL_OK; /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ /* DeInit not allowed if calibration is ongoing */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) { status = HAL_ERROR; } else { - /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + /* Disable the selected opamp */ + SET_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp)); + /* Open all switches on non-inverting input, inverting input and output */ /* feedback. */ - CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); - - /* DeInit the low level hardware */ + /* Note: OPAMP register CSR is written directly, independently of OPAMP */ + /* instance, because all OPAMP settings are dispatched in the same */ + /* register. */ + /* Settings of bits for each OPAMP instances are managed case by */ + /* case using macro (OPAMP_CSR_S3SELX(), OPAMP_CSR_ANAWSELX(), ...) */ + CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES(hopamp)); + + /* Note: Registers and bits shared with other OPAMP instances are kept */ + /* unchanged, to not impact other OPAMP while operating on the */ + /* selected OPAMP. */ + /* Unchanged: bit OPAMP_OTR_OT_USER (parameter "UserTrimming") */ + /* bit OPAMP_CSR_AOP_RANGE (parameter "PowerSupplyRange")*/ + + /* DeInit the low level hardware: GPIO, CLOCK and NVIC */ HAL_OPAMP_MspDeInit(hopamp); - /* Update the OPAMP state*/ + /* Update the OPAMP state*/ hopamp->State = HAL_OPAMP_STATE_RESET; } @@ -502,6 +548,9 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef* hopamp) */ __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* hopamp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hopamp); + /* NOTE : This function Should not be modified, when the callback is needed, the function "HAL_OPAMP_MspInit()" must be implemented in the user file. */ @@ -514,6 +563,9 @@ __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* hopamp) */ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* hopamp) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hopamp); + /* NOTE : This function Should not be modified, when the callback is needed, the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file. */ @@ -529,8 +581,8 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* hopamp) * @verbatim =============================================================================== - ##### IO operation functions ##### - =============================================================================== + ##### IO operation functions ##### + =============================================================================== [..] This subsection provides a set of functions allowing to manage the OPAMP start, stop and calibration actions. @@ -551,7 +603,7 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef* hopamp) /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) { status = HAL_ERROR; } @@ -563,7 +615,7 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef* hopamp) if(hopamp->State == HAL_OPAMP_STATE_READY) { /* Enable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); + CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp)); /* Update the OPAMP state */ /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */ @@ -590,7 +642,7 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef* hopamp) /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ /* Check if OPAMP calibration ongoing */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) { status = HAL_ERROR; @@ -603,7 +655,7 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef* hopamp) if(hopamp->State == HAL_OPAMP_STATE_BUSY) { /* Disable the selected opamp */ - SET_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); + SET_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp)); /* Update the OPAMP state*/ /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/ @@ -620,14 +672,13 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef* hopamp) /** * @brief Run the self calibration of one OPAMP * @note Trimming values (PMOS & NMOS) are updated and user trimming is - * enabled is calibration is succesful. + * enabled if calibration is succesful. * @note Calibration is performed in the mode specified in OPAMP init * structure (mode normal or low-power). To perform calibration for * both modes, repeat this function twice after OPAMP init structure * accordingly updated. - * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P - * and N transistors: 10 steps with 1 ms for each step). - * @param hopamp: handle + * @note Calibration runs about 10 ms. + * @param hopamp handle * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled * @retval HAL status */ @@ -648,13 +699,13 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) uint32_t tmp_OpaxSwitchesContextBackup = 0; - uint8_t trimming_diff_pair_iteration_count = 0; - uint8_t delta = 0; - + uint8_t trimming_diff_pair_iteration_count = 0; /* For calibration loop algorithm: to repeat the calibration loop for both differential transistors pair high and low */ + uint8_t delta = 0; /* For calibration loop algorithm: Variable for dichotomy steps value */ + uint8_t final_step_check = 0; /* For calibration loop algorithm: Flag for additional check of last trimming step */ /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) { status = HAL_ERROR; } @@ -673,11 +724,11 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) /* Backup of switches configuration to restore it at the end of the */ /* calibration. */ - tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); + tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES(hopamp)); /* Open all switches on non-inverting input, inverting input and output */ /* feedback. */ - CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); + CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES(hopamp)); /* Set calibration mode to user programmed trimming values */ SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); @@ -697,7 +748,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) /* Enable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); + CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp)); /* Perform trimming for both differential transistors pair high and low */ for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) @@ -713,8 +764,8 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) tmp_Opaxcalout_DefaultSate = RESET; /* Enable calibration for N differential pair */ - MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_L(hopamp), - __OPAMP_CSR_OPAXCAL_H(hopamp) ); + MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L(hopamp), + OPAMP_CSR_OPAXCAL_H(hopamp) ); } else /* (trimming_diff_pair_iteration_count == 1) */ { @@ -724,11 +775,11 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opaxcalout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp); + tmp_Opaxcalout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp); /* Enable calibration for P differential pair */ - MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_H(hopamp), - __OPAMP_CSR_OPAXCAL_L(hopamp) ); + MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H(hopamp), + OPAMP_CSR_OPAXCAL_L(hopamp) ); } @@ -738,25 +789,37 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) /* can extend the search range to +/- 15 units. */ /* - Trimming initial value 15: search range will go from 0 to 30 */ /* (Trimming value 31 is forbidden). */ + /* Note: After dichotomy sweep, the trimming result is determined. */ + /* However, the final trimming step is deduced from previous */ + /* trimming steps tested but is not effectively tested. */ + /* An additional test step (using variable "final_step_check") */ + /* allow to Test the final trimming step. */ *opamp_trimmingvalue = 15; delta = 16; - while (delta != 0) + while ((delta != 0) || (final_step_check == 1)) { - /* Set candidate trimming */ - MODIFY_REG(*tmp_opamp_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser); + /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser); /* Offset trimming time: during calibration, minimum time needed */ /* between two steps to have 1 mV accuracy. */ HAL_Delay(OPAMP_TRIMMING_DELAY); + /* Set flag for additional check of last trimming step equal to */ + /* dichotomy step before its division by 2 (equivalent to previous */ + /* value of dichotomy step). */ + final_step_check = delta; + /* Divide range by 2 to continue dichotomy sweep */ delta >>= 1; /* Set trimming values for next iteration in function of trimming */ /* result toggle (versus initial state). */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp)) != tmp_Opaxcalout_DefaultSate) + /* Note: on the last trimming loop, delta is equal to 0 and */ + /* therefore has no effect. */ + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp)) != tmp_Opaxcalout_DefaultSate) { /* If calibration output is has toggled, try lower trimming */ *opamp_trimmingvalue -= delta; @@ -766,15 +829,32 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) /* If calibration output is has not toggled, try higher trimming */ *opamp_trimmingvalue += delta; } + + } + + /* Check trimming result of the selected step and perform final fine */ + /* trimming. */ + /* - If calibration output is has toggled: the current step is */ + /* already optimized. */ + /* - If calibration output is has not toggled: the current step can */ + /* be optimized by incrementing it of one step. */ + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp)) == tmp_Opaxcalout_DefaultSate) + { + *opamp_trimmingvalue += 1; + + /* Set final fine trimming */ + MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser); } } - + + /* Disable calibration for P and N differential pairs */ /* Disable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, (__OPAMP_CSR_OPAXCAL_H(hopamp) | - __OPAMP_CSR_OPAXCAL_L(hopamp) | - __OPAMP_CSR_OPAXPD(hopamp)) ); + CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H(hopamp) | + OPAMP_CSR_OPAXCAL_L(hopamp) | + OPAMP_CSR_OPAXPD(hopamp)) ); /* Backup of switches configuration to restore it at the end of the */ /* calibration. */ @@ -806,16 +886,77 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) hopamp->State = HAL_OPAMP_STATE_READY; } + else { /* OPAMP can not be calibrated from this mode */ status = HAL_ERROR; } } - + return status; } +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the OPAMP data + transfers. + + + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected opamp configuration. + * Caution: On STM32L1, HAL OPAMP lock is software lock only + * (not hardware lock as available on some other STM32 devices) + * @param hopamp: OPAMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + /* OPAMP can be locked when enabled and running in normal mode */ + /* It is meaningless otherwise */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ + || (hopamp->State == HAL_OPAMP_STATE_READY) \ + || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ + || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + + { + status = HAL_ERROR; + } + + else + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + /* OPAMP state changed to locked */ + hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED; + } + return status; +} + /** * @brief Return the OPAMP factory trimming value * Caution: On STM32L1 OPAMP, user can retrieve factory trimming if @@ -835,16 +976,16 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) * function after OPAMP init structure accordingly updated. * @retval Trimming value (P or N): range: 0->31 * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available - * @{ + * */ -OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) { - OPAMP_TrimmingValueTypeDef trimmingvalue; + HAL_OPAMP_TrimmingValueTypeDef trimmingvalue; __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) || (hopamp->State == HAL_OPAMP_STATE_BUSY) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) @@ -879,71 +1020,15 @@ OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, { tmp_opamp_reg_trimming = &OPAMP->LPOTR; } - + /* Get factory trimming */ - trimmingvalue = ((*tmp_opamp_reg_trimming >> __OPAMP_OFFSET_TRIM_BITSPOSITION(hopamp, trimmingoffset)) & OPAMP_TRIM_VALUE_MASK); - } + trimmingvalue = ((*tmp_opamp_reg_trimming >> OPAMP_OFFSET_TRIM_BITSPOSITION(hopamp, trimmingoffset)) & OPAMP_TRIM_VALUE_MASK); + } } return trimmingvalue; } -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - -@endverbatim - * @{ - */ - -/** - * @brief Lock the selected opamp configuration. - * Caution: On STM32L1, HAL OPAMP lock is software lock only (not - * hardware lock as on some other STM32 devices) - * @param hopamp: OPAMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - /* OPAMP can be locked when enabled and running in normal mode */ - /* It is meaningless otherwise */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ - || (hopamp->State == HAL_OPAMP_STATE_READY) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ - || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) - - { - status = HAL_ERROR; - } - - else - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - /* OPAMP state changed to locked */ - hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED; - } - return status; -} - /** * @} */ @@ -955,7 +1040,7 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp) @verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permit to get in run-time the status of the peripheral. @@ -971,7 +1056,7 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp) HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef* hopamp) { /* Check the OPAMP handle allocation */ - if(hopamp == HAL_NULL) + if(hopamp == NULL) { return HAL_OPAMP_STATE_RESET; } @@ -990,7 +1075,7 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef* hopamp) * @} */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */ #endif /* HAL_OPAMP_MODULE_ENABLED */ /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.h index 177ab8038a2..3a939d45e48 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_opamp.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of OPAMP HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" @@ -61,6 +61,7 @@ /** @defgroup OPAMP_Exported_Types OPAMP Exported Types * @{ */ + /** * @brief OPAMP Init structure definition */ @@ -70,12 +71,10 @@ typedef struct uint32_t PowerSupplyRange; /*!< Specifies the power supply range: above or under 2.4V. This parameter must be a value of @ref OPAMP_PowerSupplyRange Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */ - - uint32_t UserTrimming; /*!< Specifies the trimming mode - This parameter must be a value of @ref OPAMP_UserTrimming - UserTrimming is either factory or user trimming. - Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */ - + + uint32_t PowerMode; /*!< Specifies the power mode Normal or Low-Power. + This parameter must be a value of @ref OPAMP_PowerMode */ + uint32_t Mode; /*!< Specifies the OPAMP mode This parameter must be a value of @ref OPAMP_Mode mode is either Standalone or Follower */ @@ -87,28 +86,37 @@ typedef struct - In Follower mode: i.e when mode is OPAMP_FOLLOWER_MODE This parameter is Not Applicable */ - uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: - This parameter must be a value of @ref OPAMP_NonInvertingInput - NonInvertingInput is either VP0, VP1 or VP2 */ + uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: + This parameter must be a value of @ref OPAMP_NonInvertingInput + Note: Non-inverting input availability depends on OPAMP instance: + OPAMP1: Non-inverting input is either IO0, DAC_Channel1 + OPAMP2: Non-inverting input is either IO0, DAC_Channel1, DAC_Channel2 + OPAMP3: Non-inverting input is either IO0, DAC_Channel2 (OPAMP3 availability depends on STM32L1 devices) */ - uint32_t PowerMode; /*!< Specifies the power mode Normal or Low-Power. - This parameter must be a value of @ref OPAMP_PowerMode */ + uint32_t UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref OPAMP_UserTrimming + UserTrimming is either factory or user trimming. + Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */ uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) + 16 is typical default value */ + uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) + 16 is typical default value */ + uint32_t TrimmingValuePLowPower; /*!< Specifies the offset trimming value (PMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) + 16 is typical default value */ uint32_t TrimmingValueNLowPower; /*!< Specifies the offset trimming value (NMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) + 16 is typical default value */ }OPAMP_InitTypeDef; @@ -130,7 +138,7 @@ typedef enum }HAL_OPAMP_StateTypeDef; /** - * @brief OPAMP Handle Structure definition + * @brief OPAMP Handle Structure definition */ typedef struct { @@ -143,16 +151,17 @@ typedef struct } OPAMP_HandleTypeDef; /** - * @brief OPAMP_TrimmingValueTypeDef @brief definition + * @brief HAl_OPAMP_TrimmingValueTypeDef definition */ -typedef uint32_t OPAMP_TrimmingValueTypeDef; +typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants * @{ */ @@ -175,8 +184,6 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; #define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< OPAMP standalone mode */ #define OPAMP_FOLLOWER_MODE ((uint32_t)0x00000001) /*!< OPAMP follower mode */ -#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \ - ((INPUT) == OPAMP_FOLLOWER_MODE)) /** * @} */ @@ -184,13 +191,10 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_NonInvertingInput OPAMP NonInvertingInput * @{ */ -#define OPAMP_NONINVERTINGINPUT_VP0 ((uint32_t)0x00000000) /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */ -#define OPAMP_NONINVERTINGINPUT_DAC_CH1 ((uint32_t)0x00000001) /*!< Comparator non-inverting input connected internally to DAC channel 1 */ -#define OPAMP_NONINVERTINGINPUT_DAC_CH2 ((uint32_t)0x00000002) /*!< Comparator non-inverting input connected internally to DAC channel 2. Available on OPAMP2 only. */ +#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */ +#define OPAMP_NONINVERTINGINPUT_DAC_CH1 ((uint32_t)0x00000001) /*!< Comparator non-inverting input connected internally to DAC channel 1. Available only on OPAMP1 and OPAMP2. */ +#define OPAMP_NONINVERTINGINPUT_DAC_CH2 ((uint32_t)0x00000002) /*!< Comparator non-inverting input connected internally to DAC channel 2. Available only on OPAMP2 and OPAMP3 (OPAMP3 availability depends on STM32L1 devices). */ -#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_VP0) || \ - ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) || \ - ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2) ) /** * @} */ @@ -198,16 +202,10 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_InvertingInput OPAMP InvertingInput * @{ */ -#define OPAMP_INVERTINGINPUT_VM0 ((uint32_t)0x00000000) /*!< Comparator inverting input connected to dedicated IO pin low-leakage */ -#define OPAMP_INVERTINGINPUT_VM1 ((uint32_t)0x00000001) /*!< Comparator inverting input connected to alternative IO pin available on some device packages */ - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_INVERTINGINPUT_VM1 /*!< Alternate name for comparator inverting input connected to alternative IO pin available on some device packages */ +/* Note: Literal "OPAMP_SEC_INVERTINGINPUT_IO1" is a legacy naming of "OPAMP_INVERTINGINPUT_IO1". It is equivalent and must be replaced by "OPAMP_INVERTINGINPUT_IO1". */ +#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< Comparator inverting input connected to dedicated IO pin low-leakage */ +#define OPAMP_INVERTINGINPUT_IO1 ((uint32_t)0x00000001) /*!< Comparator inverting input connected to alternative IO pin available on some device packages */ -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_VM0 /* For compatibility with other STM32 devices */ -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_VM1 /* For compatibility with other STM32 devices */ - -#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_VM0) || \ - ((INPUT) == OPAMP_INVERTINGINPUT_VM1) ) /** * @} */ @@ -218,8 +216,6 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; #define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000) #define OPAMP_POWERMODE_LOWPOWER ((uint32_t)0x00000001) -#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \ - ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) ) /** * @} */ @@ -230,20 +226,16 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; #define OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000) /*!< Power supply range low (VDDA lower than 2.4V) */ #define OPAMP_POWERSUPPLY_HIGH OPAMP_CSR_AOP_RANGE /*!< Power supply range high (VDDA higher than 2.4V) */ -#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \ - ((RANGE) == OPAMP_POWERSUPPLY_HIGH) ) /** * @} */ -/** @defgroup OPAMP_UserTrimming OPAMP UserTrimming +/** @defgroup OPAMP_UserTrimming OPAMP User Trimming * @{ */ #define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ #define OPAMP_TRIMMING_USER OPAMP_OTR_OT_USER /*!< User trimming */ -#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \ - ((TRIMMING) == OPAMP_TRIMMING_USER)) /** * @} */ @@ -256,8 +248,6 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; #define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000000) /*!< Offset trimming P */ #define OPAMP_FACTORYTRIMMING_N POSITION_VAL(OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH) /*!< Offset trimming N */ -#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \ - ((TRIMMING) == OPAMP_FACTORYTRIMMING_P) ) /** * @} */ @@ -281,24 +271,22 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @} */ - /* Exported macros -----------------------------------------------------------*/ /** @defgroup OPAMP_Private_Macro OPAMP Private Macro * @{ */ - + /** @brief Reset OPAMP handle state * @param __HANDLE__: OPAMP handle. * @retval None */ #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET) - + /** * @} */ - /* Private macro -------------------------------------------------------------*/ /** @defgroup OPAMP_Private_Macro OPAMP Private Macro @@ -311,8 +299,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_OPAXPD(__HANDLE__) \ - (OPAMP_CSR_OPA1PD << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_OPAXPD(__HANDLE__) \ + (OPAMP_CSR_OPA1PD << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bit S3SELx (switch 3) corresponding to the @@ -320,8 +308,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_S3SELX(__HANDLE__) \ - (OPAMP_CSR_S3SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_S3SELX(__HANDLE__) \ + (OPAMP_CSR_S3SEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bit S4SELx (switch 4) corresponding to the @@ -329,8 +317,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_S4SELX(__HANDLE__) \ - (OPAMP_CSR_S4SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_S4SELX(__HANDLE__) \ + (OPAMP_CSR_S4SEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bit S5SELx (switch 5) corresponding to the @@ -338,8 +326,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_S5SELX(__HANDLE__) \ - (OPAMP_CSR_S5SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_S5SELX(__HANDLE__) \ + (OPAMP_CSR_S5SEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bit S3SELx (switch 6) corresponding to the @@ -347,8 +335,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_S6SELX(__HANDLE__) \ - (OPAMP_CSR_S6SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_S6SELX(__HANDLE__) \ + (OPAMP_CSR_S6SEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bit OPAxCAL_L (offset calibration for differential @@ -356,8 +344,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_OPAXCAL_L(__HANDLE__) \ - (OPAMP_CSR_OPA1CAL_L << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_OPAXCAL_L(__HANDLE__) \ + (OPAMP_CSR_OPA1CAL_L << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bit OPAxCAL_H (offset calibration for differential @@ -365,8 +353,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_OPAXCAL_H(__HANDLE__) \ - (OPAMP_CSR_OPA1CAL_H << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_OPAXCAL_H(__HANDLE__) \ + (OPAMP_CSR_OPA1CAL_H << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bit OPAxLPM (low power mode) corresponding to the @@ -374,8 +362,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_OPAXLPM(__HANDLE__) \ - (OPAMP_CSR_OPA1LPM << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) +#define OPAMP_CSR_OPAXLPM(__HANDLE__) \ + (OPAMP_CSR_OPA1LPM << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) /** * @brief Select the OPAMP bits of all switches corresponding to the @@ -383,19 +371,19 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_ALL_SWITCHES(__HANDLE__) \ +#define OPAMP_CSR_ALL_SWITCHES(__HANDLE__) \ ( ( ((__HANDLE__)->Instance != OPAMP2) \ )? \ ( \ - ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ + ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ | \ - (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) \ + (OPAMP_CSR_ANAWSEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__))) \ ) \ : \ ( \ - ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ + ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ | \ - (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) \ + (OPAMP_CSR_ANAWSEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__))) \ | \ (OPAMP_CSR_S7SEL2) \ ) \ @@ -407,8 +395,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_ANAWSELX(__HANDLE__) \ - (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) +#define OPAMP_CSR_ANAWSELX(__HANDLE__) \ + (OPAMP_CSR_ANAWSEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__))) /** * @brief Select the OPAMP bit OPAxCALOUT in function of the selected @@ -416,8 +404,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle * @retval None */ -#define __OPAMP_CSR_OPAXCALOUT(__HANDLE__) \ - (OPAMP_CSR_OPA1CALOUT << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) +#define OPAMP_CSR_OPAXCALOUT(__HANDLE__) \ + (OPAMP_CSR_OPA1CALOUT << (OPAMP_INSTANCE_DECIMAL(__HANDLE__))) /** * @brief Select the OPAMP trimming bits position value (position of LSB) @@ -429,8 +417,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * Must be a value of @ref OPAMP_FactoryTrimming. * @retval None */ -#define __OPAMP_OFFSET_TRIM_BITSPOSITION(__HANDLE__, __TRIM_HIGH_LOW__) \ - ((__OPAMP_INSTANCE_DECIMAL__((__HANDLE__)) * OPAMP_OTR_INSTANCE_OFFSET) + (__TRIM_HIGH_LOW__)) +#define OPAMP_OFFSET_TRIM_BITSPOSITION(__HANDLE__, __TRIM_HIGH_LOW__) \ + ((OPAMP_INSTANCE_DECIMAL((__HANDLE__)) * OPAMP_OTR_INSTANCE_OFFSET) + (__TRIM_HIGH_LOW__)) /** * @brief Shift the OPAMP trimming bits to register OPAMP_OTR or register @@ -442,8 +430,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @param __TRIMMING_VALUE__: Trimming value * @retval None */ -#define __OPAMP_OFFSET_TRIM_SET(__HANDLE__, __TRIM_HIGH_LOW__, __TRIMMING_VALUE__) \ - ((__TRIMMING_VALUE__) << (__OPAMP_OFFSET_TRIM_BITSPOSITION((__HANDLE__), (__TRIM_HIGH_LOW__)))) +#define OPAMP_OFFSET_TRIM_SET(__HANDLE__, __TRIM_HIGH_LOW__, __TRIMMING_VALUE__) \ + ((__TRIMMING_VALUE__) << (OPAMP_OFFSET_TRIM_BITSPOSITION((__HANDLE__), (__TRIM_HIGH_LOW__)))) /** * @brief Check that trimming value is within correct range @@ -452,19 +440,36 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; */ #define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1E) +#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \ + ((INPUT) == OPAMP_FOLLOWER_MODE)) + +#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ + ((INPUT) == OPAMP_INVERTINGINPUT_IO1) ) + +#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \ + ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) ) + +#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \ + ((RANGE) == OPAMP_POWERSUPPLY_HIGH) ) + +#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \ + ((TRIMMING) == OPAMP_TRIMMING_USER)) + +#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \ + ((TRIMMING) == OPAMP_FACTORYTRIMMING_P) ) + /** * @} */ - + /* Include OPAMP HAL Extension module */ #include "stm32l1xx_hal_opamp_ex.h" /* Exported functions --------------------------------------------------------*/ - /** @addtogroup OPAMP_Exported_Functions * @{ - */ + */ /** @addtogroup OPAMP_Exported_Functions_Group1 * @{ @@ -481,11 +486,11 @@ void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp); /** @addtogroup OPAMP_Exported_Functions_Group2 * @{ */ + /* I/O operation functions *****************************************************/ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp); HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp); HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); -OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** * @} */ @@ -493,8 +498,10 @@ OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, /** @addtogroup OPAMP_Exported_Functions_Group3 * @{ */ + /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** * @} */ @@ -502,18 +509,17 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); /** @addtogroup OPAMP_Exported_Functions_Group4 * @{ */ + /* Peripheral State functions **************************************************/ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); + /** * @} */ /** * @} - */ - - - + */ /** * @} @@ -523,7 +529,7 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); * @} */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */ #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c index 2b975c01cd3..076d03987c8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c @@ -2,20 +2,20 @@ ****************************************************************************** * @file stm32l1xx_hal_opamp_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Extended OPAMP HAL module driver. * * This file provides firmware functions to manage the following - * functionalities of the Power Controller (OPAMP) peripheral: + * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) + * peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions * - @verbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -45,6 +45,10 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" +#ifdef HAL_OPAMP_MODULE_ENABLED + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) + /** @addtogroup STM32L1xx_HAL_Driver * @{ */ @@ -54,17 +58,13 @@ * @{ */ -#ifdef HAL_OPAMP_MODULE_ENABLED - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ + /** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions * @{ */ @@ -134,15 +134,15 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA uint32_t tmp_OpaxSwitchesContextBackup = 0; - uint8_t trimming_diff_pair_iteration_count = 0; - uint8_t delta = 0; - + uint8_t trimming_diff_pair_iteration_count = 0; /* For calibration loop algorithm: to repeat the calibration loop for both differential transistors pair high and low */ + uint8_t delta = 0; /* For calibration loop algorithm: Variable for dichotomy steps value */ + uint8_t final_step_check = 0; /* For calibration loop algorithm: Flag for additional check of last trimming step */ /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp1 == HAL_NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || - (hopamp2 == HAL_NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || - (hopamp3 == HAL_NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) ) + if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || + (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || + (hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) ) { status = HAL_ERROR; } @@ -246,9 +246,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1); - tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2); - tmp_Opa3calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp3); + tmp_Opa1calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp1); + tmp_Opa2calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp2); + tmp_Opa3calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp3); /* Enable calibration for P differential pair */ MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, @@ -262,29 +262,37 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* can extend the search range to +/- 15 units. */ /* - Trimming initial value 15: search range will go from 0 to 30 */ /* (Trimming value 31 is forbidden). */ + /* Note: After dichotomy sweep, the trimming result is determined. */ + /* However, the final trimming step is deduced from previous */ + /* trimming steps tested but is not effectively tested. */ + /* An additional test step (using variable "final_step_check") */ + /* allow to Test the final trimming step. */ *opamp1_trimmingvalue = 15; *opamp2_trimmingvalue = 15; *opamp3_trimmingvalue = 15; delta = 16; - while (delta != 0) + while ((delta != 0) || (final_step_check == 1)) { /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); - MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); - - MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); - - MODIFY_REG(*tmp_opamp3_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser); + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); + MODIFY_REG(*tmp_opamp3_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser); /* Offset trimming time: during calibration, minimum time needed */ /* between two steps to have 1 mV accuracy. */ HAL_Delay(OPAMP_TRIMMING_DELAY); + /* Set flag for additional check of last trimming step equal to */ + /* dichotomy step before its division by 2 (equivalent to previous */ + /* value of dichotomy step). */ + final_step_check = delta; + /* Divide range by 2 to continue dichotomy sweep */ delta >>= 1; @@ -292,7 +300,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* result toggle (versus initial state). */ /* Trimming values update with dichotomy delta of previous */ /* iteration. */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) + /* Note: on the last trimming loop, delta is equal to 0 and */ + /* therefore has no effect. */ + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) { /* If calibration output is has toggled, try lower trimming */ *opamp1_trimmingvalue -= delta; @@ -303,11 +313,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA *opamp1_trimmingvalue += delta; } - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - /* Trimming values update with dichotomy delta of previous */ - /* iteration. */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) { /* If calibration output is has toggled, try lower trimming */ *opamp2_trimmingvalue -= delta; @@ -317,12 +323,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* If calibration output is has not toggled, try higher trimming */ *opamp2_trimmingvalue += delta; } - - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - /* Trimming values update with dichotomy delta of previous */ - /* iteration. */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp3)) != tmp_Opa3calout_DefaultSate) + + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp3)) != tmp_Opa3calout_DefaultSate) { /* If calibration output is has toggled, try lower trimming */ *opamp3_trimmingvalue -= delta; @@ -332,8 +334,39 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* If calibration output is has not toggled, try higher trimming */ *opamp3_trimmingvalue += delta; } + } + + /* Check trimming result of the selected step and perform final fine */ + /* trimming. */ + /* - If calibration output is has toggled: the current step is */ + /* already optimized. */ + /* - If calibration output is has not toggled: the current step can */ + /* be optimized by incrementing it of one step. */ + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) == tmp_Opa1calout_DefaultSate) + { + *opamp1_trimmingvalue += 1; + /* Set final fine trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); } + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) == tmp_Opa2calout_DefaultSate) + { + *opamp2_trimmingvalue += 1; + + /* Set final fine trimming */ + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); + } + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp3)) == tmp_Opa3calout_DefaultSate) + { + *opamp3_trimmingvalue += 1; + + /* Set final fine trimming */ + MODIFY_REG(*tmp_opamp3_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser); + } + } @@ -460,14 +493,14 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA uint32_t tmp_OpaxSwitchesContextBackup = 0; - uint8_t trimming_diff_pair_iteration_count = 0; - uint8_t delta = 0; - + uint8_t trimming_diff_pair_iteration_count = 0; /* For calibration loop algorithm: to repeat the calibration loop for both differential transistors pair high and low */ + uint8_t delta = 0; /* For calibration loop algorithm: Variable for dichotomy steps value */ + uint8_t final_step_check = 0; /* For calibration loop algorithm: Flag for additional check of last trimming step */ /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp1 == HAL_NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || - (hopamp2 == HAL_NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) ) + if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || + (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) ) { status = HAL_ERROR; } @@ -553,8 +586,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1); - tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2); + tmp_Opa1calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp1); + tmp_Opa2calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp2); /* Enable calibration for P differential pair */ MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, @@ -568,31 +601,44 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* can extend the search range to +/- 15 units. */ /* - Trimming initial value 15: search range will go from 0 to 30 */ /* (Trimming value 31 is forbidden). */ + /* Note: After dichotomy sweep, the trimming result is determined. */ + /* However, the final trimming step is deduced from previous */ + /* trimming steps tested but is not effectively tested. */ + /* An additional test step (using variable "final_step_check") */ + /* allow to Test the final trimming step. */ *opamp1_trimmingvalue = 15; *opamp2_trimmingvalue = 15; delta = 16; - while (delta != 0) + while ((delta != 0) || (final_step_check == 1)) { /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); - MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); - - MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); /* Offset trimming time: during calibration, minimum time needed */ /* between two steps to have 1 mV accuracy. */ HAL_Delay(OPAMP_TRIMMING_DELAY); + /* Set flag for additional check of last trimming step equal to */ + /* dichotomy step before its division by 2 (equivalent to previous */ + /* value of dichotomy step). */ + final_step_check = delta; + /* Divide range by 2 to continue dichotomy sweep */ delta >>= 1; /* Set trimming values for next iteration in function of trimming */ /* result toggle (versus initial state). */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) + /* Trimming values update with dichotomy delta of previous */ + /* iteration. */ + /* Note: on the last trimming loop, delta is equal to 0 and */ + /* therefore has no effect. */ + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) { /* If calibration output is has toggled, try lower trimming */ *opamp1_trimmingvalue -= delta; @@ -603,9 +649,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA *opamp1_trimmingvalue += delta; } - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) { /* If calibration output is has toggled, try lower trimming */ *opamp2_trimmingvalue -= delta; @@ -615,8 +659,32 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* If calibration output is has not toggled, try higher trimming */ *opamp2_trimmingvalue += delta; } + } + + /* Check trimming result of the selected step and perform final fine */ + /* trimming. */ + /* - If calibration output is has toggled: the current step is */ + /* already optimized. */ + /* - If calibration output is has not toggled: the current step can */ + /* be optimized by incrementing it of one step. */ + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) == tmp_Opa1calout_DefaultSate) + { + *opamp1_trimmingvalue += 1; + /* Set final fine trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); } + if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) == tmp_Opa2calout_DefaultSate) + { + *opamp2_trimmingvalue += 1; + + /* Set final fine trimming */ + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); + + } + } @@ -690,7 +758,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA */ /** @defgroup OPAMPEx_Exported_Functions_Group2 Extended Peripheral Control functions - * @brief Extended control functions + * @brief Extended peripheral control functions * @verbatim =============================================================================== @@ -715,7 +783,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp) /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) || (hopamp->State == HAL_OPAMP_STATE_READY) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) || (hopamp->State == HAL_OPAMP_STATE_BUSY)) @@ -738,12 +806,11 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp) * @} */ - /** * @} */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */ #endif /* HAL_OPAMP_MODULE_ENABLED */ /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h index 135ebcc99c0..397a4c5678b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_opamp_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of OPAMP HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" @@ -55,9 +55,6 @@ /** @addtogroup OPAMPEx * @{ */ - - - /* Exported types ------------------------------------------------------------*/ /* Exported constants ---------------------------------------------------------*/ /** @defgroup OPAMPEx_Exported_Constants OPAMPEx Exported Constants @@ -142,7 +139,7 @@ * @param __HANDLE__: OPAMP handle * @retval "0" for OPAMP1, "1" for OPAMP2, "2" for OPAMP3 */ -#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__) \ +#define OPAMP_INSTANCE_DECIMAL(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == OPAMP1) \ )? \ ((uint32_t)0) \ @@ -161,7 +158,7 @@ * @param __HANDLE__: OPAMP handle * @retval "0" for OPAMP1, "1" for OPAMP2 */ -#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__) \ +#define OPAMP_INSTANCE_DECIMAL(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == OPAMP1) \ )? \ ((uint32_t)0) \ @@ -170,6 +167,59 @@ ) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/** + * @brief Check OPAMP non-inverting input in function of OPAMPx instance + * @param __HANDLE__: OPAMP handle + * @param INPUT: OPAMP non-inverting input + * @retval None + */ +#define IS_OPAMP_NONINVERTING_INPUT_CHECK_INSTANCE(__HANDLE__, INPUT) \ + ( ( ((__HANDLE__)->Instance == OPAMP1) \ + )? \ + ( \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) \ + ) \ + : \ + ( ( ((__HANDLE__)->Instance == OPAMP2) \ + )? \ + ( \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2) \ + ) \ + : \ + ( \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2) \ + ) \ + ) \ + ) +#else +/** + * @brief Check OPAMP non-inverting input in function of OPAMPx instance + * @param __HANDLE__: OPAMP handle + * @param INPUT: OPAMP non-inverting input + * @retval None + */ +#define IS_OPAMP_NONINVERTING_INPUT_CHECK_INSTANCE(__HANDLE__, INPUT) \ + ( ( ((__HANDLE__)->Instance == OPAMP1) \ + )? \ + ( \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) \ + ) \ + : \ + ( \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2) \ + ) \ + ) +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + /** * @} */ @@ -180,7 +230,7 @@ */ /* I/O operation functions *****************************************************/ -/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended IO operation functions +/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions * @{ */ #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) @@ -196,7 +246,6 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA * @{ */ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); - /** * @} */ @@ -213,7 +262,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); * @} */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */ #ifdef __cplusplus } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.c index 33596aedecc..50217dc4b8d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_pcd.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -28,7 +28,7 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using - (+++) __USB_CLK_ENABLE); + (+++) __HAL_RCC_USB_CLK_ENABLE); (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -44,7 +44,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -87,7 +87,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Constants PCD Private Constants + +/** @defgroup PCD_Private_Define PCD Private Define * @{ */ #define BTABLE_ADDRESS (0x000) @@ -109,6 +110,7 @@ static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufA * @} */ +/* Exported functions ---------------------------------------------------------*/ /** @defgroup PCD_Exported_Functions PCD Exported Functions * @{ @@ -140,7 +142,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) uint32_t wInterrupt_Mask = 0; /* Check the PCD handle allocation */ - if(hpcd == HAL_NULL) + if(hpcd == NULL) { return HAL_ERROR; } @@ -148,10 +150,16 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - hpcd->State = PCD_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); + if(hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + } + + hpcd->State = HAL_PCD_STATE_BUSY; /* Init endpoints structures */ for (i = 0; i < hpcd->Init.dev_endpoints ; i++) @@ -198,7 +206,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->Instance->CNTR = wInterrupt_Mask; hpcd->USB_Address = 0; - hpcd->State= PCD_READY; + hpcd->State= HAL_PCD_STATE_READY; return HAL_OK; } @@ -211,12 +219,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) { /* Check the PCD handle allocation */ - if(hpcd == HAL_NULL) + if(hpcd == NULL) { return HAL_ERROR; } - hpcd->State = PCD_BUSY; + hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ HAL_PCD_Stop(hpcd); @@ -224,7 +232,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /* DeInit the low level hardware */ HAL_PCD_MspDeInit(hpcd); - hpcd->State = PCD_READY; + hpcd->State = HAL_PCD_STATE_RESET; return HAL_OK; } @@ -236,8 +244,11 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implenetd in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file */ } @@ -248,8 +259,11 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implenetd in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file */ } @@ -273,18 +287,19 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) */ /** - * @brief Start The USB OTG Device. + * @brief Start the USB device. * @param hpcd: PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { HAL_PCDEx_SetConnectionState (hpcd, 1); + return HAL_OK; } /** - * @brief Stop The USB OTG Device. + * @brief Stop the USB device. * @param hpcd: PCD handle * @retval HAL status */ @@ -304,287 +319,597 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) __HAL_UNLOCK(hpcd); return HAL_OK; } - -/** - * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - uint32_t wInterrupt_Mask = 0; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) - { - /* servicing of the endpoint correct transfer interrupt */ - /* clear of the CTR flag into the sub */ - PCD_EP_ISR_Handler(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); - HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVRM)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVRM); - } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { - hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE); - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - - /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); - HAL_PCD_SOFCallback(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) - { - /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); - } -} - -/** - * @brief Data out stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implenetd in the user file - */ -} - -/** - * @brief Data IN stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implenetd in the user file - */ -} -/** - * @brief Setup stage callback - * @param hpcd: ppp handle - * @retval None - */ - __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implenetd in the user file - */ -} - -/** - * @brief USB Start Of Frame callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implenetd in the user file - */ -} - -/** - * @brief USB Reset callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implenetd in the user file - */ -} - - -/** - * @brief Suspend event callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implenetd in the user file - */ -} - -/** - * @brief Resume event callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implenetd in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implenetd in the user file - */ -} - -/** - * @brief Incomplete ISO IN callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implenetd in the user file - */ -} - -/** - * @brief Connection event callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implenetd in the user file - */ -} - /** - * @brief Disconnection event callbacks - * @param hpcd: ppp handle - * @retval None + * @} */ - __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implenetd in the user file - */ -} /** * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. + */ -@endverbatim +/** @addtogroup PCD_Private_Functions PCD Private Functions * @{ */ - -/** - * @brief Connect the USB device - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - HAL_PCDEx_SetConnectionState (hpcd, 1); - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - /** - * @brief Disconnect the USB device + * @brief This function handles PCD Endpoint interrupt request. * @param hpcd: PCD handle * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { - __HAL_LOCK(hpcd); - - /* Disable DP Pull-Down bit*/ - HAL_PCDEx_SetConnectionState (hpcd, 0); + PCD_EPTypeDef *ep; + uint16_t count=0; + uint8_t EPindex; + __IO uint16_t wIstr; + __IO uint16_t wEPVal = 0; - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Set the USB Device address - * @param hpcd: PCD handle - * @param address: new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - - if(address == 0) - { - /* set device address and enable function */ - hpcd->Instance->DADDR = USB_DADDR_EF; - } - else /* USB Address will be applied later */ - { - hpcd->USB_Address = address; + /* stay in loop while pending interrupts */ + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (EPindex == 0) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, 0); + + + if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) + { + hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0; + } + + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0) + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ + HAL_PCD_SetupStageCallback(hpcd); + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + ep->xfer_buff+=ep->xfer_count; + } + + /* Process Control Data OUT Packet*/ + HAL_PCD_DataOutStageCallback(hpcd, 0); + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + } + } + else + { + + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); + if ((wEPVal & USB_EP_CTR_RX) != 0) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); + ep = &hpcd->OUT_ep[EPindex]; + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0) + { + count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + { + /*read from endpoint BUF0Addr buffer*/ + count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count+=count; + ep->xfer_buff+=count; + + if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ + HAL_PCD_DataOutStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0) + { + ep = &hpcd->IN_ep[EPindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); + + /* IN double Buffering*/ + if (ep->doublebuffer == 0) + { + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) + { + /*read from endpoint BUF0Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + } + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff+=ep->xfer_count; + + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx = pointer to USB register. + * @param pbUsrBuf: pointer to user memory area. + * @param wPMABufAddr: address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ + uint32_t i, temp1, temp2; + uint16_t *pdwVal; + pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); + for (i = n; i != 0; i--) + { + temp1 = (uint16_t) * pbUsrBuf; + pbUsrBuf++; + temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + *pdwVal++ = temp2; + pdwVal++; + pbUsrBuf++; + } +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx = pointer to USB register. + * @param pbUsrBuf = pointer to user memory area. + * @param wPMABufAddr: address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1;/* /2*/ + uint32_t i; + uint32_t *pdwVal; + pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); + for (i = n; i != 0; i--) + { + *(uint16_t*)pbUsrBuf++ = *pdwVal++; + pbUsrBuf++; + } +} + +/** + * @} + */ + +/** @addtogroup PCD_Exported_Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/** + * @brief This function handles PCD interrupt request. + * @param hpcd: PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + uint32_t wInterrupt_Mask = 0; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + PCD_EP_ISR_Handler(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + HAL_PCD_ResetCallback(hpcd); + HAL_PCD_SetAddress(hpcd, 0); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + } + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) + { + hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + HAL_PCD_ResumeCallback(hpcd); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) + { + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= USB_CNTR_LPMODE; + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + { + HAL_PCD_SuspendCallback(hpcd); + } + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + HAL_PCD_SOFCallback(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + } +} + +/** + * @brief Data out stage callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + + +/** + * @brief Suspend event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + HAL_PCDEx_SetConnectionState (hpcd, 1); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Disconnect the USB device + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Disable DP Pull-Down bit*/ + HAL_PCDEx_SetConnectionState (hpcd, 0); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Set the USB Device address + * @param hpcd: PCD handle + * @param address: new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + + if(address == 0) + { + /* set device address and enable function */ + hpcd->Instance->DADDR = USB_DADDR_EF; + } + else /* USB Address will be applied later */ + { + hpcd->USB_Address = address; } __HAL_UNLOCK(hpcd); @@ -594,7 +919,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @brief Open and configure an endpoint * @param hpcd: PCD handle * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packert size + * @param ep_mps: endpoint max packet size * @param ep_type: endpoint type * @retval HAL status */ @@ -814,7 +1139,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u else { /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len); } PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); @@ -878,8 +1203,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } else { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + /*Set the Double buffer counter */ + PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len); /*Write the data to the USB endpoint*/ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) @@ -890,6 +1215,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { pmabuffer = ep->pmaaddr0; } + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in); } @@ -931,408 +1257,152 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /* This macro sets STALL status for RX & TX*/ PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); } - else - { - if (ep->is_in) - { - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL); - } - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); - } - else - { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Flush an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return HAL_OK; -} - -/** - * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling - * @param hpcd: PCD handle - * @retval status - */ -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - hpcd->Instance->CNTR |= USB_CNTR_RESUME; - return HAL_OK; -} - -/** - * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling - * @param hpcd: PCD handle - * @retval status - */ -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - - -/** - * @brief Return the PCD state - * @param hpcd : PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) -{ - return hpcd->State; -} - - -/** - * @brief Software Device Connection - * @param hpcd: PCD handle - * @param state: Device state - * @retval None - */ - __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCDEx_SetConnectionState could be implenetd in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup PCD_Private_Functions - * @{ - */ - - -/** - * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) -{ - PCD_EPTypeDef *ep; - uint16_t count=0; - uint8_t EPindex; - __IO uint16_t wIstr; - __IO uint16_t wEPVal = 0; - - /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) - { - /* extract highest priority endpoint number */ - EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (EPindex == 0) - { - /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - ep = &hpcd->IN_ep[0]; - - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); - - - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) - { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; - } - - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0) - { - /* Get SETUP Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Process SETUP Packet*/ - HAL_PCD_SetupStageCallback(hpcd); - } - - else if ((wEPVal & USB_EP_CTR_RX) != 0) - { - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; - } - - /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); - - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); - } - } + else + { + if (ep->is_in) + { + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); } else { - - /* Decode and service non control endpoints interrupt */ - - /* process related endpoint register */ - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) - { - /* clear int flag */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); - ep = &hpcd->OUT_ep[EPindex]; - - /* OUT double Buffering*/ - if (ep->doublebuffer == 0) - { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) - { - /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); - } - /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) - { - /* RX COMPLETE */ - HAL_PCD_DataOutStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - - } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0) - { - ep = &hpcd->IN_ep[EPindex]; - - /* clear int flag */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); - } - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - } + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL); } } + __HAL_UNLOCK(hpcd); + return HAL_OK; } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx = pointer to USB register. - * @param pbUsrBuf: pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. - * @retval None + * @brief Clear a STALL condition over in an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status */ -static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ - uint32_t i, temp1, temp2; - uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) + PCD_EPTypeDef *ep; + + if ((0x80 & ep_addr) == 0x80) { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; - *pdwVal++ = temp2; - pdwVal++; - pbUsrBuf++; + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 0; + ep->num = ep_addr & 0x7F; + ep->is_in = ((ep_addr & 0x80) == 0x80); + + __HAL_LOCK(hpcd); + + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); } + __HAL_UNLOCK(hpcd); + + return HAL_OK; } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx = pointer to USB register. - * @param pbUsrBuf = pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @brief Flush an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return HAL_OK; +} + +/** + * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + hpcd->Instance->CNTR |= USB_CNTR_RESUME; + return HAL_OK; +} + +/** + * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + + +/** + * @brief Return the PCD state + * @param hpcd : PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} + + +/** + * @brief Software Device Connection + * @param hpcd: PCD handle + * @param state: Device state * @retval None */ -static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) + __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) { - uint32_t n = (wNBytes + 1) >> 1;/* /2*/ - uint32_t i; - uint32_t *pdwVal; - pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) - { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; - pbUsrBuf++; - } + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_SetConnectionState could be implenetd in the user file + */ } /** * @} */ +/** + * @} + */ + + #endif /* HAL_PCD_MODULE_ENABLED */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.h index f014e3d79b5..8a10d78f4ab 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -60,25 +60,30 @@ */ /** - * @brief PCD State structures definition + * @brief PCD State structure definition */ typedef enum { - PCD_READY = 0x00, - PCD_ERROR = 0x01, - PCD_BUSY = 0x02, - PCD_TIMEOUT = 0x03 + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 } PCD_StateTypeDef; +/** + * @brief PCD double buffered endpoint direction + */ typedef enum { - /* double buffered endpoint direction */ PCD_EP_DBUF_OUT, PCD_EP_DBUF_IN, PCD_EP_DBUF_ERR, }PCD_EP_DBUF_DIR; -/* endpoint buffer number */ +/** + * @brief PCD endpoint buffer number + */ typedef enum { PCD_EP_NOBUF, @@ -96,21 +101,25 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ + This parameter can be any value of @ref PCD_Core_Speed */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS */ + This parameter can be any value of @ref PCD_EP0_MPS */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ + This parameter can be any value of @ref PCD_Core_PHY */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. + This parameter can be set to ENABLE or DISABLE */ - uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ + uint32_t low_power_enable; /*!< Enable or disable Low Power mode + This parameter can be set to ENABLE or DISABLE */ - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ + uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ }PCD_InitTypeDef; @@ -126,7 +135,7 @@ typedef struct This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type */ + This parameter can be any value of @ref PCD_EP_Type */ uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ @@ -178,23 +187,24 @@ typedef struct * @} */ +/* Include PCD HAL Extension module */ #include "stm32l1xx_hal_pcd_ex.h" /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ -/** @defgroup USB_Exti_Line_Wakeup USB_Exti_Line_Wakeup +/** @defgroup PCD_Exti_Line_Wakeup PCD_Exti_Line_Wakeup * @{ */ -#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ /** * @} */ -/** @defgroup USB_Core_Speed USB Core Speed +/** @defgroup PCD_Core_Speed PCD Core Speed * @{ */ #define PCD_SPEED_HIGH 0 /* Not Supported */ @@ -203,7 +213,7 @@ typedef struct * @} */ - /** @defgroup USB_Core_PHY USB Core PHY + /** @defgroup PCD_Core_PHY PCD Core PHY * @{ */ #define PCD_PHY_EMBEDDED 2 @@ -211,7 +221,7 @@ typedef struct * @} */ -/** @defgroup USB_EP0_MPS USB EP0 MPS +/** @defgroup PCD_EP0_MPS PCD EP0 MPS * @{ */ #define DEP0CTL_MPS_64 0 @@ -227,7 +237,7 @@ typedef struct * @} */ -/** @defgroup USB_EP_Type USB EP Type +/** @defgroup PCD_EP_Type PCD EP Type * @{ */ #define PCD_EP_TYPE_CTRL 0 @@ -238,7 +248,7 @@ typedef struct * @} */ -/** @defgroup USB_ENDP_Type USB_ENDP_Type +/** @defgroup PCD_ENDP PCD ENDP * @{ */ @@ -251,21 +261,25 @@ typedef struct #define PCD_ENDP6 ((uint8_t)6) #define PCD_ENDP7 ((uint8_t)7) -/* Endpoint Kind */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 - -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE +#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE /** * @} */ - +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind + * @{ + */ +#define PCD_SNG_BUF 0 +#define PCD_DBL_BUF 1 /** * @} */ +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros @@ -275,23 +289,32 @@ typedef struct #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) -#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP -#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP) -#define __HAL_USB_EXTI_GET_FLAG() EXTI->PR & (USB_EXTI_LINE_WAKEUP) -#define __HAL_USB_EXTI_CLEAR_FLAG() EXTI->PR = USB_EXTI_LINE_WAKEUP +#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE +#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\ - EXTI->RTSR |= USB_EXTI_LINE_WAKEUP +#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do{ \ + EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \ + } while(0) -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (USB_EXTI_LINE_WAKEUP);\ - EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP) +#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \ + do{ \ + EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE); \ + EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \ + } while(0) -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\ - EXTI->RTSR |= USB_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= USB_EXTI_LINE_WAKEUP +#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do{ \ + EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \ + EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \ + EXTI->FTSR |= USB_WAKEUP_EXTI_LINE; \ + } while(0) /** * @} @@ -627,7 +650,7 @@ typedef struct }/* PCD_SET_EP_CNT_RX_REG */ #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ + uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ } /** @@ -706,7 +729,7 @@ typedef struct } \ else if((bDir) == PCD_EP_DBUF_IN)\ {/* IN endpoint */ \ - *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ } \ } /* SetEPDblBuf1Count */ @@ -792,8 +815,8 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c index 2d4f654e1e7..21d2f86039b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,15 +65,20 @@ * @{ */ -/* -@verbatim - =============================================================================== - ##### Peripheral extended features functions ##### +/** @defgroup PCDEx_Exported_Functions_Group2 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure PMA for the EndPoint + @endverbatim * @{ */ - + /** * @brief Configure PMA for EP * @param hpcd : Device instance @@ -129,7 +134,9 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, return HAL_OK; } - +/** + * @} + */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h index 408752c1fa1..9d53dcb535a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h @@ -1,14 +1,14 @@ /** ****************************************************************************** - * @file stm32l1xx_hal_pcd.h + * @file stm32l1xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -62,6 +62,11 @@ /** @addtogroup PCDEx_Exported_Functions * @{ */ + +/** @addtogroup PCDEx_Exported_Functions_Group2 + * @{ + */ + HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, @@ -70,7 +75,10 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, * @} */ - +/** + * @} + */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.c index 87cd0f6a45c..aae0e3b7e93 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_pwr.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief PWR HAL module driver. * * This file provides firmware functions to manage the following @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -84,7 +84,7 @@ write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() macro. + __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. @endverbatim @@ -102,8 +102,8 @@ */ void HAL_PWR_DeInit(void) { - __PWR_FORCE_RESET(); - __PWR_RELEASE_RESET(); + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); } /** @@ -157,7 +157,7 @@ void HAL_PWR_DisableBkUpAccess(void) (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through - __HAL_PVD_EXTI_ENABLE_IT() macro. + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. *** WakeUp pin configuration *** @@ -354,7 +354,7 @@ void HAL_PWR_DisableBkUpAccess(void) * detection level. * @retval None */ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); @@ -366,7 +366,7 @@ void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE(); /* Configure interrupt mode */ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) @@ -383,12 +383,12 @@ void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { - __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER(); + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { - __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER(); + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } } @@ -563,6 +563,62 @@ void HAL_PWR_EnterSTANDBYMode(void) __WFI(); } + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enables CORTEX M3 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M3 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + + /** * @brief This function handles the PWR PVD interrupt request. * @note This API should be called under the PVD_IRQHandler(). diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.h index 3ee00bc99b1..4418a39bb02 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_pwr.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -75,6 +75,19 @@ typedef struct /** * @} */ + +/* Internal constants --------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +/** + * @} + */ + + /* Exported constants --------------------------------------------------------*/ @@ -149,10 +162,7 @@ typedef struct #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage (Compare internally to VREFINT) */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + /** * @} */ @@ -168,12 +178,8 @@ typedef struct #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) -/** - * @} + /** + * @} */ /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode @@ -182,8 +188,6 @@ typedef struct #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) /** * @} */ @@ -193,7 +197,7 @@ typedef struct */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + /** * @} */ @@ -203,7 +207,7 @@ typedef struct */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01) #define PWR_STOPENTRY_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) + /** * @} */ @@ -216,9 +220,7 @@ typedef struct #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) + /** * @} */ @@ -242,7 +244,7 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro PWR Exported Macro +/** @defgroup PWR_Exported_Macros PWR Exported Macros * @{ */ @@ -295,52 +297,80 @@ typedef struct * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2) - -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) /** * @brief Enable interrupt on PVD Exti Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** * @brief Disable interrupt on PVD Exti Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** * @brief Enable event on PVD Exti Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) /** * @brief Disable event on PVD Exti Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + /** - * @brief PVD EXTI line configuration: clear falling edge trigger and set rising edge. + * @brief PVD EXTI line configuration: set falling edge trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \ - EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + /** - * @brief PVD EXTI line configuration: set falling edge trigger. + * @brief Disable the PVD Extended Interrupt Falling Trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + /** * @brief PVD EXTI line configuration: set rising edge trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + + /** * @brief Check whether the specified PVD EXTI interrupt flag is set or not. @@ -358,11 +388,47 @@ typedef struct * @brief Generate a Software interrupt on selected EXTI line. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) + /** * @} */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) + +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) + + +/** + * @} + */ + + + /* Include PWR HAL Extension module */ #include "stm32l1xx_hal_pwr_ex.h" @@ -390,7 +456,7 @@ void HAL_PWR_DisableBkUpAccess(void); */ /* Peripheral Control functions ************************************************/ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); @@ -403,6 +469,13 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSTANDBYMode(void); +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + + + void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVDCallback(void); /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c index 93d5a720f60..fc1a08092a3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -77,6 +77,16 @@ * @{ */ +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR & PWR_CR_VOS); +} + + /** * @brief Enables the Fast WakeUp from Ultra Low Power mode. * @note This bit works in conjunction with ULP bit. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h index 6be71efab49..3f3370c3037 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ */ -/** @defgroup PWR_WakeUp_Pins PWREx Wakeup Pins +/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins * @{ */ -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 @@ -102,6 +102,7 @@ */ /* Peripheral Control methods ************************************************/ +uint32_t HAL_PWREx_GetVoltageRange(void); void HAL_PWREx_EnableFastWakeUp(void); void HAL_PWREx_DisableFastWakeUp(void); void HAL_PWREx_EnableUltraLowPower(void); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.c index d5fc7df63ff..5e5e90a03ed 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_rcc.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -18,8 +18,8 @@ After reset the device is running from multispeed internal oscillator clock (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled, and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at MSI speed. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at MSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. @@ -27,16 +27,31 @@ (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers + (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals whose clocks are not derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) (*) SDIO only for STM32L1xxxD devices + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -62,7 +77,7 @@ * ****************************************************************************** */ - + /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" @@ -79,27 +94,18 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Defines RCC Private Defines - * @{ - */ - -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ - +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ /** * @} */ - /* Private macro -------------------------------------------------------------*/ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ -#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO1_GPIO_PORT GPIOA #define MCO1_PIN GPIO_PIN_8 @@ -111,18 +117,24 @@ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ -const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t aPLLDivisionFactorTable[4] = {1, 2, 3, 4}; -const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; - +const uint8_t aPLLMULFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; /** * @} */ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); +/** + * @} + */ -/** @defgroup RCC_Private_Functions RCC Exported Functions +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ */ @@ -131,11 +143,11 @@ const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; * @verbatim =============================================================================== -##### Initialization and de-initialization functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external oscillators - (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration @@ -144,7 +156,6 @@ const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. - (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC clock source. @@ -153,28 +164,28 @@ const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (#) PLL (clocked by HSI or HSE), featuring different output clocks: (++) The first output is used to generate the high speed system clock (up to 32 MHz) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clockis automatically switched to MSI and an interrupt + clock source), the System clocks automatically switched to MSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE, HSE or PLL clock (through a configurable prescaler) on PA8 pin. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB buses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock @@ -189,7 +200,13 @@ const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz and PCLK1 32 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: + frequency should be adapted accordingly. + @endverbatim + * @{ + */ + +/* + Additional consideration on the HCLK based on Latency settings: +----------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |------------------------------------------------------| @@ -200,8 +217,9 @@ const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; |---------------|------------------|-----------------|-----------------| |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 | +----------------------------------------------------------------------+ - (#) The following table gives the different clock source frequencies depending on the product - voltage range: + + The following table gives the different clock source frequencies depending on the product + voltage range: +------------------------------------------------------------------------------------------+ | Product voltage | Clock frequency | | |------------------|-----------------------------|-----------------------| @@ -216,9 +234,6 @@ const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz | | | | | | (PLLVCO max = 24 MHz) | +------------------------------------------------------------------------------------------+ - - @endverbatim - * @{ */ /** @@ -241,7 +256,7 @@ void HAL_RCC_DeInit(void) /* Switch SYSCLK to MSI*/ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); - + /* Reset HSION, HSEON, CSSON, HSEBYP & PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP); @@ -256,14 +271,23 @@ void HAL_RCC_DeInit(void) /* Disable all interrupts */ CLEAR_REG(RCC->CIR); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = MSI_VALUE; } /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) @@ -271,6 +295,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) uint32_t tickstart = 0; /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ @@ -278,42 +303,29 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } } else { - /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ - __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - /* Check the HSE State */ + + /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till HSE is ready */ + /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) @@ -324,10 +336,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till HSE is bypassed or disabled */ + /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) @@ -346,8 +358,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) @@ -364,15 +376,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) else { /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) { - /* Enable the Internal High Speed oscillator (HSI). */ + /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) @@ -389,10 +401,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) @@ -408,65 +420,96 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); - assert_param(IS_RCC_MSIRANGE(RCC_OscInitStruct->MSIClockRange)); - - /* Configures the Internal Multi Speed oscillator (MSI) clock range. */ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - - /* Check if MSI is used as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)) + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* When the MSI is used as system clock it will not be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) { - /* When MSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON)) + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) { return HAL_ERROR; } - /* Otherwise, just the calibration is allowed */ + + /* Otherwise, just the calibration and MSI range change are allowed */ else { - /* Adjusts the Multi Speed oscillator (MSI) calibration value. */ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); } } else { /* Check the MSI State */ - if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF) + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) { /* Enable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ + + /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } - - /* Adjusts the Multi Speed oscillator (MSI) calibration value. */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + } else { /* Disable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ + + /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } - } + } } } } @@ -477,12 +520,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSI is ready */ @@ -499,10 +542,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till LSI is ready */ + /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) @@ -519,7 +562,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable Power Clock*/ - __PWR_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); @@ -529,39 +572,24 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) while((PWR->CR & PWR_CR_DBP) == RESET) { - if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } - /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON) + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -569,26 +597,27 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till LSE is ready */ + /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } + /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { @@ -596,15 +625,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); - - + /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -612,7 +640,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_TIMEOUT; } } - + /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLMUL, @@ -620,7 +648,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ @@ -637,10 +665,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -655,50 +683,50 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) return HAL_ERROR; } } + return HAL_OK; } /** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle - * @arg FLASH_LATENCY_1: FLASH One Latency cycle + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function * * @note The MSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). + * clock source is ready (clock stable after start-up delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source will be ready. - * You can use HAL_RCC_GetClockConfig() function to know which clock is + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @note Depending on the device voltage range, the software has to set correctly * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0; /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); - + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ - - /* Increasing the CPU frequency */ + + /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ @@ -710,200 +738,105 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { return HAL_ERROR; } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else - { - /* Check the MSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) - { - return HAL_ERROR; - } + return HAL_ERROR; } - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } + return HAL_ERROR; } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } + return HAL_ERROR; } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } + return HAL_ERROR; } - } - } - /* Decreasing the CPU frequency */ - else - { - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); - /*------------------------- SYSCLK Configuration -------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) { - /* Check the MSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - return HAL_ERROR; + return HAL_TIMEOUT; } } - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - } - + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); @@ -913,7 +846,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { return HAL_ERROR; } - } + } + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) @@ -928,7 +862,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } - + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -957,50 +894,50 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /** * @brief Selects the clock source to output on MCO pin. * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx: specifies the output direction for the clock source. + * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: - * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource: specifies the clock source to output. + * @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected - * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected - * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected - * @arg RCC_MCO1SOURCE_MSI: MSI oscillator clock selected - * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected - * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected - * @arg RCC_MCO1SOURCE_LSI: LSI clock selected - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected - * @param RCC_MCODiv: specifies the MCO DIV. + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCO clock - * @arg RCC_MCODIV_2: division by 2 applied to MCO clock - * @arg RCC_MCODIV_4: division by 4 applied to MCO clock - * @arg RCC_MCODIV_8: division by 8 applied to MCO clock - * @arg RCC_MCODIV_16: division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock * @retval None */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { - GPIO_InitTypeDef gpio; - + GPIO_InitTypeDef gpio = {0}; + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); /* MCO Clock Enable */ - __MCO1_CLK_ENABLE(); + MCO1_CLK_ENABLE(); - /* Configure the MCO1 pin in alternate function mode */ - gpio.Pin = MCO1_PIN; - gpio.Mode = GPIO_MODE_AF_PP; - gpio.Speed = GPIO_SPEED_HIGH; - gpio.Pull = GPIO_NOPULL; + /* Configure the MCO1 pin in alternate function mode */ + gpio.Pin = MCO1_PIN; + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; gpio.Alternate = GPIO_AF0_MCO; HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); } /** @@ -1014,7 +951,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M */ void HAL_RCC_EnableCSS(void) { - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE; + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; } /** @@ -1023,20 +960,19 @@ void HAL_RCC_EnableCSS(void) */ void HAL_RCC_DisableCSS(void) { - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE; + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; } /** * @brief Returns the SYSCLK frequency - * * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * @note If SYSCLK source is MSI, function returns values based on MSI + * @note If SYSCLK source is MSI, function returns a value based on MSI * Value as defined by the MSI range. * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations @@ -1050,12 +986,11 @@ void HAL_RCC_DisableCSS(void) * value for HSE crystal. * * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. + * baud-rate for the communication peripherals or configure other parameters. * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * - * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) @@ -1068,35 +1003,35 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; break; } - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; break; } - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { - pllm = aPLLMulFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; + pllm = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; plld = aPLLDivisionFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> POSITION_VAL(RCC_CFGR_PLLDIV)]; if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = HSE_VALUE * (pllm / plld); + pllvco = (HSE_VALUE * pllm) / plld; } else { /* HSI used as PLL clock source */ - pllvco = HSI_VALUE * (pllm / plld); + pllvco = (HSI_VALUE * pllm) / plld; } sysclockfreq = pllvco; break; } - case RCC_CFGR_SWS_MSI: /* MSI used as system clock source */ - default: /* MSI used as system clock */ + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ { msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> POSITION_VAL(RCC_ICSCR_MSIRANGE); sysclockfreq = (32768 * (1 << (msiclkrange + 1))); @@ -1117,7 +1052,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void) */ uint32_t HAL_RCC_GetHCLKFreq(void) { - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; return SystemCoreClock; } @@ -1130,7 +1064,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); } /** @@ -1142,22 +1076,26 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); } /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI; - + + /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { @@ -1171,7 +1109,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } - + /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { @@ -1236,15 +1174,19 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Configures the RCC_ClkInitStruct according to the internal + * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. - * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency: Pointer on the Flash Latency. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; @@ -1275,7 +1217,7 @@ void HAL_RCC_NMI_IRQHandler(void) if(__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CCSCallback(); + HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); @@ -1286,10 +1228,10 @@ void HAL_RCC_NMI_IRQHandler(void) * @brief RCC Clock Security System interrupt callback * @retval none */ -__weak void HAL_RCC_CCSCallback(void) +__weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CCSCallback could be implemented in the user file + the HAL_RCC_CSSCallback could be implemented in the user file */ } @@ -1301,6 +1243,58 @@ __weak void HAL_RCC_CCSCallback(void) * @} */ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ +/** + * @brief Update number of Flash wait states in line with MSI range and current + voltage range + * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) +{ + uint32_t vos = 0; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + { + vos = HAL_PWREx_GetVoltageRange(); + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + vos = HAL_PWREx_GetVoltageRange(); + __HAL_RCC_PWR_CLK_DISABLE(); + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (msirange == RCC_MSIRANGE_6)) + { + latency = FLASH_LATENCY_1; /* 1WS */ + } + } + + __HAL_FLASH_SET_LATENCY(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != latency) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h index 6d09afeb1b6..7d6d4a26865 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_rcc.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L1xx_HAL_RCC_H @@ -51,10 +51,197 @@ */ /** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout * @{ */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define MSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ + +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x08 +#define RCC_CIR_OFFSET 0x0C +#define RCC_CSR_OFFSET 0x34 +/** + * @} + */ + +/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4))) +/* Alias word address of MSION bit */ +#define RCC_MSION_BIT_NUMBER POSITION_VAL(RCC_CR_MSION) +#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_MSION_BIT_NUMBER * 4))) +/* Alias word address of HSEON bit */ +#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4))) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4))) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4))) + +/* Alias word address of RMVF bit */ +#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEON) +#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEBYP) +#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4))) + +/* Alias word address of RTCEN bit */ +#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCEN) +#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4))) + +/* Alias word address of RTCRST bit */ +#define RCC_RTCRST_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCRST) +#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCRST_BIT_NUMBER * 4))) + +/** + * @} + */ + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1) +#define CSR_REG_INDEX ((uint8_t)2) + +#define RCC_FLAG_MASK ((uint8_t)0x1F) -/* Exported types ------------------------------------------------------------*/ +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) +#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF) +#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ + ((__RANGE__) == RCC_MSIRANGE_1) || \ + ((__RANGE__) == RCC_MSIRANGE_2) || \ + ((__RANGE__) == RCC_MSIRANGE_3) || \ + ((__RANGE__) == RCC_MSIRANGE_4) || \ + ((__RANGE__) == RCC_MSIRANGE_5) || \ + ((__RANGE__) == RCC_MSIRANGE_6)) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ + ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) + +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ + ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ + ((__MUL__) == RCC_PLL_MUL48)) +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ @@ -65,17 +252,17 @@ */ typedef struct { - uint32_t PLLState; /*!< The new state of the PLL. + uint32_t PLLState; /*!< PLLState: The new state of the PLL. This parameter can be a value of @ref RCC_PLL_Config */ - uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ - uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ - uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Division_Factor*/ + uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Division_Factor*/ } RCC_PLLInitTypeDef; /** @@ -83,14 +270,14 @@ typedef struct */ typedef struct { - uint32_t OscillatorType; /*!< The oscillators to be configured. + uint32_t OscillatorType; /*!< The oscillators to be configured. This parameter can be a value of @ref RCC_Oscillator_Type */ uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ @@ -98,11 +285,11 @@ typedef struct uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ - uint32_t MSIState; /*!< The new state of the MSI. - This parameter can be a value of @ref RCC_MSI_Config */ + uint32_t MSIState; /*!< The new state of the MSI. + This parameter can be a value of @ref RCC_MSI_Config */ uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ @@ -110,7 +297,7 @@ typedef struct uint32_t MSIClockRange; /*!< The MSI frequency range. This parameter can be a value of @ref RCC_MSI_Clock_Range */ - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ } RCC_OscInitTypeDef; @@ -133,7 +320,6 @@ typedef struct uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - } RCC_ClkInitTypeDef; /** @@ -144,88 +330,19 @@ typedef struct /** @defgroup RCC_Exported_Constants RCC Exported Constants * @{ */ -#define DBP_TIMEOUT_VALUE ((uint32_t)100) -#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion - * @brief RCC registers bit address in the alias region +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00 -#define RCC_CFGR_OFFSET 0x08 -#define RCC_CIR_OFFSET 0x0C -#define RCC_CSR_OFFSET 0x34 -#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) -#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) -#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) -#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) - -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION) -#define CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4))) -/* Alias word address of MSION bit */ -#define MSION_BITNUMBER POSITION_VAL(RCC_CR_MSION) -#define CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4))) -/* Alias word address of HSEON bit */ -#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON) -#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4))) -/* Alias word address of CSSON bit */ -#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON) -#define CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4))) -/* Alias word address of PLLON bit */ -#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON) -#define CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4))) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION) -#define CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4))) - -/* Alias word address of LSEON bit */ -#define LSEON_BITNUMBER POSITION_VAL(RCC_CSR_LSEON) -#define CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4))) -/* Alias word address of LSEON bit */ -#define LSEBYP_BITNUMBER POSITION_VAL(RCC_CSR_LSEBYP) -#define CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4))) - -/* Alias word address of RTCEN bit */ -#define RTCEN_BITNUMBER POSITION_VAL(RCC_CSR_RTCEN) -#define CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4))) - -/* Alias word address of RTCRST bit */ -#define RTCRST_BITNUMBER POSITION_VAL(RCC_CSR_RTCRST) -#define CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4))) - -/* CR register byte 2 (Bits[23:16]) base address */ -#define CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ /** * @} */ -/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source - * @{ - */ - -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI -#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE - -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSE)) -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type RCC Oscillator Type +/** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) @@ -234,59 +351,44 @@ typedef struct #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) - -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) /** * @} */ -/** @defgroup RCC_HSE_Config RCC HSE Config +/** @defgroup RCC_HSE_Config HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00000001) -#define RCC_HSE_BYPASS ((uint32_t)0x00000005) - -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) +#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ +#define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */ /** * @} */ -/** @defgroup RCC_LSE_Config RCC LSE Config +/** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) -#define RCC_LSE_ON ((uint32_t)0x00000001) -#define RCC_LSE_BYPASS ((uint32_t)0x00000005) +#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ +#define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */ -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) /** * @} */ -/** @defgroup RCC_HSI_Config RCC HSI Config +/** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000) -#define RCC_HSI_ON ((uint32_t)0x00000001) +#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) - -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) /** * @} */ -/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range +/** @defgroup RCC_MSI_Clock_Range MSI Clock Range * @{ */ @@ -298,186 +400,176 @@ typedef struct #define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /*!< MSI = 2.097 MHz */ #define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /*!< MSI = 4.194 MHz */ -#define IS_RCC_MSIRANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ - ((__RANGE__) == RCC_MSIRANGE_1) || \ - ((__RANGE__) == RCC_MSIRANGE_2) || \ - ((__RANGE__) == RCC_MSIRANGE_3) || \ - ((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6)) /** * @} */ - -/** @defgroup RCC_LSI_Config RCC LSI Config + +/** @defgroup RCC_LSI_Config LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000) -#define RCC_LSI_ON ((uint32_t)0x00000001) +#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) /** * @} */ - -/** @defgroup RCC_MSI_Config RCC MSI Config +/** @defgroup RCC_MSI_Config MSI Config * @{ */ #define RCC_MSI_OFF ((uint32_t)0x00000000) #define RCC_MSI_ON ((uint32_t)0x00000001) -#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) - #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */ /** * @} */ -/** @defgroup RCC_PLL_Config RCC PLL Config +/** @defgroup RCC_PLL_Config PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000) -#define RCC_PLL_OFF ((uint32_t)0x00000001) -#define RCC_PLL_ON ((uint32_t)0x00000002) +#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ +#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ +#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) /** * @} */ -/** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor +/** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ -#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 -#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 -#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 +/** + * @} + */ -#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ - ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ /** * @} */ -/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status * @{ */ +#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 -#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 -#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 -#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 -#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 -#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 -#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 -#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 -#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 - -#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ - ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ - ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ - ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ - ((__MUL__) == RCC_PLL_MUL48)) /** * @} */ -/** @defgroup RCC_System_Clock_Type RCC System Clock Type +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15)) /** * @} */ -/** @defgroup RCC_System_Clock_Source RCC System Clock Source +/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ -#define RCC_SYSCLKSOURCE_MSI ((uint32_t)RCC_CFGR_SW_MSI) -#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) -#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) -#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) /** * @} - */ + */ -/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source +/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler * @{ */ -#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1) -#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2) -#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4) -#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8) -#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16) -#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64) -#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128) -#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256) -#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512) +#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock */ +#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ +#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ +#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ +/** + * @} + */ -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) +/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */ /** * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source + */ + +/** @defgroup RCC_PLL_Division_Factor PLL Division Factor * @{ */ -#define RCC_HCLK_DIV1 ((uint32_t)RCC_CFGR_PPRE1_DIV1) -#define RCC_HCLK_DIV2 ((uint32_t)RCC_CFGR_PPRE1_DIV2) -#define RCC_HCLK_DIV4 ((uint32_t)RCC_CFGR_PPRE1_DIV4) -#define RCC_HCLK_DIV8 ((uint32_t)RCC_CFGR_PPRE1_DIV8) -#define RCC_HCLK_DIV16 ((uint32_t)RCC_CFGR_PPRE1_DIV16) -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) +#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 +#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 +#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 + /** * @} - */ + */ -/** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source +/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor * @{ */ -#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_CSR_RTCSEL_LSE) -#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_CSR_RTCSEL_LSI) -#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)RCC_CSR_RTCSEL_HSE) -#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)(RCC_CR_RTCPRE_0 | RCC_CSR_RTCSEL_HSE)) -#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)(RCC_CR_RTCPRE_1 | RCC_CSR_RTCSEL_HSE)) -#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)(RCC_CR_RTCPRE | RCC_CSR_RTCSEL_HSE)) + +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 +#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 +#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 +#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 + /** * @} - */ + */ -/** @defgroup RCC_MCO_Index RCC MCO Index +/** @defgroup RCC_MCO_Index MCO Index * @{ */ #define RCC_MCO1 ((uint32_t)0x00000000) -#define RCC_MCO RCC_MCO1 +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ -#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO)) /** * @} */ -/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler +/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler * @{ */ #define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1) @@ -486,14 +578,11 @@ typedef struct #define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8) #define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16) -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ - ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ - ((__DIV__) == RCC_MCODIV_16)) /** * @} - */ + */ -/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source * @{ */ #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) @@ -505,245 +594,439 @@ typedef struct #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL) -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) /** * @} */ - -/** @defgroup RCC_Interrupt RCC Interrupt +/** @defgroup RCC_Interrupt Interrupts * @{ */ -#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) -#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) -#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) -#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) -#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) -#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) -#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSS) -#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /*!< MSI Ready Interrupt flag */ +#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ /** * @} - */ + */ -/** @defgroup RCC_Flag RCC Flag - * Elements values convention: 0XXYYYYYb +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register - * - XX : Register index - * - 01: CR register - * - 11: CSR register + * - XXX : Register index + * - 001: CR register + * - 010: CSR register * @{ */ -#define CR_REG_INDEX ((uint8_t)1) -#define CSR_REG_INDEX ((uint8_t)3) - /* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) -#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) -#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) -#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) -#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_RMVF))) -#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) - -#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ +#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */ +#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_RMVF_BIT_NUMBER)) /*!< Remove reset flag */ +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ +#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */ /** * @} - */ + */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Macros RCC Exported Macros * @{ */ -/** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable +/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ -#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) -#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) -#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) -#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) -#define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN)) +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) + +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) -#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) -#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) -#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) - -#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) -#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) -#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) -#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) -#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) - -#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) -#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) -#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +/** + * @} + */ -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_COMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN)) + +/** + * @} */ -#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) -#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) -#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN)) -#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) -#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) -#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) -#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) -#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) -#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) -#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) -#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) -#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) -#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) -#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) -#define __COMP_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_COMPEN)) - -#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) -#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN)) - -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. + * @{ */ -#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) -#define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN)) -#define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN)) -#define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN)) -#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) -#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) -#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) - -#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) -#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) -#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) /** * @} */ - + /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release * @brief Force or release AHB peripheral reset. * @{ - */ -#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) -#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) -#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) -#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) -#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) -#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) - -#define __CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) -#define __FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST)) -#define __DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) - -#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) -#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) -#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) -#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) -#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) -#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) - -#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST)) -#define __FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST)) -#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST)) - -/** @brief Force or release APB1 peripheral reset. - */ -#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) -#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) -#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST)) - -#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) -#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) -#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST)) - -/** @brief Force or release APB2 peripheral reset. - */ -#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) -#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -#define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) -#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) -#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) - -#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) -#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) -#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) -#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) -#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) + +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) +#define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) + +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST)) +#define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) /** * @} @@ -756,25 +1039,25 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ -#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN)) -#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN)) -#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN)) -#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN)) -#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN)) -#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN)) -#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN)) -#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN)) -#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN)) -#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN)) -#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN)) -#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN)) -#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN)) -#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN)) -#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN)) -#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN)) /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -782,37 +1065,37 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) -#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) -#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) -#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) -#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) -#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN)) -#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) -#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN)) - -#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) -#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) -#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) -#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) -#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) -#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN)) -#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) -#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN)) /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -820,26 +1103,231 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) -#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) -#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) -#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) -#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) -#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) -#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ -#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) -#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) -#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) -#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) -#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) -#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == RESET) /** * @} */ +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) +#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) +#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * @note HSI can not be stopped if it is used as system clock source. In this case, @@ -850,20 +1338,158 @@ typedef struct * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. */ -#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE) -#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE) +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) -/** @brief Macros to enable or disable the External High Speed oscillator (HSE). - * @param __HSE_STATE__: specifies the new state of the HSE. +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM))) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + } \ + }while(0) + +/** + * @} + */ + +/** @defgroup RCC_MSI_Configuration MSI Configuration + * @{ */ -#define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__HSE_STATE__)) -/** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). +/** @brief Macro to enable Internal Multi Speed oscillator (MSI). + * @note After enabling the MSI, the application software should wait on MSIRDY + * flag to be set indicating that MSI clock is stable and can be used as + * system clock source. + */ +#define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Multi Speed oscillator (MSI). * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure @@ -871,118 +1497,200 @@ typedef struct * Security System CSS is enabled). * @note MSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the MSI. - * @note After enabling the MSI, the application software should wait on MSIRDY - * flag to be set indicating that MSI clock is stable and can be used as - * system clock source. * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator * clock cycles. */ -#define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) CR_MSION_BB = ENABLE) -#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) CR_MSION_BB = DISABLE) - -/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ - (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM))) +#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE) -/** @brief macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. +/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal MSI RC. - * @param _MSICALIBRATIONVALUE_: specifies the calibration trimming value. + * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value. * (default is RCC_MSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ + * This parameter must be a number between 0 and 0xFF. + */ #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM))) - + /* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. * @note After restart from Reset or wakeup from STANDBY, the MSI clock is * around 2.097 MHz. The MSI clock does not change after wake-up from * STOP mode. * @note The MSI clock range can be modified on the fly. - * @param _MSIRANGEVALUE_: specifies the MSI Clock range. + * @param _MSIRANGEVALUE_ specifies the MSI Clock range. * This parameter must be one of the following values: - * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz - * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz - * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz - * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz - * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz - * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) - * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz - */ -#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz + */ +#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \ + RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) + +/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode + * @retval MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz + */ +#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)) - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. +/** + * @} */ -#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE) -#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE) - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE). - */ -#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \ - do{ \ - if ((__LSE_STATE__) == RCC_LSE_OFF) \ - { \ - *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \ - *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \ - } \ - else if ((__LSE_STATE__) == RCC_LSE_ON) \ - { \ - *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \ - *(__IO uint32_t *) CSR_LSEON_BB = ENABLE; \ - } \ - else \ - { \ - *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \ - *(__IO uint32_t *) CSR_LSEBYP_BB = ENABLE; \ - } \ - }while(0) - -/** @brief Macros to enable or disable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ */ -#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = ENABLE) -#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = DISABLE) -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 + * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 + * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 + * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 + * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 + * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 + * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24 + * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32 + * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48 + * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in + * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is + * in Range 3. + * + * @param __PLLDIV__ specifies the division factor for PLL VCO input clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO /2 + * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO /3 + * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO /4 + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. */ -#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) CSR_RTCRST_BB = ENABLE) -#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) CSR_RTCRST_BB = DISABLE) +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) -/** @brief Macro to configures the RTC clock (RTCCLK). +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** + * @} + */ + + /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macro to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). * - * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC @@ -1002,168 +1710,153 @@ typedef struct RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ } while (0) -/** @brief macros to get the RTC clock source. +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() */ #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. +/** + * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK). + * + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock + * */ -#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE) -#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE) +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE))) -/** @brief macros to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock - * This parameter can be one of the following values: - * @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 - * @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4 - * @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6 - * @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8 - * @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 - * @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 - * @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24 - * @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32 - * @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48 - * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in - * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is - * in Range 3. - * - * @param __PLLDIV__: specifies the division factor for PLL VCO input clock - * This parameter can be one of the following values: - * @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2 - * @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3 - * @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4 - * +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE) -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * @arg RCC_CFGR_SWS_MSI: MSI used as system clock - * @arg RCC_CFGR_SWS_HSI: HSI used as system clock - * @arg RCC_CFGR_SWS_HSE: HSE used as system clock - * @arg RCC_CFGR_SWS_PLL: PLL used as system clock - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) - -/** @brief macros to manage the specified RCC Flags and interrupts. +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE) + +/** + * @} */ -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts.). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) - -/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_MSIRDY: MSI ready interrupt. - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - * @arg RCC_IT_CSS: Clock Security System interrupt + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + * @arg @ref RCC_IT_CSS Clock Security System interrupt */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__)) +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) /** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_MSIRDY: MSI ready interrupt. - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - * @arg RCC_IT_CSS: Clock Security System interrupt + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + * @arg @ref RCC_IT_CSS Clock Security System interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) /** @brief Check RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. - * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready. - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. - * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. - * @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*) - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. - * @arg RCC_FLAG_PINRST: Pin reset. - * @arg RCC_FLAG_PORRST: POR/PDR reset. - * @arg RCC_FLAG_SFTRST: Software reset. - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. - * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*) + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. * @note (*) This bit is available in high and medium+ density devices only. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) - -/** @brief Get oscillator clock selected as PLL input clock - * @retval The clock source used for PLL entry. The returned value can be one - * of the following: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock +/** + * @} */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC)) /** * @} - */ + */ /* Include RCC HAL Extension module */ #include "stm32l1xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Private_Functions +/** @addtogroup RCC_Exported_Functions * @{ */ @@ -1198,8 +1891,8 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CCSCallback(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); /** * @} @@ -1207,11 +1900,11 @@ void HAL_RCC_CCSCallback(void); /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c index 90970b01096..fdb16ec5f23 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c @@ -2,10 +2,9 @@ ****************************************************************************** * @file stm32l1xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Extended RCC HAL module driver. - * * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions @@ -13,7 +12,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -47,21 +46,36 @@ * @{ */ +#ifdef HAL_RCC_MODULE_ENABLED + + /** @defgroup RCCEx RCCEx * @brief RCC Extension HAL module driver * @{ */ -#ifdef HAL_RCC_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Functions RCCEx Exported Functions +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ @@ -79,110 +93,131 @@ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) and RCC_BDCR register are set to their reset values. + the backup registers) are set to their reset values. @endverbatim * @{ */ /** - * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the - * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock). * @retval HAL status + * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig() + * to possibly update HSE divider. */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0; - + uint32_t tickstart = 0; + uint32_t temp_reg = 0; + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - ) +#if defined(LCD) + || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) +#endif /* LCD */ + ) + { + /* check for RTC Parameters used to output RTCCLK */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + } + +#if defined(LCD) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) { - /* Enable Power Controller clock */ - __PWR_CLK_ENABLE(); + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection)); + } +#endif /* LCD */ + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while((PWR->CR & PWR_CR_DBP) == RESET) { - if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } - tmpreg = (RCC->CSR & RCC_CSR_RTCSEL); - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - if((tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - ) + /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ + temp_reg = (RCC->CR & RCC_CR_RTCPRE); + if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) +#if defined (LCD) + || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) +#endif /* LCD */ + ) + { /* Check HSE State */ + if (((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) && HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + /* To update HSE divider, first switch-OFF HSE clock oscillator*/ + return HAL_ERROR; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); + + if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ + && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#if defined(LCD) + || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \ + && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) +#endif /* LCD */ + )) { /* Store the content of CSR register before the reset of Backup Domain */ - tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of CSR register */ - RCC->CSR = tmpreg; - } - - /* If LSE is selected as RTC clock source, wait for LSE reactivation */ - if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - ) - { - /* Get timeout */ - tickstart = HAL_GetTick(); + RCC->CSR = temp_reg; - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSERDY)) { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - return HAL_TIMEOUT; - } - } + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } - + return HAL_OK; } /** * @brief Get the PeriphClkInit according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks). * @retval None */ @@ -192,13 +227,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +#if defined(LCD) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +#endif /* LCD */ /* Get the RTC/LCD configuration -----------------------------------------------*/ srcclk = __HAL_RCC_GET_RTC_SOURCE(); @@ -212,20 +243,97 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Source clock is HSE. Need to get the prescaler value*/ PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); } -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +#if defined(LCD) PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +#endif /* LCD */ } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (depends on devices) + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t temp_reg = 0, clkprediv = 0, frequency = 0; + uint32_t srcclk = 0; + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: +#if defined(LCD) + case RCC_PERIPHCLK_LCD: +#endif /* LCD */ + { + /* Get RCC CSR configuration ------------------------------------------------------*/ + temp_reg = RCC->CSR; + + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready if RTC clock selection is LSE */ + if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready if RTC clock selection is LSI */ + else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSE */ + else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + /* Get the current HSE clock divider */ + clkprediv = __HAL_RCC_GET_RTC_HSE_PRESCALER(); + + switch (clkprediv) + { + case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ + { + frequency = HSE_VALUE / 16; + break; + } + case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ + { + frequency = HSE_VALUE / 8; + break; + } + case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ + { + frequency = HSE_VALUE / 4; + break; + } + default: /* HSE DIV2 has been selected */ + { + frequency = HSE_VALUE / 2; + break; + } + } + } + /* Clock not enabled for RTC */ + else + { + frequency = 0; + } + break; + } + default: + { + break; + } + } + return(frequency); +} + +#if defined(RCC_CSR_LSECSSON) /** * @brief Enables the LSE Clock Security System. * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied @@ -253,9 +361,59 @@ void HAL_RCCEx_EnableLSECSS(void) */ void HAL_RCCEx_DisableLSECSS(void) { + /* Disable LSE CSS */ *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE; + + /* Disable LSE CSS IT */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Enable the LSE Clock Security System IT & corresponding EXTI line. + * @note LSE Clock Security System IT is mapped on RTC EXTI line 19 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 19 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} +#endif /* RCC_CSR_LSECSSON */ /** * @} @@ -265,11 +423,11 @@ void HAL_RCCEx_DisableLSECSS(void) * @} */ -#endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h index f3800e3b05b..8ce5c386bdf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,6 +54,51 @@ * @{ */ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +#define LSI_VALUE ((uint32_t)37000) /* ~37kHz */ + +#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\ + || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\ + || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +/* Alias word address of LSECSSON bit */ +#define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON) +#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4))) + +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/ + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) + +#else /* Not LCD LINE */ + +#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +/** + * @} + */ + /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types @@ -71,16 +116,16 @@ typedef struct uint32_t RTCClockSelection; /*!< specifies the RTC clock source. This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) uint32_t LCDClockSelection; /*!< specifies the LCD clock source. This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ } RCC_PeriphCLKInitTypeDef; /** @@ -98,43 +143,30 @@ typedef struct */ #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001) -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - -#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) - -#else /* Not LCD LINE */ +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ /** * @} */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -/* Alias word address of LSECSSON bit */ -#define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON) -#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4))) +#if defined(RCC_CSR_LSECSSON) +/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_MR19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ +/** + * @} + */ +#endif /* RCC_CSR_LSECSSON */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ /** * @} @@ -152,112 +184,197 @@ typedef struct * using it. * @{ */ -#if defined (STM32L151xB) || defined (STM32L152xB) || \ - defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) -#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) -#define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN)) - -#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) -#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) -#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_AESEN)) -#define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) -#define __FSMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FSMCEN)) -#define __FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN)) -#define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) +#define __HAL_RCC_LCD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN)) -#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) -#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) -#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) - -#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - -#define __OPAMP_CLK_ENABLE() __COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ -#define __OPAMP_CLK_DISABLE() __COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\ + || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */ /** @brief Enables or disables the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) -#define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN)) -#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ @@ -270,106 +387,117 @@ typedef struct * @brief Forces or releases AHB peripheral reset. * @{ */ -#if defined (STM32L151xB) || defined (STM32L152xB) || \ - defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) -#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) -#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) -#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) -#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) -#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) -#define __DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) -#define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) -#define __FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) -#define __FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) -#define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) +#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) +#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** @brief Forces or releases APB1 peripheral reset. */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) -#define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) -#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) -#define __OPAMP_FORCE_RESET() __COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ -#define __OPAMP_RELEASE_RESET() __COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ /** @brief Forces or releases APB2 peripheral reset. */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) -#define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ @@ -385,61 +513,65 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ -#if defined (STM32L151xB) || defined (STM32L152xB) || \ - defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) -#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) -#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) -#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) -#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) -#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) -#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) -#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) -#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) -#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) -#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) -#define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) +#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) +#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -447,34 +579,47 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) -#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) -#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) -#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) -#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) -#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -482,10 +627,130 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == RESET) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != RESET) +#define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == RESET) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED() +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED() + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ @@ -493,26 +758,152 @@ typedef struct * @} */ -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) +/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == RESET) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == RESET) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == RESET) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == RESET) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == RESET) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != RESET) +#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == RESET) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == RESET) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +/** @defgroup RCCEx_LCD_Configuration LCd Configuration + * @brief Macros to configure clock source of LCD peripherals. + * @{ + */ /** @brief Macro to configures LCD clock (LCDCLK). * @note LCD and RTC use the same configuration * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the * LCD clock source. * - * @param __LCD_CLKSOURCE__: specifies the LCD clock source. + * @param __LCD_CLKSOURCE__ specifies the LCD clock source. * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock */ #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) @@ -520,14 +911,112 @@ typedef struct */ #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(RCC_CSR_LSECSSON) + +/** + * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable interrupt on RCC LSE CSS EXTI Line 19. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable event on RCC LSE CSS EXTI Line 19. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable event on RCC LSE CSS EXTI Line 19. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS)) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) + +#endif /* RCC_CSR_LSECSSON */ + /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Functions +/** @addtogroup RCCEx_Exported_Functions * @{ */ @@ -537,17 +1026,17 @@ typedef struct HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(RCC_CSR_LSECSSON) void HAL_RCCEx_EnableLSECSS(void); void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ - +#endif /* RCC_CSR_LSECSSON */ /** * @} */ @@ -571,3 +1060,4 @@ void HAL_RCCEx_DisableLSECSS(void); #endif /* __STM32L1xx_HAL_RCC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.c index 1b63aeff269..c96c0f23bfd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_rtc.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -55,7 +55,7 @@ accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() function. + __HAL_RCC_PWR_CLK_ENABLE() function. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. @@ -102,7 +102,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -196,7 +196,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { /* Check the RTC peripheral state */ - if(hrtc == HAL_NULL) + if(hrtc == NULL) { return HAL_ERROR; } @@ -212,6 +212,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) if(hrtc->State == HAL_RTC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); } @@ -269,6 +272,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) */ __weak HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32l1xx_hal_rtc_ex.c */ @@ -284,6 +290,9 @@ __weak HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_MspInit could be implemented in the user file */ @@ -297,6 +306,9 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_MspDeInit could be implemented in the user file */ @@ -327,8 +339,8 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) * @param sTime: Pointer to Time structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -345,7 +357,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -450,8 +462,8 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * @param sDate: Pointer to date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -466,14 +478,14 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); @@ -556,8 +568,11 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @param sDate: Pointer to Date structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -577,7 +592,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the date structure parameters to Binary format */ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); @@ -620,7 +635,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_ALARM(Alarm)); + assert_param(IS_RTC_ALARM(Alarm)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -702,35 +717,37 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) -{ - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA)) +{ + /* Get the AlarmA interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) + /* Get the pending status of the AlarmA Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET) { - /* AlarmA callback */ + /* AlarmA callback */ HAL_RTC_AlarmAEventCallback(hrtc); - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + + /* Clear the AlarmA interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); } } - - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB)) + + /* Get the AlarmB interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET) + /* Get the pending status of the AlarmB Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET) { - /* AlarmB callback */ + /* AlarmB callback */ HAL_RTCEx_AlarmBEventCallback(hrtc); - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); + + /* Clear the AlarmB interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); } } /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -744,6 +761,9 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTC_AlarmAEventCallback could be implemented in the user file */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.h index b1092a56fe9..b4b558d73b4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_rtc.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -243,10 +243,10 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format * @{ */ -#define FORMAT_BIN ((uint32_t)0x000000000) -#define FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN ((uint32_t)0x000000000) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD)) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) /** * @} */ @@ -344,7 +344,7 @@ typedef struct #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 #define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) /** * @} */ @@ -355,7 +355,7 @@ typedef struct #define RTC_ALARM_A RTC_CR_ALRAE #define RTC_ALARM_B RTC_CR_ALRBE -#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) /** * @} */ @@ -396,6 +396,7 @@ typedef struct (__HANDLE__)->Instance->WPR = 0xFF; \ } while(0) + /** * @brief Enable the RTC ALARMA peripheral. * @param __HANDLE__: specifies the RTC handle. @@ -449,95 +450,126 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) /** * @brief Get the selected RTC Alarm's flag status. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: + * @param __FLAG__: specifies the RTC Alarm Flag sources to check. + * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF + * @arg RTC_FLAG_ALRAWF + * @arg RTC_FLAG_ALRBWF * @retval None */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) /** * @brief Clear the RTC Alarm's pending flags. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF + * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @arg RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +/** + * @brief Enable interrupt on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @brief Disable interrupt on the RTC Alarm associated Exti line. * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable event on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable event on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. */ -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) -/* alias define maintained for legacy */ -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT +/** + * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) /** - * @brief Disable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. */ -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); } while(0); -/* alias define maintained for legacy */ -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +/** + * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); } while(0); /** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. + * @retval Line Status. */ -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) +#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Clear the RTC Exti flags. - * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Clear the RTC Alarm associated Exti line flag. + * @retval None. */ -#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) +#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) -/* alias define maintained for legacy */ -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +/** + * @brief Generate a Software interrupt on RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) /** * @} @@ -616,9 +648,39 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); /** @addtogroup RTC_Internal_Functions * @{ */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ + +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); uint8_t RTC_ByteToBcd2(uint8_t Value); uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** + * @} + */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c index 846441bb05f..c48f95eef96 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -63,7 +63,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -182,12 +182,12 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) hrtc->Instance->CALIBR = (uint32_t)0x00000000; hrtc->Instance->ALRMAR = (uint32_t)0x00000000; hrtc->Instance->ALRMBR = (uint32_t)0x00000000; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) hrtc->Instance->SHIFTR = (uint32_t)0x00000000; hrtc->Instance->CALR = (uint32_t)0x00000000; hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Reset ISR register and exit initialization mode */ hrtc->Instance->ISR = (uint32_t)0x00000000; @@ -229,16 +229,25 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) */ /** - * @brief Gets RTC current time. + * @brief Get RTC current time. * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTime: Pointer to Time structure + * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field (if availabale) returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers. + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @note If available, you can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds + * value in second fraction ratio with time unit following generic formula: + * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read + * to ensure consistency between the time and date values. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -248,10 +257,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Get subseconds values from the correspondent registers*/ +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + /* Get subseconds structure field from the corresponding register*/ sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Get the TR register */ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); @@ -263,7 +275,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the time structure parameters to Binary format */ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); @@ -289,8 +301,8 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) @@ -298,26 +310,26 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA uint32_t tickstart = 0; uint32_t tmpreg = 0; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -386,10 +398,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA ((uint32_t)sAlarm->AlarmMask)); } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Configure the Alarm A or Alarm B Sub Second registers */ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -422,10 +434,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } hrtc->Instance->ALRMAR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Configure the Alarm A Sub Second register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMA_ENABLE(hrtc); } @@ -456,10 +468,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } hrtc->Instance->ALRMBR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Configure the Alarm B Sub Second register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMB_ENABLE(hrtc); } @@ -483,8 +495,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @note The Alarm register can only be written when the corresponding Alarm * is disabled (Use the HAL_RTC_DeactivateAlarm()). * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. @@ -494,26 +506,26 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { uint32_t tickstart = 0; uint32_t tmpreg = 0; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -579,10 +591,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Configure the Alarm A or Alarm B Sub Second registers */ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -615,10 +627,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } hrtc->Instance->ALRMAR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Configure the Alarm A Sub Second register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMA_ENABLE(hrtc); /* Configure the Alarm interrupt */ @@ -651,10 +663,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } hrtc->Instance->ALRMBR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Configure the Alarm B Sub Second register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMB_ENABLE(hrtc); /* Configure the Alarm interrupt */ @@ -662,9 +674,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -688,20 +700,20 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef * @arg RTC_ALARM_B: AlarmB * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { uint32_t tmpreg = 0; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(Alarm)); + assert_param(IS_RTC_ALARM(Alarm)); if(Alarm == RTC_ALARM_A) { @@ -709,18 +721,18 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA sAlarm->Alarm = RTC_ALARM_A; tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ } else { sAlarm->Alarm = RTC_ALARM_B; tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ } /* Fill the structure with the read parameters */ @@ -728,14 +740,14 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); @@ -785,10 +797,10 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { uint32_t tickstart = 0; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ { /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; @@ -937,9 +949,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -998,8 +1010,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) * @param sTimeStampDate: Pointer to Date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * FORMAT_BIN: Binary data format - * FORMAT_BCD: BCD data format + * RTC_FORMAT_BIN: Binary data format + * RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) @@ -1018,9 +1030,9 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) sTimeStamp->SubSeconds = (uint32_t)((hrtc->Instance->TSSSR) & RTC_TSSSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Fill the Date structure fields with the read parameters */ sTimeStampDate->Year = 0; @@ -1029,7 +1041,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the TimeStamp structure parameters to Binary format */ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); @@ -1061,22 +1073,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef uint32_t tmpreg = 0; /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) { /* Configure the RTC_TAFCR register */ @@ -1099,7 +1111,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ hrtc->Instance->TAFCR |= tmpreg; hrtc->State = HAL_RTC_STATE_READY; @@ -1123,22 +1135,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType uint32_t tmpreg = 0; /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Configure the tamper trigger */ if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) { @@ -1160,16 +1172,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger); hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPIE); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ hrtc->Instance->TAFCR |= tmpreg; /* Configure the Tamper Interrupt in the RTC_TAFCR */ hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); hrtc->State = HAL_RTC_STATE_READY; @@ -1189,7 +1201,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) { - assert_param(IS_TAMPER(Tamper)); + assert_param(IS_RTC_TAMPER(Tamper)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1214,66 +1226,67 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T * @retval None */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) +{ + /* Get the TimeStamp interrupt source enable status */ + if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) + /* Get the pending status of the TIMESTAMP Interrupt */ + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET) { /* TIMESTAMP callback */ HAL_RTCEx_TimeStampEventCallback(hrtc); - + /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); } } - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1)) + /* Get the Tamper1 interrupts source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) + /* Get the pending status of the Tamper1 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET) { - /* Tamper callback */ + /* Tamper1 callback */ HAL_RTCEx_Tamper1EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + + /* Clear the Tamper1 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); } } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2)) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + /* Get the Tamper2 interrupts source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) + /* Get the pending status of the Tamper2 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET) { - /* Tamper callback */ + /* Tamper2 callback */ HAL_RTCEx_Tamper2EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ + + /* Clear the Tamper2 interrupt pending bit */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); } } - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP3)) + /* Get the Tamper3 interrupts source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) + /* Get the pending status of the Tamper3 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET) { - /* Tamper callback */ + /* Tamper3 callback */ HAL_RTCEx_Tamper3EventCallback(hrtc); - /* Clear the Tamper interrupt pending bit */ + /* Clear the Tamper3 interrupt pending bit */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); } } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Clear the EXTI s Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1287,6 +1300,9 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file */ @@ -1300,12 +1316,15 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file */ } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Tamper 2 callback. * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains @@ -1314,7 +1333,10 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } @@ -1326,11 +1348,14 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file */ } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @brief This function handles TimeStamp polling request. @@ -1405,7 +1430,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ return HAL_OK; } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief This function handles Tamper2 Polling. * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains @@ -1470,7 +1495,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ return HAL_OK; } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} @@ -1491,9 +1516,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ */ /** - * @brief Sets wake up timer. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set wake up timer. + * @param hrtc: RTC handle * @param WakeUpCounter: Wake up counter * @param WakeUpClock: Wake up clock * @retval HAL status @@ -1503,8 +1527,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1514,6 +1538,28 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){ + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); tickstart = HAL_GetTick(); @@ -1559,9 +1605,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } /** - * @brief Sets wake up timer with interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set wake up timer with interrupt. + * @param hrtc: RTC handle * @param WakeUpCounter: Wake up counter * @param WakeUpClock: Wake up clock * @retval HAL status @@ -1571,8 +1616,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1582,6 +1627,28 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){ + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); tickstart = HAL_GetTick(); @@ -1613,9 +1680,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t hrtc->Instance->CR |= (uint32_t)WakeUpClock; /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); /* Configure the Interrupt in the RTC_CR register */ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); @@ -1706,23 +1773,21 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) +{ + /* Get the pending status of the WAKEUPTIMER Interrupt */ + if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET) { - /* WAKEUPTIMER callback */ + /* WAKEUPTIMER callback */ HAL_RTCEx_WakeUpTimerEventCallback(hrtc); - + /* Clear the WAKEUPTIMER interrupt pending bit */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); } - } - /* Clear the EXTI s line Flag for RTC WakeUpTimer */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -1735,6 +1800,9 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file */ @@ -1970,7 +2038,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) return HAL_OK; } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Sets the Smooth calibration parameters. * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains @@ -1984,21 +2052,21 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue must be equal to 0. + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue mut be equal to 0. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -2033,7 +2101,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo } /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -2140,10 +2208,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh return HAL_OK; } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains @@ -2162,12 +2230,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ { -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Check the parameters */ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /* Process Locked */ __HAL_LOCK(hrtc); @@ -2177,13 +2245,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Clear flags before config */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)CalibOutput; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); @@ -2329,7 +2397,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) return HAL_OK; } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Enables the Bypass Shadow feature. * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains @@ -2395,7 +2463,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) return HAL_OK; } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} @@ -2424,6 +2492,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) */ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h index 103bec8b520..a4ef6f6dcad 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -70,7 +70,7 @@ typedef struct uint32_t Trigger; /*!< Specifies the Tamper Trigger. This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) uint32_t Filter; /*!< Specifies the RTC Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ @@ -85,7 +85,7 @@ typedef struct uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ }RTC_TamperTypeDef; /** @@ -103,14 +103,21 @@ typedef struct uint8_t Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ @@ -129,10 +136,10 @@ typedef struct uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_AlarmMask_Definitions */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ @@ -161,7 +168,7 @@ typedef struct #define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) #define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \ RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \ RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \ @@ -176,7 +183,7 @@ typedef struct RTC_FLAG_TAMP1F | \ RTC_FLAG_RECALPF)) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -184,11 +191,11 @@ typedef struct /** @defgroup RTC_Synchronous_Predivider Synchronous Predivider * @{ */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) #elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x1FFF) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -196,15 +203,15 @@ typedef struct /** @defgroup RTC_Interrupts_Definitions Interrupts Definitions * @{ */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) -#define RTC_IT_TAMP3 ((uint32_t)0x00080000) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) +#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) +#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) +#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) +#define RTC_IT_TAMP1 ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP1E)) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define RTC_IT_TAMP2 ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP2E)) +#define RTC_IT_TAMP3 ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP3E)) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -212,26 +219,26 @@ typedef struct /** @defgroup RTC_Flags_Definitions Flags Definitions * @{ */ -#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) -#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_FLAG_SHPF ((uint32_t)0x00000008) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) +#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) +#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ +#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) +#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) +#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) +#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) +#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) +#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) +#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) +#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) +#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ +#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) +#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) +#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) /** * @} */ @@ -317,16 +324,16 @@ typedef struct * @{ */ #define RTC_TAMPER_1 RTC_TAFCR_TAMP1E -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define RTC_TAMPER_2 RTC_TAFCR_TAMP2E #define RTC_TAMPER_3 RTC_TAFCR_TAMP3E -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_TAMPER(TAMPER) (((~(RTC_TAMPER_1|RTC_TAMPER_2|RTC_TAMPER_3) & (TAMPER)) == (uint32_t)RESET) && ((TAMPER) != (uint32_t)RESET)) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define IS_RTC_TAMPER(TAMPER) (((~(RTC_TAMPER_1|RTC_TAMPER_2|RTC_TAMPER_3) & (TAMPER)) == (uint32_t)RESET) && ((TAMPER) != (uint32_t)RESET)) #else -#define IS_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define IS_RTC_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -336,25 +343,25 @@ typedef struct */ #define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) #define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) #elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) -#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** @defgroup RTCEx_Tamper_Filter_Definitions Tamper Filter Definitions * @{ */ @@ -367,7 +374,7 @@ typedef struct #define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 consecutive samples at the active level. */ -#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) @@ -395,7 +402,7 @@ typedef struct #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ -#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ @@ -419,7 +426,7 @@ typedef struct #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ -#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) @@ -433,7 +440,7 @@ typedef struct #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) /** * @} @@ -445,12 +452,12 @@ typedef struct #define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ -#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ +#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) /** * @} */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** @defgroup RTCEx_Wakeup_Timer_Definitions Wakeup Timer Definitions * @{ @@ -462,14 +469,14 @@ typedef struct #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) -#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) /** * @} */ @@ -560,7 +567,7 @@ typedef struct * @} */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** @defgroup RTC_Alarm_Sub_Seconds_Value Alarm Sub Seconds Value * @{ */ @@ -625,7 +632,7 @@ typedef struct /** * @} */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} @@ -746,28 +753,126 @@ typedef struct */ #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Enable the RTC Tamper1 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP1E) + +/** + * @brief Disable the RTC Tamper1 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP1E) + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC)\ + || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA)\ + || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA)\ + || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +/** + * @brief Enable the RTC Tamper2 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP2E) + +/** + * @brief Disable the RTC Tamper2 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP2E) + +/** + * @brief Enable the RTC Tamper3 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP3E) + +/** + * @brief Disable the RTC Tamper3 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP3E) + + /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. * This parameter can be: - * @arg RTC_IT_TAMP1 - * @arg RTC_IT_TAMP2 - * @arg RTC_IT_TAMP3 + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP1F) != RESET) ? SET : RESET) : \ + ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP2F) != RESET) ? SET : RESET) : \ + (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP3F) != RESET) ? SET : RESET)) #else /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. * This parameter can be: - * @arg RTC_IT_TAMP1 + * @arg RTC_IT_TAMP1: Tamper1 interrupt * @retval None */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP1F) != RESET) ? SET : RESET) + #endif -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Enable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) + * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) + * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, + * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, + * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE + * STM32L151xDX, STM32L152xDX, STM32L162xDX + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(((__HANDLE__)->Instance->TAFCR), RTC_TAFCR_TAMPIE) + +/** + * @brief Disable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) + * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) + * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, + * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, + * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE + * STM32L151xDX, STM32L152xDX, STM32L162xDX + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(((__HANDLE__)->Instance->TAFCR), RTC_TAFCR_TAMPIE) + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) + * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) + * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, + * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, + * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE + * STM32L151xDX, STM32L152xDX, STM32L162xDX + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & RTC_TAFCR_TAMPIE) != RESET) ? SET : RESET) /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. @@ -779,15 +884,35 @@ typedef struct */ #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) /** * @brief Get the selected RTC TimeStamp's flag status. @@ -817,11 +942,20 @@ typedef struct * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_TAMP1F + * @arg RTC_FLAG_TAMP2F (*) + * @arg RTC_FLAG_TAMP3F (*) + * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, + * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, + * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE + * STM32L151xDX, STM32L152xDX, STM32L162xDX * @retval None */ #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC)\ + || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA)\ + || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA)\ + || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** * @brief Get the selected RTC shift operation's flag status. * @param __HANDLE__: specifies the RTC handle. @@ -831,7 +965,7 @@ typedef struct * @retval None */ #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @brief Clear the RTC Time Stamp's pending flags. @@ -841,7 +975,7 @@ typedef struct * @arg RTC_FLAG_TSF * @retval None */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** * @brief Clear the RTC Tamper's pending flags. @@ -849,19 +983,183 @@ typedef struct * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_TAMP1F + * @arg RTC_FLAG_TAMP2F (*) + * @arg RTC_FLAG_TAMP3F (*) + * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, + * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, + * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE + * STM32L151xDX, STM32L152xDX, STM32L162xDX * @retval None */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** * @brief Clear the RTC Wake Up timer's pending flags. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. * This parameter can be: - * @arg RTC_FLAG_WUTF + * @arg RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); } while(0); + +/** + * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); } while(0); + +/** + * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the RTC WakeUp Timer associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); } while(0); + +/** + * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); } while(0); + +/** + * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** * @} @@ -887,17 +1185,17 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ /** * @} */ @@ -926,13 +1224,13 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value); HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); #else HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); @@ -956,6 +1254,28 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ + +/** + * @} + */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.c index aeeb6dccb42..4899fc6fa30 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_sd.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -30,14 +30,14 @@ It is used as follows: (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API: - (##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE(); + (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE(); (##) SDIO pins configuration for SD card - (+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE(); + (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init() and according to your pin assignment; (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() and HAL_SD_WriteBlocks_DMA() APIs). - (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE(); + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. (##) NVIC configuration if you need to use interrupt process when using DMA transfer. (+++) Configure the SDIO and DMA interrupt priorities using functions @@ -54,7 +54,7 @@ ================================================ [..] To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - the SD Card and put it into StandBy State (Ready for data transfer). + the SD Card and put it into Standby State (Ready for data transfer). This function provide the following operations: (#) Apply the SD Card initialization process at 400KHz and check the SD Card @@ -94,14 +94,14 @@ ============================== [..] (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function support only 512-byte block length (the block size should be - chosen as 512 byte). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function support only 512-byte block length (the block size should be - chosen as 512 byte). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to call the function HAL_SD_CheckReadOperation(), to insure @@ -111,13 +111,13 @@ =============================== [..] (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function support only 512-byte block length (the block size should be - chosen as 512 byte). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function support only 512-byte block length (the block size should be + This function support only 512-bytes block length (the block size should be chosen as 512 byte). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. @@ -137,7 +137,7 @@ ================================== [..] Below the list of most used macros in SD HAL driver. - + (+) __HAL_SD_SDIO_ENABLE : Enable the SD device (+) __HAL_SD_SDIO_DISABLE : Disable the SD device (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer @@ -153,7 +153,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -183,27 +183,29 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" +#ifdef HAL_SD_MODULE_ENABLED + /** @addtogroup STM32L1xx_HAL_Driver * @{ */ -/** @defgroup SD SD - * @brief SD HAL module driver +/** @addtogroup SD * @{ */ -#ifdef HAL_SD_MODULE_ENABLED #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - -/** @defgroup SD_Private_Define SD Private Define +/** @addtogroup SD_Private_Defines * @{ */ - /** - * @brief SDIO Static flags, TimeOut, FIFO Address + * @brief SDIO Data block size + */ +#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4)) +/** + * @brief SDIO Static flags, Timeout, FIFO Address */ #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ @@ -229,7 +231,7 @@ #define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) #define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) #define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) +#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000) #define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) #define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) #define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) @@ -285,12 +287,9 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SD_Private_Functions SD Private Functions +/** @addtogroup SD_Private_Functions_Prototypes * @{ */ - static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd); static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr); static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); @@ -311,22 +310,21 @@ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma); static void SD_DMA_RxError(DMA_HandleTypeDef *hdma); static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma); static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); - /** * @} */ - -/** @defgroup SD_Exported_Functions SD Exported Functions +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SD_Exported_Functions * @{ */ -/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup SD_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== [..] This section provides functions allowing to initialize/de-initialize the SD card device to be ready for use. @@ -418,6 +416,9 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_MspInit could be implemented in the user file */ @@ -430,6 +431,9 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_MspDeInit could be implemented in the user file */ @@ -439,13 +443,13 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * @} */ -/** @defgroup SD_Exported_Functions_Group2 IO operation functions +/** @addtogroup SD_Exported_Functions_Group2 * @brief Data transfer functions * @verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== + ============================================================================== + ##### IO operation functions ##### + ============================================================================== [..] This subsection provides a set of functions allowing to manage the data transfer from/to SD card. @@ -461,7 +465,7 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * @param pReadBuffer: pointer to the buffer that will contain the received data * @param ReadAddr: Address from where data is to be read * @param BlockSize: SD card Data block size - * This parameter should be 512 + * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of SD blocks to read * @retval SD Card error state */ @@ -500,7 +504,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff /* Configure the SD DPSM (Data Path State Machine) */ sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdio_datainitstructure.DataBlockSize = (uint32_t)(9 << 4); + sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE; sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; @@ -645,7 +649,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuff * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit * @param WriteAddr: Address from where data is to be written * @param BlockSize: SD card Data block size - * This parameter should be 512. + * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of SD blocks to write * @retval SD Card error state */ @@ -863,7 +867,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBu * @param pReadBuffer: Pointer to the buffer that will contain the received data * @param ReadAddr: Address from where data is to be read * @param BlockSize: SD card Data block size - * This paramater should be 512. + * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of blocks to read. * @retval SD Card error state */ @@ -906,7 +910,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead hsd->hdmarx->XferErrorCallback = SD_DMA_RxError; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)); + HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4); if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { @@ -980,7 +984,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pRead * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit * @param WriteAddr: Address from where data is to be read * @param BlockSize: the SD card Data block size - * This parameter should be 512. + * @note BlockSize must be 512 bytes. * @param NumberOfBlocks: Number of blocks to write * @retval SD Card error state */ @@ -1020,7 +1024,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWri hsd->hdmatx->XferErrorCallback = SD_DMA_TxError; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)); + HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4); /* Enable SDIO DMA transfer */ __HAL_SD_SDIO_DMA_ENABLE(); @@ -1308,7 +1312,7 @@ HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint { } - /* Wait untill the card is in programming state */ + /* Wait until the card is in programming state */ errorstate = SD_IsCardProgramming(hsd, &cardstate); delay = SD_DATATIMEOUT; @@ -1402,6 +1406,9 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_XferCpltCallback could be implemented in the user file */ @@ -1414,6 +1421,9 @@ __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_XferErrorCallback could be implemented in the user file */ @@ -1427,6 +1437,9 @@ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) */ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_RxCpltCallback could be implemented in the user file */ @@ -1440,6 +1453,9 @@ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) */ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_RxErrorCallback could be implemented in the user file */ @@ -1453,6 +1469,9 @@ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) */ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_TxCpltCallback could be implemented in the user file */ @@ -1466,6 +1485,9 @@ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) */ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_DMA_TxErrorCallback could be implemented in the user file */ @@ -1475,7 +1497,7 @@ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup SD_Exported_Functions_Group3 * @brief management functions * @verbatim @@ -1588,7 +1610,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy /* Byte 10 */ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); - pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024; + pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024); pCardInfo->CardBlockSize = 512; } else @@ -1716,7 +1738,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode) { HAL_SD_ErrorTypedef errorstate = SD_OK; - SDIO_InitTypeDef init; + SDIO_InitTypeDef tmpinit; /* MMC Card does not support this feature */ if (hsd->CardType == MULTIMEDIA_CARD) @@ -1747,15 +1769,15 @@ HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32 if (errorstate == SD_OK) { /* Configure the SDIO peripheral */ - init.ClockEdge = hsd->Init.ClockEdge; - init.ClockBypass = hsd->Init.ClockBypass; - init.ClockPowerSave = hsd->Init.ClockPowerSave; - init.BusWide = WideMode; - init.HardwareFlowControl = hsd->Init.HardwareFlowControl; - init.ClockDiv = hsd->Init.ClockDiv; + tmpinit.ClockEdge = hsd->Init.ClockEdge; + tmpinit.ClockBypass = hsd->Init.ClockBypass; + tmpinit.ClockPowerSave = hsd->Init.ClockPowerSave; + tmpinit.BusWide = WideMode; + tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl; + tmpinit.ClockDiv = hsd->Init.ClockDiv; /* Configure SDIO peripheral interface */ - SDIO_Init(hsd->Instance, init); + SDIO_Init(hsd->Instance, tmpinit); } else { @@ -1944,7 +1966,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) * @} */ -/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions +/** @addtogroup SD_Exported_Functions_Group4 * @brief Peripheral State functions * @verbatim @@ -2019,13 +2041,13 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ + /* Send ACMD13 (SD_APP_STATUS) with argument as card's RCA */ sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STAUS; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS; SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS); + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS); if (errorstate != SD_OK) { @@ -2081,7 +2103,7 @@ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstat else { /* No error flag set */ - } + } count = SD_DATATIMEOUT; while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) @@ -2214,11 +2236,12 @@ HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatu /** * @} */ - + +/* Private function ----------------------------------------------------------*/ /** @addtogroup SD_Private_Functions * @{ */ - + /** * @brief SD DMA transfer complete Rx callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -2237,6 +2260,9 @@ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) { } + /* Disable the DMA channel */ + HAL_DMA_Abort(hdma); + /* Transfer complete user callback */ HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); } @@ -2272,7 +2298,10 @@ static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) while(hsd->SdTransferCplt == 0) { } - + + /* Disable the DMA channel */ + HAL_DMA_Abort(hdma); + /* Transfer complete user callback */ HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); } @@ -2403,7 +2432,7 @@ static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) } /** - * @brief Selects od Deselects the corresponding card. + * @brief Selects of Deselects the corresponding card. * @param hsd: SD handle * @param addr: Address of the card to be selected * @retval SD Card error state @@ -2448,6 +2477,10 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) /* Set Power State to ON */ SDIO_PowerState_ON(hsd->Instance); + /* 1ms: required power up waiting time before starting the SD initialization + sequence */ + HAL_Delay(1); + /* Enable SDIO Clock */ __HAL_SD_SDIO_ENABLE(); @@ -2465,7 +2498,7 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) if(errorstate != SD_OK) { - /* CMD Response TimeOut (wait for CMDSENT flag) */ + /* CMD Response Timeout (wait for CMDSENT flag) */ return errorstate; } @@ -2498,7 +2531,7 @@ static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) /* Check for error conditions */ errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - /* If errorstate is Command TimeOut, it is a MMC card */ + /* If errorstate is Command Timeout, it is a MMC card */ /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) or SD card 1.x */ if(errorstate == SD_OK) @@ -2593,7 +2626,7 @@ static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardS SDIO_CmdInitTypeDef sdio_cmdinitstructure; HAL_SD_ErrorTypedef errorstate = SD_OK; - if(pCardStatus == HAL_NULL) + if(pCardStatus == NULL) { errorstate = SD_INVALID_PARAMETER; @@ -2822,7 +2855,7 @@ static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CM return(SD_STREAM_WRITE_OVERRUN); } - if((response_r1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) + if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) { return(SD_CID_CSD_OVERWRITE); } @@ -3393,7 +3426,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t * return(SD_STREAM_WRITE_OVERRUN); } - if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) + if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) { return(SD_CID_CSD_OVERWRITE); } @@ -3424,7 +3457,7 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t * /** * @} */ - + #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ #endif /* HAL_SD_MODULE_ENABLED */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.h index 42d86ce1e42..c7a673b4e91 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_sd.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of SD HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -52,15 +52,19 @@ * @{ */ -/** @addtogroup SD +/** @defgroup SD SD + * @brief SD HAL module driver * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup SD_Exported_Types SD Exported Types * @{ */ +/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition + * @{ + */ #define SD_InitTypeDef SDIO_InitTypeDef #define SD_TypeDef SDIO_TypeDef @@ -96,9 +100,12 @@ typedef struct DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ }SD_HandleTypeDef; - /** - * @brief Card Specific Data: CSD Register + * @} + */ + +/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register + * @{ */ typedef struct { @@ -141,10 +148,13 @@ typedef struct __IO uint8_t Reserved4; /*!< Always 1 */ }HAL_SD_CSDTypedef; - /** - * @brief Card Identification Data: CID Register + * @} */ + +/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register + * @{ + */ typedef struct { __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ @@ -159,10 +169,13 @@ typedef struct __IO uint8_t Reserved2; /*!< Always 1 */ }HAL_SD_CIDTypedef; - /** - * @brief SD Card Status returned by ACMD13 + * @} */ + +/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 + * @{ + */ typedef struct { __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */ @@ -177,10 +190,13 @@ typedef struct __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */ }HAL_SD_CardStatusTypedef; - /** - * @brief SD Card information structure + * @} */ + +/** @defgroup SD_Exported_Types_Group5 SD Card information structure + * @{ + */ typedef struct { HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */ @@ -191,10 +207,13 @@ typedef struct uint8_t CardType; /*!< SD card type */ }HAL_SD_CardInfoTypedef; - /** - * @brief SD Error status enumeration Structure definition + * @} */ + +/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition + * @{ + */ typedef enum { /** @@ -248,10 +267,13 @@ typedef enum SD_OK = (0) }HAL_SD_ErrorTypedef; - /** - * @brief SD Transfer state enumeration structure - */ + * @} + */ + +/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure + * @{ + */ typedef enum { SD_TRANSFER_OK = 0, /*!< Transfer success */ @@ -259,10 +281,13 @@ typedef enum SD_TRANSFER_ERROR = 2 /*!< Transfer failed */ }HAL_SD_TransferStateTypedef; - /** - * @brief SD Card State enumeration structure - */ + * @} + */ + +/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure + * @{ + */ typedef enum { SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */ @@ -276,10 +301,13 @@ typedef enum SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */ }HAL_SD_CardStateTypedef; - /** - * @brief SD Operation enumeration structure - */ + * @} + */ + +/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure + * @{ + */ typedef enum { SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */ @@ -288,6 +316,9 @@ typedef enum SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */ }HAL_SD_OperationTypedef; +/** + * @} + */ /** * @} @@ -360,7 +391,7 @@ typedef enum */ #define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ +#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ #define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ #define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to @@ -614,12 +645,11 @@ typedef enum */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup SD_Exported_Functions +/** @defgroup SD_Exported_Functions SD Exported Functions * @{ */ -/* Initialization and de-initialization functions **********************************/ -/** @addtogroup SD_Exported_Functions_Group1 +/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo); @@ -630,8 +660,7 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); * @} */ -/* I/O operation functions *****************************************************/ -/** @addtogroup SD_Exported_Functions_Group2 +/** @defgroup SD_Exported_Functions_Group2 I/O operation functions * @{ */ /* Blocking mode: Polling */ @@ -658,9 +687,8 @@ HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Ti /** * @} */ - -/* Peripheral Control functions ************************************************/ -/** @addtogroup SD_Exported_Functions_Group3 + +/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions * @{ */ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo); @@ -671,8 +699,8 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd); * @} */ -/* Peripheral State functions **************************************************/ -/** @addtogroup SD_Exported_Functions_Group4 +/* Peripheral State functions ************************************************/ +/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions * @{ */ HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); @@ -681,19 +709,82 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); /** * @} */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup SD_Private_Types SD Private Types + * @{ + */ /** * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SD_Private_Defines SD Private Defines + * @{ */ - + /** * @} */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup SD_Private_Variables SD Private Variables + * @{ + */ /** * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SD_Private_Constants SD Private Constants + * @{ */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SD_Private_Macros SD Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.c index 0e84648a90a..093c04072d5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_smartcard.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -21,10 +21,10 @@ (#) Declare a SMARTCARD_HandleTypeDef handle structure. (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: - (##) Enable the USARTx interface clock. + (##) Enable the interface clock of the USARTx associated to the SMARTCARD. (##) SMARTCARD pins configuration: (+++) Enable the clock for the SMARTCARD GPIOs. - (+++) Configure these SMARTCARD pins as alternate function pull-up. + (+++) Configure the SMARTCARD pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -37,6 +37,8 @@ (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. @@ -92,6 +94,7 @@ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether the specified SMARTCARD interrupt has occurred or not [..] (@) You can refer to the SMARTCARD HAL driver header file for more useful macros @@ -100,7 +103,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -143,15 +146,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ -#define SMARTCARD_TIMEOUT_VALUE 22000 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ +/* Private macros --------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions @@ -175,7 +170,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe * @{ */ -/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions +/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -199,11 +194,6 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe (++) Word Length => Should be 9 bits (8 bits + parity) (++) Stop Bit (++) Parity: => Should be enabled - +-------------------------------------------------------------+ - | M bit | PCE bit | SMARTCARD frame | - |---------------------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ (++) USART polarity (++) USART phase (++) USART LastBit @@ -221,7 +211,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe [..] Please refer to the ISO 7816-3 specification for more details. - -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended + (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop bits for both transmitting and receiving to avoid switching between the two configurations. [..] @@ -232,6 +222,15 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe * @{ */ +/* + Additionnal remark on the smartcard frame: + +-------------------------------------------------------------+ + | M bit | PCE bit | SMARTCARD frame | + |---------------------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ +*/ + /** * @brief Initializes the SmartCard mode according to the specified * parameters in the SMARTCARD_HandleTypeDef and create the associated handle. @@ -242,7 +241,15 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) { /* Check the SMARTCARD handle allocation */ - if(hsc == HAL_NULL) + if(hsc == NULL) + { + return HAL_ERROR; + } + + /* Check Wordlength, Parity and Stop bits parameters */ + if ( (!(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength))) + ||(!(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits))) + ||(!(IS_SMARTCARD_PARITY(hsc->Init.Parity))) ) { return HAL_ERROR; } @@ -250,15 +257,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState)); + assert_param(IS_SMARTCARD_PRESCALER(hsc->Init.Prescaler)); if(hsc->State == HAL_SMARTCARD_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hsc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_SMARTCARD_MspInit(hsc); } hsc->State = HAL_SMARTCARD_STATE_BUSY; + /* Disable the Peripheral */ + __HAL_SMARTCARD_DISABLE(hsc); + /* Set the Prescaler */ MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler); @@ -274,12 +288,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN); CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); - - /* Enable the SMARTCARD Framing Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - /* Enable the Peripharal */ __HAL_SMARTCARD_ENABLE(hsc); @@ -305,7 +313,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) { /* Check the SMARTCARD handle allocation */ - if(hsc == HAL_NULL) + if(hsc == NULL) { return HAL_ERROR; } @@ -318,6 +326,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /* Disable the Peripheral */ __HAL_SMARTCARD_DISABLE(hsc); + hsc->Instance->CR1 = 0x0; + hsc->Instance->CR2 = 0x0; + hsc->Instance->CR3 = 0x0; + hsc->Instance->BRR = 0x0; + hsc->Instance->GTPR = 0x0; + /* DeInit the low level hardware */ HAL_SMARTCARD_MspDeInit(hsc); @@ -336,8 +350,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) +__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspInit can be implemented in the user file */ @@ -349,8 +366,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) +__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspDeInit can be implemented in the user file */ @@ -371,25 +391,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. [..] - Smartcard is a single wire half duplex communication protocol. + (#) Smartcard is a single wire half duplex communication protocol. The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. The USART should be configured as: - - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register - - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + defined in the ISO 7816-3 standard. + (#) The USART should be configured as: + (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. + or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the Transmit or Receive process + will be executed respectively at the end of the Transmit or Receive process The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication - error is detected + error is detected. (#) Blocking mode APIs are : (++) HAL_SMARTCARD_Transmit() @@ -424,13 +445,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -453,31 +473,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * hsc->TxXferCount = Size; while(hsc->TxXferCount > 0) { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData; - WRITE_REG(hsc->Instance->DR, (*tmp & (uint16_t)0x01FF)); - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - pData +=2; - } - else - { - pData +=1; - } - } - else - { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF)); + return HAL_TIMEOUT; } + WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF)); hsc->TxXferCount--; } @@ -517,13 +517,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -548,39 +547,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p /* Check the remain data to be received */ while(hsc->RxXferCount > 0) { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) - { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData; - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF); - pData +=2; - } - else - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF); - pData +=1; - } - } - else + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F); - } + return HAL_TIMEOUT; } + *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); hsc->RxXferCount--; } @@ -615,12 +586,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -643,15 +614,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; } - /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); + /* Process Unlocked */ + __HAL_UNLOCK(hsc); /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - /* Enable the SMARTCARD Transmit data register empty Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE); @@ -673,12 +641,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -701,6 +669,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; } + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + /* Enable the SMARTCARD Data Register not empty Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); @@ -710,9 +681,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - return HAL_OK; } else @@ -732,12 +700,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { uint32_t *tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -770,6 +738,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the SMARTCARD CR3 register */ SET_BIT(hsc->Instance->CR3,USART_CR3_DMAT); @@ -797,12 +768,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { uint32_t *tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -857,64 +828,58 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) { - uint32_t tmp1 = 0, tmp2 = 0; + uint32_t tmp_flag = 0, tmp_it_source = 0; - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE); + tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE); + tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE); /* SMARTCARD parity error interrupt occurred -----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_SMARTCARD_CLEAR_PEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); + tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE); + tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); /* SMARTCARD frame error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_SMARTCARD_CLEAR_FEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); + tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE); /* SMARTCARD noise error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_SMARTCARD_CLEAR_NEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); + tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE); /* SMARTCARD Over-Run interrupt occurred ---------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE); + tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE); + tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE); /* SMARTCARD in mode Receiver --------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { SMARTCARD_Receive_IT(hsc); } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE); + tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE); + tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE); /* SMARTCARD in mode Transmitter -----------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { SMARTCARD_Transmit_IT(hsc); } - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC); + tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC); + tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC); /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { SMARTCARD_EndTransmit_IT(hsc); } @@ -922,6 +887,9 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /* Call the Error call Back in case of Errors */ if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) { + /* Clear all the error flag at once */ + __HAL_SMARTCARD_CLEAR_PEFLAG(hsc); + /* Set the SMARTCARD state ready to be able to start again the process */ hsc->State= HAL_SMARTCARD_STATE_READY; HAL_SMARTCARD_ErrorCallback(hsc); @@ -929,39 +897,48 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) } /** - * @brief Tx Transfer completed callbacks. + * @brief Tx Transfer completed callback. * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file */ } /** - * @brief Rx Transfer completed callbacks. + * @brief Rx Transfer completed callback. * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file */ } /** - * @brief SMARTCARD error callbacks. + * @brief SMARTCARD error callback. * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE: This function should not be modified, when the callback is needed, the HAL_SMARTCARD_ErrorCallback can be implemented in the user file */ @@ -1040,27 +1017,8 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) in the SMARTCARD CR3 register */ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); - /* Wait for SMARTCARD TC Flag */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - hsc->State = HAL_SMARTCARD_STATE_TIMEOUT; - HAL_SMARTCARD_ErrorCallback(hsc); - } - else - { - /* No Timeout */ - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - HAL_SMARTCARD_TxCpltCallback(hsc); - } + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC); } /** @@ -1186,29 +1144,12 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe */ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) { - uint16_t* tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX)) { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) - { - tmp = (uint16_t*) hsc->pTxBuffPtr; - WRITE_REG(hsc->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - hsc->pTxBuffPtr += 2; - } - else - { - hsc->pTxBuffPtr += 1; - } - } - else - { - WRITE_REG(hsc->Instance->DR, (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF)); - } + WRITE_REG(hsc->Instance->DR, (*hsc->pTxBuffPtr++ & (uint8_t)0xFF)); if(--hsc->TxXferCount == 0) { @@ -1249,9 +1190,6 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); - hsmartcard->State = HAL_SMARTCARD_STATE_READY; } @@ -1269,37 +1207,12 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar */ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) { - uint16_t* tmp = 0; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + tmp_state = hsc->State; + if((tmp_state == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX)) { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) - { - tmp = (uint16_t*) hsc->pRxBuffPtr; - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF); - hsc->pRxBuffPtr += 2; - } - else - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF); - hsc->pRxBuffPtr += 1; - } - } - else - { - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); - } - else - { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F); - } - } + *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); if(--hsc->RxXferCount == 0) { @@ -1342,7 +1255,6 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) { /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity)); assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase)); assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); @@ -1357,7 +1269,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */ CLEAR_BIT(hsc->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE)); - /*-------------------------- SMARTCARD CR2 Configuration ------------------------*/ + /*------ SMARTCARD-associated USART registers setting : CR2 Configuration ------*/ /* Clear CLKEN, CPOL, CPHA and LBCL bits */ /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/ /* Set CPOL bit according to hsc->Init.CLKPolarity value */ @@ -1370,21 +1282,21 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */ MODIFY_REG(hsc->Instance->CR2, USART_CR2_STOP,(uint32_t)(hsc->Init.StopBits)); - /*-------------------------- SMARTCARD CR1 Configuration -----------------------*/ + /*------ SMARTCARD-associated USART registers setting : CR1 Configuration ------*/ /* Clear M, PCE, PS, TE and RE bits */ /* Configure the SMARTCARD Word Length, Parity and mode: - Set the M bits according to hsc->Init.WordLength value - Set PCE and PS bits according to hsc->Init.Parity value + Set the M according to hsc->Init.WordLength value (forced to 1 as 9B data frame should be selected) + Set PCE and PS bits according to hsc->Init.Parity value (PCE bit forced to 1 as parity control should always be enabled) Set TE and RE bits according to hsc->Init.Mode value */ MODIFY_REG(hsc->Instance->CR1, ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), - ((uint32_t)(hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode)) ); + ((uint32_t)(USART_CR1_M | USART_CR1_PCE | hsc->Init.Parity | hsc->Init.Mode)) ); - /*-------------------------- USART CR3 Configuration -----------------------*/ + /*------ SMARTCARD-associated USART registers setting : CR3 Configuration ------*/ /* Clear CTSE and RTSE bits */ CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); - /*-------------------------- USART BRR Configuration -----------------------*/ + /*------ SMARTCARD-associated USART registers setting : BRR Configuration ------*/ if(hsc->Instance == USART1) { hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.h index dd03d4b1b6e..17188c3e794 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_hal_smartcard.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief This file contains all the functions prototypes for the SMARTCARD * firmware library. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -68,8 +68,8 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate. The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (hsc->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ + - IntegerDivider = ((PCLKx) / (16 * (hsmartcard->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref SMARTCARD_Word_Length */ @@ -77,14 +77,14 @@ typedef struct uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref SMARTCARD_Stop_Bits */ - uint32_t Parity; /*!< Specifies the parity mode. + uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref SMARTCARD_Parity @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).*/ - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref SMARTCARD_Mode */ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. @@ -97,11 +97,14 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler - This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ + uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock + to provide the smartcard clock. The value given in the register + (5 significant bits) is multiplied by 2 to give the division factor of + the source clock frequency; + This parameter can be a value of @ref SMARTCARD_Prescaler */ - uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time - This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ + uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number + of baud clocks */ uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state This parameter can be a value of @ref SMARTCARD_NACK_State */ @@ -122,49 +125,37 @@ typedef enum HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ }HAL_SMARTCARD_StateTypeDef; -/** - * @brief HAL SMARTCARD Error Code structure definition - */ -typedef enum -{ - HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ - HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ - HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ - HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ - HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_SMARTCARD_ErrorTypeDef; /** * @brief SMARTCARD handle Structure definition */ typedef struct { - USART_TypeDef *Instance; /* USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ - SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */ + SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ - uint16_t TxXferSize; /* SmartCard Tx Transfer size */ + uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ - uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */ + uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ - uint16_t RxXferSize; /* SmartCard Rx Transfer size */ + uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ - uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */ + uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */ + __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */ - __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SmartCard Error code */ + __IO uint32_t ErrorCode; /*!< SmartCard Error code */ }SMARTCARD_HandleTypeDef; /** @@ -176,12 +167,26 @@ typedef struct * @{ */ +/** @defgroup SMARTCARD_Error_Codes SMARTCARD Error Codes + * @{ + */ +#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ + +/** + * @} + */ + + /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ -#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000) #define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) + /** * @} */ @@ -189,12 +194,8 @@ typedef struct /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits * @{ */ -#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000) #define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) -#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) #define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) -#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \ - ((STOPBITS) == SMARTCARD_STOPBITS_1_5)) /** * @} */ @@ -202,11 +203,8 @@ typedef struct /** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ */ -#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000) #define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ - ((PARITY) == SMARTCARD_PARITY_ODD)) /** * @} */ @@ -217,7 +215,6 @@ typedef struct #define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) #define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) #define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) /** * @} */ @@ -227,7 +224,6 @@ typedef struct */ #define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) #define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) -#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) /** * @} */ @@ -237,7 +233,6 @@ typedef struct */ #define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) #define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) -#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) /** * @} */ @@ -247,8 +242,15 @@ typedef struct */ #define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) #define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) -#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ - ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method + * @{ + */ +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /** * @} */ @@ -256,10 +258,8 @@ typedef struct /** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State * @{ */ -#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000) -#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \ - ((NACK) == SMARTCARD_NACK_DISABLED)) +#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) +#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) /** * @} */ @@ -268,56 +268,89 @@ typedef struct * @{ */ -#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) -#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) +#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) +#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) /** * @} */ +/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler + * @{ + */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001) /*!< SYSCLK divided by 2 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002) /*!< SYSCLK divided by 4 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003) /*!< SYSCLK divided by 6 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004) /*!< SYSCLK divided by 8 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005) /*!< SYSCLK divided by 10 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006) /*!< SYSCLK divided by 12 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007) /*!< SYSCLK divided by 14 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008) /*!< SYSCLK divided by 16 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009) /*!< SYSCLK divided by 18 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000A) /*!< SYSCLK divided by 20 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000B) /*!< SYSCLK divided by 22 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000C) /*!< SYSCLK divided by 24 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000D) /*!< SYSCLK divided by 26 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000E) /*!< SYSCLK divided by 28 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000F) /*!< SYSCLK divided by 30 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010) /*!< SYSCLK divided by 32 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011) /*!< SYSCLK divided by 34 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012) /*!< SYSCLK divided by 36 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013) /*!< SYSCLK divided by 38 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014) /*!< SYSCLK divided by 40 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015) /*!< SYSCLK divided by 42 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016) /*!< SYSCLK divided by 44 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017) /*!< SYSCLK divided by 46 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018) /*!< SYSCLK divided by 48 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019) /*!< SYSCLK divided by 50 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001A) /*!< SYSCLK divided by 52 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001B) /*!< SYSCLK divided by 54 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001C) /*!< SYSCLK divided by 56 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001D) /*!< SYSCLK divided by 58 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001E) /*!< SYSCLK divided by 60 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001F) /*!< SYSCLK divided by 62 */ +/** + * @} + */ + + + /** @defgroup SMARTCARD_Flags SMARTCARD Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the SR register * @{ */ -#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC) -#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE) -#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE) -#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE) +#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC) +#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE) +#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE) +#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE) /** * @} */ /** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register + * - XXXX : Interrupt mask (16 bits) in the Y register * - Y : Interrupt source register (4 bits) - * - 01: CR1 register - * - 10: CR3 register + * - 0001: CR1 register + * - 0010: CR3 register * * @{ */ -#define SMARTCARD_IT_PE ((uint32_t)0x10000100) -#define SMARTCARD_IT_TXE ((uint32_t)0x10000080) -#define SMARTCARD_IT_TC ((uint32_t)0x10000040) -#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020) -#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010) -#define SMARTCARD_IT_ERR ((uint32_t)0x20000001) -/** - * @} - */ +#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) +#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) +#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) +#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) +#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) +#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE)) -/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask - * @{ - */ -#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF) /** * @} */ @@ -325,7 +358,8 @@ typedef struct /** * @} */ - + + /* Exported macro ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros * @{ @@ -334,22 +368,23 @@ typedef struct /** @brief Reset SMARTCARD handle state * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) -/** @brief Flushs the Smartcard DR register +/** @brief Flush the Smartcard DR register * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). + * @retval None */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) -/** @brief Checks whether the specified Smartcard flag is set or not. +/** @brief Check whether the specified Smartcard flag is set or not. * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag * @arg SMARTCARD_FLAG_TC: Transmission Complete flag * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag @@ -362,13 +397,14 @@ typedef struct */ #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -/** @brief Clears the specified Smartcard pending flags. +/** @brief Clear the specified Smartcard pending flags. * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __FLAG__: specifies the flag to check. - * This parameter can be any combination of the following values: + * This parameter can be any combination of the following values: * @arg SMARTCARD_FLAG_TC: Transmission Complete flag. * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag. + * @retval None * * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun * error) flags are cleared by software sequence: a read operation to @@ -384,42 +420,50 @@ typedef struct /** @brief Clear the SMARTCARD PE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ -#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ +}while(0) + + + /** @brief Clear the SMARTCARD FE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD NE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD ORE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD IDLE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) -/** @brief Enables the specified SmartCard interrupt. +/** @brief Enable the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt @@ -428,13 +472,14 @@ typedef struct * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt * @arg SMARTCARD_IT_PE: Parity Error interrupt * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK))) -/** @brief Disables the specified SmartCard interrupts. +/** @brief Disable the specified SmartCard interrupts. * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. * This parameter can be one of the following values: * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt @@ -444,12 +489,12 @@ typedef struct * @arg SMARTCARD_IT_PE: Parity Error interrupt * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK))) -/** @brief Checks whether the specified SmartCard interrupt has occurred or not. +/** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __IT__: specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt @@ -460,54 +505,121 @@ typedef struct * @arg SMARTCARD_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) + +/** @brief Enables the SMARTCARD one bit sample method + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR3, (USART_CR3_ONEBIT))) + +/** @brief Disables the SMARTCARD one bit sample method + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (USART_CR3_ONEBIT))) /** @brief Enable the USART associated to the SMARTCARD Handle * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) /** @brief Disable the USART associated to the SMARTCARD Handle * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) +/** @brief Enable the SmartCard DMA request. + * @param __HANDLE__: specifies the SmartCard Handle. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). + * @param __REQUEST__: specifies the SmartCard DMA request. + * This parameter can be one of the following values: + * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request + * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request + * @retval None + */ +#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) + +/** @brief Disable the SmartCard DMA request. + * @param __HANDLE__: specifies the SmartCard Handle. + * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). + * @param __REQUEST__: specifies the SmartCard DMA request. + * This parameter can be one of the following values: + * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request + * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request + * @retval None + */ +#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) + /** * @} */ + /* Private macros --------------------------------------------------------*/ /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros * @{ */ -/** @brief Macros to enable or disable the SmartCard DMA request. - * @param __HANDLE__: specifies the SmartCard Handle. - * @param __REQUEST__: specifies the SmartCard DMA request. - * This parameter can be one of the following values: - * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request - * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request - */ -#define SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) -#define SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) +#define SMARTCARD_CR1_REG_INDEX 1 +#define SMARTCARD_CR3_REG_INDEX 3 #define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) #define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100) #define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -#define SMARTCARD_BRR(__PCLK__, __BAUD__) ((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) - -/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the - * maximum clock on L1 (i.e. 32 MHz) divided by the oversampling used - * on the SMARTCARD (i.e. 16). No overSampling by 16 on Smartcard. - * @param __BAUDRATE__: Baud rate set by the configuration function. - * @retval Test result (TRUE or FALSE) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */ +#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \ + (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \ + (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F)) + +/** Check the Baud rate range. + * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) + * divided by the smallest oversampling used on the USART (i.e. 16) + * __BAUDRATE__: Baud rate set by the configuration function. + * Return : TRUE or FALSE */ #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001) + +#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) + +#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \ + ((STOPBITS) == SMARTCARD_STOPBITS_1_5)) + +#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ + ((PARITY) == SMARTCARD_PARITY_ODD)) + +#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (~((uint32_t)SMARTCARD_MODE_TX_RX))) == 0x00) && \ + ((MODE) != (uint32_t)0x00000000)) + +#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) + +#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) + +#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ + ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) + +#define IS_SMARTCARD_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ + ((ONEBIT) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) + +#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \ + ((NACK) == SMARTCARD_NACK_DISABLE)) + +#define IS_SMARTCARD_PRESCALER(PRESCALER) (((PRESCALER) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ + ((PRESCALER) <= SMARTCARD_PRESCALER_SYSCLK_DIV62) ) + +/** SMARTCARD interruptions flag mask + * + */ +#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ + USART_CR1_IDLEIE | USART_CR3_EIE ) + + /** * @} */ @@ -519,13 +631,12 @@ typedef struct * @{ */ -/** @addtogroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions +/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc); -HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc); HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c index b4a3db40525..4b3609598f2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_spi.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief SPI HAL module driver. * * This file provides firmware functions to manage the following @@ -59,7 +59,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -182,6 +182,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef * */ __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + return HAL_ERROR; } @@ -194,7 +197,7 @@ __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ - if(hspi == HAL_NULL) + if(hspi == NULL) { return HAL_ERROR; } @@ -222,6 +225,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_MspInit could be implenetd in the user file */ @@ -235,6 +241,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_MspDeInit could be implenetd in the user file */ @@ -261,38 +270,16 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode APIs are : - (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive() in full duplex mode - - (#) Non Blocking mode API's with Interrupt are : - (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive_IT()in full duplex mode - (++) HAL_SPI_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SPI_TxCpltCallback() - (++) HAL_SPI_RxCpltCallback() - (++) HAL_SPI_TxRxCpltCallback() - (++) HAL_SPI_TxHalfCpltCallback() - (++) HAL_SPI_RxHalfCpltCallback() - (++) HAL_SPI_TxRxHalfCpltCallback() - (++) HAL_SPI_ErrorCallback() + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. @endverbatim * @{ @@ -312,7 +299,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -334,12 +321,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /*Init field not used in handle to zero */ hspi->TxISR = 0; hspi->RxISR = 0; - hspi->pRxBuffPtr = HAL_NULL; + hspi->pRxBuffPtr = NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -376,7 +363,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->TxXferCount--; } /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -402,7 +389,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->TxXferCount--; } /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -456,7 +443,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -475,7 +462,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /*Init field not used in handle to zero */ hspi->RxISR = 0; hspi->TxISR = 0; - hspi->pTxBuffPtr = HAL_NULL; + hspi->pTxBuffPtr = NULL; hspi->TxXferSize = 0; hspi->TxXferCount = 0; @@ -486,7 +473,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -522,7 +509,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->RxXferCount--; } /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -543,7 +530,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->RxXferCount--; } /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -569,7 +556,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->RxXferCount--; /* Wait until RXNE flag is set: CRC Received */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { @@ -579,6 +566,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Read CRC to Flush RXNE flag */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); } if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) @@ -590,7 +578,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->State = HAL_SPI_STATE_READY; /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -630,7 +618,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) { - if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -663,7 +651,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxISR = 0; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -687,7 +675,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -717,7 +705,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxXferCount--; /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -758,7 +746,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -786,7 +774,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxXferCount--; /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } @@ -815,7 +803,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -825,6 +813,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Read CRC */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); } /* Wait until Busy flag is reset before disabling SPI */ @@ -837,12 +826,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->State = HAL_SPI_STATE_READY; /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -876,7 +865,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -898,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /*Init field not used in handle to zero */ hspi->RxISR = 0; - hspi->pRxBuffPtr = HAL_NULL; + hspi->pRxBuffPtr = NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; @@ -909,7 +898,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -952,7 +941,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -971,7 +960,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /*Init field not used in handle to zero */ hspi->TxISR = 0; - hspi->pTxBuffPtr = HAL_NULL; + hspi->pTxBuffPtr = NULL; hspi->TxXferSize = 0; hspi->TxXferCount = 0; @@ -990,7 +979,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -1035,7 +1024,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p if((hspi->State == HAL_SPI_STATE_READY) || \ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) { - if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -1066,7 +1055,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->RxXferCount = Size; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -1104,7 +1093,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1126,7 +1115,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /*Init field not used in handle to zero */ hspi->TxISR = 0; hspi->RxISR = 0; - hspi->pRxBuffPtr = HAL_NULL; + hspi->pRxBuffPtr = NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; @@ -1137,7 +1126,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -1188,7 +1177,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1207,7 +1196,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /*Init field not used in handle to zero */ hspi->RxISR = 0; hspi->TxISR = 0; - hspi->pTxBuffPtr = HAL_NULL; + hspi->pTxBuffPtr = NULL; hspi->TxXferSize = 0; hspi->TxXferCount = 0; @@ -1226,7 +1215,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -1279,7 +1268,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if((hspi->State == HAL_SPI_STATE_READY) || \ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) { - if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -1312,7 +1301,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->TxISR = 0; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -1342,7 +1331,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - /* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing is performed in DMA reception complete callback */ if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) { @@ -1351,7 +1340,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } else { - hspi->hdmatx->XferErrorCallback = HAL_NULL; + hspi->hdmatx->XferErrorCallback = NULL; } /* Enable the Tx DMA Channel */ @@ -1436,12 +1425,12 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) */ /* Abort the SPI DMA tx Channel */ - if(hspi->hdmatx != HAL_NULL) + if(hspi->hdmatx != NULL) { HAL_DMA_Abort(hspi->hdmatx); } /* Abort the SPI DMA rx Channel */ - if(hspi->hdmarx != HAL_NULL) + if(hspi->hdmarx != NULL) { HAL_DMA_Abort(hspi->hdmarx); } @@ -1527,6 +1516,9 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_TxCpltCallback could be implenetd in the user file */ @@ -1540,6 +1532,9 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_RxCpltCallback() could be implenetd in the user file */ @@ -1553,6 +1548,9 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file */ @@ -1566,6 +1564,9 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file */ @@ -1579,6 +1580,9 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file */ @@ -1592,6 +1596,9 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file */ @@ -1605,6 +1612,9 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : - This function Should not be modified, when the callback is needed, the HAL_SPI_ErrorCallback() could be implenetd in the user file. - The ErrorCode parameter in the hspi handle is updated by the SPI processes @@ -1648,7 +1658,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI Error Code */ -HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) { return hspi->ErrorCode; } @@ -1752,7 +1762,7 @@ static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi) if(hspi->TxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* calculate and transfer CRC on Tx line */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); @@ -1771,7 +1781,7 @@ static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi) { __IO uint16_t tmpreg = 0; - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until RXNE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) @@ -1781,6 +1791,7 @@ static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi) /* Read CRC to reset RXNE flag */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* Wait until RXNE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) @@ -1889,7 +1900,7 @@ static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount--; /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set CRC Next to calculate CRC on Rx side */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); @@ -1978,7 +1989,7 @@ static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma) CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until RXNE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) @@ -1988,6 +1999,7 @@ static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma) /* Read CRC */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) @@ -2037,7 +2049,7 @@ static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma) if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) { /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Check if CRC is done on going (RXNE flag set) */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) @@ -2050,6 +2062,7 @@ static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma) } /* Read CRC */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) @@ -2143,7 +2156,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA module. * @retval None */ -static void SPI_DMAError(DMA_HandleTypeDef *hdma) +static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hspi->TxXferCount = 0; @@ -2189,7 +2202,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef * __HAL_SPI_DISABLE(hspi); /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -2223,7 +2236,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef * __HAL_SPI_DISABLE(hspi); /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h index 92fc0444a1f..ddf1dcda438 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_spi.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -118,21 +118,6 @@ typedef enum }HAL_SPI_StateTypeDef; -/** - * @brief HAL SPI Error Code structure definition - */ -typedef enum -{ - HAL_SPI_ERROR_NONE = 0x00, /*!< No error */ - HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */ - HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */ - HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */ - HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */ - HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */ - -}HAL_SPI_ErrorTypeDef; - /** * @brief SPI handle Structure definition */ @@ -166,7 +151,7 @@ typedef struct __SPI_HandleTypeDef __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ - __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */ + __IO uint32_t ErrorCode; /* SPI Error code */ }SPI_HandleTypeDef; /** @@ -180,6 +165,21 @@ typedef struct __SPI_HandleTypeDef * @{ */ +/** @defgroup SPI_Error_Codes SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE ((uint32_t)0x08) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x20) /*!< Flag: RXNE,TXE, BSY */ + +/** + * @} + */ + /** @defgroup SPI_mode SPI mode * @{ */ @@ -301,11 +301,11 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_CRC_Calculation SPI CRC Calculation * @{ */ -#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) -#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) /** @@ -407,23 +407,38 @@ typedef struct __SPI_HandleTypeDef * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE);}while(0) +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg); \ + }while(0) /** @brief Clear the SPI OVR pending flag. * @param __HANDLE__: specifies the SPI handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ - (__HANDLE__)->Instance->SR;}while(0) +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + }while(0) /** @brief Clear the SPI FRE pending flag. * @param __HANDLE__: specifies the SPI handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR) +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + }while(0) /** @brief Enables the SPI. * @param __HANDLE__: specifies the SPI Handle. @@ -528,7 +543,7 @@ void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.c index e45ed2ac6fe..b7ad51d1d77 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Extended SPI HAL module driver. * * This file provides firmware functions to manage the following @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -78,7 +78,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ - if(hspi == HAL_NULL) + if(hspi == NULL) { return HAL_ERROR; } @@ -99,6 +99,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) if(hspi->State == HAL_SPI_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); } @@ -122,7 +125,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Configure : CRC Polynomial */ hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.h index f392ef25da2..918159f60b3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_spi_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -61,23 +61,23 @@ /** @defgroup SPI_Exported_Constants SPI Exported Constants * @{ */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) /** @defgroup SPI_TI_mode SPI TI mode * @{ */ -#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) -#define SPI_TIMODE_ENABLED SPI_CR2_FRF +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ - ((MODE) == SPI_TIMODE_ENABLED)) +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ + ((MODE) == SPI_TIMODE_ENABLE)) #else /** @defgroup SPI_TI_mode SPI TI mode disable * @brief SPI TI Mode not supported for Category 1 and 2 * @{ */ -#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) -#define IS_SPI_TIMODE(MODE) ((MODE) == SPI_TIMODE_DISABLED) +#define IS_SPI_TIMODE(MODE) ((MODE) == SPI_TIMODE_DISABLE) #endif /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.c index b6fa9cdc010..37e7cdd7ab5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_sram.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -64,7 +64,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -98,28 +98,27 @@ * @{ */ -/** @defgroup SRAM SRAM - * @brief SRAM driver modules - * @{ - */ #ifdef HAL_SRAM_MODULE_ENABLED #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +/** @defgroup SRAM SRAM + * @brief SRAM driver modules + * @{ + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup SRAM_Exported_Functions SRAM Exported Functions * @{ */ /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions. * @verbatim ============================================================================== @@ -143,13 +142,16 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) { /* Check the SRAM handle parameter */ - if(hsram == HAL_NULL) + if(hsram == NULL) { return HAL_ERROR; } if(hsram->State == HAL_SRAM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hsram->Lock = HAL_UNLOCKED; + /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); } @@ -199,6 +201,9 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) */ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspInit could be implemented in the user file */ @@ -212,6 +217,9 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) */ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspDeInit could be implemented in the user file */ @@ -225,6 +233,9 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) */ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file */ @@ -238,6 +249,9 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) */ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file */ @@ -247,7 +261,7 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions +/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions * @brief Input Output and memory control functions * @verbatim @@ -512,7 +526,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - /* Enable the DMA Stream */ + /* Enable the DMA Channel */ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); /* Update the SRAM controller state */ @@ -551,7 +565,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - /* Enable the DMA Stream */ + /* Enable the DMA Channel */ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); /* Update the SRAM controller state */ @@ -568,7 +582,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre */ /** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief management functions + * @brief Control functions * @verbatim ============================================================================== @@ -635,7 +649,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) * @} */ -/** @defgroup SRAM_Exported_Functions_Group4 State functions +/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions * @brief Peripheral State functions * @verbatim @@ -668,11 +682,12 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) /** * @} */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#endif /* HAL_SRAM_MODULE_ENABLED */ + /** * @} */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +#endif /* HAL_SRAM_MODULE_ENABLED */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.h index 88d2d59dcac..e3bb718fe7d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_sram.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,18 +50,17 @@ * @{ */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + /** @addtogroup SRAM * @{ */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - /* Exported typedef ----------------------------------------------------------*/ -/** @defgroup SRAM_Exported_typedef SRAM Exported typedef +/** @defgroup SRAM_Exported_Types SRAM Exported Types * @{ */ - /** * @brief HAL SRAM State structures definition */ @@ -80,9 +79,9 @@ typedef enum */ typedef struct { - FSMC_NORSRAM_TYPEDEF *Instance; /*!< Register base address */ + FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended; /*!< Extended mode register base address */ + FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ @@ -101,7 +100,7 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup SRAM_Exported_macro SRAM Exported macro +/** @defgroup SRAM_Exported_Macros SRAM Exported Macros * @{ */ @@ -183,12 +182,12 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); * @} */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - /** * @} */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c index 59fc67aa57b..2da817d51c4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32l1xx_hal_tim.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief TIM HAL module driver. + * @version V1.1.3 + * @date 04-March-2016 + * @brief TIM HAL module driver * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + Time Base Initialization @@ -13,8 +13,8 @@ * + Time Base Start DMA * + Time Output Compare/PWM Initialization * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption + * + Time Output Compare/PWM Start + * + Time Output Compare/PWM Start Interruption * + Time Output Compare/PWM Start DMA * + Time Input Capture Initialization * + Time Input Capture Channel Configuration @@ -62,10 +62,10 @@ (++) Encoder mode output : HAL_TIM_Encoder_MspInit() (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); + __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the @@ -82,8 +82,8 @@ PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: @@ -102,7 +102,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -151,38 +151,29 @@ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); - +static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); - -static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); +static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAError(DMA_HandleTypeDef *hdma); -static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); /** * @} */ -/* External functions ---------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions * @{ @@ -218,7 +209,7 @@ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == HAL_NULL) + if(htim == NULL) { return HAL_ERROR; } @@ -230,6 +221,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); } @@ -280,6 +274,9 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ @@ -292,6 +289,9 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Base_MspDeInit could be implemented in the user file */ @@ -491,7 +491,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) { /* Check the TIM handle allocation */ - if(htim == HAL_NULL) + if(htim == NULL) { return HAL_ERROR; } @@ -503,6 +503,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); } @@ -553,6 +556,9 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ @@ -565,6 +571,9 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OC_MspDeInit could be implemented in the user file */ @@ -936,7 +945,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. + (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. (+) Start the Time PWM. (+) Stop the Time PWM. @@ -957,7 +966,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == HAL_NULL) + if(htim == NULL) { return HAL_ERROR; } @@ -969,6 +978,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); } @@ -1019,6 +1031,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ @@ -1031,6 +1046,9 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_PWM_MspDeInit could be implemented in the user file */ @@ -1427,7 +1445,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == HAL_NULL) + if(htim == NULL) { return HAL_ERROR; } @@ -1439,6 +1457,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); } @@ -1483,12 +1504,15 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) } /** - * @brief Initializes the TIM INput Capture MSP. + * @brief Initializes the TIM Input Capture MSP. * @param htim: TIM handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ @@ -1501,6 +1525,9 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_IC_MspDeInit could be implemented in the user file */ @@ -1678,7 +1705,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /** - * @brief Starts the TIM Input Capture measurement on in DMA mode. + * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim : TIM Input Capture handle * @param Channel : TIM Channels to be enabled * This parameter can be one of the following values: @@ -1797,7 +1824,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /** - * @brief Stops the TIM Input Capture measurement on in DMA mode. + * @brief Stops the TIM Input Capture measurement in DMA mode. * @param htim : TIM Input Capture handle * @param Channel : TIM Channels to be disabled * This parameter can be one of the following values: @@ -1897,7 +1924,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ - if(htim == HAL_NULL) + if(htim == NULL) { return HAL_ERROR; } @@ -1910,6 +1937,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); } @@ -1966,6 +1996,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ @@ -1978,6 +2011,9 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file */ @@ -2140,7 +2176,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini uint32_t tmpccer = 0; /* Check the TIM handle allocation */ - if(htim == HAL_NULL) + if(htim == NULL) { return HAL_ERROR; } @@ -2159,6 +2195,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); } @@ -2190,7 +2229,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= (~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F)); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); @@ -2249,6 +2288,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspInit could be implemented in the user file */ @@ -2261,6 +2303,9 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspDeInit could be implemented in the user file */ @@ -2273,6 +2318,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2314,6 +2360,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2357,6 +2404,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2404,6 +2452,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2454,6 +2503,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @param pData1: The destination Buffer address for IC1. * @param pData2: The destination Buffer address for IC2. * @param Length: The length of data to be transferred from TIM peripheral to memory. @@ -2577,6 +2627,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2646,7 +2697,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Capture compare 1 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); @@ -2670,7 +2721,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Capture compare 2 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; @@ -2691,7 +2742,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Capture compare 3 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; @@ -2712,7 +2763,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Capture compare 4 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; @@ -2733,7 +2784,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* TIM Update event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); HAL_TIM_PeriodElapsedCallback(htim); @@ -2742,7 +2793,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* TIM Trigger detection event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); HAL_TIM_TriggerCallback(htim); @@ -2792,7 +2843,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2954,12 +3004,13 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) { + __HAL_LOCK(htim); + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - __HAL_LOCK(htim); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); htim->State = HAL_TIM_STATE_BUSY; @@ -3150,27 +3201,27 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write - * This parameters can be on of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_DCR + * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_DCR * @param BurstRequestSrc: TIM DMA Request sources - * This parameters can be on of the following values: + * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source @@ -3179,7 +3230,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer: The Buffer address. * @param BurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3358,29 +3409,27 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read - * This parameters can be on of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR + * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_DCR * @param BurstRequestSrc: TIM DMA Request sources - * This parameters can be on of the following values: + * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source @@ -3389,7 +3438,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer: The Buffer address. * @param BurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3571,16 +3620,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @param htim: TIM handle * @param EventSource: specifies the event source. * This parameter can be one of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note TBC can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC. + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @note TIM6 and TIM7 can only generate an update event. * @retval HAL status */ @@ -3756,17 +3802,14 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo { uint32_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); @@ -3788,6 +3831,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3809,6 +3857,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -3824,6 +3877,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -3835,6 +3892,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -3846,6 +3907,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); @@ -3932,149 +3997,72 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: TIM handle. + * @param htim : TIM handle. * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - + __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } - + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} - __HAL_UNLOCK(htim); +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim: TIM handle. + * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + return HAL_OK; } @@ -4178,6 +4166,9 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ @@ -4190,6 +4181,9 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ @@ -4201,6 +4195,9 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_IC_CaptureCallback could be implemented in the user file */ @@ -4213,6 +4210,9 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ @@ -4225,6 +4225,9 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ @@ -4237,6 +4240,9 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ @@ -4321,26 +4327,12 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) return htim->State; } -/** - * @} - */ - -/** - * @} - */ - - -/** @addtogroup TIM_Private_Functions - * @{ - */ - - /** * @brief TIM DMA error callback * @param hdma : pointer to DMA handle. * @retval None */ -static void TIM_DMAError(DMA_HandleTypeDef *hdma) +void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; @@ -4354,7 +4346,7 @@ static void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma : pointer to DMA handle. * @retval None */ -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; @@ -4387,7 +4379,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) * @param hdma : pointer to DMA handle. * @retval None */ -static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; @@ -4415,6 +4407,19 @@ static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } +/** + * @} + */ + +/** + * @} + */ + + +/** @addtogroup TIM_Private_Functions + * @{ + */ + /** * @brief TIM DMA Period Elapse complete callback. * @param hdma : pointer to DMA handle. @@ -4477,8 +4482,7 @@ static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structur /* Set the Prescaler value */ TIMx->PSC = (uint32_t)Structure->Prescaler; - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ + /* Generate an update event to reload the Prescaler */ TIMx->EGR = TIM_EGR_UG; } @@ -4672,6 +4676,138 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) TIMx->CCER = tmpccer; } + +/** + * @brief Time Slave configuration + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param sSlaveConfig: The slave configuration structure + * @retval None + */ +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + + } + break; + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_ITR0: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR1: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR2: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + default: + break; + } +} + /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. @@ -4688,6 +4824,9 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. */ static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) @@ -4713,11 +4852,11 @@ static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); + tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; @@ -4775,6 +4914,9 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) @@ -4793,11 +4935,11 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); + tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); + tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -4855,6 +4997,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) @@ -4873,11 +5018,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= (TIM_ICFilter << 4); + tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (TIM_ICPolarity << 8); + tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -4900,6 +5045,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) @@ -4918,11 +5066,11 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= (TIM_ICFilter << 12); + tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (TIM_ICPolarity << 12); + tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5012,7 +5160,7 @@ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Chan assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); - tmp = (uint16_t)(TIM_CCER_CC1E << Channel); + tmp = TIM_CCER_CC1E << Channel; /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; @@ -5026,9 +5174,6 @@ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Chan */ #endif /* HAL_TIM_MODULE_ENABLED */ - - - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h index fcc152149b7..d249136d542 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_tim.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -97,8 +97,7 @@ typedef struct @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */ } TIM_OC_InitTypeDef; /** @@ -116,8 +115,7 @@ typedef struct This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -183,7 +181,7 @@ typedef struct /** - * @brief Clock Configuration Handle Structure definition + * @brief TIM Clock Configuration Handle Structure definition */ typedef struct { @@ -198,7 +196,7 @@ typedef struct }TIM_ClockConfigTypeDef; /** - * @brief Clear Input Configuration Handle Structure definition + * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { @@ -264,7 +262,7 @@ typedef struct TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ + This array is accessed by a @ref TIM_DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ }TIM_HandleTypeDef; @@ -278,7 +276,7 @@ typedef struct * @{ */ -/** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ @@ -288,7 +286,7 @@ typedef struct * @} */ -/** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ @@ -297,7 +295,7 @@ typedef struct * @} */ -/** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ @@ -308,7 +306,7 @@ typedef struct * @} */ -/** @defgroup TIM_Counter_Mode TIM_Counter_Mode +/** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) @@ -316,31 +314,21 @@ typedef struct #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS - -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ - ((MODE) == TIM_COUNTERMODE_DOWN) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) /** * @} */ -/** @defgroup TIM_ClockDivision TIM_ClockDivision +/** @defgroup TIM_ClockDivision TIM ClockDivision * @{ */ #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) - -#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV4)) /** * @} */ -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes * @{ */ #define TIM_OCMODE_TIMING ((uint32_t)0x0000) @@ -351,68 +339,38 @@ typedef struct #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) - -#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ - ((MODE) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ - ((MODE) == TIM_OCMODE_ACTIVE) || \ - ((MODE) == TIM_OCMODE_INACTIVE) || \ - ((MODE) == TIM_OCMODE_TOGGLE) || \ - ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) - -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTSTATE_ENABLE)) /** * @} */ -/** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State +/** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) - -#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ - ((STATE) == TIM_OCFAST_ENABLE)) /** * @} */ -/** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) - -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCPOLARITY_LOW)) /** * @} */ -/** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ - ((STATE) == TIM_OCIDLESTATE_RESET)) /** * @} */ -/** @defgroup TIM_Channel TIM_Channel +/** @defgroup TIM_Channel TIM Channel * @{ */ #define TIM_CHANNEL_1 ((uint32_t)0x0000) @@ -420,37 +378,21 @@ typedef struct #define TIM_CHANNEL_3 ((uint32_t)0x0008) #define TIM_CHANNEL_4 ((uint32_t)0x000C) #define TIM_CHANNEL_ALL ((uint32_t)0x0018) - -#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_ALL)) - -#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) /** * @} */ -/** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE - -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) /** * @} */ -/** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be @@ -458,57 +400,41 @@ typedef struct #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ - -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_TRC)) /** * @} */ -/** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ - -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) /** * @} */ -/** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) - -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ - ((MODE) == TIM_OPMODE_REPETITIVE)) /** * @} */ -/** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) - -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ - ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) /** * @} */ -/** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition +/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition * @{ */ #define TIM_IT_UPDATE (TIM_DIER_UIE) @@ -517,12 +443,11 @@ typedef struct #define TIM_IT_CC3 (TIM_DIER_CC3IE) #define TIM_IT_CC4 (TIM_DIER_CC4IE) #define TIM_IT_TRIGGER (TIM_DIER_TIE) - /** * @} */ -/** @defgroup TIM_DMA_sources TIM_DMA_sources +/** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ #define TIM_DMA_UPDATE (TIM_DIER_UDE) @@ -531,28 +456,24 @@ typedef struct #define TIM_DMA_CC3 (TIM_DIER_CC3DE) #define TIM_DMA_CC4 (TIM_DIER_CC4DE) #define TIM_DMA_TRIGGER (TIM_DIER_TDE) - -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) /** * @} */ -/** @defgroup TIM_Event_Source TIM_Event_Source +/** @defgroup TIM_Event_Source TIM Event Source * @{ */ -#define TIM_EventSource_Update TIM_EGR_UG -#define TIM_EventSource_CC1 TIM_EGR_CC1G -#define TIM_EventSource_CC2 TIM_EGR_CC2G -#define TIM_EventSource_CC3 TIM_EGR_CC3G -#define TIM_EventSource_CC4 TIM_EGR_CC4G -#define TIM_EventSource_Trigger TIM_EGR_TG - -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /** * @} */ -/** @defgroup TIM_Flag_definition TIM_Flag_definition +/** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ #define TIM_FLAG_UPDATE (TIM_SR_UIF) @@ -565,12 +486,11 @@ typedef struct #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) - /** * @} */ -/** @defgroup TIM_Clock_Source TIM_Clock_Source +/** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) @@ -583,22 +503,11 @@ typedef struct #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) - -#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) /** * @} */ -/** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ @@ -606,144 +515,90 @@ typedef struct #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ - -#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) /** * @} */ -/** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ - -#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Filter TIM_Clock_Filter - * @{ - */ -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ -/** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source +/** @defgroup TIM_ClearInput_Source TIM ClearInput Source * @{ */ #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) - -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) /** * @} */ -/** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity +/** @defgroup TIM_ClearInput_Polarity TIM ClearInput Polarity * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ - - -#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) /** * @} */ -/** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler +/** @defgroup TIM_ClearInput_Prescaler TIM ClearInput Prescaler * @{ */ #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ - -#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter - * @{ - */ -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state * @{ */ #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) #define TIM_OSSR_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ - ((STATE) == TIM_OSSR_DISABLE)) /** * @} */ -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state * @{ */ #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) #define TIM_OSSI_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ - ((STATE) == TIM_OSSI_DISABLE)) /** * @} */ -/** @defgroup TIM_Lock_level TIM_Lock_level +/** @defgroup TIM_Lock_level TIM Lock level * @{ */ #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) - -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ - ((LEVEL) == TIM_LOCKLEVEL_1) || \ - ((LEVEL) == TIM_LOCKLEVEL_2) || \ - ((LEVEL) == TIM_LOCKLEVEL_3)) /** * @} */ -/** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) /** * @} */ -/** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ #define TIM_TRGO_RESET ((uint32_t)0x0000) @@ -754,20 +609,11 @@ typedef struct #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) /** * @} */ -/** @defgroup TIM_Slave_Mode TIM_Slave_Mode +/** @defgroup TIM_Slave_Mode TIM Slave Mode * @{ */ #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) @@ -775,29 +621,20 @@ typedef struct #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) - -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ - ((MODE) == TIM_SLAVEMODE_GATED) || \ - ((MODE) == TIM_SLAVEMODE_RESET) || \ - ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ - ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) /** * @} */ -/** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode +/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) /** * @} */ -/** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ #define TIM_TS_ITR0 ((uint32_t)0x0000) @@ -809,31 +646,11 @@ typedef struct #define TIM_TS_TI2FP2 ((uint32_t)0x0060) #define TIM_TS_ETRF ((uint32_t)0x0070) #define TIM_TS_NONE ((uint32_t)0xFFFF) - -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_NONE)) /** * @} */ -/** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ @@ -841,149 +658,81 @@ typedef struct #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ - -#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) /** * @} */ -/** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ - -#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter - * @{ - */ -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ -/** @defgroup TIM_TI1_Selection TIM_TI1_Selection +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) - -#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ - ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address - * @{ - */ -#define TIM_DMABase_CR1 (0x00000000) -#define TIM_DMABase_CR2 (0x00000001) -#define TIM_DMABase_SMCR (0x00000002) -#define TIM_DMABase_DIER (0x00000003) -#define TIM_DMABase_SR (0x00000004) -#define TIM_DMABase_EGR (0x00000005) -#define TIM_DMABase_CCMR1 (0x00000006) -#define TIM_DMABase_CCMR2 (0x00000007) -#define TIM_DMABase_CCER (0x00000008) -#define TIM_DMABase_CNT (0x00000009) -#define TIM_DMABase_PSC (0x0000000A) -#define TIM_DMABase_ARR (0x0000000B) -#define TIM_DMABase_CCR1 (0x0000000D) -#define TIM_DMABase_CCR2 (0x0000000E) -#define TIM_DMABase_CCR3 (0x0000000F) -#define TIM_DMABase_CCR4 (0x00000010) -#define TIM_DMABase_DCR (0x00000012) -#define TIM_DMABase_OR (0x00000013) - -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) /** * @} */ -/** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ -#define TIM_DMABurstLength_1Transfer (0x00000000) -#define TIM_DMABurstLength_2Transfers (0x00000100) -#define TIM_DMABurstLength_3Transfers (0x00000200) -#define TIM_DMABurstLength_4Transfers (0x00000300) -#define TIM_DMABurstLength_5Transfers (0x00000400) -#define TIM_DMABurstLength_6Transfers (0x00000500) -#define TIM_DMABurstLength_7Transfers (0x00000600) -#define TIM_DMABurstLength_8Transfers (0x00000700) -#define TIM_DMABurstLength_9Transfers (0x00000800) -#define TIM_DMABurstLength_10Transfers (0x00000900) -#define TIM_DMABurstLength_11Transfers (0x00000A00) -#define TIM_DMABurstLength_12Transfers (0x00000B00) -#define TIM_DMABurstLength_13Transfers (0x00000C00) -#define TIM_DMABurstLength_14Transfers (0x00000D00) -#define TIM_DMABurstLength_15Transfers (0x00000E00) -#define TIM_DMABurstLength_16Transfers (0x00000F00) -#define TIM_DMABurstLength_17Transfers (0x00001000) -#define TIM_DMABurstLength_18Transfers (0x00001100) - -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) +#define TIM_DMABASE_CR1 (0x00000000) +#define TIM_DMABASE_CR2 (0x00000001) +#define TIM_DMABASE_SMCR (0x00000002) +#define TIM_DMABASE_DIER (0x00000003) +#define TIM_DMABASE_SR (0x00000004) +#define TIM_DMABASE_EGR (0x00000005) +#define TIM_DMABASE_CCMR1 (0x00000006) +#define TIM_DMABASE_CCMR2 (0x00000007) +#define TIM_DMABASE_CCER (0x00000008) +#define TIM_DMABASE_CNT (0x00000009) +#define TIM_DMABASE_PSC (0x0000000A) +#define TIM_DMABASE_ARR (0x0000000B) +#define TIM_DMABASE_CCR1 (0x0000000D) +#define TIM_DMABASE_CCR2 (0x0000000E) +#define TIM_DMABASE_CCR3 (0x0000000F) +#define TIM_DMABASE_CCR4 (0x00000010) +#define TIM_DMABASE_DCR (0x00000012) +#define TIM_DMABASE_OR (0x00000013) /** * @} */ -/** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) /** * @} */ -/** @defgroup DMA_Handle_index DMA_Handle_index +/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index * @{ */ #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ @@ -996,7 +745,7 @@ typedef struct * @} */ -/** @defgroup Channel_CC_State Channel_CC_State +/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State * @{ */ #define TIM_CCx_ENABLE ((uint32_t)0x0001) @@ -1010,18 +759,277 @@ typedef struct */ /* Private Constants -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM_Private_Constants +/** @defgroup TIM_Private_Constants TIM Private Constants * @{ */ /* The counter of a timer instance is disabled only if all the CCx channels have been disabled */ -#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) /** * @} */ +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ + ((MODE) == TIM_COUNTERMODE_DOWN) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ + ((MODE) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ + ((MODE) == TIM_OCMODE_ACTIVE) || \ + ((MODE) == TIM_OCMODE_INACTIVE) || \ + ((MODE) == TIM_OCMODE_TOGGLE) || \ + ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ + ((STATE) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ + ((STATE) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ + ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ + ((MODE) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ + ((MODE) == TIM_ENCODERMODE_TI2) || \ + ((MODE) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) + +#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) + +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) + +#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ + ((STATE) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ + ((STATE) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM_LOCKLEVEL_1) || \ + ((LEVEL) == TIM_LOCKLEVEL_2) || \ + ((LEVEL) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ + ((SOURCE) == TIM_TRGO_ENABLE) || \ + ((SOURCE) == TIM_TRGO_UPDATE) || \ + ((SOURCE) == TIM_TRGO_OC1) || \ + ((SOURCE) == TIM_TRGO_OC1REF) || \ + ((SOURCE) == TIM_TRGO_OC2REF) || \ + ((SOURCE) == TIM_TRGO_OC3REF) || \ + ((SOURCE) == TIM_TRGO_OC4REF)) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ + ((MODE) == TIM_SLAVEMODE_GATED) || \ + ((MODE) == TIM_SLAVEMODE_RESET) || \ + ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) + +#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ + ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ + ((BASE) == TIM_DMABASE_CR2) || \ + ((BASE) == TIM_DMABASE_SMCR) || \ + ((BASE) == TIM_DMABASE_DIER) || \ + ((BASE) == TIM_DMABASE_SR) || \ + ((BASE) == TIM_DMABASE_EGR) || \ + ((BASE) == TIM_DMABASE_CCMR1) || \ + ((BASE) == TIM_DMABASE_CCMR2) || \ + ((BASE) == TIM_DMABASE_CCER) || \ + ((BASE) == TIM_DMABASE_CNT) || \ + ((BASE) == TIM_DMABASE_PSC) || \ + ((BASE) == TIM_DMABASE_ARR) || \ + ((BASE) == TIM_DMABASE_CCR1) || \ + ((BASE) == TIM_DMABASE_CCR2) || \ + ((BASE) == TIM_DMABASE_CCR3) || \ + ((BASE) == TIM_DMABASE_CCR4) || \ + ((BASE) == TIM_DMABASE_DCR) || \ + ((BASE) == TIM_DMABASE_OR)) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) + +/** @brief Set TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @param __ICPSC__: specifies the prescaler value. + * @retval None + */ +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + +/** @brief Reset TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @retval None + */ +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + + +/** @brief Set TIM IC polarity + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @param __POLARITY__: specifies TIM Channel Polarity + * @retval None + */ +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) + +/** @brief Reset TIM IC polarity + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @retval None + */ +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) + +/** + * @} + */ +/* Private Functions --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /** @defgroup TIM_Exported_Macros TIM Exported Macros @@ -1048,57 +1056,113 @@ typedef struct */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } while(0) /** - * @brief Enable the specified TIM interrupt. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. + * @brief Enables the specified TIM interrupt. + * @param __HANDLE__: specifies the TIM Handle. + * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt * @retval None */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) /** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__: TIM handle - * @param __DMA__: specifies the DMA Channel to be enabled or disabled. + * @brief Disables the specified TIM interrupt. + * @param __HANDLE__: specifies the TIM Handle. + * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt * @retval None */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** - * @brief Disable the specified TIM interrupt. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. + * @brief Enables the specified DMA request. + * @param __HANDLE__: specifies the TIM Handle. + * @param __DMA__: specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__: TIM handle - * @param __DMA__: specifies the DMA Channel to be enabled or disabled. + * @brief Disables the specified DMA request. + * @param __HANDLE__: specifies the TIM Handle. + * @param __DMA__: specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** - * @brief Get the TIM Channel pending flags. - * @param __HANDLE__: TIM handle - * @param __FLAG__: Get the specified flag. - * @retval The state of FLAG (SET or RESET). + * @brief Checks whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__: specifies the TIM Handle. + * @param __FLAG__: specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** - * @brief Clear the TIM Channel pending flags. - * @param __HANDLE__: TIM handle - * @param __FLAG__: specifies the flag to clear. - * @retval None + * @brief Clears the specified TIM interrupt flag. + * @param __HANDLE__: specifies the TIM Handle. + * @param __FLAG__: specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) @@ -1108,49 +1172,32 @@ typedef struct * @param __INTERRUPT__: specifies the TIM interrupt source to check. * @retval The state of TIM_IT (SET or RESET). */ -#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Clear the TIM interrupt pending bits +/** + * @brief Clear the TIM interrupt pending bits * @param __HANDLE__: TIM handle * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) -/** @brief TIM counter direction - * @param __HANDLE__: TIM handle - */ -#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** @brief Set TIM prescaler - * @param __HANDLE__: TIM handle - * @param __PRESC__: specifies the prescaler value. - * @retval None +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter + * @param __HANDLE__: TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. */ -#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) -/** @brief Set TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @param __ICPSC__: specifies the prescaler value. - * @retval None - */ -#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) - -/** @brief Reset TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel +/** + * @brief Sets the TIM active prescaler register value on update event. + * @param __HANDLE__: TIM handle. + * @param __PRESC__: specifies the active prescaler register new value. * @retval None */ -#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Sets the TIM Capture Compare Register value on runtime without @@ -1165,7 +1212,7 @@ typedef struct * @param __COMPARE__: specifies the Capture Compare register new value. * @retval None */ -#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) /** @@ -1179,7 +1226,7 @@ typedef struct * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @retval None */ -#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) /** @@ -1188,14 +1235,14 @@ typedef struct * @param __COUNTER__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Gets the TIM Counter Register value on runtime. * @param __HANDLE__: TIM handle. * @retval None */ -#define __HAL_TIM_GetCounter(__HANDLE__) \ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ ((__HANDLE__)->Instance->CNT) /** @@ -1205,7 +1252,7 @@ typedef struct * @param __AUTORELOAD__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ @@ -1216,7 +1263,7 @@ typedef struct * @param __HANDLE__: TIM handle. * @retval None */ -#define __HAL_TIM_GetAutoreload(__HANDLE__) \ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ ((__HANDLE__)->Instance->ARR) /** @@ -1230,7 +1277,7 @@ typedef struct * @arg TIM_CLOCKDIVISION_DIV4 * @retval None */ -#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do{ \ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ @@ -1242,7 +1289,7 @@ typedef struct * @param __HANDLE__: TIM handle. * @retval None */ -#define __HAL_TIM_GetClockDivision(__HANDLE__) \ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** @@ -1263,10 +1310,10 @@ typedef struct * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ -#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do{ \ - __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ - __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ } while(0) /** @@ -1280,12 +1327,59 @@ typedef struct * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval None */ -#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__: TIM handle. + * @note When the USR bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__: TIM handle. + * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * (+) Counter overflow/underflow + * (+) Setting the UG bit + * (+) Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) + +/** + * @brief Sets the TIM Capture x input polarity on runtime. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__: Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + /** * @} */ @@ -1315,7 +1409,6 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); - /** * @} */ @@ -1445,6 +1538,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); @@ -1483,6 +1577,10 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.c index 3b67e03116c..6e356586b72 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,7 +58,7 @@ */ /** @defgroup TIMEx TIMEx - * @brief TIM HAL module driver + * @brief TIM Extended HAL module driver * @{ */ @@ -71,6 +71,8 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions * @{ */ @@ -84,10 +86,8 @@ ============================================================================== [..] This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. + (+)Configure Master synchronization. + (+) Configure timer remapping capabilities. @endverbatim * @{ @@ -134,52 +134,52 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @param htim: TIM handle. * @param Remap: specifies the TIM remapping source. * This parameter is a combination of the following values depending on TIM instance. + * @retval HAL status * - * For TIM2, the parameter can have the following values: + * @note For TIM2, the parameter can have the following values: * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO * - * For TIM3, the parameter can have the following values: + * @note For TIM3, the parameter can have the following values: * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO * - * For TIM9, the parameter is a combination of 2 fields (field1 | field2): - * field1 can have the following values: + * @note For TIM9, the parameter is a combination of 2 fields (field1 | field2): + * @note For TIM9, the field1 can have the following values: * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O - * field2 can have the following values: + * @note For TIM9, the field2 can have the following values: * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO * - * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): - * field1 can have the following values: + * @note For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): + * @note For TIM10, the field1 can have the following values: * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI - * field2 can have the following values: + * @note For TIM10, the field2 can have the following values: * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO - * field3 can have the following values: + * @note For TIM10, the field3 can have the following values: * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt * - * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): - * field1 can have the following values: + * @note For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): + * @note For TIM11, the field1 can have the following values: * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI - * field2 can have the following values: + * @note For TIM11, the field2 can have the following values: * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO - * field3 can have the following values: + * @note For TIM11, the field3 can have the following values: * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO * - * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { @@ -199,47 +199,6 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) return HAL_OK; } -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extension Callbacks functions - * @brief Extension Callbacks functions - * -@verbatim - ============================================================================== - ##### Extension Callbacks functions ##### - ============================================================================== - [..] - This section provides Extension TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extension Peripheral State functions - * @brief Extension Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extension Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.h index bc227f306ca..11d997851a8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -73,60 +73,59 @@ typedef struct { * @} */ - /* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIMEx_Exported_Constants +/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants * @{ */ -/** @defgroup TIMEx_Remap TIMEx_Remap +/** @defgroup TIMEx_Remap TIMEx Remap * @{ */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /* !< TIM2 ITR1 input is connected to TIM10 OC */ -#define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /* !< TIM2 ITR1 input is connected to TIM5 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /* !< TIM3 ITR2 input is connected to TIM11 OC */ -#define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /* !< TIM3 ITR2 input is connected to TIM5 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /* !< TIM9 ITR1 input is connected to TIM3 TGO */ -#define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /* !< TIM9 ITR1 input is connected to touch sensing I/O */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ -#define TIM_TIM9_GPIO (0x00000000) /* !< TIM9 Channel1 is connected to GPIO */ -#define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /* !< TIM9 Channel1 is connected to LSE internal clock */ -#define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /* !< TIM9 Channel1 is connected to GPIO */ -#define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /* !< TIM9 Channel1 is connected to GPIO */ - - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM10_TI1RMP (0x00000000) /* !< TIM10 Channel 1 depends on TI1_RMP */ -#define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /* !< TIM10 Channel 1 is connected to RI */ -#define TIM_TIM10_ETR_LSE (0x00000000) /* !< TIM10 ETR input is connected to LSE clock */ -#define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /* !< TIM10 ETR input is connected to TIM9 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ -#define TIM_TIM10_GPIO (0x00000000) /* !< TIM10 Channel1 is connected to GPIO */ -#define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /* !< TIM10 Channel1 is connected to LSI internal clock */ -#define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /* !< TIM10 Channel1 is connected to LSE internal clock */ -#define TIM_TIM10_RTC TIM_OR_TI1RMP /* !< TIM10 Channel1 is connected to RTC wakeup interrupt */ - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM11_TI1RMP (0x00000000) /* !< TIM11 Channel 1 depends on TI1_RMP */ -#define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /* !< TIM11 Channel 1 is connected to RI */ -#define TIM_TIM11_ETR_LSE (0x00000000) /* !< TIM11 ETR input is connected to LSE clock */ -#define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /* !< TIM11 ETR input is connected to TIM9 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ -#define TIM_TIM11_GPIO (0x00000000) /* !< TIM11 Channel1 is connected to GPIO */ -#define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /* !< TIM11 Channel1 is connected to MSI internal clock */ -#define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /* !< TIM11 Channel1 is connected to HSE_RTC clock */ -#define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /* !< TIM11 Channel1 is connected to GPIO */ - - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /*!< TIM2 ITR1 input is connected to TIM10 OC */ +#define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM2 ITR1 input is connected to TIM5 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */ + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /*!< TIM3 ITR2 input is connected to TIM11 OC */ +#define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM3 ITR2 input is connected to TIM5 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */ + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /*!< TIM9 ITR1 input is connected to TIM3 TGO */ +#define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /*!< TIM9 ITR1 input is connected to touch sensing I/O */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */ +#define TIM_TIM9_GPIO (0x00000000) /*!< TIM9 Channel1 is connected to GPIO */ +#define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /*!< TIM9 Channel1 is connected to LSE internal clock */ +#define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /*!< TIM9 Channel1 is connected to GPIO */ +#define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /*!< TIM9 Channel1 is connected to GPIO */ + + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define TIM_TIM10_TI1RMP (0x00000000) /*!< TIM10 Channel 1 depends on TI1_RMP */ +#define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /*!< TIM10 Channel 1 is connected to RI */ +#define TIM_TIM10_ETR_LSE (0x00000000) /*!< TIM10 ETR input is connected to LSE clock */ +#define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM10 ETR input is connected to TIM9 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */ +#define TIM_TIM10_GPIO (0x00000000) /*!< TIM10 Channel1 is connected to GPIO */ +#define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /*!< TIM10 Channel1 is connected to LSI internal clock */ +#define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /*!< TIM10 Channel1 is connected to LSE internal clock */ +#define TIM_TIM10_RTC TIM_OR_TI1RMP /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */ + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define TIM_TIM11_TI1RMP (0x00000000) /*!< TIM11 Channel 1 depends on TI1_RMP */ +#define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /*!< TIM11 Channel 1 is connected to RI */ +#define TIM_TIM11_ETR_LSE (0x00000000) /*!< TIM11 ETR input is connected to LSE clock */ +#define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM11 ETR input is connected to TIM9 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */ +#define TIM_TIM11_GPIO (0x00000000) /*!< TIM11 Channel1 is connected to GPIO */ +#define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /*!< TIM11 Channel1 is connected to MSI internal clock */ +#define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /*!< TIM11 Channel1 is connected to HSE_RTC clock */ +#define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /*!< TIM11 Channel1 is connected to GPIO */ + + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ ( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \ (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \ @@ -134,7 +133,7 @@ typedef struct { (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \ (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \ ) -#else /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ +#else /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) */ #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ ( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \ (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \ @@ -168,23 +167,6 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group2 - * @{ - */ - -/** - * @} - */ - -/* Extension Callback *********************************************************/ - -/** @addtogroup TIMEx_Exported_Functions_Group3 - * @{ - */ - -/** - * @} - */ /* Extension Peripheral State functions **************************************/ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.c index 53ef551f2dc..b255cbe015b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_uart.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -24,7 +24,7 @@ (##) Enable the USARTx interface clock. (##) UART pins configuration: (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. + (+++) Configure the UART pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -39,58 +39,56 @@ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the huart Init structure. (#) For the UART asynchronous mode, initialize the UART registers by calling the HAL_UART_Init() API. - + (#) For the UART Half duplex mode, initialize the UART registers by calling the HAL_HalfDuplex_Init() API. - + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. - + (#) For the Multi-Processor mode, initialize the UART registers by calling the HAL_MultiProcessor_Init() API. - + [..] (@) The specific UART interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive process. - + [..] (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed HAL_UART_MspInit() API. - + [..] - Three operation modes are available within this driver : - + Three operation modes are available within this driver : + *** Polling mode IO operation *** ================================= [..] (+) Send an amount of data in blocking mode using HAL_UART_Transmit() (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - *** Interrupt mode IO operation *** + *** Interrupt mode IO operation *** =================================== - [..] + [..] (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_TxCpltCallback (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback + add his own code by customization of function pointer HAL_UART_RxCpltCallback (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_UART_ErrorCallback - *** DMA mode IO operation *** + *** DMA mode IO operation *** ============================== [..] (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() @@ -102,33 +100,34 @@ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback + add his own code by customization of function pointer HAL_UART_RxCpltCallback (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_UART_ErrorCallback - (+) Pause the DMA Transfer using HAL_UART_DMAPause() - (+) Resume the DMA Transfer using HAL_UART_DMAResume() - (+) Stop the DMA Transfer using HAL_UART_DMAStop() - + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + *** UART HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in UART HAL driver. - + (+) __HAL_UART_ENABLE: Enable the UART peripheral - (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt - - [..] + (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not + + [..] (@) You can refer to the UART HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -153,7 +152,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal.h" @@ -162,7 +161,7 @@ * @{ */ -/** @defgroup UART UART HAL module driver +/** @defgroup UART UART * @brief HAL UART module driver * @{ */ @@ -170,15 +169,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#define UART_TIMEOUT_VALUE 22000 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions UART Private Functions @@ -218,21 +209,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, (++) Baud Rate (++) Word Length (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | UART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ + (++) Parity (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Methode @@ -245,6 +222,24 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, * @{ */ +/* + Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ +*/ + /** * @brief Initializes the UART mode according to the specified parameters in * the UART_InitTypeDef and create the associated handle. @@ -255,24 +250,30 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } - + + /* Check the parameters */ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { - /* Check the parameters */ + /* The hardware flow control is available only for USART1, USART2, USART3 */ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); } else { - /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if(huart->State == HAL_UART_STATE_RESET) { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_UART_MspInit(huart); } @@ -288,8 +289,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); /* Enable the peripheral */ __HAL_UART_ENABLE(huart); @@ -311,16 +312,21 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } /* Check UART instance */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + if(huart->State == HAL_UART_STATE_RESET) { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_UART_MspInit(huart); } @@ -336,11 +342,11 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - huart->Instance->CR3 |= USART_CR3_HDSEL; + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); /* Enable the peripheral */ __HAL_UART_ENABLE(huart); @@ -366,7 +372,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -375,15 +381,14 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - - /* LIN mode limited to 16-bit oversampling only */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - return HAL_ERROR; - } - + assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); + if(huart->State == HAL_UART_STATE_RESET) { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_UART_MspInit(huart); } @@ -399,11 +404,11 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* In LIN mode, the following bits must be kept cleared: - CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - huart->Instance->CR2 |= USART_CR2_LINEN; + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); @@ -423,7 +428,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe * parameters in the UART_InitTypeDef and create the associated handle. * @param huart: Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param Address: UART node address + * @param Address: UART node address * @param WakeUpMethod: specifies the UART wakeup method. * This parameter can be one of the following values: * @arg UART_WAKEUPMETHOD_IDLELINE: Wakeup by an idle line detection @@ -433,7 +438,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -444,9 +449,14 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Check the Address & wake up method parameters */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); assert_param(IS_UART_ADDRESS(Address)); - + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + if(huart->State == HAL_UART_STATE_RESET) { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_UART_MspInit(huart); } @@ -462,8 +472,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* In Multi-Processor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); /* Set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, Address); @@ -490,7 +500,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -503,6 +513,10 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); + huart->Instance->CR1 = 0x0; + huart->Instance->CR2 = 0x0; + huart->Instance->CR3 = 0x0; + /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); @@ -523,8 +537,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_MspInit could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file */ } @@ -536,8 +553,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_MspDeInit could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file */ } @@ -566,7 +586,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or receive process. + will be executed respectively at the end of the transmit or receive process. The HAL_UART_ErrorCallback() user callback will be executed when a communication error is detected. @@ -614,19 +634,19 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX)) + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a non-blocking receive process is ongoing or not */ if(huart->State == HAL_UART_STATE_BUSY_RX) @@ -669,12 +689,12 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->Instance->DR = (*pData++ & (uint8_t)0xFF); } } - + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Check if a non-blocking receive process is ongoing or not */ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { @@ -684,10 +704,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u { huart->State = HAL_UART_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -708,22 +728,22 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - uint32_t tmp1 = 0; - - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) + uint32_t tmp_state = 0; + + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->State == HAL_UART_STATE_BUSY_TX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; } @@ -731,10 +751,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { huart->State = HAL_UART_STATE_BUSY_RX; } - + huart->RxXferSize = Size; huart->RxXferCount = Size; - + /* Check the remain data to be received */ while(huart->RxXferCount > 0) { @@ -742,7 +762,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui if(huart->Init.WordLength == UART_WORDLENGTH_9B) { if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } tmp = (uint16_t*) pData ; @@ -757,11 +777,11 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pData +=1; } - } + } else { if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } if(huart->Init.Parity == UART_PARITY_NONE) @@ -772,10 +792,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); } - + } } - + /* Check if a non-blocking transmit process is ongoing or not */ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { @@ -787,12 +807,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -806,12 +826,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - uint32_t tmp = 0; - - tmp = huart->State; - if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX)) + uint32_t tmp_state = 0; + + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -834,12 +854,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->State = HAL_UART_STATE_BUSY_TX; } - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -864,12 +878,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - uint32_t tmp = 0; + uint32_t tmp_state = 0; - tmp = huart->State; - if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX)) + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -892,15 +906,15 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->State = HAL_UART_STATE_BUSY_RX; } + /* Process Unlocked */ + __HAL_UNLOCK(huart); + /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); @@ -923,12 +937,12 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX)) + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -964,9 +978,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -992,12 +1009,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -1034,7 +1051,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1061,18 +1078,17 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) if(huart->State == HAL_UART_STATE_BUSY_TX) { /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } else if(huart->State == HAL_UART_STATE_BUSY_RX) { /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } else if (huart->State == HAL_UART_STATE_BUSY_TX_RX) { /* Disable the UART DMA Tx & Rx requests */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); } else { @@ -1084,7 +1100,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1098,38 +1114,37 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if(huart->State == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } else if(huart->State == HAL_UART_STATE_BUSY_RX) { /* Clear the Overrun flag before resumming the Rx transfer*/ __HAL_UART_CLEAR_OREFLAG(huart); /* Enable the UART DMA Rx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { /* Clear the Overrun flag before resumming the Rx transfer*/ __HAL_UART_CLEAR_OREFLAG(huart); /* Enable the UART DMA Tx & Rx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; - huart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); } else { /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_ERROR; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1148,16 +1163,15 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) */ /* Disable the UART Tx/Rx DMA requests */ - huart->Instance->CR3 &= ~USART_CR3_DMAT; - huart->Instance->CR3 &= ~USART_CR3_DMAR; + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); /* Abort the UART DMA tx channel */ - if(huart->hdmatx != HAL_NULL) + if(huart->hdmatx != NULL) { HAL_DMA_Abort(huart->hdmatx); } /* Abort the UART DMA rx channel */ - if(huart->hdmarx != HAL_NULL) + if(huart->hdmarx != NULL) { HAL_DMA_Abort(huart->hdmarx); } @@ -1175,74 +1189,67 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { - uint32_t tmp1 = 0, tmp2 = 0; + uint32_t tmp_flag = 0, tmp_it_source = 0; - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE); + tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE); + tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE); /* UART parity error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_UART_CLEAR_PEFLAG(huart); - huart->ErrorCode |= HAL_UART_ERROR_PE; } - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); + tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE); + tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); /* UART frame error interrupt occurred -------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_UART_CLEAR_FEFLAG(huart); - + if((tmp_flag != RESET) && (tmp_it_source != RESET)) + { huart->ErrorCode |= HAL_UART_ERROR_FE; } - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); + tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE); /* UART noise error interrupt occurred -------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_UART_CLEAR_NEFLAG(huart); - + if((tmp_flag != RESET) && (tmp_it_source != RESET)) + { huart->ErrorCode |= HAL_UART_ERROR_NE; } - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); + tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE); /* UART Over-Run interrupt occurred ----------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_UART_CLEAR_OREFLAG(huart); - + if((tmp_flag != RESET) && (tmp_it_source != RESET)) + { huart->ErrorCode |= HAL_UART_ERROR_ORE; } - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE); + tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE); + tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE); /* UART in mode Receiver ---------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { UART_Receive_IT(huart); } - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE); + tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE); + tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE); /* UART in mode Transmitter ------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { UART_Transmit_IT(huart); } - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC); + tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC); + tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC); /* UART in mode Transmitter end --------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { UART_EndTransmit_IT(huart); } if(huart->ErrorCode != HAL_UART_ERROR_NONE) { + /* Clear all the error flag at once */ + __HAL_UART_CLEAR_PEFLAG(huart); + /* Set the UART state ready to be able to start again the process */ huart->State = HAL_UART_STATE_READY; @@ -1258,8 +1265,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file */ } @@ -1271,8 +1281,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file */ } @@ -1284,8 +1297,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file */ } @@ -1297,8 +1313,11 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file */ } @@ -1310,8 +1329,11 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file */ } @@ -1347,7 +1369,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) { /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); @@ -1355,7 +1377,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) huart->State = HAL_UART_STATE_BUSY; /* Send break characters */ - huart->Instance->CR1 |= USART_CR1_SBK; + SET_BIT(huart->Instance->CR1, USART_CR1_SBK); huart->State = HAL_UART_STATE_READY; @@ -1382,7 +1404,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) huart->State = HAL_UART_STATE_BUSY; /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - huart->Instance->CR1 |= USART_CR1_RWU; + SET_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->State = HAL_UART_STATE_READY; @@ -1409,7 +1431,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) huart->State = HAL_UART_STATE_BUSY; /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->State = HAL_UART_STATE_READY; @@ -1427,24 +1449,15 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00; - /* Process Locked */ __HAL_LOCK(huart); huart->State = HAL_UART_STATE_BUSY; /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_TE; - - /* Write to USART CR1 */ - huart->Instance->CR1 = (uint32_t)tmpreg; + MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_TE); huart->State = HAL_UART_STATE_READY; @@ -1462,24 +1475,15 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00; - /* Process Locked */ __HAL_LOCK(huart); huart->State = HAL_UART_STATE_BUSY; /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_RE; - - /* Write to USART CR1 */ - huart->Instance->CR1 = (uint32_t)tmpreg; + MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_RE); huart->State = HAL_UART_STATE_READY; @@ -1555,35 +1559,16 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { huart->TxXferCount = 0; /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - /* Wait for UART TC Flag */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - huart->State = HAL_UART_STATE_TIMEOUT; - HAL_UART_ErrorCallback(huart); - } - else - { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - HAL_UART_TxCpltCallback(huart); - } + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); } /* DMA Circular mode */ else @@ -1615,13 +1600,13 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { huart->RxXferCount = 0; /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Check if a transmit process is ongoing or not */ if(huart->State == HAL_UART_STATE_BUSY_TX_RX) @@ -1744,10 +1729,10 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_BUSY_TX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX)) { if(huart->Init.WordLength == UART_WORDLENGTH_9B) { @@ -1802,12 +1787,6 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State = HAL_UART_STATE_READY; } @@ -1825,10 +1804,10 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - uint32_t tmp1 = 0; + uint32_t tmp_state = 0; - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) + tmp_state = huart->State; + if((tmp_state == HAL_UART_STATE_BUSY_RX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX)) { if(huart->Init.WordLength == UART_WORDLENGTH_9B) { @@ -1898,26 +1877,17 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) uint32_t tmpreg = 0x00; /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - /*-------------------------- USART CR2 Configuration -----------------------*/ + /*------- UART-associated USART registers setting : CR2 Configuration ------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - /*-------------------------- USART CR1 Configuration -----------------------*/ + /*------- UART-associated USART registers setting : CR1 Configuration ------*/ /* Configure the UART Word Length, Parity and mode: Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value @@ -1928,14 +1898,14 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ + /*------- UART-associated USART registers setting : CR3 Configuration ------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); /* Check the Over Sampling */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) { - /*-------------------------- USART BRR Configuration ---------------------*/ + /*------- UART-associated USART registers setting : BRR Configuration ------*/ if((huart->Instance == USART1)) { huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); @@ -1947,7 +1917,7 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) } else { - /*-------------------------- USART BRR Configuration ---------------------*/ + /*------- UART-associated USART registers setting : BRR Configuration ------*/ if((huart->Instance == USART1)) { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.h index 601c8b528ae..e9852377958 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_hal_uart.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief This file contains all the functions prototypes for the UART * firmware library. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -111,49 +111,36 @@ typedef enum HAL_UART_STATE_ERROR = 0x04 /*!< Error */ }HAL_UART_StateTypeDef; -/** - * @brief HAL UART Error Code structure definition - */ -typedef enum -{ - HAL_UART_ERROR_NONE = 0x00, /*!< No error */ - HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_UART_ErrorTypeDef; - /** * @brief UART handle Structure definition */ typedef struct { - USART_TypeDef *Instance; /* UART registers base address */ + USART_TypeDef *Instance; /*!< UART registers base address */ - UART_InitTypeDef Init; /* UART communication parameters */ + UART_InitTypeDef Init; /*!< UART communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - uint16_t TxXferSize; /* UART Tx Transfer size */ + uint16_t TxXferSize; /*!< UART Tx Transfer size */ - uint16_t TxXferCount; /* UART Tx Transfer Counter */ + uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - uint16_t RxXferSize; /* UART Rx Transfer size */ + uint16_t RxXferSize; /*!< UART Rx Transfer size */ - uint16_t RxXferCount; /* UART Rx Transfer Counter */ + uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef State; /* UART communication state */ + __IO HAL_UART_StateTypeDef State; /*!< UART communication state */ - __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */ + __IO uint32_t ErrorCode; /*!< UART Error code */ }UART_HandleTypeDef; @@ -165,14 +152,27 @@ typedef struct /** @defgroup UART_Exported_Constants UART Exported constants * @{ */ - + +/** @defgroup UART_Error_Codes UART Error Codes + * @{ + */ + +#define HAL_UART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ + +/** + * @} + */ + /** @defgroup UART_Word_Length UART Word Length * @{ */ #define UART_WORDLENGTH_8B ((uint32_t)0x00000000) #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ - ((LENGTH) == UART_WORDLENGTH_9B)) /** * @} */ @@ -182,8 +182,6 @@ typedef struct */ #define UART_STOPBITS_1 ((uint32_t)0x00000000) #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ - ((STOPBITS) == UART_STOPBITS_2)) /** * @} */ @@ -194,9 +192,6 @@ typedef struct #define UART_PARITY_NONE ((uint32_t)0x00000000) #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ - ((PARITY) == UART_PARITY_EVEN) || \ - ((PARITY) == UART_PARITY_ODD)) /** * @} */ @@ -208,11 +203,6 @@ typedef struct #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == UART_HWCONTROL_NONE) || \ - ((CONTROL) == UART_HWCONTROL_RTS) || \ - ((CONTROL) == UART_HWCONTROL_CTS) || \ - ((CONTROL) == UART_HWCONTROL_RTS_CTS)) /** * @} */ @@ -223,7 +213,7 @@ typedef struct #define UART_MODE_RX ((uint32_t)USART_CR1_RE) #define UART_MODE_TX ((uint32_t)USART_CR1_TE) #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) + /** * @} */ @@ -233,8 +223,6 @@ typedef struct */ #define UART_STATE_DISABLE ((uint32_t)0x00000000) #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) -#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ - ((STATE) == UART_STATE_ENABLE)) /** * @} */ @@ -244,8 +232,6 @@ typedef struct */ #define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) -#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ - ((SAMPLING) == UART_OVERSAMPLING_8)) /** * @} */ @@ -255,19 +241,15 @@ typedef struct */ #define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) -#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) /** * @} */ - + /** @defgroup UART_WakeUp_functions UART Wakeup Functions * @{ */ #define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800) -#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /** * @} */ @@ -293,33 +275,26 @@ typedef struct /** @defgroup UART_Interrupt_definition UART Interrupt Definitions * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register + * - XXXX : Interrupt mask (16 bits) in the Y register * - Y : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register * * @{ - */ -#define UART_IT_PE ((uint32_t)0x10000100) -#define UART_IT_TXE ((uint32_t)0x10000080) -#define UART_IT_TC ((uint32_t)0x10000040) -#define UART_IT_RXNE ((uint32_t)0x10000020) -#define UART_IT_IDLE ((uint32_t)0x10000010) + */ -#define UART_IT_LBD ((uint32_t)0x20000040) -#define UART_IT_CTS ((uint32_t)0x30000400) +#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) +#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) +#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) +#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) +#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) -#define UART_IT_ERR ((uint32_t)0x30000001) +#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE)) -/** - * @} - */ +#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE)) +#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE)) -/** @defgroup UART_Interruption_Mask UART interruptions flag mask - * @{ - */ -#define UART_IT_MASK ((uint32_t)0x0000FFFF) /** * @} */ @@ -327,7 +302,8 @@ typedef struct /** * @} */ - + + /* Exported macro ------------------------------------------------------------*/ /** @defgroup UART_Exported_Macros UART Exported Macros * @{ @@ -336,21 +312,23 @@ typedef struct /** @brief Reset UART handle state * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) -/** @brief Flushs the UART DR register +/** @brief Flush the UART DR register * @param __HANDLE__: specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) -/** @brief Checks whether the specified UART flag is set or not. +/** @brief Check whether the specified UART flag is set or not. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) @@ -367,10 +345,10 @@ typedef struct */ #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -/** @brief Clears the specified UART pending flag. +/** @brief Clear the specified UART pending flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). @@ -393,49 +371,57 @@ typedef struct /** @brief Clear the UART PE pending flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ +}while(0) + + + /** @brief Clear the UART FE pending flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART NE pending flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART ORE pending flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART IDLE pending flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) -/** @brief Enables or disables the specified UART interrupt. +/** @brief Enable the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __INTERRUPT__: specifies the UART interrupt source to check. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__: specifies the UART interrupt source to enable. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt * @arg UART_IT_LBD: LIN Break detection interrupt @@ -447,17 +433,35 @@ typedef struct * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) + + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__: specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) -/** @brief Checks whether the specified UART interrupt has occurred or not. +/** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @param __IT__: specifies the UART interrupt source to check. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) @@ -466,10 +470,10 @@ typedef struct * @arg UART_IT_TC: Transmission complete interrupt * @arg UART_IT_RXNE: Receive Data register not empty interrupt * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ERR: Error interrupt + * @arg UART_IT_ERR: Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == UART_CR2_REG_INDEX)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) /** @brief macros to enables or disables the UART's one bit sampling method @@ -478,20 +482,101 @@ typedef struct * UART peripheral (availability depending on device for UARTy). * @retval None */ -#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) -#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) + +/** @brief Enable CTS flow control + * This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0) + +/** @brief Disable CTS flow control + * This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0) + +/** @brief Enable RTS flow control + * This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0) + +/** @brief Disable RTS flow control + * This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0) + /** @brief Enable UART * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART - * The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -500,34 +585,92 @@ typedef struct * @} */ + /* Private macros --------------------------------------------------------*/ /** @defgroup UART_Private_Macros UART Private Macros * @{ */ +#define UART_CR1_REG_INDEX 1 +#define UART_CR2_REG_INDEX 2 +#define UART_CR3_REG_INDEX 3 + #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_))) #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100) #define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100) -#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F)) - +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */ +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0)) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F)) #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_))) #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100) -#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F)) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 8 + 50) / 100) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4) + \ + ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8) << 1)) + \ + (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07)) +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#define IS_UART_LIN_WORD_LENGTH(LENGTH) ((LENGTH) == UART_WORDLENGTH_8B) + +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) + +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) + +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) + +#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00) && \ + ((MODE) != (uint32_t)0x00000000)) + +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) + +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +#define IS_UART_LIN_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16) + +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) + +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) + -/** @brief Check UART Baud rate - * @param __BAUDRATE__: Baudrate specified by the user +/** Check UART Baud rate + * __BAUDRATE__: Baudrate specified by the user * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval Test result (TRUE or FALSE). + * Return : TRUE or FALSE */ #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001) -#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) + +/** Check UART Node Address + * __ADDRESS__: UART Node address specified by the user + * UART Node address is used in Multi processor communication for wakeup + * with address mark detection. + * This parameter must be a number between Min_Data = 0 and Max_Data = 15 + * Return : TRUE or FALSE + */ +#define IS_UART_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) + +/** UART interruptions flag mask + */ +#define UART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ + USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) + /** * @} */ - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.c index 9127e1d23ec..a8111918283 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_usart.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: @@ -23,7 +23,7 @@ (##) Enable the USARTx interface clock. (##) USART pins configuration: (+++) Enable the clock for the USART GPIOs. - (+++) Configure these USART pins as alternate function pull-up. + (+++) Configure the USART pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -36,6 +36,8 @@ (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the husart Init structure. @@ -60,13 +62,9 @@ =================================== [..] (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() - (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_USART_TxCpltCallback (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() - (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can add his own code by customization of function pointer HAL_USART_RxCpltCallback (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can @@ -102,6 +100,7 @@ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt + (+) __HAL_USART_GET_IT_SOURCE: Check whether the specified USART interrupt has occurred or not [..] (@) You can refer to the USART HAL driver header file for more useful macros @@ -110,7 +109,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -155,12 +154,11 @@ * @{ */ #define DUMMY_DATA 0xFFFF -#define USART_TIMEOUT_VALUE 22000 /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup USART_Private_Functions USART Private Functions @@ -188,7 +186,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar * @{ */ -/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -202,21 +200,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar (++) Baud Rate (++) Word Length (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ + (++) Parity (++) USART polarity (++) USART phase (++) USART LastBit @@ -229,6 +213,24 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar @endverbatim * @{ */ + +/* + Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ +*/ /** * @brief Initializes the USART mode according to the specified @@ -240,7 +242,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) { /* Check the USART handle allocation */ - if(husart == HAL_NULL) + if(husart == NULL) { return HAL_ERROR; } @@ -250,6 +252,9 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_RESET) { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_USART_MspInit(husart); } @@ -284,7 +289,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { /* Check the USART handle allocation */ - if(husart == HAL_NULL) + if(husart == NULL) { return HAL_ERROR; } @@ -317,8 +322,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) */ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_MspInit could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_MspInit can be implemented in the user file */ } @@ -330,8 +338,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) */ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_MspDeInit could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_MspDeInit can be implemented in the user file */ } @@ -365,7 +376,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) using DMA mode. The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process + will be executed respectively at the end of the transmit or Receive process The HAL_USART_ErrorCallback() user callback will be executed when a communication error is detected @@ -415,7 +426,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -492,7 +503,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == HAL_NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -595,7 +606,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -703,7 +714,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -752,7 +763,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == HAL_NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -766,6 +777,9 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; + /* Process Unlocked */ + __HAL_UNLOCK(husart); + /* Enable the USART Data Register not empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); @@ -775,9 +789,6 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(husart); - /* Send dummy byte in order to generate the clock for the slave to send data */ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); @@ -802,7 +813,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -819,6 +830,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; + /* Process Unlocked */ + __HAL_UNLOCK(husart); + /* Enable the USART Data Register not empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); @@ -828,9 +842,6 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); - /* Process Unlocked */ - __HAL_UNLOCK(husart); - /* Enable the USART Transmit Data Register Empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); @@ -856,7 +867,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -883,6 +894,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); @@ -914,7 +928,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == HAL_NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -987,7 +1001,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1028,6 +1042,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); + /* Clear the Overrun flag: mandatory for the second transfer in circular mode */ __HAL_USART_CLEAR_OREFLAG(husart); @@ -1105,19 +1122,18 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) */ /* Abort the USART DMA Tx channel */ - if(husart->hdmatx != HAL_NULL) + if(husart->hdmatx != NULL) { HAL_DMA_Abort(husart->hdmatx); } /* Abort the USART DMA Rx channel */ - if(husart->hdmarx != HAL_NULL) + if(husart->hdmarx != NULL) { HAL_DMA_Abort(husart->hdmarx); } /* Disable the USART Tx/Rx DMA requests */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); husart->State = HAL_USART_STATE_READY; @@ -1132,56 +1148,53 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) */ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { - uint32_t tmp1 = 0, tmp2 = 0; + uint32_t tmp_flag = 0, tmp_it_source = 0; - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE); + tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE); + tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE); /* USART parity error interrupt occurred -----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_USART_CLEAR_PEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_PE; } - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); + tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE); + tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); /* USART frame error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_USART_CLEAR_FEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_FE; } - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); + tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE); /* USART noise error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_USART_CLEAR_NEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_NE; } - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); + tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE); /* USART Over-Run interrupt occurred ---------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { - __HAL_USART_CLEAR_OREFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_ORE; } if(husart->ErrorCode != HAL_USART_ERROR_NONE) { + /* Clear all the error flag at once */ + __HAL_USART_CLEAR_PEFLAG(husart); + /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; HAL_USART_ErrorCallback(husart); } - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE); + tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE); + tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE); /* USART in mode Receiver --------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { if(husart->State == HAL_USART_STATE_BUSY_RX) { @@ -1193,10 +1206,10 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } } - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE); + tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE); + tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE); /* USART in mode Transmitter -----------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { if(husart->State == HAL_USART_STATE_BUSY_TX) { @@ -1208,10 +1221,10 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } } - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC); + tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC); + tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC); /* USART in mode Transmitter (transmission end) -----------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((tmp_flag != RESET) && (tmp_it_source != RESET)) { USART_EndTransmit_IT(husart); } @@ -1227,8 +1240,11 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_TxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback can be implemented in the user file */ } @@ -1240,8 +1256,11 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) */ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_TxHalfCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback can be implemented in the user file */ } @@ -1253,8 +1272,11 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_RxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback can be implemented in the user file */ } @@ -1266,8 +1288,11 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_RxHalfCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback can be implemented in the user file */ } @@ -1279,8 +1304,11 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_TxRxCpltCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback can be implemented in the user file */ } @@ -1292,8 +1320,11 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_ErrorCallback could be implemented in the user file + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback can be implemented in the user file */ } @@ -1365,27 +1396,18 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { husart->TxXferCount = 0; + if(husart->State == HAL_USART_STATE_BUSY_TX) { - /* Wait for USART TC Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - husart->State = HAL_USART_STATE_TIMEOUT; - HAL_USART_ErrorCallback(husart); - } - else - { - /* No Timeout */ - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - husart->State= HAL_USART_STATE_READY; - HAL_USART_TxCpltCallback(husart); - } + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } } /* DMA Circular mode */ @@ -1422,7 +1444,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { husart->RxXferCount = 0; if(husart->State == HAL_USART_STATE_BUSY_RX) @@ -1431,6 +1453,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) in the USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + husart->State= HAL_USART_STATE_READY; HAL_USART_RxCpltCallback(husart); } /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ @@ -1438,12 +1461,11 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); + husart->State= HAL_USART_STATE_READY; HAL_USART_TxRxCpltCallback(husart); } - husart->State= HAL_USART_STATE_READY; } /* DMA circular mode */ else @@ -1814,7 +1836,6 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) static void USART_SetConfig(USART_HandleTypeDef *husart) { /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); @@ -1837,16 +1858,17 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) /* Write to USART CR2 */ MODIFY_REG(husart->Instance->CR2, (uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP), - ((uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits))); + ((uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits))); /*-------------------------- USART CR1 Configuration -----------------------*/ /* Configure the USART Word Length, Parity and mode: Set the M bits according to husart->Init.WordLength value Set PCE and PS bits according to husart->Init.Parity value - Set TE and RE bits according to husart->Init.Mode value */ + Set TE and RE bits according to husart->Init.Mode value + Force OVER8 bit to 1 in order to reach the max USART frequencies */ MODIFY_REG(husart->Instance->CR1, - (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), - (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode); + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Clear CTSE and RTSE bits */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.h index 658d71f3dea..0bb15bd6778 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l1xx_hal_usart.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief This file contains all the functions prototypes for the USART * firmware library. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,8 +83,8 @@ typedef struct at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_Mode */ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. @@ -113,49 +113,37 @@ typedef enum HAL_USART_STATE_ERROR = 0x04 /*!< Error */ }HAL_USART_StateTypeDef; -/** - * @brief HAL USART Error Code structure definition - */ -typedef enum -{ - HAL_USART_ERROR_NONE = 0x00, /*!< No error */ - HAL_USART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_USART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_USART_ERROR_FE = 0x04, /*!< frame error */ - HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_USART_ErrorTypeDef; /** * @brief USART handle Structure definition */ typedef struct { - USART_TypeDef *Instance; /* USART registers base address */ - - USART_InitTypeDef Init; /* Usart communication parameters */ + USART_TypeDef *Instance; /*!< USART registers base address */ - uint8_t *pTxBuffPtr; /* Pointer to Usart Tx transfer Buffer */ + USART_InitTypeDef Init; /*!< Usart communication parameters */ - uint16_t TxXferSize; /* Usart Tx Transfer size */ + uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */ - __IO uint16_t TxXferCount; /* Usart Tx Transfer Counter */ + uint16_t TxXferSize; /*!< Usart Tx Transfer size */ - uint8_t *pRxBuffPtr; /* Pointer to Usart Rx transfer Buffer */ + __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */ - uint16_t RxXferSize; /* Usart Rx Transfer size */ + uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */ - __IO uint16_t RxXferCount; /* Usart Rx Transfer Counter */ + uint16_t RxXferSize; /*!< Usart Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /* Usart Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* Usart Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_USART_StateTypeDef State; /* Usart communication state */ + __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */ - __IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */ + __IO uint32_t ErrorCode; /*!< USART Error code */ }USART_HandleTypeDef; @@ -168,13 +156,24 @@ typedef struct * @{ */ +/** @defgroup USART_Error_Codes USART Error Codes + * @{ + */ +#define HAL_USART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_USART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_USART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_USART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_USART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +/** + * @} + */ + /** @defgroup USART_Word_Length USART Word Length * @{ */ -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ - ((LENGTH) == USART_WORDLENGTH_9B)) +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /** * @} */ @@ -182,14 +181,10 @@ typedef struct /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ -#define USART_STOPBITS_1 ((uint32_t)0x00000000) -#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) -#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ - ((STOPBITS) == USART_STOPBITS_0_5) || \ - ((STOPBITS) == USART_STOPBITS_1_5) || \ - ((STOPBITS) == USART_STOPBITS_2)) +#define USART_STOPBITS_1 ((uint32_t)0x00000000) +#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) +#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /** * @} */ @@ -197,12 +192,9 @@ typedef struct /** @defgroup USART_Parity USART Parity * @{ */ -#define USART_PARITY_NONE ((uint32_t)0x00000000) -#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ - ((PARITY) == USART_PARITY_EVEN) || \ - ((PARITY) == USART_PARITY_ODD)) +#define USART_PARITY_NONE ((uint32_t)0x00000000) +#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** * @} */ @@ -210,10 +202,10 @@ typedef struct /** @defgroup USART_Mode USART Mode * @{ */ -#define USART_MODE_RX ((uint32_t)USART_CR1_RE) -#define USART_MODE_TX ((uint32_t)USART_CR1_TE) -#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) +#define USART_MODE_RX ((uint32_t)USART_CR1_RE) +#define USART_MODE_TX ((uint32_t)USART_CR1_TE) +#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) + /** * @} */ @@ -221,10 +213,8 @@ typedef struct /** @defgroup USART_Clock USART Clock * @{ */ -#define USART_CLOCK_DISABLED ((uint32_t)0x00000000) -#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \ - ((CLOCK) == USART_CLOCK_ENABLED)) +#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) +#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /** * @} */ @@ -232,9 +222,8 @@ typedef struct /** @defgroup USART_Clock_Polarity USART Clock Polarity * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x00000000) -#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) -#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) +#define USART_POLARITY_LOW ((uint32_t)0x00000000) +#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /** * @} */ @@ -242,9 +231,8 @@ typedef struct /** @defgroup USART_Clock_Phase USART Clock Phase * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x00000000) -#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) -#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) +#define USART_PHASE_1EDGE ((uint32_t)0x00000000) +#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /** * @} */ @@ -252,10 +240,8 @@ typedef struct /** @defgroup USART_Last_Bit USART Last Bit * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) -#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ - ((LASTBIT) == USART_LASTBIT_ENABLE)) +#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) +#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /** * @} */ @@ -263,10 +249,8 @@ typedef struct /** @defgroup USART_NACK_State USART NACK State * @{ */ -#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK) -#define USARTNACK_DISABLED ((uint32_t)0x00000000) -#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \ - ((NACK) == USARTNACK_DISABLED)) +#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK) +#define USART_NACK_DISABLE ((uint32_t)0x00000000) /** * @} */ @@ -277,50 +261,43 @@ typedef struct * @{ */ -#define USART_FLAG_CTS ((uint32_t)USART_SR_CTS) -#define USART_FLAG_LBD ((uint32_t)USART_SR_LBD) -#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define USART_FLAG_TC ((uint32_t)USART_SR_TC) -#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define USART_FLAG_NE ((uint32_t)USART_SR_NE) -#define USART_FLAG_FE ((uint32_t)USART_SR_FE) -#define USART_FLAG_PE ((uint32_t)USART_SR_PE) +#define USART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define USART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define USART_FLAG_TC ((uint32_t)USART_SR_TC) +#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define USART_FLAG_NE ((uint32_t)USART_SR_NE) +#define USART_FLAG_FE ((uint32_t)USART_SR_FE) +#define USART_FLAG_PE ((uint32_t)USART_SR_PE) /** * @} */ /** @defgroup USART_Interrupt_definition USART Interrupts Definition * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register + * - XXXX : Interrupt mask (16 bits) in the Y register * - Y : Interrupt source register (4bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register * * @{ */ -#define USART_IT_PE ((uint32_t)0x10000100) -#define USART_IT_TXE ((uint32_t)0x10000080) -#define USART_IT_TC ((uint32_t)0x10000040) -#define USART_IT_RXNE ((uint32_t)0x10000020) -#define USART_IT_IDLE ((uint32_t)0x10000010) -#define USART_IT_LBD ((uint32_t)0x20000040) -#define USART_IT_CTS ((uint32_t)0x30000400) +#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) +#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) +#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) +#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) +#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) -#define USART_IT_ERR ((uint32_t)0x30000001) +#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE)) +#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE)) +#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE)) -/** - * @} - */ -/** @defgroup USART_Interruption_Mask USART interruptions flag mask - * @{ - */ -#define USART_IT_MASK ((uint32_t)0x0000FFFF) /** * @} */ @@ -328,7 +305,8 @@ typedef struct /** * @} */ - + + /* Exported macro ------------------------------------------------------------*/ /** @defgroup USART_Exported_Macros USART Exported Macros * @{ @@ -337,14 +315,14 @@ typedef struct /** @brief Reset USART handle state * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) -/** @brief Checks whether the specified USART flag is set or not. +/** @brief Check whether the specified USART flag is set or not. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg USART_FLAG_TXE: Transmit data register empty flag @@ -360,9 +338,9 @@ typedef struct #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -/** @brief Clears the specified USART pending flags. +/** @brief Clear the specified USART pending flags. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: * @arg USART_FLAG_TC: Transmission Complete flag. @@ -383,43 +361,50 @@ typedef struct /** @brief Clear the USART PE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ -#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ +}while(0) + + /** @brief Clear the USART FE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART NE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART ORE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART IDLE pending flag. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) -/** @brief Enables or disables the specified Usart interrupts. +/** @brief Enable the specified Usart interrupts. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @param __INTERRUPT__: specifies the USART interrupt source to check. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). + * @param __INTERRUPT__: specifies the USART interrupt source to enable. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt @@ -429,18 +414,33 @@ typedef struct * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) + + +/** @brief Disable the specified Usart interrupts. + * @param __HANDLE__: specifies the USART Handle. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). + * @param __INTERRUPT__: specifies the USART interrupt source to disable. + * This parameter can be one of the following values: + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) -/** @brief Checks whether the specified Usart interrupt has occurred or not. +/** @brief Check whether the specified Usart interrupt has occurred or not. * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __IT__: specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt @@ -451,21 +451,33 @@ typedef struct * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == USART_CR2_REG_INDEX)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) +/** @brief Enables the USART one bit sample method + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR3, (USART_CR3_ONEBIT)) + +/** @brief Disables the UART one bit sample method + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR3,(USART_CR3_ONEBIT)) + /** @brief Enable USART * @param __HANDLE__: specifies the USART Handle. - * The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None - */ + */ #define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) /** @brief Disable USART * @param __HANDLE__: specifies the USART Handle. - * The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral + * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None - */ + */ #define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) @@ -473,23 +485,62 @@ typedef struct * @} */ + /* Private macros --------------------------------------------------------*/ /** @defgroup USART_Private_Macros USART Private Macros * @{ */ -#define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) +#define USART_CR1_REG_INDEX 1 +#define USART_CR2_REG_INDEX 2 +#define USART_CR3_REG_INDEX 3 + +#define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(2*(__BAUD__))) #define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100) #define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -#define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) +#define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x07)) -/** @brief Check USART Baud rate - * @param __BAUDRATE__: Baudrate specified by the user - * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval Test result (TRUE or FALSE) +/** Check USART Baud rate + * __BAUDRATE__: Baudrate specified by the user + * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * return : TRUE or FALSE */ #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ + ((LENGTH) == USART_WORDLENGTH_9B)) + +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ + ((STOPBITS) == USART_STOPBITS_0_5) || \ + ((STOPBITS) == USART_STOPBITS_1_5) || \ + ((STOPBITS) == USART_STOPBITS_2)) + +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ + ((PARITY) == USART_PARITY_EVEN) || \ + ((PARITY) == USART_PARITY_ODD)) + +#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00) && ((MODE) != (uint32_t)0x00000000)) + +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \ + ((CLOCK) == USART_CLOCK_ENABLE)) + +#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) + +#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) + +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ + ((LASTBIT) == USART_LASTBIT_ENABLE)) + +#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \ + ((NACK) == USART_NACK_DISABLE)) + +/** USART interruptions flag mask + * + */ +#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ + USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) + /** * @} */ @@ -501,7 +552,7 @@ typedef struct * @{ */ -/** @addtogroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.c index f92f2d0e3e7..9ef64f79ef0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_hal_wwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -31,8 +31,8 @@ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (mS) = 1000 * (Counter – Window) / WWDG clock - (++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock + (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Min-max timeout value at @32MHz (PCLK1): ~128us / ~65.6ms. @@ -40,7 +40,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE(). + (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Set the WWDG prescaler, refresh window and counter value using HAL_WWDG_Init() function. (+) Start the WWDG using HAL_WWDG_Start() function. @@ -70,7 +70,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -116,7 +116,7 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup WWDG_Exported_Functions WWDG Exported Functions * @{ @@ -151,7 +151,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) { /* Check the WWDG handle allocation */ - if(hwwdg == HAL_NULL) + if(hwwdg == NULL) { return HAL_ERROR; } @@ -164,6 +164,9 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) if(hwwdg->State == HAL_WWDG_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hwwdg->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); } @@ -228,6 +231,9 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) */ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hwwdg); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_WWDG_MspInit could be implemented in the user file */ @@ -241,6 +247,9 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) */ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hwwdg); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_WWDG_MspDeInit could be implemented in the user file */ @@ -309,7 +318,7 @@ HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) hwwdg->State = HAL_WWDG_STATE_BUSY; /* Enable the Early Wakeup Interrupt */ - __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI); + __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI); /* Enable the peripheral */ __HAL_WWDG_ENABLE(hwwdg); @@ -353,7 +362,7 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) * @brief Handles WWDG interrupt request. * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro. + * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function. * When the downcounter reaches the value 0x40, and EWI interrupt is * generated and the corresponding Interrupt Service Routine (ISR) can * be used to trigger specific actions (such as communications or data @@ -363,23 +372,27 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) * @retval None */ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) -{ - /* WWDG Early Wakeup Interrupt occurred */ - if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) +{ + /* Check if Early Wakeup Interrupt is enable */ + if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) { - /* Early Wakeup callback */ - HAL_WWDG_WakeupCallback(hwwdg); + /* Wheck if WWDG Early Wakeup Interrupt occurred */ + if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + { + /* Early Wakeup callback */ + HAL_WWDG_WakeupCallback(hwwdg); - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Clear the WWDG Data Ready flag */ - __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF); + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Clear the WWDG Early Wakeup flag */ + __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); + /* Process Unlocked */ + __HAL_UNLOCK(hwwdg); + } } -} +} /** * @brief Early Wakeup WWDG callback. @@ -389,6 +402,9 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) */ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hwwdg); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_WWDG_WakeupCallback could be implemented in the user file */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.h index e99a07b80d8..3145d289c67 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_hal_wwdg.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -113,23 +113,10 @@ typedef struct * @{ */ -/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress AliasRegion - * @brief WWDG registers bit address in the alias region - * @{ - */ - -/* --- CFR Register ---*/ -/* Alias word address of EWI bit */ -#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04) - -/** - * @} - */ - /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition * @{ */ -#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI) +#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ /** * @} @@ -139,7 +126,7 @@ typedef struct * @brief WWDG Flag definition * @{ */ -#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */ +#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ /** * @} @@ -148,10 +135,10 @@ typedef struct /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ */ -#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ #define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ ((__PRESCALER__) == WWDG_PRESCALER_2) || \ @@ -201,37 +188,49 @@ typedef struct * @param __HANDLE__: WWDG handle * @retval None */ -#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) +#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA) /** - * @brief Gets the selected WWDG's flag status. + * @brief Disables the WWDG peripheral. * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - * @retval The new state of WWDG_FLAG (SET or RESET). + * @note WARNING: This is a dummy macro for HAL code alignment. + * Once enable, WWDG Peripheral cannot be disabled except by a system reset. + * @retval None */ -#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */ /** - * @brief Clears the WWDG's pending flags. + * @brief Enables the WWDG early wakeup interrupt. * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. + * @param __INTERRUPT__: specifies the interrupt to enable. * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @arg WWDG_IT_EWI: Early wakeup interrupt + * @note Once enabled this interrupt cannot be disabled except by a system reset. * @retval None */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) +#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CFR |= (__INTERRUPT__)) /** - * @brief Enables the WWDG early wakeup interrupt. - * @param __INTERRUPT__: specifies the interrupt to enable. + * @brief Disables the WWDG early wakeup interrupt. + * @param __HANDLE__: WWDG handle + * @param __INTERRUPT__: specifies the interrupt to disable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt - * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @note WARNING: This is a dummy macro for HAL code alignment. + * Once enabled this interrupt cannot be disabled except by a system reset. * @retval None */ -#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__)) +#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */ + +/** + * @brief Gets the selected WWDG's it status. + * @param __HANDLE__: WWDG handle + * @param __INTERRUPT__: specifies the it to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Clear the WWDG's interrupt pending bits * bits to clear the selected interrupt pending bits. @@ -240,7 +239,36 @@ typedef struct * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag */ -#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Gets the selected WWDG's flag status. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the WWDG's pending flags. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval None + */ +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Checks if the specified WWDG interrupt source is enabled or disabled. + * @param __HANDLE__: WWDG Handle. + * @param __INTERRUPT__: specifies the WWDG interrupt source to check. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early Wakeup Interrupt + * @retval state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.c index cd74ac5581a..1aa2ef8c319 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_ll_fsmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -20,7 +20,7 @@ (+) The NOR/PSRAM memory controller [..] The FSMC functional block makes the interface with synchronous and asynchronous static - memories and SDRAM memories. Its main purposes are: + memories. Its main purposes are: (+) to translate AHB transactions into the appropriate external device protocol. (+) to meet the access time requirements of the external memory devices. @@ -34,28 +34,12 @@ (++) PSRAM (4 memory banks). (+) Independent Chip Select control for each memory bank. (+) Independent configuration for each memory bank. - - ============================================================================= - ##### How to use NORSRAM device driver ##### - ============================================================================= - - [..] - This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order - to run the NORSRAM external devices. - - (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() - (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() - (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() - (+) FSMC NORSRAM bank extended timing configuration using the function - FSMC_NORSRAM_Extended_Timing_Init() - (+) FSMC NORSRAM bank enable/disable write operation using the functions - FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() @endverbatim ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -89,27 +73,59 @@ * @{ */ +#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) /** @defgroup FSMC_LL FSMC_LL * @brief FSMC driver modules * @{ */ -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ +/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros + * @{ + */ + +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/** @defgroup FSMC_Exported_Functions FSMC Exported Functions +/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions * @{ */ -/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions +/** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() + (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() + (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() + (+) FSMC NORSRAM bank extended timing configuration using the function + FSMC_NORSRAM_Extended_Timing_Init() + (+) FSMC NORSRAM bank enable/disable write operation using the functions + FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() + + +@endverbatim + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -133,11 +149,10 @@ * @param Init: Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef* Init) +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) { - uint32_t tmpr = 0; - /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); assert_param(IS_FSMC_MUX(Init->DataAddressMux)); assert_param(IS_FSMC_MEMORY(Init->MemoryType)); @@ -152,27 +167,32 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_ assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); + /* Disable NORSRAM Device */ + __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); + /* Set NORSRAM device control parameters */ - tmpr = (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WrapMode |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst - ); - if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) { - tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; + MODIFY_REG(Device->BTCR[Init->NSBank], \ + (FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | FSMC_BCRx_MTYP | \ + FSMC_BCRx_MWID | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ + FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | FSMC_BCRx_CBURSTRW), \ + (FSMC_NORSRAM_FLASH_ACCESS_ENABLE | Init->DataAddressMux | Init->MemoryType | \ + Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity | Init->WrapMode | Init->WaitSignalActive |\ + Init->WriteOperation | Init->WaitSignal | Init->ExtendedMode | Init->AsynchronousWait | Init->WriteBurst ) \ + ); + } + else + { + MODIFY_REG(Device->BTCR[Init->NSBank], \ + (FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | FSMC_BCRx_MTYP | \ + FSMC_BCRx_MWID | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ + FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | FSMC_BCRx_CBURSTRW), \ + (FSMC_NORSRAM_FLASH_ACCESS_DISABLE | Init->DataAddressMux | Init->MemoryType | \ + Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity | Init->WrapMode | Init->WaitSignalActive |\ + Init->WriteOperation | Init->WaitSignal | Init->ExtendedMode | Init->AsynchronousWait | Init->WriteBurst ) \ + ); } - - Device->BTCR[Init->NSBank] = tmpr; return HAL_OK; } @@ -185,22 +205,23 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_ * @param Bank: NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Disable the FSMC_NORSRAM device */ __FSMC_NORSRAM_DISABLE(Device, Bank); /* De-initialize the FSMC_NORSRAM device */ /* FSMC_NORSRAM_BANK1 */ - if(Bank == FSMC_BANK1_NORSRAM1) + if(Bank == FSMC_NORSRAM_BANK1) { Device->BTCR[Bank] = 0x000030DB; } - /* FSMC_BANK1_NORSRAM2, FSMC_BANK1_NORSRAM3 or FSMC_BANK1_NORSRAM4 */ + /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ else { Device->BTCR[Bank] = 0x000030D2; @@ -221,11 +242,10 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM * @param Bank: NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0; - /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); @@ -233,19 +253,20 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NO assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Set FSMC_NORSRAM device timing parameters */ - tmpr = (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) |\ - ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) |\ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) |\ - (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) |\ - (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BTRx_DATLAT)) |\ - (Timing->AccessMode) - ); - - Device->BTCR[Bank + 1] = tmpr; - + MODIFY_REG(Device->BTCR[Bank + 1], \ + (FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD | FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN | \ + FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT | FSMC_BTRx_ACCMOD), \ + ( Timing->AddressSetupTime | \ + ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \ + ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) | \ + ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) | \ + (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ + (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BTRx_DATLAT)) | \ + (Timing->AccessMode))); + return HAL_OK; } @@ -261,23 +282,30 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NO * @arg FSMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { + /* Check the parameters */ + assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) { /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) |\ - ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) |\ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)) |\ - (Timing->AccessMode)); + MODIFY_REG(Device->BWTR[Bank], \ + (FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | FSMC_BWTRx_BUSTURN), \ + (Timing->AddressSetupTime | \ + ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ + ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ + Timing->AccessMode | \ + ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)))); } else { @@ -293,7 +321,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPED */ -/** @defgroup HAL_FSMC_NORSRAM_Group2 Control functions +/** @defgroup FSMC_NORSRAM_Group2 Control functions * @brief management functions * @verbatim @@ -314,10 +342,14 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPED * @param Bank: NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) { + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + /* Enable write operation */ - Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; + SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); return HAL_OK; } @@ -328,10 +360,15 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Devic * @param Bank: NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) { + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_NORSRAM_BANK(Bank)); + /* Disable write operation */ - Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; + CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); + return HAL_OK; } @@ -344,14 +381,16 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Devi * @} */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#endif /* HAL_FSMC_MODULE_ENABLED */ /** * @} */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#endif /* HAL_FSMC_MODULE_ENABLED */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h index be6e92b36b1..676b2251882 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_ll_fsmc.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief Header file of FSMC HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,8 +43,6 @@ extern "C" { #endif -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" @@ -52,18 +50,142 @@ * @{ */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + /** @addtogroup FSMC_LL * @{ */ +/** @addtogroup FSMC_LL_Private_Macros + * @{ + */ + +#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ + ((__BANK__) == FSMC_NORSRAM_BANK2) || \ + ((__BANK__) == FSMC_NORSRAM_BANK3) || \ + ((__BANK__) == FSMC_NORSRAM_BANK4)) + +#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) + +#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) + +#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) + +#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ + ((__MODE__) == FSMC_ACCESS_MODE_B) || \ + ((__MODE__) == FSMC_ACCESS_MODE_C) || \ + ((__MODE__) == FSMC_ACCESS_MODE_D)) + +/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance + * @{ + */ + +#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) + +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance + * @{ + */ + +#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) + +/** + * @} + */ + +#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) + +#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) + +#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) + +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) + +#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) + +#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) + +#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) + +#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) + +#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) + +/** @defgroup FSMC_Data_Latency FSMC Data Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) +/** + * @} + */ + +#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) +/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** + * @} + */ + /* Exported typedef ----------------------------------------------------------*/ -/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef +/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types * @{ */ -#define FSMC_NORSRAM_TYPEDEF FSMC_Bank1_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_Bank1E_TypeDef +#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef +#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef #define FSMC_NORSRAM_DEVICE FSMC_Bank1 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E @@ -174,6 +296,10 @@ typedef struct /* Exported constants --------------------------------------------------------*/ +/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants + * @{ + */ + /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants * @{ */ @@ -181,21 +307,11 @@ typedef struct /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank * @{ */ -#define FSMC_BANK1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_BANK1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_BANK1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_BANK1_NORSRAM4 ((uint32_t)0x00000006) - -/* To keep compatibility with previous families */ -#define FSMC_NORSRAM_BANK1 FSMC_BANK1_NORSRAM1 -#define FSMC_NORSRAM_BANK2 FSMC_BANK1_NORSRAM2 -#define FSMC_NORSRAM_BANK3 FSMC_BANK1_NORSRAM3 -#define FSMC_NORSRAM_BANK4 FSMC_BANK1_NORSRAM4 +#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000) +#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002) +#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004) +#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006) -#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \ - ((__BANK__) == FSMC_BANK1_NORSRAM2) || \ - ((__BANK__) == FSMC_BANK1_NORSRAM3) || \ - ((__BANK__) == FSMC_BANK1_NORSRAM4)) /** * @} */ @@ -207,8 +323,6 @@ typedef struct #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) -#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) /** * @} */ @@ -222,9 +336,6 @@ typedef struct #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) -#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) /** * @} */ @@ -237,9 +348,6 @@ typedef struct #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) -#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) /** * @} */ @@ -261,8 +369,6 @@ typedef struct #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) -#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) /** * @} */ @@ -275,8 +381,6 @@ typedef struct #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) -#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) /** * @} */ @@ -288,8 +392,6 @@ typedef struct #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) -#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) /** * @} */ @@ -301,8 +403,6 @@ typedef struct #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) /** * @} */ @@ -314,8 +414,6 @@ typedef struct #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) -#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) /** * @} */ @@ -327,9 +425,6 @@ typedef struct #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) -#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) - /** * @} */ @@ -341,8 +436,6 @@ typedef struct #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) -#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) /** * @} */ @@ -354,9 +447,6 @@ typedef struct #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) -#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) - /** * @} */ @@ -368,81 +458,10 @@ typedef struct #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) -#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time - * @{ - */ - -#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time - * @{ - */ - -#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) /** * @} */ -/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time - * @{ - */ - -#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration - * @{ - */ - -#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division FSMC CLK Division - * @{ - */ - -#define FSMC_CLK_DIV2 ((uint32_t)0x00000002) -#define FSMC_CLK_DIV3 ((uint32_t)0x00000003) -#define FSMC_CLK_DIV4 ((uint32_t)0x00000004) -#define FSMC_CLK_DIV5 ((uint32_t)0x00000005) -#define FSMC_CLK_DIV6 ((uint32_t)0x00000006) -#define FSMC_CLK_DIV7 ((uint32_t)0x00000007) -#define FSMC_CLK_DIV8 ((uint32_t)0x00000008) -#define FSMC_CLK_DIV9 ((uint32_t)0x00000009) -#define FSMC_CLK_DIV10 ((uint32_t)0x0000000A) -#define FSMC_CLK_DIV11 ((uint32_t)0x0000000B) -#define FSMC_CLK_DIV12 ((uint32_t)0x0000000C) -#define FSMC_CLK_DIV13 ((uint32_t)0x0000000D) -#define FSMC_CLK_DIV14 ((uint32_t)0x0000000E) -#define FSMC_CLK_DIV15 ((uint32_t)0x0000000F) -#define FSMC_CLK_DIV16 ((uint32_t)0x00000010) -#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency FSMC Data Latency - * @{ - */ - -#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) -/** - * @} - */ - /** @defgroup FSMC_Access_Mode FSMC Access Mode * @{ */ @@ -452,40 +471,20 @@ typedef struct #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) -#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ - ((__MODE__) == FSMC_ACCESS_MODE_B) || \ - ((__MODE__) == FSMC_ACCESS_MODE_C) || \ - ((__MODE__) == FSMC_ACCESS_MODE_D)) /** * @} */ -/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance - * @{ - */ - -#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) - -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance - * @{ - */ - -#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) - -/** - * @} - */ - /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros + * @{ + */ + /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros * @brief macros to handle NOR device enable/disable and read/write operations * @{ @@ -497,7 +496,7 @@ typedef struct * @param __BANK__: FSMC_NORSRAM Bank * @retval none */ -#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN) +#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -505,7 +504,12 @@ typedef struct * @param __BANK__: FSMC_NORSRAM Bank * @retval none */ -#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN) +#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) + +/** + * @} + */ + /** * @} @@ -513,38 +517,45 @@ typedef struct /* Exported functions --------------------------------------------------------*/ -/** @addtogroup FSMC_Exported_Functions +/** @addtogroup FSMC_LL_Exported_Functions * @{ */ -/** @addtogroup HAL_FSMC_NORSRAM_Group1 +/** @addtogroup FSMC_NORSRAM + * @{ + */ + +/** @addtogroup FSMC_NORSRAM_Group1 * @{ */ /* FSMC_NORSRAM Controller functions ******************************************/ /* Initialization/de-initialization functions */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ -/** @addtogroup HAL_FSMC_NORSRAM_Group2 +/** @addtogroup FSMC_NORSRAM_Group2 * @{ */ /* FSMC_NORSRAM Control functions */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); + +/** + * @} + */ /** * @} */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ /** * @} @@ -554,6 +565,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Dev * @} */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + /** * @} */ @@ -565,3 +578,4 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Dev #endif /* __STM32L1xx_LL_FSMC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.c index 5593941bcbb..80c1d0a83cc 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l1xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 + * @version V1.1.3 + * @date 04-March-2016 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -21,13 +21,6 @@ peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA devices. - [..] The MultiMedia Card system specifications are available through the MultiMedia Card - Association website at www.mmca.org, published by the MMCA technical committee. - SD memory card and SD I/O card system specifications are available through the SD card - Association website at www.sdcard.org. - CE-ATA system specifications are available through the CE-ATA work group web site at - www.ce-ata.org. - [..] The SDIO features include the following: (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit @@ -65,8 +58,8 @@ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO peripheral. - (+) Enable the Power ON State using the SDIO_PowerState_ON(hsdio) - function and disable it using the function SDIO_PowerState_OFF(hsdio). + (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx) + function and disable it using the function SDIO_PowerState_OFF(SDIOx). (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. @@ -80,7 +73,7 @@ __SDIO_DMA_DISABLE(). (+) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDIO_SendCommand(), + commands to the card use the SDIO_SendCommand(SDIOx), SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has to fill the command structure (pointer to SDIO_CmdInitTypeDef) according to the selected command to be sent. @@ -106,7 +99,7 @@ (#) First, user has to fill the data structure (pointer to SDIO_DataInitTypeDef) according to the selected data type to be received. The parameters that should be filled are: - (++) Data TimeOut + (++) Data Timeout (++) Data Length (++) Data Block size (++) Data Transfer direction: should be from card (To SDIO) @@ -126,7 +119,7 @@ (#) First, user has to fill the data structure (pointer to SDIO_DataInitTypeDef) according to the selected data type to be received. The parameters that should be filled are: - (++) Data TimeOut + (++) Data Timeout (++) Data Length (++) Data Block size (++) Data Transfer direction: should be to card (To CARD) @@ -144,7 +137,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -246,8 +239,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) return HAL_OK; } - - /** * @} */ @@ -437,7 +428,7 @@ HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDI assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode)); assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM)); - /* Set the SDIO Data TimeOut value */ + /* Set the SDIO Data Timeout value */ SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut; /* Set the SDIO DataLength value */ @@ -468,7 +459,7 @@ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) /** * @brief Get the FIFO data - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDIO register base * @retval Data received */ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) @@ -495,7 +486,6 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) return HAL_OK; } - /** * @} */ @@ -507,7 +497,6 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h index 283ace2affb..c961c5acbc0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l1xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of low layer SDMMC HAL module. + * @version V1.1.3 + * @date 04-March-2016 + * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,21 +67,21 @@ typedef struct { uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ + This parameter can be a value of @ref SDIO_Clock_Edge */ uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ + This parameter can be a value of @ref SDIO_Clock_Bypass */ uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or disabled when the bus is idle. - This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ + This parameter can be a value of @ref SDIO_Clock_Power_Save */ uint32_t BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ + This parameter can be a value of @ref SDIO_Bus_Wide */ uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ @@ -103,15 +103,15 @@ typedef struct Max_Data = 64 */ uint32_t Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDMMC_LL_Response_Type */ + This parameter can be a value of @ref SDIO_Response_Type */ uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_CPSM_State */ + This parameter can be a value of @ref SDIO_CPSM_State */ }SDIO_CmdInitTypeDef; @@ -125,18 +125,18 @@ typedef struct uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ + This parameter can be a value of @ref SDIO_Data_Block_Size */ uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer is a read or write. - This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ + This parameter can be a value of @ref SDIO_Transfer_Direction */ uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ + This parameter can be a value of @ref SDIO_Transfer_Type */ uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_DPSM_State */ + This parameter can be a value of @ref SDIO_DPSM_State */ }SDIO_DataInitTypeDef; /** @@ -148,7 +148,7 @@ typedef struct * @{ */ -/** @defgroup SDMMC_LL_Clock_Edge Clock Edge +/** @defgroup SDIO_Clock_Edge Clock Edge * @{ */ #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) @@ -160,7 +160,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass +/** @defgroup SDIO_Clock_Bypass Clock Bypass * @{ */ #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) @@ -172,7 +172,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving +/** @defgroup SDIO_Clock_Power_Save Clock Power Saving * @{ */ #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) @@ -184,7 +184,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Bus_Wide Bus Width +/** @defgroup SDIO_Bus_Wide Bus Width * @{ */ #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) @@ -198,7 +198,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control +/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control * @{ */ #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) @@ -210,7 +210,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Clock_Division Clock Division +/** @defgroup SDIO_Clock_Division Clock Division * @{ */ #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) @@ -218,7 +218,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Command_Index Command Index +/** @defgroup SDIO_Command_Index Command Index * @{ */ #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) @@ -226,7 +226,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Response_Type Response Type +/** @defgroup SDIO_Response_Type Response Type * @{ */ #define SDIO_RESPONSE_NO ((uint32_t)0x00000000) @@ -240,7 +240,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt +/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt * @{ */ #define SDIO_WAIT_NO ((uint32_t)0x00000000) @@ -254,7 +254,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_CPSM_State CPSM State +/** @defgroup SDIO_CPSM_State CPSM State * @{ */ #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) @@ -266,7 +266,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Response_Registers Response Register +/** @defgroup SDIO_Response_Registers Response Register * @{ */ #define SDIO_RESP1 ((uint32_t)0x00000000) @@ -282,7 +282,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Data_Length Data Lenght +/** @defgroup SDIO_Data_Length Data Lenght * @{ */ #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) @@ -290,7 +290,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size +/** @defgroup SDIO_Data_Block_Size Data Block Size * @{ */ #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) @@ -328,7 +328,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction +/** @defgroup SDIO_Transfer_Direction Transfer Direction * @{ */ #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) @@ -340,7 +340,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Transfer_Type Transfer Type +/** @defgroup SDIO_Transfer_Type Transfer Type * @{ */ #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) @@ -352,7 +352,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_DPSM_State DPSM State +/** @defgroup SDIO_DPSM_State DPSM State * @{ */ #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) @@ -364,11 +364,11 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode +/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode * @{ */ -#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000) -#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001) +#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) +#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001) #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) @@ -376,7 +376,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources +/** @defgroup SDIO_Interrupt_sources Interrupt Sources * @{ */ #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL @@ -403,12 +403,11 @@ typedef struct #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND - /** * @} */ -/** @defgroup SDMMC_LL_Flags Flags +/** @defgroup SDIO_Flags Flags * @{ */ #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL @@ -435,25 +434,21 @@ typedef struct #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND - /** * @} */ /** * @} - */ - + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros * @{ */ - -/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions - * @brief SDMMC_LL registers bit address in the alias region + +/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region * @{ */ - /* ------------ SDIO registers bit address in the alias region -------------- */ #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) @@ -502,6 +497,14 @@ typedef struct /* Alias word address of SDIOEN bit */ #define SDIOEN_BITNUMBER 0x0B #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions + * @brief SDMMC_LL registers bit address in the alias region + * @{ + */ /* ---------------------- SDIO registers bit mask --------------------------- */ /* --- CLKCR Register ---*/ @@ -510,6 +513,7 @@ typedef struct SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) +/* --- PWRCTRL Register ---*/ /* --- DCTRL Register ---*/ /* SDIO DCTRL Clear Mask */ #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ @@ -524,7 +528,7 @@ typedef struct /* SDIO RESP Registers Address */ #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) -/* SDIO Intialization Frequency (400KHz max) */ +/* SDIO Initialization Frequency (400KHz max) */ #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* SDIO Data Transfer Frequency */ @@ -533,12 +537,12 @@ typedef struct /** * @} */ - + /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration * @brief macros to handle interrupts and specific clock configurations * @{ */ - + /** * @brief Enable the SDIO device. * @retval None @@ -830,11 +834,11 @@ typedef struct /** * @} */ - + /** * @} - */ - + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SDMMC_LL_Exported_Functions * @{ @@ -848,7 +852,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); /** * @} */ - + /* I/O operation functions *****************************************************/ /** @addtogroup HAL_SDMMC_LL_Group2 * @{ @@ -880,6 +884,7 @@ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); /* SDIO IO Cards mode management functions */ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); + /** * @} */ @@ -895,7 +900,7 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); /** * @} */ - + #ifdef __cplusplus } #endif From 84e65c7ee3018d67d84fa5aa66d301c4270bbc58 Mon Sep 17 00:00:00 2001 From: svastm Date: Wed, 25 May 2016 17:20:16 +0200 Subject: [PATCH 2/4] [STM32L1XX] Init daylight saving time --- hal/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c index 66d4437a431..cdf2e6976af 100755 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c @@ -193,6 +193,8 @@ time_t rtc_read(void) timeinfo.tm_hour = timeStruct.Hours; timeinfo.tm_min = timeStruct.Minutes; timeinfo.tm_sec = timeStruct.Seconds; + // Daylight Saving Time information is not available + timeinfo.tm_isdst = -1; // Convert to timestamp time_t t = mktime(&timeinfo); From 3243b38f5b43c38ec4b2ae654905cb2987e8e0e7 Mon Sep 17 00:00:00 2001 From: svastm Date: Wed, 25 May 2016 17:55:22 +0200 Subject: [PATCH 3/4] [STM32L1XX] Fix deinit of SystemCoreClock on ARM toolchain --- hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c index b486ffcb847..3c1a3a04ef2 100755 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c @@ -66,6 +66,9 @@ static void init_uart(serial_t *obj) UartHandle.Init.Mode = UART_MODE_TX_RX; } + // Fix because HAL_RCC_GetHCLKFreq() don't update anymore SystemCoreClock + SystemCoreClockUpdate(); + HAL_UART_Init(&UartHandle); } From 6ebb2e6c6c0fdd86dd6f99c5053fbb518b6b1b54 Mon Sep 17 00:00:00 2001 From: svastm Date: Thu, 26 May 2016 09:25:19 +0200 Subject: [PATCH 4/4] [STM32L1XX] Reset UART on init --- .../hal/TARGET_STM/TARGET_STM32L1/serial_api.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c index 3c1a3a04ef2..434bd4344d5 100755 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c @@ -66,7 +66,7 @@ static void init_uart(serial_t *obj) UartHandle.Init.Mode = UART_MODE_TX_RX; } - // Fix because HAL_RCC_GetHCLKFreq() don't update anymore SystemCoreClock + // Fix because HAL_RCC_GetHCLKFreq() don't update anymore SystemCoreClock SystemCoreClockUpdate(); HAL_UART_Init(&UartHandle); @@ -84,28 +84,38 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) // Enable UART clock if (obj->uart == UART_1) { + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); __USART1_CLK_ENABLE(); obj->index = 0; } if (obj->uart == UART_2) { + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); __USART2_CLK_ENABLE(); obj->index = 1; } if (obj->uart == UART_3) { + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); __USART3_CLK_ENABLE(); obj->index = 2; } #if defined(UART4_BASE) if (obj->uart == UART_4) { + __HAL_RCC_UART4_FORCE_RESET(); + __HAL_RCC_UART4_RELEASE_RESET(); __UART4_CLK_ENABLE(); obj->index = 3; } #endif #if defined(UART5_BASE) if (obj->uart == UART_5) { + __HAL_RCC_UART5_FORCE_RESET(); + __HAL_RCC_UART5_RELEASE_RESET(); __UART5_CLK_ENABLE(); obj->index = 4; }