From 0d3268b61c0fa7f5fedfa7341fa2b31a5583258e Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Wed, 11 May 2016 14:57:33 +0100 Subject: [PATCH 1/6] [BEETLE] Add initial support This patch adds support for the BEETLE Target. The compilers supported by this target are: * ARMCC * GCC ARM The exporters and the CMSIS/HAL components will follow in future patches. Signed-off-by: Vincenzo Frascino --- hal/targets.json | 9 +++++++++ tools/build_release.py | 5 +++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hal/targets.json b/hal/targets.json index f49d04e38f2..eccd116003f 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -1532,6 +1532,15 @@ "macros": ["CMSDK_BEID"], "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"] }, + "ARM_BEETLE_SOC": { + "inherits": ["ARM_IOTSS_Target"], + "core": "Cortex-M3", + "supported_toolchains": ["ARM", "GCC_ARM"], + "default_toolchain": "ARM", + "extra_labels": ["ARM_SSG", "BEETLE"], + "macros": ["CMSDK_BEETLE", "WSF_MS_PER_TICK=20", "WSF_TOKEN_ENABLED=FALSE", "WSF_TRACE_ENABLED=TRUE", "WSF_ASSERT_ENABLED=FALSE", "WSF_PRINTF_MAX_LEN=128", "ASIC", "CONFIG_HOST_REV=0x20", "CONFIG_ALLOW_DEEP_SLEEP=FALSE", "HCI_VS_TARGET", "CONFIG_ALLOW_SETTING_WRITE=TRUE", "WSF_MAX_HANDLERS=20", "NO_LEDS"], + "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI"] + }, "RZ_A1H": { "supported_form_factors": ["ARDUINO"], "core": "Cortex-A9", diff --git a/tools/build_release.py b/tools/build_release.py index d9d3683a17e..5299ec76e36 100644 --- a/tools/build_release.py +++ b/tools/build_release.py @@ -127,6 +127,7 @@ ('ARM_MPS2_M4' , ('ARM',)), ('ARM_MPS2_M7' , ('ARM',)), ('ARM_IOTSS_BEID' , ('ARM',)), + ('ARM_BEETLE_SOC' , ('ARM', 'GCC_ARM')), ('RZ_A1H' , ('ARM', 'GCC_ARM')), @@ -217,7 +218,7 @@ if platforms is not None and not target_name in platforms: print("Excluding %s from release" % target_name) continue - + if target_name not in TARGET_NAMES: print "Target '%s' is not a valid target. Excluding from release" continue @@ -257,7 +258,7 @@ if platforms is not None and not target_name in platforms: print("Excluding %s from release" % target_name) continue - + if target_name not in TARGET_NAMES: print "Target '%s' is not a valid target. Excluding from release" continue From 44be0626a6d6e1de5ff1cc48afe4adbd7c034bae Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Wed, 11 May 2016 15:45:03 +0100 Subject: [PATCH 2/6] [BEETLE] Add initial Beetle CMSIS files This patch adds support for BEETLE SoC Target into the CMSIS layer. It contains: * Beetle System Core * APB DualTimer Driver * APB Timer Driver * eFlash Driver * Flash Cache Driver * ARM Toolchain Support * GCC ARM Toolchain Support Signed-off-by: Vincenzo Frascino --- .../TARGET_BEETLE/CMSDK_BEETLE.h | 1027 +++++++++++++++++ .../TOOLCHAIN_ARM_STD/BEETLE.sct | 35 + .../TOOLCHAIN_ARM_STD/startup_BEETLE.s | 316 +++++ .../TARGET_BEETLE/TOOLCHAIN_GCC_ARM/BEETLE.ld | 181 +++ .../TOOLCHAIN_GCC_ARM/startup_BEETLE.S | 273 +++++ .../TARGET_BEETLE/apb_dualtimer.c | 360 ++++++ .../TARGET_BEETLE/apb_dualtimer.h | 142 +++ .../TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.c | 236 ++++ .../TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.h | 98 ++ .../TARGET_ARM_SSG/TARGET_BEETLE/cmsis.h | 44 + .../TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.c | 43 + .../TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.h | 39 + .../TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c | 357 ++++++ .../TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h | 154 +++ .../TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c | 200 ++++ .../TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h | 106 ++ .../TARGET_BEETLE/system_CMSDK_BEETLE.c | 95 ++ .../TARGET_BEETLE/system_CMSDK_BEETLE.h | 59 + .../TARGET_BEETLE/system_core_beetle.c | 121 ++ .../TARGET_BEETLE/system_core_beetle.h | 71 ++ .../TARGET_BEETLE/system_core_version.c | 39 + .../TARGET_BEETLE/system_core_version.h | 45 + .../TARGET_BEETLE/systick_timer.c | 90 ++ .../TARGET_BEETLE/systick_timer.h | 51 + 24 files changed, 4182 insertions(+) create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/CMSDK_BEETLE.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/BEETLE.sct create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/startup_BEETLE.s create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/BEETLE.ld create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/startup_BEETLE.S create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.h create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.c create mode 100644 hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.h diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/CMSDK_BEETLE.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/CMSDK_BEETLE.h new file mode 100644 index 00000000000..08ffa4e11bd --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/CMSDK_BEETLE.h @@ -0,0 +1,1027 @@ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 ARMCM3.h + */ + + +#ifndef CMSDK_BEETLE_H +#define CMSDK_BEETLE_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* --------------------- CMSDK_BEETLE Specific Interrupt Numbers ---------------- */ + UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */ + Spare_IRQn = 1, /* Undefined */ + UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */ + I2C0_IRQn = 3, /* I2C 0 Interrupt */ + I2C1_IRQn = 4, /* I2C 1 Interrupt */ + RTC_IRQn = 5, /* RTC Interrupt */ + PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */ + PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ + SPI0_IRQn = 11, /* SPI 0 Interrupt */ + UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ + SPI1_IRQn = 13, /* SPI 1 Interrupt */ + QSPI_IRQn = 14, /* QUAD SPI Interrupt */ + DMA_IRQn = 15, /* Reserved for DMA Interrup */ + PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ + PORT0_1_IRQn = 17, /* There are 16 pins in total */ + PORT0_2_IRQn = 18, + PORT0_3_IRQn = 19, + PORT0_4_IRQn = 20, + PORT0_5_IRQn = 21, + PORT0_6_IRQn = 22, + PORT0_7_IRQn = 23, + PORT0_8_IRQn = 24, + PORT0_9_IRQn = 25, + PORT0_10_IRQn = 26, + PORT0_11_IRQn = 27, + PORT0_12_IRQn = 28, + PORT0_13_IRQn = 29, + PORT0_14_IRQn = 30, + PORT0_15_IRQn = 31, + SYSERROR_IRQn = 32, /* System Error Interrupt */ + EFLASH_IRQn = 33, /* Embedded Flash Interrupt */ + LLCC_TXCMD_EMPTY_IRQn = 34, /* t.b.a */ + LLCC_TXEVT_EMPTY_IRQn = 35, /* t.b.a */ + LLCC_TXDMAH_DONE_IRQn = 36, /* t.b.a */ + LLCC_TXDMAL_DONE_IRQn = 37, /* t.b.a */ + LLCC_RXCMD_VALID_IRQn = 38, /* t.b.a */ + LLCC_RXEVT_VALID_IRQn = 39, /* t.b.a */ + LLCC_RXDMAH_DONE_IRQn = 40, /* t.b.a */ + LLCC_RXDMAL_DONE_IRQn = 41, /* t.b.a */ + PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */ + PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */ + TRNG_IRQn = 44, /* Random number generator Interrupt */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ +#define __CM3_REV 0x0201U /* Core revision r2p1 */ +#define __MPU_PRESENT 1 /* MPU present */ +#define __VTOR_PRESENT 1 /* VTOR present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_BEETLE.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/* ======================================================================== */ +/* ============ LLCC/DMAC v1 ============ */ +/* ======================================================================== */ + +typedef struct +{ + __IO uint32_t BUF_STATE; // +0x00 + __I uint32_t STATUS; // +0x00 + __IO uint32_t PTR_ADDR; // +0x08 + __IO uint32_t PTR_CTRL; // +0x0c + __O uint32_t NXT_ADDR; // +0x10 + __O uint32_t NXT_CTRL; // +0x14 + __I uint32_t rsvd_18[2]; // +0x18 + __IO uint32_t BUF0_ADDR; // +0x20 + __IO uint32_t BUF0_CTRL; // +0x24 + __I uint32_t rsvd_28[2]; // +0x28 + __IO uint32_t BUF1_ADDR; // +0x30 + __IO uint32_t BUF1_CTRL; // +0x34 + __IO uint32_t INTEN; // +0x38 + __IO uint32_t IRQSTATUS; // +0x3c +} DMAC_CHAN_TypeDef; + +// DMA buffer control state machine +#define DMAC_BUFSTATE_MT 0 +#define DMAC_BUFSTATE_A 1 +#define DMAC_BUFSTATE_AB 5 +#define DMAC_BUFSTATE_B 2 +#define DMAC_BUFSTATE_BA 6 +#define DMAC_BUFSTATE_FULL_IDX 2 + +// DMA Control structure MASKs +#define DMAC_CHAN_ADDR_MASK 0xfffffffc +#define DMAC_CHAN_COUNT_MASK 0x0000ffff +#define DMAC_CHAN_SIZE_MASK 0x00030000 +#define DMAC_CHAN_AFIX_MASK 0x00040000 +#define DMAC_CHAN_LOOP_MASK 0x00080000 +#define DMAC_CHAN_ATTR_MASK 0xfff00000 +#define DMAC_CHAN_COUNT_IDX_LO 0 +#define DMAC_CHAN_COUNT_IDX_HI 15 +#define DMAC_CHAN_SIZE_IDX_LO 16 +#define DMAC_CHAN_SIZE_IDX_HI 17 +#define DMAC_CHAN_AFIX_IDX 18 +#define DMAC_CHAN_LOOP_IDX 19 +#define DMAC_CHAN_TRIG_IDX_LO 20 +#define DMAC_CHAN_TRIG_IDX_HI 23 +#define DMAC_CHAN_ATTR_IDX_LO 24 +#define DMAC_CHAN_ATTR_IDX_HI 31 +#define DMAC_CHAN_IRQ_IDX 0 +#define DMAC_CHAN_ERR_IDX 1 + +typedef struct +{ + __I uint32_t ID_MAIN; // +0x0000 + __I uint32_t ID_REV; // +0x0004 + __I uint32_t rsvd_0008[30]; // +0x0008 + __IO uint32_t STANDBY_CTRL; // +0x0080 +} LLCC_CTL_TypeDef; + +typedef struct +{ + __I uint32_t CMD_DATA0; // +0x2000 + __I uint32_t CMD_DATA1; // +0x2004 + __I uint32_t rsvd_008[14]; // +0x2008 + __I uint32_t DMAH_DATA0; // +0x2040 + __I uint32_t DMAH_DATA1; // +0x2044 + __I uint32_t rsvd_048[6]; // +0x2048 + __I uint32_t DMAL_DATA0; // +0x2060 + __I uint32_t DMAL_DATA1; // +0x2064 + __I uint32_t rsvd_068[6]; // +0x2068 + __I uint32_t EVT_DATA0; // +0x2080 + __I uint32_t EVT_DATA1; // +0x2084 + __I uint32_t rsvd_088[14]; // +0x2088 + __I uint32_t INTERRUPT; // +0x20c0 + __IO uint32_t INTENMASK; // +0x20c4 + __IO uint32_t INTENMASK_SET; // +0x20c8 + __IO uint32_t INTENMASK_CLR; // +0x20cc + __I uint32_t REQUEST; // +0x20d0 + __I uint32_t rsvd_0d4[3]; // +0x20d4 + __I uint32_t XFERREQ; // +0x20e0 + __I uint32_t XFERACK; // +0x20e4 + __I uint32_t rsvd_0e8[6]; // +0x20e8 +} LLCC_RXD_TypeDef; + +typedef struct +{ + __IO uint32_t CMD_DATA0; // +0x3000 + __IO uint32_t CMD_DATA1; // +0x3004 + __I uint32_t rsvd_008[14]; // +0x3008 + __IO uint32_t DMAH_DATA0; // +0x3040 + __IO uint32_t DMAH_DATA1; // +0x3044 + __I uint32_t rsvd_048[6]; // +0x3048 + __IO uint32_t DMAL_DATA0; // +0x3060 + __IO uint32_t DMAL_DATA1; // +0x3064 + __I uint32_t rsvd_068[6]; // +0x3068 + __IO uint32_t EVT_DATA0; // +0x3080 + __IO uint32_t EVT_DATA1; // +0x3084 + __I uint32_t rsvd_088[14]; // +0x3088 + __I uint32_t INTERRUPT; // +0x30c0 + __IO uint32_t INTENMASK; // +0x30c4 + __IO uint32_t INTENMASK_SET; // +0x30c8 + __IO uint32_t INTENMASK_CLR; // +0x30cc + __I uint32_t REQUEST; // +0x30d0 + __I uint32_t ACTIVE; // +0x30d4 + __I uint32_t VCREADY; // +0x30d8 + __I uint32_t rsvd_0dc; // +0x30dc + __IO uint32_t XFERREQ; // +0x30e0 + __I uint32_t XFERACK; // +0x30e4 + __I uint32_t rsvd_0e8[6]; // +0x30e8 +} LLCC_TXD_TypeDef; + +// TX?RX buffer handshake/interrupt fields +#define LLCC_CMD0_MASK 0x01 +#define LLCC_CMD1_MASK 0x02 +#define LLCC_CMD_MASK 0x03 +#define LLCC_CMD_IRQ_MASK LLCC_CMD_MASK +#define LLCC_DMAH1_MASK 0x04 +#define LLCC_DMAH2_MASK 0x08 +#define LLCC_DMAH_MASK 0x0c +#define LLCC_DMAL1_MASK 0x10 +#define LLCC_DMAL2_MASK 0x20 +#define LLCC_DMAL_MASK 0x30 +#define LLCC_EVT0_MASK 0x40 +#define LLCC_EVT1_MASK 0x80 +#define LLCC_EVT_IRQ_MASK LLCC_EVT1_MASK +#define LLCC_EVT_MASK 0xc0 +#define LLCC_CMD0_IDX 0 +#define LLCC_CMD1_IDX 1 +#define LLCC_CMD_IDX LLCC_CMD1_IDX +#define LLCC_CMD_IRQ_IDX 1 +#define LLCC_DMAH1_IDX 2 +#define LLCC_DMAH2_IDX 3 +#define LLCC_DMAL1_IDX 4 +#define LLCC_DMAL2_IDX 5 +#define LLCC_EVT0_IDX 6 +#define LLCC_EVT1_IDX 7 +#define LLCC_EVT_IDX LLCC_EVT1_IDX + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_INTSTATUS_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_INTSTATUS_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_INTSTATUS_TXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_INTSTATUS_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_INTSTATUS_RXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_INTSTATUS_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_INTSTATUS_TXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ + uint32_t RESERVED0[3]; + __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */ + __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */ + uint32_t RESERVED1[2]; + __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */ + __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */ + uint32_t RESERVED2[2]; + __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */ + __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */ + __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */ + __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */ + __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */ + __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */ + uint32_t RESERVED3[10]; + __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */ + __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */ + __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */ + __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */ + __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */ + __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */ + uint32_t RESERVED4[2]; + __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */ + __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */ + __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */ + __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */ + __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */ + __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */ + uint32_t RESERVED5[2]; + __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */ + __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */ + __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */ + __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */ + __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */ + __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */ + __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */ + __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */ + __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */ + __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */ + uint32_t RESERVED6[2]; + __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */ + __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */ + __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */ + uint32_t RESERVED7[1]; + __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */ + __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */ + __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined ( __CC_ARM ) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +#define LLCC_CONT_BASE (0xA0000000UL) +#define LLCC_CTRL_BASE (LLCC_CONT_BASE) +#define LLCC_RXD_BASE (LLCC_CONT_BASE+0x2000) +#define LLCC_TXD_BASE (LLCC_CONT_BASE+0x3000) + +#define DMAC_CONT_BASE (0xA0001000UL) +#define DMAC_DMARH_BASE (DMAC_CONT_BASE+0x00) +#define DMAC_DMARL_BASE (DMAC_CONT_BASE+0x40) +#define DMAC_DMAWH_BASE (DMAC_CONT_BASE+0x80) +#define DMAC_DMAWL_BASE (DMAC_CONT_BASE+0xC0) +#define DMAC_HCIR_BASE DMAC_DMARL_BASE +#define DMAC_HCIW_BASE DMAC_DMAWL_BASE +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + +#define LLCC_CTL ((LLCC_CTL_TypeDef *) LLCC_CTRL_BASE) +#define LLCC_RXD ((LLCC_RXD_TypeDef *) LLCC_RXD_BASE) +#define LLCC_TXD ((LLCC_TXD_TypeDef *) LLCC_TXD_BASE) +#define DMAC_DMARH ((DMAC_CHAN_TypeDef *) DMAC_DMARH_BASE) +#define DMAC_DMARL ((DMAC_CHAN_TypeDef *) DMAC_DMARL_BASE) +#define DMAC_DMAWH ((DMAC_CHAN_TypeDef *) DMAC_DMAWH_BASE) +#define DMAC_DMAWL ((DMAC_CHAN_TypeDef *) DMAC_DMAWL_BASE) +#define DMAC_HCIR DMAC_DMAWL +#define DMAC_HCIW DMAC_DMARL + +/********************************************************************* +* GPIO 2 / 3 BIT FEILD POS, OUTPUTS +*************************************************************************/ +/* GPIO 2 */ +#define CORDIO_LLCCTRL_RESETX_BIT (1<<0) +#define CORDIO_LLCCTRL_SYSTEM_RESET_BIT (1<<1) +#define CORDIO_LLCCTRL_LLC_RESET_BIT (1<<2) +#define CORDIO_LLCCTRL_WAKE_REQ_BIT (1<<3) +#define CORDIO_LLCCTRL_SLEEP_REQ_BIT (1<<4) +#define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT (1<<5) +#define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT (1<<6) +#define CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT (1<<7) + +/* GPIO 3 */ +#define CORDIO_LLCCTRL_VMEM_ON_BIT ((1<<10) | (1 << 11)) + +/********************************************************************* +* GPIO 2 / 3 BIT FEILD POS, INPUTS +*************************************************************************/ + +#define CORDIO_LLCCTRL_RESET_SYNDROME_MSK (3<<0) + +#define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT (1<<2) +#define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT (1<<3) + +#define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT (1<<4) +#define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT (1<<5) +#define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT (1<<6) +#define CORDIO_LLCCTRL_STATUS_AWAKE_BIT (1<<7) + +/**************************************************************/ +// RESET LOW +#define CORDIO_LLCCTRL_RESETX_ASSERT() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_RESETX_BIT) +#define CORDIO_LLCCTRL_RESETX_NEGATE() (CMSDK_GPIO2->DATAOUT |= CORDIO_LLCCTRL_RESETX_BIT) +// RESET HIGH +#define CORDIO_LLCCTRL_SYSTEM_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SYSTEM_RESET_BIT) +#define CORDIO_LLCCTRL_SYSTEM_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SYSTEM_RESET_BIT) + +// RESET HIGH +#define CORDIO_LLCCTRL_LLC_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_LLC_RESET_BIT) +#define CORDIO_LLCCTRL_LLC_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_LLC_RESET_BIT) + +// ACTIVE HIGH +#define CORDIO_LLCCTRL_WAKE_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_WAKE_REQ_BIT) +#define CORDIO_LLCCTRL_WAKE_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_WAKE_REQ_BIT) + +// ACTIVE HIGH +#define CORDIO_LLCCTRL_SLEEP_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SLEEP_REQ_BIT) +#define CORDIO_LLCCTRL_SLEEP_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SLEEP_REQ_BIT) + +// ACTIVE HIGH +#define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT) +#define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT) +// ACTIVE HIGH +#define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT) +#define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT) + +// ACTIVE HIGH +#define CORDIO_LLCCTRL_32M_XTAL_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT) +#define CORDIO_LLCCTRL_32M_XTAL_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT) +// ASSERTS HIGH +#define CORDIO_LLCCTRL_VMEM_ON_ASSERT() (CMSDK_GPIO3->DATAOUT |=CORDIO_LLCCTRL_VMEM_ON_BIT) +#define CORDIO_LLCCTRL_VMEM_ON_NEGATE() (CMSDK_GPIO3->DATAOUT &=~CORDIO_LLCCTRL_VMEM_ON_BIT) + + +/************ READ STATUS ********************/ + +// ACTIVE HIGH, BIT INDEPANDENT +#define CORDIO_LLCCTRL_RESET_SYNDROME_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_RESET_SYNDROME_MSK) +// ACTIVE HIGH +#define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT) +// ACTIVE HIGH +#define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT) +// ACTIVE HIGH +#define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT) +// ACTIVE HIGH +#define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT) +// ACTIVE HIGH +#define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT) +// ACTIVE HIGH +#define CORDIO_LLCCTRL_STATUS_AWAKE_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_AWAKE_BIT) + + +/* ---- DEBUG MASK & VALUE BITs used for diagnosis ---- */ +#define INSTALL_DEBUG__GPIO_TOGGLES + +#ifdef INSTALL_DEBUG__GPIO_TOGGLES + +#define GPIO_TOGGLES_MSK (0xFC) + +#define BIT_0 (1<<0) +#define BIT_1 (1<<1) +#define BIT_2 (1<<2) +#define BIT_3 (1<<3) +#define BIT_4 (1<<4) +#define BIT_5 (1<<5) +#define BIT_6 (1<<6) +#define BIT_7 (1<<7) + +#define BIT_SET(B) (CMSDK_GPIO0->DATAOUT |= ((B) & (GPIO_TOGGLES_MSK))) + +#define BIT_CLR(B) (CMSDK_GPIO0->DATAOUT &= ~((B) & (GPIO_TOGGLES_MSK))) + +/* BIT TOGGLE, XOR */ +#define BIT_TGL(B) (CMSDK_GPIO0->DATAOUT ^= ((B) & (GPIO_TOGGLES_MSK))) + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_BEETLE_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/BEETLE.sct b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/BEETLE.sct new file mode 100644 index 00000000000..fb8115f4f42 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/BEETLE.sct @@ -0,0 +1,35 @@ +;/* +; * BEETLE CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00040000 { ; load region size_region + ER_IROM1 0x00000000 0x00040000 { ; load address = execution address + *.o (RESET, +FIRST) + *(InRoot$$Sections) + .ANY (+RO) + } + ; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM + RW_IRAM1 (0x20000000+0x140) (0x20000-0x140) { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/startup_BEETLE.s b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/startup_BEETLE.s new file mode 100644 index 00000000000..fa8d2437bc6 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_ARM_STD/startup_BEETLE.s @@ -0,0 +1,316 @@ +;/* +; * BEETLE CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +; +; This file is derivative of CMSIS V5.00 startup_ARMCM3.s +; +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_Handler ; UART 0 RX and TX Handler + DCD Spare_IRQ_Handler ; Undefined + DCD UART1_Handler ; UART 1 RX and TX Handler + DCD I2C0_Handler ; I2C 0 Handler + DCD I2C1_Handler ; I2C 1 Handler + DCD RTC_Handler ; RTC Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI0_Handler ; SPI 0 Handler + DCD UARTOVF_Handler ; UART 0,1 Overflow Handler + DCD SPI1_Handler ; SPI 1 Handler + DCD QSPI_Handler ; QSPI Handler + DCD DMA_Handler ; DMA handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD SysError_Handler ; System Error (Flash Cache) + DCD EFLASH_Handler ; Embedded Flash + DCD LLCC_TXCMD_EMPTY_Handler ; LLCC_TXCMDIRQ + DCD LLCC_TXEVT_EMPTY_Handler ; LLCC_TXEVTIRQ + DCD LLCC_TXDMAH_DONE_Handler ; LLCC_TXDMA0IRQ + DCD LLCC_TXDMAL_DONE_Handler ; LLCC_TXDMA1IRQ + DCD LLCC_RXCMD_VALID_Handler ; LLCC_RXCMDIRQ + DCD LLCC_RXEVT_VALID_Handler ; LLCC_RXEVTIRQ + DCD LLCC_RXDMAH_DONE_Handler ; LLCC_RXDMA0IRQ + DCD LLCC_RXDMAL_DONE_Handler ; LLCC_RXDMA1IRQ + DCD PORT2_COMB_Handler ; GPIO 2 + DCD PORT3_COMB_Handler ; GPIO 3 + DCD TRNG_Handler ; TRNG +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UART0_Handler [WEAK] + EXPORT Spare_IRQ_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI0_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT SPI1_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + EXPORT SysError_Handler [WEAK] + EXPORT EFLASH_Handler [WEAK] + EXPORT LLCC_TXEVT_EMPTY_Handler [WEAK] + EXPORT LLCC_TXCMD_EMPTY_Handler [WEAK] + EXPORT LLCC_RXEVT_VALID_Handler [WEAK] + EXPORT LLCC_RXCMD_VALID_Handler [WEAK] + EXPORT LLCC_TXDMAL_DONE_Handler [WEAK] + EXPORT LLCC_RXDMAL_DONE_Handler [WEAK] + EXPORT LLCC_TXDMAH_DONE_Handler [WEAK] + EXPORT LLCC_RXDMAH_DONE_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + +UART0_Handler +Spare_IRQ_Handler +UART1_Handler +I2C0_Handler +I2C1_Handler +RTC_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI0_Handler +UARTOVF_Handler +SPI1_Handler +QSPI_Handler +DMA_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler +SysError_Handler +EFLASH_Handler +LLCC_TXEVT_EMPTY_Handler +LLCC_TXCMD_EMPTY_Handler +LLCC_RXEVT_VALID_Handler +LLCC_RXCMD_VALID_Handler +LLCC_TXDMAL_DONE_Handler +LLCC_RXDMAL_DONE_Handler +LLCC_TXDMAH_DONE_Handler +LLCC_RXDMAH_DONE_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +TRNG_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/BEETLE.ld b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/BEETLE.ld new file mode 100644 index 00000000000..e3188ed10a5 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/BEETLE.ld @@ -0,0 +1,181 @@ +/* + * BEETLE CMSIS Library + */ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 gcc_arm.ld + */ +/* Linker script for mbed BEETLE SoC */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 + RAM (rwx) : ORIGIN = 0x20000140, LENGTH = 0x00020000 - 0x00000140 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + *(.text.Reset_Handler) + *(.text.System_Init) + . = ALIGN(4); + } > VECTORS + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + bss_size = __bss_end__ - __bss_start__; + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + +} /* End of sections */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/startup_BEETLE.S b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/startup_BEETLE.S new file mode 100644 index 00000000000..03a3d70edda --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/TOOLCHAIN_GCC_ARM/startup_BEETLE.S @@ -0,0 +1,273 @@ +/* + * BEETLE CMSIS Library + */ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 startup_ARMCM3.S + */ + .syntax unified + .arch armv7-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vector_table,"a",%progbits + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long UART0_Handler /* 0:UART 0 RX and TX Combined Interrupt */ + .long Spare_Handler /* 1:Undefined */ + .long UART1_Handler /* 2:UART 1 RX and TX Combined Interrupt */ + .long I2C0_Handler /* 3:I2C 0 Interrupt */ + .long I2C1_Handler /* 4:I2C 1 Interrupt */ + .long RTC_Handler /* 5:RTC Interrupt */ + .long PORT0_Handler /* 6:GPIO Port 0 combined Interrupt */ + .long PORT1_ALL_Handler /* 7:GPIO Port 1 combined Interrupt */ + .long TIMER0_Handler /* 8:TIMER 0 Interrupt */ + .long TIMER1_Handler /* 9:TIMER 1 Interrupt */ + .long DUALTIMER_Handler /* 10:Dual Timer Interrupt */ + .long SPI0_Handler /* 11:SPI 0 Interrupt */ + .long UARTOVF_Handler /* 12:UART 0,1,2 Overflow Interrupt */ + .long SPI1_Handler /* 13:SPI 1 Interrupt */ + .long QSPI_Handler /* 14:QUAD SPI Interrupt */ + .long DMA_Handler /* 15:Touch Screen Interrupt */ + .long PORT0_0_Handler /* 16:All P0 and P1I/O pins used as irq source */ + .long PORT0_1_Handler /* 17:There are 16 pins in total */ + .long PORT0_2_Handler /* 18: */ + .long PORT0_3_Handler /* 19: */ + .long PORT0_4_Handler /* 20: */ + .long PORT0_5_Handler /* 21: */ + .long PORT0_6_Handler /* 22: */ + .long PORT0_7_Handler /* 23: */ + .long PORT0_8_Handler /* 24: */ + .long PORT0_9_Handler /* 25: */ + .long PORT0_10_Handler /* 26: */ + .long PORT0_11_Handler /* 27: */ + .long PORT0_12_Handler /* 28: */ + .long PORT0_13_Handler /* 29: */ + .long PORT0_14_Handler /* 30: */ + .long PORT0_15_Handler /* 31: */ + .long SysError_Handler /* 32: System Error (Flash Cache) */ + .long EFLASH_Handler /* 33: Embedded Flash */ + .long LLCC_TXCMD_EMPTY_Handler /* 34: LLCC_TXCMDIRQ */ + .long LLCC_TXEVT_EMPTY_Handler /* 35: LLCC_TXEVTIRQ */ + .long LLCC_TXDMAH_DONE_Handler /* 36: LLCC_TXDMA0IRQ */ + .long LLCC_TXDMAL_DONE_Handler /* 37: LLCC_TXDMA1IRQ */ + .long LLCC_RXCMD_VALID_Handler /* 38: LLCC_RXCMDIRQ */ + .long LLCC_RXEVT_VALID_Handler /* 39: LLCC_RXEVTIRQ */ + .long LLCC_RXDMAH_DONE_Handler /* 40: LLCC_RXDMA0IRQ */ + .long LLCC_RXDMAL_DONE_Handler /* 41: LLCC_RXDMA1IRQ */ + .long PORT2_COMB_Handler /* 42: GPIO 2 */ + .long PORT3_COMB_Handler /* 43: GPIO 3 */ + .long TRNG_Handler /* 44: TRNG */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* + * Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. + */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + +/* Initialize .bss */ +init_bss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + ldr r3, =bss_size + + cmp r3, #0 + beq system_startup + + mov r4, #0 +zero: + strb r4, [r1], #1 + subs r3, r3, #1 + bne zero + +system_startup: + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* + * Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers + */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + /* External interrupts */ + def_irq_default_handler UART0_Handler /* 0:UART 0 RX and TX Combined Interrupt */ + def_irq_default_handler Spare_Handler /* 1:Undefined */ + def_irq_default_handler UART1_Handler /* 2:UART 1 RX and TX Combined Interrupt */ + def_irq_default_handler I2C0_Handler /* 3:I2C 0 Interrupt */ + def_irq_default_handler I2C1_Handler /* 4:I2C 1 Interrupt */ + def_irq_default_handler RTC_Handler /* 5:RTC Interrupt */ + def_irq_default_handler PORT0_Handler /* 6:GPIO Port 0 combined Interrupt */ + def_irq_default_handler PORT1_ALL_Handler /* 7:GPIO Port 1 combined Interrupt */ + def_irq_default_handler TIMER0_Handler /* 8:TIMER 0 Interrupt */ + def_irq_default_handler TIMER1_Handler /* 9:TIMER 1 Interrupt */ + def_irq_default_handler DUALTIMER_Handler /* 10:Dual Timer Interrupt */ + def_irq_default_handler SPI0_Handler /* 11:SPI 0 Interrupt */ + def_irq_default_handler UARTOVF_Handler /* 12:UART 0,1,2 Overflow Interrupt */ + def_irq_default_handler SPI1_Handler /* 13:SPI 1 Interrupt */ + def_irq_default_handler QSPI_Handler /* 14:QUAD SPI Interrupt */ + def_irq_default_handler DMA_Handler /* 15:Touch Screen Interrupt */ + def_irq_default_handler PORT0_0_Handler /* 16:All P0 and P1I/O pins used as irq source */ + def_irq_default_handler PORT0_1_Handler /* 17:There are 16 pins in total */ + def_irq_default_handler PORT0_2_Handler /* 18: */ + def_irq_default_handler PORT0_3_Handler /* 19: */ + def_irq_default_handler PORT0_4_Handler /* 20: */ + def_irq_default_handler PORT0_5_Handler /* 21: */ + def_irq_default_handler PORT0_6_Handler /* 22: */ + def_irq_default_handler PORT0_7_Handler /* 23: */ + def_irq_default_handler PORT0_8_Handler /* 24: */ + def_irq_default_handler PORT0_9_Handler /* 25: */ + def_irq_default_handler PORT0_10_Handler /* 26: */ + def_irq_default_handler PORT0_11_Handler /* 27: */ + def_irq_default_handler PORT0_12_Handler /* 28: */ + def_irq_default_handler PORT0_13_Handler /* 29: */ + def_irq_default_handler PORT0_14_Handler /* 30: */ + def_irq_default_handler PORT0_15_Handler /* 31: */ + def_irq_default_handler SysError_Handler /* 32: System Error (Flash Cache) */ + def_irq_default_handler EFLASH_Handler /* 33: Embedded Flash */ + def_irq_default_handler LLCC_TXCMD_EMPTY_Handler /* 34: LLCC_TXCMDIRQ */ + def_irq_default_handler LLCC_TXEVT_EMPTY_Handler /* 35: LLCC_TXEVTIRQ */ + def_irq_default_handler LLCC_TXDMAH_DONE_Handler /* 36: LLCC_TXDMA0IRQ */ + def_irq_default_handler LLCC_TXDMAL_DONE_Handler /* 37: LLCC_TXDMA1IRQ */ + def_irq_default_handler LLCC_RXCMD_VALID_Handler /* 38: LLCC_RXCMDIRQ */ + def_irq_default_handler LLCC_RXEVT_VALID_Handler /* 39: LLCC_RXEVTIRQ */ + def_irq_default_handler LLCC_RXDMAH_DONE_Handler /* 40: LLCC_RXDMA0IRQ */ + def_irq_default_handler LLCC_RXDMAL_DONE_Handler /* 41: LLCC_RXDMA1IRQ */ + def_irq_default_handler PORT2_COMB_Handler /* 42: GPIO 2 */ + def_irq_default_handler PORT3_COMB_Handler /* 43: GPIO 3 */ + def_irq_default_handler TRNG_Handler /* 44: TRNG */ + + .end diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.c new file mode 100644 index 00000000000..ea6ec17dbc7 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.c @@ -0,0 +1,360 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis.h" +#include "apb_dualtimer.h" + +/* DualTimer Private Data */ +typedef struct { + /* DualTimer 1 Definition */ + CMSDK_DUALTIMER_SINGLE_TypeDef *dualtimer1; + /* DualTimer 2 Definition */ + CMSDK_DUALTIMER_SINGLE_TypeDef *dualtimer2; + /* Dual Timer IRQn */ + uint32_t dualtimerIRQn; + /* DualTimer 1 Reload Value */ + uint32_t dualtimer1Reload; + /* DualTimer 2 Reload Value */ + uint32_t dualtimer2Reload; + /* Timer state */ + uint32_t state; +} apb_dualtimer_t; + +/* Timer state definitions */ +#define DUALTIMER_INITIALIZED (1) +#define DUALTIMER_ENABLED (1 << 1) + +/* + * This Timer is written for MBED OS and keeps count + * of the ticks. All the elaboration logic is demanded + * to the upper layers. + */ +#define DUALTIMER_MAX_VALUE 0xFFFFFFFF +#define DUALTIMER_TICKS_US (SystemCoreClock/1000000) + +/* Dual Timers Array */ +static apb_dualtimer_t DualTimers[NUM_DUALTIMERS]; + +/* + * DualTimer_Initialize(): Initializes a hardware timer + * timer: timer to be Initialized + * time_us: timer reload value in us - 0 to reload to timer max value + * time_us = ticks_value / TIMER_TICK_US + */ +void DualTimer_Initialize(uint32_t timer, uint32_t time_us) +{ + uint32_t reload = 0; + + if (timer < NUM_DUALTIMERS) + { + if (time_us == 0) + reload = DUALTIMER_MAX_VALUE; + else + reload = (time_us) * DUALTIMER_TICKS_US; + + switch(timer) { + case 0: DualTimers[timer].dualtimer1 = CMSDK_DUALTIMER1; + DualTimers[timer].dualtimer2 = CMSDK_DUALTIMER2; + DualTimers[timer].dualtimerIRQn = DUALTIMER_IRQn; + DualTimers[timer].dualtimer1Reload = reload; + DualTimers[timer].dualtimer2Reload = reload; + DualTimers[timer].state = DUALTIMER_INITIALIZED; + default: break; + } + } +} + +/* + * DualTimer_ReturnMode(): returns the correct mode for Dual Timer Control + * mode: mode set by user + * @return: mode for TimeControl register + */ +uint32_t DualTimer_ReturnMode(timerenable_t mode) +{ + uint32_t return_mode = 0; + /* Check Interrupt Enable */ + if (((mode & DUALTIMER_INT) >> DUALTIMER_INT_MASK) == 1) + return_mode |= CMSDK_DUALTIMER_CTRL_INTEN_Msk; + /* Check 32 bit Counter */ + if (((mode & DUALTIMER_COUNT_32) >> DUALTIMER_COUNT_32_MASK) == 1) + return_mode |= CMSDK_DUALTIMER_CTRL_SIZE_Msk; + /* Check Periodic Mode */ + if (((mode & DUALTIMER_PERIODIC) >> DUALTIMER_PERIODIC_MASK) == 1) + return_mode |= CMSDK_DUALTIMER_CTRL_MODE_Msk; + /* Check OneShot Mode */ + if (((mode & DUALTIMER_ONESHOT) >> DUALTIMER_ONESHOT_MASK) == 1) + return_mode |= CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk; + + return return_mode; +} + +/* + * DualTimer_Enable(): Enables a hardware timer + * timer: timer to be enabled + * mode: enable mode + */ +void DualTimer_Enable(uint32_t timer, timerenable_t mode) +{ + uint32_t dualtimerControl = 0; + /* The timer has to be contained in a valid range */ + if (timer < NUM_DUALTIMERS) { + /* Timer has to be already initialized */ + if (DualTimers[timer].state == DUALTIMER_INITIALIZED) { + /* Disable Timer */ + (DualTimers[timer].dualtimer1)->TimerControl = 0x0; + (DualTimers[timer].dualtimer2)->TimerControl = 0x0; + /* Reload Value */ + (DualTimers[timer].dualtimer1)->TimerLoad = + DualTimers[timer].dualtimer1Reload; + (DualTimers[timer].dualtimer2)->TimerLoad = + DualTimers[timer].dualtimer2Reload; + /* Set up Dual Timer Control */ + dualtimerControl = DualTimer_ReturnMode(mode); + (DualTimers[timer].dualtimer1)->TimerControl = dualtimerControl; + (DualTimers[timer].dualtimer2)->TimerControl = dualtimerControl; + /* Enable Counter */ + (DualTimers[timer].dualtimer1)->TimerControl |= + CMSDK_DUALTIMER_CTRL_EN_Msk; + (DualTimers[timer].dualtimer2)->TimerControl |= + CMSDK_DUALTIMER_CTRL_EN_Msk; + /* Change timer state */ + DualTimers[timer].state |= DUALTIMER_ENABLED; + } + } +} + +/* + * DualTimer_Disable(): Disables a hardware timer + * timer: timer to be disabled + * dis_timer: 0 both - 1 dual timer 1 - 2 dual timer 2 + */ +void DualTimer_Disable(uint32_t timer, uint32_t dis_timer) +{ + /* The timer has to be contained in a valid range */ + if (timer < NUM_DUALTIMERS) { + /* Timer has to be already initialized and enabled */ + if (DualTimers[timer].state == (DUALTIMER_INITIALIZED | DUALTIMER_ENABLED)) { + /* Disable Timer */ + switch (dis_timer) + { + case 0: (DualTimers[timer].dualtimer1)->TimerControl = 0x0; + (DualTimers[timer].dualtimer2)->TimerControl = 0x0; + break; + case 1: (DualTimers[timer].dualtimer1)->TimerControl = 0x0; + break; + case 2: (DualTimers[timer].dualtimer2)->TimerControl = 0x0; + break; + default: break; + } + /* Change timer state */ + DualTimers[timer].state = DUALTIMER_INITIALIZED; + } + } +} + +/* + * DualTimer_isEnabled(): verifies if a timer is enabled + * timer: timer to be verified + * @return: 0 disabled - 1 enabled + */ +uint32_t DualTimer_isEnabled(uint32_t timer) +{ + /* The timer has to be contained in a valid range */ + if (timer < NUM_DUALTIMERS) { + /* Timer has to be already initialized and enabled */ + if (DualTimers[timer].state == (DUALTIMER_INITIALIZED | DUALTIMER_ENABLED)) + return 1; + } else { + return 0; + } + return 0; +} + +/* + * DualTimer_Read_1(): provides single timer 1 VALUE + * timer: timer to be read + * @return: timer VALUE + */ +uint32_t DualTimer_Read_1(uint32_t timer) +{ + uint32_t return_value = 0; + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + return_value = (DualTimers[timer].dualtimer1Reload + - (DualTimers[timer].dualtimer1)->TimerValue) + / DUALTIMER_TICKS_US; + } + + return return_value; +} + +/* + * DualTimer_Read_2(): provides single timer 2 VALUE + * timer: timer to be read + * @return: timer VALUE + */ +uint32_t DualTimer_Read_2(uint32_t timer) +{ + uint32_t return_value = 0; + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + return_value = (DualTimers[timer].dualtimer2Reload + - (DualTimers[timer].dualtimer2)->TimerValue) + / DUALTIMER_TICKS_US; + } + + return return_value; +} + +/* + * DualTimer_SetInterrupt_1(): sets timer 1 Interrupt + * timer: timer on which interrupt is set + * time_us: reloading value us + * mode: enable mode + */ +void DualTimer_SetInterrupt_1(uint32_t timer, uint32_t time_us, + timerenable_t mode) +{ + uint32_t dualtimerControl = 0; + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + /* Disable Timer */ + DualTimer_Disable(timer, SINGLETIMER1); + /* Set up Dual Timer Control */ + dualtimerControl = DualTimer_ReturnMode(mode); + (DualTimers[timer].dualtimer1)->TimerControl = + CMSDK_DUALTIMER_CTRL_INTEN_Msk + | dualtimerControl; + /* Reload Value */ + DualTimers[timer].dualtimer1Reload = (time_us) + * DUALTIMER_TICKS_US; + (DualTimers[timer].dualtimer1)->TimerLoad = + DualTimers[timer].dualtimer1Reload; + /* Enable Counter */ + (DualTimers[timer].dualtimer1)->TimerControl |= + CMSDK_DUALTIMER_CTRL_EN_Msk; + /* Change timer state */ + DualTimers[timer].state |= DUALTIMER_ENABLED; + } +} + +/* + * DualTimer_SetInterrupt_2(): sets timer 2 Interrupt + * timer: timer on which interrupt is set + * time_us: reloading value us + * mode: enable mode + */ +void DualTimer_SetInterrupt_2(uint32_t timer, uint32_t time_us, + timerenable_t mode) +{ + uint32_t dualtimerControl = 0; + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + /* Disable Timer */ + DualTimer_Disable(timer, SINGLETIMER2); + /* Set up Dual Timer Control */ + dualtimerControl = DualTimer_ReturnMode(mode); + (DualTimers[timer].dualtimer2)->TimerControl = + CMSDK_DUALTIMER_CTRL_INTEN_Msk + | dualtimerControl; + /* Reload Value */ + DualTimers[timer].dualtimer2Reload = (time_us) + * DUALTIMER_TICKS_US; + (DualTimers[timer].dualtimer2)->TimerLoad = + DualTimers[timer].dualtimer2Reload; + /* Enable Counter */ + (DualTimers[timer].dualtimer2)->TimerControl |= + CMSDK_DUALTIMER_CTRL_EN_Msk; + /* Change timer state */ + DualTimers[timer].state |= DUALTIMER_ENABLED; + } +} + +/* + * DualTimer_DisableInterrupt(): disables timer interrupt + * timer: timer on which interrupt is disabled + */ +void DualTimer_DisableInterrupt(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + /* Disable Interrupt */ + (DualTimers[timer].dualtimer1)->TimerControl &= + CMSDK_DUALTIMER_CTRL_EN_Msk; + (DualTimers[timer].dualtimer2)->TimerControl &= + CMSDK_DUALTIMER_CTRL_EN_Msk; + } +} + +/* + * DualTimer_ClearInterrupt(): clear timer interrupt + * timer: timer on which interrupt needs to be cleared + */ +void DualTimer_ClearInterrupt(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + /* Clear Interrupt */ + (DualTimers[timer].dualtimer1)->TimerIntClr = + CMSDK_DUALTIMER_INTCLR_Msk; + (DualTimers[timer].dualtimer2)->TimerIntClr = + CMSDK_DUALTIMER_INTCLR_Msk; + } +} + +/* + * DualTimer_GetIRQn(): returns IRQn of a DualTimer + * timer: timer on which IRQn is defined - 0 if it is not defined + */ +uint32_t DualTimer_GetIRQn(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + return DualTimers[timer].dualtimerIRQn; + } + return 0; +} + +/* + * DualTimer_GetIRQInfo(): provides the single timer who caused + * the interrupt. + * dualtimer: dualtimer that triggered the IRQ + * @return: a single timer - 0 if it is not defined + */ +uint32_t DualTimer_GetIRQInfo(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + if((DualTimers[timer].dualtimer1)->TimerRIS) + return SINGLETIMER1; + else + return SINGLETIMER2; + } + return 0; +} + +/* + * DualTimer_GetTicksUS(): returns the Ticks per us + * timer: timer associated with the Ticks per us + * @return: Ticks per us - 0 if the timer is disables + */ +uint32_t DualTimer_GetTicksUS(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (DualTimer_isEnabled(timer) == 1) { + return DUALTIMER_TICKS_US; + } + return 0; +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.h new file mode 100644 index 00000000000..85c4f026855 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_dualtimer.h @@ -0,0 +1,142 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _APB_DUAL_TIMER_DRV_H +#define _APB_DUAL_TIMER_DRV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Supported Number of Dual Timers */ +#define NUM_DUALTIMERS 1 +#define DUALTIMER0 0 +#define SINGLETIMER1 1 +#define SINGLETIMER2 2 + +/* + * DualTimer_Initialize(): Initializes a hardware timer + * timer: timer to be Initialized + * time_us: timer reload value in us - 0 to reload to timer max value + * time_us = tick_value / TIMER_TICK_US + */ +void DualTimer_Initialize(uint32_t timer, uint32_t time_us); + +/* Enable Mode */ +typedef uint8_t timerenable_t; +/* Interrupt */ +#define DUALTIMER_INT_MASK (0) +#define DUALTIMER_INT (1 << DUALTIMER_INT_MASK) +/* 32 bit Counter */ +#define DUALTIMER_COUNT_32_MASK (1) +#define DUALTIMER_COUNT_32 (1 << DUALTIMER_COUNT_32_MASK) +/* Periodic mode */ +#define DUALTIMER_PERIODIC_MASK (2) +#define DUALTIMER_PERIODIC (1 << DUALTIMER_PERIODIC_MASK) +/* OneShot mode */ +#define DUALTIMER_ONESHOT_MASK (3) +#define DUALTIMER_ONESHOT (1 << DUALTIMER_ONESHOT_MASK) + +/* + * DualTimer_Enable(): Enables a hardware timer + * timer: timer to be enabled + * mode: enable mode + */ +void DualTimer_Enable(uint32_t timer, timerenable_t mode); + +/* + * DualTimer_Disable(): Disables a hardware timer + * timer: timer to be disabled + * dis_timer: 0 both - 1 dual timer 1 - 2 dual timer 2 + */ +void DualTimer_Disable(uint32_t timer, uint32_t dis_timer); + +/* + * DualTimer_isEnabled(): verifies if a timer is enabled + * timer: timer to be verified + * @return: 0 disabled - 1 enabled + */ +uint32_t DualTimer_isEnabled(uint32_t timer); + +/* + * DualTimer_Read_1(): provides single timer 1 VALUE + * timer: timer to be read + * @return: timer VALUE us + */ +uint32_t DualTimer_Read_1(uint32_t timer); + +/* + * DualTimer_Read_2(): provides single timer 2 VALUE + * timer: timer to be read + * @return: timer VALUE us + */ +uint32_t DualTimer_Read_2(uint32_t timer); + +/* + * DualTimer_SetInterrupt_1(): sets timer 1 Interrupt + * timer: timer on which interrupt is set + * time_us: reloading value us + * mode: enable mode + */ +void DualTimer_SetInterrupt_1(uint32_t timer, uint32_t time_us, + timerenable_t mode); + +/* + * DualTimer_SetInterrupt_2(): sets timer 2 Interrupt + * timer: timer on which interrupt is set + * time_us: reloading value us + * mode: enable mode + */ +void DualTimer_SetInterrupt_2(uint32_t timer, uint32_t time_us, + timerenable_t mode); + +/* + * DualTimer_DisableInterrupt(): disables timer interrupt + * timer: timer on which interrupt is disabled + */ +void DualTimer_DisableInterrupt(uint32_t timer); + +/* + * DualTimer_ClearInterrupt(): clear timer interrupt + * timer: timer on which interrupt needs to be cleared + */ +void DualTimer_ClearInterrupt(uint32_t timer); + +/* + * DualTimer_GetIRQn(): returns IRQn of a DualTimer + * timer: timer on which IRQn is defined - 0 if it is not defined + */ +uint32_t DualTimer_GetIRQn(uint32_t timer); + +/* + * DualTimer_GetIRQInfo(): provides the single timer who caused + * the interrupt. + * timer: dualtimer that triggered the IRQ + * @return: a single timer + */ +uint32_t DualTimer_GetIRQInfo(uint32_t dualtimer); + +/* + * DualTimer_GetTicksUS(): returns the Ticks per us + * timer: timer associated with the Ticks per us + * @return: Ticks per us - 0 if the timer is disables + */ +uint32_t DualTimer_GetTicksUS(uint32_t timer); + +#ifdef __cplusplus +} +#endif +#endif /* _APB_DUAL_TIMER_DRV_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.c new file mode 100644 index 00000000000..1b0a56bbcc7 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.c @@ -0,0 +1,236 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis.h" +#include "apb_timer.h" + +/* Timer Private Data */ +typedef struct { + /* Timer Definition */ + CMSDK_TIMER_TypeDef *timerN; + /* Timer IRQn */ + uint32_t timerIRQn; + /* Timer Reload Value */ + uint32_t timerReload; + /* Timer state */ + uint32_t state; +} apb_timer_t; + +/* Timer state definitions */ +#define TIMER_INITIALIZED (1) +#define TIMER_ENABLED (1 << 1) + +/* + * This Timer is written for MBED OS and keeps count + * of the ticks. All the elaboration logic is demanded + * to the upper layers. + */ +#define TIMER_MAX_VALUE 0xFFFFFFFF +#define TIMER_TICKS_US (SystemCoreClock/1000000) + +/* Timers Array */ +static apb_timer_t Timers[NUM_TIMERS]; + +void Timer_Index_Init(uint32_t timer, uint32_t reload, + CMSDK_TIMER_TypeDef *TimerN, uint32_t IRQn) +{ + Timers[timer].timerN = TimerN; + Timers[timer].timerIRQn = IRQn; + Timers[timer].timerReload = reload; + Timers[timer].state = TIMER_INITIALIZED; +} + +/* + * Timer_Initialize(): Initializes an hardware timer + * timer: timer to be Initialized + * time_us: timer reload value in us - 0 to reload to timer max value + * time_us = tick_value / TIMER_TICKS_US + */ +#define TIMER_INIT(index, reload) Timer_Index_Init(index, reload, CMSDK_TIMER##index, TIMER##index##_IRQn) +void Timer_Initialize(uint32_t timer, uint32_t time_us) +{ + uint32_t reload = 0; + + if (timer < NUM_TIMERS) + { + if (time_us == 0) + reload = TIMER_MAX_VALUE; + else + reload = (time_us) * TIMER_TICKS_US; + + switch(timer) { + case 0: TIMER_INIT(0, reload); + break; + case 1: TIMER_INIT(1, reload); + break; + default: break; + } + } +} + +/* + * Timer_Enable(): Enables a hardware timer + * timer: timer to be enabled + */ +void Timer_Enable(uint32_t timer) +{ + /* The timer has to be contained in a valid range */ + if (timer < NUM_TIMERS) { + /* Timer has to be already initialized */ + if (Timers[timer].state == TIMER_INITIALIZED) { + /* Disable Timer */ + (Timers[timer].timerN)->CTRL = 0x0; + /* Reload Value */ + (Timers[timer].timerN)->RELOAD = Timers[timer].timerReload; + /* Enable Interrupt */ + (Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk; + /* Enable Counter */ + (Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk; + /* Change timer state */ + Timers[timer].state |= TIMER_ENABLED; + } + } +} + +/* + * Timer_Disable(): Disables a hardware timer + * timer: timer to be disabled + */ +void Timer_Disable(uint32_t timer) +{ + /* The timer has to be contained in a valid range */ + if (timer < NUM_TIMERS) { + /* Timer has to be already initialized and enabled */ + if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED)) { + /* Disable Timer */ + (Timers[timer].timerN)->CTRL = 0x0; + /* Change timer state */ + Timers[timer].state = TIMER_INITIALIZED; + } + } +} + +/* + * Timer_isEnabled(): verifies if a timer is enabled + * timer: timer to be verified + * @return: 0 disabled - 1 enabled + */ +uint32_t Timer_isEnabled(uint32_t timer) +{ + /* The timer has to be contained in a valid range */ + if (timer < NUM_TIMERS) { + /* Timer has to be already initialized and enabled */ + if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED)) + return 1; + } else { + return 0; + } + return 0; +} + +/* + * Timer_Read(): provides timer VALUE + * timer: timer to be read + * @return: timer VALUE us + */ +uint32_t Timer_Read(uint32_t timer) +{ + uint32_t return_value = 0; + /* Verify if the Timer is enabled */ + if (Timer_isEnabled(timer) == 1) { + return_value = (Timers[timer].timerReload + - (Timers[timer].timerN)->VALUE) + / TIMER_TICKS_US; + } + + return return_value; +} + +/* + * Timer_SetInterrupt(): sets timer Interrupt + * timer: timer on which interrupt is set + * time_us: reloading time in us + */ +void Timer_SetInterrupt(uint32_t timer, uint32_t time_us) +{ + /* Verify if the Timer is enabled */ + if (Timer_isEnabled(timer) == 1) { + /* Disable Timer */ + Timer_Disable(timer); + /* Enable Interrupt */ + (Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk; + /* Initialize Timer Value */ + Timers[timer].timerReload = (time_us) * TIMER_TICKS_US; + (Timers[timer].timerN)->RELOAD = Timers[timer].timerReload; + (Timers[timer].timerN)->VALUE = Timers[timer].timerReload; + /* Enable Counter */ + (Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk; + /* Change timer state */ + Timers[timer].state |= TIMER_ENABLED; + } +} + +/* + * Timer_DisableInterrupt(): disables timer interrupt + * timer: timer on which interrupt is disabled + */ +void Timer_DisableInterrupt(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (Timer_isEnabled(timer) == 1) { + /* Disable Interrupt */ + (Timers[timer].timerN)->CTRL &= CMSDK_TIMER_CTRL_EN_Msk; + } +} + +/* + * Timer_ClearInterrupt(): clear timer interrupt + * timer: timer on which interrupt needs to be cleared + */ +void Timer_ClearInterrupt(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (Timer_isEnabled(timer) == 1) { + /* Clear Interrupt */ + (Timers[timer].timerN)->INTCLEAR = CMSDK_TIMER_INTCLEAR_Msk; + } +} + +/* + * Timer_GetIRQn(): returns IRQn of a Timer + * timer: timer on which IRQn is defined - 0 if it is not defined + */ +uint32_t Timer_GetIRQn(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (Timer_isEnabled(timer) == 1) { + return Timers[timer].timerIRQn; + } + return 0; +} + +/* + * Timer_GetTicksUS(): returns the number of Ticks per us + * timer: timer associated with the Ticks per us + * @return: Ticks per us - 0 if the timer is disables + */ +uint32_t Timer_GetTicksUS(uint32_t timer) +{ + /* Verify if the Timer is enabled */ + if (Timer_isEnabled(timer) == 1) { + return TIMER_TICKS_US; + } + return 0; +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.h new file mode 100644 index 00000000000..c174174e74e --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/apb_timer.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _APB_TIMER_DRV_H +#define _APB_TIMER_DRV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Supported Number of Timers */ +#define NUM_TIMERS 2 +#define TIMER0 0 +#define TIMER1 1 + +/* + * Timer_Initialize(): Initializes an hardware timer + * timer: timer to be Initialized + * time_us: timer reload value in us - 0 to reload to timer max value + * time_us = tick_value / TIMER_TICK_US + */ +void Timer_Initialize(uint32_t timer, uint32_t time_us); + +/* + * Timer_Enable(): Enables an hardware timer + * timer: timer to be enabled + */ +void Timer_Enable(uint32_t timer); + +/* + * Timer_Disable(): Disables an hardware timer + * timer: timer to be disabled + */ +void Timer_Disable(uint32_t timer); + +/* + * Timer_isEnabled(): verifies if a timer is enabled + * timer: timer to be verified + * @return: 0 disabled - 1 enabled + */ +uint32_t Timer_isEnabled(uint32_t timer); + +/* + * Timer_Read(): provides timer VALUE + * timer: timer to be read + * @return: timer VALUE + */ +uint32_t Timer_Read(uint32_t timer); + +/* + * Timer_SetInterrupt(): sets timer Interrupt + * timer: timer on which interrupt is set + * time_us: reloading time in us + */ +void Timer_SetInterrupt(uint32_t timer, uint32_t time_us); + +/* + * Timer_DisableInterrupt(): disables timer interrupt + * timer: timer on which interrupt is disabled + */ +void Timer_DisableInterrupt(uint32_t timer); + +/* + * Timer_ClearInterrupt(): clear timer interrupt + * timer: timer on which interrupt needs to be cleared + */ +void Timer_ClearInterrupt(uint32_t timer); + +/* + * Timer_GetIRQn(): returns IRQn of a Timer + * timer: timer on which IRQn is defined - 0 if it is not defined + */ +uint32_t Timer_GetIRQn(uint32_t timer); + +/* + * Timer_GetTicksUS(): returns the number of Ticks per us + * timer: timer associated with the Ticks per us + * @return: Ticks per us - 0 if the timer is disables + */ +uint32_t Timer_GetTicksUS(uint32_t timer); + +#ifdef __cplusplus +} +#endif +#endif /* _APB_TIMER_DRV_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis.h new file mode 100644 index 00000000000..df172235201 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * A generic CMSIS include header, pulling in BEETLE SoC specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +/* Beetle Core */ +#include "CMSDK_BEETLE.h" +/* Beetle System Core */ +#include "system_CMSDK_BEETLE.h" +/* Beetle Core Config */ +#include "system_core_beetle.h" +/* APB Dual Timer */ +#include "apb_dualtimer.h" +/* APB Timer */ +#include "apb_timer.h" +/* Cortex M3 SysTick Driver */ +#include "systick_timer.h" +/* Flash Cache Driver */ +#include "fcache_api.h" +/* Embedded Flash Driver */ +#include "eflash_api.h" +/* NVIC Driver */ +#include "cmsis_nvic.h" +/* System Core Version */ +#include "system_core_version.h" + +#endif diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.c new file mode 100644 index 00000000000..c409f8699b7 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.c @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * CMSIS-style functionality to support dynamic vectors + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) //Location of vectors in RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) //Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.h new file mode 100644 index 00000000000..88c7fb1fbe7 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS (16 + 48) +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c new file mode 100644 index 00000000000..748b7c7885c --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c @@ -0,0 +1,357 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "eflash_api.h" + +/* EFlash Private Data */ +typedef struct { + /* basebank0 start address */ + unsigned int basebank0; + /* basebank0 mass erase + info pages address */ + unsigned int basebank0_me; + /* basebank1 start address */ + unsigned int basebank1; + /* basebank1 mass erase + info pages address */ + unsigned int basebank1_me; +} eflash_t; + +static eflash_t eflash; + +/* EFlash_IdCheck: Detect the part number to see if device is present */ +int EFlash_IdCheck() +{ + unsigned int eflash_id; + + eflash_id = readl(SYS_EFLASH_PIDR2) & (EFLASH_DES_1 | EFLASH_JEDEC); + + if (readl(SYS_EFLASH_PIDR0) != FLS_PID0 + || readl(SYS_EFLASH_PIDR1) != FLS_PID1 + || eflash_id != FLS_PID2) + /* port ID and ARM ID does not match */ + return 1; + else + return 0; +} + +/* EFlash_ReturnBank1BaseAddress: Returns start address of bank 1 */ +int EFlash_ReturnBank1BaseAddress() +{ + unsigned int hwparams0; + int baseaddr; + + hwparams0 = readl(SYS_EFLASH_HWPARAMS0) & EFLASH_FLASHSIZE; + + switch(hwparams0) + { + case 0x11: + /* 128kb flash size - first page of bank 1 is 0x20000 */ + baseaddr = 0x20000; + break; + case 0x12: + /* 256kb flash size - first page of bank 1 is 0x40000 */ + baseaddr = 0x40000; + break; + default: + /* unsupported flash size */ + baseaddr = -1; + break; + } + + return baseaddr; +} + +/* EFlash_Initialize: eFlash Initialize function */ +void EFlash_Initialize() +{ + /* Find the start address of banks */ + eflash.basebank0 = 0x0; + eflash.basebank0_me = 0x40000000; + eflash.basebank1 = EFlash_ReturnBank1BaseAddress(); + eflash.basebank1_me = 0x80000000; + + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK); + + /* + * Configure to use external clock + * EXTCL = 31250 ns -> + * 1 ms = 32 clock count 32khz ext_clk -> ER_CLK_COUNT = 32 + * 1 us = 84 clock count system_clk -> WR_CLK_COUNT = 84 + * EXT_CLK_CONF = 0x1 [Erase] External clock used for erase counters (>1ms) + * HCLK used for write counters + * RD_CLK_COUNT = 0x3 + */ + writel(SYS_EFLASH_CONFIG0, 0x00200B43); + + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY); +} + +/* + * EFlash_Erase: Erases flash banks + * Mode: + * 0 - erases bank 0 + * 1 - erases bank 1 + * 2 - erases bank 0 + info pages + * 3 - erases bank 1 + info pages + * 4 - erases bank 0 + 1 + * 5 - erases bank 0 + 1 with info pages + */ +void EFlash_Erase(int mode) +{ + switch (mode) + { + case 0: + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #0 */ + writel(SYS_EFLASH_WADDR, eflash.basebank0); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + break; + case 1: + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #1 */ + writel(SYS_EFLASH_WADDR, eflash.basebank1); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + break; + case 2: + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #0 + info pages */ + writel(SYS_EFLASH_WADDR, eflash.basebank0_me); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + break; + case 3: + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #1 + info pages */ + writel(SYS_EFLASH_WADDR, eflash.basebank1_me); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + break; + case 4: + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #0 */ + writel(SYS_EFLASH_WADDR, eflash.basebank0); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #1 */ + writel(SYS_EFLASH_WADDR, eflash.basebank1); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller gets unlocked */ + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + break; + case 5: + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #0 + info pages */ + writel(SYS_EFLASH_WADDR, eflash.basebank0_me); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_LOCK_MASK) == EFLASH_LOCK); + /* Erase Block #1 + info pages */ + writel(SYS_EFLASH_WADDR, eflash.basebank1_me); + writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE); + /* Wait until eFlash controller is not busy */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + break; + default: + break; + } +} + +/* EFlash_ErasePage: Erase a Page */ +void EFlash_ErasePage(unsigned int waddr) +{ + /* Erase the page starting a waddr */ + writel(SYS_EFLASH_WADDR, waddr); + writel(SYS_EFLASH_CTRL, EFLASH_ERASE); + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); +} + +/* + * EFlash_Write: Write function + * Parameters: + * waddr - address in flash + * data - data to be written + */ +void EFlash_Write(unsigned int waddr, unsigned int data) +{ + /* Set Write Data Register */ + writel(SYS_EFLASH_WDATA, data); + /* Set Write Address Register */ + writel(SYS_EFLASH_WADDR, waddr); + /* Start Write Operation through CTRL register */ + writel(SYS_EFLASH_CTRL, EFLASH_WRITE); + /* Wait until eFlash controller gets unlocked */ + while ((readl(SYS_EFLASH_STATUS) + & EFLASH_BUSY_MASK) == EFLASH_BUSY); + + /* Flash Cache invalidate if FCache enabled */ + if (FCache_isEnabled() == 1) + FCache_Invalidate(); +} + +/* + * EFlash_WritePage: Write Page function + * Parameters: + * waddr - address in flash + * page_size - data to be written + * buf - buffer containing the data + */ +int EFlash_WritePage(unsigned int waddr, unsigned int page_size, + unsigned char *buf) +{ + unsigned int page_index; + unsigned int data; + + /* To be verified */ + for(page_index = 0; page_index < page_size; page_index = page_index + 4) { + /* Recreate the 32 bit word */ + data = ((unsigned int) buf[page_index + 3]) << 24 | + ((unsigned int) buf[page_index + 2]) << 16 | + ((unsigned int) buf[page_index + 1]) << 8 | + ((unsigned int) buf[page_index]); + /* Write the word in memory */ + EFlash_Write(waddr, data); + waddr += 4; + } + + return 0; +} + +/* + * EFlash_Read: Read function + * Parameters: + * waddr - address in flash + * Returns: + * the vaule read at address waddr + */ +unsigned int EFlash_Read(unsigned int waddr) +{ + unsigned int eflash_read = readl(waddr); + return eflash_read; +} + +/* + * EFlash_Verify: Verifies if the eFlash has been written correctly. + * Parameters: + * waddr - address in flash + * page_size - data to be written + * buf - buffer containing the data + * Returns: + * (waddr+page_size) - OK or Failed Address + */ +unsigned int EFlash_Verify(unsigned int waddr, unsigned int page_size, + unsigned char *buf) +{ + unsigned int page_index; + unsigned int eflash_data, buf_data; + + /* To be verified */ + for(page_index = 0; page_index < page_size; page_index = page_index + 4) { + /* Recreate the 32 bit word */ + buf_data = ((unsigned int) buf[page_index + 3]) << 24 | + ((unsigned int) buf[page_index + 2]) << 16 | + ((unsigned int) buf[page_index + 1]) << 8 | + ((unsigned int) buf[page_index]); + /* Read the word in memory */ + eflash_data = EFlash_Read(waddr); + if (eflash_data != buf_data) + break; + waddr += 4; + } + + /* Allign the address before return */ + return (waddr); +} + +/* + * EFlash_BlankCheck: Verifies if there is any Blank Block in eFlash + * Parameters: + * waddr - address in flash + * page_size - data to be written + * pat - pattern of a blank block + * Returns: + * 0 - OK or 1- Failed + */ +int EFlash_BlankCheck(unsigned int waddr, unsigned int page_size, + unsigned char pat) +{ + unsigned int page_index; + unsigned int eflash_data, buf_data; + + /* Page size div by 4 */ + page_size = page_size >> 2; + + /* To be verified */ + for(page_index = 0; page_index < page_size; page_index = page_index + 4) { + /* Recreate the 32 bit word */ + buf_data = ((unsigned int) pat) << 24 | + ((unsigned int) pat) << 16 | + ((unsigned int) pat) << 8 | + ((unsigned int) pat); + /* Read the word in memory */ + eflash_data = EFlash_Read(waddr); + if (eflash_data != buf_data) + return 1; + waddr += 4; + } + + return 0; +} + +/* + * Delay ns (uncalibrated delay) + */ +void EFlash_Delay(unsigned int period) { + int loop; + for (loop = 0; loop < period; loop++) + continue; +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h new file mode 100644 index 00000000000..84f278e2a9d --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.h @@ -0,0 +1,154 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _EFLASH_DRV_H +#define _EFLASH_DRV_H + +#include "fcache_api.h" + +#ifdef __cplusplus + +extern "C" { +#else +#include +#endif + + /* eFLASH Address Map */ +#define SYS_EFLASH_BASE 0x40009000 +#define SYS_EFLASH_IRQ_SET_STATUS (SYS_EFLASH_BASE + 0x008) +#define SYS_EFLASH_IRQ_CLR_STATUS (SYS_EFLASH_BASE + 0x008) +#define SYS_EFLASH_CTRL (SYS_EFLASH_BASE + 0x014) +#define SYS_EFLASH_STATUS (SYS_EFLASH_BASE + 0x018) +#define SYS_EFLASH_CONFIG0 (SYS_EFLASH_BASE + 0x01C) +#define SYS_EFLASH_WADDR (SYS_EFLASH_BASE + 0x028) +#define SYS_EFLASH_WDATA (SYS_EFLASH_BASE + 0x02C) +#define SYS_EFLASH_HWPARAMS0 (SYS_EFLASH_BASE + 0x034) +#define SYS_EFLASH_PIDR0 (SYS_EFLASH_BASE + 0xFE0) +#define SYS_EFLASH_PIDR1 (SYS_EFLASH_BASE + 0xFE4) +#define SYS_EFLASH_PIDR2 (SYS_EFLASH_BASE + 0xFE8) + + /* SYS_EFLASH_CTRL (RW): Flash Control Register */ +#define EFLASH_WRITE 1 /* Write one word on eFlash */ +#define EFLASH_ROW_WRITE (1 << 1) /* Write a row of eFlash */ +#define EFLASH_ERASE (1 << 2) /* Erase one page of eFlash */ +#define EFLASH_MASS_ERASE (1 << 3) /* Erases all pages of the eFlash*/ +#define EFLASH_STOP (1 << 4) /* Stop any write erase operation */ + + /* SYS_EFLASH_STATUS (RO): Status Register */ +#define EFLASH_BUSY_MASK 1 /* EFlash Busy Mask */ +#define EFLASH_BUSY 1 /* EFlash Busy */ +#define EFLASH_LOCK_MASK (1 << 1) /* EFlash Lock Mask */ +#define EFLASH_LOCK (1 << 1) /* EFlash Lock */ + + /* SYS_EFLASH_HWPARAMS0 (RO): HW parameters */ +#define EFLASH_FLASHSIZE 0x1F /* Flash Size */ + + /* SYS_EFLASH_PIDR2 (RO): Flash Memory Information */ +#define EFLASH_DES_1 0x7 /* JEP106 Id Mask */ +#define EFLASH_JEDEC 0x8 /* JEDEC assigned val Mask */ +#define EFLASH_REVISION 0xF0 /* Revision number */ + + /* Macros */ +#define readl(reg) *(volatile unsigned int *)reg +#define writel(reg, val) *(unsigned int *)reg = val; + + /* peripheral and component ID values */ +#define FLS_PID4 0x14 +#define FLS_PID5 0x00 +#define FLS_PID6 0x00 +#define FLS_PID7 0x00 +#define FLS_PID0 0x30 +#define FLS_PID1 0xB8 +#define FLS_PID2 0x0B +#define FLS_PID3 0x00 +#define FLS_CID0 0x0D +#define FLS_CID1 0xF0 +#define FLS_CID2 0x05 +#define FLS_CID3 0xB1 + +/* Functions */ +/* EFlash_Initialize: eFlash Initialize function */ +void EFlash_Initialize(void); +/* + * EFlash_Erase: Erases flash banks + * Mode: + * 0 - erases bank 0 + * 1 - erases bank 1 + * 2 - erases bank 0 + info pages + * 3 - erases bank 1 + info pages + * 4 - erases bank 0 + 1 + * 5 - erases bank 0 + 1 with info pages + */ +void EFlash_Erase(int mode); +/* EFlash_ErasePage: Erase a Page */ +void EFlash_ErasePage(unsigned int waddr); +/* + * EFlash_Write: Write function + * Parameters: + * waddr - address in flash + * data - data to be written + */ +void EFlash_Write(unsigned int waddr, unsigned int data); +/* + * EFlash_WritePage: Write Page function + * Parameters: + * waddr - address in flash + * page_size - data to be written + * buf - buffer containing the data + */ +int EFlash_WritePage(unsigned int waddr, + unsigned int page_size, unsigned char *buf); +/* + * EFlash_Read: Read function + * Parameters: + * waddr - address in flash + * Returns: + * the vaule read at address waddr + */ +unsigned int EFlash_Read(unsigned int waddr); +/* + * EFlash_Verify: Verifies if the eFlash has been written correctly. + * Parameters: + * waddr - address in flash + * page_size - data to be written + * buf - buffer containing the data + * Returns: + * (waddr+page_size) - OK or Failed Address + */ +unsigned int EFlash_Verify(unsigned int waddr, + unsigned int page_size, unsigned char *buf); +/* + * EFlash_BlankCheck: Verifies if there is any Blank Block in eFlash + * Parameters: + * waddr - address in flash + * page_size - data to be written + * pat - pattern of a blank block + * Returns: + * 0 - OK or 1- Failed + */ +int EFlash_BlankCheck(unsigned int waddr, + unsigned int page_size, unsigned char pat); + +/* EFlash_Delay function */ +void EFlash_Delay(unsigned int period); + +/* EFlash_ReturnBank1BaseAddress: Returns start address of bank 1 */ +int EFlash_ReturnBank1BaseAddress(void); + +#ifdef __cplusplus +} +#endif +#endif /* _FCACHE_DRV_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c new file mode 100644 index 00000000000..a3aa0367f31 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c @@ -0,0 +1,200 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fcache_api.h" + +static unsigned int enabled; +static unsigned int fcache_mode; +/* Functions */ + +/* + * FCache_Initialize: flash cache initialize funtion + */ +void FCache_Initialize() +{ + unsigned int irqstat; + + /* Clear interrupt status register */ + irqstat = readl(SYS_FCACHE_IRQSTAT) & (FCACHE_POW_ERR | FCACHE_MAN_INV_ERR); + writel(SYS_FCACHE_IRQSTAT, irqstat); + + /* Cache Disabled: Set enabled to 0 */ + enabled = 0; +} + +/* + * FCache_Enable: Enables the flash cache + * mode: supported modes: + * 0 - auto-power auto-invalidate + * 1 - manual-power, manual-invalidate + */ +void FCache_Enable(int mode) +{ + /* Save Enable Mode */ + fcache_mode = mode; + + /* Enable the FCache */ + switch (fcache_mode) { + case 0: + /* Statistic counters enabled, Cache enable, + * auto-inval, auto-power control + */ + writel(SYS_FCACHE_CCR, (FCACHE_EN | FCACHE_STATISTIC_EN)); + /* Wait until the cache is enabled */ + while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED); + /* Cache Enabled: Set enabled to 1 */ + enabled = 1; + break; + case 1: + /* + * Statistic counters enabled, Cache disabled, + * Manual power request (Setting: Power CTRL: + * Manual, Invalidate: Manual) + */ + writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ + | FCACHE_SET_MAN_POW + | FCACHE_SET_MAN_INV + | FCACHE_STATISTIC_EN)); + /* Wait until the cache rams are powered */ + while ((readl(SYS_FCACHE_SR) & FCACHE_POW_STAT) != FCACHE_POW_STAT); + /* Statistic counters enabled, Cache enabled + * Manual invalidate request (Setting: Power CTRL: + * Manual, Invalidate: Manual) + */ + writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ + | FCACHE_POW_REQ + | FCACHE_SET_MAN_POW + | FCACHE_SET_MAN_INV + | FCACHE_STATISTIC_EN)); + /* Wait until the cache is invalidated */ + while ((readl(SYS_FCACHE_SR) & FCACHE_INV_STAT) == FCACHE_INV_STAT); + /* Statistic counters enabled, Cache enable, + * manual-inval, manual-power control + */ + writel(SYS_FCACHE_CCR, (FCACHE_EN + | FCACHE_POW_REQ + | FCACHE_SET_MAN_POW + | FCACHE_SET_MAN_INV + | FCACHE_STATISTIC_EN)); + /* Wait until the cache is enabled */ + while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED); + /* Cache Enabled: Set enabled to 1 */ + enabled = 1; + break; + default: + break; + } +} + +/* + * FCache_Disable: Disables the cache + */ +void FCache_Disable() +{ + /* Disable the FCache */ + switch (fcache_mode) { + case 0: + /* Statistic counters enabled, Cache disable, + * auto-inval, auto-power control + */ + writel(SYS_FCACHE_CCR, FCACHE_STATISTIC_EN); + /* Wait until the cache is disabled */ + while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); + /* Cache Enabled: Set enabled to 0 */ + enabled = 0; + break; + case 1: + /* Statistic counters enabled, Cache disable, + * manual-inval, manual-power control + */ + writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ + | FCACHE_SET_MAN_POW + | FCACHE_SET_MAN_INV + | FCACHE_STATISTIC_EN)); + /* Wait until the cache is disabled */ + while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); + /* Cache Enabled: Set enabled to 0 */ + enabled = 0; + break; + default: + break; + } +} + +/* + * FCache_Invalidate: to be invalidated the cache needs to be disabled. + * return -1: flash cannot be disabled + * -2: flash cannot be enabled + */ +int FCache_Invalidate() +{ + /* Manual cache invalidate */ + if (fcache_mode == 1) + { + /* Disable Flash Cache */ + if (enabled == 1) + FCache_Disable(); + else + goto error; + + /* Trigger INV_REQ */ + writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ + | FCACHE_POW_REQ + | FCACHE_SET_MAN_POW + | FCACHE_SET_MAN_INV + | FCACHE_STATISTIC_EN)); + + /* Wait until INV_REQ is finished */ + while ((readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED); + + /* Clear Stats */ + writel(SYS_FCACHE_CSHR, 0); + writel(SYS_FCACHE_CSMR, 0); + + /* Enable Flash Cache */ + if (enabled == 0) + FCache_Enable(1); + +error: + if (enabled == 0) + return -1; + else + return -2; + } + + return 0; +} + +unsigned int * FCache_GetStats() +{ + static unsigned int stats[2]; + + /* Cache Statistics HIT Register */ + stats[0] = readl(SYS_FCACHE_CSHR); + /* Cache Statistics MISS Register */ + stats[1] = readl(SYS_FCACHE_CSMR); + + return stats; +} + +/* + * FCache_isEnabled: returns 1 if FCache is enabled + */ +unsigned int FCache_isEnabled() +{ + return enabled; +} + diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h new file mode 100644 index 00000000000..3060188c4eb --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FCACHE_DRV_H +#define _FCACHE_DRV_H + +#ifdef __cplusplus + +extern "C" { +#else +#include +#endif + + /* Flash Cache Address Map */ +#define SYS_FCACHE_BASE 0x40003000 +/* Configuration and Control Register */ +#define SYS_FCACHE_CCR (SYS_FCACHE_BASE) +/* Status Register */ +#define SYS_FCACHE_SR (SYS_FCACHE_BASE + 0x4) +/* Interrupt Req Status Register */ +#define SYS_FCACHE_IRQSTAT (SYS_FCACHE_BASE + 0x8) +/* Cache Statistic Hit Register */ +#define SYS_FCACHE_CSHR (SYS_FCACHE_BASE + 0x14) +/* Cache Statistic Miss Register */ +#define SYS_FCACHE_CSMR (SYS_FCACHE_BASE + 0x18) + + /* SYS_FCACHE_CCR (RW): Configuration and Control Register */ +#define FCACHE_EN 1 /* FCache Enable */ +#define FCACHE_INV_REQ (1 << 1) /* Manual Invalidate Request */ +#define FCACHE_POW_REQ (1 << 2) /* Manual SRAM Power Request */ +#define FCACHE_SET_MAN_POW (1 << 3) /* Power Control Setting */ +#define FCACHE_SET_MAN_INV (1 << 4) /* Invalidate Control Setting */ +#define FCACHE_SET_PREFETCH (1 << 5) /* Cache Prefetch Setting */ +#define FCACHE_STATISTIC_EN (1 << 6) /* Enable Statistics Logic */ + + /* SYS_FCACHE_SR (RO): Status Register */ +#define FCACHE_CS 0x3 /* Cache Status Mask */ +#define FCACHE_CS_DISABLED 0x0 +#define FCACHE_CS_ENABLING 0x1 +#define FCACHE_CS_ENABLED 0x2 +#define FCACHE_CS_DISABLING 0x3 +#define FCACHE_INV_STAT 0x4 /* Invalidating Status */ +#define FCACHE_POW_STAT 0x10 /* SRAM Power Ack */ + + /* SYS_FCACHE_IRQSTAT (RW): Interrupt Req Status Register */ +#define FCACHE_POW_ERR 1 /* SRAM Power Error */ +#define FCACHE_MAN_INV_ERR (1 << 1) /* Manual Invalidation error status */ + + /* Macros */ +#define readl(reg) *(volatile unsigned int *)reg +#define writel(reg, val) *(unsigned int *)reg = val; + +/* Functions */ + +/* + * FCache_Initialize: flash cache initialize funtion + */ +void FCache_Initialize(void); + +/* + * FCache_Enable: Enables the flash cache + * mode: supported modes: + * 0 - auto-power auto-invalidate + * 1 - manual-power, manual-invalidate + */ +void FCache_Enable(int mode); + +/* + * FCache_Disable: Disables the cache + */ +void FCache_Disable(void); + +/* + * FCache_Invalidate: to be invalidated the cache needs to be disabled. + * return -1: flash cannot be disabled + * -2: flash cannot be enabled + */ +int FCache_Invalidate(void); + +/* + * FCache_GetStats: provides cache stats + */ +unsigned int * FCache_GetStats(void); + +/* + * FCache_isEnabled: returns 1 if FCache is enabled + */ +unsigned int FCache_isEnabled(void); + +#ifdef __cplusplus +} +#endif +#endif /* _FCACHE_DRV_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.c new file mode 100644 index 00000000000..ff6fbdaf5fc --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 system_ARMCM3.c + */ + +#include "cmsis.h" + +/*---------------------------------------------------------------------------- + * Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (48000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + +/*---------------------------------------------------------------------------- + * Clock Variable definitions + *----------------------------------------------------------------------------*/ +/* !< System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + * Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; + + // Enable AHB and APB clock + /* GPIO */ + CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; + /* + * Activate clock for: I2C1, SPI1, SPIO, QUADSPI, WDOG, + * I2C0, UART0, UART1, TIMER0, TIMER1, DUAL TIMER, TRNG + */ + CMSDK_SYSCON->APBCLKCFG0SET = SYSTEM_CORE_TIMER0 + | SYSTEM_CORE_TIMER1 + | SYSTEM_CORE_DUALTIMER0 + | SYSTEM_CORE_UART0 + | SYSTEM_CORE_UART1 + | SYSTEM_CORE_I2C0 + | SYSTEM_CORE_WDOG + | SYSTEM_CORE_QSPI + | SYSTEM_CORE_SPI0 + | SYSTEM_CORE_SPI1 + | SYSTEM_CORE_I2C1 + | SYSTEM_CORE_TRNG; + /* Beetle System Core Config */ + SystemCoreConfig(); +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.h new file mode 100644 index 00000000000..355523b9308 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file is derivative of CMSIS V5.00 system_ARMCM3.h + */ + + +#ifndef SYSTEM_CMSDK_BEETLE_H +#define SYSTEM_CMSDK_BEETLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_BEETLE_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.c new file mode 100644 index 00000000000..9ff7c651f06 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.c @@ -0,0 +1,121 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "CMSDK_BEETLE.h" +#include "system_core_beetle.h" + +/* + * SystemCoreConfig(): Configure the System Core + */ +void SystemCoreConfig() +{ + /* Set GPIO Alternate Functions */ + CMSDK_GPIO0->ALTFUNCSET = (1<<0); /* Sheild 0 UART 0 RXD */ + CMSDK_GPIO0->ALTFUNCSET |= (1<<1); /* Sheild 0 UART 0 TXD */ + CMSDK_GPIO0->ALTFUNCSET |= (1<<14); /* Sheild 0 I2C SDA SBCON2 */ + CMSDK_GPIO0->ALTFUNCSET |= (1<<15); /* Sheild 0 I2C SCL SBCON2 */ + CMSDK_GPIO0->ALTFUNCSET |= (1<<10); /* Sheild 0 SPI_3 nCS */ + CMSDK_GPIO0->ALTFUNCSET |= (1<<11); /* Sheild 0 SPI_3 MOSI */ + CMSDK_GPIO0->ALTFUNCSET |= (1<<12); /* Sheild 0 SPI_3 MISO */ + CMSDK_GPIO0->ALTFUNCSET |= (1<<13); /* Sheild 0 SPI_3 SCK */ + + CMSDK_GPIO1->ALTFUNCSET = (1<<0); /* UART 1 RXD */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<1); /* UART 1 TXD */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<6); /* Sheild 1 I2C SDA */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<7); /* Sheild 1 I2C SCL */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<2); /* ADC SPI_2 nCS */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<3); /* ADC SPI_2 MOSI */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<4); /* ADC SPI_2 MISO */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<5); /* ADC SPI_2 SCK */ + + CMSDK_GPIO1->ALTFUNCSET |= (1<<8); /* QSPI CS 2 */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<9); /* QSPI CS 1 */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<10); /* QSPI IO 0 */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<11); /* QSPI IO 1 */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<12); /* QSPI IO 2 */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<13); /* QSPI IO 3 */ + CMSDK_GPIO1->ALTFUNCSET |= (1<<14); /* QSPI SCK */ + + /* Set the ARD_PWR_EN GPIO1[15] as an output */ + CMSDK_GPIO1->OUTENABLESET |= (0x1 << 15); + /* Set on 3v3 (for ARDUINO HDR compliancy) */ + CMSDK_GPIO1->DATA |= (0x1 << 15); +} + +/* POWER MANAGEMENT */ + +/* + * SystemPowerConfig(): Configures the System Power Modes + */ +void SystemPowerConfig() +{ + /* Configure APB Peripheral Clock in sleep state */ + CMSDK_SYSCON->APBCLKCFG1SET = SYSTEM_CORE_TIMER0 + | SYSTEM_CORE_TIMER1 + | SYSTEM_CORE_DUALTIMER0 + | SYSTEM_CORE_UART1 + | SYSTEM_CORE_I2C0 + | SYSTEM_CORE_QSPI + | SYSTEM_CORE_SPI0 + | SYSTEM_CORE_SPI1 + | SYSTEM_CORE_I2C1; + + /* Configure APB Peripheral Clock in deep sleep state */ + CMSDK_SYSCON->APBCLKCFG2SET = SYSTEM_CORE_TIMER0 + | SYSTEM_CORE_TIMER1 + | SYSTEM_CORE_DUALTIMER0 + | SYSTEM_CORE_UART1 + | SYSTEM_CORE_I2C0 + | SYSTEM_CORE_QSPI + | SYSTEM_CORE_SPI0 + | SYSTEM_CORE_SPI1 + | SYSTEM_CORE_I2C1; + + /* Configure Wakeup Sources */ + CMSDK_SYSCON->PWRDNCFG1SET = SYSTEM_CORE_DUALTIMER0; +} + +/* + * SystemPowerSuspend(): Enters in System Suspend + */ +void SystemPowerSuspend(power_mode_t mode) +{ + if (mode == POWER_MODE_DEEP_SLEEP) { + /* Enable deepsleep */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + /* Ensure effect of last store takes effect */ + __DSB(); + /* Enter sleep mode */ + __WFI(); + } else { + /* Enter sleep mode */ + __WFI(); + } +} + +/* + * SystemPowerResume(): Returns from System Suspend + */ +void SystemPowerResume(power_mode_t mode) +{ + if (mode == POWER_MODE_DEEP_SLEEP) { + /* Disable sleeponexit */ + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + /* Ensure effect of last store takes effect */ + __DSB(); + } +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.h new file mode 100644 index 00000000000..7c7e7b2bca8 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_beetle.h @@ -0,0 +1,71 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_CORE_BEETLE_H +#define SYSTEM_CORE_BEETLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SystemCoreConfig(): Configure the System Core + */ +void SystemCoreConfig(void); + +/* POWER MANAGEMENT */ +/* Power Mode Type Definition */ +typedef enum { + /* Sleep Power Mode */ + POWER_MODE_SLEEP = 0, + /* Deep Sleep Power Mode */ + POWER_MODE_DEEP_SLEEP = 1 +} power_mode_t; + +/* APB System Core Clocks */ +#define SYSTEM_CORE_TIMER0 (1 << 0) +#define SYSTEM_CORE_TIMER1 (1 << 1) +#define SYSTEM_CORE_DUALTIMER0 (1 << 2) +#define SYSTEM_CORE_UART0 (1 << 4) +#define SYSTEM_CORE_UART1 (1 << 5) +#define SYSTEM_CORE_I2C0 (1 << 7) +#define SYSTEM_CORE_WDOG (1 << 8) +#define SYSTEM_CORE_QSPI (1 << 11) +#define SYSTEM_CORE_SPI0 (1 << 12) +#define SYSTEM_CORE_SPI1 (1 << 13) +#define SYSTEM_CORE_I2C1 (1 << 14) +#define SYSTEM_CORE_TRNG (1 << 15) /* TRNG can not be a wakeup source */ + +/* + * SystemPowerConfig(): Configures the System Power Modes + */ +void SystemPowerConfig(void); + +/* + * SystemPowerSuspend(): Enters in System Suspend + */ +void SystemPowerSuspend(power_mode_t mode); + +/* + * SystemPowerResume(): Returns from System Suspend + */ +void SystemPowerResume(power_mode_t mode); + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_CORE_BEETLE_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.c new file mode 100644 index 00000000000..fd1ba1166b9 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.c @@ -0,0 +1,39 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include "system_core_version.h" + +#define REALLY_MAKE_STR(y) #y +#define MAKE_STR(x) REALLY_MAKE_STR(x) +#define SYSTEM_CORE_VERSION() (SYSTEM_CORE_PLATFORM ".SYSTEM.CORE." \ + MAKE_STR(SYSTEM_CORE_OS) \ + "." MAKE_STR(SYSTEM_CORE_VERSION_MAJOR) \ + "." MAKE_STR(SYSTEM_CORE_VERSION_MINOR) \ + "." MAKE_STR(SYSTEM_CORE_VERSION_PATCH) \ + " " SYSTEM_CORE_DATE \ + " " SYSTEM_CORE_TIME) + +/* Private Data */ +static uint32_t initialized = 0; +const char *system_core_version = SYSTEM_CORE_VERSION(); + + /* Get System Core Version */ +const char* SystemCoreGetVersion() +{ + return system_core_version; +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.h new file mode 100644 index 00000000000..35d1baebd9b --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_core_version.h @@ -0,0 +1,45 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_CORE_VERSION_H +#define SYSTEM_CORE_VERSION_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Platform Name */ +#define SYSTEM_CORE_PLATFORM "ARM SSG BEETLE" + +/* OS Version */ +#define SYSTEM_CORE_OS 2 + +/* System Core Version */ +#define SYSTEM_CORE_VERSION_MAJOR 0 +#define SYSTEM_CORE_VERSION_MINOR 1 +#define SYSTEM_CORE_VERSION_PATCH 0 +#define SYSTEM_CORE_DATE __DATE__ +#define SYSTEM_CORE_TIME __TIME__ + +/* Get System Core Version */ +const char* SystemCoreGetVersion(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CORE_VERSION_H */ diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.c b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.c new file mode 100644 index 00000000000..5b5857d6b9c --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.c @@ -0,0 +1,90 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" +#include "systick_timer.h" + +volatile uint32_t MyTicks; + +/* Private Data SysTick */ +static uint32_t clock; + +/* + * This Timer is written for MBED OS so the interrupt + * is used to keep track of the overflow. + */ +#define SYSTICK_MAX_RELOAD 0xFFFFFFFF +#define SYSTICK_DIVIDER_US (SystemCoreClock/1000000) + +void SysTick_Handler(void) +{ + MyTicks++; +#if 0 + printf("System Tick Interrupt: %u\n\r", MyTicks); +#endif +} + +/* + * SysTick_Initialize(): Initializes the SysTick timer + */ +void SysTick_Initialize(void) +{ + clock = SYSTICK_MAX_RELOAD; +#if 0 + printf("\n\rEnable System Tick Interrupt...\n\r"); +#endif + MyTicks=0; + + /* SysTick Reload Value Register */ + SysTick->LOAD = clock; + + /* + * SysTick_CTRL_CLKSOURCE_Msk : Use core's clock + * SysTick_CTRL_ENABLE_Msk : Enable SysTick + * SysTick_CTRL_TICKINT_Msk : Active the SysTick interrupt on the NVIC + */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk + | SysTick_CTRL_ENABLE_Msk + | SysTick_CTRL_TICKINT_Msk; +} + +/* + * SysTick_Disable(): Disables the SysTick timer + */ +void SysTick_Disable(void) +{ + /* Disable SysTick */ + SysTick->CTRL = 0; +} + +/* + * SysTick_Read(): Read SysTick Value + * @return: the SysTick VALUE + */ +uint32_t SysTick_Read(void) +{ + return ((clock - (SysTick->VAL)) / SYSTICK_DIVIDER_US); +} + +/* + * SysTick_Overflow(): Read SysTick Overflow Value + * @return: the SysTick Overflow VALUE + */ +uint32_t SysTick_Overflow(void) +{ + return MyTicks; +} diff --git a/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.h b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.h new file mode 100644 index 00000000000..0d214c757b2 --- /dev/null +++ b/hal/targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/systick_timer.h @@ -0,0 +1,51 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _SYSTICK_TIMER_H +#define _SYSTICK_TIMER_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SysTick_Initialize(): Initializes the SysTick timer + */ +void SysTick_Initialize(void); + +/* + * SysTick_Disable(): Disables the SysTick timer + */ +void SysTick_Disable(void); + +/* + * SysTick_Read(): Read SysTick Value + * @return: the SysTick VALUE + */ +uint32_t SysTick_Read(void); + +/* + * SysTick_Overflow(): Read SysTick Overflow Value + * @return: the SysTick Overflow VALUE + */ +uint32_t SysTick_Overflow(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTICK_TIMER_H */ From 09b5551d419230a726abe2f163bcae2e6df27277 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Wed, 11 May 2016 16:02:24 +0100 Subject: [PATCH 3/6] [BEETLE] Add initial Beetle HAL files This patch adds support for BEETLE SoC Target into the HAL layer. It contains: * Beetle Platform Configuration * I2C API * SPI API * Serial API * Port API * us Ticker API Signed-off-by: Vincenzo Frascino --- .../TARGET_BEETLE/PeripheralNames.h | 82 +++ .../TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h | 151 ++++++ .../TARGET_ARM_SSG/TARGET_BEETLE/PortNames.h | 32 ++ .../TARGET_BEETLE/analogin_api.c | 148 +++++ .../hal/TARGET_ARM_SSG/TARGET_BEETLE/device.h | 21 + .../TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c | 86 +++ .../TARGET_BEETLE/gpio_irq_api.c | 399 ++++++++++++++ .../TARGET_BEETLE/gpio_object.h | 55 ++ .../TARGET_ARM_SSG/TARGET_BEETLE/i2c_api.c | 508 ++++++++++++++++++ .../TARGET_ARM_SSG/TARGET_BEETLE/i2c_def.h | 101 ++++ .../TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c | 135 +++++ .../TARGET_BEETLE/mbed_sdk_init.c | 29 + .../TARGET_ARM_SSG/TARGET_BEETLE/objects.h | 70 +++ .../hal/TARGET_ARM_SSG/TARGET_BEETLE/pinmap.c | 27 + .../TARGET_ARM_SSG/TARGET_BEETLE/port_api.c | 70 +++ .../TARGET_ARM_SSG/TARGET_BEETLE/serial_api.c | 330 ++++++++++++ .../TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c | 271 ++++++++++ .../TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h | 134 +++++ .../TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c | 94 ++++ 19 files changed, 2743 insertions(+) create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PeripheralNames.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PortNames.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/analogin_api.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/device.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_irq_api.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_api.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_def.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/mbed_sdk_init.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/objects.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/pinmap.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/port_api.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/serial_api.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h create mode 100644 hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PeripheralNames.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PeripheralNames.h new file mode 100644 index 00000000000..87d311f19d9 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PeripheralNames.h @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "i2c_def.h" +#include "spi_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)CMSDK_UART0_BASE, + UART_1 = (int)CMSDK_UART1_BASE +} UARTName; + +typedef enum { + I2C_0 = (int)I2C0_BASE, + I2C_1 = (int)I2C1_BASE + +} I2CName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5 +} ADCName; + +typedef enum { + SPI_0 = (int)SPI0_BASE, + SPI_1 = (int)SPI1_BASE +} SPIName; + +typedef enum { + PWM_1 = 0, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11 +} PWMName; + +#define STDIO_UART_TX UART_TX1 +#define STDIO_UART_RX UART_RX1 +#define STDIO_UART UART_1 + +#define MBED_UART0 UART_TX0, UART_RX0 +#define MBED_UART1 UART_TX1, UART_RX1 +#define MBED_UARTUSB UART_TX1, UART_RX1 + +//USB UART +#define USBTX UART_TX1 +#define USBRX UART_RX1 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h new file mode 100644 index 00000000000..af03c749e87 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h @@ -0,0 +1,151 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { +/* BEETLE Pin Names */ +/* GPIO0 */ + P0_0 = 0, + P0_1 = 1, + P0_2 = 2, + P0_3 = 3, + P0_4 = 4, + P0_5 = 5, + P0_6 = 6, + P0_7 = 7, + P0_8 = 8, + P0_9 = 9, + P0_10 = 10, + P0_11 = 11, + P0_12 = 12, + P0_13 = 13, + P0_14 = 14, + P0_15 = 15, + +/* GPIO1 */ + P1_0 = 16, + P1_1 = 17, + P1_2 = 18, + P1_3 = 19, + P1_4 = 20, + P1_5 = 21, + P1_6 = 22, + P1_7 = 23, + P1_8 = 24, + P1_9 = 25, + P1_10 = 26, + P1_11 = 27, + P1_12 = 28, + P1_13 = 29, + P1_14 = 30, + P1_15 = 31, + +/* Arduino Connector Namings */ + A0 = 600, + A1 = 601, + A2 = 602, + A3 = 603, + A4 = 604, + A5 = 605, + D0 = P0_0, + D1 = P0_1, + D2 = P0_2, + D3 = P0_3, + D4 = P0_4, + D5 = P0_5, + D6 = P0_6, + D7 = P0_7, + D8 = P0_8, + D9 = P0_9, + D10 = P0_10, + D11 = P0_11, + D12 = P0_12, + D13 = P0_13, + D14 = P0_14, + D15 = P0_15, + +/* TRACE Ports */ + TRACECLK = P0_2, + TRACED0 = P0_6, + TRACED1 = P0_7, + TRACED2 = P0_8, + TRACED3 = P0_9, + +/* Other BEETLE Pin Names */ + + //Shield SPI + SHIELD_SPI_SCK = 320, + SHIELD_SPI_MOSI = 321, + SHIELD_SPI_MISO = 322, + SHIELD_SPI_nCS = 323, + + //ADC SPI + ADC_SPI_MOSI = 650, + ADC_SPI_MISO = 651, + ADC_SPI_SCK = 652, + ADC_SPI_nCS = 653, + + //Uart + UART_TX0 = 400, + UART_RX0 = 401, + UART_TX1 = 402, + UART_RX1 = 403, + + //Shield I2C + SHIELD_SDA = 504, + SHIELD_SCL = 505, + + // Internal I2C for temperature and acceleromter sensor + SENSOR_SDA = 506, + SENSOR_SCL = 507, + + // Not connected + NC = (int)0xFFFFFFFF, + // LEDS not connected + LED1 = NC, + LED2 = NC, + LED3 = NC, + LED4 = NC, +} PinName; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PortNames.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PortNames.h new file mode 100644 index 00000000000..c7751a5559e --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PortNames.h @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/analogin_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/analogin_api.c new file mode 100644 index 00000000000..76929547c6f --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/analogin_api.c @@ -0,0 +1,148 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis.h" +#include "mbed_assert.h" +#include "wait_api.h" +#include "analogin_api.h" +#include "gpio_api.h" +#include "spi_api.h" +#include "pinmap.h" + +#if DEVICE_ANALOGIN + +/* + * Channel Address for the next acquisition: + * XXAAAXXX XXXXXXXX + */ +#define ADC_SPI_ADDRESS 11 + +/* ADC Resolution */ +#define ADC_RESOLUTION 0xFFF + +/* ADC Voltage Divider */ +#define ADC_DIV 819.0 + +/* PinMap structure for ADC IN */ +static const PinMap PinMap_ADC[] = { + {A0, ADC0_0, 0}, + {A1, ADC0_1, 0}, + {A2, ADC0_2, 0}, + {A3, ADC0_3, 0}, + {A4, ADC0_4, 0}, + {A5, ADC0_5, 0}, + {NC, NC, 0} +}; + +/* ADC SPI Private Data */ +typedef struct { + /* ADC SPI */ + spi_t analogin_spi; + /* ADC SPI CS */ + gpio_t adc_spi_cs_gpio; + /* ADC SPI State */ + uint32_t analog_spi_inited; +} analogin_spi_t; +/* ADC SPI Device */ +static analogin_spi_t analogin_spi_dev; + +/* + * ADC SPI CS + */ +#define ADC_SPI_CS P1_2 + +/* + * Initialize the analogin peripheral + * Configures the pin used by analogin. + * obj: The analogin object to initialize + * pin: The analogin pin name + */ +void analogin_init(analogin_t *obj, PinName pin) +{ + /* Initialize ADC Pin */ + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + /* Verify if pin is valid */ + MBED_ASSERT(obj->adc != (ADCName)NC); + + /* Initialize the ADC SPI */ + if(analogin_spi_dev.analog_spi_inited == 0){ + /* Initialize SPI for ADC */ + spi_init(&(analogin_spi_dev.analogin_spi), ADC_SPI_MOSI, + ADC_SPI_MISO, ADC_SPI_SCK, ADC_SPI_nCS); + spi_format(&(analogin_spi_dev.analogin_spi), 16, 3, 0); + /* Set SPI to MAX Freq */ + spi_frequency(&(analogin_spi_dev.analogin_spi), 0); + + /* Initialize CS GPIO */ + gpio_init_out(&(analogin_spi_dev.adc_spi_cs_gpio), ADC_SPI_CS); + + analogin_spi_dev.analog_spi_inited = 1; + } + + /* If pin is valid assign it to the ADC data structure */ + obj->pin = pin; + obj->pin_number = pin-600; + obj->address = (0x0000 | (pin-600)); + + /* Configure the pinout */ + pinmap_pinout(pin, PinMap_ADC); +} + +/* + * Read the value from analogin pin, represented as an unsigned 16bit value + * obj: The analogin object + * @return: An unsigned 16bit value representing the current input voltage + */ +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t result = 0; + + /* + * The ADC SPI hw is 8 bit format, 16 bit emulation is required + * in the SPI driver. + */ + /* CS = 1 */ + gpio_write(&(analogin_spi_dev.adc_spi_cs_gpio), 1); + /* Do the first read */ + (void)spi_master_write(&(analogin_spi_dev.analogin_spi), + ((obj->pin_number) << ADC_SPI_ADDRESS)); + /* CS = 0 */ + gpio_write(&(analogin_spi_dev.adc_spi_cs_gpio), 0); + /* Wait 50 us */ + wait_us(50); + /* CS = 1 */ + gpio_write(&(analogin_spi_dev.adc_spi_cs_gpio), 1); + /* The second read provides the result */ + result = spi_master_write(&(analogin_spi_dev.analogin_spi), + ((obj->pin_number) << ADC_SPI_ADDRESS)); + /* CS = 0 */ + gpio_write(&(analogin_spi_dev.adc_spi_cs_gpio), 0); + + return result; +} + +/* + * Read the input voltage, represented as a float in the range [0.0, 1.0] + * obj: The analogin object + * @return: A floating value representing the current input voltage + */ +float analogin_read(analogin_t *obj) +{ + uint16_t result = analogin_read_u16(obj); + return (float)((result & ADC_RESOLUTION) * 1.0f) / ADC_DIV; +} + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/device.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/device.h new file mode 100644 index 00000000000..0849da0d36f --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/device.h @@ -0,0 +1,21 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c new file mode 100644 index 00000000000..d8d40b0525b --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" + +// function to enable the GPIO pin +uint32_t gpio_set(PinName pin) { + uint32_t pin_value = 0; + + if(pin <= 15) { + pin_value = pin; + } else if (pin >= 16 && pin <= 31) { + pin_value = pin-16; + } + + pin_function(pin, 0); + + return (1 << pin_value); +} + +//function to initialise the gpio pin +// this links the board control bits for each pin +// with the object created for the pin +void gpio_init(gpio_t *obj, PinName pin) { + if (pin == NC) { + return; + } else { + int pin_value = 0; + obj->pin = pin; + if (pin <=15) { + pin_value = pin; + } else if (pin >= 16 && pin <= 31) { + pin_value = pin-16; + } + + obj->mask = 0x1 << pin_value; + obj->pin_number = pin; + if (pin <=15) { + obj->reg_data = &CMSDK_GPIO0->DATAOUT; + obj->reg_in = &CMSDK_GPIO0->DATA; + obj->reg_dir = &CMSDK_GPIO0->OUTENABLESET; + obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR; + } else if (pin >= 16 && pin <= 31) { + obj->reg_data = &CMSDK_GPIO1->DATAOUT; + obj->reg_in = &CMSDK_GPIO1->DATA; + obj->reg_dir = &CMSDK_GPIO1->OUTENABLESET; + obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR; + } + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + if(obj->pin >= 0 && obj->pin <= 31) { + switch (direction) { + case PIN_INPUT : *obj->reg_dirclr = obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } + } else { + return; + } +} + +int gpio_is_connected(const gpio_t *obj){ + if(obj->pin != (PinName)NC){ + return 1; + } else { + return 0; + } +} diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_irq_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_irq_api.c new file mode 100644 index 00000000000..37f7936d670 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_irq_api.c @@ -0,0 +1,399 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +#define CHANNEL_NUM 32 +#define CMSDK_GPIO_0 CMSDK_GPIO0 +#define CMSDK_GPIO_1 CMSDK_GPIO1 +#define PININT_IRQ 0 + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler irq_handler; + +static inline void handle_interrupt_in(uint32_t channel) { + uint32_t ch_bit = (1 << channel); + // Return immediately if: + // * The interrupt was already served + // * There is no user handler + // * It is a level interrupt, not an edge interrupt + if (ch_bit <16){ + if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) + || ((CMSDK_GPIO_0->INTTYPESET) == 0)) + return; + + if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) + && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_0->INTPOLSET = ch_bit; + } + if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) + && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_FALL); + } + CMSDK_GPIO_0->INTCLEAR = ch_bit; + } + + if (ch_bit>=16) { + if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) + || ((CMSDK_GPIO_1->INTTYPESET) == 0)) + return; + + if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) + && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_RISE); + CMSDK_GPIO_1->INTPOLSET = ch_bit; + } + if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) + && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { + irq_handler(channel_ids[channel], IRQ_FALL); + } + CMSDK_GPIO_1->INTCLEAR = ch_bit; + } +} + +void gpio0_irq0(void) { + handle_interrupt_in(0); +} + +void gpio0_irq1(void) { + handle_interrupt_in(1); +} + +void gpio0_irq2(void) { + handle_interrupt_in(2); +} + +void gpio0_irq3(void) { + handle_interrupt_in(3); +} + +void gpio0_irq4(void) { + handle_interrupt_in(4); +} + +void gpio0_irq5(void) { + handle_interrupt_in(5); +} + +void gpio0_irq6(void) { + handle_interrupt_in(6); +} + +void gpio0_irq7(void) { + handle_interrupt_in(7); +} + +void gpio0_irq8(void) { + handle_interrupt_in(8); +} + +void gpio0_irq9(void) { + handle_interrupt_in(9); +} + +void gpio0_irq10(void) { + handle_interrupt_in(10); +} + +void gpio0_irq11(void) { + handle_interrupt_in(11); +} + +void gpio0_irq12(void) { + handle_interrupt_in(12); +} + +void gpio0_irq13(void) { + handle_interrupt_in(13); +} + +void gpio0_irq14(void) { + handle_interrupt_in(14); +} + +void gpio0_irq15(void) { + handle_interrupt_in(15); +} + +void gpio1_irq0(void) { + handle_interrupt_in(16); +} + +void gpio1_irq1(void) { + handle_interrupt_in(17); +} + +void gpio1_irq2(void) { + handle_interrupt_in(18); +} + +void gpio1_irq3(void) { + handle_interrupt_in(19); +} + +void gpio1_irq4(void) { + handle_interrupt_in(20); +} + +void gpio1_irq5(void) { + handle_interrupt_in(21); +} + +void gpio1_irq6(void) { + handle_interrupt_in(22); +} + +void gpio1_irq7(void) { + handle_interrupt_in(23); +} + +void gpio1_irq8(void) { + handle_interrupt_in(24); +} + +void gpio1_irq9(void) { + handle_interrupt_in(25); +} + +void gpio1_irq10(void) { + handle_interrupt_in(26); +} + +void gpio1_irq11(void) { + handle_interrupt_in(27); +} + +void gpio1_irq12(void) { + handle_interrupt_in(28); +} + +void gpio1_irq13(void) { + handle_interrupt_in(29); +} + +void gpio1_irq14(void) { + handle_interrupt_in(30); +} + +void gpio1_irq15(void) { + handle_interrupt_in(31); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, + gpio_irq_handler handler, uint32_t id) { + if (pin == NC) {return -1;} + else { + + irq_handler = handler; + + int found_free_channel = 0; + int i = 0; + for (i=0; ich = i; + found_free_channel = 1; + break; + } + } + if (!found_free_channel) + return -1; + /* To select a pin for any of the eight pin interrupts, write the pin number + * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. + * @see: mbed_capi/PinNames.h + */ + if (pin <16) { + CMSDK_GPIO_0->INTENSET |= (0x1 << pin); + } + + if (pin >= 16) { + CMSDK_GPIO_1->INTENSET |= (0x1 << pin); + } + + void (*channels_irq)(void) = NULL; + switch (obj->ch) { + case 0: + channels_irq = &gpio0_irq0; + break; + case 1: + channels_irq = &gpio0_irq1; + break; + case 2: + channels_irq = &gpio0_irq2; + break; + case 3: + channels_irq = &gpio0_irq3; + break; + case 4: + channels_irq = &gpio0_irq4; + break; + case 5: + channels_irq = &gpio0_irq5; + break; + case 6: + channels_irq = &gpio0_irq6; + break; + case 7: + channels_irq = &gpio0_irq7; + break; + case 8: + channels_irq = &gpio0_irq8; + break; + case 9: + channels_irq = &gpio0_irq9; + break; + case 10: + channels_irq = &gpio0_irq10; + break; + case 11: + channels_irq = &gpio0_irq11; + break; + case 12: + channels_irq = &gpio0_irq12; + break; + case 13: + channels_irq = &gpio0_irq13; + break; + case 14: + channels_irq = &gpio0_irq14; + break; + case 15: + channels_irq = &gpio0_irq15; + break; + case 16: + channels_irq = &gpio1_irq0; + break; + case 17: + channels_irq = &gpio1_irq1; + break; + case 18: + channels_irq = &gpio1_irq2; + break; + case 19: + channels_irq = &gpio1_irq3; + break; + case 20: + channels_irq = &gpio1_irq4; + break; + case 21: + channels_irq = &gpio1_irq5; + break; + case 22: + channels_irq = &gpio1_irq6; + break; + case 23: + channels_irq = &gpio1_irq7; + break; + case 24: + channels_irq = &gpio1_irq8; + break; + case 25: + channels_irq = &gpio1_irq9; + break; + case 26: + channels_irq = &gpio1_irq10; + break; + case 27: + channels_irq = &gpio1_irq11; + break; + case 28: + channels_irq = &gpio1_irq12; + break; + case 29: + channels_irq = &gpio1_irq13; + break; + case 30: + channels_irq = &gpio1_irq14; + break; + case 31: + channels_irq = &gpio1_irq15; + break; + } + NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), + (uint32_t)channels_irq); + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); + + return 0; + } +} + +void gpio_irq_free(gpio_irq_t *obj) { +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + unsigned int ch_bit = (1 << obj->ch); + + // Clear interrupt + if (obj->ch <16) { + if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) { + CMSDK_GPIO_0->INTCLEAR = ch_bit; + } + } + if (obj->ch >= 16) { + if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) { + CMSDK_GPIO_1->INTCLEAR = ch_bit; + } + } + + // Edge trigger + if (obj->ch <16) { + CMSDK_GPIO_0->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_0->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_0->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_0->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_0->INTENCLR |= ch_bit; + } + } + } + if (obj->ch >= 16) { + CMSDK_GPIO_1->INTTYPESET &= ch_bit; + if (event == IRQ_RISE) { + CMSDK_GPIO_1->INTPOLSET |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } + } else { + CMSDK_GPIO_1->INTPOLCLR |= ch_bit; + if (enable) { + CMSDK_GPIO_1->INTENSET |= ch_bit; + } else { + CMSDK_GPIO_1->INTENCLR |= ch_bit; + } + } + } +} + +void gpio_irq_enable(gpio_irq_t *obj) { + NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +} + +void gpio_irq_disable(gpio_irq_t *obj) { + NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); +} diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h new file mode 100644 index 00000000000..a2c16ed3671 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + uint32_t pin_number; + + __IO uint32_t *reg_dir; + __IO uint32_t *reg_dirclr; + __IO uint32_t *reg_data; + __I uint32_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + if (value == 1){ + *obj->reg_data |= (obj->mask); + } else if (value == 0){ + *obj->reg_data &= ~(obj->mask); + } +} + +static inline int gpio_read(gpio_t *obj) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_api.c new file mode 100644 index 00000000000..814be490b4c --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_api.c @@ -0,0 +1,508 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" +#include "i2c_def.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "wait_api.h" +/* States of a possibly combined I2C transfer */ +typedef enum i2c_transfer_state_t { + I2C_TRANSFER_SINGLE, /* Non combined transfer */ + I2C_TRANSFER_COMBINED_FIRST_MESSAGE, /* + * First message of a + * combined transfer + */ + I2C_TRANSFER_COMBINED_INTERMEDIATE_MESSAGE, /* + * Message in the middle + * of a combined + * transfer + */ + I2C_TRANSFER_COMBINED_LAST_MESSAGE, /* + * Last message of a combined + * transfer + */ +} i2c_transfer_state_t; + +/* + * Driver private data structure that should not be shared by multiple + * instances of the driver + * (same driver for multiple instances of the IP) + */ +typedef struct private_i2c_t { + /* State of a possibly combined ongoing i2c transfer */ + i2c_transfer_state_t transfer_state; +}private_i2c_t; + + +/* + * Retrieve the private data of the instance related to a given IP + */ +static private_i2c_t* get_i2c_private(i2c_t *obj) { + static private_i2c_t data0, data1; + /* + * Select which instance to give using the base + * address of registers + */ + switch((intptr_t)obj->i2c) { + case I2C0_BASE: + return &data0; + case I2C1_BASE: + return &data1; + default: + error("i2c driver private data structure not found for this registers base address"); + return (void*)0; + } +} + +/* + * Infer the current state of a possibly combined transfer + * (repeated restart) from the current state and the "stop" parameter + * of read and write functions + * MUST be called ONCE AND ONLY ONCE at the beginning of i2c transfer + * functions (read and write) + */ +static i2c_transfer_state_t update_transfer_state(i2c_t *obj, int stop) { + private_i2c_t* private_data = get_i2c_private(obj); + i2c_transfer_state_t *state = &private_data->transfer_state; + + /* + * Choose the current and next state depending on the current state + * This basically implements rising and falling edge detection on + * "stop" variable + */ + switch(*state) { + /* This is the default state for non restarted repeat transfer */ + default: + case I2C_TRANSFER_SINGLE: /* Not a combined transfer */ + if (stop) { + *state = I2C_TRANSFER_SINGLE; + } else { + *state = I2C_TRANSFER_COMBINED_FIRST_MESSAGE; + } + break; + + /* First message of a combined transfer */ + case I2C_TRANSFER_COMBINED_FIRST_MESSAGE: + /* Message in the middle of a combined transfer */ + case I2C_TRANSFER_COMBINED_INTERMEDIATE_MESSAGE: + if (stop) { + *state = I2C_TRANSFER_COMBINED_LAST_MESSAGE; + } else { + *state = I2C_TRANSFER_COMBINED_INTERMEDIATE_MESSAGE; + } + break; + + /* Last message of a combined transfer */ + case I2C_TRANSFER_COMBINED_LAST_MESSAGE: + if (stop) { + *state = I2C_TRANSFER_SINGLE; + } else { + *state = I2C_TRANSFER_COMBINED_FIRST_MESSAGE; + } + break; + } + + return *state; +} + + +static const PinMap PinMap_I2C_SDA[] = { + {SHIELD_SDA, I2C_0, 0}, + {SENSOR_SDA, I2C_1, 0}, + {NC, NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {SHIELD_SCL, I2C_0, 0}, + {SENSOR_SCL, I2C_1, 0}, + {NC, NC, 0} +}; + +static void clear_isr(i2c_t *obj) { + /* + * Writing to the IRQ status register clears set bits. Therefore, to + * clear indiscriminately, just read the register and write it back. + */ + uint32_t reg = obj->i2c->IRQ_STATUS; + obj->i2c->IRQ_STATUS = reg; +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + /* Determine the I2C to use */ + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = (I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); + + if ((int)obj->i2c == NC) { + error("I2C pin mapping failed"); + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + /* + * Default configuration: + * - MS : Master mode + * - NEA : Normal (7-bit) addressing + * - ACKEN : Send ACKs when reading from slave + * - CLR_FIFO : Not a configuration bit => clears the FIFO + */ + uint32_t reg = I2C_CTRL_MS | \ + I2C_CTRL_NEA | \ + I2C_CTRL_ACKEN | \ + I2C_CTRL_CLR_FIFO; + + obj->i2c->CONTROL = reg; + + get_i2c_private(obj)->transfer_state = I2C_TRANSFER_SINGLE; + + i2c_frequency(obj, 100000); /* Default to 100kHz SCL frequency */ +} + +int i2c_start(i2c_t *obj) { + return 0; +} + +int i2c_stop(i2c_t *obj) { + /* Clear the hardware FIFO */ + obj->i2c->CONTROL |= I2C_CTRL_CLR_FIFO; + /* Clear the HOLD bit used for performing combined transfers */ + obj->i2c->CONTROL &= ~I2C_CTRL_HOLD; + /* Reset the transfer size (read and write) */ + obj->i2c->TRANSFER_SIZE = 0; + /* Clear interrupts */ + clear_isr(obj); + return 0; +} + +void i2c_frequency(i2c_t *obj, int hz) { + /* + * Divider is split in two halfs : A and B + * A is 2 bits wide and B is 6 bits wide + * The Fscl frequency (SCL clock) is calculated with the following + * equation: + * Fscl=SystemCoreClock/(22*(A+1)*(B+1)) + * Here, we only calculate the B divisor which already enables a + * wide enough range of values + */ + uint32_t divisor_a = 0; /* Could be changed if a wider range of hz + is needed */ + uint32_t divisor_b = (SystemCoreClock / (22.0 * hz)) - 1; + + /* Clamp the divisors to their maximal value */ + divisor_a = divisor_a > I2C_CTRL_DIVISOR_A_BIT_MASK ? + I2C_CTRL_DIVISOR_A_BIT_MASK : divisor_a; + divisor_b = divisor_b > I2C_CTRL_DIVISOR_B_BIT_MASK ? + I2C_CTRL_DIVISOR_B_BIT_MASK : divisor_b; + + uint8_t divisor_combinded = (divisor_a & I2C_CTRL_DIVISOR_A_BIT_MASK) + | (divisor_b & I2C_CTRL_DIVISOR_B_BIT_MASK); + + obj->i2c->CONTROL = (obj->i2c->CONTROL & ~I2C_CTRL_DIVISORS) + | (divisor_combinded << I2C_CTRL_DIVISOR_OFFSET); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int bytes_read = 0; + int length_backup = length; + char *data_backup = data; + obj->last_xfer_address = address; + i2c_transfer_state_t transfer_state = update_transfer_state(obj, stop); + + /* Try to write until it finally succeed or times out */ + int main_timeout = 10; + int retry = 0; + do { + main_timeout--; + + retry = 0; + bytes_read = 0; + length = length_backup; + data = data_backup; + + uint32_t reg = obj->i2c->CONTROL & 0xff7f; + reg |= I2C_CTRL_RW | \ + I2C_CTRL_CLR_FIFO; + /* + * Only touch the HOLD bit at the beginning of + * (possibly combined) transactions + */ + if(transfer_state == I2C_TRANSFER_COMBINED_FIRST_MESSAGE + || transfer_state == I2C_TRANSFER_SINGLE) { + + reg |= I2C_CTRL_HOLD; + } + obj->i2c->CONTROL = reg; + + /* Set the expected number of bytes to be received */ + if (length > I2C_TRANSFER_SIZE) { + error("I2C transfer size too big for the FIFO"); + } + obj->i2c->TRANSFER_SIZE = length & I2C_TRANSFER_SIZE; + + clear_isr(obj); + + /* + * Start the transaction by writing address. + * Discard the lower bit as it is automatically set + * by the controller based on I2C_CTRL_RW bit in CONTROL + * register + */ + obj->i2c->ADDRESS = (address & 0xFF) >> 1; + + if(transfer_state == I2C_TRANSFER_COMBINED_LAST_MESSAGE + || transfer_state == I2C_TRANSFER_SINGLE) { + + /* Clear the hold bit before reading the DATA register */ + obj->i2c->CONTROL &= ~I2C_CTRL_HOLD; + } + + /* Wait for completion of the address transfer */ + int completion_timeout = 1000; + while (completion_timeout) { + completion_timeout--; + + uint32_t irq_status = obj->i2c->IRQ_STATUS; + if (irq_status & I2C_IRQ_NACK + || irq_status & I2C_IRQ_ARB_LOST) { + + retry = 1; + break; + } + + if(irq_status & I2C_IRQ_COMP) { + break; + } + } + + /* If retry, jump to the beginning and try again */ + if (retry || !completion_timeout) { + retry = 1; + continue; + } + + clear_isr(obj); + + /* Read the data from the DATA register */ + completion_timeout = 1000; + while (length && completion_timeout) { + completion_timeout--; + + uint32_t irq_status = obj->i2c->IRQ_STATUS; + uint32_t status = obj->i2c->STATUS; + + if(irq_status & I2C_IRQ_NACK || + irq_status & I2C_IRQ_ARB_LOST) { + + retry = 1; + break; + } + + /* + * Just wait for RXDV because COMP is only risen at the end + * of the transfer + */ + if (status & I2C_STATUS_RXDV) { + *data++ = obj->i2c->DATA & 0xFF; + length--; + bytes_read++; + } + + if (irq_status & I2C_IRQ_RX_UNF) { + error("Reading more bytes than the I2C transfer size"); + retry = 1; + break; + } + } + + /* If retry, jump to the beginning and try again */ + if (retry || !completion_timeout) { + retry = 1; + continue; + } + } while(retry && main_timeout); + + if (!main_timeout) { + bytes_read = 0; + data = data_backup; + } + + obj->i2c->CONTROL |= I2C_CTRL_CLR_FIFO; + clear_isr(obj); + return bytes_read; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, + int stop) { + + int bytes_written = 0; + int length_backup = length; + const char *data_backup = data; + obj->last_xfer_address = address; + i2c_transfer_state_t transfer_state = update_transfer_state(obj, stop); + + /* Try to write until it finally succeed or times out */ + int main_timeout = 10; + int retry = 0; + do { + main_timeout--; + + retry = 0; + bytes_written = 0; + length = length_backup; + data = data_backup; + + /* Read the defined bits in the control register */ + uint32_t reg = obj->i2c->CONTROL & 0xff7f; + reg |= I2C_CTRL_CLR_FIFO; + reg &= ~I2C_CTRL_RW; + + /* + * Only touch the HOLD bit at the beginning of + * (possibly combined) transactions + */ + if(transfer_state == I2C_TRANSFER_COMBINED_FIRST_MESSAGE + || transfer_state == I2C_TRANSFER_SINGLE) { + + reg |= I2C_CTRL_HOLD; + } + obj->i2c->CONTROL = reg; + + clear_isr(obj); + + /* Set the expected number of bytes to be transmitted */ + if (length > I2C_TRANSFER_SIZE) { + error("I2C transfer size too big for the FIFO"); + } + + /* Set the expected number of bytes to be transmitted */ + obj->i2c->TRANSFER_SIZE = length & I2C_TRANSFER_SIZE; + + /* + * Write the address, triggering the start of the transfer + * Discard the lower bit as it is automatically set + * by the controller based on I2C_CTRL_RW bit in CONTROL + * register + */ + obj->i2c->ADDRESS = (address & 0xFF) >> 1; + + /* Send the data bytes */ + int write_timeout = 1000 + length; + while (length && write_timeout) { + write_timeout--; + uint32_t irq_status = obj->i2c->IRQ_STATUS; + /* If overflow, undo last step */ + if (irq_status & I2C_IRQ_TX_OVF) { + *data--; + length++; + bytes_written--; + /* Clear the bit by writing 1 to it */ + obj->i2c->IRQ_STATUS |= I2C_IRQ_TX_OVF; + } + + if (irq_status & I2C_IRQ_NACK + || irq_status & I2C_IRQ_ARB_LOST) { + + retry = 1; + break; + } + + obj->i2c->DATA = *data++; + length--; + bytes_written++; + } + + /* If retry, jump to the beginning and try again */ + if (retry || !write_timeout) { + retry = 1; + continue; + } + + if(transfer_state == I2C_TRANSFER_COMBINED_LAST_MESSAGE + || transfer_state == I2C_TRANSFER_SINGLE) { + /* + * Clear the hold bit to signify the end + * of the write sequence + */ + obj->i2c->CONTROL &= ~I2C_CTRL_HOLD; + } + + + /* Wait for transfer completion */ + int completion_timeout = 1000; + while (completion_timeout) { + completion_timeout--; + + uint32_t irq_status = obj->i2c->IRQ_STATUS; + if(irq_status & I2C_IRQ_NACK + || irq_status & I2C_IRQ_ARB_LOST) { + retry = 1; + break; + } + if(irq_status & I2C_IRQ_COMP) { + break; + } + } + + /* If retry, jump to the beginning and try again */ + if (retry || !completion_timeout) { + continue; + } + + obj->i2c->CONTROL |= I2C_CTRL_CLR_FIFO; + clear_isr(obj); + } while(retry && main_timeout); + + return bytes_written; +} + +void i2c_reset(i2c_t *obj) { + i2c_stop(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) { + char i2c_ret = 0; + i2c_read(obj, obj->last_xfer_address, &i2c_ret, 1, last); + return i2c_ret; +} + +int i2c_byte_write(i2c_t *obj, int data) { + /* Store the number of written bytes */ + uint32_t wb = i2c_write(obj, obj->last_xfer_address, (char*)&data, 1, 0); + if (wb == 1) + return 1; + else + return 0; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) { +} + +int i2c_slave_receive(i2c_t *obj) { + return 0; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) { + return 0; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + return 0; +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { +} diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_def.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_def.h new file mode 100644 index 00000000000..b1b458d0b6d --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/i2c_def.h @@ -0,0 +1,101 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * I2C interface Support + * ===================== + */ + +#ifndef MBED_I2C_DEF_H +#define MBED_I2C_DEF_H + +#include /* standard types definitions */ + +typedef struct beetle_i2c +{ + __IO uint32_t CONTROL; /* RW Control register */ + __I uint32_t STATUS; /* RO Status register */ + __IO uint32_t ADDRESS; /* RW I2C address register */ + __IO uint32_t DATA; /* RW I2C data register */ + __IO uint32_t IRQ_STATUS; /* RO Interrupt status register ( read only but write to clear bits) */ + __IO uint32_t TRANSFER_SIZE; /* RW Transfer size register */ + __IO uint32_t SLAVE_MONITOR; /* RW Slave monitor pause register */ + __IO uint32_t TIMEOUT; /* RW Time out register */ + __I uint32_t IRQ_MASK; /* RO Interrupt mask register */ + __O uint32_t IRQ_ENABLE; /* WO Interrupt enable register */ + __O uint32_t IRQ_DISABLE; /* WO Interrupt disable register */ + +}I2C_TypeDef; + +#define I2C0_BASE (0x40007000ul) /* Shield Header I2C Base Address */ +#define I2C1_BASE (0x4000E000ul) /* Onboard I2C Base Address */ + +#define SHIELD_I2C ((I2C_TypeDef *) I2C0_BASE ) +#define BOARD_I2C ((I2C_TypeDef *) I2C1_BASE ) + +/* Control Register Masks */ +#define I2C_CTRL_RW 0x0001 /* Transfer direction */ +#define I2C_CTRL_MS 0x0002 /* Mode (master / slave) */ +#define I2C_CTRL_NEA 0x0004 /* Addressing mode */ +#define I2C_CTRL_ACKEN 0x0008 /* ACK enable */ +#define I2C_CTRL_HOLD 0x0010 /* Clock hold enable */ +#define I2C_SLVMON 0x0020 /* Slave monitor mode */ +#define I2C_CTRL_CLR_FIFO 0x0040 /* Force clear of FIFO */ +#define I2C_CTRL_DIVISOR_B 0x3F00 /* Stage B clock divider */ +#define I2C_CTRL_DIVISOR_A 0xA000 /* Stage A clock divider */ +#define I2C_CTRL_DIVISORS 0xFF00 /* Combined A and B fields */ +#define I2C_CTRL_DIVISOR_OFFSET 8 /* Offset of the clock divisor in + * the CONTROL register + */ +#define I2C_CTRL_DIVISOR_A_BIT_MASK 0x03 + /* + * First part of the clock + * divisor in the CONTROL register + */ +#define I2C_CTRL_DIVISOR_B_BIT_MASK 0x3F + /* + * Second part of the clock + * divisor in the CONTROL register + */ + +/* Status Register Masks */ +#define I2C_STATUS_RXRW 0x0008 /* Mode of transmission from master */ +#define I2C_STATUS_RXDV 0x0020 /* Valid data waiting to be read */ +#define I2C_STATUS_TXDV 0x0040 /* Still a data byte to be sent */ +#define I2C_STATUS_RXOVF 0x0080 /* Receiver overflow */ +#define I2C_STATUS_BA 0x0100 /* Bus active */ + +/* Address Register Masks */ +#define I2C_ADDRESS_7BIT 0x007F + +/* Interrupt Status / Enable / Disable Register Masks */ +#define I2C_IRQ_COMP 0x0001 /* Transfer complete */ +#define I2C_IRQ_DATA 0x0002 /* More data */ +#define I2C_IRQ_NACK 0x0004 /* Transfer not acknowledged */ +#define I2C_IRQ_TO 0x0008 /* Transfer timed out */ +#define I2C_IRQ_SLV_RDY 0x0010 /* Monitored slave ready */ +#define I2C_IRQ_RX_OVF 0x0020 /* Receive overflow */ +#define I2C_IRQ_TX_OVF 0x0040 /* Transmit overflow */ +#define I2C_IRQ_RX_UNF 0x0080 /* Receive underflow */ +#define I2C_IRQ_ARB_LOST 0x0200 /* Arbitration lost */ + +/* Transfer Size Register Masks */ +#define I2C_TRANSFER_SIZE 0xFF + +/* Error codes */ +#define E_SUCCESS 0x0 +#define E_INCOMPLETE_DATA 0x1 + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c new file mode 100644 index 00000000000..c5bdf7316c2 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/lp_ticker.c @@ -0,0 +1,135 @@ +/* + * PackageLicenseDeclared: Apache-2.0 + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" +#include "device.h" +#include "objects.h" +#include "lp_ticker_api.h" + +/* Private lp_ticker data */ +/* lp_ticker initialize */ +static uint32_t lp_ticker_initialized = 0; +/* lp_ticker reload value */ +static uint32_t lp_ticker_reload = 0x0; /* Max Value */ +/* Store Overflow Count */ +static uint32_t lp_ticker_overflows_count = 0; + +#if DEVICE_LOWPOWERTIMER +/** + * Interrupt Handler + */ +void __lp_ticker_irq_handler(void) +{ + if (DualTimer_GetIRQInfo(DUALTIMER0) == SINGLETIMER2) { + DualTimer_ClearInterrupt(DUALTIMER0); + lp_ticker_overflows_count++; + } else { + lp_ticker_irq_handler(); + } +} + +/** + * Initialize the low power ticker + */ +void lp_ticker_init(void) +{ + uint32_t lp_ticker_irqn = 0; + /* Verify if lp_ticker has been already Initialized */ + if (lp_ticker_initialized == 1) + { + return; + } + lp_ticker_initialized = 1; + + /* Dualtimer Initialize */ + DualTimer_Initialize(DUALTIMER0, lp_ticker_reload); + /* Dualtimer Enable */ + DualTimer_Enable(DUALTIMER0, DUALTIMER_COUNT_32 + //| DUALTIMER_PERIODIC + ); + /* DualTimer get IRQn */ + lp_ticker_irqn = DualTimer_GetIRQn(DUALTIMER0); + /* Enable lp_ticker IRQ */ + NVIC_SetVector((IRQn_Type)lp_ticker_irqn, + (uint32_t)__lp_ticker_irq_handler); + NVIC_EnableIRQ((IRQn_Type)lp_ticker_irqn); +} + +/** + * Read the current counter + * @return: The current timer's counter value in microseconds + */ +uint32_t lp_ticker_read(void) +{ + uint32_t microseconds = 0; + + /* Verify if lp_ticker has not been Initialized */ + if (lp_ticker_initialized == 0) + lp_ticker_init(); + + /* Read Timer Value */ + microseconds = DualTimer_Read_2(DUALTIMER0); + + return microseconds; +} + +/** + * Set interrupt for specified timestamp + * timestamp: The time in microseconds to be set + */ +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + int32_t delta = 0; + + /* Verify if lp_ticker has been not Initialized */ + if (lp_ticker_initialized == 0) + lp_ticker_init(); + + /* Calculate the delta */ + delta = (int32_t)(timestamp - lp_ticker_read()); + /* Check if the event was in the past */ + if (delta <= 0) { + /* This event was in the past */ + DualTimer_SetInterrupt_1(DUALTIMER0, 0, + DUALTIMER_COUNT_32 | DUALTIMER_ONESHOT); + return; + } + + /* Enable interrupt on SingleTimer1 */ + DualTimer_SetInterrupt_1(DUALTIMER0, delta, + DUALTIMER_COUNT_32 | DUALTIMER_ONESHOT); +} + +/** + * Disable low power ticker interrupt + */ +void lp_ticker_disable_interrupt(void) +{ + /* Disable Interrupt */ + DualTimer_DisableInterrupt(DUALTIMER0); +} + +/** + * Clear the low power ticker interrupt + */ +void lp_ticker_clear_interrupt(void) +{ + /* Clear Interrupt */ + DualTimer_ClearInterrupt(DUALTIMER0); +} + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/mbed_sdk_init.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/mbed_sdk_init.c new file mode 100644 index 00000000000..6c19d23f735 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/mbed_sdk_init.c @@ -0,0 +1,29 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis.h" + +void mbed_sdk_init(void) { + /* Beetle System Power Config */ + SystemPowerConfig(); + + /* Config EFlash Controller Clock */ + EFlash_Initialize(); + + /* Initialize Flash Cache */ + FCache_Initialize(); + FCache_Enable(1); + FCache_Invalidate(); +} diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/objects.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/objects.h new file mode 100644 index 00000000000..92be5a56a0d --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/objects.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "i2c_def.h" +#include "spi_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + uint32_t ch; +}; + +struct port_s { + __IO uint32_t *reg_dir; + __IO uint32_t *reg_dirclr; + __IO uint32_t *reg_out; + __IO uint32_t *reg_in; + PortName port; + uint32_t mask; +}; + +struct serial_s { + CMSDK_UART_TypeDef *uart; + int index; +}; + +struct i2c_s { + I2C_TypeDef *i2c; + uint16_t last_xfer_address; +}; + +struct spi_s { + SPI_TypeDef *spi; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint32_t pin_number; + __IO uint32_t address; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/pinmap.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/pinmap.c new file mode 100644 index 00000000000..f1e3f688560 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/pinmap.c @@ -0,0 +1,27 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +void pin_function(PinName pin, int function) { + MBED_ASSERT(pin != (PinName)NC); + +} + +void pin_mode(PinName pin, PinMode mode) { + MBED_ASSERT(pin != (PinName)NC); +} diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/port_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/port_api.c new file mode 100644 index 00000000000..ad71199cf2e --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/port_api.c @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" + +PinName port_pin(PortName port, int pin_n) { + return (PinName)((port << PORT_SHIFT) | pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + obj->port = port; + obj->mask = mask; + + CMSDK_GPIO_TypeDef *port_reg = + (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE + ((int)port * 0x10)); + + obj->reg_in = &port_reg->DATAOUT; + obj->reg_dir = &port_reg->OUTENABLESET; + obj->reg_dirclr = &port_reg->OUTENABLECLR; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<16; i++) { + if (obj->mask & (1<port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_in = value; +} + +int port_read(port_t *obj) { + return (*obj->reg_in); +} + diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/serial_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/serial_api.c new file mode 100644 index 00000000000..469d061e157 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/serial_api.c @@ -0,0 +1,330 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "PinNames.h" +#include "mbed_error.h" +#include "gpio_api.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ + +static const PinMap PinMap_UART_TX[] = { + {UART_TX0, UART_0, 0}, + {UART_TX1, UART_1, 0}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {UART_RX0, UART_0, 0}, + {UART_RX1, UART_1, 0}, + {NC, NC, 0} +}; + +#define UART_NUM 2 + +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +struct serial_global_data_s { + uint32_t serial_irq_id; + gpio_t sw_rts, sw_cts; + uint8_t count, rx_irq_set_flow, rx_irq_set_api; +}; + +static struct serial_global_data_s uart_data[UART_NUM]; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + // determine the UART to use + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + if ((int)uart == NC) { + error("Serial pinout mapping failed"); + } + + obj->uart = (CMSDK_UART_TypeDef *)uart; + //set baud rate and enable Uart in normarl mode (RX and TX enabled) + switch (uart) { + case UART_0: + { + CMSDK_UART0->CTRL = 0; // Disable UART when changing configuration + if ((int)tx != NC) { + CMSDK_UART0->CTRL = 0x1; // TX enable + } + if ((int)rx != NC) { + CMSDK_UART0->CTRL |= 0x2; // RX enable + } + } + break; + case UART_1: + { + CMSDK_UART1->CTRL = 0; // Disable UART when changing configuration + if((int)tx != NC) { + CMSDK_UART1->CTRL = 0x1; // TX enable + } + if((int)rx != NC) { + CMSDK_UART1->CTRL |= 0x2; // RX enable + } + } + break; + } + + // set default baud rate and format + serial_baud(obj, 9600); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + switch (uart) { + case UART_0: + obj->index = 0; + break; + case UART_1: + obj->index = 1; + break; + } + uart_data[obj->index].sw_rts.pin = NC; + uart_data[obj->index].sw_cts.pin = NC; + serial_set_flow_control(obj, FlowControlNone, NC, NC); + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + uart_data[obj->index].serial_irq_id = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + // BEETLE has a simple divider to control the baud rate. The formula is: + // + // Baudrate = PCLK / BAUDDIV + // + // PCLK = SystemCoreClock + // so for a desired baud rate of 9600 + // SystemCoreClock / 9600 + // + //check to see if minimum baud value entered + int baudrate_div = 0; + baudrate_div = SystemCoreClock / baudrate; + if (baudrate >= 16) { + switch ((int)obj->uart) { + case UART_0: + CMSDK_UART0->BAUDDIV = baudrate_div; + break; + case UART_1: + CMSDK_UART1->BAUDDIV = baudrate_div; + break; + default: + error("serial_baud"); + break; + } + } else { + error("serial_baud"); + } + +} + +void serial_format(serial_t *obj, int data_bits, + SerialParity parity, int stop_bits) { +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t intstatus, uint32_t index, + CMSDK_UART_TypeDef *puart) { + SerialIrq irq_type; + switch (intstatus) { + case 1: + { + irq_type = TxIrq; + } + break; + + case 2: + { + irq_type = RxIrq; + } + break; + + default: return; + } /* End of Switch */ + + if ((irq_type == RxIrq) && (NC != uart_data[index].sw_rts.pin)) { + gpio_write(&uart_data[index].sw_rts, 1); + // Disable interrupt if it wasn't enabled by other part of the application + if (!uart_data[index].rx_irq_set_api) { + // puart->CTRL &= ~(1 << RxIrq); + /* Disable Rx interrupt */ + puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk); + } + } + + if (uart_data[index].serial_irq_id != 0) { + if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) { + irq_handler(uart_data[index].serial_irq_id, irq_type); + } + } + + if( irq_type == TxIrq ) { + /* Clear the TX interrupt Flag */ + puart->INTCLEAR |= 0x01; + } else { + /* Clear the Rx interupt Flag */ + puart->INTCLEAR |= 0x02; + } +} + +void uart0_irq() { + uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, + (CMSDK_UART_TypeDef*)CMSDK_UART0); +} + +void uart1_irq() { + uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, + (CMSDK_UART_TypeDef*)CMSDK_UART1); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + uart_data[obj->index].serial_irq_id = id; +} + +static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { + /* Declare a variable of type IRQn, initialise to 0 */ + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + + /********************************************************************* + * BEETLE SOC BOARD * + *********************************************************************/ + case UART_0: + { + irq_n = UART0_IRQn; + vector = (uint32_t)&uart0_irq; + } + break; + case UART_1: + { + irq_n = UART1_IRQn; + vector = (uint32_t)&uart1_irq; + } + break; + } + + if (enable) { + if(irq == TxIrq) { + /* Transmit IRQ, set appripriate enable */ + + /* set TX interrupt enable in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; + } else { + /* set Rx interrupt on in CTRL REG */ + obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; + } + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + + } else if ((irq == TxIrq) || (uart_data[obj->index].rx_irq_set_api + + uart_data[obj->index].rx_irq_set_flow == 0)) { + /* Disable IRQ */ + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + + obj->uart->CTRL &= ~(1 << (irq + 2)); + + all_disabled = (obj->uart->CTRL & (1 << (other_irq + 2))) == 0; + + if (all_disabled) { + NVIC_DisableIRQ(irq_n); + } + } +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + if (RxIrq == irq) + uart_data[obj->index].rx_irq_set_api = enable; + serial_irq_set_internal(obj, irq, enable); +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + while (serial_readable(obj) == 0); + int data = obj->uart->DATA; + return data; +} + +void serial_putc(serial_t *obj, int c) { +#ifdef SERIAL_TEST + // Add CR to LF + if (c == 0x0A) { + while (serial_writable(obj)); + obj->uart->DATA = 0x0D; + } +#endif + + while (serial_writable(obj)); + obj->uart->DATA = c; +} + +int serial_readable(serial_t *obj) { + return obj->uart->STATE & 2; +} + +int serial_writable(serial_t *obj) { + return obj->uart->STATE & 1; +} + +void serial_clear(serial_t *obj) { + obj->uart->DATA = 0x00; +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { +} + +void serial_break_clear(serial_t *obj) { +} +void serial_set_flow_control(serial_t *obj, FlowControl type, + PinName rxflow, PinName txflow) { +} diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c new file mode 100644 index 00000000000..6bdf11c71b9 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c @@ -0,0 +1,271 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "spi_api.h" +#include "spi_def.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "wait_api.h" + +/* + * Driver private data structure that should not be shared by multiple + * instances of the driver (same driver for multiple instances of the IP) + */ +typedef struct { + uint32_t size; /* size of an SPI frame in bits: can be 8 or 16 */ +} private_spi_t; + +static const PinMap PinMap_SPI_SCLK[] = { + {SHIELD_SPI_SCK , SPI_0, 0}, + {ADC_SPI_SCK , SPI_1, 0}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {SHIELD_SPI_MOSI, SPI_0, 0}, + {ADC_SPI_MOSI, SPI_1, 0}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {SHIELD_SPI_MISO, SPI_0, 0}, + {ADC_SPI_MISO, SPI_1, 0}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {SHIELD_SPI_nCS, SPI_0, 0}, + {ADC_SPI_nCS, SPI_1, 0}, + {NC, NC, 0} +}; + +/* + * Retrieve the private data of the instance related to a given IP + */ +static private_spi_t* get_spi_private(spi_t *obj) { + static private_spi_t data0, data1; + /* + * Select which instance to give using the base + * address of registers + */ + switch ((intptr_t)obj->spi) { + case SPI0_BASE: + return &data0; + case SPI1_BASE: + return &data1; + default: + error("SPI driver private data structure not found for this registers base address"); + return (void*)0; + } +} + +void spi_init(spi_t *obj, PinName mosi, + PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = (SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl); + if ((int)obj->spi == NC) { + error("SPI pinout mapping failed"); + } + + /* Set default format and frequency */ + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode SPI_MSB, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode SPI_LSB, slave + } + spi_frequency(obj, 1562500); + + /* Pin out the spi pins */ + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + /* + * Set desired enabled IRQs: + * MF: Mode Fail + * TF: TX FIFO Full + * TNF: TX FIFO Not Full + * RNE: RX FIFO Not Empty + */ + uint32_t irqs = (IRQ_ENABLE_MFE | IRQ_ENABLE_TFE + | IRQ_ENABLE_TNFE | IRQ_ENABLE_RNEE); + + /* + * Enable: + * - Master mode + * - Manual start mode + * - Manual chip select + * - Peripheral select decode + */ + obj->spi->CONFIG |= (CONFIG_MSEL | CONFIG_MSE + /*| CONFIG_MCSE | CONFIG_PSD*/); + + /* Set all peripheral select lines high - these should be unused */ + obj->spi->CONFIG |= 0x00000; //CONFIG_PCSL; + + obj->spi->IRQ_ENABLE = irqs; + obj->spi->IRQ_DISABLE = ~irqs; + obj->spi->SPI_ENABLE |= SPI_ENABLE_SPIE; +} + +void spi_free(spi_t *obj) { +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + private_spi_t *private_spi = get_spi_private(obj); + + obj->spi->SPI_ENABLE &= ~SPI_ENABLE_SPIE; + + /* + * The mbed API specifies 'bits' as being 4-16 per frame. This + * controller supports only 8 or 16 bit frames. Therefore we will + * assume 8 bits and, if anything larger is specified, we will use + * 16 bits. + */ + obj->spi->CONFIG &= ~CONFIG_TWS; /* 00 = 8 bit frame */ + private_spi->size = 8; + + if (bits > 8) { + switch (bits) { + case 16: + private_spi->size = 16; + break; + default: + obj->spi->CONFIG |= CONFIG_TWS_1; /* 01 = 16 bit frame */ + break; + } + } + + switch (mode) { + default: + case 0: + obj->spi->CONFIG &= ~CONFIG_CPOL; + obj->spi->CONFIG &= ~CONFIG_CPHA; + break; + case 1: + obj->spi->CONFIG &= ~CONFIG_CPOL; + obj->spi->CONFIG |= CONFIG_CPHA; + break; + case 2: + obj->spi->CONFIG |= CONFIG_CPOL; + obj->spi->CONFIG &= ~CONFIG_CPHA; + break; + case 3: + obj->spi->CONFIG |= CONFIG_CPOL; + obj->spi->CONFIG |= CONFIG_CPHA; + break; + } + + obj->spi->SPI_ENABLE |= SPI_ENABLE_SPIE; +} + +void spi_frequency(spi_t *obj, int hz) { + /* + * Valid frequencies are derived from a 25MHz peripheral clock. + * Frequency | Divisor | MBRD Value | Hz + * 12.0 MHz 2 000 12000000 + * 6.0 MHz 4 001 6000000 + * 3.0 MHz 8 010 3000000 + * 1.5 MHz 16 011 1500000 + * 750.0 KHz 32 100 750000 + * 375.0 KHz 64 101 375000 + * 187.500 KHz 128 110 187500 + * 93.750 KHz 256 111 93750 + */ + int valid_frequencies[] = {12000000, 6000000, 3000000, 1500000, + 750000, 375000, 187500, 93750}; + uint16_t mbrd_value = 0; + uint32_t config = (obj->spi->CONFIG & ~CONFIG_MBRD); + + /* Store the index of the minimum supported frequency */ + uint32_t index = 7; + + for (int i = 0; i < 8; i++) { + if (hz >= valid_frequencies[i]) { + /* + * Store the index of the closest lower or equal supported + * frequency. + */ + index = i; + break; + } + + mbrd_value++; + } + + /* + * Set the selected frequency. If the frequency is below the minimum + * supported the driver sets the minumum. + */ + config |= index << CONFIG_MBRD_SHIFT; + + /* + * If the specified frequency didn't match any of the valid frequencies + * then leave CONFIG_MBRD to the closest lower frequency supported. + */ + obj->spi->CONFIG = config; +} + +int spi_master_write(spi_t *obj, int value) { + private_spi_t *private_spi = get_spi_private(obj); + + int data = 0; + if(private_spi->size == 16) { + obj->spi->TX_DATA = (uint8_t)((value >> 8) & TX_DATA_TDATA); + obj->spi->TX_DATA = (uint8_t)(value & TX_DATA_TDATA); + + /* Manually trigger start */ + obj->spi->CONFIG |= CONFIG_MSC; + + while(!(obj->spi->IRQ_STATUS & IRQ_STATUS_TNF)) + continue; + + data = (obj->spi->RX_DATA & RX_DATA_RDATA) << 8; + data = data | (obj->spi->RX_DATA & RX_DATA_RDATA); + } else { + + obj->spi->TX_DATA = (uint16_t)(value & TX_DATA_TDATA); + + /* Manually trigger start */ + obj->spi->CONFIG |= CONFIG_MSC; + + while(!(obj->spi->IRQ_STATUS & IRQ_STATUS_TNF)) + continue; + + data = obj->spi->RX_DATA & RX_DATA_RDATA; + } + + return data; +} + +uint8_t spi_get_module(spi_t *obj) { + return obj->spi->MID; +} + +int spi_busy(spi_t *obj) { + return 0; +} diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h new file mode 100644 index 00000000000..2555b32aec9 --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h @@ -0,0 +1,134 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * SSP interface Support + * ===================== + */ + +#ifndef MBED_SPI_DEF_H +#define MBED_SPI_DEF_H + +#include /* standard types definitions */ + +#define Module_ID 0x00090108 + +typedef struct beetle_spi +{ + __IO uint32_t CONFIG; /* 0x00 RW Configuration Register */ + __I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/ + __O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/ + __O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */ + __I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */ + __IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */ + __IO uint32_t DELAY; /* 0x18 RW Delay Register */ + __O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */ + __I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */ + __IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */ + __IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */ + __IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */ + uint32_t reserved[208]; + __I uint32_t MID; /* 0xFC RO Module ID Register */ +}SPI_TypeDef; + + +#define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */ +#define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */ + +#define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE ) +#define ADC_SPI ((SPI_TypeDef *) SPI1_BASE ) + +/* Configuration Register Bit Masks */ +#define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select +#define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge +#define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase +#define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256) +#define CONFIG_MBRD_0 0x00008 +#define CONFIG_MBRD_1 0x00010 +#define CONFIG_MBRD_2 0x00020 +#define CONFIG_MBRD_SHIFT 3 +#define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size +#define CONFIG_TWS_0 0x00000 +#define CONFIG_TWS_1 0x00040 +#define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select +#define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode +#define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only) +#define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable +#define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable +#define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command +#define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable +#define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable + +/* Interrupt Status Register Bit Masks */ +#define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow +#define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail +#define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status) +#define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status) +#define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status) +#define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status) +#define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow + +/* Interrupt Enable Register Bit Masks */ +#define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable +#define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable +#define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable +#define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable +#define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable +#define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable +#define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable + +/* Interrupt Disable Register Bit Masks */ +#define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable +#define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable +#define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable +#define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable +#define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable +#define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable +#define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable + +/* Interrupt Mask Register Bit Masks */ +#define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask +#define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask +#define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask +#define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask +#define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask +#define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask +#define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask + +/* SPI Enable Register Bit Masks */ +#define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable + +/* Delay Register Bit Masks */ +#define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init +#define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After +#define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between +#define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS + +/* Transmit Data Register Bit Masks */ +#define TX_DATA_TDATA 0xFF + +/* Receive Data Register Bit Masks */ +#define RX_DATA_RDATA 0xFF + +/* Slave Idle Count Register Bit Masks */ +#define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count + +/* TX Threshold Register Bit Masks */ +#define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold + +/* RX Threshold Register Bit Masks */ +#define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold + +#endif diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c new file mode 100644 index 00000000000..0afda94e2ca --- /dev/null +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c @@ -0,0 +1,94 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "us_ticker_api.h" +#include "PeripheralNames.h" +/* Private data */ +/* us_ticker reload value */ +static uint32_t us_ticker_reload = 0x0; /* Max Value */ +/* us ticker initialized */ +static uint32_t us_ticker_inited = 0; +/* us ticker overflow */ +static uint32_t us_ticker_overflow = 0; + +void __us_ticker_irq_handler(void) { + Timer_ClearInterrupt(TIMER1); + us_ticker_overflow++; +} + +void us_ticker_init(void) { + uint32_t us_ticker_irqn0 = 0; + uint32_t us_ticker_irqn1 = 0; + + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + /* Initialize Timer 0 */ + Timer_Initialize(TIMER0, us_ticker_reload); + /* Enable Timer 0 */ + Timer_Enable(TIMER0); + + /* Initialize Timer 1 */ + Timer_Initialize(TIMER1, us_ticker_reload); + /* Enable Timer 1 */ + Timer_Enable(TIMER1); + + /* Timer 0 get IRQn */ + us_ticker_irqn0 = Timer_GetIRQn(TIMER0); + NVIC_SetVector((IRQn_Type)us_ticker_irqn0, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ((IRQn_Type)us_ticker_irqn0); + + /* Timer 1 get IRQn */ + us_ticker_irqn1 = Timer_GetIRQn(TIMER1); + NVIC_SetVector((IRQn_Type)us_ticker_irqn1, (uint32_t)__us_ticker_irq_handler); + NVIC_EnableIRQ((IRQn_Type)us_ticker_irqn1); +} + +uint32_t us_ticker_read() { + uint32_t return_value = 0; + + if (!us_ticker_inited) + us_ticker_init(); + return_value = Timer_Read(TIMER1); + return return_value; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + int32_t delta = 0; + + if (!us_ticker_inited) + us_ticker_init(); + delta = (int32_t)(timestamp - us_ticker_read()); + /* Check if the event was in the past */ + if (delta <= 0) { + /* This event was in the past */ + Timer_SetInterrupt(TIMER0, 0); + return; + } + + /* If the event was not in the past enable interrupt */ + Timer_SetInterrupt(TIMER0, delta); +} + +void us_ticker_disable_interrupt(void) { + Timer_DisableInterrupt(TIMER0); +} + +void us_ticker_clear_interrupt(void) { + Timer_ClearInterrupt(TIMER0); +} From c1442139a0005293e92f599b322a3695fc6e18c9 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Wed, 11 May 2016 16:15:15 +0100 Subject: [PATCH 4/6] [BEETLE] Add support for uVision 5 exporter This patch adds support for uVision 5 exporter to the Beetle Target. Signed-off-by: Vincenzo Frascino --- hal/targets.json | 6 + .../uvision5_arm_beetle_soc.uvproj.tmpl | 430 ++++++++++++++++++ tools/export_test.py | 1 + 3 files changed, 437 insertions(+) create mode 100644 tools/export/uvision5_arm_beetle_soc.uvproj.tmpl diff --git a/hal/targets.json b/hal/targets.json index eccd116003f..fcf311d55a9 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -1539,6 +1539,12 @@ "default_toolchain": "ARM", "extra_labels": ["ARM_SSG", "BEETLE"], "macros": ["CMSDK_BEETLE", "WSF_MS_PER_TICK=20", "WSF_TOKEN_ENABLED=FALSE", "WSF_TRACE_ENABLED=TRUE", "WSF_ASSERT_ENABLED=FALSE", "WSF_PRINTF_MAX_LEN=128", "ASIC", "CONFIG_HOST_REV=0x20", "CONFIG_ALLOW_DEEP_SLEEP=FALSE", "HCI_VS_TARGET", "CONFIG_ALLOW_SETTING_WRITE=TRUE", "WSF_MAX_HANDLERS=20", "NO_LEDS"], + "progen": { + "target": "beetle", + "uvision5": { + "template": ["uvision5_arm_beetle_soc.uvproj.tmpl"] + } + }, "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI"] }, "RZ_A1H": { diff --git a/tools/export/uvision5_arm_beetle_soc.uvproj.tmpl b/tools/export/uvision5_arm_beetle_soc.uvproj.tmpl new file mode 100644 index 00000000000..d20e6399fbb --- /dev/null +++ b/tools/export/uvision5_arm_beetle_soc.uvproj.tmpl @@ -0,0 +1,430 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + ARM BEETLE SoC + 0x4 + ARM-ADS + + + ARMCM3 + ARM + IROM(0x00000000,0x40000) IRAM(0x20000200,0x1FE00) CPUTYPE("Cortex-M3") CLOCK(24000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + $K\ARM\ARMCC\bin\fromelf.exe --bin --output=.\build\@L.bin !L + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + + --gnu --no_rtti + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --entry=Reset_Handler + + + + + + + + + + + + + + + + + + + --c99 + + + + + + + + + + + + diff --git a/tools/export_test.py b/tools/export_test.py index fdb990c5416..aed64112979 100644 --- a/tools/export_test.py +++ b/tools/export_test.py @@ -161,6 +161,7 @@ def test_export(toolchain, target, expected_error=None): ('uvision', 'DISCO_F469NI'), ('uvision', 'DISCO_L476VG'), ('uvision', 'MOTE_L152RC'), + ('uvision', 'ARM_BEETLE_SOC'), ('lpcxpresso', 'LPC1768'), ('lpcxpresso', 'LPC4088'), From 4f61cfd7f68ea6c6075293e2d7b2367a1c439975 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Wed, 11 May 2016 16:44:31 +0100 Subject: [PATCH 5/6] [BEETLE] Add support for GCC ARM exporter This patch adds support for GCC ARM exporter to the Beetle Target. Signed-off-by: Vincenzo Frascino --- tools/export/gcc_arm_arm_beetle_soc.tmpl | 1 + tools/export/gccarm.py | 1 + tools/toolchains/gcc.py | 13 ++++++------- 3 files changed, 8 insertions(+), 7 deletions(-) create mode 100644 tools/export/gcc_arm_arm_beetle_soc.tmpl diff --git a/tools/export/gcc_arm_arm_beetle_soc.tmpl b/tools/export/gcc_arm_arm_beetle_soc.tmpl new file mode 100644 index 00000000000..6e616cc8842 --- /dev/null +++ b/tools/export/gcc_arm_arm_beetle_soc.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} diff --git a/tools/export/gccarm.py b/tools/export/gccarm.py index 18e67f55ad9..4df3fe55023 100644 --- a/tools/export/gccarm.py +++ b/tools/export/gccarm.py @@ -115,6 +115,7 @@ class GccArm(Exporter): 'SAMD21G18A', 'SAML21J18A', 'SAMG55J19', + 'ARM_BEETLE_SOC', ] DOT_IN_RELATIVE_PATH = True diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index eeba3d607e6..f8e252dc794 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -175,7 +175,7 @@ def compile(self, cc, source, object, includes): cmd.extend(self.get_dep_option(object)) cmd.extend(["-o", object, source]) - + # Call cmdline hook cmd = self.hook.get_cmdline_compiler(cmd) @@ -194,13 +194,13 @@ def link(self, output, objects, libraries, lib_dirs, mem_map): name, _ = splitext(basename(l)) libs.append("-l%s" % name[3:]) libs.extend(["-l%s" % l for l in self.sys_libs]) - + # Build linker command map_file = splitext(output)[0] + ".map" cmd = self.ld + ["-o", output, "-Wl,-Map=%s" % map_file] + objects + ["-Wl,--start-group"] + libs + ["-Wl,--end-group"] if mem_map: cmd.extend(['-T', mem_map]) - + for L in lib_dirs: cmd.extend(['-L', L]) cmd.extend(libs) @@ -215,7 +215,7 @@ def link(self, output, objects, libraries, lib_dirs, mem_map): cmd_list = [] for c in cmd[1:]: if c: - cmd_list.append(('"%s"' % c) if not c.startswith('-') else c) + cmd_list.append(('"%s"' % c) if not c.startswith('-') else c) string = " ".join(cmd_list).replace("\\", "/") f.write(string) @@ -228,7 +228,7 @@ def archive(self, objects, lib_path): with open(archive_files, "wb") as f: o_list = [] for o in objects: - o_list.append('"%s"' % o) + o_list.append('"%s"' % o) string = " ".join(o_list).replace("\\", "/") f.write(string) @@ -268,7 +268,7 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, self.cc += ["-DMBED_RTOS_SINGLE_THREAD"] self.cppc += ["-DMBED_RTOS_SINGLE_THREAD"] - if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: + if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368", "ARM_BEETLE_SOC"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) elif target.name in ["RZ_A1H", "VK_RZ_A1H", "ARCH_MAX", "DISCO_F407VG", "DISCO_F429ZI", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F410RB", "NUCLEO_F411RE", "NUCLEO_F446RE", "ELMO_F411RE", "MTS_MDOT_F411RE", "MTS_DRAGONFLY_F411RE", "DISCO_F746NG"]: self.ld.extend(["-u_printf_float", "-u_scanf_float"]) @@ -291,4 +291,3 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) self.ld += ["-nostdlib"] - From ce1c2c780ad7e5bce48ea957615cfe1fc8614532 Mon Sep 17 00:00:00 2001 From: Vincenzo Frascino Date: Thu, 2 Jun 2016 18:18:16 +0100 Subject: [PATCH 6/6] [BEETLE] Add LED Emulation The current version of MBED test environment requires LEDs to be present in the platform. Beetle HW does not provide any user programmable LEDs. This patch provides an emulation of the feature by using dummy PINs. Signed-off-by: Vincenzo Frascino --- .../TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h | 11 +++++----- .../TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c | 6 ++++++ .../TARGET_BEETLE/gpio_object.h | 20 ++++++++++++++----- 3 files changed, 27 insertions(+), 10 deletions(-) diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h index af03c749e87..14ce5d80705 100644 --- a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/PinNames.h @@ -126,13 +126,14 @@ typedef enum { SENSOR_SDA = 506, SENSOR_SCL = 507, + // Emulated LEDS + LED1 = 1001, + LED2 = 1002, + LED3 = 1003, + LED4 = 1004, + // Not connected NC = (int)0xFFFFFFFF, - // LEDS not connected - LED1 = NC, - LED2 = NC, - LED3 = NC, - LED4 = NC, } PinName; typedef enum { diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c index d8d40b0525b..065b185a529 100644 --- a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_api.c @@ -24,6 +24,9 @@ uint32_t gpio_set(PinName pin) { pin_value = pin; } else if (pin >= 16 && pin <= 31) { pin_value = pin-16; + } else if (pin >= 1001 && pin <= 1004) { + /* Emulated LEDs */ + return (1); } pin_function(pin, 0); @@ -44,6 +47,9 @@ void gpio_init(gpio_t *obj, PinName pin) { pin_value = pin; } else if (pin >= 16 && pin <= 31) { pin_value = pin-16; + } else if (pin >= 1001 && pin <= 1004) { + /* Emulated LEDs */ + return; } obj->mask = 0x1 << pin_value; diff --git a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h index a2c16ed3671..2d1f64d5650 100644 --- a/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h +++ b/hal/targets/hal/TARGET_ARM_SSG/TARGET_BEETLE/gpio_object.h @@ -37,15 +37,25 @@ typedef struct { } gpio_t; static inline void gpio_write(gpio_t *obj, int value) { - if (value == 1){ - *obj->reg_data |= (obj->mask); - } else if (value == 0){ - *obj->reg_data &= ~(obj->mask); + if (obj->pin < LED1 || obj->pin > LED4) { + if (value == 1) { + *obj->reg_data |= (obj->mask); + } else if (value == 0){ + *obj->reg_data &= ~(obj->mask); + } + } else { + /* Emulated LEDs return without taking any action */ + return; } } static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); + if (obj->pin < LED1 || obj->pin > LED4) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); + } else { + /* Emulated LEDs return OFF always */ + return 0; + } } #ifdef __cplusplus