From 1e2e14e11ddf01b1387962854ea94bce98086979 Mon Sep 17 00:00:00 2001 From: tomoyuki yamanaka Date: Fri, 3 Jun 2016 18:36:28 +0900 Subject: [PATCH 1/7] Implement SystemcoreClock We implemented SystemcoreClock which is defined in CMSIS. --- .../TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c | 15 +++++++++++++++ .../TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h | 2 ++ .../TARGET_VK_RZ_A1H/system_VKRZA1H.c | 15 +++++++++++++++ .../TARGET_VK_RZ_A1H/system_VKRZA1H.h | 2 ++ 4 files changed, 34 insertions(+) diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c index a07f8c4bc8e..71d93e76f6f 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c @@ -51,6 +51,7 @@ void FPUEnable(void); uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ /** @@ -198,6 +199,20 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) } } +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock. + */ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; +} + + /** * Initialize the system * diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h index 832e58bb915..bd7ba038091 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h @@ -43,6 +43,8 @@ extern "C" { #endif +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + typedef void(*IRQHandler)(); uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); uint32_t InterruptHandlerUnregister(IRQn_Type); diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c index 04bfbd0935f..d97ccae0694 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c @@ -51,6 +51,7 @@ void FPUEnable(void); uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ /** @@ -198,6 +199,20 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) } } +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock. + */ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; +} + + /** * Initialize the system * diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h index bc7637b39d6..f04b37b8a40 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h @@ -43,6 +43,8 @@ extern "C" { #endif +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + typedef void(*IRQHandler)(); uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); uint32_t InterruptHandlerUnregister(IRQn_Type); From 0a9e5fa3d60083146aa6b0adbf683fe3a0d72f13 Mon Sep 17 00:00:00 2001 From: tomoyuki yamanaka Date: Fri, 10 Jun 2016 16:13:35 +0900 Subject: [PATCH 2/7] Implement SystemCoreClockUpdate () function We changed to calculare the CPU Clock by the division ratio setting of from FRQCR register. --- .../TARGET_RZ_A1H/system_MBRZA1H.c | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c index 71d93e76f6f..d8db0843e1a 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c @@ -49,6 +49,12 @@ void FPUEnable(void); #endif +#define FRQCR_IFC_MSK (0x0030) +#define FRQCR_IFC_SHFT (8) +#define FRQCR_IFC_1P1 (0) /* x1/1 */ +#define FRQCR_IFC_2P3 (1) /* x2/3 */ +#define FRQCR_IFC_1P3 (3) /* x1/3 */ + uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ @@ -209,7 +215,22 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) */ void SystemCoreClockUpdate (void) { - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; + + switch (frqcr_ifc) { + case FRQCR_IFC_1P1: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + break; + case FRQCR_IFC_2P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; + break; + case FRQCR_IFC_1P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; + break; + default: + /* do nothing */ + break; + } } From 8f3e72f01c17bf8a4e2e561afe0115043891bdab Mon Sep 17 00:00:00 2001 From: tomoyuki yamanaka Date: Fri, 10 Jun 2016 16:16:06 +0900 Subject: [PATCH 3/7] Implement SystemCoreClockUpdate () function --- .../TARGET_VK_RZ_A1H/system_VKRZA1H.c | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c index d97ccae0694..8017e372a39 100644 --- a/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c +++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c @@ -49,6 +49,12 @@ void FPUEnable(void); #endif +#define FRQCR_IFC_MSK (0x0030) +#define FRQCR_IFC_SHFT (8) +#define FRQCR_IFC_1P1 (0) /* x1/1 */ +#define FRQCR_IFC_2P3 (1) /* x2/3 */ +#define FRQCR_IFC_1P3 (3) /* x1/3 */ + uint32_t IRQNestLevel; unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ @@ -209,7 +215,22 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq) */ void SystemCoreClockUpdate (void) { - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; + + switch (frqcr_ifc) { + case FRQCR_IFC_1P1: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; + break; + case FRQCR_IFC_2P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; + break; + case FRQCR_IFC_1P3: + SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; + break; + default: + /* do nothing */ + break; + } } From 3b2d75fcdac0983a02cb14450d2f4ecbf2069e27 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 13 Jun 2016 21:50:39 +0100 Subject: [PATCH 4/7] error - include interface header file to get mbed_error_vprinf() declaration --- hal/common/error.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hal/common/error.c b/hal/common/error.c index faa1622e31c..3b121934221 100644 --- a/hal/common/error.c +++ b/hal/common/error.c @@ -18,6 +18,7 @@ #include "device.h" #include "toolchain.h" #include "mbed_error.h" +#include "mbed_interface.h" #if DEVICE_STDIO_MESSAGES #include #endif From 81a7bdc4823e734980cc599d33028b778b40ac10 Mon Sep 17 00:00:00 2001 From: 0xc0170 Date: Mon, 13 Jun 2016 22:14:13 +0100 Subject: [PATCH 5/7] critical - fix __STDC_LIMIT_MACROS for armcc UINT32_MAX is defined only if __STDC_LIMIT_MACROS is provided prior including stdint.h --- hal/common/critical.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hal/common/critical.c b/hal/common/critical.c index 8705a88061e..735a8b65ab9 100644 --- a/hal/common/critical.c +++ b/hal/common/critical.c @@ -15,7 +15,7 @@ * limitations under the License. */ - +#define __STDC_LIMIT_MACROS #include #include #include "cmsis.h" From b8502c6d8456d632198aedd38b97704829c271ba Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Mon, 13 Jun 2016 23:33:28 +0100 Subject: [PATCH 6/7] Add missing EFM32 Pearl Gecko to README. --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 147cdcdc8ac..135070a9faf 100644 --- a/README.md +++ b/README.md @@ -95,6 +95,7 @@ Silicon Labs: * [EFM32 Leopard Gecko](https://developer.mbed.org/platforms/EFM32-Leopard-Gecko/) (Cortex-M3) * [EFM32 Giant Gecko](https://developer.mbed.org/platforms/EFM32-Giant-Gecko/) (Cortex-M3) * [EFM32 Wonder Gecko](https://developer.mbed.org/platforms/EFM32-Wonder-Gecko/) (Cortex-M4) +* [EFM32 Pearl Gecko](https://developer.mbed.org/platforms/EFM32-Pearl-Gecko/) (Cortex-M4) Atmel: * [SAM R21 XPRO](https://developer.mbed.org/platforms/SAMR21-XPRO/) (Cortex-M0+) From dcff9b15e70921e1f0931b5b999d9aa7b6ec011d Mon Sep 17 00:00:00 2001 From: Mihail Stoyanov Date: Tue, 14 Jun 2016 01:57:01 +0100 Subject: [PATCH 7/7] Minor update to tools - logging of tests and output --- tools/build_api.py | 2 -- tools/toolchains/__init__.py | 13 +++++++------ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/tools/build_api.py b/tools/build_api.py index f8b80991626..3904cd3bf3b 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -383,8 +383,6 @@ def build_library(src_paths, build_path, target, toolchain_name, if toolchain_output: cur_result["output"] += toolchain_output - cur_result["output"] += str(e) - add_result_to_report(report, cur_result) # Let Exception propagate diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index 777a2cd1745..464ad5d0635 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -241,8 +241,9 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, self.mp_pool = None - if 'UVISOR_PRESENT=1' in self.macros: + if 'UVISOR' in self.target.features and 'UVISOR_SUPPORTED' in self.target.extra_labels: self.target.core = re.sub(r"F$", '', self.target.core) + self.flags = deepcopy(self.DEFAULT_FLAGS) def get_output(self): @@ -253,9 +254,12 @@ def print_notify(self, event, silent=False): """ msg = None - if event['type'] in ['info', 'debug']: + if not self.VERBOSE and event['type'] == 'tool_error': msg = event['message'] - + + elif event['type'] in ['info', 'debug']: + msg = event['message'] + elif event['type'] == 'cc': event['severity'] = event['severity'].title() event['file'] = basename(event['file']) @@ -775,9 +779,6 @@ def link_program(self, r, tmp_path, name): def default_cmd(self, command): self.debug("Command: %s"% ' '.join(command)) _stdout, _stderr, _rc = run_cmd(command) - # Print all warning / erros from stderr to console output - for error_line in _stderr.splitlines(): - print error_line self.debug("Return: %s"% _rc)