From 3750f6eea97b8a7ed95ce68c83f0c8dd3028e23c Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Thu, 9 Jun 2016 23:25:18 +0200 Subject: [PATCH 01/12] rename feature to device_has in new target PR #1881 renamed option in targets.json - this commit is doing the same with the new target --- hal/targets.json | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hal/targets.json b/hal/targets.json index 35dd8fc898e..44569589832 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -789,6 +789,21 @@ "progen": {"target":"nucleo-l011k4"}, "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"] }, + "NUCLEO_F767ZI": { + "inherits": ["Target"], + "core": "Cortex-M7F", + "extra_labels": ["STM", "STM32F7", "STM32F767", "STM32F767ZI"], + "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], + "default_toolchain": "ARM", + "progen": { + "target": "nucleo-f767zi", + "uvision5": { + "template": ["uvision.uvproj.tmpl"] + } + }, + "detect_code": ["0799"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"] + }, "NUCLEO_L031K6": { "inherits": ["Target"], "core": "Cortex-M0", From c8c711f5664ab936011ae1cc9735f57ee55bbf7f Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Wed, 8 Jun 2016 16:53:45 +0200 Subject: [PATCH 02/12] rebase and adding ARM_STD config, all F7 use ARM as default toolchain - changing device.h -> targets.json after rebase - adding startup and config files for ARM_STD toolchain - changing all STM32F7xx targets to ARM as default toolchain (instead of uARM before) --- hal/targets.json | 2 + .../TOOLCHAIN_ARM_STD/startup_stm32f769xx.s | 479 ++++++++++++++++++ .../TOOLCHAIN_ARM_STD/stm32f767zi.sct | 45 ++ .../TOOLCHAIN_ARM_STD/sys.cpp | 56 ++ 4 files changed, 582 insertions(+) create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.s create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/stm32f767zi.sct create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/hal/targets.json b/hal/targets.json index 44569589832..362b64fded1 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -767,6 +767,7 @@ "core": "Cortex-M7F", "extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746ZG"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], + "default_toolchain": "ARM", "progen": { "target": "nucleo-f746zg", "iar": { @@ -983,6 +984,7 @@ "core": "Cortex-M7F", "extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746NG"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], + "default_toolchain": "ARM", "progen": {"target": "disco-f746ng"}, "detect_code": ["0815"], "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"] diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.s b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.s new file mode 100644 index 00000000000..8521c8b3242 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/startup_stm32f769xx.s @@ -0,0 +1,479 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f769xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 22-April-2016 +;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__initial_sp EQU 0x20080000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD DSI_IRQHandler ; DSI + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DSI_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SDMMC2_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +JPEG_IRQHandler +MDIOS_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/stm32f767zi.sct b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/stm32f767zi.sct new file mode 100644 index 00000000000..aaa6ed8f35e --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/stm32f767zi.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2016, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) +LR_IROM1 0x08000000 0x200000 { ; load region size_region + + ER_IROM1 0x08000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/sys.cpp b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..bb665909b98 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif From 19877e38e914a2c00e1c20f8617eb89ce3161386 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Tue, 7 Jun 2016 00:35:10 +0200 Subject: [PATCH 03/12] adding gccarm and uvision5 exporter --- .../TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s | 500 ++++++++++++++++++ .../TOOLCHAIN_ARM_MICRO/stm32f767zi.sct | 45 ++ .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 ++ tools/export/gccarm.py | 1 + .../export/gcc_arm_nucleo_f767zi.tmpl | 1 + 5 files changed, 603 insertions(+) create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/stm32f767zi.sct create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 workspace_tools/export/gcc_arm_nucleo_f767zi.tmpl diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s new file mode 100644 index 00000000000..1c591e6e56d --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s @@ -0,0 +1,500 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f769xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 22-April-2016 +;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20080000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD DSI_IRQHandler ; DSI + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DSI_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SDMMC2_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +JPEG_IRQHandler +MDIOS_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/stm32f767zi.sct b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/stm32f767zi.sct new file mode 100644 index 00000000000..aaa6ed8f35e --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/stm32f767zi.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2016, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) +LR_IROM1 0x08000000 0x200000 { ; load region size_region + + ER_IROM1 0x08000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/sys.cpp b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 00000000000..bb665909b98 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/export/gccarm.py b/tools/export/gccarm.py index 2388bb33c0a..d06ddcd5632 100644 --- a/tools/export/gccarm.py +++ b/tools/export/gccarm.py @@ -84,6 +84,7 @@ class GccArm(Exporter): 'NUCLEO_F303RE', 'NUCLEO_F334R8', 'NUCLEO_F746ZG', + 'NUCLEO_F767ZI', 'DISCO_L053C8', 'NUCLEO_L011K4', 'NUCLEO_L031K6', diff --git a/workspace_tools/export/gcc_arm_nucleo_f767zi.tmpl b/workspace_tools/export/gcc_arm_nucleo_f767zi.tmpl new file mode 100644 index 00000000000..6e616cc8842 --- /dev/null +++ b/workspace_tools/export/gcc_arm_nucleo_f767zi.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} From 810b4d015a417d7479f05c1c6ad97cad39df5e87 Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Thu, 2 Jun 2016 14:04:37 +0200 Subject: [PATCH 04/12] typo in target names for travis build --- tools/build_travis.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/build_travis.py b/tools/build_travis.py index 7f7d9b7ea37..d12fc926a0c 100644 --- a/tools/build_travis.py +++ b/tools/build_travis.py @@ -58,6 +58,8 @@ { "target": "NUCLEO_L031K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_L073RZ", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "NUCLEO_F446RE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_F746ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_F767ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "MOTE_L152RC", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, From e3365e8236f6fb7353261fd4486c33c17054ac89 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Thu, 2 Jun 2016 00:44:57 +0200 Subject: [PATCH 05/12] adding new target test results: Test summary: +--------+---------------+-----------+-------------+---------------------------------------+--------------------+---------------+-------+ | Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | Loops | +--------+---------------+-----------+-------------+---------------------------------------+--------------------+---------------+-------+ | OK | NUCLEO_F767ZI | GCC_ARM | DTCT_1 | Simple detect test | 0.53 | 10 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | EXAMPLE_1 | /dev/null | 5.78 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_10 | Hello World | 0.37 | 5 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_11 | Ticker Int | 11.39 | 15 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_12 | C++ | 1.41 | 10 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_16 | RTC | 4.57 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_2 | stdio | 0.79 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_23 | Ticker Int us | 11.37 | 15 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_24 | Timeout Int us | 11.41 | 15 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_25 | Time us | 11.4 | 15 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_26 | Integer constant division | 1.41 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_34 | Ticker Two callbacks | 11.41 | 15 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_37 | Serial NC RX | 10.9 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_38 | Serial NC TX | 15.38 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_A1 | Basic | 1.34 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_A21 | Call function before main (mbed_main) | 1.45 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_A9 | Serial Echo at 115200 | 6.5 | 20 | 1/1 | | OK | NUCLEO_F767ZI | GCC_ARM | MBED_BUSOUT | BusOut | 2.28 | 15 | 1/1 | +--------+---------------+-----------+-------------+---------------------------------------+--------------------+---------------+-------+ Result: 18 OK Completed in 174.85 sec --- hal/targets.json | 7 + .../TOOLCHAIN_GCC_ARM/STM32F767ZI.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s | 644 + .../TARGET_NUCLEO_F767ZI/cmsis.h | 38 + .../TARGET_NUCLEO_F767ZI/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F767ZI/cmsis_nvic.h | 54 + .../TARGET_NUCLEO_F767ZI/hal_tick.c | 140 + .../TARGET_NUCLEO_F767ZI/hal_tick.h | 62 + .../TARGET_NUCLEO_F767ZI/stm32f767xx.h | 10056 ++++++++++++++++ .../TARGET_NUCLEO_F767ZI/stm32f7xx.h | 216 + .../TARGET_NUCLEO_F767ZI/stm32f7xx_hal_conf.h | 454 + .../TARGET_NUCLEO_F767ZI/system_stm32f7xx.c | 852 ++ .../TARGET_NUCLEO_F767ZI/system_stm32f7xx.h | 126 + .../TARGET_NUCLEO_F767ZI/PeripheralNames.h | 99 + .../TARGET_NUCLEO_F767ZI/PeripheralPins.c | 328 + .../TARGET_NUCLEO_F767ZI/PinNames.h | 260 + .../TARGET_NUCLEO_F767ZI/PortNames.h | 54 + .../TARGET_NUCLEO_F767ZI/device.h | 72 + .../TARGET_NUCLEO_F767ZI/objects.h | 119 + 19 files changed, 13789 insertions(+) create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f767xx.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7xx.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7xx_hal_conf.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.h create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralNames.h create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralPins.c create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PinNames.h create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PortNames.h create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h diff --git a/hal/targets.json b/hal/targets.json index 362b64fded1..9ec83cb3ff2 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -805,6 +805,13 @@ "detect_code": ["0799"], "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"] }, + "NUCLEO_F767ZI": { + "inherits": ["Target"], + "core": "Cortex-M7F", + "extra_labels": ["STM", "STM32F7", "STM32F767", "STM32F767ZI"], + "supported_toolchains": ["GCC_ARM"], + "progen": { "target": "nucleo-f769zi"} + }, "NUCLEO_L031K6": { "inherits": ["Target"], "core": "Cortex-M0", diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld new file mode 100644 index 00000000000..ed431e6a49c --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (rwx) : ORIGIN = 0x200001F8, LENGTH = 320K - 0x1F8 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s new file mode 100644 index 00000000000..3cb97ec6334 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s @@ -0,0 +1,644 @@ +/** + ****************************************************************************** + * @file startup_stm32f769xx.s + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief STM32F769xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word DSI_IRQHandler /* DSI */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word JPEG_IRQHandler /* JPEG */ + .word MDIOS_IRQHandler /* MDIOS */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis.h new file mode 100644 index 00000000000..ee3ba9007b7 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f7xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.c new file mode 100644 index 00000000000..69a0fa58323 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.h new file mode 100644 index 00000000000..0a26d73682f --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 98 vectors = 392 bytes from 0x40 to 0x1C7 +// Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM +#define NVIC_NUM_VECTORS 114 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.c new file mode 100644 index 00000000000..e21ca156ae0 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.c @@ -0,0 +1,140 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +// 0=NO, 1=PG6 toggles at each tick +#define DEBUG_TICK 0 + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void HAL_IncTick(void); +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if DEBUG_TICK > 0 + HAL_GPIO_TogglePin(GPIOG, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + uint32_t PclkFreq; + + // Get clock configuration + // Note: PclkFreq contains here the Latency (not used after) + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq); + + // Get TIM5 clock value + PclkFreq = HAL_RCC_GetPCLK1Freq(); + + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + + // TIMxCLK = PCLKx when the APB prescaler = 1 else TIMxCLK = 2 * PCLKx + if (RCC_ClkInitStruct.APB1CLKDivider == RCC_HCLK_DIV1) + TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq) / 1000000) - 1; // 1 us tick + else + TimMasterHandle.Init.Prescaler = (uint16_t)((PclkFreq * 2) / 1000000) - 1; // 1 us tick + + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if DEBUG_TICK > 0 + __GPIOG_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.h new file mode 100644 index 00000000000..6501819b5d2 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/hal_tick.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f7xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f767xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f767xx.h new file mode 100644 index 00000000000..3976ab01769 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f767xx.h @@ -0,0 +1,10056 @@ +/** + ****************************************************************************** + * @file stm32f767xx.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f767xx + * @{ + */ + +#ifndef __STM32F767xx_H +#define __STM32F767xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F7xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */ + DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */ + DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */ + SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */ + CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */ + CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */ + CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */ + CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */ + JPEG_IRQn = 108, /*!< JPEG global Interrupt */ + MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ +#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ + + +#include "system_stm32f7xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ + +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */ + __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */ + __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */ + __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ + __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ + __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */ + __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ + uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ + __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ + __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ + __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ + __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ + __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ + __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ + __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ + __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ + __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ + __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ + __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ + __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ + __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ + __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ + __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ + __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ + __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ + __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ + __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ + __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ + __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ + __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ + __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ + __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ + __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ + __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ + __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ + __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ + __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ + __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ + __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ + __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ + __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ + __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ + __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ + __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ + __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ + __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ + __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ + __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */ + __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */ + __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */ + __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */ + __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */ + __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */ + __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */ + __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */ + __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */ + __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */ + __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */ + __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */ + __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */ + __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */ + __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */ + __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */ + __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */ + __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */ + __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */ + __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */ + __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */ + __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */ + __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */ + __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */ + __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */ +} MDIOS_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x081FFFFFU /*!< FLASH end address */ + +/* Legacy define */ +#define FLASH_BASE FLASHAXI_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define CAN3_BASE (APB1PERIPH_BASE + 0x3400U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800U) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U) +#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U) +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ +#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100U) +#define ETH_PTP_BASE (ETH_BASE + 0x0700U) +#define ETH_DMA_BASE (ETH_BASE + 0x1000U) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) +#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000U + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U +#define USB_OTG_FS_PERIPH_BASE 0x50000000U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define CAN3 ((CAN_TypeDef *) CAN3_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD 0x00000001U /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx + * @{ + */ + +#ifndef __STM32F7xx_H +#define __STM32F7xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F7) +#define STM32F7 +#endif /* STM32F7 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \ + !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) + /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, + STM32F756NG Devices */ + /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, + STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */ + /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */ + /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, + STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */ +#define STM32F767xx /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, + STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */ + /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, + STM32F769NG, STM32F769NI Devices */ + /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */ + /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.1.0 + */ +#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F7_CMSIS_VERSION)) +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32F756xx) + #include "stm32f756xx.h" +#elif defined(STM32F746xx) + #include "stm32f746xx.h" +#elif defined(STM32F745xx) + #include "stm32f745xx.h" +#elif defined(STM32F765xx) + #include "stm32f765xx.h" +#elif defined(STM32F767xx) + #include "stm32f767xx.h" +#elif defined(STM32F769xx) + #include "stm32f769xx.h" +#elif defined(STM32F777xx) + #include "stm32f777xx.h" +#elif defined(STM32F779xx) + #include "stm32f779xx.h" +#else + #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/** + * @} + */ + +#ifdef USE_HAL_DRIVER + #include "stm32f7xx_hal_conf.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F7xx_H */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7xx_hal_conf.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7xx_hal_conf.h new file mode 100644 index 00000000000..358b3571254 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7xx_hal_conf.h @@ -0,0 +1,454 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_DFSDM_MODULE_ENABLED +#define HAL_DSI_MODULE_ENABLED +#define HAL_JPEG_MODULE_ENABLED +#define HAL_MDIOS_MODULE_ENABLED + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 200U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.c new file mode 100644 index 00000000000..9b3d57eecf0 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.c @@ -0,0 +1,852 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @version V1.0.2 + * @date 21-September-2015 + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails + * | (external 25MHz xtal) | (internal 16MHz clock) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 216 | 216 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 216 | 216 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 54 | 54 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 108 | 108 + *----------------------------------------------------------------------------- + * USB capable | YES | NO + * with 48 MHz precise clock | | + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" +#include "hal_tick.h" + +HAL_StatusTypeDef HAL_Init(void); + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STMicroelectronics EVAL/Discovery boards as data memory */ +/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define + need to be added in the project preprocessor to avoid SDRAM multiple configuration + (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */ +/* #define DATA_IN_ExtSRAM */ +/* #define DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock + HAL_Init(); + + // Enable CPU L1-Cache + SCB_EnableICache(); + SCB_EnableDCache(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f7xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0; +#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x55550545; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554145; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xFF800FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55400555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CC00CC; + GPIOG->AFR[1] = 0xC00000CC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x80220AAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0x80320FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x40110555; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x55550450; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00145555; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[4] = 0x00001091; + FMC_Bank1->BTCR[5] = 0x00110212; + FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E5; + FMC_Bank5_6->SDTR[0] = 0x01116361; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x000000F3; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#elif defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x50150005; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554005; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55400555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CC00CC; + GPIOG->AFR[1] = 0xC000000C; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x80020A0A; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0x80020A0A; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x40010505; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x55550450; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00145555; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E5; + FMC_Bank5_6->SDTR[0] = 0x01116361; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x000000F3; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#elif defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x55550545; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554145; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55000555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00200AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x00300FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00100555; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[4] = 0x00001091; + FMC_Bank1->BTCR[5] = 0x00110212; + FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; + +#endif /* DATA_IN_ExtSRAM */ + + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + // Output clock on MCO2 pin(PC9) for debugging purpose + // Can be visualized on CN8 connector pin 4 + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + // Enable power clock + __PWR_CLK_ENABLE(); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */ + } + // Warning: this configuration is for a 8 MHz xtal clock only + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + // Activate the OverDrive to reach the 216 MHz Frequency + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + return 0; // FAIL + } + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + // Enable CPU L1-Cache + SCB_EnableICache(); + SCB_EnableDCache(); + + // Enable power clock + __PWR_CLK_ENABLE(); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + // Activate the OverDrive to reach the 216 MHz Frequency + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + return 0; // FAIL + } + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.h new file mode 100644 index 00000000000..f452d4d8e5a --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/system_stm32f7xx.h @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F7XX_H +#define __SYSTEM_STM32F7XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F7xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F7xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F7XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralNames.h new file mode 100644 index 00000000000..819b12e8fc9 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralNames.h @@ -0,0 +1,99 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE +} UARTName; + +#define STDIO_UART_TX PD_8 +#define STDIO_UART_RX PD_9 +#define STDIO_UART UART_3 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE, + SPI_6 = (int)SPI6_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + I2C_4 = (int)I2C4_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralPins.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralPins.c new file mode 100644 index 00000000000..f128dd2320f --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PeripheralPins.c @@ -0,0 +1,328 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ============================================================================= +// Notes: +// * Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// * Only the pins that are placed on the Arduino connector are described. +// ============================================================================= + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - ARDUINO A0 + // {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 (used by ethernet) + // {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 (used by ethernet) + {PA_3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN2 + {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - ARDUINO D13 + {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO D12 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (JP6) - ARDUINO D11 + // {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (used by LED1) + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,10, 0)}, // ADC1_IN10 - ARDUINO A1 + // {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,11, 0)}, // ADC1_IN11 (used by ethernet) + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,13, 0)}, // ADC1_IN13 - ARDUINO A2 + // {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,14, 0)}, // ADC1_IN14 (used by ethernet) + // {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,15, 0)}, // ADC1_IN15 (used by ethernet) + + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 - ARDUINO A3 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,14, 0)}, // ADC3_IN14 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,15, 0)}, // ADC3_IN15 - ARDUINO A4 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - ARDUINO A5 + + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + // {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // (used by LED2) + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + // {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (used by us_ticker) + // {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 (used by ethernet) + // {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (used by ethernet & us_ticker) + // {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 (used by ethernet) + // {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (used by ethernet & us_ticker) + // {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 (used by ethernet) + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + // {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (used by us_ticker) + // {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + // {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + // {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + // {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (used by ethernet) + // {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (used by ethernet) + // {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (used by ethernet) + // {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet) + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (used by USB) + // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (used by USB) + // {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 (used by USB) + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + // {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (used by LED1) + // {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + // {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + // {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + // {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + // {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (used by LED2) + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (remove JP7 to use it) + // {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N (used by LED3) + // {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N (used by LED3) + // {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 (used by LED3) + // {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + // {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 + + // {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + // {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + // {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + // {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)}, // (used by ethernet) + // {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb) + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO_TX + + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D1 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + // {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // (used by ethernet) + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO A0 + // {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb) + // {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by LED2) + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + // {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO_RX + + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D0 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + // {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART2)}, // (used by ethernet) + // {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb) + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (used by LED3) + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // ARDUINO D9 + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // ARDUINO D6 + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by usb) + // {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART4)}, // (used by LED1) + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // (remove JP7 to use it) + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // ARDUINO D10 + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (remove JP6 to use it) + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + // {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by Ethernet) + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO A2 + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // ARDUINO D1 + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D12 + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + // {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + // {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by LED3) + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // ARDUINO D3 + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D13 + // {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by USB) + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + // {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (remove JP7 to use it) + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by Ethernet) + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + // {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + // {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D14 + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // ARDUINO D5 + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PinNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PinNames.h new file mode 100644 index 00000000000..4f5e0120ee4 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PinNames.h @@ -0,0 +1,260 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7))) + +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7) |\ + ((CHANNEL & 0x0F) << 11) |\ + ((INVERTED & 0x01) << 15))) + +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) + +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // Arduino connector namings + A0 = PA_3, + A1 = PC_0, + A2 = PC_3, + A3 = PF_3, + A4 = PF_5, + A5 = PF_10, + D0 = PG_9, + D1 = PG_14, + D2 = PF_15, + D3 = PE_13, + D4 = PF_14, + D5 = PE_11, + D6 = PE_9, + D7 = PF_13, + D8 = PF_12, + D9 = PD_15, + D10 = PD_14, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PB_0, // LD1 = GREEN + LED2 = PB_7, // Blue + LED3 = PB_14, // Red + LED4 = PB_0, + USER_BUTTON = PC_13, + SERIAL_TX = PD_8, // Virtual Com Port + SERIAL_RX = PD_9, // Virtual Com Port + USBTX = PD_8, // Virtual Com Port + USBRX = PD_9, // Virtual Com Port + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PortNames.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PortNames.h new file mode 100644 index 00000000000..e875a51cdc1 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PortNames.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7, + PortI = 8, // kept for compilation + PortJ = 9, // kept for compilation + PortK = 10 // kept for compilation +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h new file mode 100644 index 00000000000..aa30383f4d7 --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device.h @@ -0,0 +1,72 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 0 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h new file mode 100644 index 00000000000..b5beed24bab --- /dev/null +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +#if DEVICE_SERIAL_FC + uint32_t hw_flow_ctl; + PinName pin_rts; + PinName pin_cts; +#endif +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; + uint8_t channel; + uint8_t inverted; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif From eb3d8d2f1702e0c53cbde515764582f61c231c93 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Thu, 2 Jun 2016 00:07:27 +0200 Subject: [PATCH 06/12] update target specific files --- .../TARGET_DISCO_F746NG/stm32f746xx.h | 12433 ++++++++-------- .../TARGET_DISCO_F746NG/stm32f7xx.h | 45 +- .../TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h | 137 +- .../TARGET_DISCO_F746NG/system_stm32f7xx.c | 1 + .../TARGET_DISCO_F746NG/system_stm32f7xx.h | 11 +- .../TARGET_NUCLEO_F746ZG/stm32f746xx.h | 12433 ++++++++-------- .../TARGET_NUCLEO_F746ZG/stm32f7xx.h | 45 +- .../TARGET_NUCLEO_F746ZG/stm32f7xx_hal_conf.h | 137 +- .../TARGET_NUCLEO_F746ZG/system_stm32f7xx.c | 1 + .../TARGET_NUCLEO_F746ZG/system_stm32f7xx.h | 11 +- 10 files changed, 12676 insertions(+), 12578 deletions(-) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h index b84b4cf36ea..e6adc5d2386 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f746xx.h * @author MCD Application Team - * @version V1.0.2 - * @date 21-September-2015 - * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File. + * @version V1.1.0 + * @date 22-April-2016 + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -172,7 +172,7 @@ typedef enum CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ - SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ } IRQn_Type; /** @@ -182,7 +182,7 @@ typedef enum /** * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ -#define __CM7_REV 0x0001 /*!< Cortex-M7 revision r0p1 */ +#define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ @@ -617,7 +617,7 @@ typedef struct __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; @@ -1142,159 +1142,163 @@ typedef struct + /** @addtogroup Peripheral_memory_map * @{ */ -#define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */ -#define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */ -#define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ -#define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */ -#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */ -#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */ -#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ -#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ -#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ +#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x080FFFFFU /*!< FLASH end address */ /* Legacy define */ #define FLASH_BASE FLASHAXI_BASE /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define I2C4_BASE (APB1PERIPH_BASE + 0x6000) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define CEC_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800U) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) /*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) -#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) /*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) -#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ +#define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) #define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) +#define ETH_MMC_BASE (ETH_BASE + 0x0100U) +#define ETH_PTP_BASE (ETH_BASE + 0x0700U) +#define ETH_DMA_BASE (ETH_BASE + 0x1000U) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) /*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) /*!< FMC Bankx registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) -#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) +#define DBGMCU_BASE 0xE0042000U /*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) -#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) - -#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) -#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) -#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) -#define USB_OTG_HOST_BASE ((uint32_t )0x400) -#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) -#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) -#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) -#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) +#define USB_OTG_HS_PERIPH_BASE 0x40040000U +#define USB_OTG_FS_PERIPH_BASE 0x50000000U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U /** * @} @@ -1428,360 +1432,366 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*! Date: Thu, 2 Jun 2016 00:06:57 +0200 Subject: [PATCH 07/12] update Cube driver to v1.4.0 --- .../Release_Notes_stm32f7xx_hal.html | 204 +- .../TARGET_STM32F7/stm32_hal_legacy.h | 295 +- .../TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c | 50 +- .../TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h | 50 +- .../TARGET_STM32F7/stm32f7xx_hal_adc.c | 21 +- .../TARGET_STM32F7/stm32f7xx_hal_adc.h | 87 +- .../TARGET_STM32F7/stm32f7xx_hal_adc_ex.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_adc_ex.h | 28 +- .../TARGET_STM32F7/stm32f7xx_hal_can.c | 425 +- .../TARGET_STM32F7/stm32f7xx_hal_can.h | 130 +- .../TARGET_STM32F7/stm32f7xx_hal_cec.c | 899 +--- .../TARGET_STM32F7/stm32f7xx_hal_cec.h | 206 +- .../TARGET_STM32F7/stm32f7xx_hal_cortex.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_cortex.h | 144 +- .../TARGET_STM32F7/stm32f7xx_hal_crc.c | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_crc.h | 46 +- .../TARGET_STM32F7/stm32f7xx_hal_crc_ex.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_crc_ex.h | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_cryp.c | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_cryp.h | 78 +- .../TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c | 98 +- .../TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h | 20 +- .../TARGET_STM32F7/stm32f7xx_hal_dac.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_dac.h | 46 +- .../TARGET_STM32F7/stm32f7xx_hal_dac_ex.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_dac_ex.h | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_dcmi.c | 416 +- .../TARGET_STM32F7/stm32f7xx_hal_dcmi.h | 240 +- .../TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c | 165 +- .../TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h | 164 +- .../TARGET_STM32F7/stm32f7xx_hal_def.h | 18 +- .../TARGET_STM32F7/stm32f7xx_hal_dfsdm.c | 3018 ++++++++++++ .../TARGET_STM32F7/stm32f7xx_hal_dfsdm.h | 710 +++ .../TARGET_STM32F7/stm32f7xx_hal_dma.c | 1027 ++-- .../TARGET_STM32F7/stm32f7xx_hal_dma.h | 181 +- .../TARGET_STM32F7/stm32f7xx_hal_dma2d.c | 1537 ++++-- .../TARGET_STM32F7/stm32f7xx_hal_dma2d.h | 460 +- .../TARGET_STM32F7/stm32f7xx_hal_dma_ex.c | 257 +- .../TARGET_STM32F7/stm32f7xx_hal_dma_ex.h | 84 +- .../TARGET_STM32F7/stm32f7xx_hal_dsi.c | 2266 +++++++++ .../TARGET_STM32F7/stm32f7xx_hal_dsi.h | 1242 +++++ .../TARGET_STM32F7/stm32f7xx_hal_eth.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_eth.h | 842 ++-- .../TARGET_STM32F7/stm32f7xx_hal_flash.c | 14 +- .../TARGET_STM32F7/stm32f7xx_hal_flash.h | 59 +- .../TARGET_STM32F7/stm32f7xx_hal_flash_ex.c | 446 +- .../TARGET_STM32F7/stm32f7xx_hal_flash_ex.h | 309 +- .../TARGET_STM32F7/stm32f7xx_hal_gpio.c | 24 +- .../TARGET_STM32F7/stm32f7xx_hal_gpio.h | 82 +- .../TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h | 278 +- .../TARGET_STM32F7/stm32f7xx_hal_hash.c | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_hash.h | 32 +- .../TARGET_STM32F7/stm32f7xx_hal_hash_ex.c | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_hash_ex.h | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_hcd.c | 10 +- .../TARGET_STM32F7/stm32f7xx_hal_hcd.h | 28 +- .../TARGET_STM32F7/stm32f7xx_hal_i2c.c | 4276 ++++++++++------- .../TARGET_STM32F7/stm32f7xx_hal_i2c.h | 487 +- .../TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c | 195 +- .../TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h | 87 +- .../TARGET_STM32F7/stm32f7xx_hal_i2s.c | 14 +- .../TARGET_STM32F7/stm32f7xx_hal_i2s.h | 94 +- .../TARGET_STM32F7/stm32f7xx_hal_irda.c | 1862 +++---- .../TARGET_STM32F7/stm32f7xx_hal_irda.h | 158 +- .../TARGET_STM32F7/stm32f7xx_hal_irda_ex.h | 8 +- .../TARGET_STM32F7/stm32f7xx_hal_iwdg.c | 358 +- .../TARGET_STM32F7/stm32f7xx_hal_iwdg.h | 119 +- .../TARGET_STM32F7/stm32f7xx_hal_jpeg.c | 3403 +++++++++++++ .../TARGET_STM32F7/stm32f7xx_hal_jpeg.h | 581 +++ .../TARGET_STM32F7/stm32f7xx_hal_lptim.c | 34 +- .../TARGET_STM32F7/stm32f7xx_hal_lptim.h | 135 +- .../TARGET_STM32F7/stm32f7xx_hal_ltdc.c | 726 ++- .../TARGET_STM32F7/stm32f7xx_hal_ltdc.h | 95 +- .../TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.c | 164 + .../TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.h | 151 + .../TARGET_STM32F7/stm32f7xx_hal_mdios.c | 629 +++ .../TARGET_STM32F7/stm32f7xx_hal_mdios.h | 537 +++ .../TARGET_STM32F7/stm32f7xx_hal_nand.c | 533 +- .../TARGET_STM32F7/stm32f7xx_hal_nand.h | 67 +- .../TARGET_STM32F7/stm32f7xx_hal_nor.c | 98 +- .../TARGET_STM32F7/stm32f7xx_hal_nor.h | 50 +- .../TARGET_STM32F7/stm32f7xx_hal_pcd.c | 82 +- .../TARGET_STM32F7/stm32f7xx_hal_pcd.h | 54 +- .../TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c | 8 +- .../TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h | 12 +- .../TARGET_STM32F7/stm32f7xx_hal_pwr.c | 14 +- .../TARGET_STM32F7/stm32f7xx_hal_pwr.h | 36 +- .../TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c | 14 +- .../TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h | 8 +- .../TARGET_STM32F7/stm32f7xx_hal_qspi.c | 923 ++-- .../TARGET_STM32F7/stm32f7xx_hal_qspi.h | 101 +- .../TARGET_STM32F7/stm32f7xx_hal_rcc.c | 276 +- .../TARGET_STM32F7/stm32f7xx_hal_rcc.h | 325 +- .../TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c | 462 +- .../TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h | 868 +++- .../TARGET_STM32F7/stm32f7xx_hal_rng.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_rng.h | 16 +- .../TARGET_STM32F7/stm32f7xx_hal_rtc.c | 13 +- .../TARGET_STM32F7/stm32f7xx_hal_rtc.h | 143 +- .../TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h | 176 +- .../TARGET_STM32F7/stm32f7xx_hal_sai.c | 1399 +++--- .../TARGET_STM32F7/stm32f7xx_hal_sai.h | 611 ++- .../TARGET_STM32F7/stm32f7xx_hal_sai_ex.c | 146 +- .../TARGET_STM32F7/stm32f7xx_hal_sai_ex.h | 48 +- .../TARGET_STM32F7/stm32f7xx_hal_sd.c | 172 +- .../TARGET_STM32F7/stm32f7xx_hal_sd.h | 166 +- .../TARGET_STM32F7/stm32f7xx_hal_sdram.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_sdram.h | 18 +- .../TARGET_STM32F7/stm32f7xx_hal_smartcard.c | 724 +-- .../TARGET_STM32F7/stm32f7xx_hal_smartcard.h | 198 +- .../stm32f7xx_hal_smartcard_ex.c | 14 +- .../stm32f7xx_hal_smartcard_ex.h | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_spdifrx.c | 480 +- .../TARGET_STM32F7/stm32f7xx_hal_spdifrx.h | 70 +- .../TARGET_STM32F7/stm32f7xx_hal_spi.c | 1902 ++++---- .../TARGET_STM32F7/stm32f7xx_hal_spi.h | 134 +- .../TARGET_STM32F7/stm32f7xx_hal_sram.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_sram.h | 16 +- .../TARGET_STM32F7/stm32f7xx_hal_tim.c | 6 +- .../TARGET_STM32F7/stm32f7xx_hal_tim.h | 200 +- .../TARGET_STM32F7/stm32f7xx_hal_tim_ex.c | 97 +- .../TARGET_STM32F7/stm32f7xx_hal_tim_ex.h | 120 +- .../TARGET_STM32F7/stm32f7xx_hal_uart.c | 1641 ++++--- .../TARGET_STM32F7/stm32f7xx_hal_uart.h | 252 +- .../TARGET_STM32F7/stm32f7xx_hal_uart_ex.h | 42 +- .../TARGET_STM32F7/stm32f7xx_hal_usart.c | 655 ++- .../TARGET_STM32F7/stm32f7xx_hal_usart.h | 110 +- .../TARGET_STM32F7/stm32f7xx_hal_usart_ex.h | 8 +- .../TARGET_STM32F7/stm32f7xx_hal_wwdg.c | 407 +- .../TARGET_STM32F7/stm32f7xx_hal_wwdg.h | 258 +- .../TARGET_STM32F7/stm32f7xx_ll_fmc.c | 80 +- .../TARGET_STM32F7/stm32f7xx_ll_fmc.h | 192 +- .../TARGET_STM32F7/stm32f7xx_ll_sdmmc.c | 11 +- .../TARGET_STM32F7/stm32f7xx_ll_sdmmc.h | 38 +- .../TARGET_STM32F7/stm32f7xx_ll_usb.c | 6 +- .../TARGET_STM32F7/stm32f7xx_ll_usb.h | 120 +- 137 files changed, 31833 insertions(+), 13772 deletions(-) create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.h create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.c create mode 100644 hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.h diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html index d6aa6457e99..6d4487249b9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html @@ -664,7 +664,7 @@

Release Notes for STM32F7xx HAL Drivers

Copyright -2015 STMicroelectronics

+2016 STMicroelectronics

@@ -676,7 +676,207 @@

Update History

-

V1.0.4 / 09-December-2015

+

V1.1.0 / 22-April-2016

+

Main +Changes

  • Official release to add the support of STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx devices
  • General updates +to fix known defects and enhancements implementation
  • Add new HAL drivers for DFSDM, DSI, JPEG and MDIOS peripherals
  • Enhance HAL delay and timebase implementation
    • Add new +drivers stm32f7xx_hal_timebase_tim_template.c, stm32f7xx_hal_timebase_rtc_alarm_template.c and +stm32f7xx_hal_timebase_rtc_wakeup_template.c which override the native HAL time +base functions (defined as weak) to either use the TIM or the RTC as time base tick source. For +more details about the usage of these drivers, please refer to HAL\HAL_TimeBase +examples and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the +application code based on HAL V1.0.4
    • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C, QSPI (referenced as PPP here below) drivers
      • Add PPP error management during DMA process. This requires the following updates on user application:
        • Configure and enable +the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f7xx_it.c file, +PPP_IRQHandler() +function: add a call to +HAL_PPP_IRQHandler() function +
        • Add and customize +the Error Callback API: HAL_PPP_ErrorCallback()
+
    • HAL I2C (referenced as PPP here below) drivers: +
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in the DMA transfer process. This requires the following updates on user application:
        • Configure and enable +the PPP IRQ in HAL_PPP_MspInit() function
      +
        • In stm32f7xx_it.c file, +PPP_IRQHandler() +function: add a call to +HAL_PPP_IRQHandler() function
+
    • HAL IWDG driver: rework overall driver for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: rework overall driver for better implementation +
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), +HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs  +
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
    • HAL QSPI driver:  Enhance the DMA transmit process by using PPP TC interrupt instead of waiting on TC flag under DMA ISR. This requires the following updates on user application:
      • Configure and enable +the QSPI IRQ in HAL_QSPI_MspInit() function
      • In stm32f7xx_it.c file, QSPI_IRQHandler() +function: add a call to +HAL_QSPI_IRQHandler() function
+
    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive() +
      • Remove +HAL CEC receive interrupt process function HAL_CEC_Receive_IT() +and enable the "receive"  mode during the Init phase +
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
         +
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and +HAL_CEC_ChangeRxBuffer() +
      • Remove the 'InitiatorAddress' field from the CEC_InitTypeDef +structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function +
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function +
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to +CEC_InitTypeDef structure
  • HAL CAN update 
    • Add the support of CAN3
  • HAL CEC update
    • Overall driver rework with break of compatibility with HAL +V1.0.4
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
+
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase +
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and +HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' field from the CEC_InitTypeDef +structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to +CEC_InitTypeDef structure
+
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in +CEC_HandleTypeDef structure to provide the CEC +state +information related to Rx Operations
      • Rename "state" +field in CEC_HandleTypeDef structure to "gstate": CEC state information +related to global Handle management and Tx Operations +
      • Update CEC process +to manage the new CEC states. +
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC +state parameters (gState, rxState)
  • HAL DMA update 
    • Add +new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to +register/unregister the different callbacks identified by +the enum typedef HAL_DMA_CallbackIDTypeDef
    • Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context
      • The new registered Abort callback is called when DMA transfer abortion is completed
    • Add the check of +compatibility between FIFO threshold level and size of the memory burst in the +HAL_DMA_Init() API +
    • Add new Error Codes: +HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and +HAL_DMA_ERROR_NOT_SUPPORTED
    • Remove all DMA states +related to MEM0/MEM1 in HAL_DMA_StateTypeDef
  • HAL DMA2D update 
    • Update the +HAL_DMA2D_DeInit() function to: +
      • Abort transfer in case +of ongoing DMA2D transfer
      +
      • Reset DMA2D control +registers
    • Update +HAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer
    • Optimize +HAL_DMA2D_IRQHandler() by reading status registers only once +
    • Update +HAL_DMA2D_ProgramLineEvent() function to: +
      • Return HAL error state +in case of wrong line value
      +
      • Enable line interrupt +after setting the line watermark configuration
    • Add new HAL_DMA2D_CLUTLoad() and HAL_DMA2D_CLUTLoad_IT() +functions to start DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Abort() +function to abort the DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Suspend() +function to suspend the DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Resume() +function to resume the DMA2D CLUT loading
    • Add new DMA2D dead time +management:
      • HAL_DMA2D_EnableDeadTime() +function to enable DMA2D dead time feature
      • HAL_DMA2D_DisableDeadTime() +function to disable DMA2D dead time feature
      • HAL_DMA2D_ConfigDeadTime() +function to configure dead time
    • Update the name of +DMA2D Input/Output color mode defines to be more clear for user (DMA2D_INPUT_XXX +for input layers Colors, DMA2D_OUTPUT_XXX for output framebuffer +Colors)
+ +
  • HAL DCMI update 
    • Rename DCMI_DMAConvCplt +to DCMI_DMAXferCplt +
    • Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral +
    • Add new timeout +implementation based on cpu cycles for DCMI stop +
    • Add HAL_DCMI_Suspend() +function to suspend DCMI capture +
    • Add HAL_DCMI_Resume() +function to resume capture after DCMI suspend +
    • Update lock mechanism +for DCMI process +
    • Update HAL_DCMI_IRQHandler() function to: +
      • Add error management in +case DMA errors through XferAbortCallback() and +HAL_DMA_Abort_IT()
      +
      • Optimize code by using +direct register read
    • Move +the content of the stm32f7xx_hal_dcmi_ex.c/.h files to common driver +files (the extension files are kept empty for projects compatibility +reason)
  • HAL FLASH update 
    • Add the support of Dual BANK feature
    • Add __HAL_FLASH_CALC_BOOT_BASE_ADR() macro to calculate the FLASH Boot Base Adress
    • Move Flash total sector define to CMSIS header files
  • HAL FMC update
    • Update FMC_NORSRAM_Init() to remove the Burst access mode configuration
    • Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks
  • HAL HCD update
    • Update HCD_Port_IRQHandler() to be compliant with new Time base implementation
  • HAL +I2C update +
    • Add the support of I2C fast mode plus (FM+)
    • Update Polling management:
      • The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    +
    • Add the management of Abort service: Abort DMA transfer through interrupt
      • In the case of Master Abort IT transfer usage:
        • Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process
        • A new abort state is defined in the HAL_I2C_StateTypeDef structure
    +
    • Add the management of I2C peripheral errors, ACK +failure and STOP condition detection during DMA process. This requires the following updates +on user application:
      • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
      • In stm32f7xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
      • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
      • Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API
    • Add the support of I2C repeated start feature: +
      • With the following new APIs
      +
        • HAL_I2C_Master_Sequential_Transmit_IT() +
        • HAL_I2C_Master_Sequential_Receive_IT() +
        • HAL_I2C_Master_Abort_IT() +
        • HAL_I2C_Slave_Sequential_Transmit_IT() +
        • HAL_I2C_Slave_Sequential_Receive_IT() +
        • HAL_I2C_EnableListen_IT() +
        • HAL_I2C_DisableListen_IT()
      +
      • Add new user callbacks:
      +
        • HAL_I2C_ListenCpltCallback()
        • HAL_I2C_AddrCallback()
      +
    • Several +updates on HAL I2C driver to implement the new I2C state machine: +
      • Add new API to get the I2C mode: +HAL_I2C_GetMode() +
      • Update I2C process to +manage the new I2C states
    +
  • HAL IWDG update
    • Overall rework of the driver for a more efficient implementation
      • Remove the following APIs:
        • HAL_IWDG_Start()
        • HAL_IWDG_MspInit()
        • HAL_IWDG_GetState()
      • Update implementation:
        • HAL_IWDG_Init() : this function insures the configuration and the start of the IWDG counter
        • HAL_IWDG_Refresh() : this function insures the reload of the IWDG counter
      • Refer to the following example to identify the changes: IWDG_Example
  • HAL LPTIM update
    • Update HAL_LPTIM_TimeOut_Start_IT() and HAL_LPTIM_Counter_Start_IT( ) APIs +to configure WakeUp Timer EXTI interrupt to be able to wakeup MCU from low power +mode by pressing the EXTI line +
    • Update HAL_LPTIM_TimeOut_Stop_IT() and HAL_LPTIM_Counter_Stop_IT( ) APIs to +disable WakeUp Timer EXTI interrupt
  • HAL LTDC update
    • Update +HAL_LTDC_IRQHandler() to manage the case of reload interrupt
    • Add LTDC extension driver needed with DSI
    • Add HAL_LTDC_SetPitch() function for pitch reconfiguration
    • Add new callback API +HAL_LTDC_ReloadEventCallback() +
    • Add HAL_LTDC_Reload() +to configure LTDC reload feature +
    • Add new No Reload LTDC +variant APIs
       +
      • HAL_LTDC_ConfigLayer_NoReload() +to configure the LTDC Layer according to the specified without reloading +
      • HAL_LTDC_SetWindowSize_NoReload() +to set the LTDC window size without reloading +
      • HAL_LTDC_SetWindowPosition_NoReload() +to set the LTDC window position without reloading +
      • HAL_LTDC_SetPixelFormat_NoReload() +to reconfigure the pixel format without reloading +
      • HAL_LTDC_SetAlpha_NoReload() +to reconfigure the layer alpha value without reloading +
      • HAL_LTDC_SetAddress_NoReload() +to reconfigure the frame buffer Address without reloading +
      • HAL_LTDC_SetPitch_NoReload() +to reconfigure the pitch for specific cases +
      • HAL_LTDC_ConfigColorKeying_NoReload() +to configure the color keying without reloading +
      • HAL_LTDC_EnableColorKeying_NoReload() +to enable the color keying without reloading +
      • HAL_LTDC_DisableColorKeying_NoReload() +to disable the color keying without reloading +
      • HAL_LTDC_EnableCLUT_NoReload() +to enable the color lookup table without reloading +
      • HAL_LTDC_DisableCLUT_NoReload() +to disable the color lookup table without +reloading
      • Note: +Variant functions with “_NoReload” post fix allows to set the LTDC +configuration/settings without immediate reload. This is useful in case +when the program requires to modify several LTDC settings (on one or +both layers) then applying (reload) these settings in one shot by +calling the function “HAL_LTDC_Reload”
+
  • HAL NOR update
    • Update NOR_ADDR_SHIFT macro implementation
  • HAL PCD update
    • Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value
  • HAL QSPI update
    • Update to manage QSPI error management during DMA process
    • Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR
    • These two improvements require the following updates on user application:
      • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
      • In stm32f7xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
      • Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()
    • Add +the management of non-blocking transfer abort service: HAL_QSPI_Abort_IT(). In +this case the user must:
      • Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process
      • A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase
    • Polling management update:
      • The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative. 
    • Refer to the following examples, which describe the changes:
      • QSPI_ReadWrite_DMA
      • QSPI_MemoryMapped
      • QSPI_ExecuteInPlace
    • Add two new APIs for the QSPI fifo threshold: +
      • HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of +the QSPI +
      • HAL_QSPI_GetFifoThreshold(): give the current FIFO +threshold
      +
    • Fix wrong data size management in HAL_QSPI_Receive_DMA()
  • HAL RCC update
    • Update HAL_RCC_PeriphCLKConfig() function to adjust the SystemCoreClock
    • Optimize HAL_RCC_ClockConfig() function code
    • Optimize internal oscillators and PLL startup times
  • HAL RTC update 
    • Update HAL_RTC_GetTime() with proper 'SubSeconds' and 'SecondFraction' management
  • HAL SAI update 
    • Update SAI state in case of TIMEOUT error within the HAL_SAI_Transmit() / HAL_SAI_Receive() +
    • Update HAL_SAI_IRQHandler: +
      • Add error management in +case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT() +
      • Add error management in +case of IT
    • Move +SAI_BlockSynchroConfig() and SAI_GetInputClock() functions to +stm32f7xx_hal_sai.c/.h files (extension files are kept empty for +projects compatibility reason)
+
  • HAL SPDIFRX update
    • Overall driver update for wait on flag management optimization
  • HAL SPI update
    • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency
      • Polling mode: +
        • Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" +statement to check on RXNE/TXE flage while transferring +data
+
      •  Interrupt mode:
        • Minimize access on SPI registers +
      • All modes:
        • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
        • Update timeout management to check on global processes
        • Update error code management in all processes
    • Update DMA process: +
      • Add the management of SPI peripheral errors during DMA process. This requires the following updates in +the user application:
        • Configure and enable the SPI IRQ in HAL_SPI_MspInit() function
        • In stm32f7xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function
        • Add and customize the Error Callback API: HAL_SPI_ErrorCallback()
        • Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA
      +
  • HAL TIM update 
    • Update HAL_TIM_ConfigOCrefClear() function for proper configuration of the SMCR register
    • Add new function HAL_TIMEx_ConfigBreakInput() to configure the break input source
  • HAL UART, USART, SMARTCARD and IRDA (referenced as PPP here below) update +
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of PPP peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
  • HAL WWDG update 
    • Overall rework of the driver for more efficient implementation
      • Remove the following APIs:
        • HAL_WWDG_Start()
        • HAL_WWDG_Start_IT()
        • HAL_WWDG_MspDeInit()
        • HAL_WWDG_GetState()
      • Update implementation:
        • HAL_WWDG_Init()
          • A new parameter in the Init Structure: EWIMode
        • HAL_WWDG_MspInit()
        • HAL_WWDG_Refresh() 
          • This function insures the reload of the counter
          • The "counter" parameter has been removed
        • HAL_WWDG_IRQHandler()
        • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()
    • Refer to the following example to identify the changes: WWDG_Example

V1.0.4 / 09-December-2015

Main Changes

  • HAL Generic update
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h index cd4be443962..e7cb8812ccf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,6 +103,7 @@ #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY @@ -128,7 +129,6 @@ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ - #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 @@ -143,6 +143,62 @@ #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif /** * @} */ @@ -173,7 +229,7 @@ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000) +#define DAC_WAVE_NONE ((uint32_t)0x00000000U) #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE @@ -377,12 +433,13 @@ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ -#if defined(STM32F3) || defined(STM32F1) +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F3 */ +#endif /* STM32F0 || STM32F3 || STM32F1 */ +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 /** * @} */ @@ -423,6 +480,14 @@ #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif /** * @} */ @@ -479,6 +544,11 @@ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS @@ -542,6 +612,9 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif /** * @} */ @@ -637,7 +710,7 @@ */ - /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE @@ -655,7 +728,7 @@ * @} */ - /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE @@ -808,9 +881,9 @@ #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) -#define CAN_TXSTATUS_OK ((uint8_t)0x01) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) /** * @} @@ -829,21 +902,95 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100) -#define ETH_MMCRIR ((uint32_t)0x00000104) -#define ETH_MMCTIR ((uint32_t)0x00000108) -#define ETH_MMCRIMR ((uint32_t)0x0000010C) -#define ETH_MMCTIMR ((uint32_t)0x00000110) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) -#define ETH_MMCTGFCR ((uint32_t)0x00000168) -#define ETH_MMCRFCECR ((uint32_t)0x00000194) -#define ETH_MMCRFAECR ((uint32_t)0x00000198) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) +#define ETH_MMCCR ((uint32_t)0x00000100U) +#define ETH_MMCRIR ((uint32_t)0x00000104U) +#define ETH_MMCTIR ((uint32_t)0x00000108U) +#define ETH_MMCRIMR ((uint32_t)0x0000010CU) +#define ETH_MMCTIMR ((uint32_t)0x00000110U) +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) +#define ETH_MMCTGFCR ((uint32_t)0x00000168U) +#define ETH_MMCRFCECR ((uint32_t)0x00000194U) +#define ETH_MMCRFAECR ((uint32_t)0x00000198U) +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) + +#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ /** * @} */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4xx || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -901,7 +1048,10 @@ #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) /** @@ -926,8 +1076,10 @@ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) /** @@ -1028,7 +1180,7 @@ */ - /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ @@ -1403,10 +1555,28 @@ #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif /** * @} */ +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ @@ -2450,7 +2620,7 @@ #endif #if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif @@ -2564,6 +2734,34 @@ #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE + /** * @} */ @@ -2853,31 +3051,7 @@ #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) - -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) - -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) - -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) - -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTSTATE_ENABLE)) +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 /** * @} */ @@ -2917,14 +3091,15 @@ #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE #define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE - +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c index d9af98f0274..4048d4d0ecd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -68,11 +68,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.0.4 + * @brief STM32F7xx HAL Driver version number V1.1.0 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ @@ -89,7 +89,7 @@ /** @addtogroup HAL_Private_Variables * @{ */ -static __IO uint32_t uwTick; +__IO uint32_t uwTick; /** * @} */ @@ -242,7 +242,7 @@ __weak void HAL_MspDeInit(void) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + HAL_SYSTICK_Config(SystemCoreClock/1000); /*Configure the SysTick IRQ priority */ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); @@ -370,7 +370,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> 16); + return((DBGMCU->IDCODE) >> 16U); } /** @@ -485,6 +485,38 @@ void HAL_DisableFMCMemorySwapping(void) SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** +* @brief Enable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_EnableMemorySwappingBank(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} + +/** +* @brief Disable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_DisableMemorySwappingBank(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h index 2a8e66ae9d1..23a1881e5b4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f7xx_hal.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -57,6 +57,23 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) +#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT +/** + * @} + */ + +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ @@ -125,6 +142,29 @@ #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ }while(0); +/** + * @brief Return the memory boot mapping as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg @ref SYSCFG_MEM_BOOT_ADD0 + * @arg @ref SYSCFG_MEM_BOOT_ADD1 + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -168,6 +208,10 @@ void HAL_EnableCompensationCell(void); void HAL_DisableCompensationCell(void); void HAL_EnableFMCMemorySwapping(void); void HAL_DisableFMCMemorySwapping(void); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c index bd135363c8d..8f9028a5f6a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -164,7 +164,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -498,7 +498,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); /* Check if Multimode enabled */ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) @@ -789,7 +789,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); @@ -843,6 +843,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { + /* Disable ADC end of conversion interrupt for regular group */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, @@ -1084,7 +1087,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); @@ -1225,6 +1228,12 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief Error ADC callback. + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h index fd054faa2e8..35ae67cb7bd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -81,13 +81,14 @@ typedef struct This parameter can be a value of @ref ADC_Resolution */ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). - This parameter can be a value of @ref ADC_data_align */ + This parameter can be a value of @ref ADC_Data_Align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). - Scan direction is upward: from rank1 to rank 'n'. */ + Scan direction is upward: from rank1 to rank 'n'. + This parameter can be set to ENABLE or DISABLE */ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of @ref ADC_EOCSelection. Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. @@ -171,34 +172,34 @@ typedef struct * @brief HAL ADC state machine: ADC states definition (bitfields) */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, +#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, +#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */ /** @@ -232,11 +233,11 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, +#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking, enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ /** * @} */ @@ -245,7 +246,7 @@ typedef struct /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler * @{ */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000) +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U) #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) @@ -256,7 +257,7 @@ typedef struct /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases * @{ */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000) +#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U) #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) @@ -279,7 +280,7 @@ typedef struct /** @defgroup ADC_Resolution ADC Resolution * @{ */ -#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) @@ -290,7 +291,7 @@ typedef struct /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) @@ -305,7 +306,7 @@ typedef struct /* compatibility with other STM32 devices. */ -#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) @@ -327,10 +328,10 @@ typedef struct * @} */ -/** @defgroup ADC_data_align ADC Data Align +/** @defgroup ADC_Data_Align ADC Data Align * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} @@ -339,7 +340,7 @@ typedef struct /** @defgroup ADC_channels ADC Common Channels * @{ */ -#define ADC_CHANNEL_0 ((uint32_t)0x00000000) +#define ADC_CHANNEL_0 ((uint32_t)0x00000000U) #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) @@ -368,7 +369,7 @@ typedef struct /** @defgroup ADC_sampling_times ADC Sampling Times * @{ */ -#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000) +#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U) #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) @@ -383,9 +384,9 @@ typedef struct /** @defgroup ADC_EOCSelection ADC EOC Selection * @{ */ -#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000) -#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001) -#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */ +#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U) +#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U) +#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */ /** * @} */ @@ -408,7 +409,7 @@ typedef struct #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U) /** * @} */ @@ -440,9 +441,9 @@ typedef struct /** @defgroup ADC_channels_type ADC Channels Type * @{ */ -#define ADC_ALL_CHANNELS ((uint32_t)0x00000001) -#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */ -#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */ +#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U) +#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */ +#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */ /** * @} */ @@ -600,11 +601,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ -#define ADC_STAB_DELAY_US ((uint32_t) 3) +#define ADC_STAB_DELAY_US ((uint32_t) 3U) /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) +#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c index 1a2a16575da..4cb8ca8c5d4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -86,7 +86,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h index 12f0ac5efef..8b5c321c722 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -77,7 +77,7 @@ typedef struct This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Rank in the injected group sequencer - This parameter must be a value of @ref ADCEx_injected_channel_selection + This parameter must be a value of @ref ADCEx_injected_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles @@ -155,7 +155,7 @@ typedef struct /** @defgroup ADCEx_Common_mode ADC Common Mode * @{ */ -#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000) +#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U) #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) @@ -175,7 +175,7 @@ typedef struct /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode * @{ */ -#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */ +#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */ #define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ #define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ #define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ @@ -186,7 +186,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected * @{ */ -#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) @@ -197,7 +197,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U) #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0) #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1) #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) @@ -217,13 +217,13 @@ typedef struct * @} */ -/** @defgroup ADCEx_injected_channel_selection ADC Injected Channel Selection +/** @defgroup ADCEx_injected_rank ADC Injected Rank * @{ */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) +#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U) +#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U) +#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U) +#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U) /** * @} */ @@ -231,7 +231,7 @@ typedef struct /** @defgroup ADCEx_channels ADC Specific Channels * @{ */ -#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c index 54d73f58658..c60b11f11ac 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_can.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -18,7 +18,8 @@ ============================================================================== [..] (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 + and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 -@- In case you are using CAN2 only, you have to enable the CAN1 clock. (#) CAN pins configuration @@ -30,9 +31,13 @@ (#) Initialize and configure the CAN using HAL_CAN_Init() function. (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. (#) Receive a CAN frame using HAL_CAN_Receive() function. + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + *** Polling mode IO operation *** ================================= [..] @@ -73,7 +78,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -165,7 +170,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { - uint32_t InitStatus = 3; + uint32_t InitStatus = CAN_INITSTATUS_FAILED; uint32_t tickstart = 0; /* Check CAN handle */ @@ -222,11 +227,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) } /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_INITSTATUS_FAILED; - } - else + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { /* Set the time triggered communication mode */ if (hcan->Init.TTCM == ENABLE) @@ -293,32 +294,28 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) ((uint32_t)hcan->Init.SJW) | \ ((uint32_t)hcan->Init.BS1) | \ ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1); + ((uint32_t)hcan->Init.Prescaler - 1); /* Request leave initialisation */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { - InitStatus = CAN_INITSTATUS_FAILED; + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } } - else + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { InitStatus = CAN_INITSTATUS_SUCCESS; } @@ -357,6 +354,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { uint32_t filternbrbitpos = 0; + CAN_TypeDef *can_ip; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); @@ -367,84 +365,99 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; +#if defined (CAN3) + /* Check the CAN instance */ + if(hcan->Instance == CAN3) + { + can_ip = CAN3; + } + else + { + can_ip = CAN1; + } +#else + can_ip = CAN1; +#endif /* Initialisation mode for the filter */ - CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; + can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; /* Select the start slave bank */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); + can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filternbrbitpos; + can_ip->FA1R &= ~(uint32_t)filternbrbitpos; /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filternbrbitpos; + can_ip->FS1R &= ~(uint32_t)filternbrbitpos; /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { /* 32-bit scale for the filter */ - CAN1->FS1R |= filternbrbitpos; + can_ip->FS1R |= filternbrbitpos; + /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filternbrbitpos; + can_ip->FM1R &= ~(uint32_t)filternbrbitpos; } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filternbrbitpos; + can_ip->FM1R |= (uint32_t)filternbrbitpos; } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) { /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; + can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; } if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) { /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filternbrbitpos; + can_ip->FFA1R |= (uint32_t)filternbrbitpos; } /* Filter activation */ if (sFilterConfig->FilterActivation == ENABLE) { - CAN1->FA1R |= filternbrbitpos; + can_ip->FA1R |= filternbrbitpos; } /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); + /* Return function status */ return HAL_OK; } @@ -542,48 +555,46 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { - uint32_t transmitmailbox = 5; + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process locked */ + __HAL_LOCK(hcan); - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } - else - { - transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - } - - if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) - { + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (hcan->pTxMsg->IDE == CAN_ID_STD) @@ -601,8 +612,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) } /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ @@ -617,8 +628,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); /* Check End of transmission flag */ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) @@ -639,29 +650,23 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } + /* Process unlocked */ + __HAL_UNLOCK(hcan); + /* Return function status */ return HAL_OK; } else { /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); + hcan->State = HAL_CAN_STATE_ERROR; /* Return function status */ return HAL_ERROR; @@ -676,16 +681,16 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) */ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) { - uint32_t transmitmailbox = 5; - uint32_t tmp = 0; + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; /* Check the parameters */ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - tmp = hcan->State; - if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX)) + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) { /* Process Locked */ __HAL_LOCK(hcan); @@ -693,96 +698,84 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /* Select one empty transmit mailbox */ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { - transmitmailbox = 0; + transmitmailbox = CAN_TXMAILBOX_0; } else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) { - transmitmailbox = 1; + transmitmailbox = CAN_TXMAILBOX_1; } - else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + else { - transmitmailbox = 2; + transmitmailbox = CAN_TXMAILBOX_2; } - else + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) { - transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); } - - if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + else { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME); + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Enable Error warning, Error passive, Bus-off, + Last error and Error Interrupts */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - } + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } else { - return HAL_BUSY; + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; } return HAL_OK; @@ -878,19 +871,16 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } + /* Process unlocked */ + __HAL_UNLOCK(hcan); + /* Return function status */ return HAL_OK; } @@ -928,21 +918,14 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); - - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); - - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); - - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); - - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + + /* Enable Error warning, Error passive, Bus-off, + Last error and Error Interrupts */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -997,7 +980,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) return HAL_ERROR; } - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ @@ -1303,20 +1286,13 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) if(hcan->State == HAL_CAN_STATE_BUSY_TX) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); } if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) @@ -1391,20 +1367,13 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum if(hcan->State == HAL_CAN_STATE_BUSY_RX) { - /* Disable Error warning Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG); - - /* Disable Error passive Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV); - - /* Disable Bus-off Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF); - - /* Disable Last error code Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC); - - /* Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR); + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); } if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h index 9478ba84b8b..3fd25c5ccfd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_can.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,14 +64,14 @@ */ typedef enum { - HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ }HAL_CAN_StateTypeDef; @@ -248,16 +248,16 @@ typedef struct /** @defgroup HAL_CAN_Error_Code HAL CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */ -#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */ -#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */ -#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */ -#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR 0x10 /*!< Form error */ -#define HAL_CAN_ERROR_ACK 0x20 /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR 0x40 /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD 0x80 /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */ +#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */ +#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */ +#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */ +#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */ +#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */ /** * @} */ @@ -265,8 +265,8 @@ typedef struct /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */ /** * @} */ @@ -274,7 +274,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -285,7 +285,7 @@ typedef struct /** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -296,7 +296,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -319,7 +319,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -334,8 +334,8 @@ typedef struct /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ /** * @} */ @@ -343,8 +343,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ /** * @} */ @@ -352,8 +352,8 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ @@ -361,8 +361,8 @@ typedef struct /** @defgroup CAN_Identifier_Type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */ /** * @} */ @@ -370,8 +370,8 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */ /** * @} */ @@ -379,8 +379,8 @@ typedef struct /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ /** * @} */ @@ -394,37 +394,37 @@ typedef struct CAN_GetFlagStatus() function. */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_INAK ((uint32_t)0x00000100) /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI ((uint32_t)0x00000102) /*!< Error flag */ -#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ -#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */ +#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */ /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */ /** * @} */ @@ -459,9 +459,9 @@ typedef struct /** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition * @{ */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +#define CAN_TXMAILBOX_0 ((uint8_t)0x00U) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01U) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02U) /** * @} */ @@ -700,8 +700,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK ((uint32_t)0x000000FFU) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c index 94aab9c56c1..222eeb53b31 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cec.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -49,7 +49,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -94,9 +94,6 @@ /** @defgroup CEC_Private_Constants CEC Private Constants * @{ */ -#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \ - | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \ - | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN) /** * @} */ @@ -107,8 +104,6 @@ /** @defgroup CEC_Private_Functions CEC Private Functions * @{ */ -static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec); -static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); /** * @} */ @@ -150,11 +145,9 @@ static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) -{ - uint32_t tmpreg = 0x0; - +{ /* Check the CEC handle allocation */ - if(hcec == NULL) + if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL)) { return HAL_ERROR; } @@ -168,41 +161,50 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen)); assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen)); assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); - assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress)); assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); - assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); + assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress)); - - if(hcec->State == HAL_CEC_STATE_RESET) + if(hcec->gState == HAL_CEC_STATE_RESET) { /* Allocate lock resource and initialize it */ hcec->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ HAL_CEC_MspInit(hcec); } - - hcec->State = HAL_CEC_STATE_BUSY; + hcec->gState = HAL_CEC_STATE_BUSY; /* Disable the Peripheral */ __HAL_CEC_DISABLE(hcec); - tmpreg = hcec->Init.SignalFreeTime; - tmpreg |= hcec->Init.Tolerance; - tmpreg |= hcec->Init.BRERxStop; - tmpreg |= hcec->Init.BREErrorBitGen; - tmpreg |= hcec->Init.LBPEErrorBitGen; - tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen; - tmpreg |= hcec->Init.SignalFreeTimeOption; - tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS); - tmpreg |= hcec->Init.ListenMode; - /* Write to CEC Control Register */ - MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg); - - /* Enable the Peripheral */ + hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\ + hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\ + hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\ + hcec->Init.ListenMode; + + /* Enable the following CEC Transmission/Reception interrupts as + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); + + /* Enable the CEC Peripheral */ __HAL_CEC_ENABLE(hcec); - hcec->State = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->gState = HAL_CEC_STATE_READY; + hcec->RxState = HAL_CEC_STATE_READY; return HAL_OK; } @@ -223,15 +225,37 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) /* Check the parameters */ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); - hcec->State = HAL_CEC_STATE_BUSY; + hcec->gState = HAL_CEC_STATE_BUSY; /* DeInit the low level hardware */ HAL_CEC_MspDeInit(hcec); + /* Disable the Peripheral */ __HAL_CEC_DISABLE(hcec); + /* Clear Flags */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR); + + /* Disable the following CEC Transmission/Reception interrupts as + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); + hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->State = HAL_CEC_STATE_RESET; + hcec->gState = HAL_CEC_STATE_RESET; + hcec->RxState = HAL_CEC_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(hcec); @@ -239,6 +263,53 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) return HAL_OK; } +/** + * @brief Initializes the Own Address of the CEC device + * @param hcec: CEC handle + * @param CEC_OwnAddress: The CEC own address. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress)); + + if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcec); + + hcec->gState = HAL_CEC_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE) + { + hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16); + } + else + { + hcec->Instance->CFGR &= ~(CEC_CFGR_OAR); + } + + hcec->gState = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + /** * @brief CEC MSP Init * @param hcec: CEC handle @@ -283,293 +354,32 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) logical addresses (4-bit long addresses, 0xF for broadcast messages destination) - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) No-Blocking mode: The communication is performed using Interrupts. + (#) The communication is performed using Interrupts. These API's return the HAL status. The end of the data processing will be indicated through the dedicated CEC IRQ when using Interrupt mode. The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks will be executed respectively at the end of the transmit or Receive process - The HAL_CEC_ErrorCallback()user callback will be executed when a communication + The HAL_CEC_ErrorCallback() user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_CEC_Transmit() - (+) HAL_CEC_Receive() - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_CEC_Transmit_IT() - (+) HAL_CEC_Receive_IT() - (+) HAL_CEC_IRQHandler() - - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (+) HAL_CEC_TxCpltCallback() - (+) HAL_CEC_RxCpltCallback() - (+) HAL_CEC_ErrorCallback() + (#) API's with Interrupt are : + (+) HAL_CEC_Transmit_IT() + (+) HAL_CEC_IRQHandler() + + (#) A set of User Callbacks are provided: + (+) HAL_CEC_TxCpltCallback() + (+) HAL_CEC_RxCpltCallback() + (+) HAL_CEC_ErrorCallback() @endverbatim * @{ */ -/** - * @brief Send data in blocking mode - * @param hcec: CEC handle - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). - * 0 means only the header is sent (ping operation). - * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) -{ - uint8_t temp = 0; - uint32_t tempisr = 0; - uint32_t tickstart = 0; - - if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) - { - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - if((pData == NULL ) && (Size > 0)) - { - hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; - } - - assert_param(IS_CEC_ADDRESS(DestinationAddress)); - assert_param(IS_CEC_MSGSIZE(Size)); - - /* Process Locked */ - __HAL_LOCK(hcec); - - hcec->State = HAL_CEC_STATE_BUSY_TX; - - hcec->TxXferCount = Size; - - /* case no data to be sent, sender is only pinging the system */ - if (Size == 0) - { - /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - - /* send header block */ - temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; - hcec->Instance->TXDR = temp; - /* Set TX Start of Message (TXSOM) bit */ - __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - - while (hcec->TxXferCount > 0) - { - hcec->TxXferCount--; - - tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - - /* check whether error occurred while waiting for TXBR to be set: - * has Tx underrun occurred ? - * has Tx error occurred ? - * has Tx Missing Acknowledge error occurred ? - * has Arbitration Loss error occurred ? */ - tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = tempisr; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } - /* TXBR to clear BEFORE writing TXDR register */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); - if (hcec->TxXferCount == 0) - { - /* if last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - hcec->Instance->TXDR = *pData++; - - /* error check after TX byte write up */ - tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = tempisr; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } /* end while (while (hcec->TxXferCount > 0)) */ - - - /* if no error up to this point, check that transmission is - * complete, that is wait until TXEOM is reset */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - } - - /* Final error check once all bytes have been transmitted */ - tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = tempisr; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive data in blocking mode. Must be invoked when RXBR has been set. - * @param hcec: CEC handle - * @param pData: pointer to received data buffer. - * @param Timeout: Timeout duration. - * Note that the received data size is not known beforehand, the latter is known - * when the reception is complete and is stored in hcec->RxXferSize. - * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). - * If only a header is received, hcec->RxXferSize = 0 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0; - - if (hcec->State == HAL_CEC_STATE_READY) - { - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - if (pData == NULL ) - { - hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; - } - - hcec->RxXferSize = 0; - /* Process Locked */ - __HAL_LOCK(hcec); - - - /* Rx loop until CEC_ISR_RXEND is set */ - while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) - { - tickstart = HAL_GetTick(); - /* Wait for next byte to be received */ - while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_TIMEOUT; - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - /* any error so far ? - * has Rx Missing Acknowledge occurred ? - * has Rx Long Bit Period error occurred ? - * has Rx Short Bit Period error occurred ? - * has Rx Bit Rising error occurred ? - * has Rx Overrun error occurred ? */ - temp = (uint32_t) (hcec->Instance->ISR); - if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = temp; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */ - - - /* read received data */ - *pData++ = hcec->Instance->RXDR; - temp = (uint32_t) (hcec->Instance->ISR); - /* end of message ? */ - if ((temp & CEC_ISR_RXEND) != 0) - { - assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize)); - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_OK; - } - - /* clear Rx-Byte Received flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR); - /* increment payload byte counter */ - hcec->RxXferSize++; - } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */ - - /* if the instructions below are executed, it means RXEND was set when RXBR was - * set for the first time: - * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))" - * loop has not been executed and this means a single byte has been sent */ - *pData++ = hcec->Instance->RXDR; - /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ - hcec->RxXferSize = 0; - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - /** * @brief Send data in interrupt mode * @param hcec: CEC handle + * @param InitiatorAddress: Initiator address * @param DestinationAddress: destination logical address * @param pData: pointer to input byte data buffer * @param Size: amount of data to be sent in bytes (without counting the header). @@ -577,122 +387,47 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status */ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) { - uint8_t temp = 0; /* if the IP isn't already busy and if there is no previous transmission already pending due to arbitration lost */ - if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX)) - && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) + if (hcec->gState == HAL_CEC_STATE_READY) { if((pData == NULL ) && (Size > 0)) { - hcec->State = HAL_CEC_STATE_ERROR; return HAL_ERROR; } assert_param(IS_CEC_ADDRESS(DestinationAddress)); + assert_param(IS_CEC_ADDRESS(InitiatorAddress)); assert_param(IS_CEC_MSGSIZE(Size)); /* Process Locked */ __HAL_LOCK(hcec); hcec->pTxBuffPtr = pData; - hcec->State = HAL_CEC_STATE_BUSY_TX; + hcec->gState = HAL_CEC_STATE_BUSY_TX; hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Enable the following two CEC Transmission interrupts as - * well as the following CEC Transmission Errors interrupts: - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); /* initialize the number of bytes to send, * 0 means only one header is sent (ping operation) */ hcec->TxXferCount = Size; - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - /* in case of no payload (Size = 0), sender is only pinging the system; - * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ + Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ if (Size == 0) { __HAL_CEC_LAST_BYTE_TX_SET(hcec); } - /* send header block */ - temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; - hcec->Instance->TXDR = temp; + hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress); /* Set TX Start of Message (TXSOM) bit */ __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + return HAL_OK; - } - /* if the IP is already busy or if there is a previous transmission - already pending due to arbitration loss */ - else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) - || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) - { - __HAL_LOCK(hcec); - /* set state to BUSY TX, in case it wasn't set already (case - * of transmission new attempt after arbitration loss) */ - if (hcec->State != HAL_CEC_STATE_BUSY_TX) - { - hcec->State = HAL_CEC_STATE_BUSY_TX; - } - /* if all data have been sent */ - if(hcec->TxXferCount == 0) - { - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); - /* Disable the CEC Transmission Error Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); - - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND); - - hcec->State = HAL_CEC_STATE_READY; - /* Call the Process Unlocked before calling the Tx call back API to give the possibility to - start again the Transmission under the Tx call back API */ - __HAL_UNLOCK(hcec); - - HAL_CEC_TxCpltCallback(hcec); - - return HAL_OK; - } - else - { - if (hcec->TxXferCount == 1) - { - /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; - hcec->TxXferCount--; - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - return HAL_OK; - } } else { @@ -701,70 +436,25 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati } /** - * @brief Receive data in interrupt mode. + * @brief Get size of the received frame. * @param hcec: CEC handle - * @param pData: pointer to received data buffer. - * Note that the received data size is not known beforehand, the latter is known - * when the reception is complete and is stored in hcec->RxXferSize. - * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). - * If only a header is received, hcec->RxXferSize = 0 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) -{ - if(hcec->State == HAL_CEC_STATE_READY) - { - if(pData == NULL ) - { - hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hcec); - hcec->RxXferSize = 0; - hcec->pRxBuffPtr = pData; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - /* the IP is moving to a ready to receive state */ - hcec->State = HAL_CEC_STATE_STANDBY_RX; - - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Enable the following CEC Reception Error Interrupts: - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - /* Enable the following two CEC Reception interrupts: - * Rx Byte Received IT - * End of Reception IT */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND); - - __HAL_CEC_ENABLE(hcec); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } + * @retval Frame size + */ +uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) +{ + return hcec->RxXferSize; } /** - * @brief Get size of the received frame. + * @brief Change Rx Buffer. * @param hcec: CEC handle + * @param Rxbuffer: Rx Buffer + * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ -uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec) +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) { - return hcec->RxXferSize; + hcec->Init.RxBuffer = Rxbuffer; } /** @@ -774,104 +464,102 @@ uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec) */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) { - /* save interrupts register for further error or interrupts handling purposes */ - hcec->ErrorCode = hcec->Instance->ISR; - /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE); - hcec->State = HAL_CEC_STATE_ERROR; - } - /* CEC transmit error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR); - hcec->State = HAL_CEC_STATE_ERROR; - } - - /* CEC TX underrun error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR); - hcec->State = HAL_CEC_STATE_ERROR; - } + /* save interrupts register for further error or interrupts handling purposes */ + uint32_t reg = 0; + reg = hcec->Instance->ISR; + + /* ----------------------------Arbitration Lost Management----------------------------------*/ /* CEC TX arbitration error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET)) + if((reg & CEC_FLAG_ARBLST) != RESET) { + hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); - hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX overrun error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR); - hcec->State = HAL_CEC_STATE_ERROR; - } - - /* CEC RX bit rising error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE); - hcec->State = HAL_CEC_STATE_ERROR; - } - - /* CEC RX short bit period error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE); - hcec->State = HAL_CEC_STATE_ERROR; - } - - /* CEC RX long bit period error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE); - hcec->State = HAL_CEC_STATE_ERROR; - } - - /* CEC RX missing acknowledge error interrupt occurred --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE); - hcec->State = HAL_CEC_STATE_ERROR; - } - - if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0) - { - HAL_CEC_ErrorCallback(hcec); - } - + /* ----------------------------Rx Management----------------------------------*/ /* CEC RX byte received interrupt ---------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET)) + if((reg & CEC_FLAG_RXBR) != RESET) { - /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Receive_IT(hcec); + /* reception is starting */ + hcec->RxState = HAL_CEC_STATE_BUSY_RX; + hcec->RxXferSize++; + /* read received byte */ + *hcec->Init.RxBuffer++ = hcec->Instance->RXDR; + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); } /* CEC RX end received interrupt ---------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET)) + if((reg & CEC_FLAG_RXEND) != RESET) { - /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Receive_IT(hcec); + /* clear IT */ + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); + + /* Rx process is completed, restore hcec->RxState to Ready */ + hcec->RxState = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->Init.RxBuffer-=hcec->RxXferSize; + HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); + hcec->RxXferSize = 0; } - + /* ----------------------------Tx Management----------------------------------*/ /* CEC TX byte request interrupt ------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET)) + if((reg & CEC_FLAG_TXBR) != RESET) { - /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Transmit_IT(hcec); + if (hcec->TxXferCount == 0) + { + /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + } + else + { + hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + hcec->TxXferCount--; + } + /* clear Tx-Byte request flag */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); } /* CEC TX end interrupt ------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET)) - { - /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Transmit_IT(hcec); + if((reg & CEC_FLAG_TXEND) != RESET) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); + + /* Tx process is ended, restore hcec->gState to Ready */ + hcec->gState = HAL_CEC_STATE_READY; + /* Call the Process Unlocked before calling the Tx call back API to give the possibility to + start again the Transmission under the Tx call back API */ + __HAL_UNLOCK(hcec); + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + HAL_CEC_TxCpltCallback(hcec); } + + /* ----------------------------Rx/Tx Error Management----------------------------------*/ + if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0) + { + hcec->ErrorCode = reg; + __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE); + + + if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET) + { + hcec->Init.RxBuffer-=hcec->RxXferSize; + hcec->RxXferSize = 0; + hcec->RxState = HAL_CEC_STATE_READY; + } + else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET)) + { + /* Set the CEC state ready to be able to start again the process */ + hcec->gState = HAL_CEC_STATE_READY; + } + + /* Error Call Back */ + HAL_CEC_ErrorCallback(hcec); + } + } /** @@ -891,14 +579,16 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Rx Transfer completed callback * @param hcec: CEC handle + * @param RxFrameSize: Size of frame * @retval None */ -__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) +__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcec); + UNUSED(RxFrameSize); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_TxCpltCallback can be implemented in the user file + the HAL_CEC_RxCpltCallback can be implemented in the user file */ } @@ -929,17 +619,23 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) [..] This subsection provides a set of functions allowing to control the CEC. (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. + (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. @endverbatim * @{ */ /** * @brief return the CEC state - * @param hcec: CEC handle + * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * the configuration information for the specified CEC module. * @retval HAL state */ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) { - return hcec->State; + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = hcec->gState; + temp2 = hcec->RxState; + + return (HAL_CEC_StateTypeDef)(temp1 | temp2); } /** @@ -956,154 +652,7 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) /** * @} */ - -/** - * @brief Send data in interrupt mode - * @param hcec: CEC handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_CEC_Transmit_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) -{ - /* if the IP is already busy or if there is a previous transmission - already pending due to arbitration loss */ - if ((hcec->State == HAL_CEC_STATE_BUSY_TX) - || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) - { - __HAL_LOCK(hcec); - /* set state to BUSY TX, in case it wasn't set already (case - * of transmission new attempt after arbitration loss) */ - if (hcec->State != HAL_CEC_STATE_BUSY_TX) - { - hcec->State = HAL_CEC_STATE_BUSY_TX; - } - /* if all data have been sent */ - if(hcec->TxXferCount == 0) - { - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); - /* Disable the CEC Transmission Error Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); - - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); - - hcec->State = HAL_CEC_STATE_READY; - /* Call the Process Unlocked before calling the Tx call back API to give the possibility to - start again the Transmission under the Tx call back API */ - __HAL_UNLOCK(hcec); - - HAL_CEC_TxCpltCallback(hcec); - - return HAL_OK; - } - else - { - if (hcec->TxXferCount == 1) - { - /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; - hcec->TxXferCount--; - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Receive data in interrupt mode. - * @param hcec: CEC handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_CEC_Receive_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) -{ - uint32_t tempisr; - - /* Three different conditions are tested to carry out the RX IT processing: - * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and - * the reception of the first byte is starting - * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX) - * and a new byte is being received - * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX) - * but has been interrupted by a new message reception or discarded due to - * arbitration loss: the reception of the first or higher priority message - * (the arbitration winner) is starting */ - if ((hcec->State == HAL_CEC_STATE_STANDBY_RX) - || (hcec->State == HAL_CEC_STATE_BUSY_RX) - || (hcec->State == HAL_CEC_STATE_BUSY_TX)) - { - /* reception is starting */ - hcec->State = HAL_CEC_STATE_BUSY_RX; - tempisr = (uint32_t) (hcec->Instance->ISR); - if ((tempisr & CEC_FLAG_RXBR) != 0) - { - /* Process Locked */ - __HAL_LOCK(hcec); - /* read received byte */ - *hcec->pRxBuffPtr++ = hcec->Instance->RXDR; - /* if last byte has been received */ - if ((tempisr & CEC_FLAG_RXEND) != 0) - { - /* clear IT */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR|CEC_FLAG_RXEND); - /* RX interrupts are not disabled at this point. - * Indeed, to disable the IT, the IP must be disabled first - * which resets the TXSOM flag. In case of arbitration loss, - * this leads to a transmission abort. - * Therefore, RX interruptions disabling if so required, - * is done in HAL_CEC_RxCpltCallback */ - - /* IP state is moved to READY. - * If the IP must remain in standby mode to listen - * any new message, it is up to HAL_CEC_RxCpltCallback - * to move it again to HAL_CEC_STATE_STANDBY_RX */ - hcec->State = HAL_CEC_STATE_READY; - - /* Call the Process Unlocked before calling the Rx call back API */ - __HAL_UNLOCK(hcec); - HAL_CEC_RxCpltCallback(hcec); - - return HAL_OK; - } - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); - - hcec->RxXferSize++; - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } - } - else - { - return HAL_BUSY; - } -} /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h index 13d796e6a8a..e59cffff96f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_cec.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -107,8 +107,6 @@ typedef struct uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ - - uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: @@ -120,23 +118,68 @@ typedef struct address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent. */ - uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */ + uint16_t OwnAddress; /*!< Own addresses configuration + This parameter can be a value of @ref CEC_OWN_ADDRESS */ + + uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ + }CEC_InitTypeDef; /** - * @brief HAL CEC State structures definition + * @brief HAL CEC State structures definition + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState. + * - gState contains CEC state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 Error information + * 0 : No Error + * 1 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized. HAL CEC Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */ - HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */ - HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */ - HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */ + HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */ }HAL_CEC_StateTypeDef; /** @@ -144,25 +187,27 @@ typedef enum */ typedef struct { - CEC_TypeDef *Instance; /* CEC registers base address */ + CEC_TypeDef *Instance; /*!< CEC registers base address */ - CEC_InitTypeDef Init; /* CEC communication parameters */ + CEC_InitTypeDef Init; /*!< CEC communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ - uint16_t TxXferCount; /* CEC Tx Transfer Counter */ + uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */ + uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ - uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */ - - uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register - in case error is reported */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_CEC_StateTypeDef */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. + This parameter can be a value of @ref HAL_CEC_StateTypeDef */ - HAL_CEC_StateTypeDef State; /* CEC communication state */ - + uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register + in case error is reported */ }CEC_HandleTypeDef; /** * @} @@ -176,7 +221,7 @@ typedef struct /** @defgroup CEC_Error_Code CEC Error Code * @{ */ -#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */ +#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */ #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ @@ -193,14 +238,14 @@ typedef struct /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter * @{ */ -#define CEC_DEFAULT_SFT ((uint32_t)0x00000000) -#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001) -#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002) -#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003) -#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004) -#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005) -#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006) -#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007) +#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) +#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) +#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) +#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) +#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) +#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) +#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) +#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) /** * @} */ @@ -208,7 +253,7 @@ typedef struct /** @defgroup CEC_Tolerance CEC Receiver Tolerance * @{ */ -#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000) +#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) /** * @} @@ -217,7 +262,7 @@ typedef struct /** @defgroup CEC_BRERxStop CEC Reception Stop on Error * @{ */ -#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000) +#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) /** * @} @@ -226,7 +271,7 @@ typedef struct /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported * @{ */ -#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) +#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) /** * @} @@ -235,7 +280,7 @@ typedef struct /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported * @{ */ -#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) +#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) /** * @} @@ -244,7 +289,7 @@ typedef struct /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message * @{ */ -#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000) +#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) /** * @} @@ -253,7 +298,7 @@ typedef struct /** @defgroup CEC_SFT_Option CEC Signal Free Time start option * @{ */ -#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000) +#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) /** * @} @@ -262,7 +307,7 @@ typedef struct /** @defgroup CEC_Listening_Mode CEC Listening mode option * @{ */ -#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000) +#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) /** * @} @@ -271,7 +316,7 @@ typedef struct /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register * @{ */ -#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) +#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) /** * @} */ @@ -279,11 +324,34 @@ typedef struct /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header * @{ */ -#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) +#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) /** * @} */ - + +/** @defgroup CEC_OWN_ADDRESS CEC Own Address + * @{ + */ +#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ +#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ +#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ +#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ +#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ +#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ +#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ +#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ +#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ +#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ +#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ +#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ +#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ +#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ +#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ +#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ +/** + * @} + */ + /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition * @{ */ @@ -358,11 +426,14 @@ typedef struct * @{ */ -/** @brief Reset CEC handle state +/** @brief Reset CEC handle gstate & RxState * @param __HANDLE__: CEC handle. * @retval None */ -#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET) +#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ + } while(0) /** @brief Checks whether or not the specified CEC interrupt flag is set. * @param __HANDLE__: specifies the CEC Handle. @@ -534,6 +605,7 @@ typedef struct /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); /** @@ -544,14 +616,12 @@ void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); -HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData); -uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); -void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); /** * @} @@ -625,34 +695,32 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ ((__MODE__) == CEC_FULL_LISTENING_MODE)) - + +/** @brief Check CEC message size. + * The message size is the payload size: without counting the header, + * it varies from 0 byte (ping operation, one header only, no payload) to + * 15 bytes (1 opcode and up to 14 operands following the header). + * @param __SIZE__: CEC message size. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10) + /** @brief Check CEC device Own Address Register (OAR) setting. * OAR address is written in a 15-bit field within CEC_CFGR register. * @param __ADDRESS__: CEC own address. * @retval Test result (TRUE or FALSE). */ -#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF) +#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF) /** @brief Check CEC initiator or destination logical address setting. * Initiator and destination addresses are coded over 4 bits. * @param __ADDRESS__: CEC initiator or logical address. * @retval Test result (TRUE or FALSE). */ -#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) - -/** @brief Check CEC message size. - * The message size is the payload size: without counting the header, - * it varies from 0 byte (ping operation, one header only, no payload) to - * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__: CEC message size. - * @retval Test result (TRUE or FALSE). - */ -#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) - +#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) /** * @} - */ - + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CEC_Private_Functions CEC Private Functions * @{ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c index a3c6fd24229..069c8117746 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -70,7 +70,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h index 69d3b4159aa..e85f140bb4e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -105,15 +105,15 @@ typedef struct /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /** * @} @@ -122,8 +122,8 @@ typedef struct /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source * @{ */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /** * @} @@ -133,10 +133,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) /** * @} */ @@ -144,8 +144,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) +#define MPU_REGION_ENABLE ((uint8_t)0x01U) +#define MPU_REGION_DISABLE ((uint8_t)0x00U) /** * @} */ @@ -153,8 +153,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) /** * @} */ @@ -162,8 +162,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) /** * @} */ @@ -171,8 +171,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) /** * @} */ @@ -180,8 +180,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) /** * @} */ @@ -189,9 +189,9 @@ typedef struct /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels * @{ */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) /** * @} */ @@ -199,34 +199,34 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /** * @} */ @@ -234,12 +234,12 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) /** * @} */ @@ -247,14 +247,14 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /** * @} */ @@ -323,9 +323,9 @@ void HAL_SYSTICK_Callback(void); ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) @@ -397,7 +397,7 @@ void HAL_SYSTICK_Callback(void); ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) #endif /* __MPU_PRESENT */ /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c index 48218bee348..c8f357bd23d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -37,7 +37,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -432,11 +432,11 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ } if(BufferLength%4 == 2) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1])); + *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1])); } if(BufferLength%4 == 3) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1])); + *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1])); *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; } } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h index 3f410f3397e..29a573a098c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,11 +65,11 @@ */ typedef enum { - HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ - HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ }HAL_CRC_StateTypeDef; /** * @} @@ -159,7 +159,7 @@ typedef struct /** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial * @{ */ -#define DEFAULT_CRC32_POLY 0x04C11DB7 +#define DEFAULT_CRC32_POLY 0x04C11DB7U /** * @} @@ -168,7 +168,7 @@ typedef struct /** @defgroup CRC_Default_InitValue Default CRC computation initialization value * @{ */ -#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /** * @} @@ -177,8 +177,8 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /** @@ -188,8 +188,8 @@ typedef struct /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ */ -#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) -#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /** * @} @@ -198,7 +198,7 @@ typedef struct /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP * @{ */ -#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) +#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U) #define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) #define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) #define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) @@ -209,10 +209,10 @@ typedef struct /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions * @{ */ -#define HAL_CRC_LENGTH_32B 32 -#define HAL_CRC_LENGTH_16B 16 -#define HAL_CRC_LENGTH_8B 8 -#define HAL_CRC_LENGTH_7B 7 +#define HAL_CRC_LENGTH_32B 32U +#define HAL_CRC_LENGTH_16B 16U +#define HAL_CRC_LENGTH_8B 8U +#define HAL_CRC_LENGTH_7B 7U /** * @} @@ -225,10 +225,10 @@ typedef struct * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) -#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) -#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) -#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) +#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U) +#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U) +#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U) +#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c index 6578394eea7..14a187b8bcd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h index 183dcf81e3b..c3fff768772 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ /** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes * @{ */ -#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) +#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U) #define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) #define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) #define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) @@ -80,7 +80,7 @@ /** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) +#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U) #define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) #define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c index ea580363a73..8943fbbaa92 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -70,7 +70,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,7 +103,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined (STM32F756xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup CRYP CRYP * @brief CRYP HAL module driver. * @{ @@ -3815,7 +3815,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) /** * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h index 05195014394..83e191b34c6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined (STM32F756xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -105,11 +105,11 @@ typedef struct typedef enum { - HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */ - HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */ - HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */ - HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */ - HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */ + HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ + HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ + HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */ + HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */ + HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */ }HAL_CRYP_STATETypeDef; /** @@ -123,9 +123,9 @@ typedef enum typedef enum { - HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ - HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */ - HAL_CRYP_PHASE_FINAL = 0x03 /*!< CRYP peripheral is in final phase + HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */ + HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */ + HAL_CRYP_PHASE_FINAL = 0x03U /*!< CRYP peripheral is in final phase This is relevant only with CCM and GCM modes */ }HAL_PhaseTypeDef; @@ -147,7 +147,7 @@ typedef struct uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - __IO uint16_t CrypInCount; /*!< Counter of inputed data */ + __IO uint16_t CrypInCount; /*!< Counter of input data */ __IO uint16_t CrypOutCount; /*!< Counter of output data */ @@ -180,7 +180,7 @@ typedef struct /** @defgroup CRYP_Key_Size CRYP Key Size * @{ */ -#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) +#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000U) #define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0 #define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1 /** @@ -190,7 +190,7 @@ typedef struct /** @defgroup CRYP_Data_Type CRYP Data Type * @{ */ -#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) +#define CRYP_DATATYPE_32B ((uint32_t)0x00000000U) #define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0 #define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1 #define CRYP_DATATYPE_1B CRYP_CR_DATATYPE @@ -201,21 +201,21 @@ typedef struct /** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection * @{ */ -#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003C) -#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000) -#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004) -#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008) -#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000C) -#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010) -#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014) -#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018) -#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001C) -#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020) -#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024) -#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028) -#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002C) -#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030) -#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034) +#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003CU) +#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000U) +#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004U) +#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008U) +#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000CU) +#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010U) +#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014U) +#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018U) +#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001CU) +#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020U) +#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024U) +#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028U) +#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002CU) +#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030U) +#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034U) /** * @} */ @@ -232,17 +232,17 @@ typedef struct /** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags * @{ */ -#define CRYP_FLAG_BUSY ((uint32_t)0x00000010) /*!< The CRYP core is currently +#define CRYP_FLAG_BUSY ((uint32_t)0x00000010U) /*!< The CRYP core is currently processing a block of data or a key preparation (for AES decryption). */ -#define CRYP_FLAG_IFEM ((uint32_t)0x00000001) /*!< Input FIFO is empty */ -#define CRYP_FLAG_IFNF ((uint32_t)0x00000002) /*!< Input FIFO is not Full */ -#define CRYP_FLAG_OFNE ((uint32_t)0x00000004) /*!< Output FIFO is not empty */ -#define CRYP_FLAG_OFFU ((uint32_t)0x00000008) /*!< Output FIFO is Full */ -#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002) /*!< Output FIFO service raw +#define CRYP_FLAG_IFEM ((uint32_t)0x00000001U) /*!< Input FIFO is empty */ +#define CRYP_FLAG_IFNF ((uint32_t)0x00000002U) /*!< Input FIFO is not Full */ +#define CRYP_FLAG_OFNE ((uint32_t)0x00000004U) /*!< Output FIFO is not empty */ +#define CRYP_FLAG_OFFU ((uint32_t)0x00000008U) /*!< Output FIFO is Full */ +#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U) /*!< Output FIFO service raw interrupt status */ -#define CRYP_FLAG_INRIS ((uint32_t)0x01000001) /*!< Input FIFO service raw +#define CRYP_FLAG_INRIS ((uint32_t)0x01000001U) /*!< Input FIFO service raw interrupt status */ /** * @} @@ -301,7 +301,7 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ +#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) /** @brief Check whether the specified CRYP interrupt is set or not. @@ -521,7 +521,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c index 83a154c0f67..71de5aa6bdb 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -69,7 +69,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -102,7 +102,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined (STM32F756xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup CRYPEx CRYPEx * @brief CRYP Extension HAL module driver. * @{ @@ -534,10 +534,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ hcryp->Init.pScratch[bufferidx++] = 0xFF; hcryp->Init.pScratch[bufferidx++] = 0xFE; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff; + hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; headersize += 6; } /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ @@ -1173,19 +1173,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ if(headersize < 65280) { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); headersize += 2; } else { /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFF; - hcryp->Init.pScratch[bufferidx++] = 0xFE; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff; + hcryp->Init.pScratch[bufferidx++] = 0xFFU; + hcryp->Init.pScratch[bufferidx++] = 0xFEU; + hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; headersize += 6; } /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ @@ -1585,19 +1585,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ if(headersize < 65280) { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); headersize += 2; } else { /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFF; - hcryp->Init.pScratch[bufferidx++] = 0xFE; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff; + hcryp->Init.pScratch[bufferidx++] = 0xFFU; + hcryp->Init.pScratch[bufferidx++] = 0xFEU; + hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; headersize += 6; } /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ @@ -2031,19 +2031,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ if(headersize < 65280) { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); headersize += 2; } else { /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFF; - hcryp->Init.pScratch[bufferidx++] = 0xFE; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff; + hcryp->Init.pScratch[bufferidx++] = 0xFFU; + hcryp->Init.pScratch[bufferidx++] = 0xFEU; + hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; headersize += 6; } /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ @@ -2424,19 +2424,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ if(headersize < 65280) { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); headersize += 2; } else { /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFF; - hcryp->Init.pScratch[bufferidx++] = 0xFE; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff; + hcryp->Init.pScratch[bufferidx++] = 0xFFU; + hcryp->Init.pScratch[bufferidx++] = 0xFEU; + hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; headersize += 6; } /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ @@ -2768,19 +2768,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ if(headersize < 65280) { - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU); + hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU); headersize += 2; } else { /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - hcryp->Init.pScratch[bufferidx++] = 0xFF; - hcryp->Init.pScratch[bufferidx++] = 0xFE; - hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00; - hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff; + hcryp->Init.pScratch[bufferidx++] = 0xFFU; + hcryp->Init.pScratch[bufferidx++] = 0xFEU; + hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U; + hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU; headersize += 6; } /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */ @@ -3032,7 +3032,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h index 1130a8473a6..f3b2425da06 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of CRYP HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined (STM32F756xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -65,10 +65,10 @@ /** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection * @{ */ -#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000) -#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004) -#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008) -#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000C) +#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000U) +#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004U) +#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008U) +#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000CU) /** * @} */ @@ -77,7 +77,7 @@ * @brief The phases are relevant only to AES-GCM and AES-CCM * @{ */ -#define CRYP_PHASE_INIT ((uint32_t)0x00000000) +#define CRYP_PHASE_INIT ((uint32_t)0x00000000U) #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH @@ -206,7 +206,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c index 2da067bb038..ab83cf7e3d3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -143,7 +143,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h index 7a3ac21b99e..e7cf931bb0f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,11 +64,11 @@ */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ }HAL_DAC_StateTypeDef; /** @@ -113,10 +113,10 @@ typedef struct /** @defgroup DAC_Error_Code DAC Error Code * @{ */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ /** * @} */ @@ -125,7 +125,7 @@ typedef struct * @{ */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ @@ -143,7 +143,7 @@ typedef struct /** @defgroup DAC_output_buffer DAC Output Buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) /** * @} @@ -152,8 +152,8 @@ typedef struct /** @defgroup DAC_Channel_selection DAC Channel Selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#define DAC_CHANNEL_1 ((uint32_t)0x00000000U) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010U) /** * @} */ @@ -161,9 +161,9 @@ typedef struct /** @defgroup DAC_data_alignment DAC Data Alignment * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) +#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) +#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) /** * @} */ @@ -342,7 +342,7 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); /** @defgroup DAC_Private_Macros DAC Private Macros * @{ */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) @@ -365,19 +365,19 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c index cc8e05ed0c3..2a6014aca4b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -25,7 +25,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h index 22040be664d..668c0a14730 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,7 +63,7 @@ /** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ @@ -75,7 +75,7 @@ #define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */ #define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ #define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ #define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c index 353465702a2..9a3169082b9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -63,7 +63,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -105,11 +105,19 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */ +#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */ + +#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */ +#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */ + +#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */ +#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */ +#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma); static void DCMI_DMAError(DMA_HandleTypeDef *hdma); /* Exported functions --------------------------------------------------------*/ @@ -140,7 +148,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma); * the configuration information for DCMI. * @retval HAL status */ -__weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) +HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) { /* Check the DCMI peripheral state */ if(hdcmi == NULL) @@ -150,60 +158,51 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /* Check function parameters */ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance)); - assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity)); assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity)); assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity)); + assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate)); assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode)); assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode)); + assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode)); + assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); + assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); + assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); + if(hdcmi->State == HAL_DCMI_STATE_RESET) { - /* Allocate lock resource and initialize it */ - hdcmi->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_DCMI_MspInit(hdcmi); } /* Change the DCMI state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Set DCMI parameters */ - /* Configures the HS, VS, DE and PC polarity */ - hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | - DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | - DCMI_CR_ESS); - hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \ - hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \ - hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \ - hdcmi->Init.JPEGMode); - + /* Configures the HS, VS, DE and PC polarity */ + hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\ + DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\ + DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\ + DCMI_CR_LSM | DCMI_CR_OELS); + + hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\ + hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\ + hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\ + hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\ + hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\ + hdcmi->Init.LineSelectStart); + if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) { - DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | - ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)| - ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) | - ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24)); - } - - /* Enable the Line interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE); - - /* Enable the VSYNC interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC); + hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\ + ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\ + ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\ + ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC)); - /* Enable the Frame capture complete interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME); - - /* Enable the Synchronization error interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR); + } - /* Enable the Overflow interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF); - - /* Enable DCMI by setting DCMIEN bit */ - __HAL_DCMI_ENABLE(hdcmi); + /* Enable the Line, Vsync, Error and Overrun interrupts */ + __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); /* Update error code */ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; @@ -310,23 +309,30 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /* Process Locked */ __HAL_LOCK(hdcmi); - + /* Lock the DCMI peripheral state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Check the parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); - + /* Enable DCMI by setting DCMIEN bit */ + __HAL_DCMI_ENABLE(hdcmi); + /* Configure the DCMI Mode */ hdcmi->Instance->CR &= ~(DCMI_CR_CM); hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode); /* Set the DMA memory0 conversion complete callback */ - hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt; + hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt; /* Set the DMA error callback */ hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError; + /* Set the dma abort callback */ + hdcmi->DMA_Handle->XferAbortCallback = NULL; + + /* Reset transfer counters value */ + hdcmi->XferCount = 0; + hdcmi->XferTransferNumber = 0; + if(Length <= 0xFFFF) { /* Enable the DMA Stream */ @@ -335,7 +341,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo else /* DCMI_DOUBLE_BUFFER Mode */ { /* Set the DMA memory1 conversion complete callback */ - hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt; + hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt; /* Initialize transfer parameters */ hdcmi->XferCount = 1; @@ -359,9 +365,12 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /* Start DMA multi buffer transfer */ HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize); } - + /* Enable Capture */ - DCMI->CR |= DCMI_CR_CAPTURE; + hdcmi->Instance->CR |= DCMI_CR_CAPTURE; + + /* Release Lock */ + __HAL_UNLOCK(hdcmi); /* Return function status */ return HAL_OK; @@ -375,36 +384,34 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo */ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) { - uint32_t tickstart = 0; + register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000); + HAL_StatusTypeDef status = HAL_OK; + /* Process locked */ + __HAL_LOCK(hdcmi); + /* Lock the DCMI peripheral state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - __HAL_DCMI_DISABLE(hdcmi); - /* Disable Capture */ - DCMI->CR &= ~(DCMI_CR_CAPTURE); - - /* Get tick */ - tickstart = HAL_GetTick(); + hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); /* Check if the DCMI capture effectively disabled */ - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) + do { - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP) + if (count-- == 0) { - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } + status = HAL_TIMEOUT; + break; + } } + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0); + + /* Disable the DCMI */ + __HAL_DCMI_DISABLE(hdcmi); /* Disable the DMA */ HAL_DMA_Abort(hdcmi->DMA_Handle); @@ -418,6 +425,78 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) /* Process Unlocked */ __HAL_UNLOCK(hdcmi); + /* Return function status */ + return status; +} + +/** + * @brief Suspend DCMI capture + * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) +{ + register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000); + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdcmi); + + if(hdcmi->State == HAL_DCMI_STATE_BUSY) + { + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_SUSPENDED; + + /* Disable Capture */ + hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); + + /* Check if the DCMI capture effectively disabled */ + do + { + if (count-- == 0) + { + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_READY; + + status = HAL_TIMEOUT; + break; + } + } + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0); + } + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + /* Return function status */ + return status; +} + +/** + * @brief Resume DCMI capture + * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) +{ + /* Process locked */ + __HAL_LOCK(hdcmi); + + if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED) + { + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Disable Capture */ + hdcmi->Instance->CR |= DCMI_CR_CAPTURE; + } + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + /* Return function status */ return HAL_OK; } @@ -430,110 +509,80 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) */ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) { + uint32_t isr_value = READ_REG(hdcmi->Instance->MISR); + /* Synchronization error interrupt management *******************************/ - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET) + if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI) { - if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET) - { - /* Disable the Synchronization error interrupt */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_ERR); - - /* Clear the Synchronization error flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Abort the DMA Transfer */ - HAL_DMA_Abort(hdcmi->DMA_Handle); - - /* Synchronization error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); - } + /* Clear the Synchronization error flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); + + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_ERROR; + + /* Set the synchronization error callback */ + hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; + + /* Abort the DMA Transfer */ + HAL_DMA_Abort_IT(hdcmi->DMA_Handle); } /* Overflow interrupt management ********************************************/ - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET) + if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI) { - if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET) - { - /* Disable the Overflow interrupt */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_OVF); - - /* Clear the Overflow flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Abort the DMA Transfer */ - HAL_DMA_Abort(hdcmi->DMA_Handle); - - /* Overflow Callback */ - HAL_DCMI_ErrorCallback(hdcmi); - } + /* Clear the Overflow flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); + + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_ERROR; + + /* Set the overflow callback */ + hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; + + /* Abort the DMA Transfer */ + HAL_DMA_Abort_IT(hdcmi->DMA_Handle); } /* Line Interrupt management ************************************************/ - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET) + if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI) { - if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET) - { - /* Clear the Line interrupt flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Line interrupt Callback */ - HAL_DCMI_LineEventCallback(hdcmi); - } + /* Clear the Line interrupt flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); + + /* Line interrupt Callback */ + HAL_DCMI_LineEventCallback(hdcmi); } /* VSYNC interrupt management ***********************************************/ - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET) + if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI) { - if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET) - { - /* Disable the VSYNC interrupt */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_VSYNC); - - /* Clear the VSYNC flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* VSYNC Callback */ - HAL_DCMI_VsyncEventCallback(hdcmi); - } + /* Clear the VSYNC flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); + + /* VSYNC Callback */ + HAL_DCMI_VsyncEventCallback(hdcmi); } - /* End of Frame interrupt management ****************************************/ - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET) + /* FRAME interrupt management ***********************************************/ + if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI) { - if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET) - { - /* Disable the End of Frame interrupt */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME); - - /* Clear the End of Frame flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* End of Frame Callback */ - HAL_DCMI_FrameEventCallback(hdcmi); + /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ + if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) + { + /* Disable the Line, Vsync, Error and Overrun interrupts */ + __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); } + + /* Disable the Frame interrupt */ + __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME); + + /* Clear the End of Frame flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); + + /* Frame Callback */ + HAL_DCMI_FrameEventCallback(hdcmi); } } @@ -612,7 +661,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) [..] This section provides functions allowing to: (+) Configure the CROP feature. (+) Enable/Disable the CROP feature. - (+) Enable/Disable the JPEG feature. + (+) Set embedded synchronization delimiters unmasks. @endverbatim * @{ @@ -628,7 +677,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) * @param Y0: DCMI window Y offset * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) +HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) { /* Process Locked */ __HAL_LOCK(hdcmi); @@ -643,8 +692,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui assert_param(IS_DCMI_WINDOW_COORDINATE(YSize)); /* Configure CROP */ - DCMI->CWSIZER = (XSize | (YSize << 16)); - DCMI->CWSTRTR = (X0 | (Y0 << 16)); + hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE)); + hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST)); /* Initialize the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -661,7 +710,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui * the configuration information for DCMI. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi) +HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) { /* Process Locked */ __HAL_LOCK(hdcmi); @@ -670,7 +719,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi) hdcmi->State = HAL_DCMI_STATE_BUSY; /* Disable DCMI Crop feature */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; + hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP; /* Change the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -687,7 +736,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi) * the configuration information for DCMI. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi) +HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) { /* Process Locked */ __HAL_LOCK(hdcmi); @@ -696,7 +745,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi) hdcmi->State = HAL_DCMI_STATE_BUSY; /* Enable DCMI Crop feature */ - DCMI->CR |= (uint32_t)DCMI_CR_CROP; + hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP; /* Change the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -762,12 +811,11 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) * the configuration information for the specified DMA module. * @retval None */ -static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma) +static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0; - + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hdcmi->State= HAL_DCMI_STATE_READY; if(hdcmi->XferCount != 0) { @@ -800,14 +848,18 @@ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma) hdcmi->XferCount = hdcmi->XferTransferNumber; } - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET) + /* Check if the frame is transferred */ + if(hdcmi->XferCount == hdcmi->XferTransferNumber) { - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* FRAME Callback */ - HAL_DCMI_FrameEventCallback(hdcmi); - } + /* Enable the Frame interrupt */ + __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME); + + /* When snapshot mode, set dcmi state to ready */ + if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) + { + hdcmi->State= HAL_DCMI_STATE_READY; + } + } } /** @@ -818,9 +870,19 @@ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma) */ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) { - DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hdcmi->State= HAL_DCMI_STATE_READY; - HAL_DCMI_ErrorCallback(hdcmi); + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE) + { + /* Initialize the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* Set DCMI Error Code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; + } + + /* DCMI error Callback */ + HAL_DCMI_ErrorCallback(hdcmi); } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h index 5e988718cce..798286c7339 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -45,11 +45,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" - -/* Include DCMI HAL Extended module */ -/* (include on top of file since DCMI structures are defined in extended file) */ -#include "stm32f7xx_hal_dcmi_ex.h" - + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -68,13 +64,67 @@ */ typedef enum { - HAL_DCMI_STATE_RESET = 0x00, /*!< DCMI not yet initialized or disabled */ - HAL_DCMI_STATE_READY = 0x01, /*!< DCMI initialized and ready for use */ - HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */ - HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */ - HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */ + HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */ + HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */ + HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */ + HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */ + HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */ + HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ }HAL_DCMI_StateTypeDef; +/** + * @brief DCMIEx Embedded Synchronisation CODE Init structure definition + */ +typedef struct +{ + uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ + uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ + uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ + uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ +}DCMI_CodesInitTypeDef; + +/** + * @brief DCMI Init structure definition + */ +typedef struct +{ + uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. + This parameter can be a value of @ref DCMI_Synchronization_Mode */ + + uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. + This parameter can be a value of @ref DCMI_PIXCK_Polarity */ + + uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_VSYNC_Polarity */ + + uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_HSYNC_Polarity */ + + uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. + This parameter can be a value of @ref DCMI_Capture_Rate */ + + uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. + This parameter can be a value of @ref DCMI_Extended_Data_Mode */ + + DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the + line/frame end delimiter */ + + uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. + This parameter can be a value of @ref DCMI_MODE_JPEG */ + + uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface + This parameter can be a value of @ref DCMI_Byte_Select_Mode */ + + uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd + This parameter can be a value of @ref DCMI_Byte_Select_Start */ + + uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface + This parameter can be a value of @ref DCMI_Line_Select_Mode */ + + uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd + This parameter can be a value of @ref DCMI_Line_Select_Start */ +}DCMI_InitTypeDef; + /** * @brief DCMI handle Structure definition */ @@ -113,10 +163,11 @@ typedef struct /** @defgroup DCMI_Error_Code DCMI Error Code * @{ */ -#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */ -#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */ -#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */ +#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */ +#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */ /** * @} */ @@ -124,7 +175,7 @@ typedef struct /** @defgroup DCMI_Capture_Mode DCMI Capture Mode * @{ */ -#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously +#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously into the destination memory through the DMA */ #define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA */ @@ -135,7 +186,7 @@ typedef struct /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode * @{ */ -#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop) +#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals */ #define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow */ @@ -147,7 +198,7 @@ typedef struct /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity * @{ */ -#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ /** @@ -157,7 +208,7 @@ typedef struct /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity * @{ */ -#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */ +#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */ #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ /** @@ -167,7 +218,7 @@ typedef struct /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity * @{ */ -#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */ +#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */ #define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ /** @@ -177,7 +228,7 @@ typedef struct /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG * @{ */ -#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */ +#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */ #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */ /** @@ -187,7 +238,7 @@ typedef struct /** @defgroup DCMI_Capture_Rate DCMI Capture Rate * @{ */ -#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */ +#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */ #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ @@ -198,7 +249,7 @@ typedef struct /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode * @{ */ -#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ @@ -210,7 +261,7 @@ typedef struct /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate * @{ */ -#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */ +#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */ /** * @} @@ -219,7 +270,7 @@ typedef struct /** @defgroup DCMI_Window_Height DCMI Window Height * @{ */ -#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */ +#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */ /** * @} @@ -228,11 +279,11 @@ typedef struct /** @defgroup DCMI_interrupt_sources DCMI interrupt sources * @{ */ -#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) -#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE) -#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) -#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) -#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) +#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */ +#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */ +#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */ +#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */ +#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */ /** * @} */ @@ -244,29 +295,71 @@ typedef struct /** * @brief DCMI SR register */ -#define DCMI_FLAG_HSYNC ((uint32_t)0x2001) -#define DCMI_FLAG_VSYNC ((uint32_t)0x2002) -#define DCMI_FLAG_FNE ((uint32_t)0x2004) +#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */ +#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */ +#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ /** - * @brief DCMI RISR register + * @brief DCMI RIS register */ -#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS) -#define DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS) -#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS) -#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS) -#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS) +#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */ +#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */ +#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */ +#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */ +#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */ /** - * @brief DCMI MISR register + * @brief DCMI MIS register + */ +#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */ +#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ +#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ +#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ +#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ +/** + * @} + */ + +/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode + * @{ + */ +#define DCMI_BSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received data */ +#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */ +#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */ +#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */ + +/** + * @} + */ + +/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start + * @{ */ -#define DCMI_FLAG_FRAMEMI ((uint32_t)0x1001) -#define DCMI_FLAG_OVFMI ((uint32_t)0x1002) -#define DCMI_FLAG_ERRMI ((uint32_t)0x1004) -#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008) -#define DCMI_FLAG_LINEMI ((uint32_t)0x1010) +#define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */ +#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */ + +/** + * @} + */ + +/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode + * @{ + */ +#define DCMI_LSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received lines */ +#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */ + /** * @} + */ + +/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start + * @{ */ +#define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */ +#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */ +/** + * @} + */ + /** * @} */ @@ -298,20 +391,28 @@ typedef struct /* Interrupt & Flag management */ /** - * @brief Get the DCMI pending flags. + * @brief Get the DCMI pending flag. * @param __HANDLE__: DCMI handle * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: + * This parameter can be one of the following values (no combination allowed) + * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) + * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) + * @arg DCMI_FLAG_FNE: FIFO empty flag * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask - * @arg DCMI_FLAG_OVFRI: Overflow flag mask + * @arg DCMI_FLAG_OVRRI: Overrun flag mask * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask * @arg DCMI_FLAG_LINERI: Line flag mask + * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status + * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status + * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status + * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status + * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status * @retval The state of FLAG. */ #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ -((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ - (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) +((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\ + (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) /** * @brief Clear the DCMI pending flags. @@ -396,10 +497,14 @@ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); +HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi); +HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); /** * @} @@ -409,9 +514,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); -HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi); +HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); +HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); +HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); + /** * @} */ @@ -432,7 +538,15 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DCMI_Private_Constants DCMI Private Constants + * @{ + */ +#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */ +#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */ +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /** @defgroup DCMI_Private_Macros DCMI Private Macros * @{ @@ -468,6 +582,20 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) +#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \ + ((MODE) == DCMI_BSM_OTHER) || \ + ((MODE) == DCMI_BSM_ALTERNATE_4) || \ + ((MODE) == DCMI_BSM_ALTERNATE_2)) + +#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \ + ((POLARITY) == DCMI_OEBS_EVEN)) + +#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \ + ((MODE) == DCMI_LSM_ALTERNATE_2)) + +#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ + ((POLARITY) == DCMI_OELS_EVEN)) + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c index 866718bf053..d4b1578ca03 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c @@ -2,29 +2,17 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 - * @brief DCMI Extension HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of DCMI extension peripheral: - * + Extension features functions - * - @verbatim - ============================================================================== - ##### DCMI peripheral extension features ##### - ============================================================================== - - [..] Support of Black and White cameras - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to manage the Black and White feature - - @endverbatim + * @version V1.1.0 + * @date 22-April-2016 + * @brief Empty file; This file is no longer used to handle the Black&White + * feature. Its content is now moved to common files + * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7 + * family. It's just kept for compatibility reasons. + * ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -53,17 +41,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -/** @defgroup DCMIEx DCMIEx - * @brief DCMI Extended HAL module driver - * @{ - */ - -#ifdef HAL_DCMI_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -71,131 +48,5 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup DCMIEx_Exported_Functions DCMIEx Exported Functions - * @{ - */ - -/** @defgroup DCMIEx_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DCMI - (+) De-initialize the DCMI - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DCMI according to the specified - * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) -{ - /* Check the DCMI peripheral state */ - if(hdcmi == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance)); - assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity)); - assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); - assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode)); - assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode)); - - assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode)); - assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); - assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); - assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); - - if(hdcmi->State == HAL_DCMI_STATE_RESET) - { - /* Init the low level hardware */ - HAL_DCMI_MspInit(hdcmi); - } - - /* Change the DCMI state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Configures the HS, VS, DE and PC polarity */ - hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\ - DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\ - DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\ - DCMI_CR_LSM | DCMI_CR_OELS); - - hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\ - hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\ - hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\ - hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\ - hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\ - hdcmi->Init.LineSelectStart); - - if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) - { - DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | - ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)| - ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) | - ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24)); - - } - - /* Enable the Line interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE); - - /* Enable the VSYNC interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC); - - /* Enable the Frame capture complete interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME); - - /* Enable the Synchronization error interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR); - - /* Enable the Overflow interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF); - - /* Enable DCMI by setting DCMIEN bit */ - __HAL_DCMI_ENABLE(hdcmi); - - /* Update error code */ - hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; - - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - return HAL_OK; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_DCMI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h index cbf4c73e690..4a037e4f33f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -39,175 +39,17 @@ #ifndef __STM32F7xx_HAL_DCMI_EX_H #define __STM32F7xx_HAL_DCMI_EX_H -#ifdef __cplusplus - extern "C" { -#endif - - /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup DCMIEx DCMIEx - * @{ - */ - - /* Exported types ------------------------------------------------------------*/ -/** @defgroup DCMIEx_Exported_Types DCMIEx Exported Types - * @{ - */ -/** - * @brief DCMIEx Embedded Synchronisation CODE Init structure definition - */ -typedef struct -{ - uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ - uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ - uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ - uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -}DCMI_CodesInitTypeDef; - -/** - * @brief DCMI Init structure definition - */ -typedef struct -{ - uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode */ - - uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity */ - - uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity */ - - uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity */ - - uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate */ - - uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode */ - - DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */ - - uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. - This parameter can be a value of @ref DCMI_MODE_JPEG */ - - uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface - This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */ - - uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd - This parameter can be a value of @ref DCMIEx_Byte_Select_Start */ - - uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface - This parameter can be a value of @ref DCMIEx_Line_Select_Mode */ - - uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd - This parameter can be a value of @ref DCMIEx_Line_Select_Start */ -}DCMI_InitTypeDef; - -/** - * @} - */ - /* Exported constants --------------------------------------------------------*/ -/** @defgroup DCMIEx_Exported_Constants DCMIEx Exported Constants - * @{ - */ - -/** @defgroup DCMIEx_Byte_Select_Mode DCMIEx Byte Select Mode - * @{ - */ -#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */ -#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */ -#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */ -#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */ - -/** - * @} - */ - -/** @defgroup DCMIEx_Byte_Select_Start DCMIEx Byte Select Start - * @{ - */ -#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */ -#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */ - -/** - * @} - */ - -/** @defgroup DCMIEx_Line_Select_Mode DCMIEx Line Select Mode - * @{ - */ -#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */ -#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */ - -/** - * @} - */ - -/** @defgroup DCMIEx_Line_Select_Start DCMIEx Line Select Start - * @{ - */ -#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */ -#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */ - -/** - * @} - */ - -/** - * @} - */ - /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ -/** @defgroup DCMIEx_Private_Macros DCMIEx Private Macros - * @{ - */ -#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \ - ((MODE) == DCMI_BSM_OTHER) || \ - ((MODE) == DCMI_BSM_ALTERNATE_4) || \ - ((MODE) == DCMI_BSM_ALTERNATE_2)) - -#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \ - ((POLARITY) == DCMI_OEBS_EVEN)) - -#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \ - ((MODE) == DCMI_LSM_ALTERNATE_2)) - -#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ - ((POLARITY) == DCMI_OELS_EVEN)) -/** - * @} - */ - /* Private functions ---------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - #endif /* __STM32F7xx_HAL_DCMI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h index 5e46652dd75..bd8d919b60f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f7xx_hal_def.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,10 +55,10 @@ */ typedef enum { - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** @@ -71,7 +71,7 @@ typedef enum } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ -#define HAL_MAX_DELAY 0xFFFFFFFF +#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) @@ -99,7 +99,7 @@ typedef enum * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #if (USE_RTOS == 1) /* Reserved for future use */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.c new file mode 100644 index 00000000000..d0b51cf3d1d --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.c @@ -0,0 +1,3018 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dfsdm.c + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief This file provides firmware functions to manage the following + * functionalities of the Digital Filter for Sigma-Delta Modulators + * (DFSDM) peripherals: + * + Initialization and configuration of channels and filters + * + Regular channels configuration + * + Injected channels configuration + * + Regular/Injected Channels DMA Configuration + * + Interrupts and flags management + * + Analog watchdog feature + * + Short-circuit detector feature + * + Extremes detector feature + * + Clock absence detector feature + * + Break generation on analog watchdog or short-circuit event + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Channel initialization *** + ============================== + [..] + (#) User has first to initialize channels (before filters initialization). + (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() : + (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE(). + (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init(). + (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the output clock, input, serial interface, analog watchdog, + offset and data right bit shift parameters for this channel using the + HAL_DFSDM_ChannelInit() function. + + *** Channel clock absence detector *** + ====================================== + [..] + (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or + HAL_DFSDM_ChannelCkabStart_IT(). + (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock + absence. + (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if + clock absence is detected. + (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or + HAL_DFSDM_ChannelCkabStop_IT(). + (#) Please note that the same mode (polling or interrupt) has to be used + for all channels because the channels are sharing the same interrupt. + (#) Please note also that in interrupt mode, if clock absence detector is + stopped for one channel, interrupt will be disabled for all channels. + + *** Channel short circuit detector *** + ====================================== + [..] + (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or + or HAL_DFSDM_ChannelScdStart_IT(). + (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short + circuit. + (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if + short circuit is detected. + (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or + or HAL_DFSDM_ChannelScdStop_IT(). + (#) Please note that the same mode (polling or interrupt) has to be used + for all channels because the channels are sharing the same interrupt. + (#) Please note also that in interrupt mode, if short circuit detector is + stopped for one channel, interrupt will be disabled for all channels. + + *** Channel analog watchdog value *** + ===================================== + [..] + (#) Get analog watchdog filter value of a channel using + HAL_DFSDM_ChannelGetAwdValue(). + + *** Channel offset value *** + ===================================== + [..] + (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset(). + + *** Filter initialization *** + ============================= + [..] + (#) After channel initialization, user has to init filters. + (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() : + (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + Please note that DFSDMz_FLT0 global interrupt could be already + enabled if interrupt is used for channel. + (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it + with DFSDMz filter handle using __HAL_LINKDMA(). + (#) Configure the regular conversion, injected conversion and filter + parameters for this filter using the HAL_DFSDM_FilterInit() function. + + *** Filter regular channel conversion *** + ========================================= + [..] + (#) Select regular channel and enable/disable continuous mode using + HAL_DFSDM_FilterConfigRegChannel(). + (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(), + HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or + HAL_DFSDM_FilterRegularMsbStart_DMA(). + (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect + the end of regular conversion. + (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called + at the end of regular conversion. + (#) Get value of regular conversion and corresponding channel using + HAL_DFSDM_FilterGetRegularValue(). + (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and + HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the + half transfer and at the transfer complete. Please note that + HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA + circular mode. + (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(), + HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA(). + + *** Filter injected channels conversion *** + =========================================== + [..] + (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel(). + (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(), + HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or + HAL_DFSDM_FilterInjectedMsbStart_DMA(). + (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect + the end of injected conversion. + (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called + at the end of injected conversion. + (#) Get value of injected conversion and corresponding channel using + HAL_DFSDM_FilterGetInjectedValue(). + (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and + HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the + half transfer and at the transfer complete. Please note that + HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA + circular mode. + (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(), + HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA(). + + *** Filter analog watchdog *** + ============================== + [..] + (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT(). + (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs. + (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT(). + + *** Filter extreme detector *** + =============================== + [..] + (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart(). + (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue(). + (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue(). + (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop(). + + *** Filter conversion time *** + ============================== + [..] + (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ +#ifdef HAL_DFSDM_MODULE_ENABLED +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** @defgroup DFSDM DFSDM + * @brief DFSDM HAL driver module + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup DFSDM_Private_Define DFSDM Private Define + * @{ + */ +#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV) +#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD) +#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR) +#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET) +#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS) +#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR) +#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8 +#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH) +#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH) +#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF) +#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF) +#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF) +#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF) +#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA) +#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA) +#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT) +#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT) +#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX) +#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN) +#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT) +#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF) +#define DFSDM_MSB_MASK 0xFFFF0000U +#define DFSDM_LSB_MASK 0x0000FFFFU +#define DFSDM_CKAB_TIMEOUT 5000U +#define DFSDM1_CHANNEL_NUMBER 8U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DFSDM_Private_Variables DFSDM Private Variables + * @{ + */ +__IO uint32_t v_dfsdm1ChannelCounter = 0; +DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DFSDM_Private_Functions DFSDM Private Functions + * @{ + */ +static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); +static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); +static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); +static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); +static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); +static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma); +static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma); +static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma); +static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma); +static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions + * @{ + */ + +/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions + * @brief Channel initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Channel initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the DFSDM channel. + (+) De-initialize the DFSDM channel. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DFSDM channel according to the specified parameters + * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + /* Check DFSDM Channel handle */ + if(hdfsdm_channel == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation)); + assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer)); + assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking)); + assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins)); + assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type)); + assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock)); + assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder)); + assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); + assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); + assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); + + /* Check that channel has not been already initialized */ + if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) + { + return HAL_ERROR; + } + + /* Call MSP init function */ + HAL_DFSDM_ChannelMspInit(hdfsdm_channel); + + /* Update the channel counter */ + v_dfsdm1ChannelCounter++; + + /* Configure output serial clock and enable global DFSDM interface only for first channel */ + if(v_dfsdm1ChannelCounter == 1) + { + assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); + /* Set the output serial clock source */ + DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); + DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; + + /* Reset clock divider */ + DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); + if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) + { + assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); + /* Set the output clock divider */ + DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << + DFSDM_CHCFGR1_CLK_DIV_OFFSET); + } + + /* enable the DFSDM global interface */ + DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; + } + + /* Set channel input parameters */ + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | + DFSDM_CHCFGR1_CHINSEL); + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | + hdfsdm_channel->Init.Input.DataPacking | + hdfsdm_channel->Init.Input.Pins); + + /* Set serial interface parameters */ + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | + hdfsdm_channel->Init.SerialInterface.SpiClock); + + /* Set analog watchdog parameters */ + hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); + hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | + ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET)); + + /* Set channel offset and right bit shift */ + hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | + (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET)); + + /* Enable DFSDM channel */ + hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; + + /* Set DFSDM Channel to ready state */ + hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; + + /* Store channel handle in DFSDM channel handle table */ + a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; + + return HAL_OK; +} + +/** + * @brief De-initialize the DFSDM channel. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + /* Check DFSDM Channel handle */ + if(hdfsdm_channel == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check that channel has not been already deinitialized */ + if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) + { + return HAL_ERROR; + } + + /* Disable the DFSDM channel */ + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); + + /* Update the channel counter */ + v_dfsdm1ChannelCounter--; + + /* Disable global DFSDM at deinit of last channel */ + if(v_dfsdm1ChannelCounter == 0) + { + DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN); + } + + /* Call MSP deinit function */ + HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel); + + /* Set DFSDM Channel in reset state */ + hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET; + + /* Reset channel handle in DFSDM channel handle table */ + a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL; + + return HAL_OK; +} + +/** + * @brief Initialize the DFSDM channel MSP. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval None + */ +__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_channel); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_DFSDM_ChannelMspInit could be implemented in the user file. + */ +} + +/** + * @brief De-initialize the DFSDM channel MSP. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval None + */ +__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_channel); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions + * @brief Channel operation functions + * +@verbatim + ============================================================================== + ##### Channel operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Manage clock absence detector feature. + (+) Manage short circuit detector feature. + (+) Get analog watchdog value. + (+) Modify offset value. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to start clock absence detection in polling mode. + * @note Same mode has to be used for all channels. + * @note If clock is not available on this channel during 5 seconds, + * clock absence detection will not be activated and function + * will return HAL_TIMEOUT error. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t channel; + uint32_t tickstart; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Get channel number from channel instance */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Clear clock absence flag */ + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) + { + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + + /* Check the Timeout */ + if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) + { + /* Set timeout status */ + status = HAL_TIMEOUT; + break; + } + } + + if(status == HAL_OK) + { + /* Start clock absence detection */ + hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to poll for the clock absence detection. + * @param hdfsdm_channel : DFSDM channel handle. + * @param Timeout : Timeout value in milliseconds. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t channel; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + return HAL_ERROR; + } + else + { + /* Get channel number from channel instance */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait clock absence detection */ + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0) + { + /* Check the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Return timeout status */ + return HAL_TIMEOUT; + } + } + } + + /* Clear clock absence detection flag */ + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + + /* Return function status */ + return HAL_OK; + } +} + +/** + * @brief This function allows to stop clock absence detection in polling mode. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t channel; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop clock absence detection */ + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); + + /* Clear clock absence flag */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start clock absence detection in interrupt mode. + * @note Same mode has to be used for all channels. + * @note If clock is not available on this channel during 5 seconds, + * clock absence detection will not be activated and function + * will return HAL_TIMEOUT error. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t channel; + uint32_t tickstart; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Get channel number from channel instance */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Clear clock absence flag */ + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) + { + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + + /* Check the Timeout */ + if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) + { + /* Set timeout status */ + status = HAL_TIMEOUT; + break; + } + } + + if(status == HAL_OK) + { + /* Activate clock absence detection interrupt */ + DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE; + + /* Start clock absence detection */ + hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; + } + } + /* Return function status */ + return status; +} + +/** + * @brief Clock absence detection callback. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval None + */ +__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_channel); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file + */ +} + +/** + * @brief This function allows to stop clock absence detection in interrupt mode. + * @note Interrupt will be disabled for all channels + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t channel; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop clock absence detection */ + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); + + /* Clear clock absence flag */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + + /* Disable clock absence detection interrupt */ + DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start short circuit detection in polling mode. + * @note Same mode has to be used for all channels + * @param hdfsdm_channel : DFSDM channel handle. + * @param Threshold : Short circuit detector threshold. + * This parameter must be a number between Min_Data = 0 and Max_Data = 255. + * @param BreakSignal : Break signals assigned to short circuit event. + * This parameter can be a values combination of @ref DFSDM_BreakSignals. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + uint32_t Threshold, + uint32_t BreakSignal) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); + assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Configure threshold and break signals */ + hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + Threshold); + + /* Start short circuit detection */ + hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to poll for the short circuit detection. + * @param hdfsdm_channel : DFSDM channel handle. + * @param Timeout : Timeout value in milliseconds. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t channel; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + return HAL_ERROR; + } + else + { + /* Get channel number from channel instance */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait short circuit detection */ + while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0) + { + /* Check the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Return timeout status */ + return HAL_TIMEOUT; + } + } + } + + /* Clear short circuit detection flag */ + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + + /* Return function status */ + return HAL_OK; + } +} + +/** + * @brief This function allows to stop short circuit detection in polling mode. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t channel; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop short circuit detection */ + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); + + /* Clear short circuit detection flag */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start short circuit detection in interrupt mode. + * @note Same mode has to be used for all channels + * @param hdfsdm_channel : DFSDM channel handle. + * @param Threshold : Short circuit detector threshold. + * This parameter must be a number between Min_Data = 0 and Max_Data = 255. + * @param BreakSignal : Break signals assigned to short circuit event. + * This parameter can be a values combination of @ref DFSDM_BreakSignals. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + uint32_t Threshold, + uint32_t BreakSignal) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); + assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Activate short circuit detection interrupt */ + DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE; + + /* Configure threshold and break signals */ + hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + Threshold); + + /* Start short circuit detection */ + hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; + } + /* Return function status */ + return status; +} + +/** + * @brief Short circuit detection callback. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval None + */ +__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_channel); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_ChannelScdCallback could be implemented in the user file + */ +} + +/** + * @brief This function allows to stop short circuit detection in interrupt mode. + * @note Interrupt will be disabled for all channels + * @param hdfsdm_channel : DFSDM channel handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t channel; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop short circuit detection */ + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); + + /* Clear short circuit detection flag */ + channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + + /* Disable short circuit detection interrupt */ + DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to get channel analog watchdog value. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval Channel analog watchdog value. + */ +int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + return (int16_t) hdfsdm_channel->Instance->CHWDATAR; +} + +/** + * @brief This function allows to modify channel offset value. + * @param hdfsdm_channel : DFSDM channel handle. + * @param Offset : DFSDM channel offset. + * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + int32_t Offset) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); + assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Modify channel offset */ + hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET); + hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET); + } + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function + * @brief Channel state function + * +@verbatim + ============================================================================== + ##### Channel state function ##### + ============================================================================== + [..] This section provides function allowing to: + (+) Get channel handle state. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to get the current DFSDM channel handle state. + * @param hdfsdm_channel : DFSDM channel handle. + * @retval DFSDM channel state. + */ +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +{ + /* Return DFSDM channel handle state */ + return hdfsdm_channel->State; +} + +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions + * @brief Filter initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Filter initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the DFSDM filter. + (+) De-initialize the DFSDM filter. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DFSDM filter according to the specified parameters + * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Check DFSDM Channel handle */ + if(hdfsdm_filter == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger)); + assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode)); + assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode)); + assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger)); + assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode)); + assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode)); + assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder)); + assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling)); + assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling)); + + /* Check parameters compatibility */ + if((hdfsdm_filter->Instance == DFSDM1_Filter0) && + ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || + (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) + { + return HAL_ERROR; + } + + /* Initialize DFSDM filter variables with default values */ + hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF; + hdfsdm_filter->InjectedChannelsNbr = 1; + hdfsdm_filter->InjConvRemaining = 1; + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE; + + /* Call MSP init function */ + HAL_DFSDM_FilterMspInit(hdfsdm_filter); + + /* Set regular parameters */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); + if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST; + } + else + { + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST); + } + + if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN; + } + else + { + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN); + } + + /* Set injected parameters */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL); + if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) + { + assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger)); + assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge)); + hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger); + } + + if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN; + } + else + { + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN); + } + + if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN; + } + else + { + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN); + } + + /* Set filter parameters */ + hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); + hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | + ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) | + (hdfsdm_filter->Init.FilterParam.IntOversampling - 1)); + + /* Store regular and injected triggers and injected scan mode*/ + hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger; + hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger; + hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge; + hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode; + + /* Enable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; + + /* Set DFSDM filter to ready state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initializes the DFSDM filter. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Check DFSDM filter handle */ + if(hdfsdm_filter == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Disable the DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); + + /* Call MSP deinit function */ + HAL_DFSDM_FilterMspDeInit(hdfsdm_filter); + + /* Set DFSDM filter in reset state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the DFSDM filter MSP. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_DFSDM_FilterMspInit could be implemented in the user file. + */ +} + +/** + * @brief De-initializes the DFSDM filter MSP. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_DFSDM_FilterMspDeInit could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions + * @brief Filter control functions + * +@verbatim + ============================================================================== + ##### Filter control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Select channel and enable/disable continuous mode for regular conversion. + (+) Select channels for injected conversion. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to select channel and to enable/disable + * continuous mode for regular conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Channel for regular conversion. + * This parameter can be a value of @ref DFSDM_Channel_Selection. + * @param ContinuousMode : Enable/disable continuous mode for regular conversion. + * This parameter can be a value of @ref DFSDM_ContinuousMode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel, + uint32_t ContinuousMode) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel)); + assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) + { + /* Configure channel and continuous mode for regular conversion */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT); + if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) + { + hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | + DFSDM_FLTCR1_RCONT); + } + else + { + hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); + } + /* Store continuous mode information */ + hdfsdm_filter->RegularContMode = ContinuousMode; + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to select channels for injected conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Channels for injected conversion. + * This parameter can be a values combination of @ref DFSDM_Channel_Selection. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) + { + /* Configure channel for injected conversion */ + hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK); + /* Store number of injected channels */ + hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel); + /* Update number of injected channels remaining */ + hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ + hdfsdm_filter->InjectedChannelsNbr : 1; + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions + * @brief Filter operation functions + * +@verbatim + ============================================================================== + ##### Filter operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular/injected channel. + (+) Poll for the end of regular/injected conversion. + (+) Stop conversion of regular/injected channel. + (+) Start conversion of regular/injected channel and enable interrupt. + (+) Call the callback functions at the end of regular/injected conversions. + (+) Stop conversion of regular/injected channel and disable interrupt. + (+) Start conversion of regular/injected channel and enable DMA transfer. + (+) Stop conversion of regular/injected channel and disable DMA transfer. + (+) Start analog watchdog and enable interrupt. + (+) Call the callback function when analog watchdog occurs. + (+) Stop analog watchdog and disable interrupt. + (+) Start extreme detector. + (+) Stop extreme detector. + (+) Get result of regular channel conversion. + (+) Get result of injected channel conversion. + (+) Get extreme detector maximum and minimum values. + (+) Get conversion time. + (+) Handle DFSDM interrupt request. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to start regular conversion in polling mode. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if injected conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + { + /* Start regular conversion */ + DFSDM_RegConvStart(hdfsdm_filter); + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to poll for the end of regular conversion. + * @note This function should be called only if regular conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Timeout : Timeout value in milliseconds. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + return HAL_ERROR; + } + else + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait end of regular conversion */ + while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) + { + /* Check the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Return timeout status */ + return HAL_TIMEOUT; + } + } + } + /* Check if overrun occurs */ + if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) + { + /* Update error code and call error callback */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; + HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); + + /* Clear regular overrun flag */ + hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; + } + /* Update DFSDM filter state only if not continuous conversion and SW trigger */ + if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + { + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; + } + /* Return function status */ + return HAL_OK; + } +} + +/** + * @brief This function allows to stop regular conversion in polling mode. + * @note This function should be called only if regular conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop regular conversion */ + DFSDM_RegConvStop(hdfsdm_filter); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start regular conversion in interrupt mode. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if injected conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + { + /* Enable interrupts for regular conversions */ + hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); + + /* Start regular conversion */ + DFSDM_RegConvStart(hdfsdm_filter); + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop regular conversion in interrupt mode. + * @note This function should be called only if regular conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Disable interrupts for regular conversions */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); + + /* Stop regular conversion */ + DFSDM_RegConvStop(hdfsdm_filter); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start regular conversion in DMA mode. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if injected conversion is ongoing. + * Please note that data on buffer will contain signed regular conversion + * value on 24 most significant bits and corresponding channel on 3 least + * significant bits. + * @param hdfsdm_filter : DFSDM filter handle. + * @param pData : The destination buffer address. + * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + int32_t *pData, + uint32_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check destination address and length */ + if((pData == NULL) || (Length == 0)) + { + status = HAL_ERROR; + } + /* Check that DMA is enabled for regular conversion */ + else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) + { + status = HAL_ERROR; + } + /* Check parameters compatibility */ + else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ + (Length != 1)) + { + status = HAL_ERROR; + } + else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) + { + status = HAL_ERROR; + } + /* Check DFSDM filter state */ + else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + { + /* Set callbacks on DMA handler */ + hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; + hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; + hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ + DFSDM_DMARegularHalfConvCplt : NULL; + + /* Start DMA in interrupt mode */ + if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ + (uint32_t) pData, Length) != HAL_OK) + { + /* Set DFSDM filter in error state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; + status = HAL_ERROR; + } + else + { + /* Start regular conversion */ + DFSDM_RegConvStart(hdfsdm_filter); + } + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start regular conversion in DMA mode and to get + * only the 16 most significant bits of conversion. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if injected conversion is ongoing. + * Please note that data on buffer will contain signed 16 most significant + * bits of regular conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @param pData : The destination buffer address. + * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + int16_t *pData, + uint32_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check destination address and length */ + if((pData == NULL) || (Length == 0)) + { + status = HAL_ERROR; + } + /* Check that DMA is enabled for regular conversion */ + else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) + { + status = HAL_ERROR; + } + /* Check parameters compatibility */ + else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ + (Length != 1)) + { + status = HAL_ERROR; + } + else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) + { + status = HAL_ERROR; + } + /* Check DFSDM filter state */ + else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + { + /* Set callbacks on DMA handler */ + hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; + hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; + hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ + DFSDM_DMARegularHalfConvCplt : NULL; + + /* Start DMA in interrupt mode */ + if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \ + (uint32_t) pData, Length) != HAL_OK) + { + /* Set DFSDM filter in error state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; + status = HAL_ERROR; + } + else + { + /* Start regular conversion */ + DFSDM_RegConvStart(hdfsdm_filter); + } + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop regular conversion in DMA mode. + * @note This function should be called only if regular conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop current DMA transfer */ + if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) + { + /* Set DFSDM filter in error state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; + status = HAL_ERROR; + } + else + { + /* Stop regular conversion */ + DFSDM_RegConvStop(hdfsdm_filter); + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to get regular conversion value. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Corresponding channel of regular conversion. + * @retval Regular conversion value + */ +int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t *Channel) +{ + uint32_t reg = 0; + int32_t value = 0; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(Channel != NULL); + + /* Get value of data register for regular channel */ + reg = hdfsdm_filter->Instance->FLTRDATAR; + + /* Extract channel and regular conversion value */ + *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); + value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET); + + /* return regular conversion value */ + return value; +} + +/** + * @brief This function allows to start injected conversion in polling mode. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if regular conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + { + /* Start injected conversion */ + DFSDM_InjConvStart(hdfsdm_filter); + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to poll for the end of injected conversion. + * @note This function should be called only if injected conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Timeout : Timeout value in milliseconds. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + return HAL_ERROR; + } + else + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait end of injected conversions */ + while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) + { + /* Check the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Return timeout status */ + return HAL_TIMEOUT; + } + } + } + /* Check if overrun occurs */ + if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) + { + /* Update error code and call error callback */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; + HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); + + /* Clear injected overrun flag */ + hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; + } + + /* Update remaining injected conversions */ + hdfsdm_filter->InjConvRemaining--; + if(hdfsdm_filter->InjConvRemaining == 0) + { + /* Update DFSDM filter state only if trigger is software */ + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + { + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; + } + + /* end of injected sequence, reset the value */ + hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ + hdfsdm_filter->InjectedChannelsNbr : 1; + } + + /* Return function status */ + return HAL_OK; + } +} + +/** + * @brief This function allows to stop injected conversion in polling mode. + * @note This function should be called only if injected conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop injected conversion */ + DFSDM_InjConvStop(hdfsdm_filter); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start injected conversion in interrupt mode. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if regular conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + { + /* Enable interrupts for injected conversions */ + hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); + + /* Start injected conversion */ + DFSDM_InjConvStart(hdfsdm_filter); + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop injected conversion in interrupt mode. + * @note This function should be called only if injected conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Disable interrupts for injected conversions */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); + + /* Stop injected conversion */ + DFSDM_InjConvStop(hdfsdm_filter); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start injected conversion in DMA mode. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if regular conversion is ongoing. + * Please note that data on buffer will contain signed injected conversion + * value on 24 most significant bits and corresponding channel on 3 least + * significant bits. + * @param hdfsdm_filter : DFSDM filter handle. + * @param pData : The destination buffer address. + * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + int32_t *pData, + uint32_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check destination address and length */ + if((pData == NULL) || (Length == 0)) + { + status = HAL_ERROR; + } + /* Check that DMA is enabled for injected conversion */ + else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) + { + status = HAL_ERROR; + } + /* Check parameters compatibility */ + else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ + (Length > hdfsdm_filter->InjConvRemaining)) + { + status = HAL_ERROR; + } + else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) + { + status = HAL_ERROR; + } + /* Check DFSDM filter state */ + else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + { + /* Set callbacks on DMA handler */ + hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; + hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; + hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ + DFSDM_DMAInjectedHalfConvCplt : NULL; + + /* Start DMA in interrupt mode */ + if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ + (uint32_t) pData, Length) != HAL_OK) + { + /* Set DFSDM filter in error state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; + status = HAL_ERROR; + } + else + { + /* Start injected conversion */ + DFSDM_InjConvStart(hdfsdm_filter); + } + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start injected conversion in DMA mode and to get + * only the 16 most significant bits of conversion. + * @note This function should be called only when DFSDM filter instance is + * in idle state or if regular conversion is ongoing. + * Please note that data on buffer will contain signed 16 most significant + * bits of injected conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @param pData : The destination buffer address. + * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + int16_t *pData, + uint32_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check destination address and length */ + if((pData == NULL) || (Length == 0)) + { + status = HAL_ERROR; + } + /* Check that DMA is enabled for injected conversion */ + else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) + { + status = HAL_ERROR; + } + /* Check parameters compatibility */ + else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ + (Length > hdfsdm_filter->InjConvRemaining)) + { + status = HAL_ERROR; + } + else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) + { + status = HAL_ERROR; + } + /* Check DFSDM filter state */ + else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + { + /* Set callbacks on DMA handler */ + hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; + hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; + hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ + DFSDM_DMAInjectedHalfConvCplt : NULL; + + /* Start DMA in interrupt mode */ + if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \ + (uint32_t) pData, Length) != HAL_OK) + { + /* Set DFSDM filter in error state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; + status = HAL_ERROR; + } + else + { + /* Start injected conversion */ + DFSDM_InjConvStart(hdfsdm_filter); + } + } + else + { + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop injected conversion in DMA mode. + * @note This function should be called only if injected conversion is ongoing. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Stop current DMA transfer */ + if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) + { + /* Set DFSDM filter in error state */ + hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; + status = HAL_ERROR; + } + else + { + /* Stop regular conversion */ + DFSDM_InjConvStop(hdfsdm_filter); + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to get injected conversion value. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Corresponding channel of injected conversion. + * @retval Injected conversion value + */ +int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t *Channel) +{ + uint32_t reg = 0; + int32_t value = 0; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(Channel != NULL); + + /* Get value of data register for injected channel */ + reg = hdfsdm_filter->Instance->FLTJDATAR; + + /* Extract channel and injected conversion value */ + *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); + value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET); + + /* return regular conversion value */ + return value; +} + +/** + * @brief This function allows to start filter analog watchdog in interrupt mode. + * @param hdfsdm_filter : DFSDM filter handle. + * @param awdParam : DFSDM filter analog watchdog parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + DFSDM_Filter_AwdParamTypeDef *awdParam) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource)); + assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel)); + assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold)); + assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold)); + assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal)); + assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Set analog watchdog data source */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); + hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource; + + /* Set thresholds and break signals */ + hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); + hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \ + awdParam->HighBreakSignal); + hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); + hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \ + awdParam->LowBreakSignal); + + /* Set channels and interrupt for analog watchdog */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); + hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \ + DFSDM_FLTCR2_AWDIE); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop filter analog watchdog in interrupt mode. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Reset channels for analog watchdog and deactivate interrupt */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE); + + /* Clear all analog watchdog flags */ + hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF); + + /* Reset thresholds and break signals */ + hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); + hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); + + /* Reset analog watchdog data source */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start extreme detector feature. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Channels where extreme detector is enabled. + * This parameter can be a values combination of @ref DFSDM_Channel_Selection. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Set channels for extreme detector */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); + hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET); + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop extreme detector feature. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t reg1; + __IO uint32_t reg2; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Check DFSDM filter state */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + { + /* Return error status */ + status = HAL_ERROR; + } + else + { + /* Reset channels for extreme detector */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); + + /* Clear extreme detector values */ + reg1 = hdfsdm_filter->Instance->FLTEXMAX; + reg2 = hdfsdm_filter->Instance->FLTEXMIN; + UNUSED(reg1); /* To avoid GCC warning */ + UNUSED(reg2); /* To avoid GCC warning */ + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to get extreme detector maximum value. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Corresponding channel. + * @retval Extreme detector maximum value + * This value is between Min_Data = -8388608 and Max_Data = 8388607. + */ +int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t *Channel) +{ + uint32_t reg = 0; + int32_t value = 0; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(Channel != NULL); + + /* Get value of extreme detector maximum register */ + reg = hdfsdm_filter->Instance->FLTEXMAX; + + /* Extract channel and extreme detector maximum value */ + *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); + value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET); + + /* return extreme detector maximum value */ + return value; +} + +/** + * @brief This function allows to get extreme detector minimum value. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Corresponding channel. + * @retval Extreme detector minimum value + * This value is between Min_Data = -8388608 and Max_Data = 8388607. + */ +int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t *Channel) +{ + uint32_t reg = 0; + int32_t value = 0; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + assert_param(Channel != NULL); + + /* Get value of extreme detector minimum register */ + reg = hdfsdm_filter->Instance->FLTEXMIN; + + /* Extract channel and extreme detector minimum value */ + *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); + value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET); + + /* return extreme detector minimum value */ + return value; +} + +/** + * @brief This function allows to get conversion time value. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval Conversion time value + * @note To get time in second, this value has to be divided by DFSDM clock frequency. + */ +uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + uint32_t reg = 0; + uint32_t value = 0; + + /* Check parameters */ + assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); + + /* Get value of conversion timer register */ + reg = hdfsdm_filter->Instance->FLTCNVTIMR; + + /* Extract conversion time value */ + value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET); + + /* return extreme detector minimum value */ + return value; +} + +/** + * @brief This function handles the DFSDM interrupts. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Check if overrun occurs during regular conversion */ + if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \ + ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0)) + { + /* Clear regular overrun flag */ + hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; + + /* Update error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; + + /* Call error callback */ + HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); + } + /* Check if overrun occurs during injected conversion */ + else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \ + ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0)) + { + /* Clear injected overrun flag */ + hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; + + /* Update error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; + + /* Call error callback */ + HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); + } + /* Check if end of regular conversion */ + else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \ + ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0)) + { + /* Call regular conversion complete callback */ + HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); + + /* End of conversion if mode is not continuous and software trigger */ + if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + { + /* Disable interrupts for regular conversions */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE); + + /* Update DFSDM filter state */ + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; + } + } + /* Check if end of injected conversion */ + else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \ + ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0)) + { + /* Call injected conversion complete callback */ + HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); + + /* Update remaining injected conversions */ + hdfsdm_filter->InjConvRemaining--; + if(hdfsdm_filter->InjConvRemaining == 0) + { + /* End of conversion if trigger is software */ + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + { + /* Disable interrupts for injected conversions */ + hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE); + + /* Update DFSDM filter state */ + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; + } + /* end of injected sequence, reset the value */ + hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ + hdfsdm_filter->InjectedChannelsNbr : 1; + } + } + /* Check if analog watchdog occurs */ + else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \ + ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0)) + { + uint32_t reg = 0; + uint32_t threshold = 0; + uint32_t channel = 0; + + /* Get channel and threshold */ + reg = hdfsdm_filter->Instance->FLTAWSR; + threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; + if(threshold == DFSDM_AWD_HIGH_THRESHOLD) + { + reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET; + } + while((reg & 1) == 0) + { + channel++; + reg = reg >> 1; + } + /* Clear analog watchdog flag */ + hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ + (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \ + (1 << channel); + + /* Call analog watchdog callback */ + HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold); + } + /* Check if clock absence occurs */ + else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ + ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \ + ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0)) + { + uint32_t reg = 0; + uint32_t channel = 0; + + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET); + + while(channel < DFSDM1_CHANNEL_NUMBER) + { + /* Check if flag is set and corresponding channel is enabled */ + if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL)) + { + /* Check clock absence has been enabled for this channel */ + if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0) + { + /* Clear clock absence flag */ + hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + + /* Call clock absence callback */ + HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); + } + } + channel++; + reg = reg >> 1; + } + } + /* Check if short circuit detection occurs */ + else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ + ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \ + ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0)) + { + uint32_t reg = 0; + uint32_t channel = 0; + + /* Get channel */ + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET); + while((reg & 1) == 0) + { + channel++; + reg = reg >> 1; + } + + /* Clear short circuit detection flag */ + hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + + /* Call short circuit detection callback */ + HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); + } +} + +/** + * @brief Regular conversion complete callback. + * @note In interrupt mode, user has to read conversion value in this function + * using HAL_DFSDM_FilterGetRegularValue. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Half regular conversion complete callback. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Injected conversion complete callback. + * @note In interrupt mode, user has to read conversion value in this function + * using HAL_DFSDM_FilterGetInjectedValue. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Half injected conversion complete callback. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Filter analog watchdog callback. + * @param hdfsdm_filter : DFSDM filter handle. + * @param Channel : Corresponding channel. + * @param Threshold : Low or high threshold has been reached. + * @retval None + */ +__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel, uint32_t Threshold) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + UNUSED(Channel); + UNUSED(Threshold); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_FilterAwdCallback could be implemented in the user file. + */ +} + +/** + * @brief Error callback. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdfsdm_filter); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DFSDM_FilterErrorCallback could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions + * @brief Filter state functions + * +@verbatim + ============================================================================== + ##### Filter state functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Get the DFSDM filter state. + (+) Get the DFSDM filter error. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to get the current DFSDM filter handle state. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval DFSDM filter state. + */ +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + /* Return DFSDM filter handle state */ + return hdfsdm_filter->State; +} + +/** + * @brief This function allows to get the current DFSDM filter error. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval DFSDM filter error code. + */ +uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + return hdfsdm_filter->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions + * @{ + */ + +/** + * @brief DMA half transfer complete callback for regular conversion. + * @param hdma : DMA handle. + * @retval None + */ +static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Get DFSDM filter handle */ + DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + + /* Call regular half conversion complete callback */ + HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter); +} + +/** + * @brief DMA transfer complete callback for regular conversion. + * @param hdma : DMA handle. + * @retval None + */ +static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Get DFSDM filter handle */ + DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + + /* Call regular conversion complete callback */ + HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); +} + +/** + * @brief DMA half transfer complete callback for injected conversion. + * @param hdma : DMA handle. + * @retval None + */ +static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Get DFSDM filter handle */ + DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + + /* Call injected half conversion complete callback */ + HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter); +} + +/** + * @brief DMA transfer complete callback for injected conversion. + * @param hdma : DMA handle. + * @retval None + */ +static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Get DFSDM filter handle */ + DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + + /* Call injected conversion complete callback */ + HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); +} + +/** + * @brief DMA error callback. + * @param hdma : DMA handle. + * @retval None + */ +static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Get DFSDM filter handle */ + DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + + /* Update error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA; + + /* Call error callback */ + HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +} + +/** + * @brief This function allows to get the number of injected channels. + * @param Channels : bitfield of injected channels. + * @retval Number of injected channels. + */ +static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) +{ + uint32_t nbChannels = 0; + uint32_t tmp; + + /* Get the number of channels from bitfield */ + tmp = (uint32_t) (Channels & DFSDM_LSB_MASK); + while(tmp != 0) + { + if((tmp & 1) != 0) + { + nbChannels++; + } + tmp = (uint32_t) (tmp >> 1); + } + return nbChannels; +} + +/** + * @brief This function allows to get the channel number from channel instance. + * @param Instance : DFSDM channel instance. + * @retval Channel number. + */ +static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) +{ + uint32_t channel = 0xFF; + + /* Get channel from instance */ + if(Instance == DFSDM1_Channel0) + { + channel = 0; + } + else if(Instance == DFSDM1_Channel1) + { + channel = 1; + } + else if(Instance == DFSDM1_Channel2) + { + channel = 2; + } + else if(Instance == DFSDM1_Channel3) + { + channel = 3; + } + else if(Instance == DFSDM1_Channel4) + { + channel = 4; + } + else if(Instance == DFSDM1_Channel5) + { + channel = 5; + } + else if(Instance == DFSDM1_Channel6) + { + channel = 6; + } + else if(Instance == DFSDM1_Channel7) + { + channel = 7; + } + + return channel; +} + +/** + * @brief This function allows to really start regular conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +{ + /* Check regular trigger */ + if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) + { + /* Software start of regular conversion */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; + } + else /* synchronous trigger */ + { + /* Disable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); + + /* Set RSYNC bit in DFSDM_FLTCR1 register */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC; + + /* Enable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; + + /* If injected conversion was in progress, restart it */ + if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) + { + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; + } + /* Update remaining injected conversions */ + hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ + hdfsdm_filter->InjectedChannelsNbr : 1; + } + } + /* Update DFSDM filter state */ + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ + HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; +} + +/** + * @brief This function allows to really stop regular conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +{ + /* Disable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); + + /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */ + if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) + { + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); + } + + /* Enable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; + + /* If injected conversion was in progress, restart it */ + if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) + { + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; + } + /* Update remaining injected conversions */ + hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ + hdfsdm_filter->InjectedChannelsNbr : 1; + } + + /* Update DFSDM filter state */ + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; +} + +/** + * @brief This function allows to really start injected conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +{ + /* Check injected trigger */ + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + { + /* Software start of injected conversion */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; + } + else /* external or synchronous trigger */ + { + /* Disable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); + + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) + { + /* Set JSYNC bit in DFSDM_FLTCR1 register */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC; + } + else /* external trigger */ + { + /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ + hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge; + } + + /* Enable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; + + /* If regular conversion was in progress, restart it */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; + } + } + /* Update DFSDM filter state */ + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ + HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ; +} + +/** + * @brief This function allows to really stop injected conversion. + * @param hdfsdm_filter : DFSDM filter handle. + * @retval None + */ +static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +{ + /* Disable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); + + /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */ + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) + { + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC); + } + else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) + { + /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ + hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN); + } + + /* Enable DFSDM filter */ + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; + + /* If regular conversion was in progress, restart it */ + if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + { + hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; + } + + /* Update remaining injected conversions */ + hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ + hdfsdm_filter->InjectedChannelsNbr : 1; + + /* Update DFSDM filter state */ + hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; +} + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* HAL_DFSDM_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.h new file mode 100644 index 00000000000..802165951ea --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.h @@ -0,0 +1,710 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dfsdm.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief Header file of DFSDM HAL module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DFSDM_H +#define __STM32F7xx_HAL_DFSDM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DFSDM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DFSDM_Exported_Types DFSDM Exported Types + * @{ + */ + +/** + * @brief HAL DFSDM Channel states definition + */ +typedef enum +{ + HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ + HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ + HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ +}HAL_DFSDM_Channel_StateTypeDef; + +/** + * @brief DFSDM channel output clock structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Output clock enable/disable */ + uint32_t Selection; /*!< Output clock is system clock or audio clock. + This parameter can be a value of @ref DFSDM_Channel_OuputClock */ + uint32_t Divider; /*!< Output clock divider. + This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ +}DFSDM_Channel_OutputClockTypeDef; + +/** + * @brief DFSDM channel input structure definition + */ +typedef struct +{ + uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. + This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ + uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. + This parameter can be a value of @ref DFSDM_Channel_DataPacking */ + uint32_t Pins; /*!< Input pins are taken from same or following channel. + This parameter can be a value of @ref DFSDM_Channel_InputPins */ +}DFSDM_Channel_InputTypeDef; + +/** + * @brief DFSDM channel serial interface structure definition + */ +typedef struct +{ + uint32_t Type; /*!< SPI or Manchester modes. + This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ + uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). + This parameter can be a value of @ref DFSDM_Channel_SpiClock */ +}DFSDM_Channel_SerialInterfaceTypeDef; + +/** + * @brief DFSDM channel analog watchdog structure definition + */ +typedef struct +{ + uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. + This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ + uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ +}DFSDM_Channel_AwdTypeDef; + +/** + * @brief DFSDM channel init structure definition + */ +typedef struct +{ + DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ + DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ + DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ + DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ + int32_t Offset; /*!< DFSDM channel offset. + This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ + uint32_t RightBitShift; /*!< DFSDM channel right bit shift. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ +}DFSDM_Channel_InitTypeDef; + +/** + * @brief DFSDM channel handle structure definition + */ +typedef struct +{ + DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ + DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ + HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ +}DFSDM_Channel_HandleTypeDef; + +/** + * @brief HAL DFSDM Filter states definition + */ +typedef enum +{ + HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ + HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ + HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ + HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ + HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ + HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ +}HAL_DFSDM_Filter_StateTypeDef; + +/** + * @brief DFSDM filter regular conversion parameters structure definition + */ +typedef struct +{ + uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. + This parameter can be a value of @ref DFSDM_Filter_Trigger */ + FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ + FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ +}DFSDM_Filter_RegularParamTypeDef; + +/** + * @brief DFSDM filter injected conversion parameters structure definition + */ +typedef struct +{ + uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. + This parameter can be a value of @ref DFSDM_Filter_Trigger */ + FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ + FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ + uint32_t ExtTrigger; /*!< External trigger. + This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ + uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. + This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ +}DFSDM_Filter_InjectedParamTypeDef; + +/** + * @brief DFSDM filter parameters structure definition + */ +typedef struct +{ + uint32_t SincOrder; /*!< Sinc filter order. + This parameter can be a value of @ref DFSDM_Filter_SincOrder */ + uint32_t Oversampling; /*!< Filter oversampling ratio. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t IntOversampling; /*!< Integrator oversampling ratio. + This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ +}DFSDM_Filter_FilterParamTypeDef; + +/** + * @brief DFSDM filter init structure definition + */ +typedef struct +{ + DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ + DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ + DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ +}DFSDM_Filter_InitTypeDef; + +/** + * @brief DFSDM filter handle structure definition + */ +typedef struct +{ + DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ + DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ + DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ + DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ + uint32_t RegularContMode; /*!< Regular conversion continuous mode */ + uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ + uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ + uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ + FunctionalState InjectedScanMode; /*!< Injected scanning mode */ + uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ + uint32_t InjConvRemaining; /*!< Injected conversions remaining */ + HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ + uint32_t ErrorCode; /*!< DFSDM filter error code */ +}DFSDM_Filter_HandleTypeDef; + +/** + * @brief DFSDM filter analog watchdog parameters structure definition + */ +typedef struct +{ + uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. + This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ + uint32_t Channel; /*!< Analog watchdog channel selection. + This parameter can be a values combination of @ref DFSDM_Channel_Selection */ + int32_t HighThreshold; /*!< High threshold for the analog watchdog. + This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ + int32_t LowThreshold; /*!< Low threshold for the analog watchdog. + This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ + uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. + This parameter can be a values combination of @ref DFSDM_BreakSignals */ + uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. + This parameter can be a values combination of @ref DFSDM_BreakSignals */ +}DFSDM_Filter_AwdParamTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants + * @{ + */ + +/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection + * @{ + */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ +/** + * @} + */ + +/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer + * @{ + */ +#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ +#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ +/** + * @} + */ + +/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing + * @{ + */ +#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ +#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ +#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ +/** + * @} + */ + +/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins + * @{ + */ +#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ +#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ +/** + * @} + */ + +/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type + * @{ + */ +#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ +#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ +#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ +#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ +/** + * @} + */ + +/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection + * @{ + */ +#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ +#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ +#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ +#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ +/** + * @} + */ + +/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order + * @{ + */ +#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ +#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ +#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ +#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ +/** + * @} + */ + +/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger + * @{ + */ +#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ +#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ +#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ +/** + * @} + */ + +/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger + * @{ + */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ + DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ + DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ + DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ +/** + * @} + */ + +/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge + * @{ + */ +#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ +#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ +#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ +/** + * @} + */ + +/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order + * @{ + */ +#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ +#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ +#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ +#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ +#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ +#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ +/** + * @} + */ + +/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source + * @{ + */ +#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ +#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ +/** + * @} + */ + +/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code + * @{ + */ +#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ +#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ +#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ +/** + * @} + */ + +/** @defgroup DFSDM_BreakSignals DFSDM break signals + * @{ + */ +#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ +#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ +#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ +#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ +#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ +/** + * @} + */ + +/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection + * @{ + */ +/* DFSDM Channels ------------------------------------------------------------*/ +/* The DFSDM channels are defined as follows: + - in 16-bit LSB the channel mask is set + - in 16-bit MSB the channel number is set + e.g. for channel 5 definition: + - the channel mask is 0x00000020 (bit 5 is set) + - the channel number 5 is 0x00050000 + --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ +#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) +#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) +#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) +#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) +#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) +#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) +#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) +#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) +/** + * @} + */ + +/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode + * @{ + */ +#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ +#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ +/** + * @} + */ + +/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold + * @{ + */ +#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ +#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros + * @{ + */ + +/** @brief Reset DFSDM channel handle state. + * @param __HANDLE__: DFSDM channel handle. + * @retval None + */ +#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) + +/** @brief Reset DFSDM filter handle state. + * @param __HANDLE__: DFSDM filter handle. + * @retval None + */ +#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions + * @{ + */ + +/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions + * @{ + */ +/* Channel initialization and de-initialization functions *********************/ +HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +/** + * @} + */ + +/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions + * @{ + */ +/* Channel operation functions ************************************************/ +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); + +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); + +int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); + +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); + +void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function + * @{ + */ +/* Channel state function *****************************************************/ +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +/** + * @} + */ + +/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions + * @{ + */ +/* Filter initialization and de-initialization functions *********************/ +HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +/** + * @} + */ + +/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions + * @{ + */ +/* Filter control functions *********************/ +HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel, + uint32_t ContinuousMode); +HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel); +/** + * @} + */ + +/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions + * @{ + */ +/* Filter operation functions *********************/ +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + DFSDM_Filter_AwdParamTypeDef* awdParam); +HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); +HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); + +int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); + +void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); + +HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); + +void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); +void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +/** + * @} + */ + +/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions + * @{ + */ +/* Filter state functions *****************************************************/ +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DFSDM_Private_Macros DFSDM Private Macros +* @{ +*/ +#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ + ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) +#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) +#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ + ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) +#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ + ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ + ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) +#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ + ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) +#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ + ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ + ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ + ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) +#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ + ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ + ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ + ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) +#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ + ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ + ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ + ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) +#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) +#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) +#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) +#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) +#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ + ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) +#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ + ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) +#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) +#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ + ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ + ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) +#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ + ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ + ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ + ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ + ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ + ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) +#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) +#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) +#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ + ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) +#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) +#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) +#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ + ((CHANNEL) == DFSDM_CHANNEL_1) || \ + ((CHANNEL) == DFSDM_CHANNEL_2) || \ + ((CHANNEL) == DFSDM_CHANNEL_3) || \ + ((CHANNEL) == DFSDM_CHANNEL_4) || \ + ((CHANNEL) == DFSDM_CHANNEL_5) || \ + ((CHANNEL) == DFSDM_CHANNEL_6) || \ + ((CHANNEL) == DFSDM_CHANNEL_7)) +#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) +#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ + ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DFSDM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c index 65cd18f0f1a..54c4e43edad 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -84,7 +84,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -138,7 +138,7 @@ typedef struct /** @addtogroup DMA_Private_Constants * @{ */ - #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ + #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */ /** * @} */ @@ -149,48 +149,12 @@ typedef struct */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear DBM bit */ - hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); - - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); /** * @} */ - + /* Exported functions ---------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions * @{ @@ -215,16 +179,18 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** - * @brief Initializes the DMA according to the specified + * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0; - +{ + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; + /* Check the DMA peripheral state */ if(hdma == NULL) { @@ -250,10 +216,32 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + /* Get the CR register value */ tmp = hdma->Instance->CR; @@ -293,6 +281,17 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; + + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } } /* Write to DMA Stream FCR */ @@ -300,11 +299,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ - DMA_CalcBaseAndBitshift(hdma); - + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; @@ -319,8 +321,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { - DMA_Base_Registers *regs; - + DMA_Base_Registers *regs; + /* Check the DMA peripheral state */ if(hdma == NULL) { @@ -330,35 +332,36 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { - return HAL_ERROR; + /* Return error status */ + return HAL_BUSY; } /* Disable the selected DMA Streamx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Streamx control register */ - hdma->Instance->CR = 0; + hdma->Instance->CR = 0U; /* Reset DMA Streamx number of data to transfer register */ - hdma->Instance->NDTR = 0; + hdma->Instance->NDTR = 0U; /* Reset DMA Streamx peripheral address register */ - hdma->Instance->PAR = 0; + hdma->Instance->PAR = 0U; /* Reset DMA Streamx memory 0 address register */ - hdma->Instance->M0AR = 0; - + hdma->Instance->M0AR = 0U; + /* Reset DMA Streamx memory 1 address register */ - hdma->Instance->M1AR = 0; - + hdma->Instance->M1AR = 0U; + /* Reset DMA Streamx FIFO control register */ - hdma->Instance->FCR = (uint32_t)0x00000021; - + hdma->Instance->FCR = (uint32_t)0x00000021U; + /* Get DMA steam Base Address */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3F << hdma->StreamIndex; + regs->IFCR = 0x3FU << hdma->StreamIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -381,7 +384,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) @verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer (+) Configure the source, destination address and data length and @@ -405,25 +408,37 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - /* Process locked */ - __HAL_LOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Check the parameters */ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + /* Process locked */ + __HAL_LOCK(hdma); - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - return HAL_OK; + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; } /** @@ -437,30 +452,54 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - /* Process locked */ - __HAL_LOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + HAL_StatusTypeDef status = HAL_OK; - /* Check the parameters */ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable all interrupts */ - hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME; - hdma->Instance->FCR |= DMA_IT_FE; - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - - return HAL_OK; -} + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + + return status; +} /** * @brief Aborts the DMA Transfer. @@ -476,37 +515,86 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - uint32_t tickstart = 0; - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != 0) + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + uint32_t tickstart = HAL_GetTick(); + + if(hdma->State != HAL_DMA_STATE_BUSY) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - return HAL_TIMEOUT; + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; } - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + return HAL_OK; +} - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } return HAL_OK; } @@ -515,151 +603,132 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CompleteLevel: Specifies the DMA level complete. + * @param CompleteLevel: Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout: Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { - uint32_t temp, tmp, tmp1, tmp2; - uint32_t tickstart = 0; - + HAL_StatusTypeDef status = HAL_OK; + uint32_t temp; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + /* calculate DMA base and stream number */ DMA_Base_Registers *regs; - regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ - temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; } else { /* Half Transfer Complete flag */ - temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((regs->ISR & temp) == RESET) + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; + + while((tmpisr & temp) == RESET ) { - tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex); - tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex); - tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex); - if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET)) - { - if(tmp != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - } - if(tmp1 != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - } - if(tmp2 != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Clear the Direct Mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; - } - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ + /* Check for the Timeout (Not applicable in circular mode)*/ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + return HAL_TIMEOUT; } } - } - - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_MEM0; - } - /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_MEM1; - } + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; } - else + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) { - /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers - are complete) */ - hdma->State = HAL_DMA_STATE_READY_MEM0; + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; } + } + + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + + status = HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + /* Process Unlocked */ __HAL_UNLOCK(hdma); + + hdma->State = HAL_DMA_STATE_READY; } else { - /* Clear the half transfer complete flag */ - regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) - { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; - } - /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; - } - } - else - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; - } + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; } - return HAL_OK; + + return status; } /** @@ -670,150 +739,140 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { + uint32_t tmpisr; + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600; + /* calculate DMA base and stream number */ - DMA_Base_Registers *regs; + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; - regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - /* Transfer Error Interrupt management ***************************************/ - if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) { /* Disable the transfer error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); - + hdma->Instance->CR &= ~(DMA_IT_TE); + /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - + /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } } } /* FIFO Error Interrupt management ******************************************/ - if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) { - /* Disable the FIFO Error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE); - /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } } } /* Direct Mode Error Interrupt management ***********************************/ - if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) { - /* Disable the direct mode Error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME); - /* Clear the direct mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } } } /* Half Transfer Complete Interrupt management ******************************/ - if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) { - /* Clear the half transfer complete flag */ - regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } } /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + else { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) { /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); } - /* Clear the half transfer complete flag */ - regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; - } - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); } } } /* Transfer Complete Interrupt management ***********************************/ - if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) { - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + + if(HAL_DMA_STATE_ABORT == hdma->State) { - /* Clear the transfer complete flag */ - regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } - /* Current memory buffer used is Memory 1 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { if(hdma->XferM1CpltCallback != NULL) { @@ -821,8 +880,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->XferM1CpltCallback(hdma); } } - /* Current memory buffer used is Memory 0 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + /* Current memory buffer used is Memory 1 */ + else { if(hdma->XferCpltCallback != NULL) { @@ -834,23 +893,18 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) { /* Disable the transfer complete interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); - } - /* Clear the transfer complete flag */ - regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_NONE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY_MEM0; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + hdma->Instance->CR &= ~(DMA_IT_TC); + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + if(hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ @@ -859,8 +913,170 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } } +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifer + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback: pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} /** * @} @@ -907,6 +1123,51 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @} */ +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + /** * @brief Returns the DMA Stream base address depending on stream number * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -915,25 +1176,119 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { - uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24; + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; /* lookup table for necessary bitshift of flags within status registers */ - static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22}; + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; - if (stream_number > 3) + if (stream_number > 3U) { /* return pointer to HISR and HIFCR */ - hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4); + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); } else { /* return pointer to LISR and LIFCR */ - hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)); + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); } return hdma->StreamBaseAddress; } + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h index 2169eafac37..69a1a431afd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,7 +67,7 @@ typedef struct { uint32_t Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_Channel_selection */ + This parameter can be a value of @ref DMAEx_Channel_selection */ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. @@ -119,17 +119,12 @@ typedef struct */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ - HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ - HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ - HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ - HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ }HAL_DMA_StateTypeDef; /** @@ -137,10 +132,24 @@ typedef enum */ typedef enum { - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + /** * @brief DMA handle Structure definition */ @@ -154,18 +163,22 @@ typedef struct __DMA_HandleTypeDef __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - void *Parent; /*!< Parent object state */ + void *Parent; /*!< Parent object state */ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ - + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ - __IO uint32_t ErrorCode; /*!< DMA Error code */ - + __IO uint32_t ErrorCode; /*!< DMA Error code */ + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ uint32_t StreamIndex; /*!< DMA Stream Index */ @@ -188,27 +201,14 @@ typedef struct __DMA_HandleTypeDef * @brief DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ -#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -/** - * @} - */ - -/** @defgroup DMA_Channel_selection DMA Channel selection - * @brief DMA channel selection - * @{ - */ -#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ -#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ -#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ -#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ -#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ -#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ -#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ -#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */ +#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ /** * @} */ @@ -217,7 +217,7 @@ typedef struct __DMA_HandleTypeDef * @brief DMA data transfer direction * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ /** @@ -229,7 +229,7 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ /** * @} */ @@ -239,29 +239,27 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ /** * @} */ - /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @brief DMA peripheral data size * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} */ - /** @defgroup DMA_Memory_data_size DMA Memory data size * @brief DMA memory data size * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ /** @@ -272,19 +270,18 @@ typedef struct __DMA_HandleTypeDef * @brief DMA mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ /** * @} */ - /** @defgroup DMA_Priority_level DMA Priority level * @brief DMA priority levels * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ @@ -292,12 +289,11 @@ typedef struct __DMA_HandleTypeDef * @} */ - /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode * @brief DMA FIFO direct mode * @{ */ -#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ +#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ /** * @} @@ -307,7 +303,7 @@ typedef struct __DMA_HandleTypeDef * @brief DMA FIFO level * @{ */ -#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ @@ -319,7 +315,7 @@ typedef struct __DMA_HandleTypeDef * @brief DMA memory burst * @{ */ -#define DMA_MBURST_SINGLE ((uint32_t)0x00000000) +#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) @@ -327,15 +323,14 @@ typedef struct __DMA_HandleTypeDef * @} */ - /** @defgroup DMA_Peripheral_burst DMA Peripheral burst * @brief DMA peripheral burst * @{ */ -#define DMA_PBURST_SINGLE ((uint32_t)0x00000000) -#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) -#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) -#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) +#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) +#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) +#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) /** * @} */ @@ -348,7 +343,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) -#define DMA_IT_FE ((uint32_t)0x00000080) +#define DMA_IT_FE ((uint32_t)0x00000080U) /** * @} */ @@ -357,26 +352,26 @@ typedef struct __DMA_HandleTypeDef * @brief DMA flag definitions * @{ */ -#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) -#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) -#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) -#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) -#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) -#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) -#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) -#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) -#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) -#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) -#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) -#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) -#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) -#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) -#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) -#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) -#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) -#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) -#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) -#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) +#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U) +#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U) +#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) +#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) +#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) +#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) +#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) +#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) +#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) +#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) +#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) +#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) +#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) +#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) +#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) +#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) +#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) +#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) +#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) +#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) /** * @} */ @@ -563,7 +558,7 @@ typedef struct __DMA_HandleTypeDef * @brief Enable the specified DMA Stream interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: + * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. * @arg DMA_IT_TE: Transfer error interrupt mask. @@ -578,7 +573,7 @@ typedef struct __DMA_HandleTypeDef * @brief Disable the specified DMA Stream interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: + * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. * @arg DMA_IT_TE: Transfer error interrupt mask. @@ -660,8 +655,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + /** * @} */ @@ -692,20 +692,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); * @brief DMA private macros * @{ */ -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7)) - #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c index b1849737360..d3ca0b2412a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma2d.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: @@ -17,55 +17,67 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Program the required configuration through following parameters: - the Transfer Mode, the output color mode and the output offset using + (#) Program the required configuration through the following parameters: + the transfer mode, the output color mode and the output offset using HAL_DMA2D_Init() function. - (#) Program the required configuration through following parameters: - the input color mode, the input color, input alpha value, alpha mode - and the input offset using HAL_DMA2D_ConfigLayer() function for foreground - or/and background layer. + (#) Program the required configuration through the following parameters: + the input color mode, the input color, the input alpha value, the alpha mode, + the red/blue swap mode, the inverted alpha mode and the input offset using + HAL_DMA2D_ConfigLayer() function for foreground or/and background layer. *** Polling mode IO operation *** ================================= [..] - (+) Configure the pdata, Destination and data length and Enable - the transfer using HAL_DMA2D_Start() - (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage + (#) Configure pdata parameter (explained hereafter), destination and data length + and enable the transfer using HAL_DMA2D_Start(). + (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage user can specify the value of timeout according to his end application. *** Interrupt mode IO operation *** =================================== [..] - (#) Configure the pdata, Destination and data length and Enable - the transfer using HAL_DMA2D_Start_IT() - (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine + (#) Configure pdata parameter, destination and data length and enable + the transfer using HAL_DMA2D_Start_IT(). + (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine. (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA2D handle structure). + add his own function by customization of function pointer XferCpltCallback (member + of DMA2D handle structure). + (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback + XferErrorCallback. - -@- In Register-to-Memory transfer mode, the pdata parameter is the register - color, in Memory-to-memory or memory-to-memory with pixel format - conversion the pdata is the source address. + -@- In Register-to-Memory transfer mode, pdata parameter is the register + color, in Memory-to-memory or Memory-to-Memory with pixel format + conversion pdata is the source address. -@- Configure the foreground source address, the background source address, - the Destination and data length and Enable the transfer using + the destination and data length then Enable the transfer using HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() in interrupt mode. -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions are used if the memory to memory with blending transfer mode is selected. - (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT() - HAL_DMA2D_EnableCLUT() functions. + (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling + mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. - (#) Optionally, configure and enable LineInterrupt using the following function: - HAL_DMA2D_ProgramLineEvent(). + (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent() + + (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two + consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() + and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or + HAL_DMA2D_DisableDeadTime(). - (#) The transfer can be suspended, continued and aborted using the following + (#) The transfer can be suspended, resumed and aborted using the following functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). + + (#) The CLUT loading can be suspended, resumed and aborted using the following + functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), + HAL_DMA2D_CLUTLoading_Abort(). - (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState() + (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). + + (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). *** DMA2D HAL driver macros list *** ============================================= @@ -73,12 +85,11 @@ Below the list of most used macros in DMA2D HAL driver : (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. - (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral. (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. - (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not. + (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros @@ -87,7 +98,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -120,7 +131,8 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -/** @addtogroup DMA2D + +/** @defgroup DMA2D DMA2D * @brief DMA2D HAL module driver * @{ */ @@ -129,11 +141,49 @@ /* Private types -------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup DMA2D_Private_Defines +/** @defgroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_TimeOut DMA2D Time Out + * @{ + */ +#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */ +#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */ +/** + * @} + */ + +/** @defgroup DMA2D_Shifts DMA2D Shifts * @{ + */ +#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */ +#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */ + +#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */ +#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */ + +#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */ +#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */ +#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */ + +#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */ +#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */ +#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */ + +#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */ + +#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */ +#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */ + +#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */ +#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */ + +#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */ +/** + * @} */ -#define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */ -#define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */ + /** * @} */ @@ -152,11 +202,11 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA2D_Exported_Functions +/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions * @{ */ -/** @defgroup DMA2D_Group1 Initialization and Configuration functions +/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -172,7 +222,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ /** - * @brief Initializes the DMA2D according to the specified + * @brief Initialize the DMA2D according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. @@ -180,8 +230,6 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) { - uint32_t tmp = 0; - /* Check the DMA2D peripheral state */ if(hdma2d == NULL) { @@ -205,44 +253,24 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; -/* DMA2D CR register configuration -------------------------------------------*/ - /* Get the CR register value */ - tmp = hdma2d->Instance->CR; - - /* Clear Mode bits */ - tmp &= (uint32_t)~DMA2D_CR_MODE; - - /* Prepare the value to be wrote to the CR register */ - tmp |= hdma2d->Init.Mode; - - /* Write to DMA2D CR register */ - hdma2d->Instance->CR = tmp; - -/* DMA2D OPFCCR register configuration ---------------------------------------*/ - /* Get the OPFCCR register value */ - tmp = hdma2d->Instance->OPFCCR; - - /* Clear Color Mode bits */ - tmp &= (uint32_t)~DMA2D_OPFCCR_CM; - - /* Prepare the value to be wrote to the OPFCCR register */ - tmp |= hdma2d->Init.ColorMode; - - /* Write to DMA2D OPFCCR register */ - hdma2d->Instance->OPFCCR = tmp; + /* DMA2D CR register configuration -------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); -/* DMA2D OOR register configuration ------------------------------------------*/ - /* Get the OOR register value */ - tmp = hdma2d->Instance->OOR; + /* DMA2D OPFCCR register configuration ---------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); - /* Clear Offset bits */ - tmp &= (uint32_t)~DMA2D_OOR_LO; + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); - /* Prepare the value to be wrote to the OOR register */ - tmp |= hdma2d->Init.OutputOffset; - - /* Write to DMA2D OOR register */ - hdma2d->Instance->OOR = tmp; +#if defined (DMA2D_OPFCCR_AI) + /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI)); +#endif /* DMA2D_OPFCCR_AI */ + +#if defined (DMA2D_OPFCCR_RBS) + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS)); +#endif /* DMA2D_OPFCCR_RBS */ + /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; @@ -263,24 +291,73 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { + /* Check the DMA2D peripheral state */ if(hdma2d == NULL) { return HAL_ERROR; } + + /* Before aborting any DMA2D transfer or CLUT loading, check + first whether or not DMA2D clock is enabled */ + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) + { + /* Abort DMA2D transfer if any */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) + { + if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) + { + /* Issue when aborting DMA2D transfer */ + return HAL_ERROR; + } + } + else + { + /* Abort background CLUT loading if any */ + if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK) + { + /* Issue when aborting background CLUT loading */ + return HAL_ERROR; + } + } + else + { + /* Abort foreground CLUT loading if any */ + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK) + { + /* Issue when aborting foreground CLUT loading */ + return HAL_ERROR; + } + } + } + } + } - /* DeInit the low level hardware */ + + /* Carry on with de-initialization of low level hardware */ HAL_DMA2D_MspDeInit(hdma2d); + + /* Reset DMA2D control registers*/ + hdma2d->Instance->CR = 0; + hdma2d->Instance->FGOR = 0; + hdma2d->Instance->BGOR = 0; + hdma2d->Instance->FGPFCCR = 0; + hdma2d->Instance->BGPFCCR = 0; + hdma2d->Instance->OPFCCR = 0; /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; - + /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hdma2d); - + return HAL_OK; } @@ -294,10 +371,10 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DMA2D_MspInit could be implemented in the user file - */ + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspInit can be implemented in the user file. + */ } /** @@ -310,17 +387,18 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DMA2D_MspDeInit could be implemented in the user file - */ + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspDeInit can be implemented in the user file. + */ } /** * @} */ -/** @defgroup DMA2D_Group2 IO operation functions + +/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @verbatim @@ -328,19 +406,28 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure the pdata, destination address and data size and - Start DMA2D transfer. + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer. (+) Configure the source for foreground and background, destination address - and data size and Start MultiBuffer DMA2D transfer. - (+) Configure the pdata, destination address and data size and - Start DMA2D transfer with interrupt. + and data size then start a MultiBuffer DMA2D transfer. + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer with interrupt. (+) Configure the source for foreground and background, destination address - and data size and Start MultiBuffer DMA2D transfer with interrupt. + and data size then start a MultiBuffer DMA2D transfer with interrupt. (+) Abort DMA2D transfer. (+) Suspend DMA2D transfer. - (+) Continue DMA2D transfer. + (+) Resume DMA2D transfer. + (+) Enable CLUT transfer. + (+) Configure CLUT loading then start transfer in polling mode. + (+) Configure CLUT loading then start transfer in interrupt mode. + (+) Abort DMA2D CLUT loading. + (+) Suspend DMA2D CLUT loading. + (+) Resume DMA2D CLUT loading. (+) Poll for transfer complete. (+) handle DMA2D interrupt request. + (+) Transfer watermark callback. + (+) CLUT Transfer Complete callback. + @endverbatim * @{ @@ -348,32 +435,29 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) /** * @brief Start the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @param pdata: Configure the source memory Buffer address if - * the memory to memory or memory to memory with pixel format - * conversion DMA2D mode is selected, and configure - * the color value if register to memory DMA2D mode is selected. + * Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) { + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Disable the Peripheral */ - __HAL_DMA2D_DISABLE(hdma2d); - + /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); @@ -385,78 +469,66 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u /** * @brief Start the DMA2D Transfer with interrupt enabled. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @param pdata: Configure the source memory Buffer address if - * the memory to memory or memory to memory with pixel format - * conversion DMA2D mode is selected, and configure - * the color value if register to memory DMA2D mode is selected. + * the Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) { + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Disable the Peripheral */ - __HAL_DMA2D_DISABLE(hdma2d); - /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); - /* Enable the transfer complete interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC); - - /* Enable the transfer Error interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE); + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); - /* Enable the configuration error interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE); - return HAL_OK; } /** * @brief Start the multi-source DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address of the foreground layer. - * @param SrcAddress2: The source memory Buffer address of the background layer. - * @param DstAddress: The destination memory Buffer address - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param SrcAddress1: The source memory Buffer address for the foreground layer. + * @param SrcAddress2: The source memory Buffer address for the background layer. + * @param DstAddress: The destination memory Buffer address. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) { + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Disable the Peripheral */ - __HAL_DMA2D_DISABLE(hdma2d); - /* Configure DMA2D Stream source2 address */ - hdma2d->Instance->BGMAR = SrcAddress2; + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); @@ -469,45 +541,36 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t /** * @brief Start the multi-source DMA2D Transfer with interrupt enabled. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address of the foreground layer. - * @param SrcAddress2: The source memory Buffer address of the background layer. + * @param SrcAddress1: The source memory Buffer address for the foreground layer. + * @param SrcAddress2: The source memory Buffer address for the background layer. * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) { + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Disable the Peripheral */ - __HAL_DMA2D_DISABLE(hdma2d); /* Configure DMA2D Stream source2 address */ - hdma2d->Instance->BGMAR = SrcAddress2; + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); - - /* Enable the configuration error interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE); - - /* Enable the transfer complete interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC); - - /* Enable the transfer Error interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE); - + + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); @@ -524,22 +587,25 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) { uint32_t tickstart = 0; - /* Disable the DMA2D */ - __HAL_DMA2D_DISABLE(hdma2d); + /* Abort the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing ‘0’ has no + effect on START bitvalue). */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively disabled */ - while((hdma2d->Instance->CR & DMA2D_CR_START) != 0) + while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) { - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT) + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; /* Change the DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma2d); @@ -547,11 +613,15 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) return HAL_TIMEOUT; } } - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); + + /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); return HAL_OK; } @@ -567,27 +637,41 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) uint32_t tickstart = 0; /* Suspend the DMA2D transfer */ - hdma2d->Instance->CR |= DMA2D_CR_SUSP; + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing ‘0’ has no + effect on START bitvalue). */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively suspended */ - while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) + while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ + && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)) { - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND) + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; /* Change the DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; return HAL_TIMEOUT; } } - /* Change the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no tranfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } return HAL_OK; } @@ -600,139 +684,478 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) */ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) { - /* Resume the DMA2D transfer */ - hdma2d->Instance->CR &= ~DMA2D_CR_SUSP; + /* Check the SUSP and START bits */ + if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) + { + /* Ongoing transfer is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } - /* Change the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Resume the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing ‘0’ has no + effect on START bitvalue). */ + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); return HAL_OK; } + /** - * @brief Polling for transfer complete or CLUT loading. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Timeout: Timeout duration + * @brief Enable the DMA2D CLUT Transfer. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) -{ - uint32_t tmp, tmp1; - uint32_t tickstart = 0; - - /* Polling for DMA2D transfer */ - if((hdma2d->Instance->CR & DMA2D_CR_START) != 0) +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if(LayerIdx == 0) { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) - { - tmp = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE); - tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE); - - if((tmp != RESET) || (tmp1 != RESET)) - { - /* Clear the transfer and configuration error flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); - - /* Change DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - } + /* Enable the background CLUT loading */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); } - /* Polling for CLUT loading */ - if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0) + else { - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) - { - if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET)) - { - /* Clear the transfer and configuration error flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); - - /* Change DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_ERROR; - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - } + /* Enable the foreground CLUT loading */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } - /* Clear the transfer complete flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); - - /* Clear the CLUT loading flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); return HAL_OK; } + + /** - * @brief Handles DMA2D interrupt request. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @brief Start DMA2D CLUT Loading. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). * @retval HAL status */ -void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) -{ - /* Transfer Error Interrupt management ***************************************/ - if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET) +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == 0) { - if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET) - { - /* Disable the transfer Error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - /* Clear the transfer error flag */ + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading with interrupt enabled. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == 0) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Abort the DMA2D CLUT loading. + * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart = 0; + __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + + /* Abort the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == 1) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is aborted */ + while((*reg & DMA2D_BGPFCCR_START) != RESET) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + + /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Change the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Suspend the DMA2D CLUT loading. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart = 0; + __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + + /* Suspend the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == 1) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is suspended */ + while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ + && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((*reg & DMA2D_BGPFCCR_START) != RESET) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no tranfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA2D CLUT loading. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the SUSP and START bits for background or foreground CLUT loading */ + if(LayerIdx == 0) + { + /* Background CLUT loading suspension check */ + if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + else + { + /* Foreground CLUT loading suspension check */ + if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + + /* Resume the CLUT loading */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + return HAL_OK; +} + + +/** + + * @brief Polling for transfer complete or CLUT loading. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) +{ + uint32_t tickstart = 0; + __IO uint32_t isrflags = 0x0; + + /* Polling for DMA2D transfer */ + if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) + { + if ((isrflags & DMA2D_FLAG_CE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the transfer and configuration error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + /* Polling for CLUT loading (foreground or background) */ + if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) || + ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) + { + if ((isrflags & DMA2D_FLAG_CAE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + } + if ((isrflags & DMA2D_FLAG_CE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear the transfer complete and CLUT loading flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} +/** + * @brief Handle DMA2D interrupt request. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); + uint32_t crflags = READ_REG(hdma2d->Instance->CR); + + /* Transfer Error Interrupt management ***************************************/ + if ((isrflags & DMA2D_FLAG_TE) != RESET) + { + if ((crflags & DMA2D_IT_TE) != RESET) + { + /* Disable the transfer Error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + + /* Clear the transfer error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); /* Change DMA2D state */ @@ -749,10 +1172,10 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) } } /* Configuration Error Interrupt management **********************************/ - if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET) + if ((isrflags & DMA2D_FLAG_CE) != RESET) { - if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET) - { + if ((crflags & DMA2D_IT_CE) != RESET) + { /* Disable the Configuration Error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); @@ -775,11 +1198,53 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) } } } + /* CLUT access Error Interrupt management ***********************************/ + if ((isrflags & DMA2D_FLAG_CAE) != RESET) + { + if ((crflags & DMA2D_IT_CAE) != RESET) + { + /* Disable the CLUT access error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); + + /* Clear the CLUT access error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* Transfer watermark Interrupt management **********************************/ + if ((isrflags & DMA2D_FLAG_TW) != RESET) + { + if ((crflags & DMA2D_IT_TW) != RESET) + { + /* Disable the transfer watermark interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Clear the transfer watermark flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); + + /* Transfer watermark Callback */ + HAL_DMA2D_LineEventCallback(hdma2d); + } + } /* Transfer Complete Interrupt management ************************************/ - if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET) + if ((isrflags & DMA2D_FLAG_TC) != RESET) { - if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET) - { + if ((crflags & DMA2D_IT_TC) != RESET) + { /* Disable the transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); @@ -802,13 +1267,70 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) } } } + /* CLUT Transfer Complete Interrupt management ******************************/ + if ((isrflags & DMA2D_FLAG_CTC) != RESET) + { + if ((crflags & DMA2D_IT_CTC) != RESET) + { + /* Disable the CLUT transfer complete interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); + + /* Clear the CLUT transfer complete flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + /* CLUT Transfer complete Callback */ + HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); + } + } + +} + +/** + * @brief Transfer watermark callback. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_LineEventCallback can be implemented in the user file. + */ +} + +/** + * @brief CLUT Transfer Complete callback. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. + */ } /** * @} */ -/** @defgroup DMA2D_Group3 Peripheral Control functions +/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim @@ -816,15 +1338,17 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure the DMA2D foreground or/and background parameters. + (+) Configure the DMA2D foreground or background layer parameters. (+) Configure the DMA2D CLUT transfer. - (+) Enable DMA2D CLUT. - (+) Disable DMA2D CLUT. (+) Configure the line watermark + (+) Configure the dead time value. + (+) Enable or disable the dead time value functionality. + @endverbatim * @{ */ + /** * @brief Configure the DMA2D Layer according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. @@ -839,14 +1363,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La { DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; - uint32_t tmp = 0; - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + uint32_t regMask = 0, regValue = 0; + /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); @@ -858,101 +1376,70 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode)); } } + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* DMA2D BGPFCR register configuration -----------------------------------*/ + /* Prepare the value to be written to the BGPFCCR register */ + + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM); + regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; + +#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) + regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI); + regMask |= DMA2D_BGPFCCR_AI; +#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */ + +#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS) + regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS); + regMask |= DMA2D_BGPFCCR_RBS; +#endif + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA); + } /* Configure the background DMA2D layer */ if(LayerIdx == 0) { - /* DMA2D BGPFCR register configuration -----------------------------------*/ - /* Get the BGPFCCR register value */ - tmp = hdma2d->Instance->BGPFCCR; - - /* Clear Input color mode, alpha value and alpha mode bits */ - tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA); - - if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) - { - /* Prepare the value to be wrote to the BGPFCCR register */ - tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000)); - } - else - { - /* Prepare the value to be wrote to the BGPFCCR register */ - tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); - } - - /* Write to DMA2D BGPFCCR register */ - hdma2d->Instance->BGPFCCR = tmp; - + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + /* DMA2D BGOR register configuration -------------------------------------*/ - /* Get the BGOR register value */ - tmp = hdma2d->Instance->BGOR; - - /* Clear colors bits */ - tmp &= (uint32_t)~DMA2D_BGOR_LO; - - /* Prepare the value to be wrote to the BGOR register */ - tmp |= pLayerCfg->InputOffset; + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); - /* Write to DMA2D BGOR register */ - hdma2d->Instance->BGOR = tmp; - - if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) - { - /* Prepare the value to be wrote to the BGCOLR register */ - tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF); - - /* Write to DMA2D BGCOLR register */ - hdma2d->Instance->BGCOLR = tmp; + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); } } /* Configure the foreground DMA2D layer */ else { - /* DMA2D FGPFCR register configuration -----------------------------------*/ - /* Get the FGPFCCR register value */ - tmp = hdma2d->Instance->FGPFCCR; - - /* Clear Input color mode, alpha value and alpha mode bits */ - tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA); + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); - if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) - { - /* Prepare the value to be wrote to the FGPFCCR register */ - tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000)); - } - else - { - /* Prepare the value to be wrote to the FGPFCCR register */ - tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); - } - - /* Write to DMA2D FGPFCCR register */ - hdma2d->Instance->FGPFCCR = tmp; - - /* DMA2D FGOR register configuration -------------------------------------*/ - /* Get the FGOR register value */ - tmp = hdma2d->Instance->FGOR; - - /* Clear colors bits */ - tmp &= (uint32_t)~DMA2D_FGOR_LO; - - /* Prepare the value to be wrote to the FGOR register */ - tmp |= pLayerCfg->InputOffset; - - /* Write to DMA2D FGOR register */ - hdma2d->Instance->FGOR = tmp; + /* DMA2D FGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); - if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - /* Prepare the value to be wrote to the FGCOLR register */ - tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF); - - /* Write to DMA2D FGCOLR register */ - hdma2d->Instance->FGCOLR = tmp; + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); } - } + } /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; + hdma2d->State = HAL_DMA2D_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdma2d); @@ -962,9 +1449,9 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /** * @brief Configure the DMA2D CLUT Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. * @param LayerIdx: DMA2D Layer index. * This parameter can be one of the following values: @@ -973,169 +1460,169 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La */ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { - uint32_t tmp = 0, tmp1 = 0; - /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Configure the CLUT of the background DMA2D layer */ if(LayerIdx == 0) { - /* Get the BGCMAR register value */ - tmp = hdma2d->Instance->BGCMAR; - - /* Clear CLUT address bits */ - tmp &= (uint32_t)~DMA2D_BGCMAR_MA; - - /* Prepare the value to be wrote to the BGCMAR register */ - tmp |= (uint32_t)CLUTCfg.pCLUT; - - /* Write to DMA2D BGCMAR register */ - hdma2d->Instance->BGCMAR = tmp; - - /* Get the BGPFCCR register value */ - tmp = hdma2d->Instance->BGPFCCR; - - /* Clear CLUT size and CLUT address bits */ - tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM); - - /* Get the CLUT size */ - tmp1 = CLUTCfg.Size << 16; - - /* Prepare the value to be wrote to the BGPFCCR register */ - tmp |= (CLUTCfg.CLUTColorMode | tmp1); - - /* Write to DMA2D BGPFCCR register */ - hdma2d->Instance->BGPFCCR = tmp; + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Get the FGCMAR register value */ - tmp = hdma2d->Instance->FGCMAR; - - /* Clear CLUT address bits */ - tmp &= (uint32_t)~DMA2D_FGCMAR_MA; - /* Prepare the value to be wrote to the FGCMAR register */ - tmp |= (uint32_t)CLUTCfg.pCLUT; + /* Set the DMA2D state to Ready*/ + hdma2d->State = HAL_DMA2D_STATE_READY; - /* Write to DMA2D FGCMAR register */ - hdma2d->Instance->FGCMAR = tmp; - - /* Get the FGPFCCR register value */ - tmp = hdma2d->Instance->FGPFCCR; - - /* Clear CLUT size and CLUT address bits */ - tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM); - - /* Get the CLUT size */ - tmp1 = CLUTCfg.Size << 8; + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); - /* Prepare the value to be wrote to the FGPFCCR register */ - tmp |= (CLUTCfg.CLUTColorMode | tmp1); - - /* Write to DMA2D FGPFCCR register */ - hdma2d->Instance->FGPFCCR = tmp; - } - return HAL_OK; } + /** - * @brief Enable the DMA2D CLUT Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * @brief Configure the line watermark. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Line: Line Watermark configuration (maximum 16-bit long value expected). + * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. + * @note The transfer watermark interrupt is disabled once it has occurred. * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ + +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) +{ /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_LINEWATERMARK(Line)); - if(LayerIdx == 0) + if (Line > DMA2D_LWR_LW) { - /* Enable the CLUT loading for the background */ - hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START; + return HAL_ERROR; } else - { - /* Enable the CLUT loading for the foreground */ - hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START; - } + { + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; - return HAL_OK; + /* Sets the Line watermark configuration */ + WRITE_REG(hdma2d->Instance->LWR, Line); + + /* Enable the Line interrupt */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; + } } /** - * @brief Disable the DMA2D CLUT Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * @brief Enable DMA2D dead time feature. + * @param hdma2d: DMA2D handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) { - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - - if(LayerIdx == 0) - { - /* Disable the CLUT loading for the background */ - hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START; - } - else - { - /* Disable the CLUT loading for the foreground */ - hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START; - } - + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR EN bit */ + SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + return HAL_OK; } /** - * @brief Define the configuration of the line watermark . - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Line: Line Watermark configuration. + * @brief Disable DMA2D dead time feature. + * @param hdma2d: DMA2D handle. * @retval HAL status */ - -HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) { - /* Process locked */ + /* Process Locked */ __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_DMA2D_LineWatermark(Line)); - /* Sets the Line watermark configuration */ - DMA2D->LWR = (uint32_t)Line; - - /* Initialize the DMA2D state*/ + /* Clear DMA2D_AMTCR EN bit */ + CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Configure dead time. + * @note The dead time value represents the guaranteed minimum number of cycles between + * two consecutive transactions on the AHB bus. + * @param hdma2d: DMA2D handle. + * @param DeadTime: dead time value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR DT field */ + MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT)); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; } /** * @} */ + -/** @defgroup DMA2D_Group4 Peripheral State functions +/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions * @brief Peripheral State functions * @verbatim @@ -1144,8 +1631,8 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32 =============================================================================== [..] This subsection provides functions allowing to : - (+) Check the DMA2D state - (+) Get error code + (+) Get the DMA2D state + (+) Get the DMA2D error code @endverbatim * @{ @@ -1176,11 +1663,19 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) /** * @} */ + +/** + * @} + */ + +/** @defgroup DMA2D_Private_Functions DMA2D Private Functions + * @{ + */ /** - * @brief Set the DMA2D Transfer parameter. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @brief Set the DMA2D transfer parameters. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the specified DMA2D. * @param pdata: The source memory Buffer address * @param DstAddress: The destination memory Buffer address @@ -1195,14 +1690,12 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ uint32_t tmp2 = 0; uint32_t tmp3 = 0; uint32_t tmp4 = 0; - - tmp = Width << 16; - + /* Configure DMA2D data size */ - hdma2d->Instance->NLR = (Height | tmp); + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); /* Configure DMA2D destination address */ - hdma2d->Instance->OMAR = DstAddress; + WRITE_REG(hdma2d->Instance->OMAR, DstAddress); /* Register to memory DMA2D mode selected */ if (hdma2d->Init.Mode == DMA2D_R2M) @@ -1212,23 +1705,23 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ tmp3 = pdata & DMA2D_OCOLR_GREEN_1; tmp4 = pdata & DMA2D_OCOLR_BLUE_1; - /* Prepare the value to be wrote to the OCOLR register according to the color mode */ - if (hdma2d->Init.ColorMode == DMA2D_ARGB8888) + /* Prepare the value to be written to the OCOLR register according to the color mode */ + if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) { tmp = (tmp3 | tmp2 | tmp1| tmp4); } - else if (hdma2d->Init.ColorMode == DMA2D_RGB888) + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) { tmp = (tmp3 | tmp2 | tmp4); } - else if (hdma2d->Init.ColorMode == DMA2D_RGB565) + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) { tmp2 = (tmp2 >> 19); tmp3 = (tmp3 >> 10); tmp4 = (tmp4 >> 3 ); tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); } - else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555) + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) { tmp1 = (tmp1 >> 31); tmp2 = (tmp2 >> 19); @@ -1236,7 +1729,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ tmp4 = (tmp4 >> 3 ); tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); } - else /* DMA2D_CMode = DMA2D_ARGB4444 */ + else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ { tmp1 = (tmp1 >> 28); tmp2 = (tmp2 >> 20); @@ -1245,12 +1738,12 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4); } /* Write to DMA2D OCOLR register */ - hdma2d->Instance->OCOLR = tmp; + WRITE_REG(hdma2d->Instance->OCOLR, tmp); } else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ { /* Configure DMA2D source address */ - hdma2d->Instance->FGMAR = pdata; + WRITE_REG(hdma2d->Instance->FGMAR, pdata); } } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h index 7ec4d72c40a..1bf1fed0cb0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dma2d.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @defgroup DMA2D DMA2D +/** @addtogroup DMA2D DMA2D * @brief DMA2D HAL module driver * @{ */ @@ -83,10 +83,10 @@ typedef struct { uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ - uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode. - This parameter can be one value of @ref DMA2D_CLUT_CM */ + uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. + This parameter can be one value of @ref DMA2D_CLUT_CM. */ - uint32_t Size; /*!< configures the DMA2D CLUT size. + uint32_t Size; /*!< Configures the DMA2D CLUT size. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ } DMA2D_CLUTCfgTypeDef; @@ -95,35 +95,67 @@ typedef struct */ typedef struct { - uint32_t Mode; /*!< configures the DMA2D transfer mode. - This parameter can be one value of @ref DMA2D_Mode */ + uint32_t Mode; /*!< Configures the DMA2D transfer mode. + This parameter can be one value of @ref DMA2D_Mode. */ - uint32_t ColorMode; /*!< configures the color format of the output image. - This parameter can be one value of @ref DMA2D_Color_Mode */ + uint32_t ColorMode; /*!< Configures the color format of the output image. + This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ uint32_t OutputOffset; /*!< Specifies the Offset value. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ +#if defined (DMA2D_OPFCCR_AI) + uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. + This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ +#endif /* DMA2D_OPFCCR_AI */ + +#if defined (DMA2D_OPFCCR_RBS) + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) + for the output pixel format converter. + This parameter can be one value of @ref DMA2D_RB_Swap. */ +#endif /* DMA2D_OPFCCR_RBS */ + } DMA2D_InitTypeDef; + /** * @brief DMA2D Layer structure definition */ typedef struct { - uint32_t InputOffset; /*!< configures the DMA2D foreground offset. + uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ - uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode . - This parameter can be one value of @ref DMA2D_Input_Color_Mode */ - - uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode. - This parameter can be one value of @ref DMA2D_ALPHA_MODE */ + uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. + This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ + + uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. + This parameter can be one value of @ref DMA2D_Alpha_Mode. */ + + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. + @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between + Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where + - InputAlpha[24:31] is the alpha value ALPHA[0:7] + - InputAlpha[16:23] is the red value RED[0:7] + - InputAlpha[8:15] is the green value GREEN[0:7] + - InputAlpha[0:7] is the blue value BLUE[0:7]. */ + +#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) + uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. + This parameter can be one value of @ref DMA2D_Alpha_Inverted. + This feature is only available on devices : + STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/ + +#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */ - uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode. - This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF - in case of A8 or A4 color mode (ARGB). - Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ +#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS) + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). + This parameter can be one value of @ref DMA2D_RB_Swap + This feature is only available on devices : + STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/ +#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */ + } DMA2D_LayerCfgTypeDef; /** @@ -131,12 +163,12 @@ typedef struct */ typedef enum { - HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */ - HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */ - HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */ + HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ + HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ + HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ }HAL_DMA2D_StateTypeDef; /** @@ -144,21 +176,21 @@ typedef enum */ typedef struct __DMA2D_HandleTypeDef { - DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */ - - DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */ + DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ + + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ - void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */ - - void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */ + void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ + + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ - HAL_LockTypeDef Lock; /*!< DMA2D Lock */ - - __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */ - - __IO uint32_t ErrorCode; /*!< DMA2D Error code */ + HAL_LockTypeDef Lock; /*!< DMA2D lock. */ + + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ + + __IO uint32_t ErrorCode; /*!< DMA2D error code. */ } DMA2D_HandleTypeDef; /** * @} @@ -172,10 +204,11 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Error_Code DMA2D Error Code * @{ */ -#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */ -#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ +#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */ +#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */ +#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ /** * @} */ @@ -183,135 +216,126 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Mode DMA2D Mode * @{ */ -#define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */ -#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */ -#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */ -#define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */ +#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ +#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ /** * @} */ -/** @defgroup DMA2D_Color_Mode DMA2D Color Mode +/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode * @{ */ -#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */ -#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */ -#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */ -#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */ -#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */ +#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ +#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ /** * @} */ -/** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE - * @{ - */ -#define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */ -/** - * @} - */ - -/** @defgroup DMA2D_SIZE DMA2D SIZE - * @{ - */ -#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */ -#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */ -/** - * @} - */ - -/** @defgroup DMA2D_Offset DMA2D Offset - * @{ - */ -#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ -/** - * @} - */ - /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode * @{ */ -#define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */ -#define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */ -#define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */ -#define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */ -#define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */ -#define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */ -#define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */ -#define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */ -#define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */ -#define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */ -#define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */ +#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */ +#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */ +#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */ +#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */ +#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */ +#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */ +#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */ +#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */ +#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */ +#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */ +#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */ /** * @} */ -/** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE +/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode * @{ */ -#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */ -#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */ -#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value +#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ +#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */ +#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value with original alpha channel value */ /** * @} */ -/** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM +#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) +/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion * @{ */ -#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */ -#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */ +#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ +#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */ /** * @} */ +#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */ -/** @defgroup DMA2D_Size_Clut DMA2D Size Clut +#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS) +/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap * @{ */ -#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */ +#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */ +#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */ /** * @} - */ + */ +#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */ -/** @defgroup DMA2D_DeadTime DMA2D DeadTime +/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode * @{ */ -#define LINE_WATERMARK DMA2D_LWR_LW +#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */ +#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */ /** * @} */ + /** @defgroup DMA2D_Interrupts DMA2D Interrupts * @{ */ -#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ -#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */ -#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */ -#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ -#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ -#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ +#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ +#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ +#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ +#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ +#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ +#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ +/** + * @} + */ + +/** @defgroup DMA2D_Flags DMA2D Flags + * @{ + */ +#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ +#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ +#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ +#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ +#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ +#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ /** * @} */ - -/** @defgroup DMA2D_Flag DMA2D Flag + +/** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ -#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ -#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */ -#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */ -#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ -#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ -#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ /** * @} */ + /** * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros ------------------------------------------------------------*/ /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros * @{ */ @@ -329,22 +353,16 @@ typedef struct __DMA2D_HandleTypeDef */ #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) -/** - * @brief Disable the DMA2D. - * @param __HANDLE__: DMA2D handle - * @retval None. - */ -#define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START) /* Interrupt & Flag management */ /** * @brief Get the DMA2D pending flags. * @param __HANDLE__: DMA2D handle - * @param __FLAG__: Get the specified flag. + * @param __FLAG__: flag to check. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag - * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag - * @arg DMA2D_FLAG_CAE: C-LUT access error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag * @arg DMA2D_FLAG_TW: Transfer Watermark flag * @arg DMA2D_FLAG_TC: Transfer complete flag * @arg DMA2D_FLAG_TE: Transfer error flag @@ -353,13 +371,13 @@ typedef struct __DMA2D_HandleTypeDef #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** - * @brief Clears the DMA2D pending flags. + * @brief Clear the DMA2D pending flags. * @param __HANDLE__: DMA2D handle * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag - * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag - * @arg DMA2D_FLAG_CAE: C-LUT access error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag * @arg DMA2D_FLAG_TW: Transfer Watermark flag * @arg DMA2D_FLAG_TC: Transfer complete flag * @arg DMA2D_FLAG_TE: Transfer error flag @@ -368,13 +386,13 @@ typedef struct __DMA2D_HandleTypeDef #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) /** - * @brief Enables the specified DMA2D interrupts. + * @brief Enable the specified DMA2D interrupts. * @param __HANDLE__: DMA2D handle * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask - * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask - * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask * @arg DMA2D_IT_TC: Transfer complete interrupt mask * @arg DMA2D_IT_TE: Transfer error interrupt mask @@ -383,13 +401,13 @@ typedef struct __DMA2D_HandleTypeDef #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** - * @brief Disables the specified DMA2D interrupts. + * @brief Disable the specified DMA2D interrupts. * @param __HANDLE__: DMA2D handle * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask - * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask - * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask * @arg DMA2D_IT_TC: Transfer complete interrupt mask * @arg DMA2D_IT_TE: Transfer error interrupt mask @@ -398,33 +416,48 @@ typedef struct __DMA2D_HandleTypeDef #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** - * @brief Checks whether the specified DMA2D interrupt has occurred or not. + * @brief Check whether the specified DMA2D interrupt source is enabled or not. * @param __HANDLE__: DMA2D handle * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask - * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask - * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask * @arg DMA2D_IT_TC: Transfer complete interrupt mask * @arg DMA2D_IT_TE: Transfer error interrupt mask - * @retval The state of INTERRUPT. + * @retval The state of INTERRUPT source. */ #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions +/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions * @{ */ + +/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + /* Initialization and de-initialization functions *******************************/ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); -void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); -void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); + +/** + * @} + */ + +/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions + * @{ + */ + /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); @@ -433,85 +466,146 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); -/* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); - -/* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); /** * @} */ -/* Private types -------------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Types DMA2D Private Types +/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions * @{ */ +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); + /** * @} - */ + */ -/* Private defines -------------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Defines DMA2D Private Defines +/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions * @{ */ +/* Peripheral State functions ***************************************************/ +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); + /** * @} */ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Variables DMA2D Private Variables +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark * @{ */ +#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ +/** + * @} + */ + +/** @defgroup DMA2D_Color_Value DMA2D Color Value + * @{ + */ +#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */ +/** + * @} + */ +/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers + * @{ + */ +#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */ /** * @} */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Constants DMA2D Private Constants + +/** @defgroup DMA2D_Offset DMA2D Offset * @{ */ - +#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ /** * @} */ + +/** @defgroup DMA2D_Size DMA2D Size + * @{ + */ +#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ +#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ +/** + * @} + */ + +/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size + * @{ + */ +#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */ +/** + * @} + */ + +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA2D_Private_Macros DMA2D Private Macros * @{ */ -#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER) +#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) -#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \ - ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \ - ((MODE_ARGB) == DMA2D_ARGB4444)) -#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE) +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) +#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) -#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \ - ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \ - ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \ - ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \ - ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \ - ((INPUT_CM) == CM_A4)) +#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ + ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ + ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ + ((INPUT_CM) == DMA2D_INPUT_A4)) #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ ((AlphaMode) == DMA2D_COMBINE_ALPHA)) + +#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ + ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) + +#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ + ((RB_Swap) == DMA2D_RB_SWAP)) + #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) -#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) +#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) @@ -522,24 +616,6 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); * @} */ -/* Private functions prototypes ---------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Functions DMA2D Private Functions - * @{ - */ - -/** - * @} - */ - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c index a498113142a..165b6791db5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: @@ -17,17 +17,17 @@ The DMA Extension HAL driver can be used as follows: (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. - + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. - -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. -@- In Multi (Double) buffer mode, it is possible to update the base address for - the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -79,40 +79,6 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -/** - * @brief Set the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} - /** * @} */ @@ -126,7 +92,7 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres /** @addtogroup DMAEx_Exported_Functions_Group1 * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### =============================================================================== @@ -154,39 +120,46 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) { - /* Process Locked */ - __HAL_LOCK(hdma); - - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { - hdma->State = HAL_DMA_STATE_BUSY_MEM0; + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; } - /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + else { - hdma->State = HAL_DMA_STATE_BUSY_MEM1; + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Enable the double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Return error status */ + status = HAL_BUSY; + } } - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Enable the double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - - return HAL_OK; + return status; } /** @@ -201,54 +174,66 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) { - /* Process Locked */ - __HAL_LOCK(hdma); - - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { - hdma->State = HAL_DMA_STATE_BUSY_MEM0; + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; } - /* Current memory buffer used is Memory 1 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) { - hdma->State = HAL_DMA_STATE_BUSY_MEM1; + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Enable the Double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); } - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Enable the Double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); - - /* Enable the Half transfer interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); - - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); - - /* Enable the fifo Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE); - - /* Enable the direct mode Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - - return HAL_OK; + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; } /** @@ -277,7 +262,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre /* change the memory1 address */ hdma->Instance->M1AR = Address; } - + return HAL_OK; } @@ -285,6 +270,48 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre * @} */ +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h index 16516c3342d..1006992dc63 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,14 +65,52 @@ */ typedef enum { - MEMORY0 = 0x00, /*!< Memory 0 */ - MEMORY1 = 0x01, /*!< Memory 1 */ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ }HAL_DMA_MemoryTypeDef; /** * @} */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMAEx_Channel_selection DMA Channel selection + * @brief DMAEx channel selection + * @{ + */ +#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/ +#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/ +#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/ +#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/ +#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/ +#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/ +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions @@ -96,6 +134,42 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre /** * @} */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10) || \ + ((CHANNEL) == DMA_CHANNEL_11) || \ + ((CHANNEL) == DMA_CHANNEL_12) || \ + ((CHANNEL) == DMA_CHANNEL_13) || \ + ((CHANNEL) == DMA_CHANNEL_14) || \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMAEx_Private_Functions DMAEx Private Functions diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.c new file mode 100644 index 00000000000..785795d217f --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.c @@ -0,0 +1,2266 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dsi.c + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief DSI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DSI peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ +/** @addtogroup DSI + * @{ + */ + +#ifdef HAL_DSI_MODULE_ENABLED + +#if defined (STM32F769xx) || defined (STM32F779xx) + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup DSI_Private_Constants + * @{ + */ +#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */ + +#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ + DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ + DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ + DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) +#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) +#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX +#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX +#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) +#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE +#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE +#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE +#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE +#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Generic DSI packet header configuration + * @param DSIx: Pointer to DSI register base + * @param ChannelID: Virtual channel ID of the header packet + * @param DataType: Packet data type of the header packet + * This parameter can be any value of : + * @ref DSI_SHORT_WRITE_PKT_Data_Type + * or @ref DSI_LONG_WRITE_PKT_Data_Type + * or @ref DSI_SHORT_READ_PKT_Data_Type + * or DSI_MAX_RETURN_PKT_SIZE + * @param Data0: Word count LSB + * @param Data1: Word count MSB + * @retval None + */ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, + uint32_t ChannelID, + uint32_t DataType, + uint32_t Data0, + uint32_t Data1) +{ + /* Update the DSI packet header with new information */ + DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16)); +} + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DSI_Exported_Functions + * @{ + */ + +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DSI + (+) De-initialize the DSI + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DSI according to the specified + * parameters in the DSI_InitTypeDef and create the associated handle. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) +{ + uint32_t tickstart = 0; + uint32_t unitIntervalx4 = 0; + uint32_t tempIDF = 0; + + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); + assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); + assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); + assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); + assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); + + if(hdsi->State == HAL_DSI_STATE_RESET) + { + /* Initialize the low level hardware */ + HAL_DSI_MspInit(hdsi); + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /**************** Turn on the regulator and enable the DSI PLL ****************/ + + /* Enable the regulator */ + __HAL_DSI_REG_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the regulator is ready */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the PLL division factors */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16)); + + /* Enable the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /*************************** Set the PHY parameters ***************************/ + + /* D-PHY clock and digital enable*/ + hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + + /* Configure the number of active data lanes */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; + hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; + + /************************ Set the DSI clock parameters ************************/ + + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv; + + /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ + /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ + /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ + tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1; + unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV); + + /* Set the bit period in high-speed mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4; + hdsi->Instance->WPCR[0] |= unitIntervalx4; + + /****************************** Error management *****************************/ + + /* Disable all error interrupts and reset the Error Mask */ + hdsi->Instance->IER[0] = 0; + hdsi->Instance->IER[1] = 0; + hdsi->ErrorMsk = 0; + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initializes the DSI peripheral registers to their default reset + * values. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) +{ + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* D-PHY clock and digital disable */ + hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Disable the regulator */ + __HAL_DSI_REG_DISABLE(hdsi); + + /* DeInit the low level hardware */ + HAL_DSI_MspDeInit(hdsi); + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Return the DSI error code + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval DSI Error Code + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +{ + /* Get the error code */ + return hdsi->ErrorCode; +} + +/** + * @brief Enable the error monitor flags + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ActiveErrors: indicates which error interrupts will be enabled. + * This parameter can be any combination of @ref DSI_Error_Data_Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + hdsi->Instance->IER[0] = 0; + hdsi->Instance->IER[1] = 0; + + /* Store active errors to the handle */ + hdsi->ErrorMsk = ActiveErrors; + + if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_PHY ) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle DSI interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handles DSI interrupt request. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) +{ + uint32_t ErrorStatus0, ErrorStatus1; + + /* Tearing Effect Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) + { + /* Clear the Tearing Effect Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); + + /* Tearing Effect Callback */ + HAL_DSI_TearingEffectCallback(hdsi); + } + } + + /* End of Refresh Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) + { + /* Clear the End of Refresh Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); + + /* End of Refresh Callback */ + HAL_DSI_EndOfRefreshCallback(hdsi); + } + } + + /* Error Interrupts management ***********************************************/ + if(hdsi->ErrorMsk != 0) + { + ErrorStatus0 = hdsi->Instance->ISR[0]; + ErrorStatus0 &= hdsi->Instance->IER[0]; + ErrorStatus1 = hdsi->Instance->ISR[1]; + ErrorStatus1 &= hdsi->Instance->IER[1]; + + if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; + } + + if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; + } + + if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_TX; + } + + if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_RX; + } + + if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; + } + + if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; + } + + if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; + } + + if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; + } + + if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; + } + + if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; + } + + /* Check only selected errors */ + if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) + { + /* DSI error interrupt user callback */ + HAL_DSI_ErrorCallback(hdsi); + } + } +} + +/** + * @brief Tearing Effect DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_TearingEffectCallback could be implemented in the user file + */ +} + +/** + * @brief End of Refresh DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_EndOfRefreshCallback could be implemented in the user file + */ +} + +/** + * @brief Operation Error DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) + (+) + (+) + +@endverbatim + * @{ + */ + +/** + * @brief Configure the Generic interface read-back Virtual Channel ID. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelID: Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCID register */ + hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; + hdsi->Instance->GVCIDR |= VirtualChannelID; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select video mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); + assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); + assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); + assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); + assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); + assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); + assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); + assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); + assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); + assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); + assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); + /* Check the LooselyPacked variant only in 18-bit mode */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); + } + + /* Select video mode by resetting CMDM and DSIM bits */ + hdsi->Instance->MCR &= ~DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + + /* Configure the video mode transmission type */ + hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; + hdsi->Instance->VMCR |= VidCfg->Mode; + + /* Configure the video packet size */ + hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; + hdsi->Instance->VPCR |= VidCfg->PacketSize; + + /* Set the chunks number to be transmitted through the DSI link */ + hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; + hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; + + /* Set the size of the null packet */ + hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; + hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1); + + /* Enable/disable the loosely packed variant to 18-bit configuration */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; + hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; + } + + /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ + hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; + hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; + + /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ + hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; + hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; + + /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ + hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; + hdsi->Instance->VLCR |= VidCfg->HorizontalLine; + + /* Set the Vertical Synchronization Active (VSA) */ + hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; + hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; + + /* Set the Vertical Back Porch (VBP)*/ + hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; + hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; + + /* Set the Vertical Front Porch (VFP)*/ + hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; + hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; + + /* Set the Vertical Active period*/ + hdsi->Instance->VVACR &= ~DSI_VVACR_VA; + hdsi->Instance->VVACR |= VidCfg->VerticalActive; + + /* Configure the command transmission mode */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; + hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; + + /* Low power largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; + hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16); + + /* Low power VACT largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; + hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; + + /* Enable LP transition in HFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; + + /* Enable LP transition in HBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; + + /* Enable LP transition in VACT period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; + + /* Enable LP transition in VFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; + + /* Enable LP transition in VBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; + + /* Enable LP transition in vertical sync period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; + + /* Enable the request for an acknowledge response at the end of a frame */ + hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; + hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select adapted command mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); + assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); + assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); + assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); + assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); + assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); + assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); + + /* Select command mode by setting CMDM and DSIM bits */ + hdsi->Instance->MCR |= DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1); + + /* Configure the maximum allowed size for write memory command */ + hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; + hdsi->Instance->LCCR |= CmdCfg->CommandSize; + + /* Configure the tearing effect source and polarity and select the refresh mode */ + hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); + hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); + + /* Configure the tearing effect acknowledge request */ + hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; + hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; + + /* Enable the Tearing Effect interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); + + /* Enable the End of Refresh interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure command transmission mode: High-speed or Low-power + * and enable/disable acknowledge request after packet transmission + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * the DSI command transmission mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); + assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); + assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); + assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); + assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); + assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); + assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); + assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); + assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); + assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); + assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); + assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); + assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); + + /* Select High-speed or Low-power for command transmission */ + hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ + DSI_CMCR_GSW1TX |\ + DSI_CMCR_GSW2TX |\ + DSI_CMCR_GSR0TX |\ + DSI_CMCR_GSR1TX |\ + DSI_CMCR_GSR2TX |\ + DSI_CMCR_GLWTX |\ + DSI_CMCR_DSW0TX |\ + DSI_CMCR_DSW1TX |\ + DSI_CMCR_DSR0TX |\ + DSI_CMCR_DLWTX |\ + DSI_CMCR_MRDPS); + hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ + LPCmd->LPGenShortWriteOneP |\ + LPCmd->LPGenShortWriteTwoP |\ + LPCmd->LPGenShortReadNoP |\ + LPCmd->LPGenShortReadOneP |\ + LPCmd->LPGenShortReadTwoP |\ + LPCmd->LPGenLongWrite |\ + LPCmd->LPDcsShortWriteNoP |\ + LPCmd->LPDcsShortWriteOneP |\ + LPCmd->LPDcsShortReadNoP |\ + LPCmd->LPDcsLongWrite |\ + LPCmd->LPMaxReadPacket); + + /* Configure the acknowledge request after each packet transmission */ + hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; + hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the flow control parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param FlowControl: flow control feature(s) to be enabled. + * This parameter can be any combination of @ref DSI_FlowControl. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); + + /* Set the DSI Host Protocol Configuration Register */ + hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; + hdsi->Instance->PCR |= FlowControl; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI PHY timer parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * the DSI PHY timing parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) +{ + uint32_t maxTime; + /* Process locked */ + __HAL_LOCK(hdsi); + + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; + + /* Clock lane timer configuration */ + + /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two + High-Speed transmission. + To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed + to Low-Power and from Low-Power to High-Speed. + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. + + Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. + */ + hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); + hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16)); + + /* Data lane timer configuration */ + hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); + hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24)); + + /* Configure the wait period to request HS transmission after a stop state */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; + hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI HOST timeout parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * the DSI host timeout parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Set the timeout clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; + hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8); + + /* High-speed transmission timeout */ + hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT; + hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16); + + /* Low-power reception timeout */ + hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT; + hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout; + + /* High-speed read timeout */ + hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT; + hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout; + + /* Low-power read timeout */ + hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT; + hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout; + + /* High-speed write timeout */ + hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT; + hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout; + + /* High-speed write presp mode */ + hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM; + hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode; + + /* Low-speed write timeout */ + hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT; + hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout; + + /* BTA timeout */ + hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT; + hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Enable the DSI host */ + __HAL_DSI_ENABLE(hdsi); + + /* Enable the DSI wrapper */ + __HAL_DSI_WRAPPER_ENABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Refresh the display in command mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the display */ + hdsi->Instance->WCR |= DSI_WCR_LTDCEN; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Controls the display color mode in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ColorMode: Color mode (full or 8-colors). + * This parameter can be any value of @ref DSI_Color_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_MODE(ColorMode)); + + /* Update the display color mode */ + hdsi->Instance->WCR &= ~DSI_WCR_COLM; + hdsi->Instance->WCR |= ColorMode; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Control the display shutdown in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * This parameter can be any value of @ref DSI_ShutDown + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHUT_DOWN(Shutdown)); + + /* Update the display Shutdown */ + hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; + hdsi->Instance->WCR |= Shutdown; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief DCS or Generic short write command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI short packet data type. + * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code. + * @param Param2: DSC parameter or second generic parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + Param1, + Param2); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief DCS or Generic long write command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI long packet data type. + * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. + * @param NbParams: Number of parameters. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t* ParametersTable) +{ + uint32_t uicounter = 0; + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/ + while(uicounter < NbParams) + { + if(uicounter == 0x00) + { + hdsi->Instance->GPDR=(Param1 | \ + ((uint32_t)(*(ParametersTable + uicounter)) << 8) | \ + ((uint32_t)(*(ParametersTable + uicounter+1))<<16) | \ + ((uint32_t)(*(ParametersTable + uicounter+2))<<24)); + uicounter += 3; + } + else + { + hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \ + ((uint32_t)(*(ParametersTable + uicounter+1)) << 8) | \ + ((uint32_t)(*(ParametersTable + uicounter+2)) << 16) | \ + ((uint32_t)(*(ParametersTable + uicounter+3)) << 24)); + uicounter+=4; + } + } + + /* Configure the packet to send a long DCS command */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + ((NbParams+1)&0x00FF), + (((NbParams+1)&0xFF00)>>8)); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Read command (DCS or generic) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelNbr: Virtual channel ID + * @param Array: pointer to a buffer to store the payload of a read back operation. + * @param Size: Data size to be read (in byte). + * @param Mode: DSI read packet data type. + * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. + * @param DCSCmd: DCS get/read command. + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); + + if(Size > 2) + { + /* set max return packet size */ + HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF)); + } + + /* Configure the packet to read command */ + if (Mode == DSI_DCS_SHORT_PKT_READ) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check that the payload read FIFO is not empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Get the first byte */ + *((uint32_t *)Array) = (hdsi->Instance->GPDR); + if (Size > 4) + { + Size -= 4; + Array += 4; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Get the remaining bytes if any */ + while(((int)(Size)) > 0) + { + if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0) + { + *((uint32_t *)Array) = (hdsi->Instance->GPDR); + Size -= 4; + Array += 4; + } + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* ULPS Request on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_URDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the D-PHY active lanes enter into ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Exit ULPS on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_UEDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Clock lane configuration: no more HS request */ + hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; + + /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR); + + /* ULPS Request on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Exit ULPS on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0; + + /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); + + /* Restore clock lane configuration to HS */ + hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Mode: Pattern generator mode + * This parameter can be one of the following values: + * 0 : Color bars (horizontal or vertical) + * 1 : BER pattern (vertical only) + * @param Orientation: Pattern generator orientation + * This parameter can be one of the following values: + * 0 : Vertical color bars + * 1 : Horizontal color bars + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Configure pattern generator mode and orientation */ + hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); + hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24)); + + /* Enable pattern generator by setting PGE bit */ + hdsi->Instance->VMCR |= DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable pattern generator by clearing PGE bit */ + hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set Slew-Rate And Delay Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CommDelay: Communication delay to be adjusted. + * This parameter can be any value of @ref DSI_Communication_Delay + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param Value: Custom value of the slew-rate or delay + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); + assert_param(IS_DSI_LANE_GROUP(Lane)); + + switch(CommDelay) + { + case DSI_SLEW_RATE_HSTX: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Slew Rate Control on Clock Lane */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL; + hdsi->Instance->WPCR[1] |= Value<<16; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Slew Rate Control on Data Lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL; + hdsi->Instance->WPCR[1] |= Value<<18; + } + break; + case DSI_SLEW_RATE_LPTX: + if(Lane == DSI_CLOCK_LANE) + { + /* Low-Power transmission Slew Rate Compensation on Clock Lane */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL; + hdsi->Instance->WPCR[1] |= Value<<6; + } + else if(Lane == DSI_DATA_LANES) + { + /* Low-Power transmission Slew Rate Compensation on Data Lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL; + hdsi->Instance->WPCR[1] |= Value<<8; + } + break; + case DSI_HS_DELAY: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Delay on Clock Lane */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL; + hdsi->Instance->WPCR[1] |= Value; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Delay on Data Lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL; + hdsi->Instance->WPCR[1] |= Value<<2; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Low-Power Reception Filter Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Low-Power RX low-pass Filtering Tuning */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT; + hdsi->Instance->WPCR[1] |= Frequency<<25; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Activate an additional current path on all lanes to meet the SDDTx parameter + * defined in the MIPI D-PHY specification + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Activate/Disactivate additional current path on all lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC; + hdsi->Instance->WPCR[1] |= ((uint32_t)State << 12); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Custom lane pins configuration + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CustomLane: Function to be applyed on selected lane. + * This parameter can be any value of @ref DSI_CustomLane + * @param Lane: select between clock or data lane 0 or data lane 1. + * This parameter can be any value of @ref DSI_Lane_Select + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); + assert_param(IS_DSI_LANE(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(CustomLane) + { + case DSI_SWAP_LANE_PINS: + if(Lane == DSI_CLOCK_LANE) + { + /* Swap pins on clock lane */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 6); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Swap pins on data lane 0 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 7); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Swap pins on data lane 1 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 8); + } + break; + case DSI_INVERT_HS_SIGNAL: + if(Lane == DSI_CLOCK_LANE) + { + /* Invert HS signal on clock lane */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 9); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Invert HS signal on data lane 0 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 10); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Invert HS signal on data lane 1 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 11); + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set custom timing for the PHY + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Timing: PHY timing to be adjusted. + * This parameter can be any value of @ref DSI_PHY_Timing + * @param State: ENABLE or DISABLE + * @param Value: Custom value of the timing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_PHY_TIMING(Timing)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(Timing) + { + case DSI_TCLK_POST: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 27); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST; + hdsi->Instance->WPCR[4] |= Value & DSI_WPCR4_TCLKPOST; + } + + break; + case DSI_TLPX_CLK: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 26); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC; + hdsi->Instance->WPCR[3] |= (Value << 24) & DSI_WPCR3_TLPXC; + } + + break; + case DSI_THS_EXIT: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 25); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT; + hdsi->Instance->WPCR[3] |= (Value << 16) & DSI_WPCR3_THSEXIT; + } + + break; + case DSI_TLPX_DATA: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 24); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD; + hdsi->Instance->WPCR[3] |= (Value << 8) & DSI_WPCR3_TLPXD; + } + + break; + case DSI_THS_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 23); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO; + hdsi->Instance->WPCR[3] |= Value & DSI_WPCR3_THSZERO; + } + + break; + case DSI_THS_TRAIL: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 22); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL; + hdsi->Instance->WPCR[2] |= (Value << 24) & DSI_WPCR2_THSTRAIL; + } + + break; + case DSI_THS_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 21); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP; + hdsi->Instance->WPCR[2] |= (Value << 16) & DSI_WPCR2_THSPREP; + } + + break; + case DSI_TCLK_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 20); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO; + hdsi->Instance->WPCR[2] |= (Value << 8) & DSI_WPCR2_TCLKZERO; + } + + break; + case DSI_TCLK_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 19); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP; + hdsi->Instance->WPCR[2] |= Value & DSI_WPCR2_TCLKPREP; + } + + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force the Clock/Data Lane in TX Stop Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_LANE_GROUP(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + if(Lane == DSI_CLOCK_LANE) + { + /* Force/Unforce the Clock Lane in TX Stop Mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 12); + } + else if(Lane == DSI_DATA_LANES) + { + /* Force/Unforce the Data Lanes in TX Stop Mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 13); + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Forces LP Receiver in Low-Power Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force/Unforce LP Receiver in Low-Power Mode */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM; + hdsi->Instance->WPCR[1] |= ((uint32_t)State << 22); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force Data Lanes in RX Mode after a BTA + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force Data Lanes in RX Mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 16); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable a pull-down on the lanes to prevent from floating states when unused + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Enable/Disable pull-down on lanes */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 18); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Switch off the contention detection on data lanes + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Contention Detection on Data Lanes OFF */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL; + hdsi->Instance->WPCR[0] |= ((uint32_t)State << 14); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DSI state. + (+) Get error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DSI state + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL state + */ +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +{ + return hdsi->State; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /*STM32F769xx | STM32F779xx */ +#endif /* HAL_DSI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.h new file mode 100644 index 00000000000..5e8a3007ba6 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.h @@ -0,0 +1,1242 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dsi.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief Header file of DSI HAL module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DSI_H +#define __STM32F7xx_HAL_DSI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32F769xx) || defined (STM32F779xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DSI DSI + * @brief DSI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DSI Init Structure definition + */ +typedef struct +{ + uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control + This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ + + uint32_t TXEscapeCkdiv; /*!< TX Escape clock division + The values 0 and 1 stop the TX_ESC clock generation */ + + uint32_t NumberOfLanes; /*!< Number of lanes + This parameter can be any value of @ref DSI_Number_Of_Lanes */ + +}DSI_InitTypeDef; + +/** + * @brief DSI PLL Clock structure definition + */ +typedef struct +{ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ + + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ + + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ + +}DSI_PLLInitTypeDef; + +/** + * @brief DSI Video mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using + 18-bit configuration). + This parameter can be any value of @ref DSI_LooselyPacked */ + + uint32_t Mode; /*!< Video mode type + This parameter can be any value of @ref DSI_Video_Mode_Type */ + + uint32_t PacketSize; /*!< Video packet size */ + + uint32_t NumberOfChunks; /*!< Number of chunks */ + + uint32_t NullPacketSize; /*!< Null packet size */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ + + uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ + + uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ + + uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ + + uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ + + uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ + + uint32_t VerticalActive; /*!< Vertical active duration */ + + uint32_t LPCommandEnable; /*!< Low-power command enable + This parameter can be any value of @ref DSI_LP_Command */ + + uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VSA, VBP and VFP regions */ + + uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VACT region */ + + uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable + This parameter can be any value of @ref DSI_LP_HFP */ + + uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable + This parameter can be any value of @ref DSI_LP_HBP */ + + uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable + This parameter can be any value of @ref DSI_LP_VACT */ + + uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable + This parameter can be any value of @ref DSI_LP_VFP */ + + uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable + This parameter can be any value of @ref DSI_LP_VBP */ + + uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable + This parameter can be any value of @ref DSI_LP_VSYNC */ + + uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable + This parameter can be any value of @ref DSI_FBTA_acknowledge */ + +}DSI_VidCfgTypeDef; + +/** + * @brief DSI Adapted command mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in + pixels. This parameter can be any value between 0x00 and 0xFFFF */ + + uint32_t TearingEffectSource; /*!< Tearing effect source + This parameter can be any value of @ref DSI_TearingEffectSource */ + + uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity + This parameter can be any value of @ref DSI_TearingEffectPolarity */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted + This parameter can be any value of @ref DSI_Vsync_Polarity */ + + uint32_t AutomaticRefresh; /*!< Automatic refresh mode + This parameter can be any value of @ref DSI_AutomaticRefresh */ + + uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable + This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ + +}DSI_CmdCfgTypeDef; + +/** + * @brief DSI command transmission mode configuration + */ +typedef struct +{ + uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ + + uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ + + uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ + + uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ + + uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ + + uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ + + uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ + + uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ + + uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ + + uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ + + uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ + + uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission + This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ + + uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable + This parameter can be any value of @ref DSI_AcknowledgeRequest */ + +}DSI_LPCmdTypeDef; + +/** + * @brief DSI PHY Timings definition + */ +typedef struct +{ + uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed + to low-power transmission */ + + uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed + to low-power transmission */ + + uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ + + uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the + Stop state */ + +}DSI_PHY_TimerTypeDef; + +/** + * @brief DSI HOST Timeouts definition + */ +typedef struct +{ + uint32_t TimeoutCkdiv; /*!< Time-out clock division */ + + uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ + + uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ + + uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ + + uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ + + uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ + + uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode + This parameter can be any value of @ref DSI_HS_PrespMode */ + + uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ + + uint32_t BTATimeout; /*!< BTA time-out */ + +}DSI_HOST_TimeoutTypeDef; + +/** + * @brief DSI States Structure definition + */ +typedef enum +{ + HAL_DSI_STATE_RESET = 0x00U, + HAL_DSI_STATE_READY = 0x01U, + HAL_DSI_STATE_ERROR = 0x02U, + HAL_DSI_STATE_BUSY = 0x03U, + HAL_DSI_STATE_TIMEOUT = 0x04U +}HAL_DSI_StateTypeDef; + +/** + * @brief DSI Handle Structure definition + */ +typedef struct +{ + DSI_TypeDef *Instance; /*!< Register base address */ + DSI_InitTypeDef Init; /*!< DSI required parameters */ + HAL_LockTypeDef Lock; /*!< DSI peripheral status */ + __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ + __IO uint32_t ErrorCode; /*!< DSI Error code */ + uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ +}DSI_HandleTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_DCS_Command DSI DCS Command + * @{ + */ +#define DSI_ENTER_IDLE_MODE 0x39U +#define DSI_ENTER_INVERT_MODE 0x21U +#define DSI_ENTER_NORMAL_MODE 0x13U +#define DSI_ENTER_PARTIAL_MODE 0x12U +#define DSI_ENTER_SLEEP_MODE 0x10U +#define DSI_EXIT_IDLE_MODE 0x38U +#define DSI_EXIT_INVERT_MODE 0x20U +#define DSI_EXIT_SLEEP_MODE 0x11U +#define DSI_GET_3D_CONTROL 0x3FU +#define DSI_GET_ADDRESS_MODE 0x0BU +#define DSI_GET_BLUE_CHANNEL 0x08U +#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU +#define DSI_GET_DISPLAY_MODE 0x0DU +#define DSI_GET_GREEN_CHANNEL 0x07U +#define DSI_GET_PIXEL_FORMAT 0x0CU +#define DSI_GET_POWER_MODE 0x0AU +#define DSI_GET_RED_CHANNEL 0x06U +#define DSI_GET_SCANLINE 0x45U +#define DSI_GET_SIGNAL_MODE 0x0EU +#define DSI_NOP 0x00U +#define DSI_READ_DDB_CONTINUE 0xA8U +#define DSI_READ_DDB_START 0xA1U +#define DSI_READ_MEMORY_CONTINUE 0x3EU +#define DSI_READ_MEMORY_START 0x2EU +#define DSI_SET_3D_CONTROL 0x3DU +#define DSI_SET_ADDRESS_MODE 0x36U +#define DSI_SET_COLUMN_ADDRESS 0x2AU +#define DSI_SET_DISPLAY_OFF 0x28U +#define DSI_SET_DISPLAY_ON 0x29U +#define DSI_SET_GAMMA_CURVE 0x26U +#define DSI_SET_PAGE_ADDRESS 0x2BU +#define DSI_SET_PARTIAL_COLUMNS 0x31U +#define DSI_SET_PARTIAL_ROWS 0x30U +#define DSI_SET_PIXEL_FORMAT 0x3AU +#define DSI_SET_SCROLL_AREA 0x33U +#define DSI_SET_SCROLL_START 0x37U +#define DSI_SET_TEAR_OFF 0x34U +#define DSI_SET_TEAR_ON 0x35U +#define DSI_SET_TEAR_SCANLINE 0x44U +#define DSI_SET_VSYNC_TIMING 0x40U +#define DSI_SOFT_RESET 0x01U +#define DSI_WRITE_LUT 0x2DU +#define DSI_WRITE_MEMORY_CONTINUE 0x3CU +#define DSI_WRITE_MEMORY_START 0x2CU +/** + * @} + */ + +/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type + * @{ + */ +#define DSI_VID_MODE_NB_PULSES 0U +#define DSI_VID_MODE_NB_EVENTS 1U +#define DSI_VID_MODE_BURST 2U +/** + * @} + */ + +/** @defgroup DSI_Color_Mode DSI Color Mode + * @{ + */ +#define DSI_COLOR_MODE_FULL 0U +#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM +/** + * @} + */ + +/** @defgroup DSI_ShutDown DSI ShutDown + * @{ + */ +#define DSI_DISPLAY_ON 0U +#define DSI_DISPLAY_OFF DSI_WCR_SHTDN +/** + * @} + */ + +/** @defgroup DSI_LP_Command DSI LP Command + * @{ + */ +#define DSI_LP_COMMAND_DISABLE 0U +#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE +/** + * @} + */ + +/** @defgroup DSI_LP_HFP DSI LP HFP + * @{ + */ +#define DSI_LP_HFP_DISABLE 0U +#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE +/** + * @} + */ + +/** @defgroup DSI_LP_HBP DSI LP HBP + * @{ + */ +#define DSI_LP_HBP_DISABLE 0U +#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VACT DSI LP VACT + * @{ + */ +#define DSI_LP_VACT_DISABLE 0U +#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE +/** + * @} + */ + +/** @defgroup DSI_LP_VFP DSI LP VFP + * @{ + */ +#define DSI_LP_VFP_DISABLE 0 +#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE +/** + * @} + */ + +/** @defgroup DSI_LP_VBP DSI LP VBP + * @{ + */ +#define DSI_LP_VBP_DISABLE 0U +#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VSYNC DSI LP VSYNC + * @{ + */ +#define DSI_LP_VSYNC_DISABLE 0U +#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE +/** + * @} + */ + +/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge + * @{ + */ +#define DSI_FBTAA_DISABLE 0U +#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE +/** + * @} + */ + +/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source + * @{ + */ +#define DSI_TE_DSILINK 0U +#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC +/** + * @} + */ + +/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity + * @{ + */ +#define DSI_TE_RISING_EDGE 0U +#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL +/** + * @} + */ + +/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity + * @{ + */ +#define DSI_VSYNC_FALLING 0U +#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL +/** + * @} + */ + +/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh + * @{ + */ +#define DSI_AR_DISABLE 0U +#define DSI_AR_ENABLE DSI_WCFGR_AR +/** + * @} + */ + +/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request + * @{ + */ +#define DSI_TE_ACKNOWLEDGE_DISABLE 0U +#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE +/** + * @} + */ + +/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request + * @{ + */ +#define DSI_ACKNOWLEDGE_DISABLE 0U +#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP + * @{ + */ +#define DSI_LP_GSW0P_DISABLE 0U +#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP + * @{ + */ +#define DSI_LP_GSW1P_DISABLE 0U +#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP + * @{ + */ +#define DSI_LP_GSW2P_DISABLE 0U +#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP + * @{ + */ +#define DSI_LP_GSR0P_DISABLE 0U +#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP + * @{ + */ +#define DSI_LP_GSR1P_DISABLE 0U +#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP + * @{ + */ +#define DSI_LP_GSR2P_DISABLE 0U +#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite + * @{ + */ +#define DSI_LP_GLW_DISABLE 0U +#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP + * @{ + */ +#define DSI_LP_DSW0P_DISABLE 0U +#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP + * @{ + */ +#define DSI_LP_DSW1P_DISABLE 0U +#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP + * @{ + */ +#define DSI_LP_DSR0P_DISABLE 0U +#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write + * @{ + */ +#define DSI_LP_DLW_DISABLE 0U +#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet + * @{ + */ +#define DSI_LP_MRDP_DISABLE 0U +#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS +/** + * @} + */ + +/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode + * @{ + */ +#define DSI_HS_PM_DISABLE 0U +#define DSI_HS_PM_ENABLE DSI_TCCR3_PM +/** + * @} + */ + + +/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control + * @{ + */ +#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0U +#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR +/** + * @} + */ + +/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes + * @{ + */ +#define DSI_ONE_DATA_LANE 0U +#define DSI_TWO_DATA_LANES 1U +/** + * @} + */ + +/** @defgroup DSI_FlowControl DSI Flow Control + * @{ + */ +#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE +#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE +#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE +#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE +#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ + DSI_FLOW_CONTROL_EOTP_TX) +/** + * @} + */ + +/** @defgroup DSI_Color_Coding DSI Color Coding + * @{ + */ +#define DSI_RGB565 ((uint32_t)0x00000000U) /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ +#define DSI_RGB666 ((uint32_t)0x00000003U) /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ +#define DSI_RGB888 ((uint32_t)0x00000005U) +/** + * @} + */ + +/** @defgroup DSI_LooselyPacked DSI Loosely Packed + * @{ + */ +#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE +#define DSI_LOOSELY_PACKED_DISABLE 0U +/** + * @} + */ + +/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity + * @{ + */ +#define DSI_HSYNC_ACTIVE_HIGH 0U +#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP +/** + * @} + */ + +/** @defgroup DSI_VSYNC_Polarity DSI VSYNC Polarity + * @{ + */ +#define DSI_VSYNC_ACTIVE_HIGH 0U +#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP +/** + * @} + */ + +/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity + * @{ + */ +#define DSI_DATA_ENABLE_ACTIVE_HIGH 0U +#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP +/** + * @} + */ + +/** @defgroup DSI_PLL_IDF DSI PLL IDF + * @{ + */ +#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001U) +#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002U) +#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003U) +#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004U) +#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005U) +#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006U) +#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007U) +/** + * @} + */ + +/** @defgroup DSI_PLL_ODF DSI PLL ODF + * @{ + */ +#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000U) +#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001U) +#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002U) +#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ + +/** @defgroup DSI_Flags DSI Flags + * @{ + */ +#define DSI_FLAG_TE DSI_WISR_TEIF +#define DSI_FLAG_ER DSI_WISR_ERIF +#define DSI_FLAG_BUSY DSI_WISR_BUSY +#define DSI_FLAG_PLLLS DSI_WISR_PLLLS +#define DSI_FLAG_PLLL DSI_WISR_PLLLIF +#define DSI_FLAG_PLLU DSI_WISR_PLLUIF +#define DSI_FLAG_RRS DSI_WISR_RRS +#define DSI_FLAG_RR DSI_WISR_RRIF +/** + * @} + */ + +/** @defgroup DSI_Interrupts DSI Interrupts + * @{ + */ +#define DSI_IT_TE DSI_WIER_TEIE +#define DSI_IT_ER DSI_WIER_ERIE +#define DSI_IT_PLLL DSI_WIER_PLLLIE +#define DSI_IT_PLLU DSI_WIER_PLLUIE +#define DSI_IT_RR DSI_WIER_RRIE +/** + * @} + */ + +/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U) /*!< DCS short write, no parameters */ +#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U) /*!< DCS short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U) /*!< Generic short write, no parameters */ +#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U) /*!< Generic short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U) /*!< Generic short write, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U) /*!< DCS long write */ +#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U) /*!< Generic long write */ +/** + * @} + */ + +/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006U) /*!< DCS short read */ +#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U) /*!< Generic short read, no parameters */ +#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U) /*!< Generic short read, one parameter */ +#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U) /*!< Generic short read, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_Error_Data_Type DSI Error Data Type + * @{ + */ +#define HAL_DSI_ERROR_NONE 0 +#define HAL_DSI_ERROR_ACK ((uint32_t)0x00000001U) /*!< acknowledge errors */ +#define HAL_DSI_ERROR_PHY ((uint32_t)0x00000002U) /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX ((uint32_t)0x00000004U) /*!< transmission error */ +#define HAL_DSI_ERROR_RX ((uint32_t)0x00000008U) /*!< reception error */ +#define HAL_DSI_ERROR_ECC ((uint32_t)0x00000010U) /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC ((uint32_t)0x00000020U) /*!< CRC error */ +#define HAL_DSI_ERROR_PSE ((uint32_t)0x00000040U) /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT ((uint32_t)0x00000080U) /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF ((uint32_t)0x00000100U) /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN ((uint32_t)0x00000200U) /*!< Generic FIFO related errors */ +/** + * @} + */ + +/** @defgroup DSI_Lane_Group DSI Lane Group + * @{ + */ +#define DSI_CLOCK_LANE ((uint32_t)0x00000000U) +#define DSI_DATA_LANES ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup DSI_Communication_Delay DSI Communication Delay + * @{ + */ +#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U) +#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U) +#define DSI_HS_DELAY ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup DSI_CustomLane DSI CustomLane + * @{ + */ +#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000U) +#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup DSI_Lane_Select DSI Lane Select + * @{ + */ +#define DSI_CLOCK_LANE ((uint32_t)0x00000000U) +#define DSI_DATA_LANE0 ((uint32_t)0x00000001U) +#define DSI_DATA_LANE1 ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup DSI_PHY_Timing DSI PHY Timing + * @{ + */ +#define DSI_TCLK_POST ((uint32_t)0x00000000U) +#define DSI_TLPX_CLK ((uint32_t)0x00000001U) +#define DSI_THS_EXIT ((uint32_t)0x00000002U) +#define DSI_TLPX_DATA ((uint32_t)0x00000003U) +#define DSI_THS_ZERO ((uint32_t)0x00000004U) +#define DSI_THS_TRAIL ((uint32_t)0x00000005U) +#define DSI_THS_PREPARE ((uint32_t)0x00000006U) +#define DSI_TCLK_ZERO ((uint32_t)0x00000007U) +#define DSI_TCLK_PREPARE ((uint32_t)0x00000008U) +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @brief Enables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN) + +/** + * @brief Disables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN) + +/** + * @brief Enables the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN) + +/** + * @brief Disable the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN) + +/** + * @brief Enables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN) + +/** + * @brief Disables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN) + +/** + * @brief Enables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN) + +/** + * @brief Disables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN) + +/** + * @brief Get the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_BUSY : Busy Flag + * @arg DSI_FLAG_PLLLS: PLL Lock Status + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RRS : Regulator Ready Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) + +/** + * @brief Clears the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval None + */ +#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) + +/** + * @brief Enables the specified DSI interrupts. + * @param __HANDLE__: DSI handle. + * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DSI interrupts. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DSI interrupt has occurred or not. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * This parameter can be one of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__)) + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Functions DSI Exported Functions + * @{ + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); + +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); + +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DSI_Private_Types DSI Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup DSI_Private_Defines DSI Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Variables DSI Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Constants DSI Private Constants + * @{ + */ +#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037) /*!< Maximum return packet configuration */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DSI_Private_Macros DSI Private Macros + * @{ + */ +#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) +#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ + ((IDF) == DSI_PLL_IN_DIV2) || \ + ((IDF) == DSI_PLL_IN_DIV3) || \ + ((IDF) == DSI_PLL_IN_DIV4) || \ + ((IDF) == DSI_PLL_IN_DIV5) || \ + ((IDF) == DSI_PLL_IN_DIV6) || \ + ((IDF) == DSI_PLL_IN_DIV7)) +#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ + ((ODF) == DSI_PLL_OUT_DIV2) || \ + ((ODF) == DSI_PLL_OUT_DIV4) || \ + ((ODF) == DSI_PLL_OUT_DIV8)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) +#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ + ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ + ((VideoModeType) == DSI_VID_MODE_BURST)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) +#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) +#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) +#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ + ((MODE) == DSI_GEN_LONG_PKT_WRITE)) +#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ + ((Timing) == DSI_TLPX_CLK ) || \ + ((Timing) == DSI_THS_EXIT ) || \ + ((Timing) == DSI_TLPX_DATA ) || \ + ((Timing) == DSI_THS_ZERO ) || \ + ((Timing) == DSI_THS_TRAIL ) || \ + ((Timing) == DSI_THS_PREPARE ) || \ + ((Timing) == DSI_TCLK_ZERO ) || \ + ((Timing) == DSI_TCLK_PREPARE)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /*STM32F769xx | STM32F779xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DSI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c index 3d3cfccc7aa..4d3b009ef34 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_eth.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -68,7 +68,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h index 7da1aede1c0..c674c60014d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_eth.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -313,48 +313,48 @@ * @{ */ /* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001) +#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) -/* ETHERNET Errors */ -#define ETH_SUCCESS ((uint32_t)0) -#define ETH_ERROR ((uint32_t)1) +/* Ethernet Errors */ +#define ETH_SUCCESS ((uint32_t)0U) +#define ETH_ERROR ((uint32_t)1U) -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3) +/* Ethernet DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U) -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) +/* Ethernet DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16) +/* Ethernet DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U) -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) +/* Ethernet DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) -/* ETHERNET DMA Rx descriptors Frame length Shift */ +/* Ethernet DMA Rx descriptors Frame length Shift */ #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */ +/* Ethernet MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */ -/* ETHERNET MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) +/* Ethernet MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) -/* ETHERNET MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) +/* Ethernet MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU) -/* ETHERNET MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) +/* Ethernet MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U) -/* ETHERNET DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) +/* Ethernet DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U) -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8 +/* Ethernet Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 +/* Ethernet Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U /** * @} */ @@ -369,16 +369,16 @@ */ typedef enum { - HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ + HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ + HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ }HAL_ETH_StateTypeDef; /** @@ -594,7 +594,7 @@ typedef struct uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ - /*!< Enhanced ETHERNET DMA PTP Descriptors */ + /*!< Enhanced Ethernet DMA PTP Descriptors */ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ uint32_t Reserved1; /*!< Reserved */ @@ -660,24 +660,24 @@ typedef struct /** @defgroup ETH_Buffers_setting ETH Buffers setting * @{ */ -#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */ -#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */ +#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ +#define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ /* Ethernet driver receive buffers are organized in a chained linked-list, when - an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO + an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO to the driver receive buffers memory. - Depending on the size of the received ethernet packet and the size of - each ethernet driver receive buffer, the received packet can take one or more - ethernet driver receive buffer. + Depending on the size of the received Ethernet packet and the size of + each Ethernet driver receive buffer, the received packet can take one or more + Ethernet driver receive buffer. - In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE + In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE and the total count of the driver receive buffers ETH_RXBUFNB. The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as @@ -692,19 +692,19 @@ typedef struct /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ #ifndef ETH_RXBUFNB - #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ + #define ETH_RXBUFNB ((uint32_t)5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ #endif /* Ethernet driver transmit buffers are organized in a chained linked-list, when - an ethernet packet is transmitted, Tx-DMA will transfer the packet from the + an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the driver transmit buffers memory to the TxFIFO. Depending on the size of the Ethernet packet to be transmitted and the size of - each ethernet driver transmit buffer, the packet to be transmitted can take - one or more ethernet driver transmit buffer. + each Ethernet driver transmit buffer, the packet to be transmitted can take + one or more Ethernet driver transmit buffer. - In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE + In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE and the total count of the driver transmit buffers ETH_TXBUFNB. The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as @@ -717,9 +717,9 @@ typedef struct #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE #endif -/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ +/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ #ifndef ETH_TXBUFNB - #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ + #define ETH_TXBUFNB ((uint32_t)5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ #endif /** @@ -746,51 +746,51 @@ typedef struct /** * @brief Bit definition of TDES0 register: DMA Tx descriptor status register */ -#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */ -#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */ -#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */ -#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */ -#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ -#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ -#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ -#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ -#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ -#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */ -#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ +#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */ +#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */ +#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */ +#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ +#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */ +#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */ +#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */ +#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */ +#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */ /** * @brief Bit definition of TDES1 register */ -#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ +#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */ /** * @brief Bit definition of TDES2 register */ -#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ +#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ /** * @brief Bit definition of TDES3 register */ -#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ +#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ /*--------------------------------------------------------------------------------------------- TDES6 | Transmit Time Stamp Low [31:0] | @@ -799,10 +799,10 @@ typedef struct ----------------------------------------------------------------------------------------------*/ /* Bit definition of TDES6 register */ - #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */ + #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ /* Bit definition of TDES7 register */ - #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */ + #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ /** * @} @@ -827,44 +827,44 @@ typedef struct /** * @brief Bit definition of RDES0 register: DMA Rx descriptor status register */ -#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ -#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ -#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ -#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */ -#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ +#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ /** * @brief Bit definition of RDES1 register */ -#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ -#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ -#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ +#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */ +#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */ /** * @brief Bit definition of RDES2 register */ -#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ +#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ /** * @brief Bit definition of RDES3 register */ -#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ +#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ /*--------------------------------------------------------------------------------------------------------------------- RDES4 | Reserved[31:15] | Extended Status [14:0] | @@ -877,39 +877,39 @@ typedef struct --------------------------------------------------------------------------------------------------------------------*/ /* Bit definition of RDES4 register */ -#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */ -#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */ -#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */ - #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ - #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */ -#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */ -#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */ -#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */ -#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */ -#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */ - #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */ - #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ +#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ +#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ +#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ +#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ +#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ +#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ +#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ +#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ +#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */ /* Bit definition of RDES6 register */ -#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */ +#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ /* Bit definition of RDES7 register */ -#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */ +#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ /** * @} */ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation * @{ */ -#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001) -#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000) +#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U) +#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U) /** * @} @@ -917,8 +917,8 @@ typedef struct /** @defgroup ETH_Speed ETH Speed * @{ */ -#define ETH_SPEED_10M ((uint32_t)0x00000000) -#define ETH_SPEED_100M ((uint32_t)0x00004000) +#define ETH_SPEED_10M ((uint32_t)0x00000000U) +#define ETH_SPEED_100M ((uint32_t)0x00004000U) /** * @} @@ -926,16 +926,16 @@ typedef struct /** @defgroup ETH_Duplex_Mode ETH Duplex Mode * @{ */ -#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800) -#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000) +#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U) +#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /** * @} */ /** @defgroup ETH_Rx_Mode ETH Rx Mode * @{ */ -#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000) -#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001) +#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U) +#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U) /** * @} */ @@ -943,8 +943,8 @@ typedef struct /** @defgroup ETH_Checksum_Mode ETH Checksum Mode * @{ */ -#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000) -#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001) +#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U) +#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U) /** * @} */ @@ -952,7 +952,7 @@ typedef struct /** @defgroup ETH_Media_Interface ETH Media Interface * @{ */ -#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000) +#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U) #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) /** * @} @@ -961,8 +961,8 @@ typedef struct /** @defgroup ETH_Watchdog ETH Watchdog * @{ */ -#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000) -#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000) +#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U) +#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U) /** * @} */ @@ -970,8 +970,8 @@ typedef struct /** @defgroup ETH_Jabber ETH Jabber * @{ */ -#define ETH_JABBER_ENABLE ((uint32_t)0x00000000) -#define ETH_JABBER_DISABLE ((uint32_t)0x00400000) +#define ETH_JABBER_ENABLE ((uint32_t)0x00000000U) +#define ETH_JABBER_DISABLE ((uint32_t)0x00400000U) /** * @} */ @@ -979,14 +979,14 @@ typedef struct /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap * @{ */ -#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ -#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ -#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ -#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ -#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ -#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ -#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ -#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ +#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */ /** * @} */ @@ -994,8 +994,8 @@ typedef struct /** @defgroup ETH_Carrier_Sense ETH Carrier Sense * @{ */ -#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000) -#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000) +#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U) +#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U) /** * @} */ @@ -1003,8 +1003,8 @@ typedef struct /** @defgroup ETH_Receive_Own ETH Receive Own * @{ */ -#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000) -#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000) +#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) +#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U) /** * @} */ @@ -1012,8 +1012,8 @@ typedef struct /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode * @{ */ -#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000) -#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000) +#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U) +#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1021,8 +1021,8 @@ typedef struct /** @defgroup ETH_Checksum_Offload ETH Checksum Offload * @{ */ -#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400) -#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000) +#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U) +#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1030,8 +1030,8 @@ typedef struct /** @defgroup ETH_Retry_Transmission ETH Retry Transmission * @{ */ -#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000) -#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200) +#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) +#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U) /** * @} */ @@ -1039,8 +1039,8 @@ typedef struct /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip * @{ */ -#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080) -#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000) +#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U) +#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1048,10 +1048,10 @@ typedef struct /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit * @{ */ -#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000) -#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020) -#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040) -#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060) +#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U) +#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U) +#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U) +#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U) /** * @} */ @@ -1059,8 +1059,8 @@ typedef struct /** @defgroup ETH_Deferral_Check ETH Deferral Check * @{ */ -#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010) -#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000) +#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U) +#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1068,8 +1068,8 @@ typedef struct /** @defgroup ETH_Receive_All ETH Receive All * @{ */ -#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000) -#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000) +#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U) +#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1077,9 +1077,9 @@ typedef struct /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter * @{ */ -#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200) -#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300) -#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000) +#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U) +#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U) +#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1087,9 +1087,9 @@ typedef struct /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames * @{ */ -#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ -#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */ /** * @} */ @@ -1097,8 +1097,8 @@ typedef struct /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception * @{ */ -#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000) -#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020) +#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U) +#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U) /** * @} */ @@ -1106,8 +1106,8 @@ typedef struct /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter * @{ */ -#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000) -#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008) +#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U) +#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U) /** * @} */ @@ -1115,8 +1115,8 @@ typedef struct /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode * @{ */ -#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001) -#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000) +#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U) +#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1124,10 +1124,10 @@ typedef struct /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter * @{ */ -#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404) -#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004) -#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) -#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010) +#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U) +#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U) +#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) +#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U) /** * @} */ @@ -1135,9 +1135,9 @@ typedef struct /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter * @{ */ -#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402) -#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002) -#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) +#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U) +#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U) +#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) /** * @} */ @@ -1145,8 +1145,8 @@ typedef struct /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause * @{ */ -#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000) -#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080) +#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U) +#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U) /** * @} */ @@ -1154,10 +1154,10 @@ typedef struct /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold * @{ */ -#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */ /** * @} */ @@ -1165,8 +1165,8 @@ typedef struct /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect * @{ */ -#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008) -#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000) +#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U) +#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1174,8 +1174,8 @@ typedef struct /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control * @{ */ -#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004) -#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000) +#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U) +#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1183,8 +1183,8 @@ typedef struct /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control * @{ */ -#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002) -#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000) +#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U) +#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1192,8 +1192,8 @@ typedef struct /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison * @{ */ -#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000) -#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000) +#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U) +#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /** * @} */ @@ -1201,10 +1201,10 @@ typedef struct /** @defgroup ETH_MAC_addresses ETH MAC addresses * @{ */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018) +#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) +#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) +#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) +#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) /** * @} */ @@ -1212,8 +1212,8 @@ typedef struct /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA * @{ */ -#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008) +#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U) +#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U) /** * @} */ @@ -1221,46 +1221,12 @@ typedef struct /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes * @{ */ -#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags - * @{ - */ -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ +#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */ /** * @} */ @@ -1268,8 +1234,8 @@ typedef struct /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame * @{ */ -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000) +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U) +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U) /** * @} */ @@ -1277,8 +1243,8 @@ typedef struct /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward * @{ */ -#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000) -#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000) +#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U) +#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1286,8 +1252,8 @@ typedef struct /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame * @{ */ -#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000) +#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U) +#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U) /** * @} */ @@ -1295,8 +1261,8 @@ typedef struct /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward * @{ */ -#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000) -#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000) +#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U) +#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1304,14 +1270,14 @@ typedef struct /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control * @{ */ -#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ /** * @} */ @@ -1319,8 +1285,8 @@ typedef struct /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames * @{ */ -#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080) -#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000) +#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U) +#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1328,8 +1294,8 @@ typedef struct /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames * @{ */ -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040) -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000) +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U) +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1337,10 +1303,10 @@ typedef struct /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control * @{ */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ /** * @} */ @@ -1348,8 +1314,8 @@ typedef struct /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate * @{ */ -#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004) -#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000) +#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U) +#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1357,8 +1323,8 @@ typedef struct /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats * @{ */ -#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000) -#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000) +#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U) +#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1366,8 +1332,8 @@ typedef struct /** @defgroup ETH_Fixed_Burst ETH Fixed Burst * @{ */ -#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000) -#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000) +#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U) +#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1375,18 +1341,18 @@ typedef struct /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length * @{ */ -#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ /** * @} */ @@ -1394,18 +1360,18 @@ typedef struct /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length * @{ */ -#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ /** * @} */ @@ -1413,8 +1379,8 @@ typedef struct /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format * @{ */ -#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080) -#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000) +#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U) +#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -1422,11 +1388,11 @@ typedef struct /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration * @{ */ -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000) -#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002) +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U) +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U) +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U) +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U) +#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U) /** * @} */ @@ -1434,8 +1400,8 @@ typedef struct /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment * @{ */ -#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */ -#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */ +#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */ +#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */ /** * @} */ @@ -1443,10 +1409,10 @@ typedef struct /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control * @{ */ -#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */ -#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */ +#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ /** * @} */ @@ -1454,8 +1420,8 @@ typedef struct /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers * @{ */ -#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ -#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */ /** * @} */ @@ -1463,9 +1429,9 @@ typedef struct /** @defgroup ETH_PMT_Flags ETH PMT Flags * @{ */ -#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */ /** * @} */ @@ -1473,9 +1439,9 @@ typedef struct /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts * @{ */ -#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */ /** * @} */ @@ -1483,9 +1449,9 @@ typedef struct /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts * @{ */ -#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */ /** * @} */ @@ -1493,11 +1459,11 @@ typedef struct /** @defgroup ETH_MAC_Flags ETH MAC Flags * @{ */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ -#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */ /** * @} */ @@ -1505,27 +1471,27 @@ typedef struct /** @defgroup ETH_DMA_Flags ETH DMA Flags * @{ */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */ -#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */ +#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */ /** * @} */ @@ -1533,11 +1499,11 @@ typedef struct /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts * @{ */ -#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ -#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */ /** * @} */ @@ -1545,24 +1511,24 @@ typedef struct /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts * @{ */ -#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ -#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ -#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ -#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ -#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ -#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ -#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ -#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ -#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ -#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */ /** * @} */ @@ -1570,12 +1536,12 @@ typedef struct /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state * @{ */ -#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ -#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */ -#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ -#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */ -#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ +#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */ +#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */ /** * @} @@ -1585,12 +1551,12 @@ typedef struct /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state * @{ */ -#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ -#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */ -#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */ -#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ -#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */ +#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */ +#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */ +#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */ /** * @} @@ -1599,8 +1565,8 @@ typedef struct /** @defgroup ETH_DMA_overflow ETH DMA overflow * @{ */ -#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ -#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ +#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */ /** * @} */ @@ -1608,7 +1574,7 @@ typedef struct /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP * @{ */ -#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ +#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ /** * @} @@ -1631,7 +1597,7 @@ typedef struct #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) /** - * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not. * @param __HANDLE__: ETH Handle * @param __FLAG__: specifies the flag of TDES0 to check. * @retval the ETH_DMATxDescFlag (SET or RESET). @@ -1639,7 +1605,7 @@ typedef struct #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) /** - * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. + * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not. * @param __HANDLE__: ETH Handle * @param __FLAG__: specifies the flag of RDES0 to check. * @retval the ETH_DMATxDescFlag (SET or RESET). @@ -1668,7 +1634,7 @@ typedef struct #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) /** - * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @brief Returns the specified Ethernet DMA Tx Desc collision count. * @param __HANDLE__: ETH Handle * @retval The Transmit descriptor collision counter value. */ @@ -1696,7 +1662,7 @@ typedef struct #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) /** - * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion. * @param __HANDLE__: ETH Handle * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. * This parameter can be one of the following values: @@ -1737,9 +1703,9 @@ typedef struct #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) /** - * @brief Enables the specified ETHERNET MAC interrupts. + * @brief Enables the specified Ethernet MAC interrupts. * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt @@ -1749,9 +1715,9 @@ typedef struct #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) /** - * @brief Disables the specified ETHERNET MAC interrupts. + * @brief Disables the specified Ethernet MAC interrupts. * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt @@ -1768,7 +1734,7 @@ typedef struct #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) /** - * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @brief Checks whether the Ethernet flow control busy bit is set or not. * @param __HANDLE__: ETH Handle * @retval The new state of flow control busy status bit (SET or RESET). */ @@ -1789,7 +1755,7 @@ typedef struct #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) /** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @brief Checks whether the specified Ethernet MAC flag is set or not. * @param __HANDLE__: ETH Handle * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: @@ -1798,30 +1764,30 @@ typedef struct * @arg ETH_MAC_FLAG_MMCR : MMC receive flag * @arg ETH_MAC_FLAG_MMC : MMC flag * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of ETHERNET MAC flag. + * @retval The state of Ethernet MAC flag. */ #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) /** - * @brief Enables the specified ETHERNET DMA interrupts. + * @brief Enables the specified Ethernet DMA interrupts. * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be * enabled @ref ETH_DMA_Interrupts * @retval None */ #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) /** - * @brief Disables the specified ETHERNET DMA interrupts. + * @brief Disables the specified Ethernet DMA interrupts. * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be * disabled. @ref ETH_DMA_Interrupts * @retval None */ #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) /** - * @brief Clears the ETHERNET DMA IT pending bit. + * @brief Clears the Ethernet DMA IT pending bit. * @param __HANDLE__ : ETH Handle * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts * @retval None @@ -1829,7 +1795,7 @@ typedef struct #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) /** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @brief Checks whether the specified Ethernet DMA flag is set or not. * @param __HANDLE__: ETH Handle * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). @@ -1837,7 +1803,7 @@ typedef struct #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) /** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @brief Checks whether the specified Ethernet DMA flag is set or not. * @param __HANDLE__: ETH Handle * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). @@ -1845,13 +1811,13 @@ typedef struct #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) /** - * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @brief Checks whether the specified Ethernet DMA overflow flag is set or not. * @param __HANDLE__: ETH Handle * @param __OVERFLOW__: specifies the DMA overflow flag to check. * This parameter can be one of the following values: * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). + * @retval The state of Ethernet DMA overflow Flag (SET or RESET). */ #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) @@ -1922,14 +1888,14 @@ typedef struct #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) /** - * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @brief Checks whether the specified Ethernet PMT flag is set or not. * @param __HANDLE__: ETH Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of ETHERNET PMT Flag (SET or RESET). + * @retval The new state of Ethernet PMT Flag (SET or RESET). */ #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) @@ -1998,9 +1964,9 @@ typedef struct #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) /** - * @brief Enables the specified ETHERNET MMC Rx interrupts. + * @brief Enables the specified Ethernet MMC Rx interrupts. * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value @@ -2009,9 +1975,9 @@ typedef struct */ #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) /** - * @brief Disables the specified ETHERNET MMC Rx interrupts. + * @brief Disables the specified Ethernet MMC Rx interrupts. * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value @@ -2020,9 +1986,9 @@ typedef struct */ #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) /** - * @brief Enables the specified ETHERNET MMC Tx interrupts. + * @brief Enables the specified Ethernet MMC Tx interrupts. * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value @@ -2032,9 +1998,9 @@ typedef struct #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) /** - * @brief Disables the specified ETHERNET MMC Tx interrupts. + * @brief Disables the specified Ethernet MMC Tx interrupts. * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c index 8ac63516bc3..59fe163b704 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -72,7 +72,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -118,8 +118,8 @@ /** @addtogroup FLASH_Private_Constants * @{ */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07U) +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ /** * @} */ @@ -352,7 +352,7 @@ void HAL_FLASH_IRQHandler(void) { /* No more sectors to Erase, user callback can be called.*/ /* Reset Sector and stop Erase sectors procedure */ - pFlash.Sector = temp = 0xFFFFFFFF; + pFlash.Sector = temp = 0xFFFFFFFFU; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(temp); /* Sector Erase procedure is completed */ @@ -400,7 +400,7 @@ void HAL_FLASH_IRQHandler(void) { /* return the faulty sector */ temp = pFlash.Sector; - pFlash.Sector = 0xFFFFFFFF; + pFlash.Sector = 0xFFFFFFFFU; break; } case FLASH_PROC_MASSERASE : diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h index 2dce315d686..cad67d65945 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ */ typedef enum { - FLASH_PROC_NONE = 0, + FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM @@ -83,7 +83,7 @@ typedef struct __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ - + __IO uint32_t Address; /* Internal variable to save address selected for program */ HAL_LockTypeDef Lock; /* FLASH locking object */ @@ -105,12 +105,12 @@ typedef struct * @brief FLASH Error Code * @{ */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002) /*!< Programming Sequence error */ -#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004) /*!< Programming Parallelism error */ -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) /*!< Programming Alignment error */ -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010) /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020) /*!< Operation Error */ +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ /** * @} */ @@ -118,10 +118,10 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */ /** * @} */ @@ -146,7 +146,7 @@ typedef struct * @{ */ #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */ /** * @} */ @@ -154,11 +154,11 @@ typedef struct /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism * @{ */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) #define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) #define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) #define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) /** * @} */ @@ -166,14 +166,29 @@ typedef struct /** @defgroup FLASH_Keys FLASH Keys * @{ */ -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) +#define FLASH_KEY1 ((uint32_t)0x45670123U) +#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) /** * @} */ +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +/** + * @} + */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c index 2cf7f3b4dc4..ab5bd9b78fb 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -14,13 +14,13 @@ ##### Flash Extension features ##### ============================================================================== - [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and + [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx devices contains the following additional features (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write capability (RWW) (+) Dual bank memory organization - (+) PCROP protection for all banks + (+) Dual boot mode ##### How to use this driver ##### ============================================================================== @@ -39,18 +39,12 @@ (++) Set the Read protection Level (++) Set the BOR level (++) Program the user Option Bytes - (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : - (++) Extended space (bank 2) erase function - (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2) - (++) Dual Boot activation - (++) Write protection configuration for bank 2 - (++) PCROP protection configuration and control for both banks @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -117,11 +111,9 @@ extern FLASH_ProcessTypeDef pFlash; * @{ */ /* Option bytes control */ -static void FLASH_MassErase(uint8_t VoltageRange); static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); static uint32_t FLASH_OB_GetUser(void); @@ -130,6 +122,15 @@ static uint8_t FLASH_OB_GetRDP(void); static uint32_t FLASH_OB_GetBOR(void); static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); +#if defined (FLASH_OPTCR_nDBANK) +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot); +#else +static void FLASH_MassErase(uint8_t VoltageRange); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); +#endif /* FLASH_OPTCR_nDBANK */ + extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} @@ -182,13 +183,17 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t if(status == HAL_OK) { /*Initialization of SectorError variable*/ - *SectorError = 0xFFFFFFFF; + *SectorError = 0xFFFFFFFFU; if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); - +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); @@ -208,9 +213,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - /* If the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; + /* If the erase operation is completed, disable the SER Bit and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); if(status != HAL_OK) { @@ -259,7 +263,11 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ } else { @@ -322,12 +330,23 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /* USER configuration */ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) { +#if defined (FLASH_OPTCR_nDBANK) + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, + pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, + pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); +#else status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, pOBInit->USERConfig & OB_IWDG_SW, pOBInit->USERConfig & OB_STOP_NO_RST, pOBInit->USERConfig & OB_STDBY_NO_RST, pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, - pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); +#endif /* FLASH_OPTCR_nDBANK */ } /* BOR Level configuration */ @@ -355,7 +374,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } /** - * @brief Get the Option byte configuration + * @brief Get the Option byte configuration * @param pOBInit: pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * @@ -384,11 +403,215 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /*Get Boot Address when Boot pin = 1 */ pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); } - /** * @} */ +#if defined (FLASH_OPTCR_nDBANK) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * @param Banks: Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + else + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector: FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if(Sector > FLASH_SECTOR_11) + { + Sector += 4; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg: Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @param NDBank: Flash Single Bank mode enabled. + * This parameter can be one of the following values: + * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) + * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) + * @param NDBoot: Flash Dual boot mode disable. + * This parameter can be one of the following values: + * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot + * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot + + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + assert_param(IS_OB_NDBANK(NDBank)); + assert_param(IS_OB_NDBOOT(NDBoot)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ + FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); +} +#else + /** * @brief Full erase of FLASH memory sectors * @param VoltageRange: The device voltage range which defines the erase parallelism. @@ -412,7 +635,7 @@ static void FLASH_MassErase(uint8_t VoltageRange) /* if the previous operation is completed, proceed to erase all sectors */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT | (VoltageRange <<8); + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); @@ -473,7 +696,90 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) } /** - * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg: Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xC00000F0)); +} +#endif /* FLASH_OPTCR_nDBANK */ + +/** + * @brief Enable the write protection of the desired bank1 or bank2 sectors * * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash sector i if CortexM7 @@ -481,7 +787,9 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * * @param WRPSector: specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) * @arg OB_WRP_SECTOR_All * * @retval HAL FLASH State @@ -514,7 +822,9 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) * * @param WRPSector: specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) * @arg OB_WRP_Sector_All * * @@ -569,67 +879,6 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) return status; } -/** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_WWDG_SW: Software WWDG selected - * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NO_RST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP - * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY - * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) -{ - uint32_t useroptionmask = 0x00; - uint32_t useroptionvalue = 0x00; - - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WWDG_SOURCE(Wwdg)); - assert_param(IS_OB_IWDG_SOURCE(Iwdg)); - assert_param(IS_OB_STOP_SOURCE(Stop)); - assert_param(IS_OB_STDBY_SOURCE(Stdby)); - assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); - assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ - FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); - - useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); - - /* Update User Option Byte */ - MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); - } - - return status; - -} - /** * @brief Set the BOR Level. * @param Level: specifies the Option Bytes BOR Reset Level. @@ -696,27 +945,6 @@ static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_ return status; } -/** - * @brief Return the FLASH User Option Byte value. - * @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return ((uint32_t)(FLASH->OPTCR & 0xC00000F0)); -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval uint32_t FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); -} - /** * @brief Returns the FLASH Read Protection level. * @retval FlagStatus FLASH ReadOut Protection Status: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h index 3a2512150b8..94a452b659b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,6 +67,11 @@ typedef struct uint32_t TypeErase; /*!< Mass erase or sector Erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ +#if defined (FLASH_OPTCR_nDBANK) + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ +#endif /* FLASH_OPTCR_nDBANK */ + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of @ref FLASHEx_Sectors */ @@ -99,7 +104,8 @@ typedef struct This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / - IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */ + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. + nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. This parameter can be a value of @ref FLASHEx_Boot_Address */ @@ -121,8 +127,8 @@ typedef struct /** @defgroup FLASHEx_Type_Erase FLASH Type Erase * @{ */ -#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */ -#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */ +#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ /** * @} */ @@ -130,10 +136,10 @@ typedef struct /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range * @{ */ -#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */ -#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */ -#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ /** * @} */ @@ -141,8 +147,8 @@ typedef struct /** @defgroup FLASHEx_WRP_State FLASH WRP State * @{ */ -#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */ -#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ /** * @} */ @@ -150,12 +156,12 @@ typedef struct /** @defgroup FLASHEx_Option_Type FLASH Option Type * @{ */ -#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ -#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ -#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ -#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */ -#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10) /*!< Boot 0 Address configuration */ -#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20) /*!< Boot 1 Address configuration */ +#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ +#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ +#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ /** * @} */ @@ -163,9 +169,9 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection * @{ */ -#define OB_RDP_LEVEL_0 ((uint8_t)0xAA) -#define OB_RDP_LEVEL_1 ((uint8_t)0x55) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 +#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55U) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0 */ /** * @} @@ -174,8 +180,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog * @{ */ -#define OB_WWDG_SW ((uint32_t)0x10) /*!< Software WWDG selected */ -#define OB_WWDG_HW ((uint32_t)0x00) /*!< Hardware WWDG selected */ +#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ +#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ /** * @} */ @@ -184,8 +190,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog * @{ */ -#define OB_IWDG_SW ((uint32_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint32_t)0x00) /*!< Hardware IWDG selected */ +#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ /** * @} */ @@ -193,8 +199,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP * @{ */ -#define OB_STOP_NO_RST ((uint32_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint32_t)0x00) /*!< Reset generated when entering in STOP */ +#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ /** * @} */ @@ -202,8 +208,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY * @{ */ -#define OB_STDBY_NO_RST ((uint32_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint32_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ /** * @} */ @@ -211,8 +217,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP * @{ */ -#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */ -#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000) /*!< IWDG counter active in STOP mode */ +#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ /** * @} */ @@ -220,8 +226,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY * @{ */ -#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */ -#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */ +#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ /** * @} */ @@ -229,25 +235,47 @@ typedef struct /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level * @{ */ -#define OB_BOR_LEVEL3 ((uint32_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint32_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint32_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint32_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBOOT) +/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT + * @{ + */ +#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ +#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash + (Dual bank Boot mode), or RAM if Boot address option in RAM */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBOOT */ +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank + * @{ + */ +#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ +#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ /** * @} */ - +#endif /* FLASH_OPTCR_nDBANK */ + /** @defgroup FLASHEx_Boot_Address FLASH Boot Address * @{ */ -#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000) /*!< Boot from ITCM RAM (0x00000000) */ -#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040) /*!< Boot from System memory bootloader (0x00100000) */ -#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080) /*!< Boot from Flash on ITCM interface (0x00200000) */ -#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000) /*!< Boot from Flash on AXIM interface (0x08000000) */ -#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000) /*!< Boot from DTCM RAM (0x20000000) */ -#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004) /*!< Boot from SRAM1 (0x20010000) */ -#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013) /*!< Boot from SRAM2 (0x2004C000) */ +#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ /** * @} */ @@ -273,12 +301,28 @@ typedef struct #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ /** * @} - */ + */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ +#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ +#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit * @{ */ -#define FLASH_MER_BIT (FLASH_CR_MER) /*!< MER bit to clear */ +#if defined (FLASH_OPTCR_nDBANK) +#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ +#else +#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ +#endif /* FLASH_OPTCR_nDBANK */ /** * @} */ @@ -286,41 +330,121 @@ typedef struct /** @defgroup FLASHEx_Sectors FLASH Sectors * @{ */ -#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */ -#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */ -#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */ -#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */ -#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */ -#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */ -#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */ -#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */ - +#if (FLASH_SECTOR_TOTAL == 24) +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ /** * @} */ +#if (FLASH_SECTOR_TOTAL == 24) /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. + * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and + * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). + * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. * @{ */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000) /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000) /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000) /*!< Write protection of Sector2 */ -#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000) /*!< Write protection of Sector3 */ -#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000) /*!< Write protection of Sector4 */ -#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000) /*!< Write protection of Sector5 */ -#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000) /*!< Write protection of Sector6 */ -#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000) /*!< Write protection of Sector7 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */ - +/* Single Bank Sectors */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ +#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ +#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ +#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ +#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ + +/* Dual Bank Sectors */ +#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ +#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ +#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ +#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ +#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ +#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ +#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ +#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ +#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ +#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ +#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ +#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ +#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ +#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ +#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ +#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ +#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ +#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ +#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ +#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ +#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ +#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ +#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ +#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ +#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ /** * @} */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 8) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Adress + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) + /** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ @@ -345,14 +469,6 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Constants FLASH Private Constants - * @{ - */ -#define FLASH_SECTOR_TOTAL 8 -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Macros FLASH Private Macros * @{ @@ -376,13 +492,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) -#define IS_OB_BOOT_ADDRESS(ADDRESS) (((ADDRESS) == OB_BOOTADDR_ITCM_RAM) || \ - ((ADDRESS) == OB_BOOTADDR_SYSTEM) || \ - ((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \ - ((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \ - ((ADDRESS) == OB_BOOTADDR_DTCM_RAM) || \ - ((ADDRESS) == OB_BOOTADDR_SRAM1) || \ - ((ADDRESS) == OB_BOOTADDR_SRAM2)) +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ ((LEVEL) == OB_RDP_LEVEL_1) ||\ @@ -422,14 +532,47 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) -#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) +#if (FLASH_SECTOR_TOTAL == 8) #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000)) +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 24) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ + ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ + ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ + ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ + ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ + ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ + ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ + ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ + ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if defined (FLASH_OPTCR_nDBANK) +#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ + ((VALUE) == OB_NDBANK_DUAL_BANK)) + +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR_nDBOOT) +#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ + ((VALUE) == OB_DUAL_BOOT_ENABLE)) +#endif /* FLASH_OPTCR_nDBOOT */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c index b400e1559c4..5c77f4dde25 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -95,7 +95,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -141,15 +141,15 @@ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE ((uint32_t)0x00000003) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) - -#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_MODE ((uint32_t)0x00000003U) +#define EXTI_MODE ((uint32_t)0x10000000U) +#define GPIO_MODE_IT ((uint32_t)0x00010000U) +#define GPIO_MODE_EVT ((uint32_t)0x00020000U) +#define RISING_EDGE ((uint32_t)0x00100000U) +#define FALLING_EDGE ((uint32_t)0x00200000U) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) + +#define GPIO_NUMBER ((uint32_t)16U) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h index f7db1cbb696..f019772387f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,25 +101,25 @@ typedef enum /** @defgroup GPIO_pins_define GPIO pins define * @{ */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ /** * @} */ @@ -134,21 +134,21 @@ typedef enum * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -157,10 +157,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< Low speed */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< Fast speed */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< High speed */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */ /** * @} */ @@ -169,9 +169,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ +#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h index 0486d4290b7..52c9fda3e60 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -68,128 +68,169 @@ /** * @brief AF 0 selection */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */ +#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 2 selection */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ /** * @brief AF 3 selection */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ - +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 4 selection */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 5 selection */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */ /** * @brief AF 6 selection */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 7 selection */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ -#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */ -#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @brief AF 8 selection */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */ -#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 9 selection */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ -#if defined(STM32F746xx) || defined(STM32F756xx) -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 10 selection */ -#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ -#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 11 selection */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - +#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @brief AF 12 selection */ -#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */ - +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @brief AF 13 selection */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -#if defined(STM32F746xx) || defined(STM32F756xx) +#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ + /** * @brief AF 14 selection */ -#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx */ +#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief AF 15 selection */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ /** @@ -340,6 +381,101 @@ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) +#elif defined(STM32F767xx) || defined(STM32F777xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F769xx) || defined(STM32F779xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI)) +#elif defined(STM32F765xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF10_OTG_FS)) #endif /* STM32F756xx || STM32F746xx */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c index 961f6ad3ece..5fad5d4fd43 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: @@ -68,7 +68,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -102,7 +102,7 @@ * @{ */ -#if defined(STM32F756xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup HASH HASH * @brief HASH HAL module driver. @@ -1869,7 +1869,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) /** * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h index 2541b3ded77..24c9d4cc356 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F756xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -85,11 +85,11 @@ typedef struct typedef enum { - HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */ - HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */ - HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */ - HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */ - HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */ + HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */ + HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */ + HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */ + HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */ + HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */ }HAL_HASH_StateTypeDef; /** @@ -102,8 +102,8 @@ typedef enum typedef enum { - HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */ - HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */ + HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */ + HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in processing phase */ }HAL_HASHPhaseTypeDef; /** @@ -156,7 +156,7 @@ typedef struct /** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection * @{ */ -#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ +#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000U) /*!< HASH function is SHA1 */ #define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ #define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ #define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ @@ -167,7 +167,7 @@ typedef struct /** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode * @{ */ -#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ +#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000U) /*!< Algorithm is HASH */ #define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ /** * @} @@ -176,7 +176,7 @@ typedef struct /** @defgroup HASH_Data_Type HASH Data Type * @{ */ -#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ +#define HASH_DATATYPE_32B ((uint32_t)0x0000U) /*!< 32-bit data. No swapping */ #define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ #define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ #define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ @@ -188,7 +188,7 @@ typedef struct * @brief HASH HMAC Long key used only for HMAC mode * @{ */ -#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ +#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000U) /*!< HMAC Key is <= 64 bytes */ #define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */ /** * @} @@ -435,7 +435,7 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); /** * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c index c8ad5b3258e..e116825bef5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief HASH HAL Extension module driver. * This file provides firmware functions to manage the following * functionalities of HASH peripheral: @@ -65,7 +65,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -98,7 +98,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) /** @defgroup HASHEx HASHEx * @brief HASH Extension HAL module driver. @@ -1627,7 +1627,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h index 63c0887bcc8..27178fad2e6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F756xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -185,7 +185,7 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash); /** * @} */ -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c index d402cfa0961..a49717bb894 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -44,7 +44,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -1188,10 +1188,6 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) } HAL_HCD_Connect_Callback(hhcd); - if(hhcd->Init.speed == HCD_SPEED_HIGH) - { - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - } } else { diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h index db7cd6eddda..45b752b9bd7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,11 +65,11 @@ */ typedef enum { - HAL_HCD_STATE_RESET = 0x00, - HAL_HCD_STATE_READY = 0x01, - HAL_HCD_STATE_ERROR = 0x02, - HAL_HCD_STATE_BUSY = 0x03, - HAL_HCD_STATE_TIMEOUT = 0x04 + HAL_HCD_STATE_RESET = 0x00U, + HAL_HCD_STATE_READY = 0x01U, + HAL_HCD_STATE_ERROR = 0x02U, + HAL_HCD_STATE_BUSY = 0x03U, + HAL_HCD_STATE_TIMEOUT = 0x04U } HCD_StateTypeDef; typedef USB_OTG_GlobalTypeDef HCD_TypeDef; @@ -109,9 +109,9 @@ typedef struct /** @defgroup HCD_Speed HCD Speed * @{ */ -#define HCD_SPEED_HIGH 0 -#define HCD_SPEED_LOW 2 -#define HCD_SPEED_FULL 3 +#define HCD_SPEED_HIGH 0U +#define HCD_SPEED_LOW 2U +#define HCD_SPEED_FULL 3U /** * @} */ @@ -119,8 +119,8 @@ typedef struct /** @defgroup HCD_PHY_Module HCD PHY Module * @{ */ -#define HCD_PHY_ULPI 1 -#define HCD_PHY_EMBEDDED 2 +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U /** * @} */ @@ -139,7 +139,7 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) #define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c index 4f39b45d5a6..f761655d008 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,9 +19,9 @@ The I2C HAL driver can be used as follows: (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; + I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -33,15 +33,16 @@ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Stream + (+++) Configure the DMA Tx or Rx stream (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() @@ -65,70 +66,130 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode IO sequential operation *** + =================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit + (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] - (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] - (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] - (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -138,8 +199,9 @@ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG : Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt @@ -150,7 +212,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -174,7 +236,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -184,7 +246,7 @@ * @{ */ -/** @defgroup I2C I2C HAL module driver +/** @defgroup I2C I2C * @brief I2C HAL module driver * @{ */ @@ -192,56 +254,106 @@ #ifdef HAL_I2C_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup I2C_Private_Constants I2C Private Constants +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define * @{ */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*State) == HAL_I2C_STATE_BUSY_TX) ? \ + ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \ + ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR))) + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup I2C_Private_Functions I2C Private Functions + +/** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ +/* Private functions to handle DMA transfer */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout); +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c); +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c); +/* Private functions to centralize the enable/disable of Interrupts */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private functions to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private functions to handle start, restart or stop a transfer */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ @@ -252,17 +364,17 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the I2Cx peripheral: + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: - (+) User must Implement HAL_I2C_MspInit() function in which he configures + (+) User must Implement HAL_I2C_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - (+) Call the function HAL_I2C_Init() to configure the selected device with + (+) Call the function HAL_I2C_Init() to configure the selected device with the selected configuration: (++) Clock Timing (++) Own Address 1 @@ -273,18 +385,18 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui (++) General call mode (++) Nostretch mode - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. @endverbatim * @{ */ /** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and create the associated handle. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) @@ -309,6 +421,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); } @@ -359,14 +472,16 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; return HAL_OK; } /** - * @brief DeInitializes the I2C peripheral. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief DeInitialize the I2C peripheral. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) @@ -389,8 +504,9 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) HAL_I2C_MspDeInit(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Release Lock */ __HAL_UNLOCK(hi2c); @@ -399,35 +515,35 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) } /** - * @brief I2C MSP Init. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Initialize the I2C MSP. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspInit could be implemented in the user file - */ + */ } /** - * @brief I2C MSP DeInit - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief DeInitialize the I2C MSP. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspDeInit could be implemented in the user file - */ + */ } /** @@ -437,22 +553,22 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the I2C data + This subsection provides a set of functions allowing to manage the I2C data transfers. (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. + (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. (#) Blocking mode functions are : @@ -463,7 +579,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Mem_Write() (++) HAL_I2C_Mem_Read() (++) HAL_I2C_IsDeviceReady() - + (#) No-Blocking mode functions with Interrupt are : (++) HAL_I2C_Master_Transmit_IT() (++) HAL_I2C_Master_Receive_IT() @@ -495,8 +611,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -505,44 +621,47 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t tickstart = 0; if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } + { + /* Process Locked */ + __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_BUSY; + return HAL_TIMEOUT; } - /* Process Locked */ - __HAL_LOCK(hi2c); + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - do + while(hi2c->XferSize > 0) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -554,35 +673,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*pData++); - sizetmp--; - Size--; + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; - if((sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); + } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -596,11 +714,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->State = HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -609,14 +728,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -625,44 +744,47 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t sizetmp = 0; + uint32_t tickstart = 0; if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_BUSY; + return HAL_TIMEOUT; } - /* Process Locked */ - __HAL_LOCK(hi2c); + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - do + while(hi2c->XferSize > 0) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -672,38 +794,37 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd { return HAL_TIMEOUT; } - } + } - /* Write data to RXDR */ - (*pData++) =hi2c->Instance->RXDR; - sizetmp--; - Size--; + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; - if((sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); + } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -717,11 +838,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->State = HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -730,14 +852,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } else { - return HAL_BUSY; + return HAL_BUSY; } } /** * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -745,24 +867,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0; + if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) + { + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -776,7 +908,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -788,17 +920,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - do + while(hi2c->XferCount > 0) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -813,13 +945,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } } - /* Read data from TXDR */ - hi2c->Instance->TXDR = (*pData++); - Size--; - }while(Size > 0); + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -840,7 +972,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -851,6 +983,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -859,14 +992,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration @@ -874,24 +1007,34 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -902,28 +1045,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(Size > 0) + while(hi2c->XferCount > 0) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - + /* Store Last receive data if any */ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; } - + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; @@ -935,12 +1079,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferCount--; } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -958,19 +1102,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Clear STOP flag */ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -979,28 +1123,25 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ +{ + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -1009,56 +1150,55 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } else { return HAL_BUSY; - } + } } /** - * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -1066,13 +1206,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -1081,55 +1218,55 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** - * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1138,48 +1275,47 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1188,48 +1324,47 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -1237,13 +1372,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -1252,18 +1384,25 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Set the I2C DMA transfer complete callback */ @@ -1272,45 +1411,32 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Abort DMA */ - HAL_DMA_Abort(hi2c->hdmatx); - - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + return HAL_OK; } else @@ -1320,9 +1446,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t } /** - * @brief Receive in master mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -1330,13 +1456,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + uint32_t xfermode = 0; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; @@ -1345,62 +1468,69 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if(hi2c->XferSize > 0) { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK) - { - /* Abort DMA */ - HAL_DMA_Abort(hi2c->hdmarx); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } return HAL_OK; } else @@ -1410,9 +1540,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D } /** - * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1421,19 +1551,23 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ - __HAL_LOCK(hi2c); + __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; @@ -1441,52 +1575,28 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + /* Enable the DMA channel */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - - /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_OK; } else @@ -1496,9 +1606,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent * @retval HAL status @@ -1507,19 +1617,23 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; @@ -1527,36 +1641,27 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size); + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Wait until DIR flag is set Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; return HAL_OK; } @@ -1567,8 +1672,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1579,31 +1684,40 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + if((pData == NULL) || (Size == 0)) { - return HAL_BUSY; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1619,23 +1733,22 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - /* Set NBYTES to write and reload if size > 255 */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1646,38 +1759,37 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress return HAL_TIMEOUT; } } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; - /* Write data to DR */ - hi2c->Instance->TXDR = (*pData++); - Sizetmp--; - Size--; - - if((Sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount!=0)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(Size > 0); + }while(hi2c->XferCount > 0); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1691,11 +1803,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->State = HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1710,8 +1823,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /** * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1722,31 +1835,40 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t Sizetmp = 0; + uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + if((pData == NULL) || (Size == 0)) { - return HAL_BUSY; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1763,59 +1885,55 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if(Size > 255) + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } do - { + { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Read data from RXDR */ - (*pData++) = hi2c->Instance->RXDR; - - /* Decrement the Size counter */ - Sizetmp--; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; - if((Sizetmp == 0)&&(Size!=0)) + if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(Size > 255) + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - Sizetmp = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - Sizetmp = Size; + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - - }while(Size > 0); + }while(hi2c->XferCount > 0); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1829,11 +1947,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1846,9 +1965,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } } /** - * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1858,14 +1977,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -1876,22 +1998,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1907,28 +2039,20 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } } - /* Set NBYTES to write and reload if size > 255 */ - /* Size > 255, need to set RELOAD bit */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -1939,9 +2063,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /** - * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -1951,14 +2075,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -1969,21 +2096,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1999,40 +2137,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } } - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - /* Size > 255, need to set RELOAD bit */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -2042,14 +2172,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -2060,31 +2193,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2100,36 +2234,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } } - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + return HAL_OK; } else @@ -2139,9 +2275,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /** - * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address @@ -2151,14 +2287,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0; + uint32_t xfermode = 0; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) @@ -2169,30 +2308,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - if(Size > 255) + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = 255; + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } else { - hi2c->XferSize = Size; + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -2208,28 +2349,37 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } } - /* Set NBYTES to write and reload if size > 255 and generate RESTART */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - return HAL_TIMEOUT; - } + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + return HAL_OK; } else @@ -2239,10 +2389,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /** - * @brief Checks if target device is ready for communication. + * @brief Checks if target device is ready for communication. * @note This function is used with Memory devices - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param Trials: Number of trials * @param Timeout: Timeout duration @@ -2284,7 +2434,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } } @@ -2294,7 +2444,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2313,7 +2463,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2332,14 +2482,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->Instance->CR2 |= I2C_CR2_STOP; /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } + } }while(I2C_Trials < Trials); hi2c->State = HAL_I2C_STATE_READY; @@ -2354,71 +2504,422 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_BUSY; } } -/** - * @} - */ - -/** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ /** - * @brief This function handles I2C event interrupt request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - /* I2C in mode Transmitter ---------------------------------------------------*/ - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET)) - { - /* Slave mode selected */ - if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) - { - I2C_SlaveTransmit_ISR(hi2c); - } - } + uint32_t xfermode = 0; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET)) - { - /* Master mode selected */ - if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)) - { - I2C_MasterTransmit_ISR(hi2c); - } - } + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - /* I2C in mode Receiver ----------------------------------------------------*/ - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET)) + if(hi2c->State == HAL_I2C_STATE_READY) { - /* Slave mode selected */ - if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX) + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If size > MAX_NBYTE_SIZE, use reload mode */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_SlaveReceive_ISR(hi2c); + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; } - } - if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET)) - { - /* Master mode selected */ - if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)) + else { - I2C_MasterReceive_ISR(hi2c); + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } } - } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } } /** - * @brief This function handles I2C error interrupt request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + uint32_t xfermode = 0; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress: Target device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if(hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + /* I2C Bus error interrupt occurred ------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) - { + if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; /* Clear BERR flag */ @@ -2426,8 +2927,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) - { + if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; /* Clear OVR flag */ @@ -2435,8 +2936,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET)) - { + if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; /* Clear ARLO flag */ @@ -2444,34 +2945,32 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_ErrorCallback(hi2c); + I2C_ITError(hi2c, hi2c->ErrorCode); } } /** - * @brief Master Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Master Tx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ } /** - * @brief Master Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Master Rx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2479,30 +2978,30 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } -/** @brief Slave Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. +/** @brief Slave Tx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ } /** - * @brief Slave Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Slave Rx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2510,31 +3009,67 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file */ } /** - * @brief Memory Tx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Slave Address Match callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS + * @param AddrMatchCode: Address Match Code * @retval None */ - __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file - */ + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ } /** - * @brief Memory Rx Transfer completed callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Memory Rx Transfer completed callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) @@ -2542,40 +3077,56 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file */ } /** - * @brief I2C error callbacks. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief I2C error callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file - */ + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ } /** * @} */ -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions * -@verbatim +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permit to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -2583,19 +3134,31 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) */ /** - * @brief Returns the I2C state. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Return the I2C handle state. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) { + /* Return I2C handle state */ return hi2c->State; } /** - * @brief Return the I2C error code - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** +* @brief Return the I2C error code. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code */ @@ -2617,439 +3180,387 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) */ /** - * @brief Handle Interrupt Flags Master Transmit Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t DevAddress; - + uint16_t devaddress = 0; + /* Process Locked */ - __HAL_LOCK(hi2c); + __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) - { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) - { - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > 255) - { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = 255; + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; + } + else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; + } + else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + { + if((hi2c->XferSize == 0) && (hi2c->XferCount != 0)) + { + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + + if(hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); hi2c->XferSize = hi2c->XferCount; + if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } } } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); + /* Call TxCpltCallback() if no stop mode is set */ + if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) + else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { if(hi2c->XferCount == 0) { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; + if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER)) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSequentialCplt(hi2c); + } } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + + if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + /* Process locked */ + __HAL_LOCK(hi2c); + + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if(hi2c->XferCount == 0) + { + if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - - /* Disable ERR, TC, STOP, NACK, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI ); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + } + else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + { + if(hi2c->XferCount > 0) { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + hi2c->XferSize--; + hi2c->XferCount--; } - /* Call the correct callback to inform upper layer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if((hi2c->XferCount == 0) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_ErrorCallback(hi2c); + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); + } + } + else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if(hi2c->XferCount > 0) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; } else { - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemTxCpltCallback(hi2c); - } - else + if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterTxCpltCallback(hi2c); + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSequentialCplt(hi2c); } } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + + /* Check if STOPF is set */ + if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); - - return HAL_OK; -} + + return HAL_OK; +} /** - * @brief Handle Interrupt Flags Master Receive Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t DevAddress; + uint16_t devaddress = 0; + uint32_t xfermode = 0; /* Process Locked */ __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) + else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0)) - { - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if(hi2c->XferCount != 0) + { + /* Recover Slave address */ + devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - if(hi2c->XferCount > 255) + /* Prepare the new XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - hi2c->XferSize = 255; - } + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + { hi2c->XferSize = hi2c->XferCount; - } - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) - { - if(hi2c->XferCount == 0) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Wrong size Status regarding TCR flag event */ - hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; - HAL_I2C_ErrorCallback(hi2c); - } - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + xfermode = I2C_AUTOEND_MODE; + } - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Disable ERR, TC, STOP, NACK, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI ); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Call the correct callback to inform upper layer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - hi2c->State = HAL_I2C_STATE_READY; + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) + /* Enable DMA Request */ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemRxCpltCallback(hi2c); + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterRxCpltCallback(hi2c); + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); } /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - -} + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} /** - * @brief Handle Interrupt Flags Slave Transmit Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags: Interrupt flags to handle. + * @param ITSources: Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) + if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ - /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0) + if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); } else { - /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Error callback to prevent upper layer */ - HAL_I2C_ErrorCallback(hi2c); } } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } - /* Check first if STOPF is set */ - /* to prevent a Write Data in TX buffer */ - /* which is stuck in TXDR until next */ - /* communication with Master */ - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI ); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) + else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - if(hi2c->XferCount > 0) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} -/** - * @brief Handle Interrupt Flags Slave Receive Mode - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c) -{ - /* Process Locked */ - __HAL_LOCK(hi2c); - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - HAL_I2C_ErrorCallback(hi2c); - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */ - __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI ); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_OK; -} + return HAL_OK; +} /** * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address * @param Timeout: Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3065,16 +3576,16 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3087,34 +3598,35 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - return HAL_OK; +return HAL_OK; } /** * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param DevAddress: Target device address * @param MemAddress: Internal memory address * @param MemAddSize: Size of internal memory address * @param Timeout: Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3130,16 +3642,16 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3152,11 +3664,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3165,811 +3677,712 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /** - * @brief DMA I2C master transmit process complete callback. - * @param hdma: DMA handle + * @brief I2C Address complete process callback. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. * @retval None */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { - uint16_t DevAddress; - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + uint8_t transferdirection = 0; + uint16_t slaveaddrcode = 0; + uint16_t ownadd1code = 0; + uint16_t ownadd2code = 0; - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + /* In case of Listen state, need to inform upper layer of address match code event */ + if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + /* If 10bits addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if(hi2c->AddrEventCount == 2) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); } } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } else { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + slaveaddrcode = ownadd2code; - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - hi2c->XferCount = 0; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); } } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + } } + /* Else clear address flag only */ else { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MasterTxCpltCallback(hi2c); - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); } } /** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma: DMA handle + * @brief I2C Master sequential complete process. + * @param hi2c: I2C handle. * @retval None */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal Use case, a AF is generated by master */ - /* to inform slave the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterRxCpltCallback(hi2c); } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c: I2C handle. + * @retval None + */ +static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { - HAL_I2C_ErrorCallback(hi2c); + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); } - else + + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { - HAL_I2C_SlaveTxCpltCallback(hi2c); + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); } } /** - * @brief DMA I2C master receive process complete callback - * @param hdma: DMA handle + * @brief I2C Master complete process. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. * @retval None */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - uint16_t DevAddress; + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + if((ITFlags & I2C_FLAG_AF) != RESET) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if (hi2c->Mode == HAL_I2C_MODE_MEM) { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferCount = 0; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MemTxCpltCallback(hi2c); } else { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } + hi2c->Mode = HAL_I2C_MODE_NONE; - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_MasterTxCpltCallback(hi2c); } } - else + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - hi2c->XferCount = 0; - hi2c->State = HAL_I2C_STATE_READY; - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if (hi2c->Mode == HAL_I2C_MODE_MEM) { - HAL_I2C_ErrorCallback(hi2c); + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + HAL_I2C_MemRxCpltCallback(hi2c); } else { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + HAL_I2C_MasterRxCpltCallback(hi2c); } } } /** - * @brief DMA I2C slave receive process complete callback. - * @param hdma: DMA handle + * @brief I2C Slave complete process. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. * @retval None */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize) { + hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c); + hi2c->XferCount += hi2c->XferSize; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } } - /* Clear STOPF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK) + /* Store Last receive data if any */ + if(((ITFlags & I2C_FLAG_RXNE) != RESET)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + + if((hi2c->XferSize > 0)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } } - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { - HAL_I2C_ErrorCallback(hi2c); + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); } - else + else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Rx Complete callback */ HAL_I2C_SlaveRxCpltCallback(hi2c); } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Slave Tx Complete callback */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } } /** - * @brief DMA I2C Memory Write process complete callback - * @param hdma : DMA handle + * @brief I2C Listen complete process. + * @param hi2c: I2C handle. + * @param ITFlags: Interrupt flags to handle. * @retval None */ -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { - uint16_t DevAddress; - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + /* Store Last receive data if any */ + if(((ITFlags & I2C_FLAG_RXNE) != RESET)) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + /* Read data from RXDR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else + if((hi2c->XferSize > 0)) { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } + hi2c->XferSize--; + hi2c->XferCount--; - /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); +} + +/** + * @brief I2C interrupts error process. + * @param hi2c: I2C handle. + * @param ErrorCode: Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = I2C_Slave_ISR_IT; + } else { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } + } + /* Abort DMA RX transfer if any */ + else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - hi2c->XferCount = 0; + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) + { + hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; - hi2c->State = HAL_I2C_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c: I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00; + } + + /* Flush TX register if not empty */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if(hi2c->XferCount == 0) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + /* Set the XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - HAL_I2C_ErrorCallback(hi2c); + hi2c->XferSize = MAX_NBYTE_SIZE; } else { - HAL_I2C_MemTxCpltCallback(hi2c); + hi2c->XferSize = hi2c->XferCount; } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } /** - * @brief DMA I2C Memory Read process complete callback + * @brief DMA I2C slave transmit process complete callback. * @param hdma: DMA handle * @retval None */ -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint16_t DevAddress; +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - /* Check if last DMA request was done with RELOAD */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) + /* If last transfer, enable STOP interrupt */ + if(hi2c->XferCount == 0) { - /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - hi2c->pBuffPtr += hi2c->XferSize; - hi2c->XferCount -= hi2c->XferSize; - if(hi2c->XferCount > 255) - { - hi2c->XferSize = 255; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > 255 */ - if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) ) - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_ErrorCallback(hi2c); - } - else - { - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - } + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); } + /* else prepare a new DMA transfer and enable TCReload interrupt */ else { - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + /* Set the XferSize to transfer */ + if(hi2c->XferCount > MAX_NBYTE_SIZE) { - HAL_I2C_ErrorCallback(hi2c); + hi2c->XferSize = MAX_NBYTE_SIZE; } else { - HAL_I2C_MemRxCpltCallback(hi2c); + hi2c->XferSize = hi2c->XferCount; } + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } /** - * @brief DMA I2C communication error callback. - * @param hdma : DMA handle + * @brief DMA I2C slave receive process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma: DMA handle * @retval None */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) +static void I2C_DMAError(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - hi2c->XferCount = 0; + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma: DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hi2c->State = HAL_I2C_STATE_READY; + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + /* Reset AbortCpltCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - HAL_I2C_ErrorCallback(hi2c); + /* Check if come from abort from user */ + if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT) + { + hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); + } } /** * @brief This function handles I2C Communication Timeout. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag: specifies the I2C flag to check. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag: Specifies the I2C flag to check. * @param Status: The new Flag status (SET or RESET). * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - } - else +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; } } } @@ -3978,19 +4391,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -3998,10 +4410,11 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4010,34 +4423,33 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } } } - return HAL_OK; + return HAL_OK; } /** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) -{ - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4050,20 +4462,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) -{ - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK) + if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -4079,6 +4489,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4087,7 +4498,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4103,16 +4514,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /** * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @param Timeout: Timeout duration + * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ @@ -4122,9 +4531,11 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; @@ -4138,17 +4549,15 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4161,20 +4570,13 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hi2c: I2C handle. - * @param DevAddress: specifies the slave address to be programmed. - * @param Size: specifies the number of bytes to be programmed. + * @param DevAddress: Specifies the slave address to be programmed. + * @param Size: Specifies the number of bytes to be programmed. * This parameter must be a value between 0 and 255. - * @param Mode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_RELOAD_MODE: Enable Reload mode . - * @arg I2C_AUTOEND_MODE: Enable Automatic end mode. - * @arg I2C_SOFTEND_MODE: Enable Software end mode. - * @param Request: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition. - * @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0). - * @arg I2C_GENERATE_START_READ: Generate Restart for read request. - * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request. + * @param Mode: New state of the I2C START condition generation. + * This parameter can be a value of @ref I2C_RELOAD_END_MODE. + * @param Request: New state of the I2C START condition generation. + * This parameter can be a value of I2C_START_STOP_MODE. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) @@ -4194,15 +4596,151 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui /* update tmpreg */ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); + (uint32_t)Mode | (uint32_t)Request); /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; -} + hi2c->Instance->CR2 = tmpreg; +} /** - * @} + * @brief Manage the enabling of Interrupts. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0; + + if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition. + * @retval HAL status */ +static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0; + + if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + + return HAL_OK; +} /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h index 0de3a38d6f4..d41ace7ca35 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_I2C_H @@ -54,7 +54,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types * @{ */ @@ -73,22 +73,22 @@ typedef struct This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_addressing_mode */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_dual_addressing_mode */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_own_address2_masks */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_general_call_addressing_mode */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_nostretch_mode */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ }I2C_InitTypeDef; @@ -97,25 +97,82 @@ typedef struct */ /** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (IP in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) * @{ */ typedef enum { - HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ - HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ - HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ - HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ - HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ - HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */ - HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + }HAL_I2C_StateTypeDef; +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 + * 0 : None + * 1 : Memory (HAL I2C communication is in Memory Mode) + * b5 + * 0 : None + * 1 : Slave (HAL I2C communication is in Slave Mode) + * b4 + * 0 : None + * 1 : Master (HAL I2C communication is in Master Mode) + * b3-b2-b1-b0 (not used) + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +}HAL_I2C_ModeTypeDef; + /** * @} */ @@ -123,45 +180,56 @@ typedef enum /** @defgroup I2C_Error_Code_definition I2C Error Code definition * @brief I2C Error Code definition * @{ - */ -#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */ -/** + */ +#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) /*!< Abort user request */ +/** * @} */ -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition * @brief I2C handle Structure definition * @{ */ -typedef struct +typedef struct __I2C_HandleTypeDef { - I2C_TypeDef *Instance; /*!< I2C registers base address */ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - I2C_InitTypeDef Init; /*!< I2C communication parameters */ + uint16_t XferSize; /*!< I2C transfer size */ - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + __IO uint16_t XferCount; /*!< I2C transfer counter */ - uint16_t XferSize; /*!< I2C transfer size */ + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ - __IO uint16_t XferCount; /*!< I2C transfer counter */ + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - HAL_LockTypeDef Lock; /*!< I2C locking object */ + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + HAL_LockTypeDef Lock; /*!< I2C locking object */ - __IO uint32_t ErrorCode; /*!< I2C Error code */ + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ }I2C_HandleTypeDef; /** * @} @@ -176,80 +244,101 @@ typedef struct * @{ */ -/** @defgroup I2C_addressing_mode I2C addressing mode +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode * @{ */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) -#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) +#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U) /** * @} */ -/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode * @{ */ -#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U) #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ -/** @defgroup I2C_own_address2_masks I2C own address2 masks +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks * @{ */ -#define I2C_OA2_NOMASK ((uint8_t)0x00) -#define I2C_OA2_MASK01 ((uint8_t)0x01) -#define I2C_OA2_MASK02 ((uint8_t)0x02) -#define I2C_OA2_MASK03 ((uint8_t)0x03) -#define I2C_OA2_MASK04 ((uint8_t)0x04) -#define I2C_OA2_MASK05 ((uint8_t)0x05) -#define I2C_OA2_MASK06 ((uint8_t)0x06) -#define I2C_OA2_MASK07 ((uint8_t)0x07) +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) /** * @} */ -/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode * @{ */ -#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U) #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ -/** @defgroup I2C_nostretch_mode I2C nostretch mode +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode * @{ */ -#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U) #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ -/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size * @{ */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) +#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U) +#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U) /** * @} - */ + */ -/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition +/** @defgroup I2C_XferDirection I2C Transfer Direction + * @{ + */ +#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U) +#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode * @{ */ #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE ((uint32_t)0x00000000) +#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U) /** * @} */ -/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode * @{ */ -#define I2C_NO_STARTSTOP ((uint32_t)0x00000000) +#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U) #define I2C_GENERATE_STOP I2C_CR2_STOP #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_WRITE I2C_CR2_START @@ -270,7 +359,6 @@ typedef struct #define I2C_IT_ADDRI I2C_CR1_ADDRIE #define I2C_IT_RXI I2C_CR1_RXIE #define I2C_IT_TXI I2C_CR1_TXIE - /** * @} */ @@ -308,122 +396,127 @@ typedef struct * @{ */ -/** @brief Reset I2C handle state - * @param __HANDLE__: specifies the I2C Handle. +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -/** @brief Enable the specified I2C interrupts. - * @param __HANDLE__: specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable. +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable - * @arg I2C_IT_STOPI: STOP detection interrupt enable - * @arg I2C_IT_NACKI: NACK received interrupt enable - * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable - * + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * * @retval None */ - -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) -/** @brief Disable the specified I2C interrupts. - * @param __HANDLE__: specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to disable. +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable - * @arg I2C_IT_STOPI: STOP detection interrupt enable - * @arg I2C_IT_NACKI: NACK received interrupt enable - * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable * * @retval None */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) -/** @brief Checks if the specified I2C interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2C Handle. - * @param __INTERRUPT__: specifies the I2C interrupt source to check. +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable - * @arg I2C_IT_STOPI: STOP detection interrupt enable - * @arg I2C_IT_NACKI: NACK received interrupt enable - * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Checks whether the specified I2C flag is set or not. - * @param __HANDLE__: specifies the I2C Handle. - * @param __FLAG__: specifies the flag to check. +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg I2C_FLAG_TXE: Transmit data register empty - * @arg I2C_FLAG_TXIS: Transmit interrupt status - * @arg I2C_FLAG_RXNE: Receive data register not empty - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_TC: Transfer complete (master mode) - * @arg I2C_FLAG_TCR: Transfer complete reload - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus alert - * @arg I2C_FLAG_BUSY: Bus busy - * @arg I2C_FLAG_DIR: Transfer direction (slave mode) + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) * - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @retval The new state of __FLAG__ (SET or RESET). */ -#define I2C_FLAG_MASK ((uint32_t)0x0001FFFF) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) -/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__: specifies the I2C Handle. - * @param __FLAG__: specifies the flag to clear. +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus alert - * + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK)) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__: specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} - */ + */ -/* Include I2C HAL Extension module */ +/* Include I2C HAL Extended module */ #include "stm32f7xx_hal_i2c_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -441,7 +534,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions * @{ @@ -464,6 +557,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); @@ -473,11 +574,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); /** * @} - */ + */ -/** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -485,18 +586,22 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); /** * @} */ -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions * @{ */ -/* Peripheral State and Errors functions *************************************/ +/* Peripheral State, Mode and Error functions *********************************/ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** @@ -506,7 +611,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} */ - + /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants * @{ @@ -522,49 +627,58 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); */ #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) + ((CALL) == I2C_GENERALCALL_ENABLE)) #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16) +#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} @@ -586,7 +700,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} */ - + #ifdef __cplusplus } #endif @@ -595,4 +709,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32F7xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c index 7fd7fa86120..07cdd7abfc3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c @@ -2,35 +2,39 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: * + Extended features functions - * + * @verbatim ============================================================================== ##### I2C peripheral Extended features ##### ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32L4XX + + [..] Comparing to other previous devices, the I2C interface for STM32F7XX devices contains the following additional features - + (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode - + (+) Disable or enable Fast Mode Plus (available only for STM32F76xxx/STM32F77xxx + devices) + ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to: (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisbleFastModePlus() @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,8 +58,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -85,22 +89,23 @@ /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters + (+) Configure Fast Mode Plus @endverbatim * @{ */ - + /** - * @brief Configures I2C Analog noise filter. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter : new state of the Analog filter. + * @brief Configure I2C Analog noise filter. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter: New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) @@ -109,41 +114,42 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) - || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else { return HAL_BUSY; } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; } /** - * @brief Configures I2C Digital noise filter. - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F. + * @brief Configure I2C Digital noise filter. + * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) @@ -154,49 +160,88 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) - || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)) + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else { return HAL_BUSY; } - - /* Process Locked */ - __HAL_LOCK(hi2c); +} - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8; +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus: Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_I2C_ENABLE(hi2c); + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus: Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - hi2c->State = HAL_I2C_STATE_READY; + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} - */ + */ /** * @} - */ + */ #endif /* HAL_I2C_MODULE_ENABLED */ /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h index ff2191e722e..12203e7e9fa 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_I2C_EX_H @@ -44,7 +44,7 @@ #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" +#include "stm32f7xx_hal_def.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ @@ -54,7 +54,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants @@ -64,13 +64,32 @@ /** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ - +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP + +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP + +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + /** * @} */ @@ -81,6 +100,11 @@ /* Peripheral Control methods ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants * @{ @@ -88,7 +112,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros @@ -97,10 +121,45 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) +#elif defined(SYSCFG_PMC_I2C1_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) +#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ /** * @} - */ + */ +/** + * @} + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions @@ -109,16 +168,16 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ /* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c index 457d78a1bb9..5563b9cb99b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -109,7 +109,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -330,10 +330,10 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ (uint16_t)hi2s->Init.CPOL)))); - + /* Write to SPIx I2SCFGR */ - hi2s->Instance->I2SCFGR = tmpreg; - + hi2s->Instance->I2SCFGR = tmpreg; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State= HAL_I2S_STATE_READY; @@ -1347,7 +1347,7 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s) /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */ switch(hi2s->Init.ClockSource) { - case I2S_CLOCK_SYSCLK : + case I2S_CLOCK_PLL : { /* Configure the PLLI2S division factor */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h index bfb8ac3c099..b2777bef953 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -91,14 +91,14 @@ typedef struct */ typedef enum { - HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */ - HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ }HAL_I2S_StateTypeDef; @@ -152,12 +152,12 @@ typedef struct *@brief I2S Error Code * @{ */ -#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */ -#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */ -#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */ -#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */ +#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */ +#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004U) /*!< UDR error */ +#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010U) /*!< Unknow Error error */ /** * @} @@ -165,8 +165,8 @@ typedef struct /** @defgroup I2S_Clock_Source I2S Clock Source * @{ */ -#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) -#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002) +#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U) +#define I2S_CLOCK_PLL ((uint32_t)0x00000002U) /** * @} */ @@ -174,10 +174,10 @@ typedef struct /** @defgroup I2S_Mode I2S Mode * @{ */ -#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) -#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) -#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) -#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) +#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) +#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U) +#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U) +#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U) /** * @} */ @@ -185,11 +185,11 @@ typedef struct /** @defgroup I2S_Standard I2S Standard * @{ */ -#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) -#define I2S_STANDARD_MSB ((uint32_t)0x00000010) -#define I2S_STANDARD_LSB ((uint32_t)0x00000020) -#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030) -#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0) +#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) +#define I2S_STANDARD_MSB ((uint32_t)0x00000010U) +#define I2S_STANDARD_LSB ((uint32_t)0x00000020U) +#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U) +#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U) /** * @} */ @@ -197,10 +197,10 @@ typedef struct /** @defgroup I2S_Data_Format I2S Data Format * @{ */ -#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) -#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001) -#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003) -#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005) +#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) +#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U) +#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U) +#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U) /** * @} */ @@ -209,7 +209,7 @@ typedef struct * @{ */ #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) +#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -217,16 +217,16 @@ typedef struct /** @defgroup I2S_Audio_Frequency I2S Audio Frequency * @{ */ -#define I2S_AUDIOFREQ_192K ((uint32_t)192000) -#define I2S_AUDIOFREQ_96K ((uint32_t)96000) -#define I2S_AUDIOFREQ_48K ((uint32_t)48000) -#define I2S_AUDIOFREQ_44K ((uint32_t)44100) -#define I2S_AUDIOFREQ_32K ((uint32_t)32000) -#define I2S_AUDIOFREQ_22K ((uint32_t)22050) -#define I2S_AUDIOFREQ_16K ((uint32_t)16000) -#define I2S_AUDIOFREQ_11K ((uint32_t)11025) -#define I2S_AUDIOFREQ_8K ((uint32_t)8000) -#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) +#define I2S_AUDIOFREQ_192K ((uint32_t)192000U) +#define I2S_AUDIOFREQ_96K ((uint32_t)96000U) +#define I2S_AUDIOFREQ_48K ((uint32_t)48000U) +#define I2S_AUDIOFREQ_44K ((uint32_t)44100U) +#define I2S_AUDIOFREQ_32K ((uint32_t)32000U) +#define I2S_AUDIOFREQ_22K ((uint32_t)22050U) +#define I2S_AUDIOFREQ_16K ((uint32_t)16000U) +#define I2S_AUDIOFREQ_11K ((uint32_t)11025U) +#define I2S_AUDIOFREQ_8K ((uint32_t)8000U) +#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U) /** * @} */ @@ -235,7 +235,7 @@ typedef struct /** @defgroup I2S_Clock_Polarity I2S Clock Polarity * @{ */ -#define I2S_CPOL_LOW ((uint32_t)0x00000000) +#define I2S_CPOL_LOW ((uint32_t)0x00000000U) #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) /** * @} @@ -334,7 +334,7 @@ typedef struct */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ tmpreg = (__HANDLE__)->Instance->DR; \ tmpreg = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg); \ @@ -346,7 +346,7 @@ typedef struct */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \ do{ \ -__IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ tmpreg = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg); \ } while(0) @@ -434,7 +434,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @{ */ #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ - ((CLOCK) == I2S_CLOCK_SYSCLK)) + ((CLOCK) == I2S_CLOCK_PLL)) #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ ((MODE) == I2S_MODE_SLAVE_RX) || \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c index c639a5dfd92..bf865611daa 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c @@ -2,10 +2,10 @@ ****************************************************************************** * @file stm32f7xx_hal_irda.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief IRDA HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): * + Initialization and de-initialization methods * + IO operation methods @@ -17,7 +17,7 @@ ============================================================================== [..] The IRDA HAL driver can be used as follows: - + (#) Declare a IRDA_HandleTypeDef handle structure. (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API: (##) Enable the USARTx interface clock. @@ -32,72 +32,72 @@ and HAL_IRDA_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx stream. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx Stream. (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream. - (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler + (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler and Mode(Receiver/Transmitter) in the hirda Init structure. (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_IRDA_MspInit() API. - -@@- The specific IRDA interrupts (Transmission complete interrupt, + -@@- The specific IRDA interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - + (#) Three operation modes are available within this driver : - + *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_IRDA_ErrorCallback - *** DMA mode IO operation *** + *** DMA mode IO operation *** ============================= [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can + (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback *** IRDA HAL driver macros list *** =================================== [..] Below the list of most used macros in IRDA HAL driver. - - (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral - (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral + + (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral + (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt - + (@) You can refer to the IRDA HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -122,7 +122,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -136,14 +136,14 @@ * @{ */ #ifdef HAL_IRDA_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup IRDA_Private_Constants * @{ */ -#define TEACK_REACK_TIMEOUT 1000 -#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000 +#define TEACK_REACK_TIMEOUT 1000U +#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /** @@ -159,10 +159,13 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAError(DMA_HandleTypeDef *hdma); +static void IRDA_DMAError(DMA_HandleTypeDef *hdma); +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); @@ -174,27 +177,27 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); * @{ */ -/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy in IrDA mode. - (+) For the asynchronous mode only these parameters can be configured: + (+) For the asynchronous mode only these parameters can be configured: (++) BaudRate - (++) WordLength + (++) WordLength (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), please refer to Reference manual for possible IRDA frame formats. (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may not be rejected. The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and + specification specifies a minimum of 10 ms delay between transmission and reception (IrDA is a half duplex protocol). (++) Mode: Receiver/transmitter modes (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode. @@ -215,78 +218,79 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); */ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) { - /* Check the IRDA handle allocation */ - if(hirda == NULL) - { - return HAL_ERROR; - } + /* Check the IRDA handle allocation */ + if(hirda == NULL) + { + return HAL_ERROR; + } - /* Check the USART/UART associated to the IRDA handle */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + /* Check the USART/UART associated to the IRDA handle */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - if(hirda->State == HAL_IRDA_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hirda->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_IRDA_MspInit(hirda); - } + if(hirda->gState == HAL_IRDA_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hirda->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_IRDA_MspInit(hirda); + } - hirda->State = HAL_IRDA_STATE_BUSY; + hirda->gState = HAL_IRDA_STATE_BUSY; - /* Disable the Peripheral to update the configuration registers */ - __HAL_IRDA_DISABLE(hirda); + /* Disable the Peripheral to update the configuration registers */ + __HAL_IRDA_DISABLE(hirda); - /* Set the IRDA Communication parameters */ - IRDA_SetConfig(hirda); + /* Set the IRDA Communication parameters */ + IRDA_SetConfig(hirda); - /* In IRDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ - hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP); - hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL); + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL); - /* set the UART/USART in IRDA mode */ - hirda->Instance->CR3 |= USART_CR3_IREN; + /* set the UART/USART in IRDA mode */ + SET_BIT(hirda->Instance->CR3, USART_CR3_IREN); - /* Enable the Peripheral */ - __HAL_IRDA_ENABLE(hirda); + /* Enable the Peripheral */ + __HAL_IRDA_ENABLE(hirda); - /* TEACK and/or REACK to check before moving hirda->State to Ready */ - return (IRDA_CheckIdleState(hirda)); + /* TEACK and/or REACK to check before moving hirda->State to Ready */ + return (IRDA_CheckIdleState(hirda)); } /** - * @brief DeInitializes the IRDA peripheral + * @brief DeInitializes the IRDA peripheral * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) { - /* Check the IRDA handle allocation */ - if(hirda == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - - hirda->State = HAL_IRDA_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_IRDA_MspDeInit(hirda); - /* Disable the Peripheral */ - __HAL_IRDA_DISABLE(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->State = HAL_IRDA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hirda); - - return HAL_OK; + /* Check the IRDA handle allocation */ + if(hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + hirda->gState = HAL_IRDA_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_IRDA_MspDeInit(hirda); + /* Disable the Peripheral */ + __HAL_IRDA_DISABLE(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_RESET; + hirda->RxState = HAL_IRDA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hirda); + + return HAL_OK; } /** @@ -295,14 +299,14 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_IRDA_MspInit could be implemented in the user file - */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_IRDA_MspInit could be implemented in the user file + */ } /** @@ -311,52 +315,52 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_IRDA_MspDeInit could be implemented in the user file - */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_IRDA_MspDeInit could be implemented in the user file + */ } /** * @} */ -/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions - * @brief IRDA Transmit/Receive functions +/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions + * @brief IRDA Transmit/Receive functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== This subsection provides a set of functions allowing to manage the IRDA data transfers. [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. (#) There are two modes of transfer: - (++) Blocking mode: the communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: the communication is performed using Interrupts + (++) Blocking mode: the communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: the communication is performed using Interrupts or DMA, these API's return the HAL status. - The end of the data processing will be indicated through the - dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks + The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks will be executed respectively at the end of the Transmit or Receive process The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected (#) Blocking mode API's are : (++) HAL_IRDA_Transmit() - (++) HAL_IRDA_Receive() - + (++) HAL_IRDA_Receive() + (#) Non-Blocking mode API's with Interrupt are : (++) HAL_IRDA_Transmit_IT() (++) HAL_IRDA_Receive_IT() @@ -372,7 +376,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) (++) HAL_IRDA_TxCpltCallback() (++) HAL_IRDA_RxCpltCallback() (++) HAL_IRDA_ErrorCallback() - + @endverbatim * @{ */ @@ -383,165 +387,147 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent - * @param Timeout: Specify timeout value + * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + uint16_t* tmp; + uint32_t tickstart = 0U; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0) + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { - hirda->TxXferCount--; - - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + + /* Process Locked */ + __HAL_LOCK(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + while(hirda->TxXferCount > 0U) { - tmp = (uint16_t*) pData; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData +=2; + hirda->TxXferCount--; + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) pData; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pData +=2; + } + else + { + hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU); + } } - else - { - hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; } - } - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; } else { - hirda->State = HAL_IRDA_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** - * @brief Receive an amount of data in blocking mode. + * @brief Receive an amount of data in blocking mode. * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received - * @param Timeout: Specify timeout value + * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint16_t uhMask; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; +{ + uint16_t* tmp; + uint16_t uhMask; + uint32_t tickstart = 0U; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - - /* Computation of the mask to apply to the RDR register - of the UART associated to the IRDA */ - IRDA_MASK_COMPUTATION(hirda); - uhMask = hirda->Mask; - - /* Check data remaining to be received */ - while(hirda->RxXferCount > 0) + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { - hirda->RxXferCount--; - - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t*) pData ; - *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - pData +=2; - } - else - { - *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); - } - } - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to the RDR register + of the UART associated to the IRDA */ + IRDA_MASK_COMPUTATION(hirda); + uhMask = hirda->Mask; + + /* Check data remaining to be received */ + while(hirda->RxXferCount > 0U) + { + hirda->RxXferCount--; + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) pData ; + *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); + pData +=2; + } + else + { + *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + } + } + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; } else { - hirda->State = HAL_IRDA_STATE_READY; + return HAL_BUSY; } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } } /** - * @brief Send an amount of data in non blocking mode. + * @brief Send an amount of data in non blocking mode. * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -550,49 +536,40 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + + return HAL_OK; } else { - hirda->State = HAL_IRDA_STATE_BUSY_TX; + return HAL_BUSY; } - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } } /** - * @brief Receives an amount of data in non blocking mode. + * @brief Receives an amount of data in non blocking mode. * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -600,57 +577,51 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - - /* Computation of the mask to apply to the RDR register - of the UART associated to the IRDA */ - IRDA_MASK_COMPUTATION(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) +{ + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to the RDR register + of the UART associated to the IRDA */ + IRDA_MASK_COMPUTATION(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the IRDA Data Register not empty Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE); + + return HAL_OK; } else { - hirda->State = HAL_IRDA_STATE_BUSY_RX; + return HAL_BUSY; } - - /* Enable the IRDA Parity Error Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the IRDA Data Register not empty Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } } /** - * @brief Sends an amount of data in non blocking mode. + * @brief Sends an amount of data in non blocking mode. * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -659,66 +630,62 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + uint32_t *tmp; + + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmatx->XferErrorCallback = IRDA_DMAError; + + /* Set the DMA abort callback */ + hirda->hdmatx->XferAbortCallback = NULL; + + /* Enable the IRDA transmit DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size); + + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the IRDA CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; } else { - hirda->State = HAL_IRDA_STATE_BUSY_TX; + return HAL_BUSY; } - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; - - /* Set the IRDA DMA half transfer complete callback */ - hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmatx->XferErrorCallback = IRDA_DMAError; - - /* Enable the IRDA transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ - hirda->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } } /** - * @brief Receives an amount of data in non blocking mode. + * @brief Receives an amount of data in non blocking mode. * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -728,57 +695,60 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; + uint32_t *tmp; - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmarx->XferErrorCallback = IRDA_DMAError; + + /* Set the DMA abort callback */ + hirda->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; } else { - hirda->State = HAL_IRDA_STATE_BUSY_RX; + return HAL_BUSY; } - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; - - /* Set the IRDA DMA half transfer complete callback */ - hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmarx->XferErrorCallback = IRDA_DMAError; - - /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the IRDA CR3 register */ - hirda->Instance->CR3 |= USART_CR3_DMAR; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } } /** @@ -789,30 +759,30 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData */ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) { - /* Process Locked */ - __HAL_LOCK(hirda); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - /* Disable the UART DMA Tx request */ - hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - /* Disable the UART DMA Rx request */ - hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx & Rx requests */ - hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; + /* Process Locked */ + __HAL_LOCK(hirda); + + if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)&& + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)&& + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; } /** @@ -823,36 +793,31 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) */ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) { - /* Process Locked */ - __HAL_LOCK(hirda); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - hirda->Instance->CR3 |= USART_CR3_DMAT; - } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); - - /* Enable the UART DMA Rx request */ - hirda->Instance->CR3 |= USART_CR3_DMAR; - } - else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); - - /* Enable the UART DMA Tx & Rx request */ - hirda->Instance->CR3 |= USART_CR3_DMAT; - hirda->Instance->CR3 |= USART_CR3_DMAR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; + /* Process Locked */ + __HAL_LOCK(hirda); + + if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; } /** @@ -863,31 +828,56 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) */ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) { - /* The Lock is not implemented on this API to allow the user application - to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / - HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Disable the UART Tx/Rx DMA requests */ - hirda->Instance->CR3 &= ~USART_CR3_DMAT; - hirda->Instance->CR3 &= ~USART_CR3_DMAR; - - /* Abort the UART DMA tx channel */ - if(hirda->hdmatx != NULL) - { - HAL_DMA_Abort(hirda->hdmatx); - } - /* Abort the UART DMA rx channel */ - if(hirda->hdmarx != NULL) - { - HAL_DMA_Abort(hirda->hdmarx); - } - - hirda->State = HAL_IRDA_STATE_READY; - - return HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / + HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Stop IRDA DMA Tx request if ongoing */ + if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel */ + if(hirda->hdmatx != NULL) + { + HAL_DMA_Abort(hirda->hdmatx); + } + IRDA_EndTxTransfer(hirda); + } + + /* Stop IRDA DMA Rx request if ongoing */ + if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if(hirda->hdmarx != NULL) + { + HAL_DMA_Abort(hirda->hdmarx); + } + IRDA_EndRxTransfer(hirda); + } + return HAL_OK; +} + +/** + * @brief DMA IRDA communication abort callback, when call by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma: DMA handle. + * @retval None + */ +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; + + HAL_IRDA_ErrorCallback(hirda); } /** @@ -898,71 +888,160 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) */ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { - /* IRDA parity error interrupt occurred -------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_PE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; - } - - /* IRDA frame error interrupt occurred --------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_FE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; - } - - /* IRDA noise error interrupt occurred --------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_NE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; - } - - /* IRDA Over-Run interrupt occurred -----------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; - } - - /* Call IRDA Error Call back function if need be --------------------------*/ - if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) - { - HAL_IRDA_ErrorCallback(hirda); - } - - /* IRDA in mode Receiver ---------------------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET)) - { - IRDA_Receive_IT(hirda); - /* Clear RXNE interrupt flag */ - __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); - } - - /* IRDA in mode Transmitter ------------------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET)) - { - IRDA_Transmit_IT(hirda); - } - - /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) - { - IRDA_EndTransmit_IT(hirda); - } + uint32_t isrflags, cr1its, cr3its, errorflags; + + isrflags = READ_REG(hirda->Instance->ISR); + cr1its = READ_REG(hirda->Instance->CR1); + cr3its = READ_REG(hirda->Instance->CR3); + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == RESET) + { + /* IRDA in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + IRDA_Receive_IT(hirda); + /* Clear RXNE interrupt flag */ + __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); + } + } + + /* If some errors occur */ + if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) + { + /* IRDA parity error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); + hirda->ErrorCode |= HAL_IRDA_ERROR_PE; + } + + /* IRDA frame error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); + hirda->ErrorCode |= HAL_IRDA_ERROR_FE; + } + + /* IRDA noise error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + } + + /* IRDA Over-Run interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + } + + /* Call IRDA Error Call back function if need be --------------------------*/ + if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + { + /* IRDA in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + IRDA_Receive_IT(hirda); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + if (((hirda->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the IRDA state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + IRDA_EndRxTransfer(hirda); + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_IRDA_ErrorCallback(hirda); + } + } + else + { + /* Call user error callback */ + HAL_IRDA_ErrorCallback(hirda); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_IRDA_ErrorCallback(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* IRDA in mode Transmitter ------------------------------------------------*/ + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + IRDA_Transmit_IT(hirda); + return; + } + + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ + if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + IRDA_EndTransmit_IT(hirda); + return; + } +} + +/** + * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). + * @param hirda: IRDA handle. + * @retval None + */ +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion). + * @param hirda: IRDA handle. + * @retval None + */ +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; } /** @@ -971,14 +1050,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file - */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file + */ } /** @@ -987,14 +1066,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) * the configuration information for the specified USART module. * @retval None */ - __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file - */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file + */ } /** @@ -1005,12 +1084,12 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file - */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file + */ } /** @@ -1021,12 +1100,12 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) */ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_RxCpltCallback can be implemented in the user file - */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxCpltCallback can be implemented in the user file + */ } /** @@ -1035,30 +1114,30 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_ErrorCallback can be implemented in the user file - */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback can be implemented in the user file + */ } /** * @} */ -/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions - * @brief IRDA control functions +/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions + * @brief IRDA control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the IRDA. - (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral. + (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral. (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters. @endverbatim * @{ @@ -1072,7 +1151,11 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { - return hirda->State; + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = hirda->gState; + temp2 = hirda->RxState; + + return (HAL_IRDA_StateTypeDef)(temp1 | temp2); } /** @@ -1083,7 +1166,11 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) */ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) { - return hirda->ErrorCode; + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = hirda->gState; + temp2 = hirda->RxState; + + return (HAL_IRDA_StateTypeDef)(temp1 | temp2); } /** @@ -1091,59 +1178,59 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) */ /** - * @brief Configure the IRDA peripheral + * @brief Configure the IRDA peripheral * @param hirda: irda handle * @retval None */ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { - uint32_t tmpreg = 0x00000000; - uint32_t clocksource = 0x00000000; - - /* Check the communication parameters */ - assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); - assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); - assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); - assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); - assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); - assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the IRDA Word Length, Parity and transfer Mode: - Set the M bits according to hirda->Init.WordLength value - Set PCE and PS bits according to hirda->Init.Parity value - Set TE and RE bits according to hirda->Init.Mode value */ - tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; - - MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); - - /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler); - - /*-------------------------- USART BRR Configuration -----------------------*/ - IRDA_GETCLOCKSOURCE(hirda, clocksource); - switch (clocksource) - { - case IRDA_CLOCKSOURCE_PCLK1: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_PCLK2: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate); - break; - default: - break; - } + uint32_t tmpreg = 0x00000000U; + uint32_t clocksource = 0x00000000U; + + /* Check the communication parameters */ + assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); + assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); + assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); + assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); + assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); + assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the IRDA Word Length, Parity and transfer Mode: + Set the M bits according to hirda->Init.WordLength value + Set PCE and PS bits according to hirda->Init.Parity value + Set TE and RE bits according to hirda->Init.Mode value */ + tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; + + MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); + + /*-------------------------- USART GTPR Configuration ----------------------*/ + MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + IRDA_GETCLOCKSOURCE(hirda, clocksource); + switch (clocksource) + { + case IRDA_CLOCKSOURCE_PCLK1: + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_PCLK2: + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_HSI: + hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_SYSCLK: + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_LSE: + hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate); + break; + default: + break; + } } /** @@ -1154,158 +1241,124 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) { - /* Initialize the IRDA ErrorCode */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - /* Check if the Transmitter is enabled */ - if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - hirda->State= HAL_IRDA_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - hirda->State= HAL_IRDA_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Initialize the IRDA state*/ - hirda->State= HAL_IRDA_STATE_READY; - - return HAL_OK; + uint32_t tickstart = 0U; + + /* Initialize the IRDA ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Initialize the IRDA state*/ + hirda->gState= HAL_IRDA_STATE_READY; + hirda->RxState= HAL_IRDA_STATE_READY; + + return HAL_OK; } /** * @brief This function handles IRDA Communication Timeout. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param Flag: specifies the IRDA flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param Flag specifies the IRDA flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET) + /* Wait until flag is set */ + while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - hirda->State= HAL_IRDA_STATE_READY; + hirda->gState= HAL_IRDA_STATE_READY; + hirda->RxState= HAL_IRDA_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hirda); + /* Process Unlocked */ + __HAL_UNLOCK(hirda); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } - } } - } - else - { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State= HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; + return HAL_OK; } /** - * @brief Send an amount of data in non blocking mode. + * @brief Send an amount of data in non blocking mode. * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp; - - if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) - { - if(hirda->TxXferCount == 0) + uint16_t* tmp; + + /* Check that a Tx process is ongoing */ + if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - /* Disable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_TxCpltCallback(hirda); - - return HAL_OK; + if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) + { + tmp = (uint16_t*) hirda->pTxBuffPtr; + hirda->Instance->RDR = (uint16_t)(*tmp & (uint16_t)0x01FFU); + if(hirda->Init.Parity == IRDA_PARITY_NONE) + { + hirda->pTxBuffPtr += 2U; + } + else + { + hirda->pTxBuffPtr += 1U; + } + } + else + { + hirda->Instance->RDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU); + } + + if(--hirda->TxXferCount == 0U) + { + /* Disable the IRDA Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + } + + return HAL_OK; } else { - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t*) hirda->pTxBuffPtr; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - hirda->pTxBuffPtr += 2; - } - else - { - hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); - } - hirda->TxXferCount--; - return HAL_OK; + return HAL_BUSY; } - } - else - { - return HAL_BUSY; - } } /** @@ -1316,29 +1369,22 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) { - /* Disable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { + /* Disable the IRDA Transmit Complete Interrupt */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_TxCpltCallback(hirda); - - return HAL_OK; + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Tx process is ended, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + HAL_IRDA_TxCpltCallback(hirda); + + return HAL_OK; } /** - * @brief Receive an amount of data in non blocking mode. + * @brief Receive an amount of data in non blocking mode. * Function called under interruption only, once * interruptions have been enabled by HAL_IRDA_Receive_IT() * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains @@ -1347,156 +1393,164 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp; - uint16_t uhMask = hirda->Mask; - - if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) - { - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + uint16_t* tmp; + uint16_t uhdata; + uint16_t uhMask = hirda->Mask; + + if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - tmp = (uint16_t*) hirda->pRxBuffPtr ; - *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - hirda->pRxBuffPtr +=2; + uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) hirda->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + hirda->pRxBuffPtr +=2U; + } + else + { + *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + } + + if(--hirda->RxXferCount == 0U) + { + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE); + + /* Disable the IRDA Parity Error Interrupt */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + HAL_IRDA_RxCpltCallback(hirda); + + return HAL_OK; + } + return HAL_OK; } else { - *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + /* Clear RXNE interrupt flag */ + __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); + return HAL_BUSY; } - - if(--hirda->RxXferCount == 0) - { - while(HAL_IS_BIT_SET(hirda->Instance->ISR, IRDA_FLAG_RXNE)) - { - } - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_RxCpltCallback(hirda); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } } - + /** - * @brief DMA IRDA Tx transfer completed callback + * @brief DMA IRDA Tx transfer completed callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode*/ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - hirda->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ - hirda->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); - - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); - } - /* DMA Circular mode */ - else - { - HAL_IRDA_TxCpltCallback(hirda); - } + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode*/ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + hirda->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { + HAL_IRDA_TxCpltCallback(hirda); + } } /** - * @brief DMA IRDA receive process half complete callback + * @brief DMA IRDA receive process half complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_IRDA_TxHalfCpltCallback(hirda); + HAL_IRDA_TxHalfCpltCallback(hirda); } /** - * @brief DMA IRDA Rx Transfer completed callback + * @brief DMA IRDA Rx Transfer completed callback * @param hdma: DMA handle * @retval None */ -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - hirda->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the IRDA CR3 register */ - hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { - hirda->State = HAL_IRDA_STATE_READY; + hirda->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; } - } - HAL_IRDA_RxCpltCallback(hirda); + HAL_IRDA_RxCpltCallback(hirda); } /** - * @brief DMA IRDA receive process half complete callback + * @brief DMA IRDA receive process half complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_IRDA_RxHalfCpltCallback(hirda); + HAL_IRDA_RxHalfCpltCallback(hirda); } /** - * @brief DMA IRDA communication error callback + * @brief DMA IRDA communication error callback * @param hdma: DMA handle * @retval None */ -static void IRDA_DMAError(DMA_HandleTypeDef *hdma) +static void IRDA_DMAError(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; - hirda->State= HAL_IRDA_STATE_READY; - hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; - HAL_IRDA_ErrorCallback(hirda); + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; + + /* Stop IRDA DMA Tx request if ongoing */ + if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) ) + { + IRDA_EndTxTransfer(hirda); + } + + /* Stop IRDA DMA Rx request if ongoing */ + if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ) + { + IRDA_EndRxTransfer(hirda); + } + + hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; + + HAL_IRDA_ErrorCallback(hirda); } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h index 976387cb18e..deb8253efba 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_irda.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -89,18 +89,63 @@ typedef struct }IRDA_InitTypeDef; /** - * @brief HAL State structures definition + * @brief HAL IRDA State structures definition + * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. + * - gState contains IRDA state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL IRDA Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_IRDA_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ + HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing + Value is allowed for gState only */ + HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_IRDA_StateTypeDef; /** @@ -108,11 +153,11 @@ typedef enum */ typedef enum { - IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */ }IRDA_ClockSourceTypeDef; /** @@ -144,7 +189,12 @@ typedef struct HAL_LockTypeDef Lock; /* Locking object */ - __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */ + __IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ __IO uint32_t ErrorCode; /* IRDA Error code */ @@ -167,12 +217,12 @@ typedef struct * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ /** * @} */ @@ -180,7 +230,7 @@ typedef struct /** @defgroup IRDA_Parity IRDA Parity * @{ */ -#define IRDA_PARITY_NONE ((uint32_t)0x0000) +#define IRDA_PARITY_NONE ((uint32_t)0x0000U) #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** @@ -201,7 +251,7 @@ typedef struct /** @defgroup IRDA_Low_Power IRDA Low Power * @{ */ -#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000) +#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U) #define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /** * @} @@ -210,7 +260,7 @@ typedef struct /** @defgroup IRDA_State IRDA State * @{ */ -#define IRDA_STATE_DISABLE ((uint32_t)0x0000) +#define IRDA_STATE_DISABLE ((uint32_t)0x0000U) #define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /** * @} @@ -219,7 +269,7 @@ typedef struct /** @defgroup IRDA_Mode IRDA Mode * @{ */ -#define IRDA_MODE_DISABLE ((uint32_t)0x0000) +#define IRDA_MODE_DISABLE ((uint32_t)0x0000U) #define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /** * @} @@ -228,7 +278,7 @@ typedef struct /** @defgroup IRDA_One_Bit IRDA One Bit * @{ */ -#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) #define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /** * @} @@ -237,7 +287,7 @@ typedef struct /** @defgroup IRDA_DMA_Tx IRDA DMA Tx * @{ */ -#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) +#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U) #define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /** * @} @@ -246,7 +296,7 @@ typedef struct /** @defgroup IRDA_DMA_Rx IRDA DMA Rx * @{ */ -#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000) +#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U) #define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /** * @} @@ -257,18 +307,18 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define IRDA_FLAG_REACK ((uint32_t)0x00400000) -#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) -#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) -#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) -#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) -#define IRDA_FLAG_TXE ((uint32_t)0x00000080) -#define IRDA_FLAG_TC ((uint32_t)0x00000040) -#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) -#define IRDA_FLAG_ORE ((uint32_t)0x00000008) -#define IRDA_FLAG_NE ((uint32_t)0x00000004) -#define IRDA_FLAG_FE ((uint32_t)0x00000002) -#define IRDA_FLAG_PE ((uint32_t)0x00000001) +#define IRDA_FLAG_REACK ((uint32_t)0x00400000U) +#define IRDA_FLAG_TEACK ((uint32_t)0x00200000U) +#define IRDA_FLAG_BUSY ((uint32_t)0x00010000U) +#define IRDA_FLAG_ABRF ((uint32_t)0x00008000U) +#define IRDA_FLAG_ABRE ((uint32_t)0x00004000U) +#define IRDA_FLAG_TXE ((uint32_t)0x00000080U) +#define IRDA_FLAG_TC ((uint32_t)0x00000040U) +#define IRDA_FLAG_RXNE ((uint32_t)0x00000020U) +#define IRDA_FLAG_ORE ((uint32_t)0x00000008U) +#define IRDA_FLAG_NE ((uint32_t)0x00000004U) +#define IRDA_FLAG_FE ((uint32_t)0x00000002U) +#define IRDA_FLAG_PE ((uint32_t)0x00000001U) /** * @} */ @@ -283,11 +333,11 @@ typedef struct * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define IRDA_IT_PE ((uint16_t)0x0028) -#define IRDA_IT_TXE ((uint16_t)0x0727) -#define IRDA_IT_TC ((uint16_t)0x0626) -#define IRDA_IT_RXNE ((uint16_t)0x0525) -#define IRDA_IT_IDLE ((uint16_t)0x0424) +#define IRDA_IT_PE ((uint16_t)0x0028U) +#define IRDA_IT_TXE ((uint16_t)0x0727U) +#define IRDA_IT_TC ((uint16_t)0x0626U) +#define IRDA_IT_RXNE ((uint16_t)0x0525U) +#define IRDA_IT_IDLE ((uint16_t)0x0424U) @@ -298,14 +348,14 @@ typedef struct * - 10: CR2 register * - 11: CR3 register */ -#define IRDA_IT_ERR ((uint16_t)0x0060) +#define IRDA_IT_ERR ((uint16_t)0x0060U) /** Elements values convention: 0000ZZZZ00000000b * - ZZZZ : Flag position in the ISR register(4bits) */ -#define IRDA_IT_ORE ((uint16_t)0x0300) -#define IRDA_IT_NE ((uint16_t)0x0200) -#define IRDA_IT_FE ((uint16_t)0x0100) +#define IRDA_IT_ORE ((uint16_t)0x0300U) +#define IRDA_IT_NE ((uint16_t)0x0200U) +#define IRDA_IT_FE ((uint16_t)0x0100U) /** * @} */ @@ -559,7 +609,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); /** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask * @{ */ -#define IRDA_IT_MASK ((uint16_t)0x001F) +#define IRDA_IT_MASK ((uint16_t)0x001FU) /** * @} */ @@ -588,7 +638,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); ((__PARITY__) == IRDA_PARITY_EVEN) || \ ((__PARITY__) == IRDA_PARITY_ODD)) -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U)) #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ ((__MODE__) == IRDA_POWERMODE_NORMAL)) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h index 90cf20d6267..bfbe113de01 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ * @{ */ #define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) +#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U) #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c index 2db141a9cce..01e2db86d4b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c @@ -2,90 +2,86 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief IWDG HAL module driver. - * * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: - * + Initialization and de-initialization functions + * + Initialization and Start functions * + IO operation functions - * + Peripheral State functions - * + * @verbatim ============================================================================== ##### IWDG Generic features ##### ============================================================================== - [..] + [..] (+) The IWDG can be started by either software or hardware (configurable - through option byte). + through option byte). + + (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even + if the main clock fails. - (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and - thus stays active even if the main clock fails. - Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. + (+) Once the IWDG is started, the LSI is forced ON and both can not be + disabled. The counter starts counting down from the reset value (0xFFF). + When it reaches the end of count value (0x000) a reset signal is + generated (IWDG reset). - (+) The IWDG counter should be refreshed at regular intervals, otherwise the - watchdog generates an MCU reset when the counter reaches 0. + (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + the IWDG_RLR value is reloaded in the counter and the watchdog reset is + prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - IWDGRST flag in RCC_CSR register can be used to inform when an IWDG - reset occurs. + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + reset occurs. + + (+) Debug mode : When the microcontroller enters debug mode (core halted), + the IWDG counter either continues to work normally or stops, depending + on DBG_IWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx + The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx devices provide the capability to measure the LSI frequency (LSI clock connected internally to TIM16 CH1 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy. - ##### How to use this driver ##### ============================================================================== - [..] - If Window option is disabled - - (+) Use IWDG using HAL_IWDG_Init() function to : - (++) Enable write access to IWDG_PR, IWDG_RLR. - (++) Configure the IWDG prescaler, counter reload value. - This reload value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - (+) Use IWDG using HAL_IWDG_Start() function to : - (++) Reload IWDG counter with value defined in the IWDG_RLR register. - (++) Start the IWDG, when the IWDG is used in software mode (no need - to enable the LSI, it will be enabled by hardware). - (+) Then the application program must refresh the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. - [..] - if Window option is enabled: - - (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter - (+) Use IWDG using HAL_IWDG_Init() function to : - (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - (++) Configure the IWDG prescaler, reload value and window value. - (+) Then the application program must refresh the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. + [..] + (#) Use IWDG using HAL_IWDG_Init() function to : + (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI + clock is forced ON and IWDG counter starts downcounting. + (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR & + IWDG_WINR. + (+) Configure the IWDG prescaler and counter reload value. This reload + value will be loaded in the IWDG counter each time the watchdog is + reloaded, then the IWDG will start counting down from this value. + (+) wait for status flags to be reset" + (+) Depending on window parameter: + (++) If Window Init parameter is same as Window register value, + nothing more is done but reload counter value in order to exit + function withy exact time base. + (++) Else modify Window register. This will automatically reload + watchdog counter. + + (#) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. *** IWDG HAL driver macros list *** ==================================== [..] - Below the list of most used macros in IWDG HAL driver. - + Below the list of most used macros in IWDG HAL driver: (+) __HAL_IWDG_START: Enable the IWDG peripheral - (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register - (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status - (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers - (+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers - + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in + the reload register + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -119,61 +115,63 @@ * @{ */ -/** @defgroup IWDG IWDG HAL module driver +#ifdef HAL_IWDG_MODULE_ENABLED +/** @addtogroup IWDG * @brief IWDG HAL module driver. * @{ */ -#ifdef HAL_IWDG_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ - -#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000 - +/* Status register need 5 RC LSI divided by prescaler clock to be updated. With + higher prescaler (256), and according to LSI variation, we need to wait at + least 6 cycles so 48 ms. */ +#define HAL_IWDG_DEFAULT_TIMEOUT 48u /** * @} */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Functions IWDG Exported Functions +/** @addtogroup IWDG_Exported_Functions * @{ */ -/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @addtogroup IWDG_Exported_Functions_Group1 + * @brief Initialization and Start functions. * @verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Start functions ##### =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters - in the IWDG_InitTypeDef and create the associated handle - (+) Manage Window option - (+) Initialize the IWDG MSP - (+) DeInitialize IWDG MSP + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters in the + IWDG_InitTypeDef of associated handle. + (+) Manage Window option. + (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + is reloaded in order to exit function with correct time base. @endverbatim * @{ */ /** - * @brief Initializes the IWDG according to the specified - * parameters in the IWDG_InitTypeDef and creates the associated handle. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * @brief Initialize the IWDG according to the specified parameters in the + * IWDG_InitTypeDef and start watchdog. Before exiting function, + * watchdog is refreshed in order to have correct time base. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the IWDG handle allocation */ if(hiwdg == NULL) @@ -182,230 +180,88 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) } /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); - /* Check pending flag, if previous update not done, return error */ - if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET)) - { - return HAL_ERROR; - } - - if(hiwdg->State == HAL_IWDG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hiwdg->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_IWDG_MspInit(hiwdg); - } - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; + /* Enable IWDG. LSI is turned on automaticaly */ + __HAL_IWDG_START(hiwdg); - /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */ - /* by writing 0x00005555 in KR */ + /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing + 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); - /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ - MODIFY_REG(hiwdg->Instance->PR, (uint32_t)IWDG_PR_PR, hiwdg->Init.Prescaler); - MODIFY_REG(hiwdg->Instance->RLR, (uint32_t)IWDG_RLR_RL, hiwdg->Init.Reload); + /* Write to IWDG registers the Prescaler & Reload values to work with */ + hiwdg->Instance->PR = hiwdg->Init.Prescaler; + hiwdg->Instance->RLR = hiwdg->Init.Reload; - /* check if window option is enabled */ - if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE)) - { - tickstart = HAL_GetTick(); + /* Check pending flag, if previous update not done, return timeout */ + tickstart = HAL_GetTick(); - /* Wait for register to be updated */ - while((uint32_t)(hiwdg->Instance->SR) != RESET) + /* Wait for register to be updated */ + while(hiwdg->Instance->SR != RESET) + { + if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) { - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } - - /* Write to IWDG WINR the IWDG_Window value to compare with */ - MODIFY_REG(hiwdg->Instance->WINR, (uint32_t)IWDG_WINR_WIN, hiwdg->Init.Window); } - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; + /* If window parameter is different than current value, modify window + register */ + if(hiwdg->Instance->WINR != hiwdg->Init.Window) + { + /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, + even if window feature is disabled, Watchdog will be reloaded by writing + windows register */ + hiwdg->Instance->WINR = hiwdg->Init.Window; + } + else + { + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + } /* Return function status */ return HAL_OK; } -/** - * @brief Initializes the IWDG MSP. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval None - */ -__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hiwdg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IWDG_MspInit could be implemented in the user file - */ -} - /** * @} */ -/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @brief IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This section provides functions allowing to: - (+) Start the IWDG. + [..] This section provides functions allowing to: (+) Refresh the IWDG. @endverbatim * @{ */ -/** - * @brief Starts the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - /* Reload IWDG counter with value defined in the RLR register */ - if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE) - { - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - } - - /* Start the IWDG peripheral */ - __HAL_IWDG_START(hiwdg); - - tickstart = HAL_GetTick(); - - /* Wait until PVU, RVU, WVU flag are RESET */ - while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) ) - { - - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hiwdg); - - return HAL_TIMEOUT; - } - } - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - - /* Return function status */ - return HAL_OK; -} /** - * @brief Refreshes the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * @brief Refresh the IWDG. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - tickstart = HAL_GetTick(); - - /* Wait until RVU flag is RESET */ - while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - { - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hiwdg); - - return HAL_TIMEOUT; - } - } - /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - /* Return function status */ return HAL_OK; } -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the IWDG state. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL state - */ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) -{ - return hiwdg->State; -} - /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h index 4c3f6b836fa..4a47853b3b3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_IWDG_H @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup IWDG +/** @defgroup IWDG IWDG * @{ */ @@ -59,19 +59,6 @@ * @{ */ -/** - * @brief IWDG HAL State Structure definition - */ -typedef enum -{ - HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ - HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ - HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ - HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ - HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ - -}HAL_IWDG_StateTypeDef; - /** * @brief IWDG Init structure definition */ @@ -97,10 +84,6 @@ typedef struct IWDG_InitTypeDef Init; /*!< IWDG required parameters */ - HAL_LockTypeDef Lock; /*!< IWDG Locking object */ - - __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ - }IWDG_HandleTypeDef; /** @@ -115,21 +98,21 @@ typedef struct /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ -#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ /** * @} */ -/** @defgroup IWDG_Window IWDG Window +/** @defgroup IWDG_Window_option IWDG Window option * @{ */ -#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF) +#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN /** * @} */ @@ -143,117 +126,83 @@ typedef struct * @{ */ -/** @brief Reset IWDG handle state - * @param __HANDLE__: IWDG handle. - * @retval None - */ -#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) - /** - * @brief Enables the IWDG peripheral. + * @brief Enable the IWDG peripheral. * @param __HANDLE__: IWDG handle * @retval None */ #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) /** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param __HANDLE__: IWDG handle + * @brief Reload IWDG counter with value defined in the reload register + * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled). + * @param __HANDLE__: IWDG handle * @retval None */ #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) -/** - * @brief Gets the selected IWDG's flag status. - * @param __HANDLE__: IWDG handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag - * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag - * @arg IWDG_FLAG_WVU: Watchdog counter window value flag - * @retval The new state of __FLAG__ (TRUE or FALSE) . - */ -#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup IWDG_Exported_Functions +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions * @{ */ -/** @addtogroup IWDG_Exported_Functions_Group1 +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions * @{ */ -/* Initialization/de-initialization functions ********************************/ +/* Initialization/Start functions ********************************************/ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); -void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); /** * @} */ -/** @addtogroup IWDG_Exported_Functions_Group2 +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ -/** @addtogroup IWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); -/** - * @} - */ - /** * @} */ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup IWDG_Private_Defines +/** @defgroup IWDG_Private_Constants IWDG Private Constants * @{ */ -/** - * @brief IWDG Key Register BitMask - */ -#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */ -#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */ -#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */ -#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */ /** - * @brief IWDG Flag definition + * @brief IWDG Key Register BitMask */ -#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */ -#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */ -#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */ +#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ /** * @} */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup IWDG_Private_Macro IWDG Private Macros +/** @defgroup IWDG_Private_Macros IWDG Private Macros * @{ */ + /** - * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. * @param __HANDLE__: IWDG handle * @retval None */ #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** - * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. * @param __HANDLE__: IWDG handle * @retval None */ @@ -277,14 +226,14 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); * @param __RELOAD__: IWDG reload value * @retval None */ -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) /** * @brief Check IWDG window value. * @param __WINDOW__: IWDG window value * @retval None */ -#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF) +#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.c new file mode 100644 index 00000000000..e6d986e3937 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.c @@ -0,0 +1,3403 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_jpeg.c + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief JPEG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the JPEG encoder/decoder peripheral: + * + Initialization and de-initialization functions + * + JPEG processing functions encoding and decoding + * + JPEG decoding Getting Info and encoding configuration setting + * + JPEG enable/disable header parsing functions (for decoding) + * + JPEG Input/Output Buffer configuration. + * + JPEG callback functions + * + JPEG Abort/Pause/Resume functions + * + JPEG custom quantization tables setting functions + * + IRQ handler management + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required. + Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral. + + (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set + the encoding parameters (mandatory before calling the encoding function). + the application can change the encoding parameter "ImageQuality" from + 1 to 100 to obtain a more or less quality (visual quality vs the original row image), + and inversely more or less jpg file size. + + (#) Note that for decoding operation the JPEG peripheral output data are organized in + YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification + ISO/IEC 10918-1 standard. + It is up to the application to transform these YCbCr blocks to RGB data that can be display. + + Respectively, for Encoding operation the JPEG peripheral input should be organized + in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr + MCU blocks transformation before feeding the JPEG peripheral with data. + + (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively + a JPEG encoding/decoding operation in polling method (blocking). + + (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively + a JPEG encoding/decoding operation with Interrupt method (not blocking). + + (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively + a JPEG encoding/decoding operation with DMA method (not blocking). + + (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation + is a JPEG decoding to provide the application with JPEG image parameters. + This callback is asserted when the JPEG peripheral successfully parse the + JPEG header. + + (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding + operations to inform the application that the input buffer has been + consumed by the peripheral and to ask for a new data chunk if the operation + (encoding/decoding) has not been complete yet. + + This CallBack should be implemented in the application side. It should + call the function HAL_JPEG_ConfigInputBuffer if new input data are available, + or call HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_INPUT" + to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the + application to provide a new input data chunk. + Once the application succeed getting new data and if the input has been paused, + the application can call the function HAL_JPEG_ConfigInputBuffer to set the new + input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume. + If the application has ended feeding the HAL JPEG with input data (no more input data), the application + Should call the function “HAL_JPEG_ConfigInputBuffer” (within the callback HAL_JPEG_GetDataCallback) + with the parameter “InDataLength” set to zero. + + The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows + to the application to provide the input data (for encoding or decoding) by chunks. + If the new input data chunk is not available (because data should be read from an input file + for example) the application can pause the JPEG input (using function HAL_JPEG_Pause) + Once the new input data chunk is available ( read from a file for example), the application + can call the function "HAL_JPEG_ConfigInputBuffer" to provide the HAL with the new chunk + then resume the JPEG HAL input by calling function "HAL_JPEG_Resume". + + The application can call functions “HAL_JPEG_ConfigInputBuffer “ then "HAL_JPEG_Resume". + any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available. + However, to keep data coherency, the function “HAL_JPEG_Pause” must be imperatively called + (if necessary) within the callback “HAL_JPEG_GetDataCallback”, i.e when the HAL JPEG has ended + Transferring the previous chunk buffer to the JPEG peripheral. + + (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver + has filled the given output buffer with the given size. + + This CallBack should be implemented in the application side. It should + call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver + with the new output buffer location and size to be used to store next data chunk. + if the application is not ready to provide the output chunk location then it can + call the function "HAL_JPEG_Pause" with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT" + to inform the JPEG HAL driver that it shall pause output data. Once the application + is ready to receive the new data chunk (output buffer location free or available) it should call + the function "HAL_JPEG_ConfigOutputBuffer" to provide the HAL JPEG driver + with the new output chunk buffer location and size, then call "HAL_JPEG_Resume" + to inform the HAL that it shall resume outputting data in the given output buffer. + + The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows + the application to receive data from the JPEG peripheral by chunks. when a chunk + is received, the application can pause the HAL JPEG output data to be able to process + these received data (YCbCr to RGB conversion in case of decoding or data storage in case + of encoding). + + The application can call functions “HAL_JPEG_ ConfigOutputBuffer“ then "HAL_JPEG_Resume". + any time (outside the HAL_JPEG_ DataReadyCallback) Once the output data buffer is free to use. + However, to keep data coherency, the function “HAL_JPEG_Pause” must be imperatively called + (if necessary) within the callback “HAL_JPEG_ DataReadyCallback”, i.e when the HAL JPEG has ended + Transferring the previous chunk buffer from the JPEG peripheral to the application. + + (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has + ended the current JPEG encoding operation, and all output data has been transmitted + to the application. + + (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has + ended the current JPEG decoding operation. and all output data has been transmitted + to the application. + + (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during + the current operation. the application can call the function "HAL_JPEG_GetError" + to retrieve the error codes. + + (#) By default the HAL JPEG driver uses the default quantization tables + as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding. + User can change these default tables if necessary using the function "HAL_JPEG_SetUserQuantTables" + Note that for decoding the quantization tables are automatically extracted from + the JPEG header. + + (#) To control JPEG state you can use the following function: HAL_JPEG_GetState() + + *** JPEG HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in JPEG HAL driver. + + (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state. + (+) __HAL_JPEG_ENABLE : Enable the JPEG peripheral. + (+) __HAL_JPEG_DISABLE : Disable the JPEG peripheral. + (+) __HAL_JPEG_GET_FLAG : Check the specified JPEG status flag. + (+) __HAL_JPEG_CLEAR_FLAG : Clear the specified JPEG status flag. + (+) __HAL_JPEG_ENABLE_IT : Enable the specified JPEG Interrupt. + (+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt. + (+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled). + + + @endverbatim + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup JPEG JPEG + * @brief JPEG HAL module driver. + * @{ + */ + +#ifdef HAL_JPEG_MODULE_ENABLED + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +/* Private define ------------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Constants + * @{ + */ +#define JPEG_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ +#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/ +#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/ + +#define JPEG_FIFO_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO size in words*/ + +#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/ + +#define JPEG_DMA_MASK ((uint32_t)0x00001800U) /* JPEG DMA request Mask*/ +#define JPEG_DMA_IDMA ((uint32_t)JPEG_CR_IDMAEN) /* DMA request for the input FIFO */ +#define JPEG_DMA_ODMA ((uint32_t)JPEG_CR_ODMAEN) /* DMA request for the output FIFO */ + +#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/ +#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/ +#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003U) /* JPEG context : operation Mask */ + +#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004U) /* JPEG context : Transfer use Polling */ +#define JPEG_CONTEXT_IT ((uint32_t)0x00000008U) /* JPEG context : Transfer use Interrupt */ +#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000CU) /* JPEG context : Transfer use DMA */ +#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000CU) /* JPEG context : Transfer Mask */ + + +#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100U) /* JPEG context : encoding config done */ + +#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000U) /* JPEG context : Pause Input */ +#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000U) /* JPEG context : Pause Output */ + +#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000U) /* JPEG context : Use custom quantization tables */ + +#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000U) /* JPEG context : ending with DMA in progress */ + +#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000U) /* Process is on going */ +#define JPEG_PROCESS_DONE ((uint32_t)0x00000001U) /* Process is done (ends) */ +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Types + * @{ + */ + +/* + JPEG Huffman Table Structure definition : + This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification + */ +typedef struct +{ + /* These two fields directly represent the contents of a JPEG DHT marker */ + uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ + + uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ + + +}JPEG_ACHuffTableTypeDef; + +typedef struct +{ + /* These two fields directly represent the contents of a JPEG DHT marker */ + uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ + + uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ + + +}JPEG_DCHuffTableTypeDef; + +typedef struct +{ + uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE]; /*!< Code length */ + + uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ + +}JPEG_AC_HuffCodeTableTypeDef; + +typedef struct +{ + uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE]; /*!< Code length */ + + uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ + +}JPEG_DC_HuffCodeTableTypeDef; +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Macros + * @{ + */ +#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK)) +/*note : To disable a DMA request we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits + located in the same DMA request enable register (CR register). */ +#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0) +/** + * @} + */ + + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Variables + * @{ + */ + +static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable = +{ + { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/ + + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ + +}; + +static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable = +{ + { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, /*Bits*/ + + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ +}; + +static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable = +{ + { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/ + + { 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */ + 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, + 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, + 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, + 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, + 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, + 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, + 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, + 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, + 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, + 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, + 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, + 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, + 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, + 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, + 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, + 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, + 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, + 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa } +}; + +static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable = +{ + { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/ + + { 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */ + 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, + 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, + 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0, + 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34, + 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26, + 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38, + 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, + 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, + 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, + 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, + 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, + 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, + 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, + 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, + 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, + 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, + 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa } +}; + + +/* + These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. +*/ +static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] = +{ + 16, 11, 10, 16, 24, 40, 51, 61, + 12, 12, 14, 19, 26, 58, 60, 55, + 14, 13, 16, 24, 40, 57, 69, 56, + 14, 17, 22, 29, 51, 87, 80, 62, + 18, 22, 37, 56, 68, 109, 103, 77, + 24, 35, 55, 64, 81, 104, 113, 92, + 49, 64, 78, 87, 103, 121, 120, 101, + 72, 92, 95, 98, 112, 100, 103, 99 +}; +static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] = +{ + 17, 18, 24, 47, 99, 99, 99, 99, + 18, 21, 26, 66, 99, 99, 99, 99, + 24, 26, 56, 99, 99, 99, 99, 99, + 47, 66, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99 +}; + +static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] = +{ + 0, 1, 8, 16, 9, 2, 3, 10, + 17, 24, 32, 25, 18, 11, 4, 5, + 12, 19, 26, 33, 40, 48, 41, 34, + 27, 20, 13, 6, 7, 14, 21, 28, + 35, 42, 49, 56, 57, 50, 43, 36, + 29, 22, 15, 23, 30, 37, 44, 51, + 58, 59, 52, 45, 38, 31, 39, 46, + 53, 60, 61, 54, 47, 55, 62, 63 +}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup JPEG_Private_Functions_Prototypes + * @{ + */ + +static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK); +static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable); +static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable); +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress); +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress); +static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1); +static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1); +static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress); +static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg); +static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg); +static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg); + +static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg); +static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg); +static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords); +static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords); +static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg); + +static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg); +static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg); +static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma); +static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma); +static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma); +static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ; +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions JPEG Exported Functions + * @{ + */ + +/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the JPEG peripheral and creates the associated handle + (+) DeInitialize the JPEG peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the JPEG according to the specified + * parameters in the JPEG_InitTypeDef and creates the associated handle. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg) +{ + /*Note : these intermediate variables are used to avoid MISRA warning + regarding rule 11.5 */ + uint32_t acLum_huffmanTableAddr = (uint32_t)(&JPEG_ACLUM_HuffTable); + uint32_t dcLum_huffmanTableAddr = (uint32_t)(&JPEG_DCLUM_HuffTable); + uint32_t acChrom_huffmanTableAddr = (uint32_t)(&JPEG_ACCHROM_HuffTable); + uint32_t dcChrom_huffmanTableAddr = (uint32_t)(&JPEG_DCCHROM_HuffTable); + + /* Check the JPEG handle allocation */ + if(hjpeg == NULL) + { + return HAL_ERROR; + } + + if(hjpeg->State == HAL_JPEG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hjpeg->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_JPEG_MspInit(hjpeg); + } + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Start the JPEG Core*/ + __HAL_JPEG_ENABLE(hjpeg); + + /* Stop the JPEG encoding/decoding process*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); + + hjpeg->QuantTable0 = (uint8_t *)JPEG_LUM_QuantTable; + hjpeg->QuantTable1 = (uint8_t *)JPEG_CHROM_QuantTable; + hjpeg->QuantTable2 = NULL; + hjpeg->QuantTable3 = NULL; + + /* init the default Huffman tables*/ + if(JPEG_Set_HuffEnc_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)acLum_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcLum_huffmanTableAddr, (JPEG_ACHuffTableTypeDef *)acChrom_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcChrom_huffmanTableAddr) != HAL_OK) + { + hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE; + + return HAL_ERROR; + } + + /* Enable header processing*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Reset the JPEG ErrorCode */ + hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; + + /*Clear the context filelds*/ + hjpeg->Context = 0; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the JPEG peripheral. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Check the JPEG handle allocation */ + if(hjpeg == NULL) + { + return HAL_ERROR; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_JPEG_MspDeInit(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Reset the JPEG ErrorCode */ + hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_RESET; + + /*Clear the context fields*/ + hjpeg->Context = 0; + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the JPEG MSP. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes JPEG MSP. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions + * @brief JPEG Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration + (+) HAL_JPEG_GetInfo() : Extract the image configuration from the JPEG header during the decoding + (+) HAL_JPEG_EnableHeaderParsing() : Enable JPEG Header parsing for decoding + (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding + (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding. + +@endverbatim + * @{ + */ + +/** + * @brief Set the JPEG encoding configuration. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pConf: pointer to a JPEG_ConfTypeDef structure that contains + * the encoding configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf) +{ + uint32_t error = HAL_OK; + uint32_t numberMCU, hfactor, vfactor,hMCU, vMCU; + + /* Check the JPEG handle allocation */ + if( (hjpeg == NULL) || (pConf == NULL) ) + { + return HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace)); + assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling)); + assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality)); + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + hjpeg->State = HAL_JPEG_STATE_BUSY; + + hjpeg->Conf.ColorSpace = pConf->ColorSpace; + hjpeg->Conf.ChromaSubsampling = pConf->ChromaSubsampling; + hjpeg->Conf.ImageHeight = pConf->ImageHeight; + hjpeg->Conf.ImageWidth = pConf->ImageWidth; + hjpeg->Conf.ImageQuality = pConf->ImageQuality; + + /* Reset the Color Space : by default only one quantization table is used*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE; + + /* Set Number of color components*/ + if(hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE) + { + /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/ + hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING; + + JPEG_SetColorGrayScale(hjpeg); + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0)); + } + else if(hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE) + { + /* + Set the Color Space for YCbCr : 2 quantization tables are used + one for Luminance(Y) and one for both Chrominances (Cb & Cr) + */ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0; + + JPEG_SetColorYCBCR(hjpeg); + + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0)); + /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/ + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1)); + + if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/ + { + /* use 3 quantization tables , one for each component*/ + hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE); + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1; + + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2)); + + /*Use Quantization 1 table for component 1*/ + hjpeg->Instance->CONFR5 &= (~JPEG_CONFR6_QT); + hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; + + /*Use Quantization 2 table for component 2*/ + hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT); + hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; + } + } + else if(hjpeg->Conf.ColorSpace == JPEG_CMYK_COLORSPACE) + { + JPEG_SetColorCMYK(hjpeg); + + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0)); + /*By default quantization table 0 for All components*/ + + if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/ + { + /* use 4 quantization tables , one for each component*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE; + + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1)); + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2)); + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (uint32_t *)(hjpeg->Instance->QMEM3)); + + /*Use Quantization 1 table for component 1*/ + hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; + + /*Use Quantization 2 table for component 2*/ + hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; + + /*Use Quantization 3 table for component 3*/ + hjpeg->Instance->CONFR7 |= JPEG_CONFR7_QT; + } + } + + if(error != HAL_OK) + { + hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_ERROR; + } + /* Set the image size*/ + hjpeg->Instance->CONFR1 |= ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16); /* set the number of lines*/ + hjpeg->Instance->CONFR3 |= ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16); /* set the number of pixels per line*/ + + if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/ + { + hfactor = 16; + vfactor = 16; + } + else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/ + { + hfactor = 16; + vfactor = 8; + } + else /* Default is 8x8 MCU, 4:4:4*/ + { + hfactor = 8; + vfactor = 8; + } + + hMCU = (hjpeg->Conf.ImageWidth / hfactor); + if((hjpeg->Conf.ImageWidth % hfactor) != 0) + { + hMCU++; /*+1 for horizontal incomplete MCU */ + } + + vMCU = (hjpeg->Conf.ImageHeight / vfactor); + if((hjpeg->Conf.ImageHeight % vfactor) != 0) + { + vMCU++; /*+1 for vertical incomplete MCU */ + } + + numberMCU = (hMCU * vMCU) - 1; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/ + /* Set the number of MCU*/ + hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU); + + hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Return function status */ + return HAL_BUSY; + } + } +} + +/** + * @brief Extract the image configuration from the JPEG header during the decoding + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains + * The JPEG decoded header informations + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) +{ + uint32_t yblockNb, cBblockNb, cRblockNb; + + /* Check the JPEG handle allocation */ + if((hjpeg == NULL) || (pInfo == NULL)) + { + return HAL_ERROR; + } + + /*Read the conf parameters */ + if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1) + { + pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE; + } + else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0) + { + pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE; + } + else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF) + { + pInfo->ColorSpace = JPEG_CMYK_COLORSPACE; + } + + pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000U) >> 16; + pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000U) >> 16; + + if((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE)) + { + yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4; + cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4; + cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4; + + if((yblockNb == 1) && (cBblockNb == 0) && (cRblockNb == 0)) + { + pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/ + } + else if((yblockNb == 0) && (cBblockNb == 0) && (cRblockNb == 0)) + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + else if((yblockNb == 3) && (cBblockNb == 0) && (cRblockNb == 0)) + { + pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING; + } + else /*Default is 4:4:4*/ + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + } + else + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + + pInfo->ImageQuality = JPEG_GetQuality(hjpeg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable JPEG Header parsing for decoding + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the JPEG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg) +{ + /* Process locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Enable header processing*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; + + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_OK; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @brief Disable JPEG Header parsing for decoding + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the JPEG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg) +{ + /* Process locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Disable header processing*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR; + + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_OK; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @brief Modify the default Quantization tables used for JPEG encoding. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param QTable0 : pointer to uint8_t , define the user quantification table for color component 1. + * If NULL assume no need to update the table and no error return + * @param QTable1 : pointer to uint8_t , define the user quantification table for color component 2. + * If NULL assume no need to update the table and no error return. + * @param QTable2 : pointer to uint8_t , define the user quantification table for color component 3, + * If NULL assume no need to update the table and no error return. + * @param QTable3 : pointer to uint8_t , define the user quantification table for color component 4. + * If NULL assume no need to update the table and no error return. + * + * @retval HAL status + */ + + +HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3) +{ + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES; + + hjpeg->QuantTable0 = QTable0; + hjpeg->QuantTable1 = QTable1; + hjpeg->QuantTable2 = QTable2; + hjpeg->QuantTable3 = QTable3; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions + * @brief processing functions. + * +@verbatim + ============================================================================== + ##### JPEG processing functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_JPEG_Encode() : JPEG encoding with polling process + (+) HAL_JPEG_Decode() : JPEG decoding with polling process + (+) HAL_JPEG_Encode_IT() : JPEG encoding with interrupt process + (+) HAL_JPEG_Decode_IT() : JPEG decoding with interrupt process + (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process + (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process + (+) HAL_JPEG_Pause() : Pause the Input/Output processing + (+) HAL_JPEG_Resume() : Resume the JPEG Input/Output processing + (+) HAL_JPEG_ConfigInputBuffer() : Config Encoding/Decoding Input Buffer + (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer + (+) HAL_JPEG_Abort() : Aborts the JPEG Encoding/Decoding + +@endverbatim + * @{ + */ + +/** + * @brief Starts JPEG encoding with polling processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU: Pointer to the Input buffer + * @param InDataLength: size in bytes Input buffer + * @param pDataOut: Pointer to the jpeg output data buffer + * @param OutDataLength: size in bytes of the Output buffer + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param((InDataLength >= 4)); + assert_param((OutDataLength >= 4)); + + /* Check In/out buffer allocation and size */ + if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \ + (InDataLength == 0) || (OutDataLength == 0)) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING ) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with Polling*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING); + + /* Get tick */ + tickstart = HAL_GetTick(); + /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ + InDataLength = InDataLength - (InDataLength % 4); + OutDataLength = OutDataLength - (OutDataLength % 4); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /*JPEG data processing : In/Out FIFO transfer*/ + while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State= HAL_JPEG_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State= HAL_JPEG_STATE_READY; + + }else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with polling processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn: Pointer to the input data buffer + * @param InDataLength: size in bytes Input buffer + * @param pDataOutMCU: Pointer to the Output data buffer + * @param OutDataLength: size in bytes of the Output buffer + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param((InDataLength >= 4)); + assert_param((OutDataLength >= 4)); + + /* Check In/out buffer allocation and size */ + if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \ + (InDataLength == 0) || (OutDataLength == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + /* Get tick */ + tickstart = HAL_GetTick(); + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with Polling*/ + /*Set the Context to Encode with Polling*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING); + + /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ + InDataLength = InDataLength - (InDataLength % 4); + OutDataLength = OutDataLength - (OutDataLength % 4); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /*JPEG data processing : In/Out FIFO transfer*/ + while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State= HAL_JPEG_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State= HAL_JPEG_STATE_READY; + + }else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG encoding with interrupt processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU: Pointer to the Input buffer + * @param InDataLength: size in bytes Input buffer + * @param pDataOut: Pointer to the jpeg output data buffer + * @param OutDataLength: size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4)); + assert_param((OutDataLength >= 4)); + + /* Check In/out buffer allocation and size */ + if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \ + (InDataLength == 0) || (OutDataLength == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + else + { + if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING ) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with IT*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT); + + /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ + InDataLength = InDataLength - (InDataLength % 4); + OutDataLength = OutDataLength - (OutDataLength % 4); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with interrupt processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn: Pointer to the input data buffer + * @param InDataLength: size in bytes Input buffer + * @param pDataOutMCU: Pointer to the Output data buffer + * @param OutDataLength: size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4)); + assert_param((OutDataLength >= 4)); + + /* Check In/out buffer allocation and size */ + if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \ + (InDataLength == 0) || (OutDataLength == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with IT*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT); + + /*In/Out Data length must be multiple of 4 Bytes (1 word)*/ + InDataLength = InDataLength - (InDataLength % 4); + OutDataLength = OutDataLength - (OutDataLength % 4); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG encoding with DMA processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU: Pointer to the Input buffer + * @param InDataLength: size in bytes Input buffer + * @param pDataOut: Pointer to the jpeg output data buffer + * @param OutDataLength: size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4)); + assert_param((OutDataLength >= 4)); + + /* Check In/out buffer allocation and size */ + if((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL) || \ + (InDataLength == 0) || (OutDataLength == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + else + { + if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING ) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with DMA*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /* JPEG encoding process using DMA */ + JPEG_DMA_StartProcess(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with DMA processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn: Pointer to the input data buffer + * @param InDataLength: size in bytes Input buffer + * @param pDataOutMCU: Pointer to the Output data buffer + * @param OutDataLength: size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4)); + assert_param((OutDataLength >= 4)); + + /* Check In/out buffer allocation and size */ + if((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL) || \ + (InDataLength == 0) || (OutDataLength == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if(hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with DMA*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /* JPEG decoding process using DMA */ + JPEG_DMA_StartProcess(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Pause the JPEG Input/Output processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param XferSelection: This parameter can be one of the following values : + * JPEG_PAUSE_RESUME_INPUT : Pause Input processing + * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing + * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) +{ + uint32_t mask = 0; + + assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); + + if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; + mask |= JPEG_DMA_IDMA; + } + if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; + mask |= JPEG_DMA_ODMA; + } + JPEG_DISABLE_DMA(hjpeg,mask); + + } + else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + + if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; + mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); + } + if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; + mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); + } + __HAL_JPEG_DISABLE_IT(hjpeg,mask); + + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Resume the JPEG Input/Output processing + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param XferSelection: This parameter can be one of the following values : + * JPEG_PAUSE_RESUME_INPUT : Resume Input processing + * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing + * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) +{ + uint32_t mask = 0; + + assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); + + if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + + if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); + mask |= JPEG_DMA_IDMA; + + /*JPEG Input DMA transfer data number must be multiple of DMA buffer size + as the destination is a 32 bits register */ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); + + if(hjpeg->InDataLength > 0) + { + /* Start DMA FIFO In transfer */ + HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2); + } + + } + if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); + mask |= JPEG_DMA_ODMA; + + /* Start DMA FIFO Out transfer */ + HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2); + } + JPEG_ENABLE_DMA(hjpeg,mask); + + } + else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); + mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); + } + if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); + mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); + } + __HAL_JPEG_ENABLE_IT(hjpeg,mask); + + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Config Encoding/Decoding Input Buffer. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module. + * @param pNewInputBuffer: Pointer to the new input data buffer + * @param InDataLength: Size in bytes of the new Input data buffer + * @retval HAL status + */ +void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength) +{ + hjpeg->pJpegInBuffPtr = pNewInputBuffer; + hjpeg->InDataLength = InDataLength; +} + +/** + * @brief Config Encoding/Decoding Output Buffer. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module. + * @param pNewOutputBuffer: Pointer to the new output data buffer + * @param OutDataLength: Size in bytes of the new Output data buffer + * @retval HAL status + */ +void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength) +{ + hjpeg->pJpegOutBuffPtr = pNewOutputBuffer; + hjpeg->OutDataLength = OutDataLength; +} + +/** + * @brief Aborts the JPEG Encoding/Decoding. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tickstart, tmpContext; + + tmpContext = hjpeg->Context; + + /*Reset the Context operation and method*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA); + + if((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + /* Stop the DMA In/out Xfer*/ + HAL_DMA_Abort(hjpeg->hdmaout); + HAL_DMA_Abort(hjpeg->hdmain); + } + + /* Stop the JPEG encoding/decoding process*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the JPEG Codec is effectively disabled */ + while(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > JPEG_TIMEOUT_VALUE) + { + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_TIMEOUT; + } + } + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Reset the Context Pause*/ + hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT); + + /* Change the DMA state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions + * @brief JPEG process callback functions. + * +@verbatim + ============================================================================== + ##### JPEG Decode/Encode callback functions ##### + ============================================================================== + [..] This section provides callback functions: + (+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback + (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback. + (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback. + (+) HAL_JPEG_ErrorCallback() : JPEG error callback. + (+) HAL_JPEG_GetDataCallback() : Get New Data chunk callback. + (+) HAL_JPEG_DataReadyCallback() : Decoded/Encoded Data ready callback. + +@endverbatim + * @{ + */ + +/** + * @brief Decoding JPEG Info ready callback. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains + * The JPEG decoded header informations + * @retval None + */ +__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(pInfo); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Encoding complete callback. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_EncodeCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Decoding complete callback. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_EncodeCpltCallback could be implemented in the user file + */ +} + +/** + * @brief JPEG error callback. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ + __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Get New Data chunk callback. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param NbDecodedData: Number of consummed data in the previous chunk in bytes + * @retval None + */ + __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(NbDecodedData); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_GetDataCallback could be implemented in the user file + */ +} + +/** + * @brief Decoded/Encoded Data ready callback. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataOut: pointer to the output data buffer + * @param OutDataLength: number in bytes of data available in the specified output buffer + * @retval None + */ +__weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(pDataOut); + UNUSED(OutDataLength); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_DataReadyCallback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management + * @brief JPEG IRQ handler. + * +@verbatim + ============================================================================== + ##### JPEG IRQ handler management ##### + ============================================================================== + [..] This section provides JPEG IRQ handler function. + (+) HAL_JPEG_IRQHandler() : handles JPEG interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief This function handles JPEG interrupt request. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg) +{ + switch(hjpeg->State) + { + case HAL_JPEG_STATE_BUSY_ENCODING: + case HAL_JPEG_STATE_BUSY_DECODING: + /* continue JPEG data encoding/Decoding*/ + /* JPEG data processing : In/Out FIFO transfer*/ + if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + JPEG_Process(hjpeg); + } + else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + JPEG_DMA_ContinueProcess(hjpeg); + + } + + break; + + default: + break; + } +} + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] This section provides JPEG State and Errors function. + (+) HAL_JPEG_GetState() : permits to get in run-time the JPEG state. + (+) HAL_JPEG_GetError() : Returns the JPEG error code if any. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the JPEG state. + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG state + */ +HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg) +{ + return hjpeg->State; +} + +/** +* @brief Return the JPEG error code +* @param hjpeg : pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the specified JPEG. +* @retval JPEG Error Code +*/ +uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) +{ + return hjpeg->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @addtogroup JPEG_Private_Functions + * @{ + */ + +/** + * @brief Generates Huffman sizes/Codes Table from Bits/vals Table + * @param Bits: pointer to bits table + * @param Huffsize: pointer to sizes table + * @param Huffcode: pointer to codes table + * @param LastK: pointer to last Coeff (table dimmension) + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) +{ + uint32_t i, p, l, code, si; + + /* Figure C.1 – Generation of table of Huffman code sizes */ + p = 0; + for (l = 0; l < 16; l++) + { + i = (uint32_t)Bits[l]; + if ( (p + i) > 256) + { /* check for table overflow */ + return HAL_ERROR; + } + while (i != 0) + { + Huffsize[p++] = (uint8_t) l+1; + i--; + } + } + Huffsize[p] = 0; + *LastK = p; + + /* Figure C.2 – Generation of table of Huffman codes */ + code = 0; + si = Huffsize[0]; + p = 0; + while (Huffsize[p] != 0) + { + while (((uint32_t) Huffsize[p]) == si) + { + Huffcode[p++] = code; + code++; + } + /* code must fit in "size" bits (si), no code is allowed to be all ones*/ + if (((uint32_t) code) >= (((uint32_t) 1) << si)) + { + return HAL_ERROR; + } + code <<= 1; + si++; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table + * that can programmed to the JPEG encoder registers + * @param AC_BitsValsTable: pointer to AC huffman bits/vals table + * @param AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable) +{ + HAL_StatusTypeDef error; + uint8_t huffsize[257]; + uint32_t huffcode[257]; + uint32_t k; + uint32_t l,lsb, msb; + uint32_t lastK; + + error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK); + if(error != HAL_OK) + { + return error; + } + + /* Figure C.3 – Ordering procedure for encoding procedure code tables */ + k=0; + + while(k < lastK) + { + l = AC_BitsValsTable->HuffVal[k]; + if(l == 0) + { + l = 160; /*l = 0x00 EOB code*/ + } + else if(l == 0xF0)/* l = 0xF0 ZRL code*/ + { + l = 161; + } + else + { + msb = (l & 0xF0) >> 4; + lsb = (l & 0x0F); + l = (msb * 10) + lsb - 1; + } + if(l >= JPEG_AC_HUFF_TABLE_SIZE) + { + return HAL_ERROR; /* Huffman Table overflow error*/ + } + else + { + AC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; + AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1; + k++; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table + * that can programmed to the JPEG encoder registers + * @param DC_BitsValsTable: pointer to DC huffman bits/vals table + * @param DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable) +{ + HAL_StatusTypeDef error; + + uint32_t k; + uint32_t l; + uint32_t lastK; + uint8_t huffsize[257]; + uint32_t huffcode[257]; + error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK); + if(error != HAL_OK) + { + return error; + } + /* Figure C.3: ordering procedure for encoding procedure code tables */ + k=0; + + while(k < lastK) + { + l = DC_BitsValsTable->HuffVal[k]; + if(l >= JPEG_DC_HUFF_TABLE_SIZE) + { + return HAL_ERROR; /* Huffman Table overflow error*/ + } + else + { + DC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; + DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1; + k++; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the JPEG register with an DC huffman table at the given DC table address + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableDC: pointer to DC huffman table + * @param DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress) +{ + HAL_StatusTypeDef error = HAL_OK; + JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable; + uint32_t i, lsb, msb; + __IO uint32_t *address, *addressDef; + + if(DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC0)) + { + address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE/2)); + } + else if (DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC1)) + { + address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE/2)); + } + else + { + return HAL_ERROR; + } + + if(HuffTableDC != NULL) + { + error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable); + if(error != HAL_OK) + { + return error; + } + addressDef = address; + *addressDef = 0x0FFF0FFF; + addressDef++; + *addressDef = 0x0FFF0FFF; + + i = JPEG_DC_HUFF_TABLE_SIZE; + while(i>0) + { + i--; + address --; + msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF); + i--; + lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF); + + *address = lsb | (msb << 16); + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the JPEG register with an AC huffman table at the given AC table address + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableAC: pointer to AC huffman table + * @param ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress) +{ + HAL_StatusTypeDef error = HAL_OK; + JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable; + uint32_t i, lsb, msb; + __IO uint32_t *address, *addressDef; + + if(ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC0)) + { + address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE/2)); + } + else if (ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC1)) + { + address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE/2)); + } + else + { + return HAL_ERROR; + } + + if(HuffTableAC != NULL) + { + error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable); + if(error != HAL_OK) + { + return error; + } + /* Default values settings : 162–167 FFFh , 168–175 FD0h–FD7h */ + /* Locations 162:175 of each AC table contain information used internally by the core */ + + addressDef = address; + for(i=0; i<3; i++) + { + *addressDef = 0x0FFF0FFF; + addressDef++; + } + *addressDef = 0x0FD10FD0; + addressDef++; + *addressDef = 0x0FD30FD2; + addressDef++; + *addressDef = 0x0FD50FD4; + addressDef++; + *addressDef = 0x0FD70FD6; + /* end of Locations 162:175 */ + + + i = JPEG_AC_HUFF_TABLE_SIZE; + while (i > 0) + { + i--; + address--; + msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF); + i--; + lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF); + + *address = lsb | (msb << 16); + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the JPEG encoder register huffman tables to used during + * the encdoing operation + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableAC0: AC0 huffman table + * @param HuffTableDC0: DC0 huffman table + * @param HuffTableAC1: AC1 huffman table + * @param HuffTableDC1: DC1 huffman table + * @retval None + */ +static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) +{ + HAL_StatusTypeDef error = HAL_OK; + + JPEG_Set_Huff_DHTMem(hjpeg, HuffTableAC0, HuffTableDC0, HuffTableAC1, HuffTableDC1); + + if(HuffTableAC0 != NULL) + { + error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC0, (uint32_t *)(hjpeg->Instance->HUFFENC_AC0)); + if(error != HAL_OK) + { + return error; + } + } + + if(HuffTableAC1 != NULL) + { + error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC1, (uint32_t *)(hjpeg->Instance->HUFFENC_AC1)); + if(error != HAL_OK) + { + return error; + } + } + + if(HuffTableDC0 != NULL) + { + error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC0, (uint32_t *)hjpeg->Instance->HUFFENC_DC0); + if(error != HAL_OK) + { + return error; + } + } + + if(HuffTableDC1 != NULL) + { + error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC1, (uint32_t *)hjpeg->Instance->HUFFENC_DC1); + if(error != HAL_OK) + { + return error; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the JPEG register huffman tables to be included in the JPEG + * file header (used for encoding only) + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableAC0: AC0 huffman table + * @param HuffTableDC0: DC0 huffman table + * @param HuffTableAC1: AC1 huffman table + * @param HuffTableDC1: DC1 huffman table + * @retval None + */ +static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) +{ + uint32_t value, index; + __IO uint32_t *address; + if(HuffTableDC0 != NULL) + { + /* DC0 Huffman Table : BITS*/ + /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/ + address = (hjpeg->Instance->DHTMEM + 3); + index = 16; + while(index > 0) + { + + *address = (((uint32_t)HuffTableDC0->Bits[index-1] & 0xFF) << 24)| + (((uint32_t)HuffTableDC0->Bits[index-2] & 0xFF) << 16)| + (((uint32_t)HuffTableDC0->Bits[index-3] & 0xFF) << 8) | + ((uint32_t)HuffTableDC0->Bits[index-4] & 0xFF); + address--; + index -=4; + + } + /* DC0 Huffman Table : Val*/ + /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */ + address = (hjpeg->Instance->DHTMEM + 6); + index = 12; + while(index > 0) + { + *address = (((uint32_t)HuffTableDC0->HuffVal[index-1] & 0xFF) << 24)| + (((uint32_t)HuffTableDC0->HuffVal[index-2] & 0xFF) << 16)| + (((uint32_t)HuffTableDC0->HuffVal[index-3] & 0xFF) << 8) | + ((uint32_t)HuffTableDC0->HuffVal[index-4] & 0xFF); + address--; + index -=4; + } + } + + if(HuffTableAC0 != NULL) + { + /* AC0 Huffman Table : BITS*/ + /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/ + address = (hjpeg->Instance->DHTMEM + 10); + index = 16; + while(index > 0) + { + + *address = (((uint32_t)HuffTableAC0->Bits[index-1] & 0xFF) << 24)| + (((uint32_t)HuffTableAC0->Bits[index-2] & 0xFF) << 16)| + (((uint32_t)HuffTableAC0->Bits[index-3] & 0xFF) << 8) | + ((uint32_t)HuffTableAC0->Bits[index-4] & 0xFF); + address--; + index -=4; + + } + /* AC0 Huffman Table : Val*/ + /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */ + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */ + address = (hjpeg->Instance->DHTMEM + 51); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFF) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFF); + *address = value; + + /*continue setting 160 AC0 huffman values */ + address--; /* address = hjpeg->Instance->DHTMEM + 50*/ + index = 160; + while(index > 0) + { + *address = (((uint32_t)HuffTableAC0->HuffVal[index-1] & 0xFF) << 24)| + (((uint32_t)HuffTableAC0->HuffVal[index-2] & 0xFF) << 16)| + (((uint32_t)HuffTableAC0->HuffVal[index-3] & 0xFF) << 8) | + ((uint32_t)HuffTableAC0->HuffVal[index-4] & 0xFF); + address--; + index -=4; + } + } + + if(HuffTableDC1 != NULL) + { + /* DC1 Huffman Table : BITS*/ + /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 51); + value = *address & 0x0000FFFFU; + value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFF) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 55); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFF); + *address = value; + + /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/ + address--; + index = 12; + while(index > 0) + { + + *address = (((uint32_t)HuffTableDC1->Bits[index+1] & 0xFF) << 24)| + (((uint32_t)HuffTableDC1->Bits[index] & 0xFF) << 16)| + (((uint32_t)HuffTableDC1->Bits[index-1] & 0xFF) << 8) | + ((uint32_t)HuffTableDC1->Bits[index-2] & 0xFF); + address--; + index -=4; + + } + /* DC1 Huffman Table : Val*/ + /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */ + address = (hjpeg->Instance->DHTMEM + 55); + value = *address & 0x0000FFFF; + value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFF) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */ + address = (hjpeg->Instance->DHTMEM + 58); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFF); + *address = value; + + /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/ + address--; + index = 8; + while(index > 0) + { + *address = (((uint32_t)HuffTableDC1->HuffVal[index+1] & 0xFF) << 24)| + (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFF) << 16)| + (((uint32_t)HuffTableDC1->HuffVal[index-1] & 0xFF) << 8) | + ((uint32_t)HuffTableDC1->HuffVal[index-2] & 0xFF); + address--; + index -=4; + } + } + + if(HuffTableAC1 != NULL) + { + /* AC1 Huffman Table : BITS*/ + /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 58); + value = *address & 0x0000FFFFU; + value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFF) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */ + address = (hjpeg->Instance->DHTMEM + 62); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFF); + *address = value; + + /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/ + address--; + index = 12; + while(index > 0) + { + + *address = (((uint32_t)HuffTableAC1->Bits[index+1] & 0xFF) << 24)| + (((uint32_t)HuffTableAC1->Bits[index] & 0xFF) << 16)| + (((uint32_t)HuffTableAC1->Bits[index-1] & 0xFF) << 8) | + ((uint32_t)HuffTableAC1->Bits[index-2] & 0xFF); + address--; + index -=4; + + } + /* AC1 Huffman Table : Val*/ + /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */ + address = (hjpeg->Instance->DHTMEM + 62); + value = *address & 0x0000FFFF; + value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFF) << 16); + *address = value; + + /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */ + address = (hjpeg->Instance->DHTMEM + 102); + index = 160; + while(index > 0) + { + *address = (((uint32_t)HuffTableAC1->HuffVal[index+1] & 0xFF) << 24)| + (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFF) << 16)| + (((uint32_t)HuffTableAC1->HuffVal[index-1] & 0xFF) << 8) | + ((uint32_t)HuffTableAC1->HuffVal[index-2] & 0xFF); + address--; + index -=4; + } + } +} + +/** + * @brief Configure the JPEG registers with a given quantization table + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param QTable: pointer to an array of 64 bytes giving the quantization table + * @param QTableAddress: destination quantization address in the JPEG peripheral + * it could be QMEM0, QMEM1, QMEM2 or QMEM3 + * @retval None + */ +static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress) +{ + uint32_t i, j, *tableAddress, quantRow, quantVal, ScaleFactor; + + if((QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM0))) || + (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM1))) || + (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM2))) || + (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM3)))) + { + tableAddress = QTableAddress; + } + else + { + return HAL_ERROR; + } + + if ((hjpeg->Conf.ImageQuality >= 50) && (hjpeg->Conf.ImageQuality <= 100)) + { + ScaleFactor = 200 - (hjpeg->Conf.ImageQuality * 2); + } + else if (hjpeg->Conf.ImageQuality > 0) + { + ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality); + } + else + { + return HAL_ERROR; + } + + /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/ + i = 0; + while( i < JPEG_QUANT_TABLE_SIZE) + { + quantRow = 0; + for(j=0; j<4; j++) + { + /* Note that the quantization coefficients must be specified in the table in zigzag order */ + quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i+j]]) * ScaleFactor) + 50) / 100; + + if(quantVal == 0) + { + quantVal = 1; + } + else if (quantVal > 255) + { + quantVal = 255; + } + + quantRow |= ((quantVal & 0xFF) << (8 * j)); + } + + i += 4; + *tableAddress = quantRow; + tableAddress ++; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the JPEG registers for YCbCr color space + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t ySamplingH; + uint32_t ySamplingV; + uint32_t yblockNb; + + /*Set Number of color components to 3*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_NF; + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1; + + /* compute MCU block size and Y, Cb ,Cr sampling factors*/ + if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ + + yblockNb = 0x30; /* 4 blocks of 8x8*/ + } + else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0x10; /* 2 blocks of 8x8*/ + } + else /*JPEG_444_SUBSAMPLING and default*/ + { + ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0; /* 1 block of 8x8*/ + } + + hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); + hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1); + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) ); + + /*Reset CONFR5 register*/ + hjpeg->Instance->CONFR5 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ + hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD); + + /*Reset CONFR6 register*/ + hjpeg->Instance->CONFR6 = 0; + /*Set Horizental and Vertical sampling factor and number of blocks for component 2*/ + /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */ + /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */ + hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD); + +} + +/** + * @brief Configure the JPEG registers for GrayScale color space + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg) +{ + /*Set Number of color components to 1*/ + hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); + + /*in GrayScale use 1 single Quantization table (Table 0)*/ + /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/ + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ; +} + +/** + * @brief Configure the JPEG registers for CMYK color space + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t ySamplingH; + uint32_t ySamplingV; + uint32_t yblockNb; + + /*Set Number of color components to 4*/ + hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS); + + /* compute MCU block size and Y, Cb ,Cr sampling factors*/ + if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ + + yblockNb = 0x30; /* 4 blocks of 8x8*/ + } + else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0x10; /* 2 blocks of 8x8*/ + } + else /*JPEG_444_SUBSAMPLING and default*/ + { + ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0; /* 1 block of 8x8*/ + } + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) ); + + /*Reset CONFR5 register*/ + hjpeg->Instance->CONFR5 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ + hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0); + + /*Reset CONFR6 register*/ + hjpeg->Instance->CONFR6 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/ + hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0); + + /*Reset CONFR7 register*/ + hjpeg->Instance->CONFR7 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/ + hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0); +} + +/** + * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg) +{ + /*Reset pause*/ + hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)); + + if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + /*Set JPEG Codec to Decoding mode */ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE; + } + else if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE) + { + /*Set JPEG Codec to Encoding mode */ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE; + } + + /*Stop JPEG processing */ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); + + /*Start Encoding/Decoding*/ + hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START; + + if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC |JPEG_IT_HPD); + } + else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + /*Enable End Of Conversation, and End Of Header parsing interruptions*/ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC |JPEG_IT_HPD); + + } +} + +/** + * @brief JPEG encoding/decoding process in case of Polling or Interrupt + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING + */ +static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext; + + /*End of header processing flag rised*/ + if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET)) + { + /*Call Header parsing complet callback */ + HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); + /* Reset the ImageQuality */ + hjpeg->Conf.ImageQuality = 0; + /* Note : the image quality is only available at the end of the decoding operation */ + /* at the current stage the calculated image quality is not correct so reset it */ + + /*Call Info Ready callback */ + HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); + + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD); + + /* Clear header processing done flag */ + __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF); + } + + /*Input FIFO status handling*/ + if((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) + { + if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != RESET) + { + /*Input FIFO threshold flag rised*/ + /*4 words (16 bytes) can be written in */ + JPEG_ReadInputData(hjpeg,4); + } + else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != RESET) + { + /*Input FIFO Not Full flag rised*/ + /*32-bit value can be written in */ + JPEG_ReadInputData(hjpeg,1); + } + } + + + /*Output FIFO flag handling*/ + if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0) + { + if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != RESET) + { + /*Output FIFO threshold flag rised*/ + /*4 words (16 bytes) can be read out */ + JPEG_StoreOutputData(hjpeg, 4); + } + else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != RESET) + { + /*Output FIFO Not Empty flag rised*/ + /*32-bit value can be read out */ + JPEG_StoreOutputData(hjpeg, 1); + } + } + + /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/ + if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF) + { + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + } + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); + + /*Call End of conversion callback */ + if(hjpeg->JpegOutCount > 0) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + hjpeg->JpegOutCount = 0; + } + + /*Reset Context Operation*/ + tmpContext = hjpeg->Context; + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + HAL_JPEG_DecodeCpltCallback(hjpeg); + } + else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE) + { + HAL_JPEG_EncodeCpltCallback(hjpeg); + } + + return JPEG_PROCESS_DONE; + } + + + return JPEG_PROCESS_ONGOING; +} + +/** + * @brief Store some output data from the JPEG peripheral to the output buffer. + * This function is used when the JPEG peripheral has new data to output + * in case of Polling or Interrupt process + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral + * @retval None + */ +static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) +{ + uint32_t index, nBwords, nbBytes , dataword, *pOutData; + + pOutData = (uint32_t *)(((uint32_t *)hjpeg->pJpegOutBuffPtr) + (hjpeg->JpegOutCount/4)); + + if(hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords*4))) + { + for(index = 0; index < nbOutputWords; index++) + { + /*Transfer 32 bits from the JPEG output FIFO*/ + *pOutData = hjpeg->Instance->DOR; + pOutData++; + hjpeg->JpegOutCount += 4; + } + if(hjpeg->OutDataLength == hjpeg->JpegOutCount) + { + /*Output Buffer is full, call DecodedDataReadyCallback*/ + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + hjpeg->JpegOutCount = 0; + } + } + else if(hjpeg->OutDataLength > hjpeg->JpegOutCount) + { + nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount)/4; + for(index = 0; index < nBwords; index++) + { + /*Transfer 32 bits from the JPEG output FIFO*/ + *pOutData = hjpeg->Instance->DOR; + pOutData++; + hjpeg->JpegOutCount += 4; + } + if(hjpeg->OutDataLength == hjpeg->JpegOutCount) + { + /*Output Buffer is full, call DecodedDataReadyCallback*/ + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + hjpeg->JpegOutCount = 0; + } + else + { + nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; + dataword = hjpeg->Instance->DOR; + for(index = 0; index < nbBytes; index++) + { + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF; + hjpeg->JpegOutCount++; + } + /*Output Buffer is full, call DecodedDataReadyCallback*/ + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + hjpeg->JpegOutCount = 0; + + nbBytes = 4 - nbBytes; + for(index = nbBytes; index < 4; index++) + { + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF; + hjpeg->JpegOutCount++; + } + } + } +} + +/** + * @brief Read some input Data from the input buffer. + * This function is used when the JPEG peripheral needs new data + * in case of Polling or Interrupt process + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request + * @retval None + */ +static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) +{ + uint32_t nbBytes = 0, nBwords, index, Dataword; + + if((hjpeg->InDataLength == 0) || (nbRequestWords == 0)) + { + /* No more Input data : nothing to do*/ + HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT); + } + else if(hjpeg->InDataLength > hjpeg->JpegInCount) + { + nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount; + } + else if(hjpeg->InDataLength == hjpeg->JpegInCount) + { + /*Call HAL_JPEG_GetDataCallback to get new data */ + HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); + if(hjpeg->InDataLength > 4) + { + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); + } + hjpeg->JpegInCount = 0; + nbBytes = hjpeg->InDataLength; + } + if((nbBytes > 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0)) + { + nBwords = nbBytes / 4; + if(nBwords >= nbRequestWords) + { + for(index = 0; index < nbRequestWords; index++) + { + hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4))); + + hjpeg->JpegInCount += 4; + } + } + else /*nBwords < nbRequestWords*/ + { + if(nBwords > 0) + { + for(index = 0; index < nBwords; index++) + { + hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4))); + + hjpeg->JpegInCount += 4; + } + } + else + { + /* end of file*/ + Dataword = 0; + for(index=0; index< nbBytes; index++) + { + Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8 * index); + hjpeg->JpegInCount++; + } + hjpeg->Instance->DIR = Dataword; + } + } + } +} + +/** + * @brief Start the JPEG DMA process (encoding/decoding) + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING + */ +static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) +{ + if((hjpeg->InDataLength < 4) || (hjpeg->OutDataLength < 4)) + { + return HAL_ERROR; + } + /* Reset Ending DMA internal context flag*/ + hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA; + + /* Disable DMA In/Out Request*/ + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA); + + /* Set the JPEG DMA In transfer complete callback */ + hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback; + /* Set the DMA In error callback */ + hjpeg->hdmain->XferErrorCallback = JPEG_DMAErrorCallback; + + /* Set the JPEG DMA Out transfer complete callback */ + hjpeg->hdmaout->XferCpltCallback = JPEG_DMAOutCpltCallback; + /* Set the DMA Out error callback */ + hjpeg->hdmaout->XferErrorCallback = JPEG_DMAErrorCallback; + /* Set the DMA Out Abort callback */ + hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback; + + /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); + + /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/ + hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4); + + /* Start DMA FIFO In transfer */ + HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2); + + /* Start DMA FIFO Out transfer */ + HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2); + + /* Enable JPEG In/Out DMA requests*/ + JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA | JPEG_DMA_ODMA); + + return HAL_OK; +} + +/** + * @brief Continue the current JPEG DMA process (encoding/decoding) + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING + */ +static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) +{ + /*End of header processing flag rises*/ + if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET)) + { + /*Call Header parsing complete callback */ + HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); + + /* Reset the ImageQuality */ + hjpeg->Conf.ImageQuality = 0; + /* Note : the image quality is only available at the end of the decoding operation */ + /* at the current stage the calculated image quality is not correct so reset it */ + + /*Call Info Ready callback */ + HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); + + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD); + + /* Clear header processing done flag */ + __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF); + } + + /*End of Conversion handling*/ + if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != RESET) + { + /*Disabkle JPEG In/Out DMA Requests*/ + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA); + + hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA; + + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL); + + if(hjpeg->hdmain->State == HAL_DMA_STATE_BUSY) + { + /* Stop the DMA In Xfer*/ + HAL_DMA_Abort_IT(hjpeg->hdmain); + } + + if(hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY) + { + /* Stop the DMA out Xfer*/ + HAL_DMA_Abort_IT(hjpeg->hdmaout); + } + else + { + return JPEG_DMA_EndProcess(hjpeg); + } + } + + return JPEG_PROCESS_ONGOING; +} + +/** + * @brief Finalize the current JPEG DMA process (encoding/decoding) + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE + */ +static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext, count = JPEG_FIFO_SIZE, *pDataOut; + + hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hjpeg->hdmaout->Instance->NDTR & DMA_SxNDT) << 2); + + /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ + if(hjpeg->JpegOutCount == hjpeg->OutDataLength) + { + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + hjpeg->JpegOutCount = 0; + } + + pDataOut = (uint32_t *)(hjpeg->pJpegOutBuffPtr + hjpeg->JpegOutCount); + + while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0)) + { + count--; + + *pDataOut = hjpeg->Instance->DOR; + pDataOut++; + hjpeg->JpegOutCount += 4; + + if(hjpeg->JpegOutCount == hjpeg->OutDataLength) + { + /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + hjpeg->JpegOutCount = 0; + } + } + + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + if(hjpeg->JpegOutCount > 0) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + hjpeg->JpegOutCount = 0; + } + + tmpContext = hjpeg->Context; + /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + HAL_JPEG_DecodeCpltCallback(hjpeg); + } + else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE) + { + HAL_JPEG_EncodeCpltCallback(hjpeg); + } + + + return JPEG_PROCESS_DONE; +} + +/** + * @brief DMA input transfer complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + + if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0)) + { + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_IDMA); + + hjpeg->JpegInCount = hjpeg->InDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2); + + /*Call HAL_JPEG_GetDataCallback to get new data */ + HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); + + if(hjpeg->InDataLength >= 4) + { + /*JPEG Input DMA transfer data number must be multiple of 32 bits word + as the destination is a 32 bits (4 bytes) register */ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4); + } + else if(hjpeg->InDataLength > 0) + { + /*Transfer last data word (i.e last 4 bytes)*/ + hjpeg->InDataLength = 4; + } + + if(((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) && (hjpeg->InDataLength > 0)) + { + /* Start DMA FIFO In transfer */ + HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2); + JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA); + } + + /* JPEG Conversion still on going : Enable the JPEG IT */ + __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD); + } +} + +/** + * @brief DMA output transfer complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + + if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0)) + { + if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0) + { + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA); + hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2); + + /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ + HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); + + if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0) + { + /* Start DMA FIFO Out transfer */ + HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2); + JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_ODMA); + } + } + + /* JPEG Conversion still on going : Enable the JPEG IT */ + __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD); + } +} + +/** + * @brief DMA Transfer error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* if DMA error is FIFO error ignore it */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK); + + hjpeg->State= HAL_JPEG_STATE_READY; + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + HAL_JPEG_ErrorCallback(hjpeg); + } +} + +/** + * @brief DMA output Abort callback + * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0) + { + JPEG_DMA_EndProcess(hjpeg); + } +} + +/** + * @brief Calculate the decoded image quality (from 1 to 100) + * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG image quality from 1 to 100. + */ +static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t quality = 0; + uint32_t quantRow, quantVal,scale, i, j; + uint32_t *tableAddress = (uint32_t *)hjpeg->Instance->QMEM0; + + i = 0; + while( i < JPEG_QUANT_TABLE_SIZE) + { + quantRow = *tableAddress; + for(j=0; j<4; j++) + { + quantVal = (quantRow >> (8 * j)) & 0xFF; + if(quantVal == 1) + { + /* if Quantization value = 1 then quality is 100%*/ + quality += 100; + } + else + { + /* Note that the quantization coefficients must be specified in the table in zigzag order */ + scale = (quantVal*100)/((uint32_t) JPEG_LUM_QuantTable[JPEG_ZIGZAG_ORDER[i+j]]); + + if(scale <= 100) + { + quality += (200 - scale)/2; + } + else + { + quality += 5000/scale; + } + } + } + + i += 4; + tableAddress ++; + } + + return (quality/((uint32_t)64)); +} +/** + * @} + */ + +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* HAL_JPEG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.h new file mode 100644 index 00000000000..90a99d935de --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.h @@ -0,0 +1,581 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_jpeg.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief Header file of JPEG HAL module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_JPEG_H +#define __STM32F7xx_HAL_JPEG_H + +#ifdef __cplusplus + extern "C" { +#endif +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup JPEG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup JPEG_Exported_Types JPEG Exported Types + * @{ + */ + +/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition + * @brief JPEG encoding configuration Structure definition + * @{ + */ +typedef struct +{ + uint8_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK + This parameter can be a value of @ref JPEG_ColorSpace_Type */ + + uint8_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0 + This parameter can be a value of @ref JPEG_ChromaSubsampling_Type */ + + uint32_t ImageHeight; /*!< Image height : number of lines */ + + uint32_t ImageWidth; /*!< Image width : number of pixels per line */ + + uint8_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */ + +}JPEG_ConfTypeDef; +/** + * @} + */ + +/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition + * @brief HAL JPEG State structure definition + * @{ + */ +typedef enum +{ + HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */ + HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */ + HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */ + HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */ + HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */ + HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */ + HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */ +}HAL_JPEG_STATETypeDef; + +/** + * @} + */ + + +/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition + * @brief JPEG handle Structure definition + * @{ + */ +typedef struct +{ + JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */ + + JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */ + + uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */ + + uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */ + + __IO uint32_t JpegInCount; /*!< Internal Counter of input data */ + + __IO uint32_t JpegOutCount; /*!< Internal Counter of output data */ + + uint32_t InDataLength; /*!< Input Buffer Length in Bytes */ + + uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */ + + DMA_HandleTypeDef *hdmain; /*!< JPEG In DMA handle parameters */ + + DMA_HandleTypeDef *hdmaout; /*!< JPEG Out DMA handle parameters */ + + uint8_t CustomQuanTable; /*!< If set to ‘1’ specify that user customized quantization tables are used */ + + uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */ + + uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */ + + uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */ + + uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */ + + HAL_LockTypeDef Lock; /*!< JPEG locking object */ + + __IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */ + + __IO uint32_t ErrorCode; /*!< JPEG Error code */ + + __IO uint32_t Context; /*!< JPEG Internal context */ + +}JPEG_HandleTypeDef; + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup JPEG_Exported_Constants JPEG Exported Constants + * @{ + */ + +/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition + * @brief JPEG Error Code definition + * @{ + */ + +#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */ +#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */ +#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ +#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */ + +/** + * @} + */ + +/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size + * @brief JPEG Quantization Table Size + * @{ + */ +#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) +/** + * @} + */ + + +/** @defgroup JPEG_ColorSpace_Type JPEG ColorSpace + * @brief JPEG Color Space + * @{ + */ +#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U) +#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0 +#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE + + +/** + * @} + */ + + +/** @defgroup JPEG_ChromaSubsampling_Type JPEG Chrominance Sampling + * @brief JPEG Chrominance Sampling + * @{ + */ +#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */ +#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */ +#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */ + +/** + * @} + */ + +/** @defgroup JPEG_ImageQuality JPEG Image Quality + * @brief JPEG Min and Max Image Quality + * @{ + */ +#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */ +#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */ + +/** + * @} + */ + +/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition + * @brief JPEG Interrupt definition + * @{ + */ +#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */ +#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */ +#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */ +#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */ +#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */ +#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */ +/** + * @} + */ + +/** @defgroup JPEG_Flag_definition JPEG Flag definition + * @brief JPEG Flags definition + * @{ + */ +#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */ +#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */ +#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */ +#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */ +#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */ +#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/ + +#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/ +/** + * @} + */ + +/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition + * @brief JPEG process pause, resume definition + * @{ + */ +#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/ +#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/ +#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup JPEG_Exported_Macros JPEG Exported Macros + * @{ + */ + +/** @brief Reset JPEG handle state + * @param __HANDLE__: specifies the JPEG handle. + * @retval None + */ +#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET) + + +/** + * @brief Enable the JPEG peripheral. + * @param __HANDLE__: specifies the JPEG handle. + * @retval None + */ +#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN) + +/** + * @brief Disable the JPEG peripheral. + * @param __HANDLE__: specifies the JPEG handle. + * @retval None + */ +#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN) + + +/** + * @brief Check the specified JPEG status flag. + * @param __HANDLE__: specifies the JPEG handle. + * @param __FLAG__ : specifies the flag to check + * This parameter can be one of the following values: + * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag + * @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written + * @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold + * @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available + * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process + * and than last data has been sent to the output FIFO + * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers + * and the internal registers have been updated + * @arg JPEG_FLAG_COF : JPEG Codec operation on going flag + * + * @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE) + */ + +#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__))) + +/** + * @brief Clear the specified JPEG status flag. + * @param __HANDLE__: specifies the JPEG handle. + * @param __FLAG__ : specifies the flag to clear + * This parameter can be one of the following values: + * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process + * and than last data has been sent to the output FIFO + * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers + * @retval : None + */ + +#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF)))) + + +/** + * @brief Enable Interrupt. + * @param __HANDLE__: specifies the JPEG handle. + * @param __INTERRUPT__ : specifies the interrupt to enable + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @retval : No retrun + */ +#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) ) + +/** + * @brief Disable Interrupt. + * @param __HANDLE__: specifies the JPEG handle. + * @param __INTERRUPT__ : specifies the interrupt to disable + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @note : To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits + * located in the same IT enable register (CR register). + * @retval : No retrun + */ +#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0) + + +/** + * @brief Get Interrupt state. + * @param __HANDLE__: specifies the JPEG handle. + * @param __INTERRUPT__ : specifies the interrupt to check + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @retval : returns The new state of __INTERRUPT__ (Enabled or disabled) + */ +#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup JPEG_Exported_Functions + * @{ + */ + +/** @addtogroup JPEG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group2 + * @{ + */ +/* Encoding/Decoding Configuration functions ********************************/ +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf); +HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); +HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group3 + * @{ + */ +/* JPEG processing functions **************************************/ +HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout); +HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout); +HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); +HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); +void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength); +void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group4 + * @{ + */ +/* JPEG Decode/Encode callback functions ********************************************************/ +void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo); +void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData); +void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group5 + * @{ + */ +/* JPEG IRQ handler management ******************************************************/ +void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group6 + * @{ + */ +/* Peripheral State and Error functions ************************************************/ +HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg); +uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup JPEG_Private_Types JPEG Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup JPEG_Private_Defines JPEG Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Variables JPEG Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Constants JPEG Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup JPEG_Private_Macros JPEG Private Macros + * @{ + */ + +/** @defgroup JPEG_IS_Definitions JPEG Private macros to check input parameters + * @{ + */ + +#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \ + ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \ + ((SUBSAMPLING) == JPEG_422_SUBSAMPLING)) + +#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX)) + +#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \ + ((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \ + ((COLORSPACE) == JPEG_CMYK_COLORSPACE)) + +#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \ + ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \ + ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT)) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Functions JPEG Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_JPEG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c index 232ac277b33..0aaa27d72a7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_lptim.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief LPTIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Low Power Timer (LPTIM) peripheral: @@ -93,7 +93,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -1001,7 +1001,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; - + /* Configure edge sensitivity for encoder mode */ /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; @@ -1162,6 +1162,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + + /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; @@ -1200,6 +1206,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1295,6 +1307,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + + /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) @@ -1340,6 +1358,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1523,6 +1547,8 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) HAL_LPTIM_DirectionDownCallback(hlptim); } } + + __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h index f0508c36dbf..df50aa32d28 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_lptim.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -60,6 +60,14 @@ * @{ */ +/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line + * @{ + */ +#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */ +/** + * @} + */ + /** * @brief LPTIM Clock configuration definition */ @@ -137,11 +145,11 @@ typedef struct */ typedef enum __HAL_LPTIM_StateTypeDef { - HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ + HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ }HAL_LPTIM_StateTypeDef; /** @@ -173,7 +181,7 @@ typedef struct /** @defgroup LPTIM_Clock_Source LPTIM Clock Source * @{ */ -#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00) +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U) #define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL /** * @} @@ -182,7 +190,7 @@ typedef struct /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler * @{ */ -#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000) +#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U) #define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 #define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 #define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)) @@ -198,7 +206,7 @@ typedef struct * @{ */ -#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) +#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U) #define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL) /** * @} @@ -207,7 +215,7 @@ typedef struct /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time * @{ */ -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT @@ -219,7 +227,7 @@ typedef struct * @{ */ -#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000) +#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U) #define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 #define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /** @@ -229,8 +237,8 @@ typedef struct /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source * @{ */ -#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF) -#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000) +#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU) +#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U) #define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) #define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 #define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) @@ -253,7 +261,7 @@ typedef struct /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time * @{ */ -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT @@ -265,7 +273,7 @@ typedef struct * @{ */ -#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000) +#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U) #define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /** * @} @@ -275,7 +283,7 @@ typedef struct * @{ */ -#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000) +#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U) #define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE /** * @} @@ -440,6 +448,89 @@ typedef struct #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +/** + * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\ + }while(0) + +/** + * @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ + }while(0) + +/** + * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the LPTIM Wake-up Timer associated Exti line flag. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + /** * @} */ @@ -610,13 +701,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU) -#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF) +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU) -#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF) +#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU) -#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF) +#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c index 09925fbb879..fa80f9b0ef8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief LTDC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: @@ -43,6 +43,19 @@ for foreground or/and background layer using respectively the following functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress. + + (#) Variant functions with “_NoReload” post fix allows to set the LTDC configuration/settings without immediate reload. + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + then applying(reload) these settings in one shot by calling the function “HAL_LTDC_Reload” + + After calling the “_NoReload” functions to set different color/format/layer settings, + the program can call the function “HAL_LTDC_Reload” To apply(Reload) these settings. + Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType” + set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required. + Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType” + set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period, + this option allows to avoid display flicker by applying the new settings during the vertical blanking period. + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() @@ -69,7 +82,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -102,7 +115,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup LTDC LTDC * @brief LTDC HAL module driver @@ -381,6 +394,27 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) HAL_LTDC_LineEvenCallback(hltdc); } } + /* Register reload Interrupt management ***************************************/ + if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET) + { + if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Register reload interrupt Callback */ + HAL_LTDC_ReloadEventCallback(hltdc); + } + } } /** @@ -415,6 +449,22 @@ __weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc) */ } +/** + * @brief Reload Event callback. + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + /** * @} */ @@ -741,7 +791,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) hltdc->State = HAL_LTDC_STATE_BUSY; /* Enable Dither by setting DTEN bit */ - LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN; + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -768,7 +818,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) hltdc->State = HAL_LTDC_STATE_BUSY; /* Disable Dither by setting DTEN bit */ - LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN; + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1029,7 +1079,81 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres } /** - * @brief Define the position of the line interrupt . + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx: LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Sets the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Sets the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Line: Line Interrupt Position. @@ -1061,6 +1185,592 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t return HAL_OK; } +/** + * @brief LTDC configuration reload. + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType: This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + assert_param(IS_LTDC_RELAOD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not Sets the Reload */ + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize: LTDC Pixel per line + * @param YSize: LTDC Line number + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = 0; + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = 0; + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0: LTDC window X offset + * @param Y0: LTDC window Y offset + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat: new pixel format value. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha: new alpha value. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address: new address value. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx: LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue: the color key value + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Configures the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx: LTDC Layer index. + * This parameter can be one of the following values: + * 0 or 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not Sets the Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + /** * @} */ @@ -1196,7 +1906,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /** * @} */ -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h index 547fa5da655..60672acf4c0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,8 @@ extern "C" { #endif -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -172,11 +173,11 @@ typedef struct */ typedef enum { - HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */ - HAL_LTDC_STATE_READY = 0x01, /*!< LTDC initialized and ready for use */ - HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */ - HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */ - HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ }HAL_LTDC_StateTypeDef; /** @@ -209,10 +210,10 @@ typedef struct /** @defgroup LTDC_Error_Code LTDC Error Code * @{ */ -#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000) /*!< LTDC No error */ -#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001) /*!< LTDC Transfer error */ -#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002) /*!< LTDC FIFO Underrun */ -#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< LTDC Timeout error */ +#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */ /** * @} */ @@ -220,7 +221,7 @@ typedef struct /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY * @{ */ -#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */ #define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ /** * @} @@ -229,7 +230,7 @@ typedef struct /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY * @{ */ -#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */ #define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ /** * @} @@ -238,7 +239,7 @@ typedef struct /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY * @{ */ -#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */ #define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ /** * @} @@ -247,7 +248,7 @@ typedef struct /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY * @{ */ -#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */ #define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ /** * @} @@ -265,7 +266,7 @@ typedef struct /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR * @{ */ -#define LTDC_COLOR ((uint32_t)0x000000FF) /*!< Color mask */ +#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */ /** * @} */ @@ -273,8 +274,8 @@ typedef struct /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 * @{ */ -#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400) /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ /** * @} */ @@ -282,8 +283,8 @@ typedef struct /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 * @{ */ -#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005) /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ /** * @} */ @@ -291,14 +292,14 @@ typedef struct /** @defgroup LTDC_Pixelformat LTDC Pixel format * @{ */ -#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001) /*!< RGB888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006) /*!< AL44 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007) /*!< AL88 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */ /** * @} */ @@ -345,6 +346,15 @@ typedef struct * @} */ +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + /** * @} */ @@ -467,6 +477,12 @@ typedef struct /** * @} */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/* Include LTDC HAL Extension module */ +#include "stm32f7xx_hal_ltdc_ex.h" +#endif /* STM32F769xx) | STM32F779xx */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup LTDC_Exported_Functions * @{ @@ -481,6 +497,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); /** * @} */ @@ -504,6 +521,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -513,6 +531,20 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + /** * @} */ @@ -599,6 +631,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER) #define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER) #define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF) +#define IS_LTDC_RELAOD(RELOADTYPE) (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR)) /** * @} */ @@ -615,7 +648,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** * @} */ -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.c new file mode 100644 index 00000000000..c3b519f3e43 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.c @@ -0,0 +1,164 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_ltdc_ex.c + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +#ifdef HAL_LTDC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ +#if defined (STM32F769xx) || defined (STM32F779xx) +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ + + return HAL_OK; +} +#endif /*STM32F769xx | STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_LTCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.h new file mode 100644 index 00000000000..e88f8d27c64 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.h @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_ltdc_ex.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_LTDC_EX_H +#define __STM32F7xx_HAL_LTDC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32F769xx) || defined (STM32F779xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" +#include "stm32f7xx_hal_dsi.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Constants LTDCEx Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ +HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + + + /* Private types -------------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Types LTDCEx Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros + * @{ + */ + + /** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /*STM32F769xx | STM32F779xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_LTDC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.c new file mode 100644 index 00000000000..500cacf3a3c --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.c @@ -0,0 +1,629 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_mdios.c + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief MDIOS HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the MDIOS Peripheral. + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The MDIOS HAL driver can be used as follow: + + (#) Declare a MDIOS_HandleTypeDef handle structure. + + (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API: + (##) Enable the MDIOS interface clock. + (##) MDIOS pins configuration: + (+++) Enable clocks for the MDIOS GPIOs. + (+++) Configure the MDIOS pins as alternate function. + (##) NVIC configuration if you need to use interrupt process: + (+++) Configure the MDIOS interrupt priority. + (+++) Enable the NVIC MDIOS IRQ handle. + + (#) Program the Port Address and the Preamble Check in the Init structure. + + (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API. + + (#) Perform direct slave read/write operations using the following APIs: + (##) Read the value of a DINn register: HAL_MDIOS_ReadReg() + (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() + + (#) Get the Master read/write operations flags using the following APIs: + (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() + (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() + + (#) Clear the read/write flags using the following APIs: + (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress() + (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress() + + (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called + the MDIOS will generate an interrupt in the following cases: + (##) a DINn register written by the Master + (##) a DOUTn register read by the Master + (##) an error occur + + (@) A callback is executed for each genereted interrupt, so the driver provide the following + HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback() + (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt + and execute the previous callbacks + + (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API. + (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources + (GPIO, Clocks, NVIC configuration ...) + + + @endverbatim + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup MDIOS MDIOS + * @brief HAL MDIOS module driver + * @{ + */ +#ifdef HAL_MDIOS_MODULE_ENABLED + +#if defined (MDIOS) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8) +#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU) +#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF)) + +#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100) +#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions + * @{ + */ + +/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the MDIOS + (+) The following parameters can be configured: + (++) Port Address + (++) Preamble Check + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MDIOS according to the specified parameters in + * the MDIOS_InitTypeDef and creates the associated handle . + * @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains + * the configuration information for MDIOS module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios) +{ + uint32_t tmpcr = 0; + + /* Check the MDIOS handle allocation */ + if(hmdios == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); + assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress)); + assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + if(hmdios->State == HAL_MDIOS_STATE_RESET) + { + /* Init the low level hardware */ + HAL_MDIOS_MspInit(hmdios); + } + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_BUSY; + + /* Get the MDIOS CR value */ + tmpcr = hmdios->Instance->CR; + + /* Clear PORT_ADDRESS, DPC and EN bits */ + tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS)); + + /* Set MDIOS control parametrs and enable the peripheral */ + tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\ + (hmdios->Init.PreambleCheck) | \ + (MDIOS_CR_EN)); + + /* Write the MDIOS CR */ + hmdios->Instance->CR = tmpcr; + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + /* Return function status */ + return HAL_OK; + +} + +/** + * @brief DeInitializes the MDIOS peripheral. + * @param hmdios: MDIOS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) +{ + /* Check the MDIOS handle allocation */ + if(hmdios == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_MDIOS_DISABLE(hmdios); + + /* DeInit the low level hardware */ + HAL_MDIOS_MspDeInit(hmdios); + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief MDIOS MSP Init + * @param hmdios: mdios handle + * @retval None + */ + __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_MspInit can be implemented in the user file + */ +} + +/** + * @brief MDIOS MSP DeInit + * @param hmdios: mdios handle + * @retval None + */ + __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_MspDeInit can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions + * @brief MDIOS Read/Write functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the MDIOS + read and write operations. + + (#) APIs that allow to the MDIOS to read/write from/to the + values of one of the DINn/DOUTn registers: + (+) Read the value of a DINn register: HAL_MDIOS_ReadReg() + (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() + + (#) APIs that provide if there are some Slave registres have been + read or written by the Master: + (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() + (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() + + (#) APIs that Clear the read/write flags: + (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress() + (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress() + + (#) A set of Callbacks are provided: + (+) HAL_MDIOS_WriteCpltCallback() + (+) HAL_MDIOS_ReadCpltCallback() + (+) HAL_MDIOS_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Writes to an MDIOS output register + * @param hmdios: mdios handle + * @param RegNum: MDIOS input register number + * @param Data: Data to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Get the addr of output register to be written by the MDIOS */ + tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum); + + /* Write to DOUTn register */ + *((uint32_t *)tmpreg) = Data; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Reads an MDIOS input register + * @param hmdios: mdios handle + * @param RegNum: MDIOS input register number + * @param pData: pointer to Data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Get the addr of input register to be read by the MDIOS */ + tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum); + + /* Read DINn register */ + *pData = (uint16_t)(*((uint32_t *)tmpreg)); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Gets Written registers by MDIO master + * @param hmdios: mdios handle + * @retval bit map of written registers addresses + */ +uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) +{ + return hmdios->Instance->WRFR; +} + +/** + * @brief Gets Read registers by MDIO master + * @param hmdios: mdios handle + * @retval bit map of read registers addresses + */ +uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) +{ + return hmdios->Instance->RDFR; +} + +/** + * @brief Clears Write registers flag + * @param hmdios: mdios handle + * @param RegNum: registers addresses to be cleared + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) +{ + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Clear write registers flags */ + hmdios->Instance->CWRFR |= (RegNum); + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Clears Read register flag + * @param hmdios: mdios handle + * @param RegNum: registers addresses to be cleared + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) +{ + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Clear read registers flags */ + hmdios->Instance->CRDFR |= (RegNum); + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Enables Events for MDIOS peripheral + * @param hmdios: mdios handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios) +{ + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */ + __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief This function handles MDIOS interrupt request. + * @param hmdios: MDIOS handle + * @retval None + */ +void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) +{ + /* Write Register Interrupt enabled ? */ + if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET) + { + /* Write register flag */ + if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET) + { + /* Write callback function */ + HAL_MDIOS_WriteCpltCallback(hmdios); + + /* Clear write register flag */ + HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG); + } + } + + /* Read Register Interrupt enabled ? */ + if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET) + { + /* Read register flag */ + if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET) + { + /* Read callback function */ + HAL_MDIOS_ReadCpltCallback(hmdios); + + /* Clear read register flag */ + HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG); + } + } + + /* Error Interrupt enabled ? */ + if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET) + { + /* All Errors Flag */ + if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET) + { + /* Error Callback */ + HAL_MDIOS_ErrorCallback(hmdios); + + /* Clear errors flag */ + __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG); + } + } + + /* check MDIOS WAKEUP exti flag */ + if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET) + { + /* MDIOS WAKEUP interrupt user callback */ + HAL_MDIOS_WakeUpCallback(hmdios); + + /* Clear MDIOS WAKEUP Exti pending bit */ + __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief Write Complete Callback + * @param hmdios: mdios handle + * @retval None + */ + __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_WriteCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Read Complete Callback + * @param hmdios: mdios handle + * @retval None + */ + __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_ReadCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Error Callback + * @param hmdios: mdios handle + * @retval None + */ + __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MDIOS WAKEUP interrupt callback + * @param hmdios: mdios handle + * @retval None + */ +__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MDIOS_WakeUpCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions + * @brief MDIOS control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the MDIOS. + (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. + (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Gets MDIOS error flags + * @param hmdios: mdios handle + * @retval bit map of occured errors + */ +uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) +{ + /* return errors flags on status register */ + return hmdios->Instance->SR; +} + +/** + * @brief Return the MDIOS HAL state + * @param hmdios: mdios handle + * @retval MDIOS state + */ +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) +{ + /* Return MDIOS state */ + return hmdios->State; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* MDIOS */ +#endif /* HAL_MDIOS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.h new file mode 100644 index 00000000000..a0f98c48830 --- /dev/null +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.h @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_mdios.h + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief Header file of MDIOS HAL module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_MDIOS_H +#define __STM32F7xx_HAL_MDIOS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (MDIOS) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup MDIOS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Types MDIOS Exported Types + * @{ + */ + +/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition + * @{ + */ + +typedef enum +{ + HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +}HAL_MDIOS_StateTypeDef; + +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition + * @{ + */ + +typedef struct +{ + uint32_t PortAddress; /*!< Specifies the MDIOS port address. + This parameter can be a value from 0 to 31 */ + uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled. + This parameter can be a value of @ref MDIOS_Preamble_Check */ +}MDIOS_InitTypeDef; + +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition + * @{ + */ + +typedef struct +{ + MDIOS_TypeDef *Instance; /*!< Register base address */ + + MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */ + + __IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */ + + HAL_LockTypeDef Lock; /*!< MDIOS Lock */ +}MDIOS_HandleTypeDef; + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants + * @{ + */ + +/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check + * @{ + */ +#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U) +#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC +/** + * @} + */ + +/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions + * @{ + */ +#define MDIOS_REG0 ((uint32_t)0x00000000U) +#define MDIOS_REG1 ((uint32_t)0x00000001U) +#define MDIOS_REG2 ((uint32_t)0x00000002U) +#define MDIOS_REG3 ((uint32_t)0x00000003U) +#define MDIOS_REG4 ((uint32_t)0x00000004U) +#define MDIOS_REG5 ((uint32_t)0x00000005U) +#define MDIOS_REG6 ((uint32_t)0x00000006U) +#define MDIOS_REG7 ((uint32_t)0x00000007U) +#define MDIOS_REG8 ((uint32_t)0x00000008U) +#define MDIOS_REG9 ((uint32_t)0x00000009U) +#define MDIOS_REG10 ((uint32_t)0x0000000AU) +#define MDIOS_REG11 ((uint32_t)0x0000000BU) +#define MDIOS_REG12 ((uint32_t)0x0000000CU) +#define MDIOS_REG13 ((uint32_t)0x0000000DU) +#define MDIOS_REG14 ((uint32_t)0x0000000EU) +#define MDIOS_REG15 ((uint32_t)0x0000000FU) +#define MDIOS_REG16 ((uint32_t)0x00000010U) +#define MDIOS_REG17 ((uint32_t)0x00000011U) +#define MDIOS_REG18 ((uint32_t)0x00000012U) +#define MDIOS_REG19 ((uint32_t)0x00000013U) +#define MDIOS_REG20 ((uint32_t)0x00000014U) +#define MDIOS_REG21 ((uint32_t)0x00000015U) +#define MDIOS_REG22 ((uint32_t)0x00000016U) +#define MDIOS_REG23 ((uint32_t)0x00000017U) +#define MDIOS_REG24 ((uint32_t)0x00000018U) +#define MDIOS_REG25 ((uint32_t)0x00000019U) +#define MDIOS_REG26 ((uint32_t)0x0000001AU) +#define MDIOS_REG27 ((uint32_t)0x0000001BU) +#define MDIOS_REG28 ((uint32_t)0x0000001CU) +#define MDIOS_REG29 ((uint32_t)0x0000001DU) +#define MDIOS_REG30 ((uint32_t)0x0000001EU) +#define MDIOS_REG31 ((uint32_t)0x0000001FU) +/** + * @} + */ + +/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags + * @{ + */ +#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U) +#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U) +#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U) +#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U) +#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U) +#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U) +#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U) +#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U) +#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U) +#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U) +#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U) +#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U) +#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U) +#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U) +#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U) +#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U) +#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U) +#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U) +#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U) +#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U) +#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U) +#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U) +#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U) +#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U) +#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U) +#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U) +#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U) +#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U) +#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U) +#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U) +#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U) +#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U) +#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU) +/** + * @} + */ + +/** @defgroup MDIOS_Interrupt_sources Interrupt Sources + * @{ + */ +#define MDIOS_IT_WRITE MDIOS_CR_WRIE +#define MDIOS_IT_READ MDIOS_CR_RDIE +#define MDIOS_IT_ERROR MDIOS_CR_EIE +/** + * @} + */ + +/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags + * @{ + */ +#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF +#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF +#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF +/** + * @} + */ + + /** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line + * @{ + */ +#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x01000000) /* !< EXTI Line 24 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros + * @{ + */ + +/** @brief Reset MDIOS handle state + * @param __HANDLE__: MDIOS handle. + * @retval None + */ +#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET) + +/** + * @brief Enable/Disable the MDIOS peripheral. + * @param __HANDLE__: specifies the MDIOS handle. + * @retval None + */ +#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN) +#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN) + + +/** + * @brief Enable the MDIOS device interrupt. + * @param __HANDLE__: specifies the MDIOS handle. + * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_IT_WRITE: Register write interrupt + * @arg MDIOS_IT_READ: Register read interrupt + * @arg MDIOS_IT_ERROR: Error interrupt + * @retval None + */ +#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the MDIOS device interrupt. + * @param __HANDLE__: specifies the MDIOS handle. + * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_IT_WRITE: Register write interrupt + * @arg MDIOS_IT_READ: Register read interrupt + * @arg MDIOS_IT_ERROR: Error interrupt + * @retval None + */ +#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** @brief Set MDIOS slave get write register flag + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__: specifies the write register flag + * @retval The state of write flag + */ +#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__)) + +/** @brief MDIOS slave get read register flag + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__: specifies the read register flag + * @retval The state of read flag + */ +#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__)) + +/** @brief MDIOS slave get interrupt + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__ : specifies the Error flag. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt + * @arg MDIOS_START_ERROR_FLAG: Register read interrupt + * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt + * @retval The state of the error flag + */ +#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) + +/** @brief MDIOS slave clear interrupt + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__ : specifies the Error flag. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt + * @arg MDIOS_START_ERROR_FLAG: Register read interrupt + * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt + * @retval none + */ +#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__) + +/** + * @brief Checks whether the specified MDIOS interrupt is set or not. + * @param __HANDLE__: specifies the MDIOS handle. + * @param __INTERRUPT__ : specifies the MDIOS interrupt sources + * This parameter can be one or a combination of the following values: + * @arg MDIOS_IT_WRITE: Register write interrupt + * @arg MDIOS_IT_READ: Register read interrupt + * @arg MDIOS_IT_ERROR: Error interrupt + * @retval The state of the interrupt source + */ +#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @brief Enable the MDIOS WAKEUP Exti Line. + * @retval None. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT() (EXTI->IMR |= (MDIOS_WAKEUP_EXTI_LINE)) + +/** + * @brief Disable the MDIOS WAKEUP Exti Line. + * @retval None. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(MDIOS_WAKEUP_EXTI_LINE)) + +/** + * @brief Enable event on MDIOS WAKEUP Exti Line. + * @retval None. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_EVENT() (EXTI->EMR |= (MDIOS_WAKEUP_EXTI_LINE)) + +/** + * @brief Disable event on MDIOS WAKEUP Exti Line. + * @retval None. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(MDIOS_WAKEUP_EXTI_LINE)) + +/** + * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not. + * @retval EXTI MDIOS WAKEUP Line Status. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() (EXTI->PR & (MDIOS_WAKEUP_EXTI_LINE)) + +/** + * @brief Clear the MDIOS WAKEUP Exti flag. + * @retval None. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG() (EXTI->PR = (MDIOS_WAKEUP_EXTI_LINE)) + +/** + * @brief Enables rising edge trigger to the MDIOS External interrupt line. + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE + +/** + * @brief Disables the rising edge trigger to the MDIOS External interrupt line. + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) + +/** + * @brief Enables falling edge trigger to the MDIOS External interrupt line. + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (MDIOS_WAKEUP_EXTI_LINE) + +/** + * @brief Disables falling edge trigger to the MDIOS External interrupt line. + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) + +/** + * @brief Enables rising/falling edge trigger to the MDIOS External interrupt line. + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE;\ + EXTI->FTSR |= MDIOS_WAKEUP_EXTI_LINE + +/** + * @brief Disables rising/falling edge trigger to the MDIOS External interrupt line. + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE);\ + EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (MDIOS_WAKEUP_EXTI_LINE)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions + * @{ + */ + +/** @addtogroup MDIOS_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios); +HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios); +/** + * @} + */ + +/** @addtogroup MDIOS_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data); +HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData); + +uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios); +HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); +HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); + +HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios); +/** + * @} + */ + +/** @addtogroup MDIOS_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios); +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Types MDIOS Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Variables MDIOS Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Constants MDIOS Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Macros MDIOS Private Macros + * @{ + */ + +#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32) + +#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32) + +#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \ + ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE)) + + /** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Functions MDIOS Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* MDIOS */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_MDIOS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c index 61a20c3fda6..f7622df7e9c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -55,7 +55,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -316,6 +316,7 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) { __IO uint32_t data = 0; + __IO uint32_t data1 = 0; uint32_t deviceAddress = 0; /* Process Locked */ @@ -324,7 +325,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Identify the device address */ @@ -335,16 +336,33 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN /* Send Read ID command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; + __DSB(); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + + /* Read the electronic signature from NAND flash */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + { + data = *(__IO uint32_t *)deviceAddress; + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); + pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + } + else + { + data = *(__IO uint32_t *)deviceAddress; + data1 = *((__IO uint32_t *)deviceAddress + 4); + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); + pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + } - /* Read the electronic signature from NAND flash */ - data = *(__IO uint32_t *)deviceAddress; - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -395,7 +413,104 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) } /** - * @brief Read Page(s) from NAND memory block + * @brief Read Page(s) from NAND memory block (8-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer : pointer to destination read buffer + * @param NumPageToRead : number of pages to read from block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +{ + __IO uint32_t index = 0; + uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) + { + /* update the buffer size */ + size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + + /* for 512 and 1 GB devices, 4th cycle is required */ + if(hnand->Info.BlockNbr >= 1024) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + /* Get Data into Buffer */ + for(; index < size; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; + } + } + else + { + /* Get Data into Buffer */ + for(; index < size; index++) + { + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; + } + } + + /* Increment read pages number */ + numPagesRead++; + + /* Decrement pages to read */ + NumPageToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; + +} + +/** + * @brief Read Page(s) from NAND memory block (16-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -403,7 +518,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param NumPageToRead : number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) { __IO uint32_t index = 0; uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; @@ -434,24 +549,30 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType /* Send read page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; - - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + __DSB(); } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); /* Get Data into Buffer */ - for(index = 0; index < size; index++) + for(; index < size; index++) { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; } /* Increment read pages number */ @@ -462,7 +583,6 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType /* Increment the NAND address */ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); - } /* Update the NAND controller state */ @@ -472,11 +592,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType __HAL_UNLOCK(hnand); return HAL_OK; - } /** - * @brief Write Page(s) to NAND memory block + * @brief Write Page(s) to NAND memory block (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -484,7 +603,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType * @param NumPageToWrite : number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) { __IO uint32_t index = 0; uint32_t tickstart = 0; @@ -516,11 +635,130 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp /* Send write page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + + /* for 512 and 1 GB devices, 4th cycle is required */ + if(hnand->Info.BlockNbr >= 1024) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + __DSB(); + } + + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + __DSB(); + } + } + else + { + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numPagesWritten++; + + /* Decrement pages to write */ + NumPageToWrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8)); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Page(s) to NAND memory block (16-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer : pointer to source buffer to write + * @param NumPageToWrite : number of pages to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize)))) + { + /* update the buffer size */ + size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); __DSB(); @@ -532,13 +770,14 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp } /* Write data to memory */ - for(index = 0; index < size; index++) + for(; index < size; index++) { - *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; __DSB(); } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) @@ -550,7 +789,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp { return HAL_TIMEOUT; } - } + } /* Increment written pages number */ numPagesWritten++; @@ -572,7 +811,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp } /** - * @brief Read Spare area(s) from NAND memory + * @brief Read Spare area(s) from NAND memory (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -580,7 +819,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp * @param NumSpareAreaToRead: Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { __IO uint32_t index = 0; uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; @@ -605,29 +844,34 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres /* Spare area(s) read loop */ while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) - { - + { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); /* Send read spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; - - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); /* Get Data into Buffer */ - for(index = 0; index < size; index++) + for(; index < size; index++) { *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; } @@ -652,7 +896,92 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres } /** - * @brief Write Spare area(s) to NAND memory + * @brief Read Spare area(s) from NAND memory (16-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer: pointer to source buffer to write + * @param NumSpareAreaToRead: Number of spare area to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + __IO uint32_t index = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Spare area(s) read loop */ + while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) + { + /* update the buffer size */ + size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); + + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + + /* for 512 and 1 GB devices, 4th cycle is required */ + if(hnand->Info.BlockNbr >= 1024) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + /* Get Data into Buffer */ + for(; index < size; index++) + { + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; + } + + /* Increment read spare areas number */ + numSpareAreaRead++; + + /* Decrement spare areas to read */ + NumSpareAreaToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -660,7 +989,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres * @param NumSpareAreaTowrite : number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { __IO uint32_t index = 0; uint32_t tickstart = 0; @@ -686,17 +1015,21 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /* Spare area(s) write loop */ while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) - { + { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); /* Send write Spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; - - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); __DSB(); /* for 512 and 1 GB devices, 4th cycle is required */ @@ -707,7 +1040,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre } /* Write data to memory */ - for(index = 0; index < size; index++) + for(; index < size; index++) { *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; __DSB(); @@ -743,7 +1076,107 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /* Process unlocked */ __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (16-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer : pointer to source buffer to write + * @param NumSpareAreaTowrite : number of spare areas to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the FMC_NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Spare area(s) write loop */ + while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) + { + /* update the buffer size */ + size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); + + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + /* for 512 and 1 GB devices, 4th cycle is required */ + if(hnand->Info.BlockNbr >= 1024) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); + __DSB(); + } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numSpareAreaWritten++; + + /* Decrement spare areas to write */ + NumSpareAreaTowrite--; + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + return HAL_OK; } @@ -775,9 +1208,11 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy /* Send Erase block command sequence */ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; - + __DSB(); *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h index 9dd35ba3803..715d52d6336 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,10 +65,10 @@ */ typedef enum { - HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ - HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ - HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ - HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ + HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ + HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ + HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ + HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ }HAL_NAND_StateTypeDef; /** @@ -179,10 +179,15 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); @@ -223,33 +228,33 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** @defgroup NAND_Private_Constants NAND Private Constants * @{ */ -#define NAND_DEVICE ((uint32_t)0x80000000) -#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000) +#define NAND_DEVICE ((uint32_t)0x80000000U) +#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) +#define NAND_CMD_AREA_A ((uint8_t)0x00U) +#define NAND_CMD_AREA_B ((uint8_t)0x01U) +#define NAND_CMD_AREA_C ((uint8_t)0x50U) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) +#define NAND_CMD_WRITE0 ((uint8_t)0x80U) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) +#define NAND_CMD_ERASE0 ((uint8_t)0x60U) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) +#define NAND_CMD_READID ((uint8_t)0x90U) +#define NAND_CMD_STATUS ((uint8_t)0x70U) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) +#define NAND_CMD_RESET ((uint8_t)0xFFU) /* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) -#define NAND_BUSY ((uint32_t)0x00000000) -#define NAND_ERROR ((uint32_t)0x00000001) -#define NAND_READY ((uint32_t)0x00000040) +#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) +#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) +#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) +#define NAND_BUSY ((uint32_t)0x00000000U) +#define NAND_ERROR ((uint32_t)0x00000001U) +#define NAND_READY ((uint32_t)0x00000040U) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c index d540025d3f2..afc745d3588 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -55,7 +55,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -137,6 +137,16 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +/** @defgroup NOR_Private_Variables NOR Private Variables + * @{ + */ + +static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; + +/** + * @} + */ + /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup NOR_Exported_Functions NOR Exported Functions @@ -194,6 +204,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); + /* Initialize NOR Memory Data Width*/ + if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) + { + uwNORMemoryDataWidth = NOR_MEMORY_8B; + } + else + { + uwNORMemoryDataWidth = NOR_MEMORY_16B; + } + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -333,15 +353,15 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I hnor->State = HAL_NOR_STATE_BUSY; /* Send read ID command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR); + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -443,9 +463,9 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint hnor->State = HAL_NOR_STATE_BUSY; /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); /* Read the data */ *pData = *(__IO uint32_t *)(uint32_t)pAddress; @@ -502,9 +522,9 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u hnor->State = HAL_NOR_STATE_BUSY; /* Send program data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); /* Write the data */ NOR_WRITE(pAddress, *pData); @@ -562,9 +582,9 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress hnor->State = HAL_NOR_STATE_BUSY; /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); /* Read buffer */ while( uwBufferSize > 0) @@ -634,12 +654,12 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr lastloadedaddress = (uint32_t)(uwAddress); /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); /* Write Buffer Load Command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1)); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1)); /* Load Data into NOR Buffer */ while(p_currentaddress <= p_endaddress) @@ -707,11 +727,11 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd hnor->State = HAL_NOR_STATE_BUSY; /* Send block erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); /* Check the NOR memory status and update the controller state */ @@ -766,12 +786,12 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) hnor->State = HAL_NOR_STATE_BUSY; /* Send NOR chip erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -824,13 +844,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR hnor->State = HAL_NOR_STATE_BUSY; /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS); + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h index 617bcd402d5..699ccac6c5e 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,11 +65,11 @@ */ typedef enum { - HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ - HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ - HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ - HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ + HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ + HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ + HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ + HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ + HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ }HAL_NOR_StateTypeDef; /** @@ -77,7 +77,7 @@ typedef enum */ typedef enum { - HAL_NOR_STATUS_SUCCESS = 0, + HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT @@ -224,29 +224,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @{ */ /* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) +#define MC_ADDRESS ((uint16_t)0x0000U) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x61) -#define CFI2_ADDRESS ((uint16_t)0x62) -#define CFI3_ADDRESS ((uint16_t)0x63) -#define CFI4_ADDRESS ((uint16_t)0x64) +#define CFI1_ADDRESS ((uint16_t)0x61U) +#define CFI2_ADDRESS ((uint16_t)0x62U) +#define CFI3_ADDRESS ((uint16_t)0x63U) +#define CFI4_ADDRESS ((uint16_t)0x64U) /* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFF) +#define NOR_TMEOUT ((uint16_t)0xFFFFU) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) +#define NOR_MEMORY_8B ((uint8_t)0x0U) +#define NOR_MEMORY_16B ((uint8_t)0x1U) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) +#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) +#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) +#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) +#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) /** * @} */ @@ -263,7 +263,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @retval NOR shifted address value */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)? \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c index 493a70779ee..148e49a38c0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -45,7 +45,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -316,8 +316,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0; uint32_t fifoemptymsk = 0, temp = 0; - USB_OTG_EPTypeDef *ep; - + USB_OTG_EPTypeDef *ep = NULL; + uint32_t hclk = 200000000; + /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) { @@ -527,7 +528,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* setup EP0 to receive SETUP packets */ USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } @@ -547,7 +548,74 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { hpcd->Init.speed = USB_OTG_SPEED_FULL; hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + if((hclk >= 14200000)&&(hclk < 15000000)) + { + /* hclk Clock Range between 14.2-15 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 15000000)&&(hclk < 16000000)) + { + /* hclk Clock Range between 15-16 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 16000000)&&(hclk < 17200000)) + { + /* hclk Clock Range between 16-17.2 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 17200000)&&(hclk < 18500000)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 18500000)&&(hclk < 20000000)) + { + /* hclk Clock Range between 18.5-20 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 20000000)&&(hclk < 21800000)) + { + /* hclk Clock Range between 20-21.8 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 21800000)&&(hclk < 24000000)) + { + /* hclk Clock Range between 21.8-24 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 24000000)&&(hclk < 27700000)) + { + /* hclk Clock Range between 24-27.7 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else if((hclk >= 27700000)&&(hclk < 32000000)) + { + /* hclk Clock Range between 27.7-32 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); + } + + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); + } } HAL_PCD_ResetCallback(hpcd); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h index e87542c4266..71da01c663b 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,20 +64,20 @@ */ typedef enum { - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 + HAL_PCD_STATE_RESET = 0x00U, + HAL_PCD_STATE_READY = 0x01U, + HAL_PCD_STATE_ERROR = 0x02U, + HAL_PCD_STATE_BUSY = 0x03U, + HAL_PCD_STATE_TIMEOUT = 0x04U } PCD_StateTypeDef; /* Device LPM suspend state */ typedef enum { - LPM_L0 = 0x00, /* on */ - LPM_L1 = 0x01, /* LPM L1 sleep */ - LPM_L2 = 0x02, /* suspend */ - LPM_L3 = 0x03, /* off */ + LPM_L0 = 0x00U, /* on */ + LPM_L1 = 0x01U, /* LPM L1 sleep */ + LPM_L2 = 0x02U, /* suspend */ + LPM_L3 = 0x03U, /* off */ }PCD_LPM_StateTypeDef; typedef USB_OTG_GlobalTypeDef PCD_TypeDef; @@ -118,9 +118,9 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_HIGH 0 -#define PCD_SPEED_HIGH_IN_FULL 1 -#define PCD_SPEED_FULL 2 +#define PCD_SPEED_HIGH 0U +#define PCD_SPEED_HIGH_IN_FULL 1U +#define PCD_SPEED_FULL 2U /** * @} */ @@ -128,8 +128,8 @@ typedef struct /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ -#define PCD_PHY_ULPI 1 -#define PCD_PHY_EMBEDDED 2 +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U /** * @} */ @@ -138,10 +138,10 @@ typedef struct * @{ */ #ifndef USBD_HS_TRDT_VALUE - #define USBD_HS_TRDT_VALUE 9 + #define USBD_HS_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ #ifndef USBD_FS_TRDT_VALUE - #define USBD_FS_TRDT_VALUE 5 + #define USBD_FS_TRDT_VALUE 5U #endif /* USBD_HS_TRDT_VALUE */ /** @@ -172,16 +172,16 @@ typedef struct #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) -#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) +#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) +#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) +#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) -#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ +#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c index 92d08f0ad46..c7300a023fd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,7 @@ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions * @{ */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h index 93a6c18a1d9..609a9a70d7c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -56,14 +56,14 @@ /* Exported types ------------------------------------------------------------*/ typedef enum { - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ + PCD_LPM_L0_ACTIVE = 0x00U, /* on */ + PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */ }PCD_LPM_MsgTypeDef; /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions * @{ */ /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c index 92d901ebb0b..9d59c0124f2 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,10 +63,10 @@ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ -#define PVD_MODE_IT ((uint32_t)0x00010000) -#define PVD_MODE_EVT ((uint32_t)0x00020000) -#define PVD_RISING_EDGE ((uint32_t)0x00000001) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) +#define PVD_MODE_IT ((uint32_t)0x00010000U) +#define PVD_MODE_EVT ((uint32_t)0x00020000U) +#define PVD_RISING_EDGE ((uint32_t)0x00000001U) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h index b210d51b961..f5bc1d1f178 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,13 +101,13 @@ typedef struct /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -115,7 +115,7 @@ typedef struct /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS /** * @} @@ -124,8 +124,8 @@ typedef struct /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /** * @} */ @@ -133,8 +133,8 @@ typedef struct /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /** * @} */ @@ -181,7 +181,7 @@ typedef struct * @retval None */ #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ @@ -364,7 +364,7 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line * @{ */ -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** * @} */ @@ -380,8 +380,6 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters * @{ */ -#define IS_PWR_WAKEUP_POLARITY(POLARITY) (((POLARITY) == PWR_POLARITY_RISINGEDGE) || \ - ((POLARITY) == PWR_POLARITY_FALLINGEDGE)) #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c index a4cf3ca0543..78a046f2e7c 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -156,6 +156,10 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) /* Enable Backup regulator */ PWR->CSR1 |= PWR_CSR1_BRE; + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; /* Get tick */ tickstart = HAL_GetTick(); @@ -181,6 +185,10 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) /* Disable Backup regulator */ PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; /* Get tick */ tickstart = HAL_GetTick(); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h index 0984b18b1f5..1fa56efa0bf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -99,7 +99,7 @@ */ #define PWR_FLAG_ODRDY PWR_CSR1_ODRDY #define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY +#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c index 312936d2182..165faea3fea 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief QSPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI). @@ -113,8 +113,20 @@ ================================================== [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo. + (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + flushes the fifo : + (++) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when + the transfer complete bi is set. + + *** Control functions *** + ========================= + [..] (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver. + (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. + (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. + (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold *** Workarounds linked to Silicon Limitation *** ==================================================== @@ -126,7 +138,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -171,7 +183,7 @@ /** @addtogroup QSPI_Private_Constants * @{ */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8)); /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); - - if(status == HAL_OK) + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + + if(status == HAL_OK) { /* Configure QSPI Clock Prescaler and Sample Shift */ @@ -404,13 +418,11 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { __IO uint32_t *data_reg; - uint32_t flag = 0, itsource = 0; + uint32_t flag = READ_REG(hqspi->Instance->SR); + uint32_t itsource = READ_REG(hqspi->Instance->CR); - /* QSPI FIFO Threshold interrupt occurred ----------------------------------*/ - flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT); - itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT); - - if((flag != RESET) && (itsource != RESET)) + /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ + if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET)) { data_reg = &hqspi->Instance->DR; @@ -428,6 +440,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) else { /* No more data available for the transfer */ + /* Disable the QSPI FIFO Threshold Interrupt */ + __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); break; } } @@ -446,6 +460,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) else { /* All data have been received for the transfer */ + /* Disable the QSPI FIFO Threshold Interrupt */ + __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); break; } } @@ -456,13 +472,10 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC); - itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC); - - if((flag != RESET) && (itsource != RESET)) + else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET)) { /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); @@ -470,60 +483,106 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - /* Clear Busy bit */ - HAL_QSPI_Abort(hqspi); + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + { + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hqspi->hdma); + } + +#if defined(QSPI1_V1_0) +/* Clear Busy bit */ + HAL_QSPI_Abort_IT(hqspi); +#endif + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + /* TX Complete callback */ HAL_QSPI_TxCpltCallback(hqspi); } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - data_reg = &hqspi->Instance->DR; - while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) { - if (hqspi->RxXferCount > 0) - { - /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; - hqspi->RxXferCount--; - } - else + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hqspi->hdma); + } + else + { + data_reg = &hqspi->Instance->DR; + while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0) { - /* All data have been received for the transfer */ - break; + if (hqspi->RxXferCount > 0) + { + /* Read the last data received in the FIFO until it is empty */ + *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + hqspi->RxXferCount--; + } + else + { + /* All data have been received for the transfer */ + break; + } } } - +#if defined(QSPI1_V1_0) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - HAL_QSPI_Abort(hqspi); + HAL_QSPI_Abort_IT(hqspi); +#endif /* QSPI_V1_0*/ + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + /* RX Complete callback */ HAL_QSPI_RxCpltCallback(hqspi); } else if(hqspi->State == HAL_QSPI_STATE_BUSY) { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + /* Command Complete callback */ HAL_QSPI_CmdCpltCallback(hqspi); } + else if(hqspi->State == HAL_QSPI_STATE_ABORT) + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; + if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) + { + /* Abort called by the user */ + + /* Abort Complete callback */ + HAL_QSPI_AbortCpltCallback(hqspi); + } + else + { + /* Abort due to an error (eg : DMA error) */ + + /* Error callback */ + HAL_QSPI_ErrorCallback(hqspi); + } + } } /* QSPI Status Match interrupt occurred ------------------------------------*/ - flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM); - itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM); - - if((flag != RESET) && (itsource != RESET)) + else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET)) { /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); /* Check if the automatic poll mode stop is activated */ if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0) { - /* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TE); + /* Disable the QSPI Transfer Error and Status Match Interrupts */ + __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -534,13 +593,10 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE); - itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE); - - if((flag != RESET) && (itsource != RESET)) + else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET)) { /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE); + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); /* Disable all the QSPI Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); @@ -548,21 +604,30 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_ERROR; - - /* Error callback */ - HAL_QSPI_ErrorCallback(hqspi); + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + { + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Disable the DMA channel */ + hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; + HAL_DMA_Abort_IT(hqspi->hdma); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ + HAL_QSPI_ErrorCallback(hqspi); + } } - /* QSPI Time out interrupt occurred -----------------------------------------*/ - flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO); - itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO); - - if((flag != RESET) && (itsource != RESET)) + /* QSPI Timeout interrupt occurred -----------------------------------------*/ + else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET)) { /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); /* Time out callback */ HAL_QSPI_TimeOutCallback(hqspi); @@ -580,6 +645,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -609,8 +675,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /* Process locked */ __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) + + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; @@ -618,7 +684,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe hqspi->State = HAL_QSPI_STATE_BUSY; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout); + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); if (status == HAL_OK) { @@ -629,11 +695,9 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe { /* When there is no data phase, the transfer start as soon as the configuration is done so wait until TC flag is set to go back in idle state */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); @@ -671,6 +735,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) { HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -701,7 +766,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /* Process locked */ __HAL_LOCK(hqspi); - if(hqspi->State == HAL_QSPI_STATE_READY) + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; @@ -709,36 +774,52 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp hqspi->State = HAL_QSPI_STATE_BUSY; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); if (status == HAL_OK) { if (cmd->DataMode == QSPI_DATA_NONE) { - /* When there is no data phase, the transfer start as soon as the configuration is done - so activate TC and TE interrupts */ - /* Enable the QSPI Transfer Error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); } /* Call the configuration function */ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - if (cmd->DataMode != QSPI_DATA_NONE) + if (cmd->DataMode == QSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so activate TC and TE interrupts */ + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI Transfer Error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); + } + else { /* Update QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } else { status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - /* Return function status */ return status; } @@ -753,18 +834,19 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); __IO uint32_t *data_reg = &hqspi->Instance->DR; /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_READY) { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; @@ -779,9 +861,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u while(hqspi->TxXferCount > 0) { /* Wait until FT flag is set to send data */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK) + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); + + if (status != HAL_OK) { - status = HAL_TIMEOUT; break; } @@ -792,17 +875,17 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u if (status == HAL_OK) { /* Wait until TC flag is set to go back in idle state */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); +#if defined(QSPI1_V1_0) /* Clear Busy bit */ status = HAL_QSPI_Abort(hqspi); +#endif /* QSPI_V1_0 */ } } @@ -811,6 +894,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u } else { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; } } @@ -837,6 +921,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); uint32_t addr_reg = READ_REG(hqspi->Instance->AR); __IO uint32_t *data_reg = &hqspi->Instance->DR; @@ -845,10 +930,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui if(hqspi->State == HAL_QSPI_STATE_READY) { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; if(pData != NULL ) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; @@ -866,9 +950,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui while(hqspi->RxXferCount > 0) { /* Wait until FT or TC flag is set to read received data */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, Timeout) != HAL_OK) + status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout); + + if (status != HAL_OK) { - status = HAL_TIMEOUT; break; } @@ -879,17 +964,17 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui if (status == HAL_OK) { /* Wait until TC flag is set to go back in idle state */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - status = HAL_QSPI_Abort(hqspi); +#if defined(QSPI1_V1_0) + /* Workaround - Extra data written in the FIFO at the end of a read transfer */ + status = HAL_QSPI_Abort(hqspi); +#endif /* QSPI_V1_0 */ } } @@ -898,6 +983,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui } else { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; } } @@ -928,10 +1014,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData if(hqspi->State == HAL_QSPI_STATE_READY) { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; if(pData != NULL ) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; @@ -943,22 +1028,32 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Configure QSPI: CCR register with functional as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); } else { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } } else { status = HAL_BUSY; - } - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } return status; } @@ -980,10 +1075,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) if(hqspi->State == HAL_QSPI_STATE_READY) { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; @@ -998,21 +1093,31 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); } else { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } } else { status = HAL_BUSY; - } - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } return status; } @@ -1022,28 +1127,79 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) * @param hqspi: QSPI handle * @param pData: pointer to data buffer * @note This function is used only in Indirect Write Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t *tmp; + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { + /* Clear the error code */ + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + /* Configure counters of the handle */ + if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + hqspi->TxXferCount = data_size; + } + else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) + { + if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + else + { + hqspi->TxXferCount = (data_size >> 1); + } + } + else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) + { + if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + else + { + hqspi->TxXferCount = (data_size >> 2); + } + } + + if (status == HAL_OK) + { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + + /* Configure size and pointer of the handle */ + hqspi->TxXferSize = hqspi->TxXferCount; hqspi->pTxBuffPtr = pData; /* Configure QSPI: CCR register with functional mode as indirect write */ @@ -1058,6 +1214,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; + /* Clear the DMA abort callback */ + hqspi->hdma->XferAbortCallback = NULL; + /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); @@ -1065,22 +1224,34 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /* Enable the QSPI transmit DMA Channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); - + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } + } else { - status = HAL_OK; + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } } else { status = HAL_BUSY; - } - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } return status; } @@ -1090,6 +1261,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat * @param hqspi: QSPI handle * @param pData: pointer to data buffer. * @note This function is used only in Indirect Read Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) @@ -1097,63 +1272,123 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData HAL_StatusTypeDef status = HAL_OK; uint32_t *tmp; uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->pRxBuffPtr = pData; - - /* Set the QSPI DMA transfer complete callback */ - hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; - - /* Set the QSPI DMA Half transfer complete callback */ - hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; - - /* Set the DMA error callback */ - hqspi->hdma->XferErrorCallback = QSPI_DMAError; + /* Configure counters of the handle */ + if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + hqspi->RxXferCount = data_size; + } + else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) + { + if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + else + { + hqspi->RxXferCount = (data_size >> 1); + } + } + else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) + { + if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + else + { + hqspi->RxXferCount = (data_size >> 2); + } + } - /* Configure the direction of the DMA */ - hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - - /* Enable the DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + if (status == HAL_OK) + { + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + + /* Configure size and pointer of the handle */ + hqspi->RxXferSize = hqspi->RxXferCount; + hqspi->pRxBuffPtr = pData; + + /* Set the QSPI DMA transfer complete callback */ + hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; + + /* Set the QSPI DMA Half transfer complete callback */ + hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; + + /* Set the DMA error callback */ + hqspi->hdma->XferErrorCallback = QSPI_DMAError; + + /* Clear the DMA abort callback */ + hqspi->hdma->XferAbortCallback = NULL; + + /* Configure the direction of the DMA */ + hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); + + /* Enable the DMA Channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); + + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } } else { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } } else { status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - + return status; } @@ -1169,6 +1404,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -1212,7 +1448,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout); + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); if (status == HAL_OK) { @@ -1228,18 +1464,16 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /* Configure QSPI: CR register with Match mode and Automatic stop enabled (otherwise there will be an infinite loop in blocking mode) */ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), - (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); + (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); /* Call the configuration function */ cmd->NbData = cfg->StatusBytesSize; QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); /* Wait until SM flag is set to go back in idle state */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); + + if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); @@ -1260,16 +1494,17 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy } /** -* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. -* @param hqspi: QSPI handle -* @param cmd: structure that contains the command configuration information. -* @param cfg: structure that contains the polling configuration information. -* @note This function is used only in Automatic Polling Mode -* @retval HAL status -*/ + * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. + * @param hqspi: QSPI handle + * @param cmd: structure that contains the command configuration information. + * @param cfg: structure that contains the polling configuration information. + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) { HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -1313,7 +1548,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); if (status == HAL_OK) { @@ -1328,27 +1563,36 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /* Configure QSPI: CR register with Match mode and Automatic stop mode */ MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), - (cfg->MatchMode | cfg->AutomaticStop)); + (cfg->MatchMode | cfg->AutomaticStop)); /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); - /* Enable the QSPI Transfer Error and status match Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); - /* Call the configuration function */ cmd->NbData = cfg->StatusBytesSize; QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI Transfer Error and status match Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); + + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } } else { - status = HAL_BUSY; + status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); } - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - /* Return function status */ return status; } @@ -1364,6 +1608,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) { HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -1404,33 +1649,34 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); - - if (status == HAL_OK) - { - /* Configure QSPI: CR register with time out counter enable */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + /* Configure QSPI: CR register with timeout counter enable */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) - { - assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - - /* Configure QSPI: LPTR register with the low-power time out value */ - WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); - - /* Enable the QSPI TimeOut Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); - } + { + assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); + + /* Configure QSPI: LPTR register with the low-power timeout value */ + WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); - /* Call the configuration function */ - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); - + /* Enable the QSPI TimeOut Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); + } + + /* Call the configuration function */ + QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); } } else { - status = HAL_BUSY; - + status = HAL_BUSY; } /* Process unlocked */ @@ -1456,7 +1702,22 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) } /** - * @brief Command completed callbacks. + * @brief Abort completed callback. + * @param hqspi: QSPI handle + * @retval None + */ +__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_QSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. * @param hqspi: QSPI handle * @retval None */ @@ -1597,12 +1858,13 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) */ /** - * @brief Return the QSPI state. + * @brief Return the QSPI handle state. * @param hqspi: QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) { + /* Return QSPI handle state */ return hqspi->State; } @@ -1623,25 +1885,93 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check if the state is in one of the busy states */ + if ((hqspi->State & 0x2) != 0) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + { + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Abort DMA channel */ + status = HAL_DMA_Abort(hqspi->hdma); + if(status != HAL_OK) + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + } + } + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - /* Wait until TC flag is set to go back in idle state */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK) - { - status = HAL_TIMEOUT; + if(status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } + + if (status == HAL_OK) + { + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } } - else + + return status; +} + +/** +* @brief Abort the current transmission (non-blocking function) +* @param hqspi: QSPI handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check if the state is in one of the busy states */ + if ((hqspi->State & 0x2) != 0) { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_ABORT; + + /* Disable all interrupts */ + __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + { + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Abort DMA channel */ + hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; + HAL_DMA_Abort_IT(hqspi->hdma); + } + else + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } } return status; @@ -1657,9 +1987,51 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) hqspi->Timeout = Timeout; } +/** @brief Set QSPI Fifo threshold. + * @param hqspi: QSPI handle. + * @param Threshold: Threshold of the Fifo (value between 1 and 16). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Synchronize init structure with new FIFO threshold value */ + hqspi->Init.FifoThreshold = Threshold; + + /* Configure QSPI FIFO Threshold */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES))); + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** @brief Get QSPI Fifo threshold. + * @param hqspi: QSPI handle. + * @retval Fifo threshold (value between 1 and 16) + */ +uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) +{ + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1); +} + /** -* @} -*/ + * @} + */ /* Private functions ---------------------------------------------------------*/ @@ -1673,31 +2045,8 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hqspi->RxXferCount = 0; - /* Wait for QSPI TC Flag */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK) - { - /* Time out Occurred */ - HAL_QSPI_ErrorCallback(hqspi); - } - else - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - HAL_DMA_Abort(hdma); - - /* Clear Transfer Complete bit */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - HAL_QSPI_Abort(hqspi); - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; - - HAL_QSPI_RxCpltCallback(hqspi); - } + /* Enable the QSPI transfer complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); } /** @@ -1710,31 +2059,8 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hqspi->TxXferCount = 0; - /* Wait for QSPI TC Flag */ - if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK) - { - /* Time out Occurred */ - HAL_QSPI_ErrorCallback(hqspi); - } - else - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - HAL_DMA_Abort(hdma); - - /* Clear Transfer Complete bit */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Clear Busy bit */ - HAL_QSPI_Abort(hqspi); - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; - - HAL_QSPI_TxCpltCallback(hqspi); - } + /* Enable the QSPI transfer complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); } /** @@ -1767,30 +2093,71 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) +{ + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* if DMA error is FIFO error ignore it */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + hqspi->RxXferCount = 0; + hqspi->TxXferCount = 0; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Abort the QSPI */ + HAL_QSPI_Abort_IT(hqspi); + } +} + +/** + * @brief DMA QSPI abort complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hqspi->RxXferCount = 0; hqspi->TxXferCount = 0; - hqspi->State = HAL_QSPI_STATE_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - HAL_QSPI_ErrorCallback(hqspi); + if(hqspi->State == HAL_QSPI_STATE_ABORT) + { + /* DMA Abort called by QSPI abort */ + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* DMA Abort called due to a transfer error interrupt */ + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ + HAL_QSPI_ErrorCallback(hqspi); + } } /** - * @brief This function wait a flag state until time out. + * @brief Wait for a flag state until timeout. * @param hqspi: QSPI handle * @param Flag: Flag checked * @param State: Value of the flag expected + * @param tickstart: Start tick value * @param Timeout: Duration of the time out * @retval HAL status */ -static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, - FlagStatus State, uint32_t Timeout) +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, + FlagStatus State, uint32_t tickstart, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - /* Wait until flag is in expected state */ while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) { @@ -1802,7 +2169,7 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp hqspi->State = HAL_QSPI_STATE_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - return HAL_TIMEOUT; + return HAL_ERROR; } } } @@ -1810,7 +2177,7 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp } /** - * @brief This function configures the communication registers + * @brief Configure the communication registers. * @param hqspi: QSPI handle * @param cmd: structure that contains the command configuration information * @param FunctionalMode: functional mode to configured @@ -1818,7 +2185,7 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode - * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode + * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode * @retval None */ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h index 6833b7f6c38..4ab01706a83 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -100,14 +100,15 @@ typedef struct */ typedef enum { - HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ - HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ - HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ - HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ - HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ - HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ - HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ - HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ + HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ + HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ + HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ + HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ + HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ + HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ + HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ + HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ + HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ }HAL_QSPI_StateTypeDef; /** @@ -207,10 +208,11 @@ typedef struct /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ /** * @} */ @@ -218,7 +220,7 @@ typedef struct /** @defgroup QSPI_SampleShifting QSPI Sample Shifting * @{ */ -#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!
      © COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -119,7 +119,6 @@ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ -const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -227,7 +226,7 @@ void HAL_RCC_DeInit(void) /* Reset PLLCFGR register */ CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U)); /* Reset PLLI2SCFGR register */ CLEAR_REG(RCC->PLLI2SCFGR); @@ -238,6 +237,9 @@ void HAL_RCC_DeInit(void) /* Disable all interrupts */ CLEAR_REG(RCC->CIR); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; } /** @@ -246,9 +248,15 @@ void HAL_RCC_DeInit(void) * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart = 0; @@ -271,21 +279,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ - __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); @@ -450,21 +443,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } - /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ @@ -530,11 +508,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ); + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ + (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ)))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); @@ -605,14 +583,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0; - + /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); - + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) @@ -626,161 +604,87 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { return HAL_ERROR; } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } } - /* Decreasing the CPU frequency */ - else + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration -------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } + return HAL_ERROR; } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } + return HAL_ERROR; } - /* HSI is selected as System Clock Source */ - else + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } + return HAL_ERROR; } - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - else + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } } - + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); @@ -790,7 +694,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { return HAL_ERROR; } - } + } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) @@ -806,6 +710,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -1005,15 +912,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /** * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; return SystemCoreClock; } @@ -1026,7 +930,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); } /** @@ -1038,7 +942,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h index 532d7efa5e7..283797b887f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -45,6 +45,10 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" + +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f7xx_hal_rcc_ex.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ @@ -60,31 +64,6 @@ * @{ */ -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 100 and Max_Data = 432 */ - - uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. - This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ - -}RCC_PLLInitTypeDef; - /** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ @@ -102,7 +81,7 @@ typedef struct uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ - uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ uint32_t LSIState; /*!< The new state of the LSI. @@ -146,11 +125,11 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /** * @} */ @@ -158,7 +137,7 @@ typedef struct /** @defgroup RCC_HSE_Config RCC HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_OFF ((uint32_t)0x00000000U) #define RCC_HSE_ON RCC_CR_HSEON #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /** @@ -168,7 +147,7 @@ typedef struct /** @defgroup RCC_LSE_Config RCC LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) +#define RCC_LSE_OFF ((uint32_t)0x00000000U) #define RCC_LSE_ON RCC_BDCR_LSEON #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /** @@ -178,8 +157,10 @@ typedef struct /** @defgroup RCC_HSI_Config RCC HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000) +#define RCC_HSI_OFF ((uint32_t)0x00000000U) #define RCC_HSI_ON RCC_CR_HSION + +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ /** * @} */ @@ -187,7 +168,7 @@ typedef struct /** @defgroup RCC_LSI_Config RCC LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000) +#define RCC_LSI_OFF ((uint32_t)0x00000000U) #define RCC_LSI_ON RCC_CSR_LSION /** * @} @@ -196,9 +177,9 @@ typedef struct /** @defgroup RCC_PLL_Config RCC PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000) -#define RCC_PLL_OFF ((uint32_t)0x00000001) -#define RCC_PLL_ON ((uint32_t)0x00000002) +#define RCC_PLL_NONE ((uint32_t)0x00000000U) +#define RCC_PLL_OFF ((uint32_t)0x00000001U) +#define RCC_PLL_ON ((uint32_t)0x00000002U) /** * @} */ @@ -206,10 +187,10 @@ typedef struct /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider * @{ */ -#define RCC_PLLP_DIV2 ((uint32_t)0x00000002) -#define RCC_PLLP_DIV4 ((uint32_t)0x00000004) -#define RCC_PLLP_DIV6 ((uint32_t)0x00000006) -#define RCC_PLLP_DIV8 ((uint32_t)0x00000008) +#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) +#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) +#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) +#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /** * @} */ @@ -226,10 +207,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type RCC System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /** * @} */ @@ -286,38 +267,38 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300) +#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) +#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) +#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) +#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) +#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) +#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) +#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) +#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) +#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) +#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) +#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) +#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) +#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) +#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) +#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) +#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) /** * @} */ @@ -327,8 +308,8 @@ typedef struct /** @defgroup RCC_MCO_Index RCC MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000) -#define RCC_MCO2 ((uint32_t)0x00000001) +#define RCC_MCO1 ((uint32_t)0x00000000U) +#define RCC_MCO2 ((uint32_t)0x00000001U) /** * @} */ @@ -336,7 +317,7 @@ typedef struct /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source * @{ */ -#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000) +#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 @@ -347,7 +328,7 @@ typedef struct /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source * @{ */ -#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 @@ -358,7 +339,7 @@ typedef struct /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler * @{ */ -#define RCC_MCODIV_1 ((uint32_t)0x00000000) +#define RCC_MCODIV_1 ((uint32_t)0x00000000U) #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) @@ -370,14 +351,14 @@ typedef struct /** @defgroup RCC_Interrupt RCC Interrupt * @{ */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) -#define RCC_IT_CSS ((uint8_t)0x80) +#define RCC_IT_LSIRDY ((uint8_t)0x01U) +#define RCC_IT_LSERDY ((uint8_t)0x02U) +#define RCC_IT_HSIRDY ((uint8_t)0x04U) +#define RCC_IT_HSERDY ((uint8_t)0x08U) +#define RCC_IT_PLLRDY ((uint8_t)0x10U) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) +#define RCC_IT_CSS ((uint8_t)0x80U) /** * @} */ @@ -392,24 +373,24 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C) +#define RCC_FLAG_HSIRDY ((uint8_t)0x21U) +#define RCC_FLAG_HSERDY ((uint8_t)0x31U) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) /* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSERDY ((uint8_t)0x41U) /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61U) +#define RCC_FLAG_BORRST ((uint8_t)0x79U) +#define RCC_FLAG_PINRST ((uint8_t)0x7AU) +#define RCC_FLAG_PORRST ((uint8_t)0x7BU) +#define RCC_FLAG_SFTRST ((uint8_t)0x7CU) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) /** * @} */ @@ -417,7 +398,7 @@ typedef struct /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations * @{ */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) +#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV @@ -442,7 +423,7 @@ typedef struct * @{ */ #define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ @@ -450,7 +431,7 @@ typedef struct } while(0) #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ @@ -472,7 +453,7 @@ typedef struct * @{ */ #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ @@ -480,7 +461,7 @@ typedef struct } while(0) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ @@ -501,7 +482,7 @@ typedef struct * @{ */ #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ @@ -563,11 +544,11 @@ typedef struct * @brief Force or release AHB peripheral reset. * @{ */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) -#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00) +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) /** @@ -578,11 +559,11 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) /** @@ -593,10 +574,10 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) /** @@ -714,7 +695,7 @@ typedef struct * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. + * (default is RCC_HSICALIBRATION_DEFAULT). */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM))) @@ -744,17 +725,20 @@ typedef struct * @{ */ /** - * @brief Macro to configure the External High Speed oscillator (__HSE__). + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this - * function. + * function. * @param __STATE__: specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after @@ -762,24 +746,27 @@ typedef struct * @arg RCC_HSE_ON: turn ON the HSE oscillator. * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - if((__STATE__) == RCC_HSE_ON) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ } while(0) /** * @} @@ -791,7 +778,7 @@ typedef struct /** * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * User should request a transition to LSE Off first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using @@ -809,12 +796,15 @@ typedef struct */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ if((__STATE__) == RCC_LSE_ON) \ { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ else if((__STATE__) == RCC_LSE_BYPASS) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ @@ -822,8 +812,8 @@ typedef struct } \ else \ { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0) /** @@ -892,39 +882,6 @@ typedef struct */ #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - - -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 100 and Max_Data = 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on - * the System clock frequency. - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\ - (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. @@ -1099,7 +1056,7 @@ typedef struct * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. @@ -1216,9 +1173,9 @@ void HAL_RCC_CSSCallback(void); * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias @@ -1232,7 +1189,7 @@ void HAL_RCC_CSSCallback(void); #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) -#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c index e4d439a0bf3..ab7b3303bd7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -114,12 +114,12 @@ * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source; in this case the Backup domain will be reset in * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. + * the backup registers) are set to their reset values. * * @retval HAL status */ @@ -200,38 +200,44 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - + /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); - + /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg0; - - /* If LSE is selected as RTC clock source, wait for LSE reactivation */ - if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY)) + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) { /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -245,8 +251,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } /*------------------------------------ TIM configuration --------------------------------------*/ @@ -406,12 +412,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*-------------------------------------- LTDC Configuration -----------------------------------*/ -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) { pllsaiused = 1; } -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { @@ -431,7 +438,39 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); } + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) @@ -598,7 +637,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); } -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { @@ -617,7 +656,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); } -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); @@ -648,7 +687,21 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg = 0; - /* Set all possible values for the extended clock type parameter------------*/ + /* Set all possible values for the extended clock type parameter------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ + RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; +#else PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ @@ -660,7 +713,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48; - +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /* Get the PLLI2S Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); @@ -733,9 +786,20 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the CK48 clock configuration -----------------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - /* Get the SDMMC clock configuration -----------------------------------------------*/ + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the DFSDM clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); @@ -830,6 +894,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = EXTERNAL_CLOCK_VALUE; break; } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ default : { break; @@ -897,6 +977,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = EXTERNAL_CLOCK_VALUE; break; } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ default : { break; @@ -906,6 +1002,324 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) return frequency; } + +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + return HAL_OK; +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h index 7714414b3cc..ada75ec9373 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +58,35 @@ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +}RCC_PLLInitTypeDef; /** * @brief PLLI2S Clock structure definition @@ -190,6 +219,17 @@ typedef struct uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ + + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ }RCC_PeriphCLKInitTypeDef; /** * @} @@ -203,33 +243,38 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection * @{ */ -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) -#if defined(STM32F746xx) || defined(STM32F756xx) -#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008) -#endif /* STM32F746xx || STM32F756xx */ -#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400) -#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800) -#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000) -#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000) -#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000) -#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000) -#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000) - +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) +#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) +#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) +#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) +#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) +#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) +#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -237,10 +282,10 @@ typedef struct /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider * @{ */ -#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000) -#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001) -#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002) -#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003) +#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) /** * @} */ @@ -248,10 +293,10 @@ typedef struct /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider * @{ */ -#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000) -#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001) -#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002) -#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003) +#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) /** * @} */ @@ -259,7 +304,7 @@ typedef struct /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR * @{ */ -#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000) +#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR @@ -270,7 +315,7 @@ typedef struct /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source * @{ */ -#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000) +#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC /** @@ -281,10 +326,12 @@ typedef struct /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source * @{ */ -#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 - +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -292,9 +339,12 @@ typedef struct /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source * @{ */ -#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -302,7 +352,7 @@ typedef struct /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source * @{ */ -#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000) +#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ /** * @} @@ -311,7 +361,7 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) +#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL @@ -322,7 +372,7 @@ typedef struct /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source * @{ */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL @@ -333,7 +383,7 @@ typedef struct /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source * @{ */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL @@ -344,7 +394,7 @@ typedef struct /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source * @{ */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL @@ -355,7 +405,7 @@ typedef struct /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source * @{ */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL @@ -366,7 +416,7 @@ typedef struct /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source * @{ */ -#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000) +#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL @@ -377,7 +427,7 @@ typedef struct /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source * @{ */ -#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL @@ -388,7 +438,7 @@ typedef struct /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source * @{ */ -#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL @@ -399,7 +449,7 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source * @{ */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 /** @@ -409,7 +459,7 @@ typedef struct /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source * @{ */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 @@ -420,7 +470,7 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source * @{ */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 /** @@ -430,7 +480,7 @@ typedef struct /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source * @{ */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 /** @@ -440,7 +490,7 @@ typedef struct /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) +#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL @@ -452,7 +502,7 @@ typedef struct /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source * @{ */ -#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000) +#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL /** * @} @@ -461,7 +511,7 @@ typedef struct /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection * @{ */ -#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000) +#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE /** * @} @@ -470,12 +520,52 @@ typedef struct /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source * @{ */ -#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000) +#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL /** * @} */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source + * @{ + */ +#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +/** + * @} + */ +#endif /* STM32F769xx || STM32F779xx */ + /** * @} */ @@ -498,23 +588,23 @@ typedef struct * using it. */ #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ @@ -522,7 +612,7 @@ typedef struct } while(0) #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ @@ -530,7 +620,7 @@ typedef struct } while(0) #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ @@ -538,7 +628,7 @@ typedef struct } while(0) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ @@ -546,7 +636,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ @@ -554,7 +644,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ @@ -562,7 +652,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ @@ -570,7 +660,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ @@ -578,7 +668,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ @@ -586,7 +676,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ @@ -594,7 +684,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ @@ -602,7 +692,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ @@ -610,7 +700,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ @@ -618,7 +708,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ @@ -626,7 +716,7 @@ typedef struct } while(0) #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ @@ -654,7 +744,7 @@ typedef struct * @brief Enable ETHERNET clock. */ #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ @@ -662,7 +752,7 @@ typedef struct } while(0) #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ @@ -670,7 +760,7 @@ typedef struct } while(0) #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ @@ -678,13 +768,13 @@ typedef struct } while(0) #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_ETH_CLK_ENABLE() do { \ __HAL_RCC_ETHMAC_CLK_ENABLE(); \ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ @@ -709,15 +799,26 @@ typedef struct * using it. */ #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ UNUSED(tmpreg); \ } while(0) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ @@ -725,21 +826,21 @@ typedef struct } while(0) #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ UNUSED(tmpreg); \ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ } while(0) - + #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -747,16 +848,16 @@ typedef struct } while(0) #define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F756x */ +#endif /* STM32F756x || STM32F777xx || STM32F779xx */ /** @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -764,7 +865,7 @@ typedef struct * using it. */ #define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ @@ -772,7 +873,7 @@ typedef struct } while(0) #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ @@ -788,7 +889,7 @@ typedef struct * using it. */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ @@ -796,7 +897,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ @@ -804,7 +905,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ @@ -812,7 +913,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ @@ -820,7 +921,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ @@ -828,7 +929,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ @@ -836,7 +937,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ @@ -844,7 +945,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ @@ -852,7 +953,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ @@ -860,15 +961,33 @@ typedef struct } while(0) #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ UNUSED(tmpreg); \ } while(0) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ @@ -876,7 +995,7 @@ typedef struct } while(0) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ @@ -884,7 +1003,7 @@ typedef struct } while(0) #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ @@ -892,7 +1011,7 @@ typedef struct } while(0) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ @@ -900,7 +1019,7 @@ typedef struct } while(0) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ @@ -908,7 +1027,7 @@ typedef struct } while(0) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ @@ -916,7 +1035,7 @@ typedef struct } while(0) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ @@ -924,7 +1043,7 @@ typedef struct } while(0) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ @@ -932,7 +1051,7 @@ typedef struct } while(0) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ @@ -940,7 +1059,7 @@ typedef struct } while(0) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ @@ -948,7 +1067,7 @@ typedef struct } while(0) #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ @@ -956,7 +1075,7 @@ typedef struct } while(0) #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ @@ -964,7 +1083,7 @@ typedef struct } while(0) #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ @@ -972,7 +1091,7 @@ typedef struct } while(0) #define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ @@ -980,7 +1099,7 @@ typedef struct } while(0) #define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ @@ -988,7 +1107,7 @@ typedef struct } while(0) #define __HAL_RCC_UART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ @@ -996,7 +1115,7 @@ typedef struct } while(0) #define __HAL_RCC_UART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ @@ -1013,6 +1132,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) @@ -1037,7 +1160,7 @@ typedef struct * using it. */ #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ @@ -1045,7 +1168,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ @@ -1053,7 +1176,7 @@ typedef struct } while(0) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ @@ -1061,15 +1184,25 @@ typedef struct } while(0) #define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ UNUSED(tmpreg); \ } while(0) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ @@ -1077,7 +1210,7 @@ typedef struct } while(0) #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ @@ -1085,7 +1218,7 @@ typedef struct } while(0) #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ @@ -1093,7 +1226,7 @@ typedef struct } while(0) #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ @@ -1101,7 +1234,7 @@ typedef struct } while(0) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ @@ -1109,7 +1242,7 @@ typedef struct } while(0) #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ @@ -1117,7 +1250,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ @@ -1125,7 +1258,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ @@ -1133,7 +1266,7 @@ typedef struct } while(0) #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ @@ -1141,7 +1274,7 @@ typedef struct } while(0) #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ @@ -1149,7 +1282,7 @@ typedef struct } while(0) #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ @@ -1157,7 +1290,7 @@ typedef struct } while(0) #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ @@ -1165,27 +1298,58 @@ typedef struct } while(0) #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ UNUSED(tmpreg); \ } while(0) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) @@ -1199,9 +1363,17 @@ typedef struct #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -1264,7 +1436,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) /** * @brief Disable ETHERNET clock. @@ -1275,7 +1447,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) /** @brief Get the enable or disable status of the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1290,12 +1462,17 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1323,6 +1500,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) @@ -1351,6 +1532,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) @@ -1391,9 +1576,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) @@ -1411,9 +1604,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1459,30 +1660,35 @@ typedef struct /** @brief Force or release AHB2 peripheral reset. */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -#if defined(STM32F756xx) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) +#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Force or release AHB3 peripheral reset */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) @@ -1498,6 +1704,9 @@ typedef struct #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) @@ -1526,6 +1735,9 @@ typedef struct #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) @@ -1561,9 +1773,9 @@ typedef struct #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) @@ -1580,10 +1792,24 @@ typedef struct #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx */ - +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) + +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1660,19 +1886,24 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1702,6 +1933,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) @@ -1730,6 +1965,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) @@ -1771,9 +2010,9 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) @@ -1792,10 +2031,22 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx */ - +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) + +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1876,19 +2127,24 @@ typedef struct #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1918,6 +2174,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) @@ -1946,6 +2206,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) @@ -1987,9 +2251,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) @@ -2008,14 +2280,92 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx */ - +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ +/*------------------------------- PLL Configuration --------------------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * @param __PLLR__: specifies the division factor for DSI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ + ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ + ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \ + ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR)))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ + ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ + ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*---------------------------------------------------------------------------------------------*/ /** @brief Macro to configure the Timers clocks prescalers @@ -2121,6 +2471,9 @@ typedef struct * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) @@ -2133,6 +2486,9 @@ typedef struct * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) @@ -2148,6 +2504,9 @@ typedef struct * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) @@ -2161,6 +2520,9 @@ typedef struct * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) @@ -2510,6 +2872,72 @@ typedef struct */ #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). + * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) + +/** @brief macro to get the SDMMC2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) + +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock + * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) + +/** @brief Macro to configure the DFSDM1 Audio clock + * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 Audio clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__: specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ /** * @} */ @@ -2581,6 +3009,61 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F765xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #endif /* STM32F746xx || STM32F756xx */ #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ @@ -2698,6 +3181,34 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) #endif /* STM32F745xx || STM32F746xx || STM32F756xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -2713,7 +3224,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** * @} */ - #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c index 622adac2dea..33166732c37 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -29,7 +29,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h index 5d7a16a0888..46016824b2d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -66,11 +66,11 @@ */ typedef enum { - HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */ - HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */ - HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ - HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */ - HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */ + HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */ + HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */ + HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */ + HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */ + HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */ }HAL_RNG_StateTypeDef; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c index 95720bbac39..d8973d120dc 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -109,7 +109,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -581,6 +581,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Get subseconds values from the correspondent registers*/ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); /* Get the TR register */ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); @@ -626,9 +629,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h index 2055807830e..9aea57d0f2f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,11 +64,11 @@ */ typedef enum { - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ }HAL_RTCStateTypeDef; @@ -111,8 +111,15 @@ typedef struct uint8_t Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ @@ -195,8 +202,8 @@ typedef struct /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) +#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U) +#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U) /** * @} */ @@ -205,8 +212,8 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) +#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U) +#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U) /** * @} */ @@ -214,7 +221,7 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U) #define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */ /** * @} @@ -223,8 +230,8 @@ typedef struct /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) /** * @} */ @@ -232,9 +239,9 @@ typedef struct /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) +#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U) +#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U) +#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U) /** * @} */ @@ -242,8 +249,8 @@ typedef struct /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) +#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U) +#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U) /** * @} */ @@ -251,8 +258,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x000000000) -#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN ((uint32_t)0x00000000U) +#define RTC_FORMAT_BCD ((uint32_t)0x00000001U) /** * @} */ @@ -261,18 +268,18 @@ typedef struct * @{ */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) /** * @} */ @@ -280,13 +287,13 @@ typedef struct /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /** * @} */ @@ -294,8 +301,8 @@ typedef struct /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) +#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U) /** * @} */ @@ -303,12 +310,12 @@ typedef struct /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U) #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U) /** * @} */ @@ -325,38 +332,38 @@ typedef struct /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. +#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U) /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U) /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U) /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U) /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U) /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U) /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U) /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U) /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U) /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U) /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U) /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U) /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U) /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U) /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match +#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U) /*!< SS[14:0] are compared and must match to activate alarm. */ /** * @} @@ -690,14 +697,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) #define RTC_TIMEOUT_VALUE 1000 -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c index d7ed7099aba..9b56828bace 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -70,7 +70,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h index 1007c3f90c6..99373da96be 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -106,10 +106,10 @@ typedef struct /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions * @{ */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) -#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) -#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) +#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U) +#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U) +#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U) +#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U) /** * @} */ @@ -117,38 +117,38 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions * @{ */ -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) +#define RTC_BKP_DR0 ((uint32_t)0x00000000U) +#define RTC_BKP_DR1 ((uint32_t)0x00000001U) +#define RTC_BKP_DR2 ((uint32_t)0x00000002U) +#define RTC_BKP_DR3 ((uint32_t)0x00000003U) +#define RTC_BKP_DR4 ((uint32_t)0x00000004U) +#define RTC_BKP_DR5 ((uint32_t)0x00000005U) +#define RTC_BKP_DR6 ((uint32_t)0x00000006U) +#define RTC_BKP_DR7 ((uint32_t)0x00000007U) +#define RTC_BKP_DR8 ((uint32_t)0x00000008U) +#define RTC_BKP_DR9 ((uint32_t)0x00000009U) +#define RTC_BKP_DR10 ((uint32_t)0x0000000AU) +#define RTC_BKP_DR11 ((uint32_t)0x0000000BU) +#define RTC_BKP_DR12 ((uint32_t)0x0000000CU) +#define RTC_BKP_DR13 ((uint32_t)0x0000000DU) +#define RTC_BKP_DR14 ((uint32_t)0x0000000EU) +#define RTC_BKP_DR15 ((uint32_t)0x0000000FU) +#define RTC_BKP_DR16 ((uint32_t)0x00000010U) +#define RTC_BKP_DR17 ((uint32_t)0x00000011U) +#define RTC_BKP_DR18 ((uint32_t)0x00000012U) +#define RTC_BKP_DR19 ((uint32_t)0x00000013U) +#define RTC_BKP_DR20 ((uint32_t)0x00000014U) +#define RTC_BKP_DR21 ((uint32_t)0x00000015U) +#define RTC_BKP_DR22 ((uint32_t)0x00000016U) +#define RTC_BKP_DR23 ((uint32_t)0x00000017U) +#define RTC_BKP_DR24 ((uint32_t)0x00000018U) +#define RTC_BKP_DR25 ((uint32_t)0x00000019U) +#define RTC_BKP_DR26 ((uint32_t)0x0000001AU) +#define RTC_BKP_DR27 ((uint32_t)0x0000001BU) +#define RTC_BKP_DR28 ((uint32_t)0x0000001CU) +#define RTC_BKP_DR29 ((uint32_t)0x0000001DU) +#define RTC_BKP_DR30 ((uint32_t)0x0000001EU) +#define RTC_BKP_DR31 ((uint32_t)0x0000001FU) /** * @} */ @@ -156,8 +156,8 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions * @{ */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) +#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U) +#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U) /** * @} */ @@ -186,9 +186,9 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) -#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002) -#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004) +#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U) +#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002U) +#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004U) /** * @} */ @@ -196,8 +196,8 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U) #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE /** @@ -207,8 +207,8 @@ typedef struct /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions * @{ */ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) -#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U) +#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U) /** * @} */ @@ -216,8 +216,8 @@ typedef struct /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions * @{ */ -#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) -#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000) +#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U) +#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U) /** * @} */ @@ -225,13 +225,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions * @{ */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */ -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 +#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800U) /*!< Tamper is activated after 2 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 +#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000U) /*!< Tamper is activated after 4 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 +#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800U) /*!< Tamper is activated after 8 consecutive samples at the active leve. */ /** * @} @@ -240,21 +240,21 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ /** * @} @@ -263,13 +263,13 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U) /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U) /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ /** * @} @@ -279,7 +279,7 @@ typedef struct * @{ */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} */ @@ -287,7 +287,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} @@ -296,12 +296,12 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U) +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U) /** * @} */ @@ -309,11 +309,11 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration +#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration +#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration +#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds */ /** * @} @@ -322,10 +322,10 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added +#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000U) /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ /** * @} @@ -334,8 +334,8 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions * @{ */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) +#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U) +#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U) /** * @} */ @@ -343,8 +343,8 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) +#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U) +#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000U) /** * @} */ @@ -924,8 +924,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_IM21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ /** * @} */ @@ -936,7 +936,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t */ /* Masks Definition */ #define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) -#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT)) +#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) /** * @} */ @@ -956,9 +956,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER) #define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \ ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING)) -#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET)) +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET)) -#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET)) +#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET)) #define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \ ((__PIN__) == RTC_TIMESTAMPPIN_POS1) || \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c index 53e69b7ec43..1719038b676 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c @@ -2,27 +2,27 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SAI HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: * + Initialization/de-initialization functions * + I/O operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - + [..] The SAI HAL driver can be used as follows: - - (#) Declare a SAI_HandleTypeDef handle structure. + + (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai). (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API: - (##) Enable the SAI interface clock. + (##) Enable the SAI interface clock. (##) SAI pins configuration: (+++) Enable the clock for the SAI GPIOs. (+++) Configure these SAI pins as alternate function pull-up. @@ -35,99 +35,108 @@ and HAL_SAI_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx stream. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx Stream. (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream. - - (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity - using HAL_SAI_Init() function. - - -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt) - will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT() - inside the transmit and receive process. - - [..] - (@) SAI Clock Source, the configuration is managed through RCCEx_PeriphCLKConfig() - function in the HAL RCC drivers - [..] + + (#) The initialization can be done by two ways + (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init(). + (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol(). + + [..] + (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt) + will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT() + inside the transmit and receive process. + [..] (@) Make sure that either: - (+@) I2S PLL is configured or - (+@) SAI PLL is configured or - (+@) External clock source is configured after setting correctly - the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file. - - [..] - (@) In master Tx mode: enabling the audio block immediately generates the bit clock - for the external slaves even if there is no data in the FIFO, However FS signal + (+@) I2S PLL is configured or + (+@) SAI PLL is configured or + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file. + [..] + (@) In master Tx mode: enabling the audio block immediately generates the bit clock + for the external slaves even if there is no data in the FIFO, However FS signal generation is conditioned by the presence of data in the FIFO. - - [..] - (@) In master Rx mode: enabling the audio block immediately generates the bit clock - and FS signal for the external slaves. - - [..] - (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: - (+@) First bit Offset <= (SLOT size - Data size) - (+@) Data size <= SLOT size - (+@) Number of SLOT x SLOT size = Frame length - (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() - (+) Receive an amount of data in blocking mode using HAL_SAI_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT() - (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SAI_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT() - (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SAI_RxCpltCallback - (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SAI_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA() - (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SAI_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA() - (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SAI_RxCpltCallback - (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SAI_ErrorCallback - (+) Pause the DMA Transfer using HAL_SAI_DMAPause() - (+) Resume the DMA Transfer using HAL_SAI_DMAResume() - (+) Stop the DMA Transfer using HAL_SAI_DMAStop() - - *** SAI HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in USART HAL driver : - - (+) __HAL_SAI_ENABLE: Enable the SAI peripheral - (+) __HAL_SAI_DISABLE: Disable the SAI peripheral - (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts - (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts - (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is + + [..] + (@) In master Rx mode: enabling the audio block immediately generates the bit clock + and FS signal for the external slaves. + + [..] + (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: + (+@) First bit Offset <= (SLOT size - Data size) + (+@) Data size <= SLOT size + (+@) Number of SLOT x SLOT size = Frame length + (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SAI_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT() + (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT() + (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_RxCpltCallback() + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SAI_ErrorCallback() + + *** DMA mode IO operation *** + ============================= + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA() + (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA() + (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_RxCpltCallback() + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SAI_ErrorCallback() + (+) Pause the DMA Transfer using HAL_SAI_DMAPause() + (+) Resume the DMA Transfer using HAL_SAI_DMAResume() + (+) Stop the DMA Transfer using HAL_SAI_DMAStop() + + *** SAI HAL driver additional function list *** + =============================================== + [..] + Below the list the others API available SAI HAL driver : + + (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode + (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode + (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode + (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode + (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo. + (+) HAL_SAI_Abort(): Abort the current transfer + + *** SAI HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SAI HAL driver : + + (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral + (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral + (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts + (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts + (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is enabled or disabled - (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not - + (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -152,7 +161,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -169,6 +178,7 @@ #ifdef HAL_SAI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ + /** @defgroup SAI_Private_Typedefs SAI Private Typedefs * @{ */ @@ -179,26 +189,26 @@ typedef enum { /** * @} */ + /* Private define ------------------------------------------------------------*/ + /** @defgroup SAI_Private_Constants SAI Private Constants * @{ */ -#define SAI_FIFO_SIZE 8 -#define SAI_DEFAULT_TIMEOUT 4 +#define SAI_FIFO_SIZE 8 +#define SAI_DEFAULT_TIMEOUT 4 /* 4ms */ #define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT) /** * @} */ -/* SAI registers Masks */ -#define CR1_CLEAR_MASK ((uint32_t)0xFF04C010) -#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000) -#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020) - -#define SAI_TIMEOUT_VALUE 10 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ + +/** @defgroup SAI_Private_Functions SAI Private Functions + * @{ + */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai); static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode); static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); @@ -217,30 +227,34 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma); static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void SAI_DMAError(DMA_HandleTypeDef *hdma); +static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions ---------------------------------------------------------*/ -/** @defgroup SAI_Exported_Functions SAI Exported Functions +/** @defgroup SAI_Exported_Functions SAI Exported Functions * @{ */ -/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SAIx peripheral: + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SAIx peripheral: - (+) User must implement HAL_SAI_MspInit() function in which he configures + (+) User must implement HAL_SAI_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - (+) Call the function HAL_SAI_Init() to configure the selected device with + (+) Call the function HAL_SAI_Init() to configure the selected device with the selected configuration: (++) Mode (Master/slave TX/RX) - (++) Protocol + (++) Protocol (++) Data Size (++) MCLK Output (++) Audio frequency @@ -248,40 +262,40 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma); (++) Frame Config (++) Slot Config - (+) Call the function HAL_SAI_DeInit() to restore the default configuration - of the selected SAI peripheral. + (+) Call the function HAL_SAI_DeInit() to restore the default configuration + of the selected SAI peripheral. @endverbatim * @{ */ /** - * @brief Initializes the structure FrameInit, SlotInit and the low part of + * @brief Initialize the structure FrameInit, SlotInit and the low part of * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol : one of the supported protocol @ref SAI_Protocol - * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize - * the configuration information for SAI module. - * @param nbslot : Number of slot. + * @param protocol: one of the supported protocol @ref SAI_Protocol + * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * the configuration information for SAI module. + * @param nbslot: Number of slot. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - + switch(protocol) { case SAI_I2S_STANDARD : case SAI_I2S_MSBJUSTIFIED : case SAI_I2S_LSBJUSTIFIED : status = SAI_InitI2S(hsai, protocol, datasize, nbslot); - break; + break; case SAI_PCM_LONG : case SAI_PCM_SHORT : status = SAI_InitPCM(hsai, protocol, datasize, nbslot); @@ -300,32 +314,31 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco } /** - * @brief Initializes the SAI according to the specified parameters - * in the SAI_InitTypeDef and create the associated handle. + * @brief Initialize the SAI according to the specified parameters. + * in the SAI_InitTypeDef structure and initialize the associated handle. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) -{ - uint32_t tmpclock = 0; - - /* This variable used to store the SAI_CK_x (value in Hz) */ - uint32_t freq = 0; - +{ + uint32_t tmpregisterGCR = 0; + uint32_t ckstr_bits = 0; uint32_t syncen_bits = 0; - + /* Check the SAI handle allocation */ if(hsai == NULL) { return HAL_ERROR; } + /* check the instance */ + assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance)); + /* Check the SAI Block parameters */ - assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); + assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol)); assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode)); - assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize)); assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit)); assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing)); @@ -336,6 +349,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode)); assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode)); assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState)); + assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); /* Check the SAI Block Frame parameters */ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); @@ -365,30 +379,22 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) SAI_Disable(hsai); /* SAI Block Synchro Configuration -----------------------------------------*/ - SAI_BlockSynchroConfig(hsai); - - /* Configure Master Clock using the following formula : - MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS - FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 - MCKDIV[3:0] = SAI_CK_x / FS * 512 */ - if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) - { - /* Get SAI clock source based on Source clock selection from RCC */ - freq = SAI_GetInputClock(hsai); - - /* (saiclocksource x 10) to keep Significant digits */ - tmpclock = (((freq * 10) / ((hsai->Init.AudioFrequency) * 512))); - - hsai->Init.Mckdiv = tmpclock / 10; - - /* Round result to the nearest integer */ - if((tmpclock % 10) > 8) - { - hsai->Init.Mckdiv+= 1; - } + /* This setting must be done with both audio block (A & B) disabled */ + switch(hsai->Init.SynchroExt) + { + case SAI_SYNCEXT_DISABLE : + tmpregisterGCR = 0; + break; + case SAI_SYNCEXT_OUTBLOCKA_ENABLE : + tmpregisterGCR = SAI_GCR_SYNCOUT_0; + break; + case SAI_SYNCEXT_OUTBLOCKB_ENABLE : + tmpregisterGCR = SAI_GCR_SYNCOUT_1; + break; + default: + break; } - /* SAI Block Configuration ------------------------------------------------------------*/ switch(hsai->Init.Synchro) { case SAI_ASYNCHRONOUS : @@ -402,36 +408,93 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) } break; case SAI_SYNCHRONOUS_EXT_SAI1 : - case SAI_SYNCHRONOUS_EXT_SAI2 : { syncen_bits = SAI_xCR1_SYNCEN_1; } break; - } + case SAI_SYNCHRONOUS_EXT_SAI2 : + { + syncen_bits = SAI_xCR1_SYNCEN_1; + tmpregisterGCR |= SAI_GCR_SYNCIN_0; + } + break; + default: + break; + } + + if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) + { + SAI1->GCR = tmpregisterGCR; + } + else + { + SAI2->GCR = tmpregisterGCR; + } + + if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) + { + uint32_t freq = 0; + uint32_t tmpval; + + if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B )) + { + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); + } + if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B )) + { + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); + } + + /* Configure Master Clock using the following formula : + MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS + FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 + MCKDIV[3:0] = SAI_CK_x / FS * 512 */ + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256); + hsai->Init.Mckdiv = tmpval / 10; + + /* Round result to the nearest integer */ + if((tmpval % 10) > 8) + { + hsai->Init.Mckdiv+= 1; + } + } + + /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ + if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { /* Transmit */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR; + } + else + { /* Receive */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0; + } + + /* SAI Block Configuration -------------------------------------------------*/ /* SAI CR1 Configuration */ hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); - - hsai->Instance->CR1|= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + + hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ hsai->Init.DataSize | hsai->Init.FirstBit | \ - hsai->Init.ClockStrobing | syncen_bits | \ + ckstr_bits | syncen_bits | \ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); /* SAI CR2 Configuration */ hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); - + /* SAI Frame Configuration -----------------------------------------*/ hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ - SAI_xFRCR_FSPO | SAI_xFRCR_FSOFF)); - hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) | - hsai->FrameInit.FSOffset | - hsai->FrameInit.FSDefinition | - hsai->FrameInit.FSPolarity | - ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); + SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); + hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) | + hsai->FrameInit.FSOffset | + hsai->FrameInit.FSDefinition | + hsai->FrameInit.FSPolarity | + ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); /* SAI Block_x SLOT Configuration ------------------------------------------*/ /* This register has no meaning in AC 97 and SPDIF audio protocol */ @@ -439,7 +502,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN )); hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize - | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); + | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; @@ -454,7 +517,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) } /** - * @brief DeInitializes the SAI peripheral. + * @brief DeInitialize the SAI peripheral. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status @@ -471,7 +534,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /* Disabled All interrupt and clear all the flag */ hsai->Instance->IMR = 0; - hsai->Instance->CLRFR = 0xFFFFFFFF; + hsai->Instance->CLRFR = 0xFFFFFFFFU; /* Disable the SAI */ SAI_Disable(hsai); @@ -484,7 +547,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Initialize the SAI state */ hsai->State = HAL_SAI_STATE_RESET; @@ -495,7 +558,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) } /** - * @brief SAI MSP Init. + * @brief Initialize the SAI MSP. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None @@ -504,14 +567,14 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_MspInit could be implemented in the user file - */ + */ } /** - * @brief SAI MSP DeInit. + * @brief DeInitialize the SAI MSP. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None @@ -520,63 +583,63 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_MspDeInit could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup SAI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup SAI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions * -@verbatim - =============================================================================== +@verbatim + ============================================================================== ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SAI data + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SAI data transfers. (+) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. (+) Blocking mode functions are : - (++) HAL_SAI_Transmit() - (++) HAL_SAI_Receive() - (++) HAL_SAI_TransmitReceive() - + (++) HAL_SAI_Transmit() + (++) HAL_SAI_Receive() + (++) HAL_SAI_TransmitReceive() + (+) Non Blocking mode functions with Interrupt are : - (++) HAL_SAI_Transmit_IT() - (++) HAL_SAI_Receive_IT() - (++) HAL_SAI_TransmitReceive_IT() + (++) HAL_SAI_Transmit_IT() + (++) HAL_SAI_Receive_IT() + (++) HAL_SAI_TransmitReceive_IT() (+) Non Blocking mode functions with DMA are : - (++) HAL_SAI_Transmit_DMA() - (++) HAL_SAI_Receive_DMA() - (++) HAL_SAI_TransmitReceive_DMA() + (++) HAL_SAI_Transmit_DMA() + (++) HAL_SAI_Receive_DMA() + (++) HAL_SAI_TransmitReceive_DMA() (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SAI_TxCpltCallback() - (++) HAL_SAI_RxCpltCallback() - (++) HAL_SAI_ErrorCallback() + (++) HAL_SAI_TxCpltCallback() + (++) HAL_SAI_RxCpltCallback() + (++) HAL_SAI_ErrorCallback() @endverbatim * @{ */ /** - * @brief Transmits an amount of data in blocking mode. + * @brief Transmit an amount of data in blocking mode. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @param pData: Pointer to data buffer @@ -587,73 +650,86 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) + + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } - + if(hsai->State == HAL_SAI_STATE_READY) - { + { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->XferSize = Size; hsai->XferCount = Size; hsai->pBuffPtr = pData; hsai->State = HAL_SAI_STATE_BUSY_TX; hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Check if the SAI is already enabled */ + + /* Check if the SAI is already enabled */ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { /* fill the fifo with data before to enabled the SAI */ - SAI_FillFifo(hsai); - /* Enable SAI peripheral */ + SAI_FillFifo(hsai); + /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + while(hsai->XferCount > 0) - { + { /* Write data if the FIFO is not full */ if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) { if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { + { hsai->Instance->DR = (*hsai->pBuffPtr++); } else if(hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; + hsai->pBuffPtr+= 2; } else { hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); hsai->pBuffPtr+= 4; - } - hsai->XferCount--; + } + hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))) + if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout))) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Clear all the flags */ + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable SAI peripheral */ + SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + /* Change the SAI state */ - hsai->State = HAL_SAI_STATE_TIMEOUT; - - return HAL_TIMEOUT; + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; } } - } - - hsai->State = HAL_SAI_STATE_READY; - + } + + hsai->State = HAL_SAI_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -663,7 +739,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint } /** - * @brief Receives an amount of data in blocking mode. + * @brief Receive an amount of data in blocking mode. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @param pData: Pointer to data buffer @@ -674,33 +750,33 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) + + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } - + if(hsai->State == HAL_SAI_STATE_READY) - { + { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->State = HAL_SAI_STATE_BUSY_RX; hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Check if the SAI is already enabled */ + + /* Check if the SAI is already enabled */ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { - /* Enable SAI peripheral */ + /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Receive data */ while(hsai->XferCount > 0) - { + { if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) { if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) @@ -716,29 +792,42 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 { *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR; hsai->pBuffPtr+= 4; - } - hsai->XferCount--; + } + hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))) + if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout))) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Clear all the flags */ + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable SAI peripheral */ + SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + /* Change the SAI state */ - hsai->State = HAL_SAI_STATE_TIMEOUT; - - return HAL_TIMEOUT; + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; } } - } - - hsai->State = HAL_SAI_STATE_READY; - + } + + hsai->State = HAL_SAI_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -748,7 +837,7 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 } /** - * @brief Transmits an amount of data in no-blocking mode with Interrupt. + * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @param pData: Pointer to data buffer @@ -757,22 +846,22 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + if(hsai->State == HAL_SAI_STATE_READY) - { + { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_TX; - + if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; @@ -785,22 +874,22 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u { hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit; } - + /* Fill the fifo before starting the communication */ SAI_FillFifo(hsai); - + /* Enable FRQ and OVRUDR interrupts */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Check if the SAI is already enabled */ + + /* Check if the SAI is already enabled */ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ + { + /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -810,7 +899,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u } /** - * @brief Receives an amount of data in no-blocking mode with Interrupt. + * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @param pData: Pointer to data buffer @@ -819,22 +908,22 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + if(hsai->State == HAL_SAI_STATE_READY) - { + { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_RX; - + if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; @@ -847,17 +936,17 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui { hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit; } - + /* Enable TXE and OVRUDR interrupts */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Check if the SAI is already enabled */ + + /* Check if the SAI is already enabled */ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { - /* Enable SAI peripheral */ + /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Process Unlocked */ __HAL_UNLOCK(hsai); @@ -865,12 +954,12 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** - * @brief Pauses the audio stream playing from the Media. + * @brief Pause the audio stream playing from the Media. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status @@ -879,18 +968,18 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) { /* Process Locked */ __HAL_LOCK(hsai); - + /* Pause the audio file playing by disabling the SAI DMA requests */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Process Unlocked */ __HAL_UNLOCK(hsai); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Resumes the audio stream playing from the Media. + * @brief Resume the audio stream playing from the Media. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status @@ -899,26 +988,26 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) { /* Process Locked */ __HAL_LOCK(hsai); - + /* Enable the SAI DMA requests */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; /* If the SAI peripheral is still not enabled, enable it */ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { - /* Enable SAI peripheral */ + /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** - * @brief Stops the audio stream playing from the Media. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Stop the audio stream playing from the Media. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -926,11 +1015,11 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) { /* Process Locked */ __HAL_LOCK(hsai); - + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Tx Stream */ + + /* Abort the SAI DMA Streams */ if(hsai->hdmatx != NULL) { if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) @@ -938,9 +1027,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) return HAL_ERROR; } } - /* Abort the SAI DMA Rx Stream */ + if(hsai->hdmarx != NULL) - { + { if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) { return HAL_ERROR; @@ -949,63 +1038,69 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Disable SAI peripheral */ SAI_Disable(hsai); - + hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** - * @brief Abort the current transfer and disbaled the SAI. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Abort the current transfer and disable the SAI. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) { - /* Disable the SAI DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Tx Stream */ - if(hsai->hdmatx != NULL) + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Check SAI DMA is enabled or not */ + if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Abort the SAI DMA Streams */ + if(hsai->hdmatx != NULL) { - return HAL_ERROR; + if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + { + return HAL_ERROR; + } } - } - /* Abort the SAI DMA Rx Stream */ - if(hsai->hdmarx != NULL) - { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + + if(hsai->hdmarx != NULL) { - return HAL_ERROR; + if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + { + return HAL_ERROR; + } } } - /* Disabled All interrupt and clear all the flag */ hsai->Instance->IMR = 0; - hsai->Instance->CLRFR = 0xFFFFFFFF; - + hsai->Instance->CLRFR = 0xFFFFFFFFU; + /* Disable SAI peripheral */ SAI_Disable(hsai); - + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** - * @brief Transmits an amount of data in no-blocking mode with DMA. + * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @param pData: Pointer to data buffer @@ -1014,53 +1109,57 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) */ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - + if(hsai->State == HAL_SAI_STATE_READY) - { + { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_TX; - + /* Set the SAI Tx DMA Half transfer complete callback */ hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt; - + /* Set the SAI TxDMA transfer complete callback */ hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt; - + /* Set the DMA error callback */ hsai->hdmatx->XferErrorCallback = SAI_DMAError; - + + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = NULL; + /* Enable the Tx DMA Stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->XferSize); - - /* Check if the SAI is already enabled */ + if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + + /* Check if the SAI is already enabled */ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - /* Enable SAI Tx DMA Request */ + + /* Enable SAI Tx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1070,7 +1169,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, } /** - * @brief Receives an amount of data in no-blocking mode with DMA. + * @brief Receive an amount of data in non-blocking mode with DMA. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @param pData: Pointer to data buffer @@ -1079,53 +1178,58 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, */ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; - } - + } + if(hsai->State == HAL_SAI_STATE_READY) - { + { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_RX; - + /* Set the SAI Rx DMA Half transfer complete callback */ hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt; - + /* Set the SAI Rx DMA transfer complete callback */ hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt; - + /* Set the DMA error callback */ hsai->hdmarx->XferErrorCallback = SAI_DMAError; - + + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = NULL; + /* Enable the Rx DMA Stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->XferSize); - + if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + /* Check if the SAI is already enabled */ if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - + /* Enable SAI Rx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1135,16 +1239,16 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u } /** - * @brief Enable the tx mute mode. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Enable the Tx mute mode. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param val : value sent during the mute @ref SAI_Block_Mute_Value + * @param val: value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) { assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); - + if(hsai->State != HAL_SAI_STATE_RESET) { CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); @@ -1155,8 +1259,8 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val } /** - * @brief Disable the tx mute mode. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Disable the Tx mute mode. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1171,17 +1275,17 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) } /** - * @brief Enable the rx mute detection. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Enable the Rx mute detection. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param callback : function called when the mute is detected - * @param counter : number a data before mute detection max 63. + * @param callback: function called when the mute is detected. + * @param counter: number a data before mute detection max 63. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) { assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); - + if(hsai->State != HAL_SAI_STATE_RESET) { /* set the mute counter */ @@ -1196,8 +1300,8 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback } /** - * @brief Disable the rx mute detection. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Disable the Rx mute detection. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1215,108 +1319,189 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) } /** - * @brief This function handles SAI interrupt request. + * @brief Handle SAI interrupt request. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval HAL status + * @retval None */ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) -{ +{ if(hsai->State != HAL_SAI_STATE_RESET) { - uint32_t tmpFlag = hsai->Instance->SR; - uint32_t tmpItSource = hsai->Instance->IMR; - - if(((tmpFlag & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((tmpItSource & SAI_IT_FREQ) == SAI_IT_FREQ)) + uint32_t itflags = hsai->Instance->SR; + uint32_t itsources = hsai->Instance->IMR; + uint32_t cr1config = hsai->Instance->CR1; + uint32_t tmperror; + + /* SAI Fifo request interrupt occured ------------------------------------*/ + if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); } - - /* check the flag only if one of them is set */ - if(tmpFlag != 0x00000000) + /* SAI Overrun error interrupt occurred ----------------------------------*/ + else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) { - /* SAI Overrun error interrupt occurred ----------------------------------*/ - if(((tmpFlag & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((tmpItSource & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + /* Get the SAI error code */ + tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR); + /* Change the SAI error code */ + hsai->ErrorCode |= tmperror; + /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ + HAL_SAI_ErrorCallback(hsai); + } + /* SAI mutedet interrupt occurred ----------------------------------*/ + else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) + { + /* Clear the SAI mutedet flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); + /* call the call back function */ + if(hsai->mutecallback != (SAIcallback)NULL) { - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - /* Change the SAI error code */ - hsai->ErrorCode = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR); - /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ - HAL_SAI_ErrorCallback(hsai); + /* inform the user that an RX mute event has been detected */ + hsai->mutecallback(); } - - /* SAI mutedet interrupt occurred ----------------------------------*/ - if(((tmpFlag & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((tmpItSource & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) + } + /* SAI AFSDET interrupt occurred ----------------------------------*/ + else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) + { + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; + /* Check SAI DMA is enabled or not */ + if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { - /* Clear the SAI mutedet flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); - /* call the call back function */ - if(hsai->mutecallback != (SAIcallback)NULL) + /* Abort the SAI DMA Streams */ + if(hsai->hdmatx != NULL) { - /* inform the user that an RX mute event has been detected */ - hsai->mutecallback(); + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + HAL_DMA_Abort_IT(hsai->hdmatx); + } + else if(hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + /* Abort DMA in IT mode */ + HAL_DMA_Abort_IT(hsai->hdmarx); } } - - /* SAI AFSDET interrupt occurred ----------------------------------*/ - if(((tmpFlag & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((tmpItSource & SAI_IT_AFSDET) == SAI_IT_AFSDET)) + else { - /* Change the SAI error code */ - hsai->ErrorCode = HAL_SAI_ERROR_AFSDET; + /* Abort SAI */ HAL_SAI_Abort(hsai); - HAL_SAI_ErrorCallback(hsai); + + /* Set error callback */ + HAL_SAI_ErrorCallback(hsai); + } + } + /* SAI LFSDET interrupt occurred ----------------------------------*/ + else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) + { + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; + + /* Check SAI DMA is enabled or not */ + if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Abort the SAI DMA Streams */ + if(hsai->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + /* Abort DMA in IT mode */ + HAL_DMA_Abort_IT(hsai->hdmatx); + } + else if(hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + /* Abort DMA in IT mode */ + HAL_DMA_Abort_IT(hsai->hdmarx); + } } - - /* SAI LFSDET interrupt occurred ----------------------------------*/ - if(((tmpFlag & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((tmpItSource & SAI_IT_LFSDET) == SAI_IT_LFSDET)) + else { - /* Change the SAI error code */ - hsai->ErrorCode = HAL_SAI_ERROR_LFSDET; + /* Abort SAI */ HAL_SAI_Abort(hsai); + + /* Set error callback */ HAL_SAI_ErrorCallback(hsai); } + } + /* SAI WCKCFG interrupt occurred ----------------------------------*/ + else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) + { + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; - /* SAI WCKCFG interrupt occurred ----------------------------------*/ - if(((tmpFlag & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((tmpItSource & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) + /* Abort the SAI DMA Streams */ + if(hsai->hdmatx != NULL) { - /* Change the SAI error code */ - hsai->ErrorCode = HAL_SAI_ERROR_WCKCFG; - HAL_SAI_Abort(hsai); - HAL_SAI_ErrorCallback(hsai); + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + /* Abort DMA in IT mode */ + HAL_DMA_Abort_IT(hsai->hdmatx); } - /* SAI CNRDY interrupt occurred ----------------------------------*/ - if(((tmpFlag & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((tmpItSource & SAI_IT_CNRDY) == SAI_IT_CNRDY)) + else if(hsai->hdmarx != NULL) { - /* Clear the SAI CNRDY flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); - /* Change the SAI error code */ - hsai->ErrorCode = HAL_SAI_ERROR_CNREADY; - /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ - HAL_SAI_ErrorCallback(hsai); - } + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + /* Abort DMA in IT mode */ + HAL_DMA_Abort_IT(hsai->hdmarx); + } + else + { + /* If WCKCFG occurs, SAI audio block is automatically disabled */ + /* Disable all interrupts and clear all flags */ + hsai->Instance->IMR = 0U; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + /* Set the SAI state to ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error Callback */ + HAL_SAI_ErrorCallback(hsai); + } + } + /* SAI CNRDY interrupt occurred ----------------------------------*/ + else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) + { + /* Clear the SAI CNRDY flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY; + /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ + HAL_SAI_ErrorCallback(hsai); + } + else + { + /* Nothing to do */ } } } /** - * @brief Tx Transfer completed callbacks. + * @brief Tx Transfer completed callback. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ - __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_TxCpltCallback could be implemented in the user file - */ + */ } /** - * @brief Tx Transfer Half completed callbacks + * @brief Tx Transfer Half completed callback. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None @@ -1325,14 +1510,14 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_TxHalfCpltCallback could be implemented in the user file - */ + */ } /** - * @brief Rx Transfer completed callbacks. + * @brief Rx Transfer completed callback. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None @@ -1341,14 +1526,14 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_RxCpltCallback could be implemented in the user file */ } /** - * @brief Rx Transfer half completed callbacks + * @brief Rx Transfer half completed callback. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None @@ -1357,14 +1542,14 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SAI_RxCpltCallback could be implemented in the user file + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_RxHalfCpltCallback could be implemented in the user file */ } /** - * @brief SAI error callbacks. + * @brief SAI error callback. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None @@ -1373,10 +1558,10 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_ErrorCallback could be implemented in the user file - */ + */ } /** @@ -1384,15 +1569,15 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) */ -/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1400,7 +1585,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) */ /** - * @brief Returns the SAI state. + * @brief Return the SAI handle state. * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL state @@ -1411,8 +1596,8 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) } /** -* @brief Return the SAI error code -* @param hsai : pointer to a SAI_HandleTypeDef structure that contains +* @brief Return the SAI error code. +* @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. * @retval SAI Error Code */ @@ -1425,37 +1610,50 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) */ /** - * @brief Initializes the SAI I2S protocol according to the specified parameters + * @} + */ + +/** @addtogroup SAI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol : one of the supported protocol - * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol: one of the supported protocol. + * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot : number of slot minimum value is 2 and max is 16. + * @param nbslot: number of slot minimum value is 2 and max is 16. * the value must be a multiple of 2. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { - /* Check the parameters */ - assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); - assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + /* Compute ClockStrobing according AudioMode */ + if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { /* Transmit */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + } + else + { /* Receive */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + } hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; hsai->SlotInit.FirstBitOffset = 0; hsai->SlotInit.SlotNumber = nbslot; - + /* in IS2 the number of slot must be even */ if((nbslot & 0x1) != 0 ) { return HAL_ERROR; } - + switch(protocol) { case SAI_I2S_STANDARD : @@ -1470,7 +1668,7 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, default : return HAL_ERROR; } - + /* Frame definition */ switch(datasize) { @@ -1479,27 +1677,27 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->FrameInit.FrameLength = 32*(nbslot/2); hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2); hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; + break; case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : hsai->Init.DataSize = SAI_DATASIZE_16; hsai->FrameInit.FrameLength = 64*(nbslot/2); hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; + break; case SAI_PROTOCOL_DATASIZE_24BIT: hsai->Init.DataSize = SAI_DATASIZE_24; hsai->FrameInit.FrameLength = 64*(nbslot/2); hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; break; - case SAI_PROTOCOL_DATASIZE_32BIT: + case SAI_PROTOCOL_DATASIZE_32BIT: hsai->Init.DataSize = SAI_DATASIZE_32; hsai->FrameInit.FrameLength = 64*(nbslot/2); hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; break; default : - return HAL_ERROR; + return HAL_ERROR; } if(protocol == SAI_I2S_LSBJUSTIFIED) { @@ -1516,31 +1714,35 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, } /** - * @brief Initializes the SAI PCM protocol according to the specified parameters + * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol : one of the supported protocol - * @param datasize : one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot : number of slot minimum value is 1 and the max is 16. + * @param protocol: one of the supported protocol + * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot: number of slot minimum value is 1 and the max is 16. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { - /* Check the parameters */ - assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); - assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + /* Compute ClockStrobing according AudioMode */ + if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { /* Transmit */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + } + else + { /* Receive */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + } hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; hsai->SlotInit.FirstBitOffset = 0; hsai->SlotInit.SlotNumber = nbslot; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - + switch(protocol) { case SAI_PCM_SHORT : @@ -1552,14 +1754,14 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, default : return HAL_ERROR; } - + switch(datasize) { case SAI_PROTOCOL_DATASIZE_16BIT: hsai->Init.DataSize = SAI_DATASIZE_16; hsai->FrameInit.FrameLength = 16 * nbslot; hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; + break; case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : hsai->Init.DataSize = SAI_DATASIZE_16; hsai->FrameInit.FrameLength = 32 * nbslot; @@ -1569,8 +1771,8 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->Init.DataSize = SAI_DATASIZE_24; hsai->FrameInit.FrameLength = 32 * nbslot; hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: + break; + case SAI_PROTOCOL_DATASIZE_32BIT: hsai->Init.DataSize = SAI_DATASIZE_32; hsai->FrameInit.FrameLength = 32 * nbslot; hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; @@ -1578,20 +1780,20 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, default : return HAL_ERROR; } - + return HAL_OK; } /** - * @brief Fill the fifo - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Fill the fifo. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) { /* fill the fifo with data before to enabled the SAI */ - while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) + while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) { if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { @@ -1612,27 +1814,27 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) } /** - * @brief return the interrupt flag to set according the SAI setup - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Return the interrupt flag to set according the SAI setup. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param mode : SAI_MODE_DMA or SAI_MODE_IT + * @param mode: SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) { - uint32_t tmpIT = SAI_IT_OVRUDR; + uint32_t tmpIT = SAI_IT_OVRUDR; if(mode == SAI_MODE_IT) { tmpIT|= SAI_IT_FREQ; } - if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && + if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) { tmpIT|= SAI_IT_CNRDY; } - + if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) { tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET; @@ -1646,36 +1848,39 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) } /** - * @brief disable the SAI and wait the disabling + * @brief Disable the SAI and wait for the disabling. * @param hsai : pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) { - uint32_t tickstart = HAL_GetTick(); + register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000); HAL_StatusTypeDef status = HAL_OK; - + + /* Disable the SAI instance */ __HAL_SAI_DISABLE(hsai); - while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET) + + do { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > SAI_TIMEOUT_VALUE) + if (count-- == 0) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - return HAL_TIMEOUT; + status = HAL_TIMEOUT; + break; } - } + } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET); + return status; } /** - * @brief Tx Handler for Transmit in Interrupt mode 8Bit transfer - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) { @@ -1683,7 +1888,7 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; HAL_SAI_TxCpltCallback(hsai); } @@ -1692,22 +1897,22 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /* Write data on DR register */ hsai->Instance->DR = (*hsai->pBuffPtr++); hsai->XferCount--; - } + } } /** - * @brief Tx Handler for Transmit in Interrupt mode for 16Bit transfer - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) { if(hsai->XferCount == 0) { - /* Handle the end of the transmission */ + /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; HAL_SAI_TxCpltCallback(hsai); } @@ -1717,14 +1922,14 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr; hsai->pBuffPtr+=2; hsai->XferCount--; - } + } } /** - * @brief Tx Handler for Transmit in Interrupt mode for 32Bit transfer - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) { @@ -1732,7 +1937,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; HAL_SAI_TxCpltCallback(hsai); } @@ -1746,81 +1951,81 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) } /** - * @brief Rx Handler for Receive in Interrupt mode 8Bit transfer - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) { - /* Receive data */ + /* Receive data */ (*hsai->pBuffPtr++) = hsai->Instance->DR; hsai->XferCount--; - - /* Check end of the transfer */ + + /* Check end of the transfer */ if(hsai->XferCount == 0) - { + { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_RxCpltCallback(hsai); + HAL_SAI_RxCpltCallback(hsai); } } /** - * @brief Rx Handler for Receive in Interrupt mode for 16Bit transfer - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) { - /* Receive data */ + /* Receive data */ *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR; hsai->pBuffPtr+=2; hsai->XferCount--; - - /* Check end of the transfer */ + + /* Check end of the transfer */ if(hsai->XferCount == 0) - { + { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_RxCpltCallback(hsai); + HAL_SAI_RxCpltCallback(hsai); } } /** - * @brief Rx Handler for Receive in Interrupt mode for 32Bit transfer - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. + * @param hsai: pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @retval None. + * @retval None */ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) { - /* Receive data */ + /* Receive data */ *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR; hsai->pBuffPtr+=4; hsai->XferCount--; - - /* Check end of the transfer */ + + /* Check end of the transfer */ if(hsai->XferCount == 0) - { + { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; - HAL_SAI_RxCpltCallback(hsai); + HAL_SAI_RxCpltCallback(hsai); } } @@ -1830,15 +2035,15 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) * the configuration information for the specified DMA module. * @retval None */ -static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) +static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) { SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent; - + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { + { hsai->XferCount = 0; - /* Disable SAI Tx DMA Request */ + /* Disable SAI Tx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); /* Stop the interrupts error handling */ @@ -1850,7 +2055,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SAI transmit process half complete callback + * @brief DMA SAI transmit process half complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1863,12 +2068,12 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SAI receive process complete callback. + * @brief DMA SAI receive process complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) +static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) { SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) @@ -1876,13 +2081,13 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) /* Disable Rx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); hsai->XferCount = 0; - + /* Stop the interrupts error handling */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); hsai->State = HAL_SAI_STATE_READY; } - HAL_SAI_RxCpltCallback(hsai); + HAL_SAI_RxCpltCallback(hsai); } /** @@ -1895,26 +2100,72 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - HAL_SAI_RxHalfCpltCallback(hsai); + HAL_SAI_RxHalfCpltCallback(hsai); +} +/** + * @brief DMA SAI communication error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMAError(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE)) + { + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Disable SAI peripheral */ + SAI_Disable(hsai); + + /* Set the SAI state ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + } + /* SAI error Callback */ + HAL_SAI_ErrorCallback(hsai); } + /** - * @brief DMA SAI communication error callback. + * @brief DMA SAI Abort callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void SAI_DMAError(DMA_HandleTypeDef *hdma) +static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) { SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Stop the DMA transfer */ - HAL_SAI_DMAStop(hsai); + /* Disable DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Disable all interrupts and clear all flags */ + hsai->Instance->IMR = 0U; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) + { + /* Disable SAI peripheral */ + SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + } + /* Set the SAI state to ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; - /* Set the SAI state ready to be able to start again the process */ - hsai->State= HAL_SAI_STATE_READY; + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error Callback */ HAL_SAI_ErrorCallback(hsai); - - hsai->XferCount = 0; } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h index 33331b5e8fd..931df77a982 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_SAI_H @@ -45,7 +45,7 @@ /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" +#include "stm32f7xx_hal_def.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ @@ -53,177 +53,191 @@ /** @addtogroup SAI * @{ - */ - -/* Exported types ------------------------------------------------------------*/ + */ + +/* Exported types ------------------------------------------------------------*/ /** @defgroup SAI_Exported_Types SAI Exported Types * @{ */ - -/** - * @brief HAL State structures definition - */ + +/** + * @brief HAL State structures definition + */ typedef enum { - HAL_SAI_STATE_RESET = 0x00, /*!< SAI not yet initialized or disabled */ - HAL_SAI_STATE_READY = 0x01, /*!< SAI initialized and ready for use */ - HAL_SAI_STATE_BUSY = 0x02, /*!< SAI internal process is ongoing */ - HAL_SAI_STATE_BUSY_TX = 0x12, /*!< Data transmission process is ongoing */ - HAL_SAI_STATE_BUSY_RX = 0x22, /*!< Data reception process is ongoing */ - HAL_SAI_STATE_TIMEOUT = 0x03, /*!< SAI timeout state */ - HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */ + HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */ + HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */ + HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ + HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ + HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ }HAL_SAI_StateTypeDef; -/** - * @brief SAI Callback prototype +/** + * @brief SAI Callback prototype */ typedef void (*SAIcallback)(void); -/** - * @brief SAI Init Structure definition +/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition + * @brief SAI Init Structure definition + * @{ */ typedef struct -{ - uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. - This parameter can be a value of @ref SAI_Block_Mode */ +{ + uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. + This parameter can be a value of @ref SAI_Block_Mode */ uint32_t Synchro; /*!< Specifies SAI Block synchronization - This parameter can be a value of @ref SAI_Block_Synchronization */ - - uint32_t SynchroExt; /*!< Specifies SAI Block synchronization, this setup is common - for BLOCKA and BLOCKB - This parameter can be a value of @ref SAI_Block_SyncExt */ + This parameter can be a value of @ref SAI_Block_Synchronization */ + + uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common + for BlockA and BlockB + This parameter can be a value of @ref SAI_Block_SyncExt + @note: If both audio blocks of same SAI are used, this parameter has + to be set to the same value for each audio block */ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. This parameter can be a value of @ref SAI_Block_Output_Drive - @note this value has to be set before enabling the audio block - but after the audio block configuration. */ + @note this value has to be set before enabling the audio block + but after the audio block configuration. */ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. This parameter can be a value of @ref SAI_Block_NoDivider - @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length + @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. - If bit NODIV in the SAI_xCR1 register is set, the frame length can - take any of the values without constraint since the input clock of + If bit NODIV in the SAI_xCR1 register is set, the frame length can + take any of the values without constraint since the input clock of the audio block should be equal to the bit clock. - There is no MCLK_x clock which can be output. */ - + There is no MCLK_x clock which can be output. */ + uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. - This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ + This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ - uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. - This parameter can be a value of @ref SAI_Audio_Frequency */ + uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. + This parameter can be a value of @ref SAI_Audio_Frequency */ - uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for - AudioFrequency the user choice - This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for + AudioFrequency the user choice + This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ - uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. - This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ - - uint32_t CompandingMode; /*!< Specifies the companding mode type. - This parameter can be a value of @ref SAI_Block_Companding_Mode */ - - uint32_t TriState; /*!< Specifies the companding mode type. - This parameter can be a value of @ref SAI_TRIState_Management */ - - /* This part of the structure is automatically filled if your are using the high level initialisation - function HAL_SAI_InitProtocol */ + uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. + This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ + + uint32_t CompandingMode; /*!< Specifies the companding mode type. + This parameter can be a value of @ref SAI_Block_Companding_Mode */ + + uint32_t TriState; /*!< Specifies the companding mode type. + This parameter can be a value of @ref SAI_TRIState_Management */ + + /* This part of the structure is automatically filled if your are using the high level initialisation + function HAL_SAI_InitProtocol */ uint32_t Protocol; /*!< Specifies the SAI Block protocol. - This parameter can be a value of @ref SAI_Block_Protocol */ - + This parameter can be a value of @ref SAI_Block_Protocol */ + uint32_t DataSize; /*!< Specifies the SAI Block data size. - This parameter can be a value of @ref SAI_Block_Data_Size */ + This parameter can be a value of @ref SAI_Block_Data_Size */ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ + This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. - This parameter can be a value of @ref SAI_Block_Clock_Strobing */ + This parameter can be a value of @ref SAI_Block_Clock_Strobing */ }SAI_InitTypeDef; +/** + * @} + */ -/** - * @brief SAI Block Frame Init structure definition +/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition + * @brief SAI Frame Init structure definition + * @{ */ - typedef struct { - uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. - This parameter must be a number between Min_Data = 8 and Max_Data = 256. - @note If master clock MCLK_x pin is declared as an output, the frame length - should be aligned to a number equal to power of 2 in order to keep - in an audio frame, an integer number of MCLK pulses by bit Clock. */ - + uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. + This parameter must be a number between Min_Data = 8 and Max_Data = 256. + @note: If master clock MCLK_x pin is declared as an output, the frame length + should be aligned to a number equal to power of 2 in order to keep + in an audio frame, an integer number of MCLK pulses by bit Clock. */ + uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. - This Parameter specifies the length in number of bit clock (SCK + 1) + This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition. - This parameter can be a value of @ref SAI_Block_FS_Definition */ - + This parameter can be a value of @ref SAI_Block_FS_Definition */ + uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity. - This parameter can be a value of @ref SAI_Block_FS_Polarity */ + This parameter can be a value of @ref SAI_Block_FS_Polarity */ uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. - This parameter can be a value of @ref SAI_Block_FS_Offset */ + This parameter can be a value of @ref SAI_Block_FS_Offset */ }SAI_FrameInitTypeDef; - /** - * @brief SAI Block Slot Init Structure definition - */ + * @} + */ +/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition + * @brief SAI Block Slot Init Structure definition + * @{ + */ typedef struct { uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. This parameter must be a number between Min_Data = 0 and Max_Data = 24 */ uint32_t SlotSize; /*!< Specifies the Slot Size. - This parameter can be a value of @ref SAI_Block_Slot_Size */ + This parameter can be a value of @ref SAI_Block_Slot_Size */ uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. - This parameter can be a value of @ref SAI_Block_Slot_Active */ + This parameter can be a value of @ref SAI_Block_Slot_Active */ }SAI_SlotInitTypeDef; +/** + * @} + */ -/** - * @brief SAI handle Structure definition +/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition + * @brief SAI handle Structure definition + * @{ */ typedef struct __SAI_HandleTypeDef { - SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ + SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ - SAI_InitTypeDef Init; /*!< SAI communication parameters */ + SAI_InitTypeDef Init; /*!< SAI communication parameters */ - SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ + SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ - SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ + SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ - uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ + uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ - uint16_t XferSize; /*!< SAI transfer size */ + uint16_t XferSize; /*!< SAI transfer size */ - uint16_t XferCount; /*!< SAI transfer counter */ + uint16_t XferCount; /*!< SAI transfer counter */ - DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ - DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ - SAIcallback mutecallback;/*!< SAI mute callback */ - - void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ - - HAL_LockTypeDef Lock; /*!< SAI locking object */ + SAIcallback mutecallback; /*!< SAI mute callback */ + + void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ + + HAL_LockTypeDef Lock; /*!< SAI locking object */ - __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ + __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ - __IO uint32_t ErrorCode; /*!< SAI Error code */ + __IO uint32_t ErrorCode; /*!< SAI Error code */ }SAI_HandleTypeDef; +/** + * @} + */ /** * @} @@ -235,17 +249,18 @@ typedef struct __SAI_HandleTypeDef * @{ */ -/** @defgroup SAI_Error_Code SAI Error Code +/** @defgroup SAI_Error_Code SAI Error Code * @{ */ -#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */ -#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */ -#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004) /*!< Anticipated Frame synchronisation detection */ -#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008) /*!< Late Frame synchronisation detection */ -#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010) /*!< codec not ready */ -#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020) /*!< Wrong clock configuration */ -#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040) /*!< Timeout error */ +#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */ +#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */ +#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */ +#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */ +#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */ +#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */ +#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ +#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */ /** * @} */ @@ -253,9 +268,9 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_SyncExt SAI External synchronisation * @{ */ -#define SAI_SYNCEXT_DISABLE ((uint32_t)0x00000000) -#define SAI_SYNCEXT_OUTBLOCKA_ENABLE ((uint32_t)0x00000001) -#define SAI_SYNCEXT_OUTBLOCKB_ENABLE ((uint32_t)0x00000002) +#define SAI_SYNCEXT_DISABLE 0 +#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1 +#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2 /** * @} */ @@ -263,11 +278,11 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Protocol SAI Supported protocol * @{ */ -#define SAI_I2S_STANDARD ((uint32_t)0x00000000) -#define SAI_I2S_MSBJUSTIFIED ((uint32_t)0x00000001) -#define SAI_I2S_LSBJUSTIFIED ((uint32_t)0x00000002) -#define SAI_PCM_LONG ((uint32_t)0x00000004) -#define SAI_PCM_SHORT ((uint32_t)0x00000008) +#define SAI_I2S_STANDARD 0 +#define SAI_I2S_MSBJUSTIFIED 1 +#define SAI_I2S_LSBJUSTIFIED 2 +#define SAI_PCM_LONG 3 +#define SAI_PCM_SHORT 4 /** * @} */ @@ -275,21 +290,10 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Protocol_DataSize SAI protocol data size * @{ */ -#define SAI_PROTOCOL_DATASIZE_16BIT ((uint32_t)0x00000000) -#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED ((uint32_t)0x00000001) -#define SAI_PROTOCOL_DATASIZE_24BIT ((uint32_t)0x00000002) -#define SAI_PROTOCOL_DATASIZE_32BIT ((uint32_t)0x00000004) -/** - * @} - */ - -/** @defgroup SAI_Clock_Source SAI Clock Source - * @{ - */ -#define SAI_CLKSOURCE_PLLSAI ((uint32_t)0x00000000) -#define SAI_CLKSOURCE_PLLI2S ((uint32_t)0x00100000) -#define SAI_CLKSOURCE_EXT ((uint32_t)0x00200000) -#define SAI_CLKSOURCE_NA ((uint32_t)0x00400000) +#define SAI_PROTOCOL_DATASIZE_16BIT 0 +#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1 +#define SAI_PROTOCOL_DATASIZE_24BIT 2 +#define SAI_PROTOCOL_DATASIZE_32BIT 3 /** * @} */ @@ -297,17 +301,16 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Audio_Frequency SAI Audio Frequency * @{ */ -#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000) -#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000) -#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000) -#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100) -#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000) -#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050) -#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000) -#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025) -#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000) -#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0) - +#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U) +#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U) +#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U) +#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U) +#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U) +#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U) +#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U) +#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U) +#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U) +#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U) /** * @} */ @@ -315,7 +318,7 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mode SAI Block Mode * @{ */ -#define SAI_MODEMASTER_TX ((uint32_t)0x00000000) +#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U) #define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) #define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) #define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) @@ -327,10 +330,9 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Protocol SAI Block Protocol * @{ */ -#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000) +#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U) #define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) #define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) - /** * @} */ @@ -338,23 +340,21 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Data_Size SAI Block Data Size * @{ */ -#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) -#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) -#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) -#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) - +#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) +#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) +#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) +#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) +#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) +#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) /** * @} - */ + */ -/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission +/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission * @{ */ -#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U) #define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) - /** * @} */ @@ -362,9 +362,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing * @{ */ -#define SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000) -#define SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)SAI_xCR1_CKSTR) - +#define SAI_CLOCKSTROBING_FALLINGEDGE 0 +#define SAI_CLOCKSTROBING_RISINGEDGE 1 /** * @} */ @@ -372,30 +371,28 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Synchronization SAI Block Synchronization * @{ */ -#define SAI_ASYNCHRONOUS ((uint32_t)0x00000000) /*!< Asynchronous */ -#define SAI_SYNCHRONOUS ((uint32_t)0x00000001) /*!< Synchronous with other block of same SAI */ -#define SAI_SYNCHRONOUS_EXT_SAI1 ((uint32_t)0x00000002) /*!< Synchronous with other SAI, SAI1 */ -#define SAI_SYNCHRONOUS_EXT_SAI2 ((uint32_t)0x00000003) /*!< Synchronous with other SAI, SAI2 */ +#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */ +#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */ +#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */ +#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */ /** * @} - */ + */ -/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive +/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive * @{ */ -#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000) +#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U) #define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) - /** * @} - */ + */ /** @defgroup SAI_Block_NoDivider SAI Block NoDivider * @{ */ -#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000) +#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) #define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) - /** * @} */ @@ -404,29 +401,26 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition * @{ */ -#define SAI_FS_STARTFRAME ((uint32_t)0x00000000) +#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U) #define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) - /** * @} */ -/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity +/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity * @{ */ -#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000) -#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO) - +#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U) +#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) /** * @} */ - -/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset + +/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset * @{ */ -#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000) +#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U) #define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) - /** * @} */ @@ -435,35 +429,34 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size * @{ */ -#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000) +#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U) #define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) #define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) /** * @} */ - + /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active * @{ */ -#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000) -#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001) -#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002) -#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004) -#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008) -#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010) -#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020) -#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040) -#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080) -#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100) -#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200) -#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400) -#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800) -#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000) -#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000) -#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000) -#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000) -#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFF) - +#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U) +#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U) +#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U) +#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U) +#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U) +#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U) +#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U) +#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U) +#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U) +#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U) +#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U) +#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U) +#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U) +#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U) +#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U) +#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U) +#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U) +#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU) /** * @} */ @@ -471,9 +464,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode * @{ */ -#define SAI_STEREOMODE ((uint32_t)0x00000000) -#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) - +#define SAI_STEREOMODE ((uint32_t)0x00000000U) +#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) /** * @} */ @@ -481,35 +473,32 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_TRIState_Management SAI TRIState Management * @{ */ -#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000) -#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) - +#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U) +#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) /** * @} */ -/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold +/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold * @{ */ -#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000) -#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)SAI_xCR2_FTH_0) -#define SAI_FIFOTHRESHOLD_HF ((uint32_t)SAI_xCR2_FTH_1) +#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U) +#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) +#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) #define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)SAI_xCR2_FTH_2) - +#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) /** * @} */ - + /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode * @{ */ -#define SAI_NOCOMPANDING ((uint32_t)0x00000000) -#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)SAI_xCR2_COMP_1) -#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) -#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) -#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) - +#define SAI_NOCOMPANDING ((uint32_t)0x00000000U) +#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) +#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) +#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) +#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) /** * @} */ @@ -517,14 +506,12 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value * @{ */ -#define SAI_ZERO_VALUE ((uint32_t)0x00000000) -#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) - +#define SAI_ZERO_VALUE ((uint32_t)0x00000000U) +#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) /** * @} */ - /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition * @{ */ @@ -535,7 +522,6 @@ typedef struct __SAI_HandleTypeDef #define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) #define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) #define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) - /** * @} */ @@ -550,21 +536,19 @@ typedef struct __SAI_HandleTypeDef #define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) #define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) #define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) - /** * @} */ - + /** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level * @{ */ -#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000) -#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000) -#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000) -#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000) -#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000) -#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000) - +#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U) +#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U) +#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U) +#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U) +#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U) +#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U) /** * @} */ @@ -572,15 +556,15 @@ typedef struct __SAI_HandleTypeDef /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup SAI_Exported_Macros SAI Exported Macros * @brief macros to handle interrupts and specific configurations * @{ */ - -/** @brief Reset SAI handle state + +/** @brief Reset SAI handle state. * @param __HANDLE__: specifies the SAI Handle. * @retval None */ @@ -590,27 +574,29 @@ typedef struct __SAI_HandleTypeDef * @param __HANDLE__: specifies the SAI Handle. * @param __INTERRUPT__: specifies the interrupt source to enable or disable. * This parameter can be one of the following values: - * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable - * @arg SAI_IT_MUTEDET: Mute detection interrupt enable - * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable - * @arg SAI_IT_FREQ: FIFO request interrupt enable - * @arg SAI_IT_CNRDY: Codec not ready interrupt enable - * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable - * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable * @retval None */ - #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) - -/** @brief Check if the specified SAI interrupt source is enabled or disabled. + +/** @brief Check whether the specified SAI interrupt source is enabled or not. * @param __HANDLE__: specifies the SAI Handle. - * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral. * @param __INTERRUPT__: specifies the SAI interrupt source to check. * This parameter can be one of the following values: - * @arg SAI_IT_TXE: Tx buffer empty interrupt enable. - * @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable. - * @arg SAI_IT_ERR: Error interrupt enable. + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) @@ -625,48 +611,46 @@ typedef struct __SAI_HandleTypeDef * @arg SAI_FLAG_FREQ: FIFO request flag. * @arg SAI_FLAG_CNRDY: Codec not ready flag. * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag. - * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. + * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/** @brief Clears the specified SAI pending flag. +/** @brief Clear the specified SAI pending flag. * @param __HANDLE__: specifies the SAI Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: - * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun - * @arg SAI_FLAG_MUTEDET: Clear Mute detection - * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration - * @arg SAI_FLAG_FREQ: Clear FIFO request + * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun + * @arg SAI_FLAG_MUTEDET: Clear Mute detection + * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration + * @arg SAI_FLAG_FREQ: Clear FIFO request * @arg SAI_FLAG_CNRDY: Clear Codec not ready * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection - * + * * @retval None */ -#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) +#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) - + /** * @} */ -/* Include RCC SAI Extension module */ -#include "stm32f7xx_hal_sai_ex.h" - /* Exported functions --------------------------------------------------------*/ /** @addtogroup SAI_Exported_Functions * @{ */ -/* Initialization/de-initialization functions **********************************/ +/* Initialization/de-initialization functions ********************************/ + /** @addtogroup SAI_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); +HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai); void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); @@ -676,7 +660,8 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); * @} */ -/* I/O operation functions *****************************************************/ +/* I/O operation functions ***************************************************/ + /** @addtogroup SAI_Exported_Functions_Group2 * @{ */ @@ -718,51 +703,24 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); /** @addtogroup SAI_Exported_Functions_Group3 * @{ */ -/* Peripheral State functions **************************************************/ +/* Peripheral State functions ************************************************/ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); /** * @} */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup SAI_Private_Types SAI Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup SAI_Private_Variables SAI Private Variables - * @{ - */ /** * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SAI_Private_Constants SAI Private Constants - * @{ */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @addtogroup SAI_Private_Macros * @{ */ -#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ - ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ - ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) +#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ + ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ + ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ @@ -775,20 +733,16 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\ ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) -#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\ - ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\ - ((SOURCE) == SAI_CLKSOURCE_EXT)) - #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) -#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ - ((MODE) == SAI_MODEMASTER_RX) || \ - ((MODE) == SAI_MODESLAVE_TX) || \ - ((MODE) == SAI_MODESLAVE_RX)) +#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ + ((MODE) == SAI_MODEMASTER_RX) || \ + ((MODE) == SAI_MODESLAVE_TX) || \ + ((MODE) == SAI_MODESLAVE_RX)) #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ @@ -807,72 +761,65 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) -#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\ +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \ ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ - ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) - -#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOSTATUS_LESS1QUARTERFULL ) || \ - ((STATUS) == SAI_FIFOSTATUS_HALFFULL) || \ - ((STATUS) == SAI_FIFOSTATUS_1QUARTERFULL) || \ - ((STATUS) == SAI_FIFOSTATUS_3QUARTERFULL) || \ - ((STATUS) == SAI_FIFOSTATUS_FULL) || \ - ((STATUS) == SAI_FIFOSTATUS_EMPTY)) + ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ - ((VALUE) == SAI_LAST_SENT_VALUE)) + ((VALUE) == SAI_LAST_SENT_VALUE)) #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \ ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \ - ((MODE) == SAI_ALAW_2CPL_COMPANDING)) + ((MODE) == SAI_ALAW_2CPL_COMPANDING)) #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \ ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ - ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) + ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ - ((STATE) == SAI_OUTPUT_RELEASED)) + ((STATE) == SAI_OUTPUT_RELEASED)) #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\ - ((MODE) == SAI_STEREOMODE)) + ((MODE) == SAI_STEREOMODE)) #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) -#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ ((SIZE) == SAI_SLOTSIZE_16B) || \ ((SIZE) == SAI_SLOTSIZE_32B)) -#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \ - ((POLARITY) == SAI_FS_ACTIVE_HIGH)) + ((POLARITY) == SAI_FS_ACTIVE_HIGH)) #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ - ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) - -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) + ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) + +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) + +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) -#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) -#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) - /** * @} */ @@ -888,12 +835,12 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c index ede3db4149f..a277d3d5f80 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c @@ -2,27 +2,17 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 - * @brief SAI Extension HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of SAI extension peripheral: - * + Extension features functions - * - @verbatim - ============================================================================== - ##### SAI peripheral extension features ##### - ============================================================================== - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to manage several sources to clock SAI - - @endverbatim + * @version V1.1.0 + * @date 22-April-2016 + * @brief Empty file; This file is no longer used to set synchronization and + * to get SAI block frequency. Its content is now moved to common files + * (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7 + * family. It's just kept for compatibility reasons. + * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -51,132 +41,12 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SAIEx SAIEx - * @brief SAI Extension HAL module driver - * @{ - */ - -#ifdef HAL_SAI_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* SAI registers Masks */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup SAI_Private_Functions SAI Private Functions - * @{ - */ - /** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions - * @{ - */ - -/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions - * @brief Extension features functions - * -@verbatim - =============================================================================== - ##### Extension features Functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the possible - SAI clock sources. - -@endverbatim - * @{ - */ - -/** - * @brief Configure SAI Block synchronization mode - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval SAI Clock Input - */ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) -{ - uint32_t tmpregisterGCR = 0; - - /* This setting must be done with both audio block (A & B) disabled */ - switch(hsai->Init.SynchroExt) - { - case SAI_SYNCEXT_DISABLE : - tmpregisterGCR = 0; - break; - case SAI_SYNCEXT_OUTBLOCKA_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_0; - break; - case SAI_SYNCEXT_OUTBLOCKB_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_1; - break; - default: - tmpregisterGCR = 0; - break; - } - - if((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2) - { - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - } - - if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) - { - SAI1->GCR = tmpregisterGCR; - } - else - { - SAI2->GCR = tmpregisterGCR; - } -} - /** - * @brief Get SAI Input Clock based on SAI source clock selection - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval SAI Clock Input - */ -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) -{ - /* This variable used to store the SAI_CK_x (value in Hz) */ - uint32_t saiclocksource = 0; - - if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) - { - saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - } - else /* SAI2_Block_A || SAI2_Block_B*/ - { - saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); - } - /* the return result is the value of SAI clock */ - return saiclocksource; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_SAI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h index 4b5878ac692..56c2abd3775 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -39,60 +39,18 @@ #ifndef __STM32F7xx_HAL_SAI_EX_H #define __STM32F7xx_HAL_SAI_EX_H -#ifdef __cplusplus - extern "C" { -#endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SAIEx - * @{ - */ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup SAIEx_Exported_Functions SAI Extended Exported Functions - * @{ - */ - -/** @addtogroup SAIEx_Exported_Functions_Group1 Extension features functions - * @{ - */ - /* Extended features functions ************************************************/ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai); -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); -/** - * @} - */ - -/** - * @} - */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - #endif /* __STM32F7xx_HAL_SAI_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c index fe7866ae123..1a5ee1528c1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -149,7 +149,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -206,67 +206,67 @@ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ SDMMC_FLAG_DBCKEND)) -#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000) +#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000U) /** * @brief Mask for errors Card Status R1 (OCR Register) */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) +#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) +#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) +#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) +#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) +#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) +#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) +#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) +#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) +#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) +#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) +#define SD_OCR_CC_ERROR ((uint32_t)0x00100000U) +#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) +#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) +#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) +#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) +#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) +#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) +#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000U) +#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) +#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) /** * @brief Masks for R6 Response */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) +#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) +#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) +#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) +#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) +#define SD_HIGH_CAPACITY ((uint32_t)0x40000000U) +#define SD_STD_CAPACITY ((uint32_t)0x00000000U) +#define SD_CHECK_PATTERN ((uint32_t)0x000001AAU) -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) +#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) +#define SD_ALLZERO ((uint32_t)0x00000000U) -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) +#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) +#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) +#define SD_CARD_LOCKED ((uint32_t)0x02000000U) -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) +#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#define SD_0TO7BITS ((uint32_t)0x000000FFU) +#define SD_8TO15BITS ((uint32_t)0x0000FF00U) +#define SD_16TO23BITS ((uint32_t)0x00FF0000U) +#define SD_24TO31BITS ((uint32_t)0xFF000000U) +#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) -#define SD_HALFFIFO ((uint32_t)0x00000008) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) +#define SD_HALFFIFO ((uint32_t)0x00000008U) +#define SD_HALFFIFOBYTES ((uint32_t)0x00000020U) /** * @brief Command Class Supported */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) -#define SD_CCCC_ERASE ((uint32_t)0x00000020) +#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080U) +#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040U) +#define SD_CCCC_ERASE ((uint32_t)0x00000020U) /** * @brief Following commands are SD Card Specific commands. @@ -1499,7 +1499,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->RCA = (uint16_t)(hsd->RCA); /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000) >> 24; + tmp = (hsd->CSD[0] & 0xFF000000U) >> 24; pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); pCardInfo->SD_csd.Reserved1 = tmp & 0x03; @@ -1517,16 +1517,16 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp; /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000) >> 24; + tmp = (hsd->CSD[1] & 0xFF000000U) >> 24; pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4); /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000) >> 16; + tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16; pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F); /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00) >> 8; + tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8; pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); @@ -1538,23 +1538,23 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); + tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); pCardInfo->SD_csd.DeviceSize |= (tmp) << 2; /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); + tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); + tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ; @@ -1565,21 +1565,21 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy else if (hsd->CardType == HIGH_CAPACITY_SD_CARD) { /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); + tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); pCardInfo->SD_csd.DeviceSize |= (tmp << 8); /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); + tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); pCardInfo->SD_csd.DeviceSize |= (tmp); /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); + tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024); pCardInfo->CardBlockSize = 512; @@ -1599,7 +1599,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24); pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; @@ -1627,7 +1627,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_csd.Reserved4 = 1; /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ManufacturerID = tmp; /* Byte 1 */ @@ -1643,7 +1643,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_cid.ProdName1 = tmp << 24; /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ProdName1 |= tmp << 16; /* Byte 5 */ @@ -1659,7 +1659,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_cid.ProdName2 = tmp; /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ProdRev = tmp; /* Byte 9 */ @@ -1675,7 +1675,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy pCardInfo->SD_cid.ProdSN |= tmp << 8; /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24); + tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); pCardInfo->SD_cid.ProdSN |= tmp; /* Byte 13 */ @@ -1840,7 +1840,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure); /* Send CMD6 switch mode */ - sdmmc_cmdinitstructure.Argument = 0x80FFFF01; + sdmmc_cmdinitstructure.Argument = 0x80FFFF01U; sdmmc_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); @@ -2121,55 +2121,55 @@ HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatu pCardStatus->SECURED_MODE = (uint8_t)tmp; /* Byte 2 */ - tmp = (sd_status[2] & 0xFF); - pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8); + tmp = (sd_status[0] & 0x00FF0000) >> 16; + pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8); /* Byte 3 */ - tmp = (sd_status[3] & 0xFF); - pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp; + tmp = (sd_status[0] & 0xFF000000) >> 24; + pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp; /* Byte 4 */ - tmp = (sd_status[4] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24); + tmp = (sd_status[1] & 0xFF); + pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24); /* Byte 5 */ - tmp = (sd_status[5] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16); + tmp = (sd_status[1] & 0xFF00) >> 8; + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16); /* Byte 6 */ - tmp = (sd_status[6] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8); + tmp = (sd_status[1] & 0xFF0000) >> 16; + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8); /* Byte 7 */ - tmp = (sd_status[7] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp; + tmp = (sd_status[1] & 0xFF000000) >> 24; + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp; /* Byte 8 */ - tmp = (sd_status[8] & 0xFF); + tmp = (sd_status[2] & 0xFF); pCardStatus->SPEED_CLASS = (uint8_t)tmp; /* Byte 9 */ - tmp = (sd_status[9] & 0xFF); + tmp = (sd_status[2] & 0xFF00) >> 8; pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; /* Byte 10 */ - tmp = (sd_status[10] & 0xF0) >> 4; + tmp = (sd_status[2] & 0xF00000) >> 20; pCardStatus->AU_SIZE = (uint8_t)tmp; /* Byte 11 */ - tmp = (sd_status[11] & 0xFF); - pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8); + tmp = (sd_status[2] & 0xFF000000) >> 24; + pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8); /* Byte 12 */ - tmp = (sd_status[12] & 0xFF); - pCardStatus->ERASE_SIZE |= (uint8_t)tmp; + tmp = (sd_status[3] & 0xFF); + pCardStatus->ERASE_SIZE |= (uint16_t)tmp; /* Byte 13 */ - tmp = (sd_status[13] & 0xFC) >> 2; + tmp = (sd_status[3] & 0xFC00) >> 10; pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; /* Byte 13 */ - tmp = (sd_status[13] & 0x3); + tmp = (sd_status[3] & 0x0300) >> 8; pCardStatus->ERASE_OFFSET = (uint8_t)tmp; return errorstate; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h index 785007900cf..51250ec35cf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -285,15 +285,15 @@ typedef enum */ typedef enum { - SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */ - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */ - SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */ - SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */ - SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */ - SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */ - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */ - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */ - SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */ + SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ + SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ + SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ + SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ + SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ + SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ + SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ + SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ + SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card is in error state */ }HAL_SD_CardStateTypedef; /** @@ -305,10 +305,10 @@ typedef enum */ typedef enum { - SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */ - SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */ - SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */ - SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */ + SD_READ_SINGLE_BLOCK = 0U, /*!< Read single block operation */ + SD_READ_MULTIPLE_BLOCK = 1U, /*!< Read multiple blocks operation */ + SD_WRITE_SINGLE_BLOCK = 2U, /*!< Write single block operation */ + SD_WRITE_MULTIPLE_BLOCK = 3U /*!< Write multiple blocks operation */ }HAL_SD_OperationTypedef; /** @@ -327,102 +327,102 @@ typedef enum /** * @brief SD Commands Index */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ -#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ -#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ -#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ +#define SD_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SD_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SD_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SD_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ +#define SD_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information +#define SD_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ -#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ -#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands +#define SD_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SD_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ +#define SD_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ +#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14U) +#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ +#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ -#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SD_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ +#define SD_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ +#define SD_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ +#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ +#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SD_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. +#define SD_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by +#define SD_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ +#define SD_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ +#define SD_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ +#define SD_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather +#define SD_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card +#define SD_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SD_CMD_NO_CMD ((uint8_t)64) +#define SD_CMD_NO_CMD ((uint8_t)64U) /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with +#define SD_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ -#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ -#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SD_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SD_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are SD Card Specific security commands. * SD_CMD_APP_CMD should be sent before sending these commands. */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43U) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_MID ((uint8_t)44U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) /*!< For SD card only */ +#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) /*!< For SD card only */ /** * @brief Supported SD Memory Cards */ -#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) +#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000U) +#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001U) +#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002U) +#define MULTIMEDIA_CARD ((uint32_t)0x00000003U) +#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004U) +#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005U) +#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006U) +#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007U) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c index 9f67fed0166..f6d18d3c725 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SDRAM HAL module driver. * This file provides a generic firmware to drive SDRAM memories mounted * as external device. @@ -63,7 +63,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h index 9eed428e202..f1c447a1697 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,12 +65,12 @@ */ typedef enum { - HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */ - HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */ - HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */ - HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */ - HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */ - HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */ + HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ + HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ + HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ + HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ + HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ + HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ }HAL_SDRAM_StateTypeDef; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c index 2e929705db5..d06aacf5ee3 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -59,7 +59,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,8 +103,8 @@ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define TEACK_REACK_TIMEOUT 1000 -#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000 +#define TEACK_REACK_TIMEOUT 1000U +#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000U #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) #define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) @@ -122,11 +122,14 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc); static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc); static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc); +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc); +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); /** * @} @@ -149,15 +152,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); (+) These parameters can be configured: (++) Baud Rate (++) Parity: parity should be enabled, - Frame Length is fixed to 8 bits plus parity: - the USART frame format is given in the following table: - - (+++) +---------------------------------------------------------------+ - (+++) | M1M0 bits | PCE bit | USART frame | - (+++) |-----------------------|---------------------------------------| - (+++) | 01 | 1 | | SB | 8 bit data | PB | STB | | - (+++) +---------------------------------------------------------------+ - + Frame Length is fixed to 8 bits plus parity. (++) Receiver/transmitter modes (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) (++) Prescaler value @@ -180,6 +175,15 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); (details for the procedures are available in reference manual). @endverbatim + + The USART frame format is given in the following table: + + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ + * @{ */ @@ -200,7 +204,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - if(hsc->State == HAL_SMARTCARD_STATE_RESET) + if(hsc->gState == HAL_SMARTCARD_STATE_RESET) { /* Allocate lock resource and initialize it */ hsc->Lock = HAL_UNLOCKED; @@ -208,7 +212,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) HAL_SMARTCARD_MspInit(hsc); } - hsc->State = HAL_SMARTCARD_STATE_BUSY; + hsc->gState = HAL_SMARTCARD_STATE_BUSY; /* Disable the Peripheral */ __HAL_SMARTCARD_DISABLE(hsc); @@ -224,11 +228,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) /* In SmartCard mode, the following bits must be kept cleared: - LINEN in the USART_CR2 register, - HDSEL and IREN bits in the USART_CR3 register.*/ - hsc->Instance->CR2 &= ~(USART_CR2_LINEN); - hsc->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN); + CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - /* set the USART in SMARTCARD mode */ - hsc->Instance->CR3 |= USART_CR3_SCEN; + /* set the USART in SMARTCARD mode */ + SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN); /* Enable the Peripheral */ __HAL_SMARTCARD_ENABLE(hsc); @@ -253,13 +257,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - hsc->State = HAL_SMARTCARD_STATE_BUSY; + hsc->gState = HAL_SMARTCARD_STATE_BUSY; /* DeInit the low level hardware */ HAL_SMARTCARD_MspDeInit(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_RESET; + hsc->gState = HAL_SMARTCARD_STATE_RESET; + hsc->RxState = HAL_SMARTCARD_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hsc); @@ -357,9 +362,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) + uint32_t tickstart = 0U; + + if(hsc->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -367,40 +374,30 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * /* Process Locked */ __HAL_LOCK(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } + hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); hsc->TxXferSize = Size; hsc->TxXferCount = Size; - while(hsc->TxXferCount > 0) + while(hsc->TxXferCount > 0U) { hsc->TxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - hsc->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hsc->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - /* Check if a non-blocking receive Process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } + + /* At end of Tx process, restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsc); @@ -422,9 +419,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) + uint32_t tickstart = 0U; + + if(hsc->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -433,38 +432,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p __HAL_LOCK(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); hsc->RxXferSize = Size; hsc->RxXferCount = Size; /* Check the remain data to be received */ - while(hsc->RxXferCount > 0) + while(hsc->RxXferCount > 0U) { hsc->RxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FF); + *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FFU); } - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } + /* At end of Rx process, restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsc); @@ -486,9 +473,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hsc->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -501,24 +489,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ hsc->TxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - + hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; + /* Process Unlocked */ __HAL_UNLOCK(hsc); + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC); + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE); return HAL_OK; } @@ -537,9 +517,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hsc->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -552,27 +533,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t hsc->RxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); + SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE); /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); + SET_BIT(hsc->Instance->CR3, USART_CR3_EIE); /* Enable the SMARTCARD Data Register not empty Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); + SET_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); return HAL_OK; } @@ -593,9 +566,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 { uint32_t *tmp; - if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hsc->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -608,21 +582,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 hsc->TxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } + hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; /* Set the SMARTCARD DMA transfer complete callback */ hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; /* Set the SMARTCARD error callback */ hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError; + + /* Set the DMA abort callback */ + hsc->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA Stream */ tmp = (uint32_t*)&pData; @@ -630,13 +599,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the SMARTCARD associated USART CR3 register */ - hsc->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); + SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -659,9 +628,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ { uint32_t *tmp; - if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hsc->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -673,32 +643,33 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ hsc->RxXferSize = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; /* Set the SMARTCARD DMA transfer complete callback */ hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; /* Set the SMARTCARD DMA error callback */ hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError; + + /* Set the DMA abort callback */ + hsc->hdmatx->XferAbortCallback = NULL; /* Enable the DMA Stream */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size); + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE); + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsc->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the SMARTCARD associated USART CR3 register */ - hsc->Instance->CR3 |= USART_CR3_DMAR; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); + SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -715,81 +686,132 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) { - /* SMARTCARD parity error interrupt occurred -------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_PEF); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - /* SMARTCARD frame error interrupt occurred ---------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_FEF); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - /* SMARTCARD noise error interrupt occurred ---------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_NEF); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_OREF); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - /* SMARTCARD receiver timeout interrupt occurred ----------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RTO) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_RTOF); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - /* Call SMARTCARD Error Call back function if need be ----------------------*/ - if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + uint32_t isrflags = READ_REG(hsc->Instance->ISR); + uint32_t cr1its = READ_REG(hsc->Instance->CR1); + uint32_t cr3its = READ_REG(hsc->Instance->CR3); + uint32_t dmarequest = 0x00U; + uint32_t errorflags = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if(errorflags == RESET) { - HAL_SMARTCARD_ErrorCallback(hsc); - } - - /* SMARTCARD in mode Receiver ----------------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE) != RESET)) - { - SMARTCARD_Receive_IT(hsc); - /* Clear RXNE interrupt flag */ - __HAL_SMARTCARD_SEND_REQ(hsc, SMARTCARD_RXDATA_FLUSH_REQUEST); + /* SMARTCARD in mode Receiver -------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + SMARTCARD_Receive_IT(hsc); + return; + } } - - /* SMARTCARD in mode Receiver, end of block interruption -------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_EOB) != RESET)) - { - hsc->State = HAL_SMARTCARD_STATE_READY; - HAL_SMARTCARD_RxCpltCallback(hsc); - /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information - * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_EOBF); - } + + /* If some errors occur */ + if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) + { + /* SMARTCARD parity error interrupt occurred ---------------------------*/ + if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; + } + + /* SMARTCARD frame error interrupt occurred ----------------------------*/ + if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; + } + + /* SMARTCARD noise error interrupt occurred ----------------------------*/ + if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + } + + /* SMARTCARD Over-Run interrupt occurred -------------------------------*/ + if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + } + /* Call the Error call Back in case of Errors */ + if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + { + /* SMARTCARD in mode Receiver -----------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + SMARTCARD_Receive_IT(hsc); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR); + if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + SMARTCARD_EndRxTransfer(hsc); + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel */ + if(hsc->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + + if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hsc->hdmarx->XferAbortCallback(hsc->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsc); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsc); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsc); + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ /* SMARTCARD in mode Transmitter -------------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_TC) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC) != RESET)) + if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { SMARTCARD_Transmit_IT(hsc); - } -} + return; + } + + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + /* Disable the SMARTCARD Transmit Complete Interrupt */ + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE); + + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + /* Tx process is ended, restore hsmartcard->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + + HAL_SMARTCARD_TxCpltCallback(hsc); + + return; + } +} /** * @brief Tx Transfer completed callbacks @@ -865,7 +887,11 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) { - return hsc->State; + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = hsc->gState; + temp2 = hsc->RxState; + + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); } /** @@ -892,41 +918,30 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) */ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) { - if((hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) { if(hsc->TxXferCount == 0) { /* Disable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC); + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE); - /* Check if a receive Process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - HAL_SMARTCARD_TxCpltCallback(hsc); - - return HAL_OK; - } - else - { - hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFF); - hsc->TxXferCount--; - - return HAL_OK; + /* Tx process is ended, restore hsmartcard->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; } + + HAL_SMARTCARD_TxCpltCallback(hsc); + + return HAL_OK; } else - { - return HAL_BUSY; + { + hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFFU); + hsc->TxXferCount--; + + return HAL_OK; } } @@ -939,42 +954,33 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) */ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) { - if((hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFF); + *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFFU); if(--hsc->RxXferCount == 0) { - while(HAL_IS_BIT_SET(hsc->Instance->ISR, SMARTCARD_FLAG_RXNE)) - { - } - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); - /* Check if a transmit Process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); - - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); - - hsc->State = HAL_SMARTCARD_STATE_READY; - } + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE); + + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + hsc->RxState = HAL_SMARTCARD_STATE_READY; HAL_SMARTCARD_RxCpltCallback(hsc); return HAL_OK; } + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -985,8 +991,8 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) */ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) { - uint32_t tmpreg = 0x00000000; - uint32_t clocksource = 0x00000000; + uint32_t tmpreg = 0x00000000U; + uint32_t clocksource = 0x00000000U; /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); @@ -1058,19 +1064,19 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK1: - hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PCLK2: - hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - hsc->Instance->BRR = (uint16_t)(HSI_VALUE / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HSI_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - hsc->Instance->BRR = (uint16_t)(LSE_VALUE / hsc->Init.BaudRate); + hsc->Instance->BRR = (uint16_t)((LSE_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); break; default: break; @@ -1084,15 +1090,19 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) */ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc) { + uint32_t tickstart = 0U; /* Initialize the SMARTCARD ErrorCode */ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ if((hsc->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) { return HAL_TIMEOUT; } @@ -1101,7 +1111,7 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc) if((hsc->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) { return HAL_TIMEOUT; } @@ -1111,7 +1121,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc) __HAL_UNLOCK(hsc); /* Initialize the SMARTCARD state*/ - hsc->State= HAL_SMARTCARD_STATE_READY; + hsc->gState= HAL_SMARTCARD_STATE_READY; + hsc->RxState= HAL_SMARTCARD_STATE_READY; return HAL_OK; } @@ -1178,71 +1189,72 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc) /** * @brief This function handles SMARTCARD Communication Timeout. - * @param hsc: SMARTCARD handle - * @param Flag: specifies the SMARTCARD flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param hsc SMARTCARD handle + * @param Flag specifies the SMARTCARD flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = 0x00; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET) + while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); - - hsc->State= HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_TIMEOUT; - } + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE); + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + hsc->gState= HAL_SMARTCARD_STATE_READY; + hsc->RxState= HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_TIMEOUT; } } } - else - { - while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); + return HAL_OK; +} - hsc->State= HAL_SMARTCARD_STATE_READY; +/* + * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). + * @param hsc: SMARTCARD handle. + * @retval None + */ +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; +} - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; +/** + * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion). + * @param hsc: SMARTCARD handle. + * @retval None + */ +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; } /** @@ -1251,35 +1263,16 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe * @retval None */ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ +{ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hsc->TxXferCount = 0; /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD associated USART CR3 register */ - hsc->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); + in the USART CR3 register */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); - /* Wait for SMARTCARD TC Flag */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, HAL_SMARTCARD_TXDMA_TIMEOUTVALUE) != HAL_OK) - { - /* Timeout Occurred */ - hsc->State = HAL_SMARTCARD_STATE_TIMEOUT; - HAL_SMARTCARD_ErrorCallback(hsc); - } - else - { - /* No Timeout */ - /* Check if a receive Process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - HAL_SMARTCARD_TxCpltCallback(hsc); - } + /* Enable the SMARTCARD Transmit Complete Interrupt */ + SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE); } /** @@ -1292,19 +1285,16 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hsc->RxXferCount = 0; + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the SMARTCARD associated USART CR3 register */ - hsc->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); - /* Check if a transmit Process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } + /* At end of Rx process, restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; HAL_SMARTCARD_RxCpltCallback(hsc); } @@ -1317,12 +1307,42 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->RxXferCount = 0; - hsc->TxXferCount = 0; - hsc->State= HAL_SMARTCARD_STATE_READY; - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; + hsc->RxXferCount = 0U; + hsc->TxXferCount = 0U; + hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Stop SMARTCARD DMA Tx request if ongoing */ + if ( (hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) ) + { + SMARTCARD_EndTxTransfer(hsc); + } + + /* Stop SMARTCARD DMA Rx request if ongoing */ + if ( (hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) ) + { + SMARTCARD_EndRxTransfer(hsc); + } + HAL_SMARTCARD_ErrorCallback(hsc); } + +/** + * @brief DMA SMARTCARD communication abort callback, when call by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma: DMA handle. + * @retval None + */ +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hsc->RxXferCount = 0U; + hsc->TxXferCount = 0U; + + HAL_SMARTCARD_ErrorCallback(hsc); +} + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h index 9e0107eccff..0b404a209a7 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -123,7 +123,43 @@ typedef struct }SMARTCARD_InitTypeDef; /** - * @brief SMARTCARD advanced features initalization structure definition + * @brief HAL SMARTCARD State structures definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. + * - gState contains SMARTCARD state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef struct { @@ -159,14 +195,23 @@ typedef struct */ typedef enum { - HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ + HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_SMARTCARD_StateTypeDef; @@ -175,11 +220,11 @@ typedef enum */ typedef enum { - SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - SMARTCARD_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */ }SMARTCARD_ClockSourceTypeDef; /** @@ -211,7 +256,12 @@ typedef struct HAL_LockTypeDef Lock; /* Locking object */ - __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /* SmartCard Error code */ @@ -228,13 +278,13 @@ typedef struct * @brief SMARTCARD Error Code * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20U) /*!< Receiver TimeOut error */ /** * @} */ @@ -277,7 +327,7 @@ typedef struct /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity * @{ */ -#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000) +#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000U) #define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /** * @} @@ -286,7 +336,7 @@ typedef struct /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ -#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000) +#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000U) #define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /** * @} @@ -295,7 +345,7 @@ typedef struct /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ -#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000) +#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000U) #define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /** * @} @@ -304,7 +354,7 @@ typedef struct /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling * @{ */ -#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000) +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000U) #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /** * @} @@ -315,7 +365,7 @@ typedef struct * @{ */ #define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000) +#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -323,7 +373,7 @@ typedef struct /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable * @{ */ -#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /** * @} @@ -343,14 +393,14 @@ typedef struct /** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization Type * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) +#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) /** * @} */ @@ -358,7 +408,7 @@ typedef struct /** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv * @{ */ -#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /** * @} @@ -367,7 +417,7 @@ typedef struct /** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv * @{ */ -#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /** * @} @@ -376,7 +426,7 @@ typedef struct /** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv * @{ */ -#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /** * @} @@ -385,7 +435,7 @@ typedef struct /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap * @{ */ -#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /** * @} @@ -394,7 +444,7 @@ typedef struct /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Disable * @{ */ -#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /** * @} @@ -403,7 +453,7 @@ typedef struct /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA Disable on Rx Error * @{ */ -#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /** * @} @@ -412,7 +462,7 @@ typedef struct /** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First * @{ */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /** * @} @@ -423,19 +473,19 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000) -#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000) -#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000) -#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000) -#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800) -#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080) -#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040) -#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020) -#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010) -#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008) -#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004) -#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002) -#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001) +#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000U) +#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000U) +#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000U) +#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000U) +#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800U) +#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U) +#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040U) +#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U) +#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U) +#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U) +#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004U) +#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002U) +#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001U) /** * @} */ @@ -451,18 +501,18 @@ typedef struct * @{ */ -#define SMARTCARD_IT_PE ((uint16_t)0x0028) -#define SMARTCARD_IT_TXE ((uint16_t)0x0727) -#define SMARTCARD_IT_TC ((uint16_t)0x0626) -#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) -#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) -#define SMARTCARD_IT_ERR ((uint16_t)0x0060) -#define SMARTCARD_IT_ORE ((uint16_t)0x0300) -#define SMARTCARD_IT_NE ((uint16_t)0x0200) -#define SMARTCARD_IT_FE ((uint16_t)0x0100) +#define SMARTCARD_IT_PE ((uint16_t)0x0028U) +#define SMARTCARD_IT_TXE ((uint16_t)0x0727U) +#define SMARTCARD_IT_TC ((uint16_t)0x0626U) +#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) +#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) +#define SMARTCARD_IT_ERR ((uint16_t)0x0060U) +#define SMARTCARD_IT_ORE ((uint16_t)0x0300U) +#define SMARTCARD_IT_NE ((uint16_t)0x0200U) +#define SMARTCARD_IT_FE ((uint16_t)0x0100U) -#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) -#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) +#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) +#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) /** * @} */ @@ -496,7 +546,7 @@ typedef struct /** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 SCAR CNT LSB POS * @{ */ -#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) +#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17U) /** * @} */ @@ -504,7 +554,7 @@ typedef struct /** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSBPOS * @{ */ -#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) +#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8U) /** * @} */ @@ -512,7 +562,7 @@ typedef struct /** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSBPOS * @{ */ -#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) +#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24U) /** * @} */ @@ -520,7 +570,7 @@ typedef struct /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask * @{ */ -#define SMARTCARD_IT_MASK ((uint16_t)0x001F) +#define SMARTCARD_IT_MASK ((uint16_t)0x001FU) /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c index a1deeb6748a..2f66763ced8 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following @@ -25,7 +25,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -128,12 +128,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Locked */ __HAL_LOCK(hsc); - hsc->State = HAL_SMARTCARD_STATE_BUSY; + hsc->gState = HAL_SMARTCARD_STATE_BUSY; /* Set the USART RTOEN bit */ hsc->Instance->CR2 |= USART_CR2_RTOEN; - hsc->State = HAL_SMARTCARD_STATE_READY; + hsc->gState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsc); @@ -151,12 +151,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Locked */ __HAL_LOCK(hsc); - hsc->State = HAL_SMARTCARD_STATE_BUSY; + hsc->gState = HAL_SMARTCARD_STATE_BUSY; /* Clear the USART RTOEN bit */ hsc->Instance->CR2 &= ~(USART_CR2_RTOEN); - hsc->State = HAL_SMARTCARD_STATE_READY; + hsc->gState = HAL_SMARTCARD_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsc); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h index 64907149879..139502ab19a 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c index 55aca7575f5..b4e3bb7593f 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration @@ -94,7 +94,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -151,7 +151,7 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart); /** * @} */ @@ -226,8 +226,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) HAL_SPDIFRX_MspInit(hspdif); } - /* SPDIFRX peripheral state is BUSY*/ - hspdif->State = HAL_SPDIFRX_STATE_BUSY; + /* SPDIFRX peripheral state is BUSY*/ + hspdif->State = HAL_SPDIFRX_STATE_BUSY; /* Disable SPDIFRX interface (IDLE State) */ __HAL_SPDIFRX_IDLE(hspdif); @@ -236,27 +236,26 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) tmpreg = hspdif->Instance->CR; tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | - SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | - SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | - SPDIFRX_CR_INSEL); - + SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | + SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL); + /* Sets the new configuration of the SPDIFRX peripheral */ tmpreg |= ((uint16_t) hspdif->Init.StereoMode | - hspdif->Init.InputSelection | - hspdif->Init.Retries | - hspdif->Init.WaitForActivity | - hspdif->Init.ChannelSelection | - hspdif->Init.DataFormat | - hspdif->Init.PreambleTypeMask | - hspdif->Init.ChannelStatusMask | - hspdif->Init.ValidityBitMask | - hspdif->Init.ParityErrorMask); - + hspdif->Init.InputSelection | + hspdif->Init.Retries | + hspdif->Init.WaitForActivity | + hspdif->Init.ChannelSelection | + hspdif->Init.DataFormat | + hspdif->Init.PreambleTypeMask | + hspdif->Init.ChannelStatusMask | + hspdif->Init.ValidityBitMask | + hspdif->Init.ParityErrorMask); + hspdif->Instance->CR = tmpreg; hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* SPDIFRX peripheral state is READY*/ + + /* SPDIFRX peripheral state is READY*/ hspdif->State = HAL_SPDIFRX_STATE_READY; return HAL_OK; @@ -277,23 +276,23 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) /* Check the parameters */ assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance)); - + hspdif->State = HAL_SPDIFRX_STATE_BUSY; /* Disable SPDIFRX interface (IDLE state) */ __HAL_SPDIFRX_IDLE(hspdif); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_SPDIFRX_MspDeInit(hspdif); hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* SPDIFRX peripheral state is RESET*/ + + /* SPDIFRX peripheral state is RESET*/ hspdif->State = HAL_SPDIFRX_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hspdif); - + return HAL_OK; } @@ -304,9 +303,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) */ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) { - /* Prevent unused argument(s) compilation warning */ + /* Prevent unused argument(s) compilation warning */ UNUSED(hspdif); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPDIFRX_MspInit could be implemented in the user file */ @@ -321,7 +320,7 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspdif); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPDIFRX_MspDeInit could be implemented in the user file */ @@ -356,23 +355,23 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF tmpreg = hspdif->Instance->CR; if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && - (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || - ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) + (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || + ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) { - return HAL_ERROR; + return HAL_ERROR; } tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | - SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); + SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); /* Sets the new configuration of the SPDIFRX peripheral */ tmpreg |= ((uint16_t) sDataFormat.StereoMode | - sDataFormat.DataFormat | - sDataFormat.PreambleTypeMask | - sDataFormat.ChannelStatusMask | - sDataFormat.ValidityBitMask | - sDataFormat.ParityErrorMask); - + sDataFormat.DataFormat | + sDataFormat.PreambleTypeMask | + sDataFormat.ChannelStatusMask | + sDataFormat.ValidityBitMask | + sDataFormat.ParityErrorMask); + hspdif->Instance->CR = tmpreg; return HAL_OK; @@ -436,8 +435,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) { - - if((pData == NULL ) || (Size == 0)) + uint32_t tickstart = 0U; + + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -447,25 +447,31 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin /* Process Locked */ __HAL_LOCK(hspdif); - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Start synchronisation */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } + hspdif->State = HAL_SPDIFRX_STATE_BUSY; + + /* Start synchronisation */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - /* Receive data flow */ - while(Size > 0) - { + while(Size > 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until RXNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -473,10 +479,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin (*pData++) = hspdif->Instance->DR; Size--; } - + /* SPDIFRX ready */ hspdif->State = HAL_SPDIFRX_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -499,8 +505,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) { - - if((pData == NULL ) || (Size == 0)) + uint32_t tickstart = 0U; + + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -510,25 +517,31 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, /* Process Locked */ __HAL_LOCK(hspdif); - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - - /* Receive control flow */ - while(Size > 0) + hspdif->State = HAL_SPDIFRX_STATE_BUSY; + + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); + + /* Receive control flow */ + while(Size > 0U) { + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait until CSRNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK) + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -536,10 +549,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, (*pData++) = hspdif->Instance->CSR; Size--; } - + /* SPDIFRX ready */ hspdif->State = HAL_SPDIFRX_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -550,6 +563,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, return HAL_BUSY; } } + /** * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt * @param hspdif: SPDIFRX handle @@ -559,53 +573,58 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { - if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX)) + uint32_t tickstart = 0U; + + if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hspdif); - + hspdif->pRxBuffPtr = pData; hspdif->RxXferSize = Size; hspdif->RxXferCount = Size; - + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; /* Check if a receive process is ongoing or not */ - hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; - - + hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; + + /* Enable the SPDIFRX PE Error Interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - + /* Enable the SPDIFRX OVR Error Interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - + /* Process Unlocked */ __HAL_UNLOCK(hspdif); - + /* Enable the SPDIFRX RXNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); - - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK) + + if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - /* Start reception */ + + /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); - } - + } + return HAL_OK; } else @@ -623,53 +642,58 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { - if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) + uint32_t tickstart = 0U; + + if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hspdif); - + hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; hspdif->CsXferCount = Size; - + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; /* Check if a receive process is ongoing or not */ - hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; - - + hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; + + /* Enable the SPDIFRX PE Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + /* Enable the SPDIFRX OVR Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + /* Process Unlocked */ __HAL_UNLOCK(hspdif); - + /* Enable the SPDIFRX CSRNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK) + + if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - /* Start reception */ + + /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); - } - + } + return HAL_OK; } else @@ -687,8 +711,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { + uint32_t tickstart = 0U; - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -698,7 +723,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, hspdif->pRxBuffPtr = pData; hspdif->RxXferSize = Size; hspdif->RxXferCount = Size; - + /* Process Locked */ __HAL_LOCK(hspdif); @@ -713,31 +738,34 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, /* Set the DMA error callback */ hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; - + /* Enable the DMA request */ HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size); - + /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ - hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; - - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK) + hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; + + if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - /* Start reception */ + + /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); - } + } /* Process Unlocked */ __HAL_UNLOCK(hspdif); - + return HAL_OK; } else @@ -755,18 +783,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { + uint32_t tickstart = 0U; - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) + if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) { hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; hspdif->CsXferCount = Size; - + /* Process Locked */ __HAL_LOCK(hspdif); @@ -781,28 +810,31 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd /* Set the DMA error callback */ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; - + /* Enable the DMA request */ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size); - + /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; - if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00)) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE) != HAL_OK) + if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - - /* Start reception */ + + /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); - } - + } + /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -853,41 +885,40 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET)) { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); + __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); SPDIFRX_ReceiveDataFlow_IT(hspdif); } - /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/ + /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET)) { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); + __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); SPDIFRX_ReceiveControlFlow_IT(hspdif); } - + /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR); - /* Change the SPDIFRX error code */ + /* Change the SPDIFRX error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR; - /* the transfer is not stopped */ + /* the transfer is not stopped */ HAL_SPDIFRX_ErrorCallback(hspdif); } - - /* SPDIFRX Parity error interrupt occurred ---------------------------------*/ + + /* SPDIFRX Parity error interrupt occurred ---------------------------------*/ if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR); - /* Change the SPDIFRX error code */ + /* Change the SPDIFRX error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE; - - /* the transfer is not stopped */ + + /* the transfer is not stopped */ HAL_SPDIFRX_ErrorCallback(hspdif); } - } /** @@ -899,7 +930,7 @@ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspdif); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file */ @@ -914,7 +945,7 @@ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspdif); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file */ @@ -929,7 +960,7 @@ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspdif); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file */ @@ -944,7 +975,7 @@ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspdif); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file */ @@ -959,7 +990,7 @@ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspdif); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPDIFRX_ErrorCallback could be implemented in the user file */ @@ -1089,7 +1120,6 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) HAL_SPDIFRX_ErrorCallback(hspdif); } - /** * @brief Receive an amount of data (Data Flow) with Interrupt * @param hspdif: SPDIFRX handle @@ -1097,22 +1127,22 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) { - /* Receive data */ - (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR; - hspdif->RxXferCount--; - - if(hspdif->RxXferCount == 0) - { - /* Disable RXNE/PE and OVR interrupts */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - HAL_SPDIFRX_RxCpltCallback(hspdif); - } + /* Receive data */ + (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR; + hspdif->RxXferCount--; + + if(hspdif->RxXferCount == 0) + { + /* Disable RXNE/PE and OVR interrupts */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + HAL_SPDIFRX_RxCpltCallback(hspdif); + } } /** @@ -1122,22 +1152,22 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) */ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) { - /* Receive data */ - (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR; - hspdif->CsXferCount--; - - if(hspdif->CsXferCount == 0) - { - /* Disable CSRNE interrupt */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - HAL_SPDIFRX_CxCpltCallback(hspdif); - } + /* Receive data */ + (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR; + hspdif->CsXferCount--; + + if(hspdif->CsXferCount == 0) + { + /* Disable CSRNE interrupt */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + HAL_SPDIFRX_CxCpltCallback(hspdif); + } } /** @@ -1146,15 +1176,11 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) * @param Flag: Flag checked * @param Status: Value of the flag expected * @param Timeout: Duration of the timeout + * @param tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set */ if(Status == RESET) { @@ -1163,7 +1189,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); @@ -1173,12 +1199,12 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - + hspdif->State= HAL_SPDIFRX_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hspdif); - + return HAL_TIMEOUT; } } @@ -1191,22 +1217,22 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - + hspdif->State= HAL_SPDIFRX_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hspdif); - + return HAL_TIMEOUT; } } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h index a96e73213f4..8d612a4aafa 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SPDIFRX HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -126,12 +126,12 @@ typedef struct */ typedef enum { - HAL_SPDIFRX_STATE_RESET = 0x00, /*!< SPDIFRX not yet initialized or disabled */ - HAL_SPDIFRX_STATE_READY = 0x01, /*!< SPDIFRX initialized and ready for use */ - HAL_SPDIFRX_STATE_BUSY = 0x02, /*!< SPDIFRX internal process is ongoing */ - HAL_SPDIFRX_STATE_BUSY_RX = 0x03, /*!< SPDIFRX internal Data Flow RX process is ongoing */ - HAL_SPDIFRX_STATE_BUSY_CX = 0x04, /*!< SPDIFRX internal Control Flow RX process is ongoing */ - HAL_SPDIFRX_STATE_ERROR = 0x07 /*!< SPDIFRX error state */ + HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */ + HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */ + HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */ + HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */ + HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */ + HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */ }HAL_SPDIFRX_StateTypeDef; /** @@ -187,12 +187,12 @@ typedef struct /** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code * @{ */ -#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */ -#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004) /*!< Parity error */ -#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */ -#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010) /*!< Unknown Error error */ +#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */ +#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */ +#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ +#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */ /** * @} */ @@ -200,10 +200,10 @@ typedef struct /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection * @{ */ -#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000) -#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000) -#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000) -#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000) +#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U) +#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U) +#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U) +#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U) /** * @} */ @@ -211,10 +211,10 @@ typedef struct /** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries * @{ */ -#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000) -#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000) -#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000) -#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000) +#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U) +#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U) +#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U) +#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U) /** * @} */ @@ -222,7 +222,7 @@ typedef struct /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity * @{ */ -#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000) +#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U) #define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA) /** * @} @@ -231,7 +231,7 @@ typedef struct /** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask * @{ */ -#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000) +#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U) #define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK) /** * @} @@ -240,7 +240,7 @@ typedef struct /** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask * @{ */ -#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */ +#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */ #define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/ /** * @} @@ -249,7 +249,7 @@ typedef struct /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask * @{ */ -#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000) +#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) #define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) /** * @} @@ -258,7 +258,7 @@ typedef struct /** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask * @{ */ -#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000) +#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U) #define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK) /** * @} @@ -267,7 +267,7 @@ typedef struct /** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection * @{ */ -#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000) +#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U) #define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL) /** * @} @@ -276,9 +276,9 @@ typedef struct /** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format * @{ */ -#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000) -#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010) -#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020) +#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U) +#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U) +#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U) /** * @} */ @@ -286,7 +286,7 @@ typedef struct /** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode * @{ */ -#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000) +#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U) #define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO) /** * @} @@ -296,8 +296,8 @@ typedef struct * @{ */ -#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC) -#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001) +#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU) +#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U) #define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c index add07bc7d0c..f8852c5bed9 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c @@ -2,15 +2,16 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SPI HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -21,7 +22,7 @@ (#) Declare a SPI_HandleTypeDef handle structure, for example: SPI_HandleTypeDef hspi; - (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: (##) Enable the SPIx interface clock (##) SPI pins configuration (+++) Enable the clock for the SPI GPIOs @@ -42,7 +43,7 @@ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customised HAL_SPI_MspInit() API. + by calling the customized HAL_SPI_MspInit() API. [..] Circular mode restriction: (#) The DMA circular mode cannot be used when the SPI is configured in these modes: @@ -56,7 +57,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -82,15 +83,15 @@ * ****************************************************************************** */ - + /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" - + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -/** @defgroup SPI SPI +/** @defgroup SPI SPI * @brief SPI HAL module driver * @{ */ @@ -106,10 +107,10 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SPI_Private_Functions +/** @defgroup SPI_Private_Functions SPI Private Functions * @{ */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -119,20 +120,23 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout); static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout); static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); @@ -184,8 +188,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ */ /** - * @brief Initializes the SPI according to the specified parameters - * in the SPI_InitTypeDef and create the associated handle. + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status @@ -212,9 +216,27 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); +#if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } + /* Align the CRC Length on the data size */ + if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } +#endif if(hspi->State == HAL_SPI_STATE_RESET) { @@ -247,20 +269,6 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } - /* Align the CRC Length on the data size */ - if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - /* CRC Length aligned on the data size : value set by default */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; - } - else - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; - } - } - /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit, CRC calculation state, CRC Length */ @@ -278,9 +286,11 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | hspi->Init.DataSize ) | frxth; +#if (USE_SPI_CRC != 0U) /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ /* Configure : CRC Polynomial */ - hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); +#endif hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State= HAL_SPI_STATE_READY; @@ -289,7 +299,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } /** - * @brief DeInitializes the SPI peripheral + * @brief DeInitialize the SPI peripheral. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status @@ -307,11 +317,6 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_BUSY; - /* check flag before the SPI disable */ - SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT); - SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT); - SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT); - /* Disable the SPI Peripheral Clock */ __HAL_SPI_DISABLE(hspi); @@ -332,14 +337,14 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) - { +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_MspInit should be implemented in the user file - */ + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ } /** @@ -348,11 +353,11 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_MspDeInit should be implemented in the user file */ @@ -369,6 +374,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) ============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the SPI data transfers. @@ -395,7 +401,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ /** - * @brief Transmit an amount of data in blocking mode + * @brief Transmit an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -405,6 +411,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = HAL_GetTick(); + HAL_StatusTypeDef errorcode = HAL_OK; + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ @@ -412,18 +421,14 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if(hspi->State != HAL_SPI_STATE_READY) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_BUSY; + errorcode = HAL_BUSY; + goto error; } - + if((pData == NULL ) || (Size == 0)) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_ERROR; + errorcode = HAL_ERROR; + goto error; } /* Set the transaction information */ @@ -442,11 +447,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint SPI_1LINE_TX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -462,16 +469,21 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint while (hspi->TxXferCount > 0) { /* Wait until TXE flag is set to send data */ - if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } } - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; } } /* Transmit data in 8 Bit mode */ @@ -479,68 +491,68 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { while (hspi->TxXferCount > 0) { - if(hspi->TxXferCount != 0x1) + /* Wait until TXE flag is set to send data */ + if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + if(hspi->TxXferCount > 1) { - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2; + } + else + { + *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; } - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; } else { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK) + /* Timeout management */ + if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) { - return HAL_TIMEOUT; + errorcode = HAL_TIMEOUT; + goto error; } - *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; } } } +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1|= SPI_CR1_CRCNEXT; } +#endif /* Check the end of the transaction */ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) { - return HAL_TIMEOUT; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else { - return HAL_OK; + errorcode = HAL_ERROR; } + +error: + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Receive an amount of data in blocking mode + * @brief Receive an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -550,28 +562,35 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) __IO uint16_t tmpreg; - - if(hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } +#endif + uint32_t tickstart = HAL_GetTick(); + HAL_StatusTypeDef errorcode = HAL_OK; if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the transmitReceive process */ + /* in this case we call the TransmitReceive process */ + /* Process Locked */ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); } - + /* Process Locked */ __HAL_LOCK(hspi); - + + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if((pData == NULL ) || (Size == 0)) + { + errorcode = HAL_ERROR; + goto error; + } + hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pData; @@ -581,6 +600,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->TxXferSize = 0; hspi->TxXferCount = 0; +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { @@ -588,6 +608,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* this is done to handle the CRCNEXT before the latest data */ hspi->RxXferCount--; } +#endif /* Set the Rx Fido threshold */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) @@ -617,68 +638,88 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Receive data in 8 Bit mode */ if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) { - while(hspi->RxXferCount > 1) + /* Transfer loop */ + while(hspi->RxXferCount > 0) { - /* Wait until the RXNE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + /* Check the RXNE flag */ + if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) { - return HAL_TIMEOUT; + /* read the received data */ + (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } } - (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; - hspi->RxXferCount--; } } - else /* Receive data in 16 Bit mode */ - { - while(hspi->RxXferCount > 1 ) + else + { + /* Transfer loop */ + while(hspi->RxXferCount > 0) { - /* Wait until RXNE flag is reset to read data */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + /* Check the RXNE flag */ + if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) { - return HAL_TIMEOUT; + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; } - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } + else + { + /* Timeout management */ + if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } } - - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; - } - /* Wait until RXNE flag is set */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Receive last data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - } - /* Receive last data in 8 Bit mode */ - else - { - (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; - } - hspi->RxXferCount--; - - /* Read CRC from DR to close CRC calculation process */ +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + /* freeze the CRC before the latest data */ + hspi->Instance->CR1|= SPI_CR1_CRCNEXT; + + /* Read the latest data */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { - /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + /* the latest data has not been received */ + errorcode = HAL_TIMEOUT; + goto error; } + + /* Receive last data in 16 Bit mode */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + /* Flag Error*/ + hspi->ErrorCode = HAL_SPI_ERROR_CRC; + errorcode = HAL_TIMEOUT; + goto error; + } + + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { tmpreg = hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ } @@ -692,48 +733,45 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + hspi->ErrorCode = HAL_SPI_ERROR_CRC; + errorcode = HAL_TIMEOUT; + goto error; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ } } } - +#endif + /* Check the end of the transaction */ if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) { - return HAL_TIMEOUT; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - hspi->State = HAL_SPI_STATE_READY; - +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->ErrorCode|= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - +#endif + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else { - return HAL_OK; + errorcode = HAL_ERROR; } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in blocking mode + * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer @@ -744,25 +782,32 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg = 0; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg; +#endif uint32_t tickstart = HAL_GetTick(); - + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + + HAL_StatusTypeDef errorcode = HAL_OK; + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - if(hspi->State != HAL_SPI_STATE_READY) + + /* Process Locked */ + __HAL_LOCK(hspi); + + if(hspi->State != HAL_SPI_STATE_READY) { - return HAL_BUSY; + errorcode = HAL_BUSY; + goto error; } - + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { - return HAL_ERROR; + errorcode = HAL_ERROR; + goto error; } - - /* Process Locked */ - __HAL_LOCK(hspi); - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pRxData; @@ -772,13 +817,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxXferCount = Size; hspi->TxXferSize = Size; +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif - /* Set the Rx Fido threshold */ + /* Set the Rx Fifo threshold */ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) { /* set fiforxthreshold according the reception data length: 16bit */ @@ -803,34 +850,40 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) { /* Check TXE flag */ - if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))) { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } + } +#endif } - /* Check RXNE flag */ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) { *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 1U; } - if(Timeout != HAL_MAX_DELAY) + if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hspi->State = HAL_SPI_STATE_READY; - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; - } + errorcode = HAL_TIMEOUT; + goto error; } } } @@ -840,7 +893,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) { /* check TXE flag */ - if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))) { if(hspi->TxXferCount > 1) { @@ -852,13 +905,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; } +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif } /* Wait until RXNE flag is reset */ @@ -879,20 +941,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; } } - if(Timeout != HAL_MAX_DELAY) + if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hspi->State = HAL_SPI_STATE_READY; - __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; - } + errorcode = HAL_TIMEOUT; + goto error; } } } +#if (USE_SPI_CRC != 0U) /* Read CRC from DR to close CRC calculation process */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { @@ -901,6 +962,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + errorcode = HAL_TIMEOUT; + goto error; } if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -919,6 +982,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + errorcode = HAL_TIMEOUT; + goto error; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ @@ -926,42 +991,36 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } } - /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hspi->State = HAL_SPI_STATE_READY; - /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->ErrorCode|= HAL_SPI_ERROR_CRC; /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; + + errorcode = HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; +#endif + + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - else + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - return HAL_OK; + errorcode = HAL_ERROR; } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -970,78 +1029,76 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - if(hspi->State == HAL_SPI_STATE_READY) + + /* Process Locked */ + __HAL_LOCK(hspi); + + if((pData == NULL) || (Size == 0)) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + errorcode = HAL_ERROR; + goto error; + } - /* Set the function for IT treatement */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - hspi->RxISR = NULL; - hspi->TxISR = SPI_TxISR_16BIT; - } - else - { - hspi->RxISR = NULL; - hspi->TxISR = SPI_TxISR_8BIT; - } - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* prepare the transfer */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + hspi->RxISR = NULL; - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->TxISR = SPI_TxISR_16BIT; } else { - return HAL_BUSY; + hspi->TxISR = SPI_TxISR_8BIT; } -} + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + __HAL_UNLOCK(hspi); + return errorcode; +} /** - * @brief Receive an amount of data in no-blocking mode with Interrupt + * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -1050,103 +1107,101 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - if(hspi->State == HAL_SPI_STATE_READY) + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if(hspi->State != HAL_SPI_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } + errorcode = HAL_BUSY; + goto error; + } + if((pData == NULL) || (Size == 0)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* the receive process is not supported in 2Lines direction master mode */ - /* in this we call the transmitReceive process */ - return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); - } - - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } - else - { - hspi->CRCSize = 0; - } - - /* check the data size to adapt Rx threshold and the set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - /* set fiforxthreshold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_16BIT; - hspi->TxISR = NULL; - } - else - { - /* set fiforxthreshold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_8BIT; - hspi->TxISR = NULL; - } - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { /* Process Unlocked */ __HAL_UNLOCK(hspi); - - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + /* the receive process is not supported in 2Lines direction master mode */ + /* in this we call the TransmitReceive process */ + return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); + } + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1; + if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); + hspi->CRCSize = 2; } - - return HAL_OK; } else { - return HAL_BUSY; + hspi->CRCSize = 0; + } + + hspi->TxISR = NULL; + /* check the data size to adapt Rx threshold and the set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + /* set fiforxthresold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + /* set fiforxthresold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); } +#endif + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer @@ -1156,95 +1211,98 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - if((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + + /* Process locked */ + __HAL_LOCK(hspi); + + if(!((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hspi); - - hspi->CRCSize = 0; - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } - - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Set the function for IT treatement */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) - { - hspi->RxISR = SPI_2linesRxISR_16BIT; - hspi->TxISR = SPI_2linesTxISR_16BIT; - } - else - { - hspi->RxISR = SPI_2linesRxISR_8BIT; - hspi->TxISR = SPI_2linesTxISR_8BIT; - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - /* check if packing mode is enabled and if there is more than 2 data to receive */ - if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) - { - /* set fiforxthreshold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* set fiforxthreshold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + errorcode = HAL_BUSY; + goto error; + } + + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + errorcode = HAL_ERROR; + goto error; + } + + hspi->CRCSize = 0; + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1; + if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); + hspi->CRCSize = 2; } - - return HAL_OK; + } + + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif + + /* check if packing mode is enabled and if there is more than 2 data to receive */ + if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) + { + /* set fiforxthresold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - return HAL_BUSY; + /* set fiforxthresold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit an amount of data in no-blocking mode with DMA + * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -1252,22 +1310,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ +{ + HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - if(hspi->State != HAL_SPI_STATE_READY) + /* Process Locked */ + __HAL_LOCK(hspi); + + if(hspi->State != HAL_SPI_STATE_READY) { - return HAL_BUSY; + errorcode = HAL_BUSY; + goto error; } - + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + errorcode = HAL_ERROR; + goto error; } - - /* Process Locked */ - __HAL_LOCK(hspi); - + hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = pData; @@ -1276,28 +1337,33 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, hspi->pRxBuffPtr = (uint8_t *)NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; - + /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_TX(hspi); } - + +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } - +#endif + /* Set the SPI TxDMA Half transfer complete callback */ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - + /* Set the SPI TxDMA transfer complete callback */ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; - + /* Set the DMA error callback */ hspi->hdmatx->XferErrorCallback = SPI_DMAError; - + + /* Set the DMA abort callback */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); /* packing mode is enabled only if the DMA setting is HALWORD */ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) @@ -1314,47 +1380,57 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; } } - + + /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */ + SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE)); + SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); + /* Enable the Tx DMA channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Check if the SPI is already enabled */ + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Enable Tx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; - + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : /* Process Unlocked */ __HAL_UNLOCK(hspi); - - return HAL_OK; + return errorcode; } /** -* @brief Receive an amount of data in no-blocking mode with DMA -* @param hspi: SPI handle -* @param pData: pointer to data buffer -* @param Size: amount of data to be sent -* @retval HAL status -*/ + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + if(hspi->State != HAL_SPI_STATE_READY) { - return HAL_BUSY; + errorcode = HAL_BUSY; + goto error; } - + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + errorcode = HAL_ERROR; + goto error; } - - /* Process Locked */ - __HAL_LOCK(hspi); hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1370,31 +1446,32 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Unlocked */ __HAL_UNLOCK(hspi); /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the transmitReceive process */ + /* in this case we call the TransmitReceive process */ return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); } - + /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } - + +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } - +#endif + /* packing mode management is enabled by the DMA settings */ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { - /* Process Locked */ - __HAL_UNLOCK(hspi); /* Restriction the DMA data received is not allowed in this mode */ - return HAL_ERROR; + errorcode = HAL_ERROR; + goto error; } - + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) { @@ -1406,37 +1483,44 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - + /* Set the SPI RxDMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; /* Set the SPI Rx DMA transfer complete callback */ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - + /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Enable Rx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; - + + /* Set the DMA abort callback */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + + /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */ + SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE)); + SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + /* Enable the Rx DMA channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - - return HAL_OK; + +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer @@ -1447,149 +1531,156 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - if((hspi->State == HAL_SPI_STATE_READY) || - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + + /* Process locked */ + __HAL_LOCK(hspi); + + if(!((hspi->State == HAL_SPI_STATE_READY) || + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hspi); - - /* check if the transmit Receive function is not called by a receive master */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Reset CRC Calculation + increase the rxsize */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - /* Reset the threshold bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - - /* the packing mode management is enabled by the DMA settings according the spi data size */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else + errorcode = HAL_BUSY; + goto error; + } + + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* check if the transmit Receive function is not called by a receive master */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation + increase the rxsize */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif + + /* Reset the threshold bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); + + /* the packing mode management is enabled by the DMA settings according the spi data size */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* set fiforxthresold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthreshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + if((hspi->TxXferSize & 0x1) == 0x0) { - if((hspi->TxXferSize & 0x1) == 0x0 ) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = hspi->TxXferCount >> 1; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; - } + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = hspi->TxXferCount >> 1; } - - if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + else { - /* set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - /* Size must include the CRC length */ - if((hspi->RxXferCount & 0x1) == 0x0 ) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = hspi->RxXferCount >> 1; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; - } + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; } - } - - /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is - the reception request (RXNE) */ - if(hspi->State == HAL_SPI_STATE_BUSY_RX) - { - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; } - else - { - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - } - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Enable Rx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; - - /* Enable the Rx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - hspi->hdmatx->XferHalfCpltCallback = NULL; - hspi->hdmatx->XferCpltCallback = NULL; - - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - } - else - { - hspi->hdmatx->XferErrorCallback = NULL; - } - - /* Enable the Tx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); + /* set fiforxthresold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if((hspi->RxXferCount & 0x1) == 0x0 ) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; + } } - - /* Enable Tx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; - - return HAL_OK; + } + + /* Set the SPI Rx DMA transfer complete callback if the transfer request is a + reception request (RXNE) */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; } else { - return HAL_BUSY; + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA abort callback */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + + /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */ + SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE)); + SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Enable the Rx DMA channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA abort callback */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + + /* Enable the Tx DMA channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Pauses the DMA Transfer. + * @brief Pause the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status @@ -1637,11 +1728,11 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() - */ - + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + /* Abort the SPI DMA tx Stream */ if(hspi->hdmatx != NULL) { @@ -1667,26 +1758,29 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + /* SPI in mode Receiver ----------------------------------------------------*/ - if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) && - (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET)) + if(((itflag & SPI_FLAG_OVR) == RESET) && + ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) { hspi->RxISR(hspi); return; } - + /* SPI in mode Transmitter ---------------------------------------------------*/ - if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET)) - { + if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) + { hspi->TxISR(hspi); return; } - - /* SPI in ERROR Treatment ---------------------------------------------------*/ - if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) + + /* SPI in Error Treatment ---------------------------------------------------*/ + if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) { /* SPI Overrun error interrupt occurred -------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + if((itflag & SPI_FLAG_OVR) != RESET) { if(hspi->State != HAL_SPI_STATE_BUSY_TX) { @@ -1698,31 +1792,79 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) return; } } - + /* SPI Mode Fault error interrupt occurred -------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) - { + if((itflag & SPI_FLAG_MODF) != RESET) + { hspi->ErrorCode |= HAL_SPI_ERROR_MODF; __HAL_SPI_CLEAR_MODFFLAG(hspi); } - + /* SPI Frame error interrupt occurred ----------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) - { + if((itflag & SPI_FLAG_FRE) != RESET) + { hspi->ErrorCode |= HAL_SPI_ERROR_FRE; __HAL_SPI_CLEAR_FREFLAG(hspi); } - - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_ErrorCallback(hspi); - - return; + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* All SPI errors are treated as Blocking errors : transfer is aborted. + Set the SPI state to ready so as to be able to restart the process, + Disable Rx/Tx Interrupts, and disable DMA Rx/Tx requests, if ongoing */ + + /* Disable TXE, RXNE, MODF, OVR, FRE, and CRCERR (Master mode fault, Overrun error, TI frame format error, CRC protocol error) interrupts */ + CLEAR_BIT(hspi->Instance->CR1, (SPI_CR2_RXNEIE | SPI_CR2_TXEIE | SPI_CR2_ERRIE)); + CLEAR_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR)); + + /* Restore SPI State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if(hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + /* Call Directly hspi->hdmarx->XferAbortCallback function in case of error */ + hspi->hdmarx->XferAbortCallback(hspi->hdmarx); + } + } + /* Abort the SPI DMA Tx channel */ + if(hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + /* Call Directly hspi->hdmatx->XferAbortCallback function in case of error */ + hspi->hdmatx->XferAbortCallback(hspi->hdmatx); + } + } + } + else + { + /* Call user error callback */ + HAL_SPI_ErrorCallback(hspi); + } + } } } /** - * @brief Tx Transfer completed callback + * @brief Tx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -1731,14 +1873,14 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxCpltCallback should be implemented in the user file - */ + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ } /** - * @brief Rx Transfer completed callbacks + * @brief Rx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -1747,14 +1889,14 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxCpltCallback should be implemented in the user file - */ + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ } /** - * @brief Tx and Rx Transfer completed callback + * @brief Tx and Rx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -1763,14 +1905,14 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxCpltCallback should be implemented in the user file - */ + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ } /** - * @brief Tx Half Transfer completed callback + * @brief Tx Half Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -1779,14 +1921,14 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxHalfCpltCallback should be implemented in the user file - */ + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ } /** - * @brief Rx Half Transfer completed callback + * @brief Rx Half Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -1795,14 +1937,14 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file - */ + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ } /** - * @brief Tx and Rx Half Transfer callback + * @brief Tx and Rx Half Transfer callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -1811,34 +1953,30 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file - */ + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ } /** - * @brief SPI error callback + * @brief SPI error callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_ErrorCallback should be implemented in the user file - */ + the HAL_SPI_ErrorCallback should be implemented in the user file + */ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occurred - */ -} - -/** - * @} + and user can use HAL_SPI_GetError() API to check the latest error occurred */ +} /** * @} @@ -1860,18 +1998,19 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) */ /** - * @brief Return the SPI state + * @brief Return the SPI handle state. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) { + /* Return SPI handle state */ return hspi->State; } /** - * @brief Return the SPI error code + * @brief Return the SPI error code. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format @@ -1885,16 +2024,18 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) * @} */ + /** * @} */ -/** @defgroup SPI_Private_Functions SPI Private Functions +/** @addtogroup SPI_Private_Functions + * @brief Private functions * @{ */ /** - * @brief DMA SPI transmit process complete callback + * @brief DMA SPI transmit process complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1909,7 +2050,13 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */ + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); @@ -1928,19 +2075,21 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI receive process complete callback + * @brief DMA SPI receive process complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO uint16_t tmpreg; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* DMA Normal mode */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { + { + +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg; /* CRC handling */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { @@ -1948,10 +2097,10 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { + { tmpreg = hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ } @@ -1959,76 +2108,71 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ - + if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ } - } + } } - - /* Disable Rx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - +#endif + + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Check the end of the transaction */ - SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); - + if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + hspi->RxXferCount = 0; hspi->State = HAL_SPI_STATE_READY; - + +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->ErrorCode|= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_RxCpltCallback(hspi); } - else +#endif + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - HAL_SPI_RxCpltCallback(hspi); - } - else - { - HAL_SPI_ErrorCallback(hspi); - } + HAL_SPI_ErrorCallback(hspi); + return; } } - else - { - HAL_SPI_RxCpltCallback(hspi); - } + HAL_SPI_RxCpltCallback(hspi); } /** - * @brief DMA SPI transmit receive process complete callback + * @brief DMA SPI transmit receive process complete callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO int16_t tmpreg; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg; /* CRC handling */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) - { + { if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ @@ -2038,48 +2182,46 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ } - } - + } +#endif + /* Check the end of the transaction */ - SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT); - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->TxXferCount = 0; hspi->RxXferCount = 0; hspi->State = HAL_SPI_STATE_READY; - + +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { - hspi->ErrorCode = HAL_SPI_ERROR_CRC; + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); } - else - { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - HAL_SPI_TxRxCpltCallback(hspi); - } - else - { - HAL_SPI_ErrorCallback(hspi); - } +#endif + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + return; } + HAL_SPI_TxRxCpltCallback(hspi); } /** - * @brief DMA SPI half transmit process complete callback + * @brief DMA SPI half transmit process complete callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -2087,12 +2229,11 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_SPI_TxHalfCpltCallback(hspi); } /** - * @brief DMA SPI half receive process complete callback + * @brief DMA SPI half receive process complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -2100,12 +2241,11 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_SPI_RxHalfCpltCallback(hspi); } /** - * @brief DMA SPI Half transmit receive process complete callback + * @brief DMA SPI half transmit receive process complete callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -2113,12 +2253,11 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_SPI_TxRxHalfCpltCallback(hspi); } /** - * @brief DMA SPI communication error callback + * @brief DMA SPI communication error callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -2136,7 +2275,22 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief Rx Handler for Transmit and Receive in Interrupt mode + * @brief DMA SPI communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma: DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2161,17 +2315,19 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); hspi->RxXferCount--; } - + /* check end of the reception */ if(hspi->RxXferCount == 0) { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_2linesRxISR_8BITCRC; return; } - +#endif + /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -2182,21 +2338,20 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } } +#if (USE_SPI_CRC != 0U) /** - * @brief Rx Handler for Transmit and Receive in Interrupt mode + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg; - - tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); UNUSED(tmpreg); /* To avoid GCC warning */ hspi->CRCSize--; - + /* check end of the reception */ if(hspi->CRCSize == 0) { @@ -2209,9 +2364,10 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) } } } +#endif /** - * @brief Tx Handler for Transmit and Receive in Interrupt mode + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2227,30 +2383,33 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /* Transmit data in 8 Bit mode */ else - { + { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } - + /* check the end of the transmission */ if(hspi->TxXferCount == 0) { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } +#endif + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - + if(hspi->RxXferCount == 0) - { + { SPI_CloseRxTx_ISR(hspi); } } } /** - * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2264,12 +2423,14 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) if(hspi->RxXferCount == 0) { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_2linesRxISR_16BITCRC; return; } - +#endif + /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -2280,8 +2441,9 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } } +#if (USE_SPI_CRC != 0U) /** - * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2297,9 +2459,10 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) SPI_CloseRxTx_ISR(hspi); } +#endif /** - * @brief Tx Handler for Transmit and Receive in Interrupt mode + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2310,14 +2473,17 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; - + /* Enable CRC Transmission */ if(hspi->TxXferCount == 0) { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } +#endif + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); @@ -2328,8 +2494,9 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } } +#if (USE_SPI_CRC != 0U) /** - * @brief Manage the CRC receive in Interrupt context + * @brief Manage the CRC 8-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2338,18 +2505,20 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { __IO uint8_t tmpreg; tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + UNUSED(tmpreg); /* To avoid GCC warning */ hspi->CRCSize--; - + if(hspi->CRCSize == 0) - { + { SPI_CloseRx_ISR(hspi); } } +#endif /** - * @brief Manage the receive in Interrupt context + * @brief Manage the receive 8-bit in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2359,25 +2528,30 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); hspi->RxXferCount--; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } +#endif if(hspi->RxXferCount == 0) { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_RxISR_8BITCRC; return; } +#endif SPI_CloseRx_ISR(hspi); } } +#if (USE_SPI_CRC != 0U) /** - * @brief Manage the CRC 16bit receive in Interrupt context + * @brief Manage the CRC 16-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2385,18 +2559,19 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { __IO uint16_t tmpreg; - + tmpreg = hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - + SPI_CloseRx_ISR(hspi); } +#endif /** - * @brief Manage the 16Bit receive in Interrupt context + * @brief Manage the 16-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2406,26 +2581,28 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; - +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } - +#endif if(hspi->RxXferCount == 0) - { + { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_RxISR_16BITCRC; return; } +#endif SPI_CloseRx_ISR(hspi); } } /** - * @brief Handle the data 8Bit transmit in Interrupt mode + * @brief Handle the data 8-bit transmit in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2434,44 +2611,48 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; - + if(hspi->TxXferCount == 0) { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } +#endif SPI_CloseTx_ISR(hspi); } } /** - * @brief Handle the data 16Bit transmit in Interrupt mode + * @brief Handle the data 16-bit transmit in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ +{ /* Transmit data in 16 Bit mode */ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; - + if(hspi->TxXferCount == 0) { +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } +#endif SPI_CloseTx_ISR(hspi); } } /** - * @brief This function handles SPI Communication Timeout. + * @brief Handle SPI Communication Timeout. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param Flag : SPI flag to check @@ -2507,22 +2688,21 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { SPI_RESET_CRC(hspi); } - + hspi->State= HAL_SPI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hspi); - + return HAL_TIMEOUT; } } } - - return HAL_OK; + return HAL_OK; } /** - * @brief This function handles SPI Communication Timeout. + * @brief Handle SPI FIFO Communication Timeout. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param Fifo : Fifo to check @@ -2548,8 +2728,8 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); @@ -2575,12 +2755,11 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, } } } - return HAL_OK; } /** - * @brief This function handles the check of the RX transaction complete. + * @brief Handle the check of the RX transaction complete. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param Timeout : Timeout duration @@ -2593,22 +2772,28 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } + + /* Control the BSY flag */ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) - { + { hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; } - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; + /* Empty the FRLVL fifo */ + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } } - return HAL_OK; } - + /** - * @brief This function handles the check of the RXTX or TX transaction complete. + * @brief Handle the check of the RXTX or TX transaction complete. * @param hspi: SPI handle * @param Timeout : Timeout duration */ @@ -2620,12 +2805,13 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; } - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; } - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + /* Control the BSY flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; @@ -2634,7 +2820,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ } /** - * @brief This function handles the close of the RXTX transaction. + * @brief Handle the end of the RXTX transaction. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2644,6 +2830,13 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { @@ -2654,65 +2847,73 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) } else { +#endif if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) { if(hspi->State == HAL_SPI_STATE_BUSY_RX) { - hspi->State = HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; HAL_SPI_RxCpltCallback(hspi); } else { - hspi->State = HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; HAL_SPI_TxRxCpltCallback(hspi); - } + } } else { hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); } +#if (USE_SPI_CRC != 0U) } +#endif } /** - * @brief This function handles the close of the RX transaction. + * @brief Handle the end of the RX transaction. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) { - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - /* Check the end of the transaction */ - SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); - - hspi->State = HAL_SPI_STATE_READY; + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + /* Check the end of the transaction */ + if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + hspi->State = HAL_SPI_STATE_READY; +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { +#endif + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); + HAL_SPI_RxCpltCallback(hspi); } else { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - HAL_SPI_RxCpltCallback(hspi); - } - else - { - HAL_SPI_ErrorCallback(hspi); - } + HAL_SPI_ErrorCallback(hspi); } +#if (USE_SPI_CRC != 0U) + } +#endif } /** - * @brief This function handles the close of the TX transaction. + * @brief Handle the end of the TX transaction. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -2722,7 +2923,13 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /* Disable TXE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); @@ -2744,6 +2951,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) */ #endif /* HAL_SPI_MODULE_ENABLED */ + /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h index feb222959da..c47e8a5b8d0 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -118,13 +118,13 @@ typedef struct */ typedef enum { - HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */ - HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing*/ - HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing*/ + HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */ }HAL_SPI_StateTypeDef; /** @@ -160,9 +160,9 @@ typedef struct __SPI_HandleTypeDef HAL_LockTypeDef Lock; /* Locking object */ - HAL_SPI_StateTypeDef State; /* SPI communication state */ + __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ - uint32_t ErrorCode; /* SPI Error code */ + __IO uint32_t ErrorCode; /* SPI Error code */ }SPI_HandleTypeDef; @@ -179,14 +179,14 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Error_Code SPI Error Code * @{ */ -#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */ -#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */ -#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */ -#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */ -#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */ -#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ -#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknow Error error */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040U) /*!< Unknow Error error */ /** * @} */ @@ -195,7 +195,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Mode SPI Mode * @{ */ -#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_SLAVE ((uint32_t)0x00000000U) #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /** * @} @@ -204,7 +204,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Direction SPI Direction Mode * @{ */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE /** @@ -214,19 +214,19 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Data_Size SPI Data Size * @{ */ -#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) -#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) -#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) -#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) -#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) -#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) -#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) -#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) -#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) -#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) -#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) -#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) -#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) +#define SPI_DATASIZE_4BIT ((uint32_t)0x0300U) +#define SPI_DATASIZE_5BIT ((uint32_t)0x0400U) +#define SPI_DATASIZE_6BIT ((uint32_t)0x0500U) +#define SPI_DATASIZE_7BIT ((uint32_t)0x0600U) +#define SPI_DATASIZE_8BIT ((uint32_t)0x0700U) +#define SPI_DATASIZE_9BIT ((uint32_t)0x0800U) +#define SPI_DATASIZE_10BIT ((uint32_t)0x0900U) +#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00U) +#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00U) +#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00U) +#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00U) +#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00U) +#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00U) /** * @} */ @@ -234,7 +234,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Polarity SPI Clock Polarity * @{ */ -#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_LOW ((uint32_t)0x00000000U) #define SPI_POLARITY_HIGH SPI_CR1_CPOL /** * @} @@ -243,7 +243,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Phase SPI Clock Phase * @{ */ -#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) #define SPI_PHASE_2EDGE SPI_CR1_CPHA /** * @} @@ -253,8 +253,8 @@ typedef struct __SPI_HandleTypeDef * @{ */ #define SPI_NSS_SOFT SPI_CR1_SSM -#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) -#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U) /** * @} */ @@ -263,7 +263,7 @@ typedef struct __SPI_HandleTypeDef * @{ */ #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP -#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000) +#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -271,14 +271,14 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ -#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) -#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008) -#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010) -#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018) -#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020) -#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) -#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) -#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U) /** * @} */ @@ -286,7 +286,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission * @{ */ -#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST /** * @} @@ -295,7 +295,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_TI_mode SPI TI mode * @{ */ -#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) #define SPI_TIMODE_ENABLE SPI_CR2_FRF /** * @} @@ -304,7 +304,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_CRC_Calculation SPI CRC Calculation * @{ */ -#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN /** * @} @@ -317,9 +317,9 @@ typedef struct __SPI_HandleTypeDef * SPI_CRC_LENGTH_8BIT : CRC 8bit * SPI_CRC_LENGTH_16BIT : CRC 16bit */ -#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000) -#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001) -#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002) +#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000U) +#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001U) +#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002U) /** * @} */ @@ -334,7 +334,7 @@ typedef struct __SPI_HandleTypeDef * level is greater or equal to 1/4(8 bits). */ #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH -#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000) +#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000U) /** * @} @@ -377,10 +377,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level * @{ */ -#define SPI_FTLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800) -#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000) -#define SPI_FTLVL_FULL ((uint32_t)0x1800) +#define SPI_FTLVL_EMPTY ((uint32_t)0x0000U) +#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800U) +#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000U) +#define SPI_FTLVL_FULL ((uint32_t)0x1800U) /** * @} @@ -389,10 +389,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level * @{ */ -#define SPI_FRLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200) -#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400) -#define SPI_FRLVL_FULL ((uint32_t)0x0600) +#define SPI_FRLVL_EMPTY ((uint32_t)0x0000U) +#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200U) +#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400U) +#define SPI_FRLVL_FULL ((uint32_t)0x0600U) /** * @} */ @@ -470,7 +470,7 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ tmpreg = (__HANDLE__)->Instance->SR; \ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ UNUSED(tmpreg); \ @@ -484,7 +484,7 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ tmpreg = (__HANDLE__)->Instance->DR; \ tmpreg = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg); \ @@ -498,7 +498,7 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg = 0x00; \ + __IO uint32_t tmpreg; \ tmpreg = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg); \ } while(0) @@ -609,7 +609,7 @@ typedef struct __SPI_HandleTypeDef ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_16BIT)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0)) /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c index e7fb8ff6e52..1e516d8f637 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -64,7 +64,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h index ee3b310c9af..0e65ce0a0cd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ */ typedef enum { - HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ - HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ }HAL_SRAM_StateTypeDef; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c index 9c28ebe92f7..4776fb4e345 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -98,7 +98,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h index f537e8e18cb..6439926ecdf 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -77,7 +77,7 @@ typedef struct uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR down-counter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: @@ -264,11 +264,11 @@ typedef struct { */ typedef enum { - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; /** @@ -276,11 +276,11 @@ typedef enum */ typedef enum { - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; /** @@ -308,7 +308,7 @@ typedef struct /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity * @{ */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** @@ -319,7 +319,7 @@ typedef struct * @{ */ #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */ /** * @} */ @@ -327,7 +327,7 @@ typedef struct /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ @@ -338,7 +338,7 @@ typedef struct /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 @@ -350,7 +350,7 @@ typedef struct /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) /** @@ -360,7 +360,7 @@ typedef struct /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) /** @@ -370,7 +370,7 @@ typedef struct /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U) #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) /** * @} @@ -379,7 +379,7 @@ typedef struct /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U) #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) /** * @} @@ -388,7 +388,7 @@ typedef struct /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) /** * @} @@ -397,7 +397,7 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U) #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) /** * @} @@ -407,7 +407,7 @@ typedef struct * @{ */ #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U) /** * @} */ @@ -416,7 +416,7 @@ typedef struct * @{ */ #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U) /** * @} */ @@ -447,7 +447,7 @@ typedef struct /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ @@ -459,7 +459,7 @@ typedef struct * @{ */ #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) +#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U) /** * @} */ @@ -494,7 +494,7 @@ typedef struct * @{ */ #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) +#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U) /** * @} */ @@ -554,7 +554,7 @@ typedef struct */ #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U) #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) @@ -613,7 +613,7 @@ typedef struct * @{ */ #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) +#define TIM_OSSR_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -622,7 +622,7 @@ typedef struct * @{ */ #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) +#define TIM_OSSI_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -630,7 +630,7 @@ typedef struct /** @defgroup TIM_Lock_level TIM Lock level * @{ */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) +#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U) #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) @@ -641,7 +641,7 @@ typedef struct * @{ */ #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) +#define TIM_BREAK_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -649,7 +649,7 @@ typedef struct /** @defgroup TIM_Break_Polarity TIM Break Polarity * @{ */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) +#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U) #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) /** * @} @@ -659,7 +659,7 @@ typedef struct * @{ */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -667,7 +667,7 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_RESET ((uint32_t)0x0000U) #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) @@ -683,7 +683,7 @@ typedef struct * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -691,15 +691,15 @@ typedef struct /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) +#define TIM_TS_ITR0 ((uint32_t)0x0000U) +#define TIM_TS_ITR1 ((uint32_t)0x0010U) +#define TIM_TS_ITR2 ((uint32_t)0x0020U) +#define TIM_TS_ITR3 ((uint32_t)0x0030U) +#define TIM_TS_TI1F_ED ((uint32_t)0x0040U) +#define TIM_TS_TI1FP1 ((uint32_t)0x0050U) +#define TIM_TS_TI2FP2 ((uint32_t)0x0060U) +#define TIM_TS_ETRF ((uint32_t)0x0070U) +#define TIM_TS_NONE ((uint32_t)0xFFFFU) /** * @} */ @@ -731,7 +731,7 @@ typedef struct /** @defgroup TIM_TI1_Selection TIM TI1 Selection * @{ */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) /** * @} @@ -740,26 +740,26 @@ typedef struct /** @defgroup TIM_DMA_Base_address TIM DMA Base address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_OR (0x00000013) +#define TIM_DMABASE_CR1 (0x00000000U) +#define TIM_DMABASE_CR2 (0x00000001U) +#define TIM_DMABASE_SMCR (0x00000002U) +#define TIM_DMABASE_DIER (0x00000003U) +#define TIM_DMABASE_SR (0x00000004U) +#define TIM_DMABASE_EGR (0x00000005U) +#define TIM_DMABASE_CCMR1 (0x00000006U) +#define TIM_DMABASE_CCMR2 (0x00000007U) +#define TIM_DMABASE_CCER (0x00000008U) +#define TIM_DMABASE_CNT (0x00000009U) +#define TIM_DMABASE_PSC (0x0000000AU) +#define TIM_DMABASE_ARR (0x0000000BU) +#define TIM_DMABASE_RCR (0x0000000CU) +#define TIM_DMABASE_CCR1 (0x0000000DU) +#define TIM_DMABASE_CCR2 (0x0000000EU) +#define TIM_DMABASE_CCR3 (0x0000000FU) +#define TIM_DMABASE_CCR4 (0x00000010U) +#define TIM_DMABASE_BDTR (0x00000011U) +#define TIM_DMABASE_DCR (0x00000012U) +#define TIM_DMABASE_OR (0x00000013U) /** * @} */ @@ -767,24 +767,24 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) /** * @} */ @@ -792,13 +792,13 @@ typedef struct /** @defgroup DMA_Handle_index DMA Handle index * @{ */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ @@ -806,10 +806,10 @@ typedef struct /** @defgroup Channel_CC_State Channel CC State * @{ */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) +#define TIM_CCx_ENABLE ((uint32_t)0x0001U) +#define TIM_CCx_DISABLE ((uint32_t)0x0000U) +#define TIM_CCxN_ENABLE ((uint32_t)0x0004U) +#define TIM_CCxN_DISABLE ((uint32_t)0x0000U) /** * @} */ @@ -1326,7 +1326,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12)) -#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000)) +#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U)) #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \ @@ -1338,9 +1338,9 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); ((__IT__) == TIM_IT_TRIGGER) || \ ((__IT__) == TIM_IT_BREAK)) -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \ ((__FLAG__) == TIM_FLAG_CC1) || \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c index e870df84885..bdd080b87b4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -72,7 +72,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -1640,7 +1640,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) @@ -1741,7 +1740,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, @@ -1906,6 +1904,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { case TIM_CLEARINPUTSOURCE_NONE: { + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + /* Clear the OCREF clear selection bit */ tmpsmcr &= ~TIM_SMCR_OCCS; @@ -2162,6 +2163,92 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, return HAL_OK; } +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** + * @brief Configures the break input source. + * @param htim: TIM handle. + * @param BreakInput: Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig: Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + uint32_t tmporx = 0; + uint32_t bkin_enable_mask = 0; + uint32_t bkin_enable_bitpos = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + + /* Check input state */ + __HAL_LOCK(htim); + + switch(sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = 0; + } + break; + + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BKE; + bkin_enable_bitpos = 8; + } + break; + + default: + break; + } + + switch(BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + } + break; + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + } + break; + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h index 290ccfc32f9..23da38fea59 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -97,7 +97,7 @@ typedef struct { */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode. + uint32_t OffStateRunMode; /*!< TIM off state in run mode. This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode. This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ @@ -121,6 +121,17 @@ typedef struct This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct { + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ +} TIMEx_BreakInputConfigTypeDef; +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -133,13 +144,13 @@ typedef struct * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_5 ((uint32_t)0x0010) -#define TIM_CHANNEL_6 ((uint32_t)0x0014) -#define TIM_CHANNEL_ALL ((uint32_t)0x003C) +#define TIM_CHANNEL_1 ((uint32_t)0x0000U) +#define TIM_CHANNEL_2 ((uint32_t)0x0004U) +#define TIM_CHANNEL_3 ((uint32_t)0x0008U) +#define TIM_CHANNEL_4 ((uint32_t)0x000CU) +#define TIM_CHANNEL_5 ((uint32_t)0x0010U) +#define TIM_CHANNEL_6 ((uint32_t)0x0014U) +#define TIM_CHANNEL_ALL ((uint32_t)0x003CU) /** * @} @@ -148,7 +159,7 @@ typedef struct /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_TIMING ((uint32_t)0x0000U) #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) @@ -170,18 +181,18 @@ typedef struct /** @defgroup TIMEx_Remap TIMEx Remap * @{ */ -#define TIM_TIM2_TIM8_TRGO (0x00000000) -#define TIM_TIM2_ETH_PTP (0x00000400) -#define TIM_TIM2_USBFS_SOF (0x00000800) -#define TIM_TIM2_USBHS_SOF (0x00000C00) -#define TIM_TIM5_GPIO (0x00000000) -#define TIM_TIM5_LSI (0x00000040) -#define TIM_TIM5_LSE (0x00000080) -#define TIM_TIM5_RTC (0x000000C0) -#define TIM_TIM11_GPIO (0x00000000) -#define TIM_TIM11_SPDIFRX (0x00000001) -#define TIM_TIM11_HSE (0x00000002) -#define TIM_TIM11_MCO1 (0x00000003) +#define TIM_TIM2_TIM8_TRGO (0x00000000U) +#define TIM_TIM2_ETH_PTP (0x00000400U) +#define TIM_TIM2_USBFS_SOF (0x00000800U) +#define TIM_TIM2_USBHS_SOF (0x00000C00U) +#define TIM_TIM5_GPIO (0x00000000U) +#define TIM_TIM5_LSI (0x00000040U) +#define TIM_TIM5_LSE (0x00000080U) +#define TIM_TIM5_RTC (0x000000C0U) +#define TIM_TIM11_GPIO (0x00000000U) +#define TIM_TIM11_SPDIFRX (0x00000001U) +#define TIM_TIM11_HSE (0x00000002U) +#define TIM_TIM11_MCO1 (0x00000003U) /** * @} */ @@ -189,9 +200,9 @@ typedef struct /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) +#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U) +#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) /** * @} */ @@ -199,7 +210,7 @@ typedef struct /** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable * @{ */ -#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) +#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) /** * @} @@ -208,7 +219,7 @@ typedef struct /** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity * @{ */ -#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) +#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U) #define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P) /** * @} @@ -217,7 +228,7 @@ typedef struct /** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_NONE ((uint32_t)0x00000000U) /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ @@ -228,7 +239,7 @@ typedef struct /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2) * @{ */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) +#define TIM_TRGO2_RESET ((uint32_t)0x00000000U) #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) @@ -251,16 +262,47 @@ typedef struct /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U) #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) +/** + * @} + */ +#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK ((uint32_t)0x00000001U) /* !< Timer break input */ +#define TIM_BREAKINPUT_BRK2 ((uint32_t)0x00000002U) /* !< Timer break2 input */ /** * @} */ +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)0x00000001U) /* !< Break input source is enabled */ +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -407,6 +449,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, u HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef); /** @@ -522,6 +567,17 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim); ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \ ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c index d9a64445157..c34a0780465 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c @@ -2,25 +2,25 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief UART HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - @verbatim + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The UART HAL driver can be used as follows: - + (#) Declare a UART_HandleTypeDef handle structure. - + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: (##) Enable the USARTx interface clock. (##) UART pins configuration: @@ -34,99 +34,99 @@ and HAL_UART_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx stream. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required - Tx/Rx parameters. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. (+++) Configure the DMA Tx/Rx Stream. (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream. - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the Init structure. (#) For the UART asynchronous mode, initialize the UART registers by calling the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling + + (#) For the UART Half duplex mode, initialize the UART registers by calling the HAL_HalfDuplex_Init() API. - + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. - - (#) For the Multi-Processor mode, initialize the UART registers by calling + + (#) For the Multi-Processor mode, initialize the UART registers by calling the HAL_MultiProcessor_Init() API. - - [..] - (@) The specific UART interrupts (Transmission complete interrupt, + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive process. - - [..] - (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the - low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized + + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_UART_MspInit() API. - - [..] - Three operation modes are available within this driver : - + + [..] + Three operation modes are available within this driver : + *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_UART_ErrorCallback - *** DMA mode IO operation *** + *** DMA mode IO operation *** ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_UART_ErrorCallback - (+) Pause the DMA Transfer using HAL_UART_DMAPause() - (+) Resume the DMA Transfer using HAL_UART_DMAResume() - (+) Stop the DMA Transfer using HAL_UART_DMAStop() - + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + *** UART HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in UART HAL driver. - - (+) __HAL_UART_ENABLE: Enable the UART peripheral - (+) __HAL_UART_DISABLE: Disable the UART peripheral + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not - - [..] - (@) You can refer to the UART HAL driver header file for more useful macros - + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -151,7 +151,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -164,52 +164,69 @@ * @brief HAL UART module driver * @{ */ + #ifdef HAL_UART_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions * @{ */ -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: + (+) For the asynchronous mode only these parameters can be configured: (++) Baud Rate - (++) Word Length + (++) Word Length (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), - please refer to Reference manual for possible UART frame formats. + please refer to Reference manual for possible UART frame formats. (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Method [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration procedures (details for the procedures are available in reference manual (RM0329)). @@ -230,7 +247,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { /* Check the parameters */ @@ -241,8 +258,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } - - if(huart->State == HAL_UART_STATE_RESET) + + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; @@ -251,11 +268,11 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { @@ -270,13 +287,13 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -293,16 +310,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - - if(huart->State == HAL_UART_STATE_RESET) + + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); @@ -321,28 +339,28 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - huart->Instance->CR3 |= USART_CR3_HDSEL; + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* TEACK and/or REACK to check before moving huart->State to Ready */ + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } /** - * @brief Initializes the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart: UART handle. * @param BreakDetectLength: specifies the LIN break detection length. * This parameter can be one of the following values: - * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection - * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) @@ -357,66 +375,66 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe assert_param(IS_UART_INSTANCE(huart->Instance)); assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength)); - - if(huart->State == HAL_UART_STATE_RESET) - { + + if(huart->gState == HAL_UART_STATE_RESET) + { /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - - huart->State = HAL_UART_STATE_BUSY; - + + huart->gState = HAL_UART_STATE_BUSY; + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; - } - + } + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - - /* In LIN mode, the following bits must be kept cleared: + + /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); - + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - huart->Instance->CR2 |= USART_CR2_LINEN; - + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - /* Enable the Peripheral */ + + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->State to Ready */ + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } - /** - * @brief Initializes the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle - * @param Address: UART node address (4-, 6-, 7- or 8-bit long) + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart: UART handle. + * @param Address: UART node address (4-, 6-, 7- or 8-bit long). * @param WakeUpMethod: specifies the UART wakeup method. * This parameter can be one of the following values: - * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection - * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to - * manage 6-, 7- or 8-bit long addresses detection + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) @@ -429,58 +447,140 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if(huart->State == HAL_UART_STATE_RESET) - { + + if(huart->gState == HAL_UART_STATE_RESET) + { /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - - huart->State = HAL_UART_STATE_BUSY; - + + huart->gState = HAL_UART_STATE_BUSY; + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; - } - + } + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - - /* In multiprocessor mode, the following bits must be kept cleared: + + /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); - + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { /* If address mark wake up method is chosen, set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); } - + /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - + /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->State to Ready */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart: UART handle. + * @param Polarity: select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime: Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime: Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +{ + uint32_t temp = 0x0; + + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + if(huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} /** - * @brief DeInitializes the UART peripheral + * @brief DeInitializes the UART peripheral * @param huart: uart handle * @retval HAL status */ @@ -491,28 +591,29 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); - huart->State = HAL_UART_STATE_BUSY; - + huart->gState = HAL_UART_STATE_BUSY; + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0; - huart->Instance->CR2 = 0x0; - huart->Instance->CR3 = 0x0; - + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State = HAL_UART_STATE_RESET; - + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + /* Process Unlock */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -521,14 +622,14 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @param huart: uart handle * @retval None */ - __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspInit can be implemented in the user file - */ + */ } /** @@ -536,24 +637,24 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @param huart: uart handle * @retval None */ - __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspDeInit can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -561,22 +662,22 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) and Half duplex data transfers. (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) No-Blocking mode: The communication is performed using Interrupts + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks will be executed respectively at the end of the transmit or Receive process The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - + (+) HAL_UART_Receive() + (#) Non-Blocking mode API's with Interrupt are : (+) HAL_UART_Transmit_IT() (+) HAL_UART_Receive_IT() @@ -584,14 +685,14 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) (+) UART_Transmit_IT() (+) UART_Receive_IT() - (#) No-Blocking mode API's with DMA are : + (#) Non-Blocking mode API's with DMA are : (+) HAL_UART_Transmit_DMA() (+) HAL_UART_Receive_DMA() (+) HAL_UART_DMAPause() (+) HAL_UART_DMAResume() (+) HAL_UART_DMAStop() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: (+) HAL_UART_TxHalfCpltCallback() (+) HAL_UART_TxCpltCallback() (+) HAL_UART_RxHalfCpltCallback() @@ -599,7 +700,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) (+) HAL_UART_ErrorCallback() - -@- In the Half duplex communication, it is forbidden to run the transmit + -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @endverbatim @@ -607,20 +708,22 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) */ /** - * @brief Send an amount of data in blocking mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout : Timeout duration + * @brief Send an amount of data in blocking mode. + * @param huart: UART handle. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be sent. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t* tmp; + uint32_t tickstart = 0U; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -629,50 +732,39 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); huart->TxXferSize = Size; huart->TxXferCount = Size; - while(huart->TxXferCount > 0) + while(huart->TxXferCount > 0U) { huart->TxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); pData += 2; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } } - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Check if a non-blocking receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { - huart->State = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -685,21 +777,23 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } /** - * @brief Receive an amount of data in blocking mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout : Timeout duration + * @brief Receive an amount of data in blocking mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; uint16_t uhMask; + uint32_t tickstart = 0U; - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -708,17 +802,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); - huart->RxXferSize = Size; + huart->RxXferSize = Size; huart->RxXferCount = Size; /* Computation of UART mask to apply to RDR register */ @@ -726,34 +815,28 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uhMask = huart->Mask; /* as long as data have to be received */ - while(huart->RxXferCount > 0) + while(huart->RxXferCount > 0U) { huart->RxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { - *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); } } - /* Check if a non-blocking transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -766,68 +849,59 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } /** - * @brief Send an amount of data in interrupt mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in interrupt mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) +{ + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - + huart->gState = HAL_UART_STATE_BUSY_TX; + /* Process Unlocked */ - __HAL_UNLOCK(huart); - + __HAL_UNLOCK(huart); + /* Enable the UART Transmit Data Register Empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); - + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in interrupt mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in interrupt mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -843,81 +917,69 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, UART_MASK_COMPUTATION(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART Data Register not empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE); return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in DMA mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in DMA mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) + + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; - huart->TxXferCount = Size; - + huart->TxXferCount = Size; + huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - + huart->gState = HAL_UART_STATE_BUSY_TX; + /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - + /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + /* Enable the UART transmit DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size); @@ -925,158 +987,151 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAT; - /* Process Unlocked */ __HAL_UNLOCK(huart); - + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in DMA mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) + * @brief Receive an amount of data in DMA mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - - if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) + + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - + huart->RxState = HAL_UART_STATE_BUSY_RX; + /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - + /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAR; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Pauses the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Pause the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - - if(huart->State == HAL_UART_STATE_BUSY_TX) + + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - return HAL_OK; + return HAL_OK; } /** - * @brief Resumes the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Resume the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { - /* Clear the Overrun flag before resuming the Rx transfer*/ + /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - /* Enable the UART DMA Rx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; - } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - - /* Enable the UART DMA Rx request before the DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } /* If the UART peripheral is still not enabled, enable it */ - if ((huart->Instance->CR1 & USART_CR1_UE) == 0) + if ((huart->Instance->CR1 & USART_CR1_UE) == 0U) { /* Enable UART peripheral */ __HAL_UART_ENABLE(huart); @@ -1086,36 +1141,49 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) } /** - * @brief Stops the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Stop the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { /* The Lock is not implemented on this API to allow the user application to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of the stream and the corresponding call back is executed. */ - - /* Disable the UART Tx/Rx DMA requests */ - huart->Instance->CR3 &= ~USART_CR3_DMAT; - huart->Instance->CR3 &= ~USART_CR3_DMAR; - - /* Abort the UART DMA tx channel */ - if(huart->hdmatx != NULL) + + /* Stop UART DMA Tx request if ongoing */ + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { - HAL_DMA_Abort(huart->hdmatx); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if(huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + + UART_EndTxTransfer(huart); } - /* Abort the UART DMA rx channel */ - if(huart->hdmarx != NULL) + + /* Stop UART DMA Rx request if ongoing */ + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { - HAL_DMA_Abort(huart->hdmarx); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + + UART_EndRxTransfer(huart); } - - huart->State = HAL_UART_STATE_READY; - + return HAL_OK; } @@ -1126,164 +1194,193 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { - /* UART parity error interrupt occurred -------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) - { - __HAL_UART_CLEAR_PEFLAG(huart); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } } - - /* UART frame error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_FEFLAG(huart); - huart->ErrorCode |= HAL_UART_ERROR_FE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_NEFLAG(huart); + /* If some errors occur */ + if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) + { - huart->ErrorCode |= HAL_UART_ERROR_NE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { - __HAL_UART_CLEAR_OREFLAG(huart); + /* UART parity error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); - huart->ErrorCode |= HAL_UART_ERROR_ORE; - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - } + huart->ErrorCode |= HAL_UART_ERROR_PE; + } - /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - HAL_UART_ErrorCallback(huart); - } + /* UART frame error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); - /* UART in mode Receiver ---------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET)) - { - UART_Receive_IT(huart); - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } - + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if(huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_UART_ErrorCallback(huart); + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ /* UART in mode Transmitter ------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET)) + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { UART_Transmit_IT(huart); + return; } /* UART in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) + if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { UART_EndTransmit_IT(huart); + return; } - -} +} /** * @brief This function handles UART Communication Timeout. - * @param huart: UART handle - * @param Flag: specifies the UART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param huart UART handle + * @param Flag specifies the UART flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - } - else + while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) { - while(__HAL_UART_GET_FLAG(huart, Flag) != RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout)) { - if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + return HAL_TIMEOUT; } } } - return HAL_OK; + return HAL_OK; } - - /** - * @brief DMA UART transmit process complete callback + * @brief DMA UART transmit process complete callback * @param hdma: DMA handle * @retval None */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* DMA Normal mode*/ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { - huart->TxXferCount = 0; + huart->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else @@ -1293,7 +1390,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA UART transmit process half complete callback + * @brief DMA UART transmit process half complete callback * @param hdma : DMA handle * @retval None */ @@ -1305,38 +1402,35 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA UART receive process complete callback + * @brief DMA UART receive process complete callback * @param hdma: DMA handle * @retval None */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) - { - huart->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; } HAL_UART_RxCpltCallback(huart); } /** - * @brief DMA UART receive process half complete callback + * @brief DMA UART receive process half complete callback * @param hdma : DMA handle * @retval None */ @@ -1344,21 +1438,48 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - HAL_UART_RxHalfCpltCallback(huart); + HAL_UART_RxHalfCpltCallback(huart); } /** - * @brief DMA UART communication error callback + * @brief DMA UART communication error callback * @param hdma: DMA handle * @retval None */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) +static void UART_DMAError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - huart->TxXferCount = 0; - huart->State= HAL_UART_STATE_READY; - huart->ErrorCode |= HAL_UART_ERROR_DMA; + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + /* Stop UART DMA Tx request if ongoing */ + if ( (huart->gState == HAL_UART_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) + { + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) + { + UART_EndRxTransfer(huart); + } + SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA); + HAL_UART_ErrorCallback(huart); +} + +/** + * @brief DMA UART communication abort callback, when call by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma: DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + HAL_UART_ErrorCallback(huart); } @@ -1371,10 +1492,10 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback can be implemented in the user file - */ + */ } /** @@ -1386,10 +1507,10 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file - */ + */ } /** @@ -1401,7 +1522,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file */ @@ -1416,7 +1537,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file */ @@ -1431,14 +1552,14 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file - */ + */ } /** - * @brief Send an amount of data in interrupt mode + * @brief Send an amount of data in interrupt mode * Function called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT() * @param huart: UART handle @@ -1448,31 +1569,17 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) + if(huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - /* Check if a receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - - /* Wait on TC flag to be able to start a second transfer */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - HAL_UART_TxCpltCallback(huart); + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); return HAL_OK; } @@ -1481,22 +1588,22 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; - } + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + huart->pTxBuffPtr += 2U; + } else { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU); } huart->TxXferCount--; - + return HAL_OK; } } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -1509,17 +1616,10 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; HAL_UART_TxCpltCallback(huart); @@ -1527,7 +1627,7 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) } /** - * @brief Receive an amount of data in interrupt mode + * @brief Receive an amount of data in interrupt mode * Function called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart: UART handle @@ -1538,9 +1638,10 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) uint16_t* tmp; uint16_t uhMask = huart->Mask; - if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { - + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pRxBuffPtr ; @@ -1549,66 +1650,92 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) } else { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); } if(--huart->RxXferCount == 0) { - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; - huart->State = HAL_UART_STATE_READY; - } - HAL_UART_RxCpltCallback(huart); - + return HAL_OK; } - + return HAL_OK; } else { - return HAL_BUSY; + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + return HAL_BUSY; } } +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart: UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart: UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; +} + /** * @} */ -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. - (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral. + (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral. (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver - (+) HAL_LIN_SendBreak() API transmits the break characters + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. @endverbatim * @{ */ @@ -1620,17 +1747,17 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ +{ /* Process Locked */ __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - + + huart->gState = HAL_UART_STATE_BUSY; + /* Enable USART mute mode by setting the MME bit in the CR1 register */ - huart->Instance->CR1 |= USART_CR1_MME; - - huart->State = HAL_UART_STATE_READY; - + SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + return (UART_CheckIdleState(huart)); } @@ -1641,28 +1768,28 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ +{ /* Process Locked */ __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - + + huart->gState = HAL_UART_STATE_BUSY; + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - huart->Instance->CR1 &= ~(USART_CR1_MME); - - huart->State = HAL_UART_STATE_READY; - + CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + return (UART_CheckIdleState(huart)); } /** * @brief Enter UART mute mode (means UART actually enters mute mode). - * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. * @param huart: uart handle * @retval HAL status */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ +{ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); } @@ -1675,7 +1802,11 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - return huart->State; + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** @@ -1690,32 +1821,32 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) } /** - * @brief Configure the UART peripheral + * @brief Configure the UART peripheral * @param huart: uart handle * @retval None */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg = 0x00000000U; UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; - HAL_StatusTypeDef ret = HAL_OK; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + uint16_t brrtemp = 0x0000U; + uint16_t usartdiv = 0x0000U; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ @@ -1723,25 +1854,25 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according + /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - + /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling */ tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ; MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); - + /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); /* Check UART Over Sampling to set Baud Rate Register */ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { + { switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: @@ -1751,108 +1882,108 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_SYSCLK: usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); break; - case UART_CLOCKSOURCE_UNDEFINED: + case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } - - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); huart->Instance->BRR = brrtemp; } else { switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); break; - case UART_CLOCKSOURCE_PCLK2: + case UART_CLOCKSOURCE_PCLK2: huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); break; - case UART_CLOCKSOURCE_HSI: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_SYSCLK: + case UART_CLOCKSOURCE_HSI: + huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); - break; + break; case UART_CLOCKSOURCE_LSE: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); break; - case UART_CLOCKSOURCE_UNDEFINED: + case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } } - return ret; + return ret; } /** - * @brief Configure the UART peripheral advanced features - * @param huart: uart handle + * @brief Configure the UART peripheral advanced features + * @param huart: uart handle * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - /* Check whether the set of advanced features to configure is properly set */ + /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - + /* if required, configure TX pin active level inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); } - + /* if required, configure RX pin active level inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); } - + /* if required, configure data inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - + /* if required, configure RX/TX pins swap */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); } - + /* if required, configure RX overrun detection disabling */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } - + /* if required, configure DMA disabling on reception error */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } - - /* if required, configure auto Baud rate detection scheme */ + + /* if required, configure auto Baud rate detection scheme */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); @@ -1864,11 +1995,11 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); } } - - /* if required, configure MSB first on communication line */ + + /* if required, configure MSB first on communication line */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); } } @@ -1882,14 +2013,19 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { + uint32_t tickstart = 0U; + /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Check if the Transmitter is enabled */ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout Occurred */ return HAL_TIMEOUT; @@ -1899,19 +2035,20 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { /* Timeout Occurred */ return HAL_TIMEOUT; } } - + /* Initialize the UART State */ - huart->State= HAL_UART_STATE_READY; - + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1925,17 +2062,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; - + huart->gState = HAL_UART_STATE_BUSY; + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - - huart->State= HAL_UART_STATE_READY; + + huart->gState= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1948,14 +2085,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1972,23 +2109,61 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); - + /* Process Locked */ __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - + + huart->gState = HAL_UART_STATE_BUSY; + /* Send break characters */ - huart->Instance->RQR |= UART_SENDBREAK_REQUEST; - - huart->State = HAL_UART_STATE_READY; - + SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - - return HAL_OK; + + return HAL_OK; } +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart: UART handle. + * @param AddressLength: this parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h index 3fc66b3c501..766d50b0299 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -144,17 +144,62 @@ typedef struct /** * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_UART_STATE_ERROR = 0x04 /*!< Error */ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_UART_StateTypeDef; /** @@ -162,12 +207,12 @@ typedef enum */ typedef enum { - UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }UART_ClockSourceTypeDef; /** @@ -201,7 +246,12 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef State; /*!< UART communication state */ + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -218,19 +268,19 @@ typedef struct /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ /** * @} */ /** @defgroup UART_Stop_Bits UART Number of Stop Bits * @{ */ -#define UART_STOPBITS_1 ((uint32_t)0x0000) +#define UART_STOPBITS_1 ((uint32_t)0x00000000U) #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /** * @} @@ -239,7 +289,7 @@ typedef struct /** @defgroup UART_Parity UART Parity * @{ */ -#define UART_PARITY_NONE ((uint32_t)0x00000000) +#define UART_PARITY_NONE ((uint32_t)0x00000000U) #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** @@ -249,7 +299,7 @@ typedef struct /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) +#define UART_HWCONTROL_NONE ((uint32_t)0x00000000U) #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) @@ -270,7 +320,7 @@ typedef struct /** @defgroup UART_State UART State * @{ */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000) +#define UART_STATE_DISABLE ((uint32_t)0x00000000U) #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /** * @} @@ -279,7 +329,7 @@ typedef struct /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) +#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U) #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /** * @} @@ -288,7 +338,7 @@ typedef struct /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U) #define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /** * @} @@ -297,7 +347,7 @@ typedef struct /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000U) #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) @@ -308,7 +358,7 @@ typedef struct /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) +#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000U) #define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /** * @} @@ -317,7 +367,7 @@ typedef struct /** @defgroup UART_LIN UART Local Interconnection Network mode * @{ */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000) +#define UART_LIN_DISABLE ((uint32_t)0x00000000U) #define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /** * @} @@ -326,7 +376,7 @@ typedef struct /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) +#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U) #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /** * @} @@ -335,7 +385,7 @@ typedef struct /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) +#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000U) #define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /** * @} @@ -344,7 +394,7 @@ typedef struct /** @defgroup UART_DMA_Rx UART DMA Rx * @{ */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x0000) +#define UART_DMA_RX_DISABLE ((uint32_t)0x0000U) #define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /** * @} @@ -353,7 +403,7 @@ typedef struct /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) +#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000U) #define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /** * @} @@ -362,7 +412,7 @@ typedef struct /** @defgroup UART_WakeUp_Methods UART WakeUp Methods * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) +#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U) #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /** * @} @@ -383,15 +433,15 @@ typedef struct /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type * @{ */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U) +#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U) +#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U) +#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U) +#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U) +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U) +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040U) +#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U) /** * @} */ @@ -399,7 +449,7 @@ typedef struct /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /** * @} @@ -408,7 +458,7 @@ typedef struct /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /** * @} @@ -417,7 +467,7 @@ typedef struct /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion * @{ */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /** * @} @@ -426,7 +476,7 @@ typedef struct /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap * @{ */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /** * @} @@ -435,7 +485,7 @@ typedef struct /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /** * @} @@ -444,7 +494,7 @@ typedef struct /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /** * @} @@ -453,7 +503,7 @@ typedef struct /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U) #define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /** * @} @@ -462,7 +512,7 @@ typedef struct /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /** * @} @@ -471,7 +521,7 @@ typedef struct /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) +#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000U) #define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /** * @} @@ -480,7 +530,7 @@ typedef struct /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) +#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24U) /** * @} */ @@ -488,7 +538,7 @@ typedef struct /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) +#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000U) #define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /** * @} @@ -497,7 +547,7 @@ typedef struct /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) +#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21U) /** * @} */ @@ -505,7 +555,7 @@ typedef struct /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) +#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16U) /** * @} */ @@ -513,7 +563,7 @@ typedef struct /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask * @{ */ -#define UART_IT_MASK ((uint32_t)0x001F) +#define UART_IT_MASK ((uint32_t)0x001FU) /** * @} */ @@ -521,7 +571,7 @@ typedef struct /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value * @{ */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /** * @} */ @@ -531,25 +581,25 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define UART_FLAG_TEACK ((uint32_t)0x00200000) -#define UART_FLAG_SBKF ((uint32_t)0x00040000) -#define UART_FLAG_CMF ((uint32_t)0x00020000) -#define UART_FLAG_BUSY ((uint32_t)0x00010000) -#define UART_FLAG_ABRF ((uint32_t)0x00008000) -#define UART_FLAG_ABRE ((uint32_t)0x00004000) -#define UART_FLAG_EOBF ((uint32_t)0x00001000) -#define UART_FLAG_RTOF ((uint32_t)0x00000800) -#define UART_FLAG_CTS ((uint32_t)0x00000400) -#define UART_FLAG_CTSIF ((uint32_t)0x00000200) -#define UART_FLAG_LBDF ((uint32_t)0x00000100) -#define UART_FLAG_TXE ((uint32_t)0x00000080) -#define UART_FLAG_TC ((uint32_t)0x00000040) -#define UART_FLAG_RXNE ((uint32_t)0x00000020) -#define UART_FLAG_IDLE ((uint32_t)0x00000010) -#define UART_FLAG_ORE ((uint32_t)0x00000008) -#define UART_FLAG_NE ((uint32_t)0x00000004) -#define UART_FLAG_FE ((uint32_t)0x00000002) -#define UART_FLAG_PE ((uint32_t)0x00000001) +#define UART_FLAG_TEACK ((uint32_t)0x00200000U) +#define UART_FLAG_SBKF ((uint32_t)0x00040000U) +#define UART_FLAG_CMF ((uint32_t)0x00020000U) +#define UART_FLAG_BUSY ((uint32_t)0x00010000U) +#define UART_FLAG_ABRF ((uint32_t)0x00008000U) +#define UART_FLAG_ABRE ((uint32_t)0x00004000U) +#define UART_FLAG_EOBF ((uint32_t)0x00001000U) +#define UART_FLAG_RTOF ((uint32_t)0x00000800U) +#define UART_FLAG_CTS ((uint32_t)0x00000400U) +#define UART_FLAG_CTSIF ((uint32_t)0x00000200U) +#define UART_FLAG_LBDF ((uint32_t)0x00000100U) +#define UART_FLAG_TXE ((uint32_t)0x00000080U) +#define UART_FLAG_TC ((uint32_t)0x00000040U) +#define UART_FLAG_RXNE ((uint32_t)0x00000020U) +#define UART_FLAG_IDLE ((uint32_t)0x00000010U) +#define UART_FLAG_ORE ((uint32_t)0x00000008U) +#define UART_FLAG_NE ((uint32_t)0x00000004U) +#define UART_FLAG_FE ((uint32_t)0x00000002U) +#define UART_FLAG_PE ((uint32_t)0x00000001U) /** * @} */ @@ -564,14 +614,14 @@ typedef struct * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE ((uint32_t)0x0028) -#define UART_IT_TXE ((uint32_t)0x0727) -#define UART_IT_TC ((uint32_t)0x0626) -#define UART_IT_RXNE ((uint32_t)0x0525) -#define UART_IT_IDLE ((uint32_t)0x0424) -#define UART_IT_LBD ((uint32_t)0x0846) -#define UART_IT_CTS ((uint32_t)0x096A) -#define UART_IT_CM ((uint32_t)0x112E) +#define UART_IT_PE ((uint32_t)0x0028U) +#define UART_IT_TXE ((uint32_t)0x0727U) +#define UART_IT_TC ((uint32_t)0x0626U) +#define UART_IT_RXNE ((uint32_t)0x0525U) +#define UART_IT_IDLE ((uint32_t)0x0424U) +#define UART_IT_LBD ((uint32_t)0x0846U) +#define UART_IT_CTS ((uint32_t)0x096AU) +#define UART_IT_CM ((uint32_t)0x112EU) /** Elements values convention: 000000000XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) @@ -580,14 +630,14 @@ typedef struct * - 10: CR2 register * - 11: CR3 register */ -#define UART_IT_ERR ((uint32_t)0x0060) +#define UART_IT_ERR ((uint32_t)0x0060U) /** Elements values convention: 0000ZZZZ00000000b * - ZZZZ : Flag position in the ISR register(4bits) */ -#define UART_IT_ORE ((uint32_t)0x0300) -#define UART_IT_NE ((uint32_t)0x0200) -#define UART_IT_FE ((uint32_t)0x0100) +#define UART_IT_ORE ((uint32_t)0x0300U) +#define UART_IT_NE ((uint32_t)0x0200U) +#define UART_IT_FE ((uint32_t)0x0100U) /** * @} */ @@ -624,7 +674,10 @@ typedef struct * @param __HANDLE__: UART handle. * @retval None */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0) /** @brief Flush the UART Data registers * @param __HANDLE__: specifies the UART Handle. @@ -918,21 +971,21 @@ typedef struct * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_LPUART(_PCLK_, _BAUD_) (((_PCLK_)*256)/((_BAUD_))) +#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode * @param _PCLK_: UART clock * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_))) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode * @param _PCLK_: UART clock * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_))) /** @brief Check UART Baud rate * @param BAUDRATE: Baudrate specified by the user @@ -1069,6 +1122,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); @@ -1091,6 +1145,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); + void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); @@ -1108,6 +1163,7 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); @@ -1141,7 +1197,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h index 6d6d656edaa..efc542fdf11 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ * @{ */ #define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) -#define UART_WORDLENGTH_8B ((uint32_t)0x0000) +#define UART_WORDLENGTH_8B ((uint32_t)0x0000U) #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ ((__LENGTH__) == UART_WORDLENGTH_8B) || \ @@ -78,7 +78,7 @@ /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) +#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) #define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) @@ -318,14 +318,44 @@ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); + +/** + * @} + */ + /** * @} */ +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + /** * @} - */ + */ +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c index a56cebf320f..e7100696824 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter @@ -52,7 +52,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -98,8 +98,8 @@ /** @addtogroup USART_Private_Constants * @{ */ -#define DUMMY_DATA ((uint16_t) 0xFFFF) -#define TEACK_REACK_TIMEOUT ((uint32_t) 1000) +#define DUMMY_DATA ((uint16_t) 0xFFFFU) +#define TEACK_REACK_TIMEOUT ((uint32_t) 1000U) #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) #define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ @@ -119,13 +119,17 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void USART_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_EndTxTransfer(USART_HandleTypeDef *husart); +static void USART_EndRxTransfer(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); + /** * @} */ @@ -152,18 +156,6 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible USART frame formats are as listed in the - following table: - - (+++) +---------------------------------------------------------------+ - (+++) | M1M0 bits | PCE bit | USART frame | - (+++) |-----------------------|---------------------------------------| - (+++) | 10 | 0 | | SB | 7-bit data | STB | | - (+++) |-----------|-----------|---------------------------------------| - (+++) | 10 | 1 | | SB | 6-bit data | PB | STB | | - (+++) +---------------------------------------------------------------+ - (++) USART polarity (++) USART phase (++) USART LastBit @@ -174,6 +166,19 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); procedure (details for the procedure are available in reference manual). @endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART frame formats are as listed in the + following table: + + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 10 | 0 | | SB | 7-bit data | STB | | + |-----------|-----------|---------------------------------------| + | 10 | 1 | | SB | 6-bit data | PB | STB | | + +---------------------------------------------------------------+ + * @{ */ @@ -216,8 +221,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ - husart->Instance->CR2 &= ~USART_CR2_LINEN; - husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); /* Enable the Peripheral */ __HAL_USART_ENABLE(husart); @@ -244,9 +249,9 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_BUSY; - husart->Instance->CR1 = 0x0; - husart->Instance->CR2 = 0x0; - husart->Instance->CR3 = 0x0; + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; /* DeInit the low level hardware */ HAL_USART_MspDeInit(husart); @@ -362,10 +367,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -375,31 +381,34 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); husart->TxXferSize = Size; husart->TxXferCount = Size; /* Check the remaining data to be sent */ - while(husart->TxXferCount > 0) + while(husart->TxXferCount > 0U) { husart->TxXferCount--; - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); pTxData += 2; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); + husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU); } } - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -430,10 +439,11 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat { uint16_t* tmp; uint16_t uhMask; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -442,6 +452,9 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); husart->RxXferSize = Size; husart->RxXferCount = Size; @@ -451,7 +464,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat uhMask = husart->Mask; /* as long as data have to be received */ - while(husart->RxXferCount > 0) + while(husart->RxXferCount > 0U) { husart->RxXferCount--; @@ -459,14 +472,14 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * clock for the slave to send data. * Whatever the frame length (7, 8 or 9-bit long), the same dummy value * can be written for all the cases. */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FFU); /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -509,10 +522,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { uint16_t* tmp; uint16_t uhMask; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -521,6 +535,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); husart->RxXferSize = Size; husart->TxXferSize = Size; @@ -538,7 +555,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t husart->RxXferCount--; /* Wait until TC flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -554,7 +571,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t } /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -563,7 +580,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { tmp = (uint16_t*) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData +=2U; } else { @@ -595,7 +612,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -620,7 +637,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT __HAL_UNLOCK(husart); /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); return HAL_OK; } @@ -642,7 +659,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if((pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -659,13 +676,13 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx husart->State = HAL_USART_STATE_BUSY_RX; /* Enable the USART Parity Error Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_PE); + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART Data Register not empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -674,11 +691,11 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Send dummy byte in order to generate the clock for the Slave to send the next data */ if(husart->Init.WordLength == USART_WORDLENGTH_9B) { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FFU); } else { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU); } return HAL_OK; @@ -702,7 +719,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -723,13 +740,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->State = HAL_USART_STATE_BUSY_TX_RX; /* Enable the USART Data Register not empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); /* Enable the USART Parity Error Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_PE); + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -743,7 +760,6 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint { return HAL_BUSY; } - } /** @@ -759,7 +775,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -782,20 +798,23 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /* Set the DMA error callback */ husart->hdmatx->XferErrorCallback = USART_DMAError; + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE)); + /* Enable the USART transmit DMA channel */ tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -821,7 +840,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if((pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -845,6 +864,21 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Set the USART DMA Rx transfer error callback */ husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* Set the DMA abort callback */ + husart->hdmatx->XferAbortCallback = NULL; + + /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE)); /* Enable the USART receive DMA channel */ tmp = (uint32_t*)&pRxData; @@ -853,19 +887,25 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Enable the USART transmit DMA channel: the transmit stream is used in order to generate in the non-blocking mode the clock to the slave device, this mode isn't a simplex receive mode but a full-duplex receive mode */ - tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - /* Process Unlocked */ - __HAL_UNLOCK(husart); return HAL_OK; } @@ -890,7 +930,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -923,6 +963,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Set the USART DMA Rx transfer error callback */ husart->hdmarx->XferErrorCallback = USART_DMAError; + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE)); + /* Enable the USART receive DMA channel */ tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); @@ -933,17 +977,23 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -966,19 +1016,22 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX) { /* Disable the USART DMA Tx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } else if(husart->State == HAL_USART_STATE_BUSY_RX) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Disable the USART DMA Rx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { /* Disable the USART DMA Tx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Disable the USART DMA Rx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } /* Process Unlocked */ @@ -1000,15 +1053,19 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX) { /* Enable the USART DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } else if(husart->State == HAL_USART_STATE_BUSY_RX) { /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + + /* Reenable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART DMA Rx request */ - husart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); } else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { @@ -1016,10 +1073,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); /* Enable the USART DMA Rx request before the DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Enable the USART DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } /* Process Unlocked */ @@ -1042,23 +1099,38 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of the stream and the corresponding call back is executed. */ - /* Disable the USART Tx/Rx DMA requests */ - husart->Instance->CR3 &= ~USART_CR3_DMAT; - husart->Instance->CR3 &= ~USART_CR3_DMAR; - - /* Abort the USART DMA tx Stream */ - if(husart->hdmatx != NULL) + /* Stop USART DMA Tx request if ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) { - HAL_DMA_Abort(husart->hdmatx); + USART_EndTxTransfer(husart); + + /* Abort the USART DMA Tx channel */ + if(husart->hdmatx != NULL) + { + HAL_DMA_Abort(husart->hdmatx); + } + + /* Disable the USART Tx DMA request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - /* Abort the USART DMA rx Stream */ - if(husart->hdmarx != NULL) + + /* Stop USART DMA Rx request if ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) { - HAL_DMA_Abort(husart->hdmarx); + USART_EndRxTransfer(husart); + + /* Abort the USART DMA Rx channel */ + if(husart->hdmarx != NULL) + { + HAL_DMA_Abort(husart->hdmarx); + } + + /* Disable the USART Rx DMA request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } - - husart->State = HAL_USART_STATE_READY; - + return HAL_OK; } @@ -1069,64 +1141,125 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) */ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { - - /* USART parity error interrupt occurred ------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - husart->ErrorCode |= HAL_USART_ERROR_PE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; - } - - /* USART frame error interrupt occurred -------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - husart->ErrorCode |= HAL_USART_ERROR_FE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; - } - - /* USART noise error interrupt occurred -------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - husart->ErrorCode |= HAL_USART_ERROR_NE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; - } - - /* USART Over-Run interrupt occurred ----------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - husart->ErrorCode |= HAL_USART_ERROR_ORE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; - } - - /* Call USART Error Call back function if need be --------------------------*/ - if(husart->ErrorCode != HAL_USART_ERROR_NONE) + uint32_t isrflags = READ_REG(husart->Instance->ISR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its = READ_REG(husart->Instance->CR3); + uint32_t errorflags; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == RESET) { - HAL_USART_ErrorCallback(husart); + /* USART in mode Receiver --------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + USART_Receive_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + } } - - /* USART in mode Receiver --------------------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET)) + + /* If some errors occur */ + if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET)) { - if(husart->State == HAL_USART_STATE_BUSY_RX) + + /* USART parity error interrupt occurred ------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { - USART_Receive_IT(husart); + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); + husart->ErrorCode |= HAL_USART_ERROR_PE; } - else + + /* USART frame error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { - USART_TransmitReceive_IT(husart); + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); + husart->ErrorCode |= HAL_USART_ERROR_FE; } - } - + + /* USART noise error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART Over-Run interrupt occurred ----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + /* Call USART Error Call back function if need be --------------------------*/ + if(husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + USART_Receive_IT(husart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || + (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + USART_EndRxTransfer(husart); + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel */ + if(husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_USART_ErrorCallback(husart); + } + } + else + { + /* Call user error callback */ + HAL_USART_ErrorCallback(husart); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_USART_ErrorCallback(husart); + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + /* USART in mode Transmitter -----------------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET)) + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { if(husart->State == HAL_USART_STATE_BUSY_TX) { @@ -1136,14 +1269,15 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { USART_TransmitReceive_IT(husart); } + return; } - + /* USART in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET)) + if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { USART_EndTransmit_IT(husart); + return; } - } /** @@ -1300,9 +1434,9 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX) { - if(husart->TxXferCount == 0) + if(husart->TxXferCount == 0U) { - /* Disable the USART Transmit Complete Interrupt */ + /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); /* Enable the USART Transmit Complete Interrupt */ @@ -1315,8 +1449,8 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + husart->pTxBuffPtr += 2U; } else { @@ -1343,10 +1477,10 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) { /* Disable the USART Transmit Complete Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); husart->State = HAL_USART_STATE_READY; @@ -1374,24 +1508,24 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); + husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU); - if(--husart->RxXferCount == 0) + if(--husart->RxXferCount == 0U) { - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); husart->State = HAL_USART_STATE_READY; @@ -1422,7 +1556,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { - if(husart->TxXferCount != 0x00) + if(husart->TxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) { @@ -1430,7 +1564,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & uhMask); - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2U; } else { @@ -1439,14 +1573,14 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) husart->TxXferCount--; /* Check the latest data transmitted */ - if(husart->TxXferCount == 0) + if(husart->TxXferCount == 0U) { - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE); } } } - if(husart->RxXferCount != 0x00) + if(husart->RxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) { @@ -1454,7 +1588,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { @@ -1465,15 +1599,15 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) } /* Check the latest data received */ - if(husart->RxXferCount == 0) + if(husart->RxXferCount == 0U) { - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); husart->State = HAL_USART_STATE_READY; @@ -1492,64 +1626,41 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) /** * @brief This function handles USART Communication Timeout. - * @param husart: USART handle - * @param Flag: specifies the USART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param husart USART handle + * @param Flag specifies the USART flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_USART_GET_FLAG(husart, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } - } - } - } - else + while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) { - while(__HAL_USART_GET_FLAG(husart, Flag) != RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout)) { - if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } + /* Disable the USART Transmit Complete Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE); + + /* Disable the USART RXNE Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); + + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + husart->State= HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; } } } @@ -1567,18 +1678,18 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { - husart->TxXferCount = 0; + husart->TxXferCount = 0U; if(husart->State == HAL_USART_STATE_BUSY_TX) { /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the USART CR3 register */ - husart->Instance->CR3 &= ~(USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Enable the USART Transmit Complete Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + SET_BIT(husart->Instance->CR1, USART_CR1_TCIE); } } /* DMA Circular mode */ @@ -1614,16 +1725,20 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { - husart->RxXferCount = 0; + husart->RxXferCount = 0U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit in USART CR3 register */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* similarly, disable the DMA TX transfer that was started to provide the clock to the slave device */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); if(husart->State == HAL_USART_STATE_BUSY_RX) { @@ -1672,14 +1787,73 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - husart->RxXferCount = 0; - husart->TxXferCount = 0; + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + + /* Stop USART DMA Tx request if ongoing */ + if((husart->State == HAL_USART_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) + { + USART_EndTxTransfer(husart); + } + + /* Stop USART DMA Rx request if ongoing */ + if((husart->State == HAL_USART_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) + { + USART_EndRxTransfer(husart); + } + husart->ErrorCode |= HAL_USART_ERROR_DMA; husart->State= HAL_USART_STATE_READY; HAL_USART_ErrorCallback(husart); } +/** + * @brief DMA USART communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma: DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + + HAL_USART_ErrorCallback(husart); +} + +/** + * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion). + * @param husart: USART handle. + * @retval None + */ +static void USART_EndTxTransfer(USART_HandleTypeDef *husart) +{ + /* At end of Tx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +} + +/** + * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion). + * @param husart: USART handle. + * @retval None + */ +static void USART_EndRxTransfer(USART_HandleTypeDef *husart) +{ + /* At end of Rx process, restore husart->RxState to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Disable RXNE, PE and ERR interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +} + /** * @brief Configure the USART peripheral * @param husart: USART handle @@ -1687,11 +1861,11 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { - uint32_t tmpreg = 0x0; + uint32_t tmpreg = 0x0U; USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; HAL_StatusTypeDef ret = HAL_OK; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint16_t brrtemp = 0x0000U; + uint16_t usartdiv = 0x0000U; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -1735,19 +1909,19 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) switch (clocksource) { case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); break; case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); break; case USART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); break; case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); break; case USART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate); + usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate); break; case USART_CLOCKSOURCE_UNDEFINED: default: @@ -1755,8 +1929,8 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) break; } - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); husart->Instance->BRR = brrtemp; return ret; @@ -1769,14 +1943,19 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) { + uint32_t tickstart = 0U; + /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Check if the Transmitter is enabled */ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) { husart->State= HAL_USART_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1786,7 +1965,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK) { husart->State= HAL_USART_STATE_TIMEOUT; return HAL_TIMEOUT; diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h index 578ff91d78a..09e5567eb47 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_usart.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,14 +103,14 @@ typedef struct */ typedef enum { - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ }HAL_USART_StateTypeDef; @@ -119,12 +119,12 @@ typedef enum */ typedef enum { - USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }USART_ClockSourceTypeDef; @@ -175,12 +175,12 @@ typedef struct * @brief USART Error Code * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ /** * @} */ @@ -188,7 +188,7 @@ typedef struct /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ -#define USART_STOPBITS_1 ((uint32_t)0x0000) +#define USART_STOPBITS_1 ((uint32_t)0x0000U) #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) #define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /** @@ -198,7 +198,7 @@ typedef struct /** @defgroup USART_Parity USART Parity * @{ */ -#define USART_PARITY_NONE ((uint32_t)0x0000) +#define USART_PARITY_NONE ((uint32_t)0x0000U) #define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** @@ -218,7 +218,7 @@ typedef struct /** @defgroup USART_Over_Sampling USART Over Sampling * @{ */ -#define USART_OVERSAMPLING_16 ((uint32_t)0x0000) +#define USART_OVERSAMPLING_16 ((uint32_t)0x0000U) #define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /** * @} @@ -226,7 +226,7 @@ typedef struct /** @defgroup USART_Clock USART Clock * @{ */ -#define USART_CLOCK_DISABLE ((uint32_t)0x0000) +#define USART_CLOCK_DISABLE ((uint32_t)0x0000U) #define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /** * @} @@ -235,7 +235,7 @@ typedef struct /** @defgroup USART_Clock_Polarity USART Clock Polarity * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x0000) +#define USART_POLARITY_LOW ((uint32_t)0x0000U) #define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /** * @} @@ -244,7 +244,7 @@ typedef struct /** @defgroup USART_Clock_Phase USART Clock Phase * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x0000) +#define USART_PHASE_1EDGE ((uint32_t)0x0000U) #define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /** * @} @@ -253,7 +253,7 @@ typedef struct /** @defgroup USART_Last_Bit USART Last Bit * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x0000) +#define USART_LASTBIT_DISABLE ((uint32_t)0x0000U) #define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /** * @} @@ -273,20 +273,20 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define USART_FLAG_REACK ((uint32_t)0x00400000) -#define USART_FLAG_TEACK ((uint32_t)0x00200000) -#define USART_FLAG_BUSY ((uint32_t)0x00010000) -#define USART_FLAG_CTS ((uint32_t)0x00000400) -#define USART_FLAG_CTSIF ((uint32_t)0x00000200) -#define USART_FLAG_LBDF ((uint32_t)0x00000100) -#define USART_FLAG_TXE ((uint32_t)0x00000080) -#define USART_FLAG_TC ((uint32_t)0x00000040) -#define USART_FLAG_RXNE ((uint32_t)0x00000020) -#define USART_FLAG_IDLE ((uint32_t)0x00000010) -#define USART_FLAG_ORE ((uint32_t)0x00000008) -#define USART_FLAG_NE ((uint32_t)0x00000004) -#define USART_FLAG_FE ((uint32_t)0x00000002) -#define USART_FLAG_PE ((uint32_t)0x00000001) +#define USART_FLAG_REACK ((uint32_t)0x00400000U) +#define USART_FLAG_TEACK ((uint32_t)0x00200000U) +#define USART_FLAG_BUSY ((uint32_t)0x00010000U) +#define USART_FLAG_CTS ((uint32_t)0x00000400U) +#define USART_FLAG_CTSIF ((uint32_t)0x00000200U) +#define USART_FLAG_LBDF ((uint32_t)0x00000100U) +#define USART_FLAG_TXE ((uint32_t)0x00000080U) +#define USART_FLAG_TC ((uint32_t)0x00000040U) +#define USART_FLAG_RXNE ((uint32_t)0x00000020U) +#define USART_FLAG_IDLE ((uint32_t)0x00000010U) +#define USART_FLAG_ORE ((uint32_t)0x00000008U) +#define USART_FLAG_NE ((uint32_t)0x00000004U) +#define USART_FLAG_FE ((uint32_t)0x00000002U) +#define USART_FLAG_PE ((uint32_t)0x00000001U) /** * @} */ @@ -302,16 +302,16 @@ typedef struct * @{ */ -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_PE ((uint16_t)0x0028U) +#define USART_IT_TXE ((uint16_t)0x0727U) +#define USART_IT_TC ((uint16_t)0x0626U) +#define USART_IT_RXNE ((uint16_t)0x0525U) +#define USART_IT_IDLE ((uint16_t)0x0424U) +#define USART_IT_ERR ((uint16_t)0x0060U) -#define USART_IT_ORE ((uint16_t)0x0300) -#define USART_IT_NE ((uint16_t)0x0200) -#define USART_IT_FE ((uint16_t)0x0100) +#define USART_IT_ORE ((uint16_t)0x0300U) +#define USART_IT_NE ((uint16_t)0x0200U) +#define USART_IT_FE ((uint16_t)0x0100U) /** * @} */ @@ -548,7 +548,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); /** @brief USART interruptions flag mask * */ -#define USART_IT_MASK ((uint16_t)0x001F) +#define USART_IT_MASK ((uint16_t)0x001FU) /** * @} @@ -653,7 +653,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ ((__PARITY__) == USART_PARITY_EVEN) || \ ((__PARITY__) == USART_PARITY_ODD)) -#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00)) +#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U)) #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ ((__SAMPLING__) == USART_OVERSAMPLING_8)) #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__)== USART_CLOCK_DISABLE) || \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h index b53b85afabe..ac9a38c9aa1 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ * @{ */ #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U) #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) /** * @} diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c index e5e6ee19525..970d86ac6f6 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c @@ -2,75 +2,101 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and de-initialization functions + * + Initialization and Configuration function * + IO operation functions - * + Peripheral State functions @verbatim ============================================================================== ##### WWDG specific features ##### ============================================================================== - [..] + [..] Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (down-counter) + time period, unless the program refreshes the counter (T[6;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). - + value rolls over from 0x40 to 0x3F). + (+) An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This + before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. + (+) Once enabled the WWDG cannot be disabled except by a system reset. - (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - reset occurs. - (+) The WWDG counter input clock is derived from the APB clock divided + + (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has + occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)). + + (+) The WWDG downcounter input clock is derived from the APB clock divided by a programmable prescaler. - (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) - (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock - (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock - (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock - - (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms + (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler) + + (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock) + where T[5;0] are the lowest 6 bits of downcounter. + + (+) WWDG Counter refresh is allowed between the following limits : + (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock) + (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock) + + (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms + + (+) The Early Wakeup Interrupt (EWI) can be used if specific safety + operations or data logging must be performed before the actual reset is + generated. When the downcounter reaches the value 0x40, an EWI interrupt + is generated and the corresponding interrupt service routine (ISR) can + be used to trigger specific actions (such as communications or data + logging), before resetting the device. + In some applications, the EWI interrupt can be used to manage a software + system check and/or system recovery/graceful degradation, without + generating a WWDG reset. In this case, the corresponding interrupt + service routine (ISR) should reload the WWDG counter to avoid the WWDG + reset, then trigger the required actions. + Note:When the EWI interrupt cannot be served, e.g. due to a system lock + in a higher priority task, the WWDG reset will eventually be generated. + + (+) Debug mode : When the microcontroller enters debug mode (core halted), + the WWDG counter either continues to work normally or stops, depending + on DBG_WWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros ##### How to use this driver ##### ============================================================================== [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of function pointer HAL_WWDG_WakeupCallback - Once enabled, EWI interrupt cannot be disabled except by a system reset. - (+) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using + + (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup + Interrupt mode using using HAL_WWDG_Init() function. + This enables WWDG peripheral and the downcounter starts downcounting + from given counter value. + Init function can be called again to modify all watchdog parameters, + however if EWI mode has been set once, it can't be clear until next + reset. + + (+) The application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset using HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the refresh window value already programmed. - + the counter is lower than the window value already programmed. + + (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when + the counter reaches 0x40. User can add his own code in weak function + HAL_WWDG_EarlyWakeupCallback(). + *** WWDG HAL driver macros list *** ================================== [..] Below the list of most used macros in WWDG HAL driver. - - (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags - (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wake-up interrupt + + (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source. + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status. + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -95,7 +121,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -104,47 +130,45 @@ * @{ */ +#ifdef HAL_WWDG_MODULE_ENABLED /** @defgroup WWDG WWDG * @brief WWDG HAL module driver. * @{ */ -#ifdef HAL_WWDG_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ + /** @defgroup WWDG_Exported_Functions WWDG Exported Functions * @{ */ -/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim ============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize the WWDG according to the specified parameters - in the WWDG_InitTypeDef and create the associated handle - (+) DeInitialize the WWDG peripheral - (+) Initialize the WWDG MSP - (+) DeInitialize the WWDG MSP - + (+) Initialize and start the WWDG according to the specified parameters + in the WWDG_InitTypeDef of associated handle. + (+) Initialize the WWDG MSP. + @endverbatim * @{ */ /** - * @brief Initializes the WWDG according to the specified - * parameters in the WWDG_InitTypeDef and creates the associated handle. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Initialize the WWDG according to the specified. + * parameters in the WWDG_InitTypeDef of associated handle. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) @@ -158,103 +182,40 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) /* Check the parameters */ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); - assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); - assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); - - if(hwwdg->State == HAL_WWDG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hwwdg->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_WWDG_MspInit(hwwdg); - } - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; + assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); + assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); + assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); - /* Set WWDG Prescaler and Window */ - MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); - /* Set WWDG Counter */ - MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); + /* Init the low level hardware */ + HAL_WWDG_MspInit(hwwdg); - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the WWDG peripheral. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Check the WWDG handle allocation */ - if(hwwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + /* Set WWDG Counter */ + WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_WWDG_MspDeInit(hwwdg); - - /* Reset WWDG Control register */ - hwwdg->Instance->CR = (uint32_t)0x0000007F; - - /* Reset WWDG Configuration register */ - hwwdg->Instance->CFR = (uint32_t)0x0000007F; - - /* Reset WWDG Status register */ - hwwdg->Instance->SR = 0; - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hwwdg); + /* Set WWDG Prescaler and Window */ + WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); /* Return function status */ return HAL_OK; } + /** - * @brief Initializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Initialize the WWDG MSP. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @note When rewriting this function in user file, mechanism may be added + * to avoid multiple initialize when HAL_WWDG_Init function is called + * again to change parameters. * @retval None */ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hwwdg); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_MspInit could be implemented in the user file - */ -} -/** - * @brief DeInitializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hwwdg); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_MspDeInit could be implemented in the user file + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_MspInit could be implemented in the user file */ } @@ -262,185 +223,83 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) * @} */ -/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions +/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### IO operation functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Start the WWDG. (+) Refresh the WWDG. - (+) Handle WWDG interrupt request. + (+) Handle WWDG interrupt request and associated function callback. @endverbatim * @{ */ /** - * @brief Starts the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Refresh the WWDG. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) { - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the WWDG with interrupt enabled. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the Early Wakeup Interrupt */ - __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI); - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Refreshes the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @param Counter: value of counter to put in WWDG counter - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to WWDG CR the WWDG Counter value to refresh with */ - MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - + WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); + /* Return function status */ return HAL_OK; } /** - * @brief Handles WWDG interrupt request. - * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations - * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro. - * When the downcounter reaches the value 0x40, and EWI interrupt is - * generated and the corresponding Interrupt Service Routine (ISR) can - * be used to trigger specific actions (such as communications or data - * logging), before resetting the device. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Handle WWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled by calling HAL_WWDG_Init function with + * EWIMode set to WWDG_EWI_ENABLE. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) -{ +{ /* Check if Early Wakeup Interrupt is enable */ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) { /* Check if WWDG Early Wakeup Interrupt occurred */ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) { - /* Early Wakeup callback */ - HAL_WWDG_WakeupCallback(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - /* Clear the WWDG Early Wakeup flag */ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); + + /* Early Wakeup callback */ + HAL_WWDG_EarlyWakeupCallback(hwwdg); } } -} +} + /** - * @brief Early Wakeup WWDG callback. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief WWDG Early Wakeup callback. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ -__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) +__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hwwdg); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_WakeupCallback could be implemented in the user file - */ -} - -/** - * @} - */ -/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the WWDG state. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL state - */ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) -{ - return hwwdg->State; + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file + */ } /** diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h index 29eb602dbcc..92254cd6ca4 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_WWDG_H @@ -52,68 +52,57 @@ /** @addtogroup WWDG * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup WWDG_Exported_Types WWDG Exported Types * @{ */ - -/** - * @brief WWDG HAL State Structure definition - */ -typedef enum -{ - HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ - HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ - HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ - HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ - HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ -}HAL_WWDG_StateTypeDef; /** - * @brief WWDG Init structure definition - */ + * @brief WWDG Init structure definition + */ typedef struct { - uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. - This parameter can be a value of @ref WWDG_Prescaler */ - - uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. - This parameter must be a number lower than Max_Data = 0x80 */ - - uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. - This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + This parameter can be a value of @ref WWDG_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. + This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + This parameter can be a value of @ref WWDG_EWI_Mode */ }WWDG_InitTypeDef; -/** - * @brief WWDG handle Structure definition - */ +/** + * @brief WWDG handle Structure definition + */ typedef struct { WWDG_TypeDef *Instance; /*!< Register base address */ - + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ - - HAL_LockTypeDef Lock; /*!< WWDG locking object */ - - __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */ - + }WWDG_HandleTypeDef; /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup WWDG_Exported_Constants WWDG Exported Constants * @{ */ /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition * @{ - */ -#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ + */ +#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ /** * @} */ @@ -121,120 +110,124 @@ typedef struct /** @defgroup WWDG_Flag_definition WWDG Flag definition * @brief WWDG Flag definition * @{ - */ -#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ + */ +#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ /** * @} */ /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ - */ -#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ + */ +#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +/** + * @} + */ + +/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode + * @{ + */ +#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ +#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ /** * @} - */ + */ /** * @} - */ + */ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup WWDG_Exported_Macros WWDG Exported Macros +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Macros WWDG Private Macros * @{ */ +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8)) -/** @brief Reset WWDG handle state - * @param __HANDLE__: WWDG handle - * @retval None +#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) + +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) + +#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \ + ((__MODE__) == WWDG_EWI_DISABLE)) +/** + * @} + */ + + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Macros WWDG Exported Macros + * @{ */ -#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) /** - * @brief Enables the WWDG peripheral. - * @param __HANDLE__: WWDG handle + * @brief Enable the WWDG peripheral. + * @param __HANDLE__ WWDG handle * @retval None */ -#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** - * @brief Disables the WWDG peripheral. + * @brief Enable the WWDG early wakeup interrupt. * @param __HANDLE__: WWDG handle - * @note WARNING: This is a dummy macro for HAL code alignment. - * Once enable, WWDG Peripheral cannot be disabled except by a system reset. + * @param __INTERRUPT__ specifies the interrupt to enable. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early wakeup interrupt + * @note Once enabled this interrupt cannot be disabled except by a system reset. * @retval None */ -#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */ +#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) /** - * @brief Gets the selected WWDG's it status. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the it to check. + * @brief Check whether the selected WWDG interrupt has occurred or not. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the it to check. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT * @retval The new state of WWDG_FLAG (SET or RESET). */ -#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) +#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) -/** @brief Clear the WWDG's interrupt pending bits +/** @brief Clear the WWDG interrupt pending bits. * bits to clear the selected interrupt pending bits. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag */ -#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) /** - * @brief Enables the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt to enable. - * This parameter can be one of the following values: - * @arg WWDG_IT_EWI: Early wakeup interrupt - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) - -/** - * @brief Disables the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt to disable. - * This parameter can be one of the following values: - * @arg WWDG_IT_EWI: Early wakeup interrupt - * @note WARNING: This is a dummy macro for HAL code alignment. - * Once enabled this interrupt cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */ - -/** - * @brief Gets the selected WWDG's flag status. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to check. + * @brief Check whether the specified WWDG flag is set or not. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval The new state of WWDG_FLAG (SET or RESET). */ -#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** - * @brief Clears the WWDG's pending flags. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. + * @brief Clear the WWDG's pending flags. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval None */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) -/** @brief Checks if the specified WWDG interrupt source is enabled or disabled. - * @param __HANDLE__: WWDG Handle. - * @param __INTERRUPT__: specifies the WWDG interrupt source to check. - * This parameter can be one of the following values: +/** @brief Check whether the specified WWDG interrupt source is enabled or not. + * @param __HANDLE__ WWDG Handle. + * @param __INTERRUPT__ specifies the WWDG interrupt source to check. + * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early Wakeup Interrupt * @retval state of __INTERRUPT__ (TRUE or FALSE). */ @@ -245,6 +238,7 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ + /** @addtogroup WWDG_Exported_Functions * @{ */ @@ -253,11 +247,8 @@ typedef struct * @{ */ /* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /** * @} */ @@ -266,68 +257,25 @@ void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); * @{ */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); -void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); -/** - * @} - */ - -/** @addtogroup WWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); -/** - * @} - */ - +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg); /** * @} */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup WWDG_Private_Constants WWDG Private Constants - * @{ - */ - /** * @} */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup WWDG_Private_Macros WWDG Private Macros - * @{ - */ -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ - ((__PRESCALER__) == WWDG_PRESCALER_8)) -#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) -#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) /** * @} */ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup WWDG_Private_Functions WWDG Private Functions - * @{ - */ - /** * @} */ -/** - * @} - */ - -/** - * @} - */ #ifdef __cplusplus } #endif diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c index 212cd411b33..b37978b61cd 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -46,7 +46,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -206,9 +206,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) { - Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\ - Init->ContinuousClock); + Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); } if(Init->NSBank != FMC_NORSRAM_BANK1) { @@ -602,10 +600,10 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) __FMC_NAND_DISABLE(Device); /* Set the FMC_NAND_BANK3 registers to their reset values */ - Device->PCR = 0x00000018; - Device->SR = 0x00000040; - Device->PMEM = 0xFCFCFCFC; - Device->PATT = 0xFCFCFCFC; + Device->PCR = 0x00000018U; + Device->SR = 0x00000040U; + Device->PMEM = 0xFCFCFCFCU; + Device->PATT = 0xFCFCFCFCU; return HAL_OK; } @@ -779,13 +777,13 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe /* Set SDRAM bank configuration parameters */ if (Init->SDBank != FMC_SDRAM_BANK2) - { + { tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ Init->RowBitsNumber |\ @@ -803,36 +801,35 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe { tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + /* Clear SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ Init->ReadBurst |\ - Init->ReadPipeDelay); + Init->ReadPipeDelay); tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ Init->WriteProtection); Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; - } + } return HAL_OK; } + /** * @brief Initializes the FMC_SDRAM device timing according to the specified * parameters in the FMC_SDRAM_TimingTypeDef @@ -859,7 +856,7 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim /* Set SDRAM device timing parameters */ if (Bank != FMC_SDRAM_BANK2) - { + { tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ @@ -877,32 +874,31 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; } else /* FMC_Bank2_SDRAM */ - { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); + /* Clear TRC and TRP bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ - (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ - (((Timing->SelfRefreshTime)-1) << 8) |\ - (((Timing->WriteRecoveryTime)-1) <<16) |\ - (((Timing->RCDDelay)-1) << 24)); + tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->RPDelay)-1) << 20)); - tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; + tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ FMC_SDTR1_TRCD)); - tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ - (((Timing->RPDelay)-1) << 20)); + + tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RCDDelay)-1) << 24)); - Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; - Device->SDTR[FMC_SDRAM_BANK1] = tmpr2; - } + Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; + } return HAL_OK; } diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h index 85dcec696c1..717c4f7b510 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -679,10 +679,10 @@ typedef struct /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) +#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) +#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) +#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) /** * @} */ @@ -690,8 +690,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) -#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) +#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) /** * @} */ @@ -699,9 +699,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) -#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) -#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) +#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) +#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) /** * @} */ @@ -709,9 +709,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) /** * @} */ @@ -719,8 +719,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -728,8 +728,8 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) +#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) /** * @} */ @@ -737,8 +737,8 @@ typedef struct /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) +#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) /** * @} */ @@ -746,8 +746,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) -#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) +#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) /** * @} */ @@ -755,8 +755,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) +#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) /** * @} */ @@ -764,8 +764,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) +#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) /** * @} */ @@ -773,8 +773,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) +#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) /** * @} */ @@ -782,8 +782,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) /** * @} */ @@ -791,7 +791,7 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) +#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1)) @@ -803,8 +803,8 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) +#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) /** * @} */ @@ -812,8 +812,8 @@ typedef struct /** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) /** * @} */ @@ -822,7 +822,7 @@ typedef struct * @{ */ #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) +#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) /** * @} */ @@ -830,9 +830,9 @@ typedef struct /** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) -#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) -#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) +#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) +#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) +#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) /** * @} @@ -848,7 +848,7 @@ typedef struct /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100) +#define FMC_NAND_BANK3 ((uint32_t)0x00000100U) /** * @} */ @@ -856,8 +856,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) +#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) /** * @} */ @@ -865,7 +865,7 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) +#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) /** * @} */ @@ -873,8 +873,8 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) /** * @} */ @@ -882,8 +882,8 @@ typedef struct /** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) +#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) +#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) /** * @} */ @@ -891,12 +891,12 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) /** * @} */ @@ -911,8 +911,8 @@ typedef struct /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank * @{ */ -#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001) +#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U) /** * @} */ @@ -920,10 +920,10 @@ typedef struct /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number * @{ */ -#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000) -#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001) -#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002) -#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003) +#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U) /** * @} */ @@ -931,9 +931,9 @@ typedef struct /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number * @{ */ -#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000) -#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004) -#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008) +#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U) /** * @} */ @@ -941,9 +941,9 @@ typedef struct /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width * @{ */ -#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) +#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) /** * @} */ @@ -951,8 +951,8 @@ typedef struct /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number * @{ */ -#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000) -#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040) +#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U) /** * @} */ @@ -960,8 +960,8 @@ typedef struct /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency * @{ */ -#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080) -#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100) +#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U) #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) /** * @} @@ -970,8 +970,8 @@ typedef struct /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection * @{ */ -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200) +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U) /** * @} */ @@ -979,8 +979,8 @@ typedef struct /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period * @{ */ -#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800) +#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U) #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) /** * @} @@ -989,8 +989,8 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst * @{ */ -#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000) +#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U) /** * @} */ @@ -998,9 +998,9 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay * @{ */ -#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000) -#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000) -#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000) +#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U) /** * @} */ @@ -1008,13 +1008,13 @@ typedef struct /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode * @{ */ -#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000) -#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001) -#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002) -#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003) -#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004) -#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005) -#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006) +#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U) +#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U) /** * @} */ @@ -1024,7 +1024,7 @@ typedef struct */ #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 -#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018) +#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U) /** * @} */ @@ -1032,7 +1032,7 @@ typedef struct /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status * @{ */ -#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000) +#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U) #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 /** @@ -1046,10 +1046,10 @@ typedef struct /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ -#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) -#define FMC_IT_LEVEL ((uint32_t)0x00000010) -#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) -#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) +#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U) +#define FMC_IT_LEVEL ((uint32_t)0x00000010U) +#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) +#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U) /** * @} */ @@ -1057,10 +1057,10 @@ typedef struct /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ -#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) -#define FMC_FLAG_LEVEL ((uint32_t)0x00000002) -#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) +#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U) +#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) +#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U) #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c index b99067f01d3..37f92c5aebc 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -138,7 +138,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -212,7 +212,7 @@ */ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); @@ -239,7 +239,6 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) } - /** * @} */ @@ -483,7 +482,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM { /* Check the parameters */ assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode)); - + /* Set SDMMC read wait mode */ MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h index 374156a7fa1..0e4a4b8a07d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -149,7 +149,7 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Edge Clock Edge * @{ */ -#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000) +#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ @@ -161,7 +161,7 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass * @{ */ -#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) +#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ @@ -173,7 +173,7 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving * @{ */ -#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) +#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ @@ -185,7 +185,7 @@ typedef struct /** @defgroup SDMMC_LL_Bus_Wide Bus Width * @{ */ -#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000) +#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 @@ -199,7 +199,7 @@ typedef struct /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control * @{ */ -#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) +#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ @@ -227,7 +227,7 @@ typedef struct /** @defgroup SDMMC_LL_Response_Type Response Type * @{ */ -#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000) +#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP @@ -241,7 +241,7 @@ typedef struct /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt * @{ */ -#define SDMMC_WAIT_NO ((uint32_t)0x00000000) +#define SDMMC_WAIT_NO ((uint32_t)0x00000000U) #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND @@ -255,7 +255,7 @@ typedef struct /** @defgroup SDMMC_LL_CPSM_State CPSM State * @{ */ -#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000) +#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ @@ -267,9 +267,9 @@ typedef struct /** @defgroup SDMMC_LL_Response_Registers Response Register * @{ */ -#define SDMMC_RESP1 ((uint32_t)0x00000000) -#define SDMMC_RESP2 ((uint32_t)0x00000004) -#define SDMMC_RESP3 ((uint32_t)0x00000008) +#define SDMMC_RESP1 ((uint32_t)0x00000000U) +#define SDMMC_RESP2 ((uint32_t)0x00000004U) +#define SDMMC_RESP3 ((uint32_t)0x00000008U) #define SDMMC_RESP4 ((uint32_t)0x0000000C) #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ @@ -291,7 +291,7 @@ typedef struct /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size * @{ */ -#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) +#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) @@ -329,7 +329,7 @@ typedef struct /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction * @{ */ -#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) +#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ @@ -341,7 +341,7 @@ typedef struct /** @defgroup SDMMC_LL_Transfer_Type Transfer Type * @{ */ -#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) +#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ @@ -353,7 +353,7 @@ typedef struct /** @defgroup SDMMC_LL_DPSM_State DPSM State * @{ */ -#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000) +#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ @@ -365,7 +365,7 @@ typedef struct /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode * @{ */ -#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) +#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c index acabf79eff5..cdecd3539ef 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.c * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -28,7 +28,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h index 568d8fa6821..51947f3203d 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @version V1.0.4 - * @date 09-December-2015 + * @version V1.1.0 + * @date 22-April-2016 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2015 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -61,9 +61,9 @@ */ typedef enum { - USB_OTG_DEVICE_MODE = 0, - USB_OTG_HOST_MODE = 1, - USB_OTG_DRD_MODE = 2 + USB_OTG_DEVICE_MODE = 0U, + USB_OTG_HOST_MODE = 1U, + USB_OTG_DRD_MODE = 2U }USB_OTG_ModeTypeDef; @@ -71,7 +71,7 @@ typedef enum * @brief URB States definition */ typedef enum { - URB_IDLE = 0, + URB_IDLE = 0U, URB_DONE, URB_NOTREADY, URB_NYET, @@ -84,7 +84,7 @@ typedef enum { * @brief Host channel States definition */ typedef enum { - HC_IDLE = 0, + HC_IDLE = 0U, HC_XFRC, HC_HALTED, HC_NAK, @@ -233,9 +233,9 @@ typedef struct /** @defgroup USB_Core_Mode_ USB Core Mode * @{ */ -#define USB_OTG_MODE_DEVICE 0 -#define USB_OTG_MODE_HOST 1 -#define USB_OTG_MODE_DRD 2 +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U /** * @} */ @@ -243,10 +243,10 @@ typedef struct /** @defgroup USB_Core_Speed_ USB Core Speed * @{ */ -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_LOW 2 -#define USB_OTG_SPEED_FULL 3 +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_LOW 2U +#define USB_OTG_SPEED_FULL 3U /** * @} */ @@ -254,8 +254,8 @@ typedef struct /** @defgroup USB_Core_PHY_ USB Core PHY * @{ */ -#define USB_OTG_ULPI_PHY 1 -#define USB_OTG_EMBEDDED_PHY 2 +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U /** * @} */ @@ -263,9 +263,9 @@ typedef struct /** @defgroup USB_Core_MPS_ USB Core MPS * @{ */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512 -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ @@ -284,10 +284,10 @@ typedef struct /** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval * @{ */ -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U /** * @} */ @@ -295,10 +295,10 @@ typedef struct /** @defgroup USB_EP0_MPS_ USB EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U /** * @} */ @@ -306,9 +306,9 @@ typedef struct /** @defgroup USB_EP_Speed_ USB EP Speed * @{ */ -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U /** * @} */ @@ -316,11 +316,11 @@ typedef struct /** @defgroup USB_EP_Type_ USB EP Type * @{ */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U /** * @} */ @@ -328,11 +328,11 @@ typedef struct /** @defgroup USB_STS_Defines_ USB STS Defines * @{ */ -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U /** * @} */ @@ -340,9 +340,9 @@ typedef struct /** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines * @{ */ -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U /** * @} */ @@ -350,27 +350,27 @@ typedef struct /** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines * @{ */ -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U /** * @} */ -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) From 2ee2aa938095edf992a259041a9b4d63f8fe3567 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 12 Jun 2016 18:41:52 +0200 Subject: [PATCH 08/12] [NUCLEO_F767] move gcc template to new path --- {workspace_tools => tools}/export/gcc_arm_nucleo_f767zi.tmpl | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {workspace_tools => tools}/export/gcc_arm_nucleo_f767zi.tmpl (100%) diff --git a/workspace_tools/export/gcc_arm_nucleo_f767zi.tmpl b/tools/export/gcc_arm_nucleo_f767zi.tmpl similarity index 100% rename from workspace_tools/export/gcc_arm_nucleo_f767zi.tmpl rename to tools/export/gcc_arm_nucleo_f767zi.tmpl From 12ff6000767800cfb5833ca82efdeb5d0756f5e8 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 12 Jun 2016 18:56:16 +0200 Subject: [PATCH 09/12] =?UTF-8?q?Add=20call=20to=20SystemCoreClockUpdate()?= =?UTF-8?q?=20and=20Reset=20peripheral=20before=20init=20=E2=80=A6=20?= =?UTF-8?q?=E2=80=A6phase.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit patch from bcostm --- .../TARGET_STM/TARGET_STM32F7/serial_api.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/serial_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/serial_api.c index b0468ac5d10..00ef41b4f7f 100644 --- a/hal/targets/hal/TARGET_STM/TARGET_STM32F7/serial_api.c +++ b/hal/targets/hal/TARGET_STM/TARGET_STM32F7/serial_api.c @@ -67,6 +67,9 @@ static void init_uart(serial_t *obj) UartHandle.Init.Mode = UART_MODE_TX_RX; } + // Fix because HAL_RCC_GetHCLKFreq() don't update anymore SystemCoreClock + SystemCoreClockUpdate(); + if (HAL_UART_Init(&UartHandle) != HAL_OK) { error("Cannot initialize UART"); } @@ -85,43 +88,59 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) // Enable USART clock switch (obj->uart) { case UART_1: + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); __USART1_CLK_ENABLE(); obj->index = 0; break; case UART_2: + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); __USART2_CLK_ENABLE(); obj->index = 1; break; #if defined(USART3_BASE) case UART_3: + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); __USART3_CLK_ENABLE(); obj->index = 2; break; #endif #if defined(UART4_BASE) case UART_4: + __HAL_RCC_UART4_FORCE_RESET(); + __HAL_RCC_UART4_RELEASE_RESET(); __UART4_CLK_ENABLE(); obj->index = 3; break; #endif #if defined(UART5_BASE) case UART_5: + __HAL_RCC_UART5_FORCE_RESET(); + __HAL_RCC_UART5_RELEASE_RESET(); __UART5_CLK_ENABLE(); obj->index = 4; break; #endif case UART_6: + __HAL_RCC_USART6_FORCE_RESET(); + __HAL_RCC_USART6_RELEASE_RESET(); __USART6_CLK_ENABLE(); obj->index = 5; break; #if defined(UART7_BASE) case UART_7: + __HAL_RCC_UART7_FORCE_RESET(); + __HAL_RCC_UART7_RELEASE_RESET(); __UART7_CLK_ENABLE(); obj->index = 6; break; #endif #if defined(UART8_BASE) case UART_8: + __HAL_RCC_UART8_FORCE_RESET(); + __HAL_RCC_UART8_RELEASE_RESET(); __UART8_CLK_ENABLE(); obj->index = 7; break; From 84e8b34312c6232e576bec9e0c45dc7e91cc81a0 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 12 Jun 2016 18:56:35 +0200 Subject: [PATCH 10/12] rebase failure --- hal/targets.json | 7 ------- 1 file changed, 7 deletions(-) diff --git a/hal/targets.json b/hal/targets.json index 9ec83cb3ff2..362b64fded1 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -805,13 +805,6 @@ "detect_code": ["0799"], "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"] }, - "NUCLEO_F767ZI": { - "inherits": ["Target"], - "core": "Cortex-M7F", - "extra_labels": ["STM", "STM32F7", "STM32F767", "STM32F767ZI"], - "supported_toolchains": ["GCC_ARM"], - "progen": { "target": "nucleo-f769zi"} - }, "NUCLEO_L031K6": { "inherits": ["Target"], "core": "Cortex-M0", From b885ff84615a5b88663aca3ebc453c993fd70df6 Mon Sep 17 00:00:00 2001 From: ohagendorf Date: Sun, 12 Jun 2016 21:36:08 +0200 Subject: [PATCH 11/12] [STM32F676] correcting memory sizes for gcc_arm --- .../TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld index ed431e6a49c..359b884aee5 100644 --- a/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld +++ b/hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/TOOLCHAIN_GCC_ARM/STM32F767ZI.ld @@ -1,8 +1,8 @@ /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - RAM (rwx) : ORIGIN = 0x200001F8, LENGTH = 320K - 0x1F8 + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + RAM (rwx) : ORIGIN = 0x200001F8, LENGTH = 512K - 0x1F8 } /* Linker script to place sections and symbol values. Should be used together From e8239e029fe47ab86370b620947d6be117dd62a6 Mon Sep 17 00:00:00 2001 From: Olaf Hagendorf Date: Wed, 15 Jun 2016 16:28:22 +0200 Subject: [PATCH 12/12] [Cortex_M7] fpu with single/double precision - bugfix and extension - creating new core name Cortex_M7F_DP for a target with a double precision fpu - adding new core name to arm.py to set compiler/linker flags to a double precision fpu when configured in target.json - up to now: gcc wrote flag for a double precision fpu -> target with STM32F746 didn't run when using double variables - mcu has only single precision fpu - changing gcc.py to use single precision for Cortex-M7 und double precision for Cortex_M7F_DP tested with NUCLEO_F746, NUCLEO_F767 and build.py+make.py and exporting with project.py + compiling/flashing - iar.py need a similar extention - I didn't change that yet because - did not run at the moment - python exception - currently worked on in PR #1948 --- hal/targets.json | 2 +- tools/targets.py | 1 + tools/toolchains/__init__.py | 1 + tools/toolchains/arm.py | 2 ++ tools/toolchains/gcc.py | 7 +++++++ 5 files changed, 12 insertions(+), 1 deletion(-) diff --git a/hal/targets.json b/hal/targets.json index 362b64fded1..29bb648255e 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -792,7 +792,7 @@ }, "NUCLEO_F767ZI": { "inherits": ["Target"], - "core": "Cortex-M7F", + "core": "Cortex-M7F_DP", "extra_labels": ["STM", "STM32F7", "STM32F767", "STM32F767ZI"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], "default_toolchain": "ARM", diff --git a/tools/targets.py b/tools/targets.py index 953523f6c7d..a57ea6a475b 100644 --- a/tools/targets.py +++ b/tools/targets.py @@ -25,6 +25,7 @@ "Cortex-M4F" : ["M4", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M4"], "Cortex-M7" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7"], "Cortex-M7F" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7"], + "Cortex-M7F_DP" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7"], "Cortex-A9" : ["A9", "CORTEX_A", "LIKE_CORTEX_A9"] } diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index b801a1a011c..1ce7b25953d 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -219,6 +219,7 @@ class mbedToolchain: "Cortex-M4F" : ["__CORTEX_M4", "ARM_MATH_CM4", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M7" : ["__CORTEX_M7", "ARM_MATH_CM7", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M7F" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M7F_DP" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-A9" : ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT", "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"], } diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 1b94a0b5bd6..0c3a20bc0f2 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -51,6 +51,8 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, cpu = "Cortex-M4.fp" elif target.core == "Cortex-M7F": cpu = "Cortex-M7.fp.sp" + elif target.core == "Cortex-M7F_DP": + cpu = "Cortex-M7.fp.dp" else: cpu = target.core diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index 027a956d59a..25227a982d1 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -52,6 +52,8 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, cpu = "cortex-m4" elif target.core == "Cortex-M7F": cpu = "cortex-m7" + elif target.core == "Cortex-M7F_DP": + cpu = "cortex-m7" else: cpu = target.core.lower() @@ -62,7 +64,12 @@ def __init__(self, target, options=None, notify=None, macros=None, silent=False, if target.core == "Cortex-M4F": self.cpu.append("-mfpu=fpv4-sp-d16") self.cpu.append("-mfloat-abi=softfp") + elif target.core == "Cortex-M7F": + self.cpu.append("-mfpu=fpv5-sp-d16") + self.cpu.append("-mfloat-abi=softfp") + + elif target.core == "Cortex-M7F_DP": self.cpu.append("-mfpu=fpv5-d16") self.cpu.append("-mfloat-abi=softfp")