diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp
index f004d86cb1f..1274151d0d4 100644
--- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp
@@ -58,10 +58,13 @@ extern "C" {
 #include "nRF5xServiceDiscovery.h"
 #include "nRF5xCharacteristicDescriptorDiscoverer.h"
 
+
 bool isEventsSignaled = false;
 
 extern "C" void assert_nrf_callback(uint16_t line_num, const uint8_t *p_file_name);
 void            app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t *p_file_name);
+extern "C" void SD_EVT_IRQHandler(void); // export the softdevice event handler for registration by nvic-set-vector.
+
 
 static void btle_handler(ble_evt_t *p_ble_evt);
 
@@ -112,10 +115,14 @@ static uint32_t signalEvent()
     return NRF_SUCCESS;
 }
 
+
 error_t btle_init(void)
 {
     nrf_clock_lf_cfg_t clockConfiguration;
 
+    // register softdevice handler vector
+    NVIC_SetVector(SD_EVT_IRQn, (uint32_t) SD_EVT_IRQHandler);
+    
     // Configure the LF clock according to values provided by btle_clock.h.
     // It is input from the chain of the yotta configuration system.
     clockConfiguration.source        = LFCLK_CONF_SOURCE;
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c
index 821e2b3bf41..aaf82a83ada 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c
@@ -39,6 +39,7 @@ static const PinMap PinMap_ADC[] = {
     {NC, NC, 0}
 };
 
+void ADC_IRQHandler(void); // export IRQ handler from nrf_drv_adc.c
 
 void analogin_init(analogin_t *obj, PinName pin)
 {
@@ -50,6 +51,8 @@ void analogin_init(analogin_t *obj, PinName pin)
     
     obj->adc_pin =  pinFunc;
     
+    NVIC_SetVector(ADC_IRQn, (uint32_t)ADC_IRQHandler);
+    
     ret_code_t ret_code;
                                               // p_config, event_handler
     ret_code = nrf_drv_adc_init(NULL , NULL); // select blocking mode
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S
index f57ccfe64bf..32a39012cf6 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S
@@ -45,28 +45,28 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 ; External Interrupts
                 DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
                 DCD      RADIO_IRQHandler ;RADIO
-                DCD      UART0_IRQHandler ;UART0
-                DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
-                DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+                DCD      UART0_IRQHandler_v ;UART0
+                DCD      SPI0_TWI0_IRQHandler_v ;SPI0_TWI0
+                DCD      SPI1_TWI1_IRQHandler_v ;SPI1_TWI1
                 DCD      0 ;Reserved
-                DCD      GPIOTE_IRQHandler ;GPIOTE
-                DCD      ADC_IRQHandler ;ADC
+                DCD      GPIOTE_IRQHandler_v ;GPIOTE
+                DCD      ADC_IRQHandler_v ;ADC
                 DCD      TIMER0_IRQHandler ;TIMER0
-                DCD      TIMER1_IRQHandler ;TIMER1
-                DCD      TIMER2_IRQHandler ;TIMER2
+                DCD      TIMER1_IRQHandler_v ;TIMER1
+                DCD      TIMER2_IRQHandler_v ;TIMER2
                 DCD      RTC0_IRQHandler ;RTC0
                 DCD      TEMP_IRQHandler ;TEMP
                 DCD      RNG_IRQHandler ;RNG
                 DCD      ECB_IRQHandler ;ECB
                 DCD      CCM_AAR_IRQHandler ;CCM_AAR
-                DCD      WDT_IRQHandler ;WDT
-                DCD      RTC1_IRQHandler ;RTC1
-                DCD      QDEC_IRQHandler ;QDEC
-                DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
-                DCD      SWI0_IRQHandler ;SWI0
-                DCD      SWI1_IRQHandler ;SWI1
-                DCD      SWI2_IRQHandler ;SWI2
-                DCD      SWI3_IRQHandler ;SWI3
+                DCD      WDT_IRQHandler_v ;WDT
+                DCD      RTC1_IRQHandler_v ;RTC1
+                DCD      QDEC_IRQHandler_v ;QDEC
+                DCD      LPCOMP_IRQHandler_v ;LPCOMP_COMP
+                DCD      SWI0_IRQHandler_v ;SWI0
+                DCD      SWI1_IRQHandler_v ;SWI1
+                DCD      SWI2_IRQHandler_v ;SWI2
+                DCD      SWI3_IRQHandler_v ;SWI3
                 DCD      SWI4_IRQHandler ;SWI4
                 DCD      SWI5_IRQHandler ;SWI5
                 DCD      0 ;Reserved
@@ -92,6 +92,7 @@ Reset_Handler   PROC
                 EXPORT  Reset_Handler             [WEAK]
                 IMPORT  SystemInit				
                 IMPORT  __main
+                IMPORT  nrf_reloc_vector_table
                 LDR     R0, =NRF_POWER_RAMON_ADDRESS
                 LDR     R2, [R0]
                 MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
@@ -99,6 +100,8 @@ Reset_Handler   PROC
                 STR     R2, [R0]
                 LDR     R0, =SystemInit               
                 BLX     R0
+                LDR     R0, =nrf_reloc_vector_table
+                BLX     R0
                 LDR     R0, =__main
                 BX      R0
                 ENDP
@@ -131,52 +134,52 @@ Default_Handler PROC
 
                 EXPORT   POWER_CLOCK_IRQHandler [WEAK]
                 EXPORT   RADIO_IRQHandler [WEAK]
-                EXPORT   UART0_IRQHandler [WEAK]
-                EXPORT   SPI0_TWI0_IRQHandler [WEAK]
-                EXPORT   SPI1_TWI1_IRQHandler [WEAK]
-                EXPORT   GPIOTE_IRQHandler [WEAK]
-                EXPORT   ADC_IRQHandler [WEAK]
+                EXPORT   UART0_IRQHandler_v [WEAK]
+                EXPORT   SPI0_TWI0_IRQHandler_v [WEAK]
+                EXPORT   SPI1_TWI1_IRQHandler_v [WEAK]
+                EXPORT   GPIOTE_IRQHandler_v [WEAK]
+                EXPORT   ADC_IRQHandler_v [WEAK]
                 EXPORT   TIMER0_IRQHandler [WEAK]
-                EXPORT   TIMER1_IRQHandler [WEAK]
-                EXPORT   TIMER2_IRQHandler [WEAK]
+                EXPORT   TIMER1_IRQHandler_v [WEAK]
+                EXPORT   TIMER2_IRQHandler_v [WEAK]
                 EXPORT   RTC0_IRQHandler [WEAK]
                 EXPORT   TEMP_IRQHandler [WEAK]
                 EXPORT   RNG_IRQHandler [WEAK]
                 EXPORT   ECB_IRQHandler [WEAK]
                 EXPORT   CCM_AAR_IRQHandler [WEAK]
-                EXPORT   WDT_IRQHandler [WEAK]
-                EXPORT   RTC1_IRQHandler [WEAK]
-                EXPORT   QDEC_IRQHandler [WEAK]
-                EXPORT   LPCOMP_COMP_IRQHandler [WEAK]
-                EXPORT   SWI0_IRQHandler [WEAK]
-                EXPORT   SWI1_IRQHandler [WEAK]
-                EXPORT   SWI2_IRQHandler [WEAK]
-                EXPORT   SWI3_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler_v [WEAK]
+                EXPORT   RTC1_IRQHandler_v [WEAK]
+                EXPORT   QDEC_IRQHandler_v [WEAK]
+                EXPORT   LPCOMP_IRQHandler_v [WEAK]
+                EXPORT   SWI0_IRQHandler_v [WEAK]
+                EXPORT   SWI1_IRQHandler_v [WEAK]
+                EXPORT   SWI2_IRQHandler_v [WEAK]
+                EXPORT   SWI3_IRQHandler_v [WEAK]
                 EXPORT   SWI4_IRQHandler [WEAK]
                 EXPORT   SWI5_IRQHandler [WEAK]
 POWER_CLOCK_IRQHandler
 RADIO_IRQHandler
-UART0_IRQHandler
-SPI0_TWI0_IRQHandler
-SPI1_TWI1_IRQHandler
-GPIOTE_IRQHandler
-ADC_IRQHandler
+UART0_IRQHandler_v
+SPI0_TWI0_IRQHandler_v
+SPI1_TWI1_IRQHandler_v
+GPIOTE_IRQHandler_v
+ADC_IRQHandler_v
 TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
+TIMER1_IRQHandler_v
+TIMER2_IRQHandler_v
 RTC0_IRQHandler
 TEMP_IRQHandler
 RNG_IRQHandler
 ECB_IRQHandler
 CCM_AAR_IRQHandler
-WDT_IRQHandler
-RTC1_IRQHandler
-QDEC_IRQHandler
-LPCOMP_COMP_IRQHandler
-SWI0_IRQHandler
-SWI1_IRQHandler
-SWI2_IRQHandler
-SWI3_IRQHandler
+WDT_IRQHandler_v
+RTC1_IRQHandler_v
+QDEC_IRQHandler_v
+LPCOMP_IRQHandler_v
+SWI0_IRQHandler_v
+SWI1_IRQHandler_v
+SWI2_IRQHandler_v
+SWI3_IRQHandler_v
 SWI4_IRQHandler
 SWI5_IRQHandler
 
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
index 6396fd84fea..3a268542b04 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
@@ -12,13 +12,16 @@
 ;
 ;WITH SOFTDEVICE:
 
-LR_IROM1 0x0001B000 0x0025000  {
-  ER_IROM1 0x0001B000 0x0025000  {
+LR_IROM1 0x1B000 0x0025000  {
+  ER_IROM1 0x1B000 0x0025000  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20002ef8 0x5108  {
+  RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x20002FB8 0x00005048  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S
index ea211543df5..d7c0f737d1e 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S
@@ -45,28 +45,28 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 ; External Interrupts
                 DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
                 DCD      RADIO_IRQHandler ;RADIO
-                DCD      UART0_IRQHandler ;UART0
-                DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
-                DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+                DCD      UART0_IRQHandler_v ;UART0
+                DCD      SPI0_TWI0_IRQHandler_v ;SPI0_TWI0
+                DCD      SPI1_TWI1_IRQHandler_v ;SPI1_TWI1
                 DCD      0 ;Reserved
-                DCD      GPIOTE_IRQHandler ;GPIOTE
-                DCD      ADC_IRQHandler ;ADC
+                DCD      GPIOTE_IRQHandler_v ;GPIOTE
+                DCD      ADC_IRQHandler_v ;ADC
                 DCD      TIMER0_IRQHandler ;TIMER0
-                DCD      TIMER1_IRQHandler ;TIMER1
-                DCD      TIMER2_IRQHandler ;TIMER2
+                DCD      TIMER1_IRQHandler_v ;TIMER1
+                DCD      TIMER2_IRQHandler_v ;TIMER2
                 DCD      RTC0_IRQHandler ;RTC0
                 DCD      TEMP_IRQHandler ;TEMP
                 DCD      RNG_IRQHandler ;RNG
                 DCD      ECB_IRQHandler ;ECB
                 DCD      CCM_AAR_IRQHandler ;CCM_AAR
-                DCD      WDT_IRQHandler ;WDT
-                DCD      RTC1_IRQHandler ;RTC1
-                DCD      QDEC_IRQHandler ;QDEC
-                DCD      LPCOMP_IRQHandler ;LPCOMP
-                DCD      SWI0_IRQHandler ;SWI0
-                DCD      SWI1_IRQHandler ;SWI1
-                DCD      SWI2_IRQHandler ;SWI2
-                DCD      SWI3_IRQHandler ;SWI3
+                DCD      WDT_IRQHandler_v ;WDT
+                DCD      RTC1_IRQHandler_v ;RTC1
+                DCD      QDEC_IRQHandler_v ;QDEC
+                DCD      LPCOMP_IRQHandler_v ;LPCOMP_COMP
+                DCD      SWI0_IRQHandler_v ;SWI0
+                DCD      SWI1_IRQHandler_v ;SWI1
+                DCD      SWI2_IRQHandler_v ;SWI2
+                DCD      SWI3_IRQHandler_v ;SWI3
                 DCD      SWI4_IRQHandler ;SWI4
                 DCD      SWI5_IRQHandler ;SWI5
                 DCD      0 ;Reserved
@@ -93,6 +93,7 @@ Reset_Handler   PROC
                 EXPORT  Reset_Handler             [WEAK]
                 IMPORT  SystemInit
                 IMPORT  __main
+                IMPORT  nrf_reloc_vector_table
                 
                 MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
                 
@@ -108,6 +109,8 @@ Reset_Handler   PROC
                 
                 LDR     R0, =SystemInit
                 BLX     R0
+                LDR     R0, =nrf_reloc_vector_table
+                BLX     R0
                 LDR     R0, =__main
                 BX      R0
                 ENDP
@@ -140,52 +143,52 @@ Default_Handler PROC
 
                 EXPORT   POWER_CLOCK_IRQHandler [WEAK]
                 EXPORT   RADIO_IRQHandler [WEAK]
-                EXPORT   UART0_IRQHandler [WEAK]
-                EXPORT   SPI0_TWI0_IRQHandler [WEAK]
-                EXPORT   SPI1_TWI1_IRQHandler [WEAK]
-                EXPORT   GPIOTE_IRQHandler [WEAK]
-                EXPORT   ADC_IRQHandler [WEAK]
+                EXPORT   UART0_IRQHandler_v [WEAK]
+                EXPORT   SPI0_TWI0_IRQHandler_v [WEAK]
+                EXPORT   SPI1_TWI1_IRQHandler_v [WEAK]
+                EXPORT   GPIOTE_IRQHandler_v [WEAK]
+                EXPORT   ADC_IRQHandler_v [WEAK]
                 EXPORT   TIMER0_IRQHandler [WEAK]
-                EXPORT   TIMER1_IRQHandler [WEAK]
-                EXPORT   TIMER2_IRQHandler [WEAK]
+                EXPORT   TIMER1_IRQHandler_v [WEAK]
+                EXPORT   TIMER2_IRQHandler_v [WEAK]
                 EXPORT   RTC0_IRQHandler [WEAK]
                 EXPORT   TEMP_IRQHandler [WEAK]
                 EXPORT   RNG_IRQHandler [WEAK]
                 EXPORT   ECB_IRQHandler [WEAK]
                 EXPORT   CCM_AAR_IRQHandler [WEAK]
-                EXPORT   WDT_IRQHandler [WEAK]
-                EXPORT   RTC1_IRQHandler [WEAK]
-                EXPORT   QDEC_IRQHandler [WEAK]
-                EXPORT   LPCOMP_IRQHandler [WEAK]
-                EXPORT   SWI0_IRQHandler [WEAK]
-                EXPORT   SWI1_IRQHandler [WEAK]
-                EXPORT   SWI2_IRQHandler [WEAK]
-                EXPORT   SWI3_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler_v [WEAK]
+                EXPORT   RTC1_IRQHandler_v [WEAK]
+                EXPORT   QDEC_IRQHandler_v [WEAK]
+                EXPORT   LPCOMP_IRQHandler_v [WEAK]
+                EXPORT   SWI0_IRQHandler_v [WEAK]
+                EXPORT   SWI1_IRQHandler_v [WEAK]
+                EXPORT   SWI2_IRQHandler_v [WEAK]
+                EXPORT   SWI3_IRQHandler_v [WEAK]
                 EXPORT   SWI4_IRQHandler [WEAK]
                 EXPORT   SWI5_IRQHandler [WEAK]
 POWER_CLOCK_IRQHandler
 RADIO_IRQHandler
-UART0_IRQHandler
-SPI0_TWI0_IRQHandler
-SPI1_TWI1_IRQHandler
-GPIOTE_IRQHandler
-ADC_IRQHandler
+UART0_IRQHandler_v
+SPI0_TWI0_IRQHandler_v
+SPI1_TWI1_IRQHandler_v
+GPIOTE_IRQHandler_v
+ADC_IRQHandler_v
 TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
+TIMER1_IRQHandler_v
+TIMER2_IRQHandler_v
 RTC0_IRQHandler
 TEMP_IRQHandler
 RNG_IRQHandler
 ECB_IRQHandler
 CCM_AAR_IRQHandler
-WDT_IRQHandler
-RTC1_IRQHandler
-QDEC_IRQHandler
-LPCOMP_IRQHandler
-SWI0_IRQHandler
-SWI1_IRQHandler
-SWI2_IRQHandler
-SWI3_IRQHandler
+WDT_IRQHandler_v
+RTC1_IRQHandler_v
+QDEC_IRQHandler_v
+LPCOMP_IRQHandler_v
+SWI0_IRQHandler_v
+SWI1_IRQHandler_v
+SWI2_IRQHandler_v
+SWI3_IRQHandler_v
 SWI4_IRQHandler
 SWI5_IRQHandler
 
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
index 94e85ccb7b9..ef516aa805a 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
@@ -12,13 +12,16 @@
 ;
 ;WITH SOFTDEVICE:
 
-LR_IROM1 0x0001B000 0x0025000  {
-  ER_IROM1 0x0001B000 0x0025000  {
+LR_IROM1 0x18000 0x0028000  {
+  ER_IROM1 0x18000 0x0028000  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20002ef8 0x1108  {
+  RW_IRAM0 0x20002000 UNINIT 0x000000c0  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x200020C0 0x00001F40  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
index 94e85ccb7b9..585ae2080d8 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
@@ -18,7 +18,10 @@ LR_IROM1 0x0001B000 0x0025000  {
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20002ef8 0x1108  {
+  RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x20002FB8 0x00001048  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
index 3c6c450487d..c48425a1479 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
@@ -120,6 +120,13 @@ SECTIONS
 	} > RAM
 
     __edata = .;
+    
+    .noinit :
+    {
+      PROVIDE(__start_noinit = .);
+      KEEP(*(.noinit))
+      PROVIDE(__stop_noinit = .);
+    } > RAM
 
 	.bss :
 	{
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld
index 1a3065845c6..fd2e208390a 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld
@@ -119,6 +119,13 @@ SECTIONS
 
 	} > RAM
 
+    .noinit :
+    {
+      PROVIDE(__start_noinit = .);
+      KEEP(*(.noinit))
+      PROVIDE(__stop_noinit = .);
+    } > RAM
+    
 	.bss :
 	{
 		. = ALIGN(4);
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S
index 03f6daaf53e..491e7123137 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S
@@ -90,36 +90,30 @@ __Vectors:
   /* External Interrupts */
     .long 	POWER_CLOCK_IRQHandler		 /*POWER_CLOCK */
     .long 	RADIO_IRQHandler		 /*RADIO */
-    .long 	UART0_IRQHandler		 /*UART0 */
-    .long 	SPI0_TWI0_IRQHandler		 /*SPI0_TWI0 */
-    .long 	SPI1_TWI1_IRQHandler		 /*SPI1_TWI1 */
+    .long 	UART0_IRQHandler_v		 /*UART0 */
+    .long 	SPI0_TWI0_IRQHandler_v		 /*SPI0_TWI0 */
+    .long 	SPI1_TWI1_IRQHandler_v		 /*SPI1_TWI1 */
     .long 	0		 /*Reserved */
-    .long 	GPIOTE_IRQHandler		 /*GPIOTE */
-    .long 	ADC_IRQHandler		 /*ADC */
+    .long 	GPIOTE_IRQHandler_v		 /*GPIOTE */
+    .long 	ADC_IRQHandler_v		 /*ADC */
     .long 	TIMER0_IRQHandler		 /*TIMER0 */
-    .long 	TIMER1_IRQHandler		 /*TIMER1 */
-    .long 	TIMER2_IRQHandler		 /*TIMER2 */
+    .long 	TIMER1_IRQHandler_v	 /*TIMER1 */
+    .long 	TIMER2_IRQHandler_v		 /*TIMER2 */
     .long 	RTC0_IRQHandler		 /*RTC0 */
     .long 	TEMP_IRQHandler		 /*TEMP */
     .long 	RNG_IRQHandler		 /*RNG */
     .long 	ECB_IRQHandler		 /*ECB */
     .long 	CCM_AAR_IRQHandler		 /*CCM_AAR */
-    .long 	WDT_IRQHandler		 /*WDT */
-    .long 	RTC1_IRQHandler		 /*RTC1 */
-    .long 	QDEC_IRQHandler		 /*QDEC */
-    .long 	LPCOMP_IRQHandler		 /*LPCOMP */
-    .long 	SWI0_IRQHandler		 /*SWI0 */
-    .long 	SWI1_IRQHandler		 /*SWI1 */
-    .long 	SWI2_IRQHandler		 /*SWI2 */
-    .long 	SWI3_IRQHandler		 /*SWI3 */
+    .long 	WDT_IRQHandler_v		 /*WDT */
+    .long 	RTC1_IRQHandler_v		 /*RTC1 */
+    .long 	QDEC_IRQHandler_v		 /*QDEC */
+    .long 	LPCOMP_IRQHandler_v		 /*LPCOMP */
+    .long 	SWI0_IRQHandler_v		 /*SWI0 */
+    .long 	SWI1_IRQHandler_v		 /*SWI1 */
+    .long 	SWI2_IRQHandler_v		 /*SWI2 */
+    .long 	SWI3_IRQHandler_v		 /*SWI3 */
     .long 	SWI4_IRQHandler		 /*SWI4 */
     .long 	SWI5_IRQHandler		 /*SWI5 */
-    .long 	0		 /*Reserved */
-    .long 	0		 /*Reserved */
-    .long 	0		 /*Reserved */
-    .long 	0		 /*Reserved */
-    .long 	0		 /*Reserved */
-    .long 	0		 /*Reserved */
 
 
     .size    __Vectors, . - __Vectors
@@ -173,6 +167,8 @@ Reset_Handler:
 
     LDR     R0, =SystemInit
     BLX     R0
+    LDR     R0, =nrf_reloc_vector_table
+    BLX     R0
     LDR     R0, =_start
     BX      R0
 
@@ -234,31 +230,31 @@ Default_Handler:
     .set    \handler, Default_Handler
     .endm
 
-    IRQ  POWER_CLOCK_IRQHandler
-    IRQ  RADIO_IRQHandler
-    IRQ  UART0_IRQHandler
-    IRQ  SPI0_TWI0_IRQHandler
-    IRQ  SPI1_TWI1_IRQHandler
-    IRQ  GPIOTE_IRQHandler
-    IRQ  ADC_IRQHandler
-    IRQ  TIMER0_IRQHandler
-    IRQ  TIMER1_IRQHandler
-    IRQ  TIMER2_IRQHandler
-    IRQ  RTC0_IRQHandler
-    IRQ  TEMP_IRQHandler
-    IRQ  RNG_IRQHandler
-    IRQ  ECB_IRQHandler
-    IRQ  CCM_AAR_IRQHandler
-    IRQ  WDT_IRQHandler
-    IRQ  RTC1_IRQHandler
-    IRQ  QDEC_IRQHandler
-    IRQ  LPCOMP_IRQHandler
-    IRQ  SWI0_IRQHandler
-    IRQ  SWI1_IRQHandler
-    IRQ  SWI2_IRQHandler
-    IRQ  SWI3_IRQHandler
-    IRQ  SWI4_IRQHandler
-    IRQ  SWI5_IRQHandler
+    IRQ  POWER_CLOCK_IRQHandler     /* restricted */
+    IRQ  RADIO_IRQHandler           /* blocked */
+    IRQ  UART0_IRQHandler_v
+    IRQ  SPI0_TWI0_IRQHandler_v
+    IRQ  SPI1_TWI1_IRQHandler_v
+    IRQ  GPIOTE_IRQHandler_v
+    IRQ  ADC_IRQHandler_v
+    IRQ  TIMER0_IRQHandler          /* blocked */
+    IRQ  TIMER1_IRQHandler_v
+    IRQ  TIMER2_IRQHandler_v
+    IRQ  RTC0_IRQHandler          /* blocked */
+    IRQ  TEMP_IRQHandler          /* restricted */
+    IRQ  RNG_IRQHandler           /* restricted */
+    IRQ  ECB_IRQHandler           /* restricted */
+    IRQ  CCM_AAR_IRQHandler       /* blocked */
+    IRQ  WDT_IRQHandler_v
+    IRQ  RTC1_IRQHandler_v
+    IRQ  QDEC_IRQHandler_v
+    IRQ  LPCOMP_IRQHandler_v
+    IRQ  SWI0_IRQHandler_v
+    IRQ  SWI1_IRQHandler_v         /* restricted for Radio Notification */
+    IRQ  SWI2_IRQHandler_v         /* blocked for SoftDevice Event */
+    IRQ  SWI3_IRQHandler_v
+    IRQ  SWI4_IRQHandler         /* blocked */
+    IRQ  SWI5_IRQHandler         /* blocked */
 
 
   .end
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S
deleted file mode 100644
index b1e263009cc..00000000000
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S
+++ /dev/null
@@ -1,237 +0,0 @@
-;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
-;; The information contained herein is confidential property of Nordic
-;; Semiconductor ASA.Terms and conditions of usage are described in detail
-;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
-;; Licensees are granted free, non-transferable use of the information. NO
-;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
-;; the file.
-
-;; Description message
-
-        MODULE  ?cstartup
-
-        ;; Stack size default : 1024
-        ;; Heap size default : 2048
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-;__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
-        DCD      RADIO_IRQHandler ;RADIO
-        DCD      UART0_IRQHandler ;UART0
-        DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
-        DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
-        DCD      0 ;Reserved
-        DCD      GPIOTE_IRQHandler ;GPIOTE
-        DCD      ADC_IRQHandler ;ADC
-        DCD      TIMER0_IRQHandler ;TIMER0
-        DCD      TIMER1_IRQHandler ;TIMER1
-        DCD      TIMER2_IRQHandler ;TIMER2
-        DCD      RTC0_IRQHandler ;RTC0
-        DCD      TEMP_IRQHandler ;TEMP
-        DCD      RNG_IRQHandler ;RNG
-        DCD      ECB_IRQHandler ;ECB
-        DCD      CCM_AAR_IRQHandler ;CCM_AAR
-        DCD      WDT_IRQHandler ;WDT
-        DCD      RTC1_IRQHandler ;RTC1
-        DCD      QDEC_IRQHandler ;QDEC
-        DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
-        DCD      SWI0_IRQHandler ;SWI0
-        DCD      SWI1_IRQHandler ;SWI1
-        DCD      SWI2_IRQHandler ;SWI2
-        DCD      SWI3_IRQHandler ;SWI3
-        DCD      SWI4_IRQHandler ;SWI4
-        DCD      SWI5_IRQHandler ;SWI5
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-
-
-__Vectors_End
-__Vectors                           EQU   __vector_table
-__Vectors_Size                      EQU   __Vectors_End - __Vectors
-NRF_POWER_RAMON_ADDRESS             EQU   0x40000524  ; NRF_POWER->RAMON address
-NRF_POWER_RAMON_RAMxON_ONMODE_Msk   EQU   0xF         ; All RAM blocks on in onmode bit mask
-
-; Default handlers.
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =NRF_POWER_RAMON_ADDRESS
-        LDR     R2, [R0]
-        MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
-        ORRS    R2, R2, R1
-        STR     R2, [R0]
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        ; Dummy exception handlers
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B .
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B .
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B .
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B .
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B .
-
-       ; Dummy interrupt handlers
-
-        PUBWEAK  POWER_CLOCK_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-POWER_CLOCK_IRQHandler
-        B .
-        PUBWEAK  RADIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RADIO_IRQHandler
-        B .
-        PUBWEAK  UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B .
-        PUBWEAK  SPI0_TWI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI0_TWI0_IRQHandler
-        B .
-        PUBWEAK  SPI1_TWI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_TWI1_IRQHandler
-        B .
-        PUBWEAK  GPIOTE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-GPIOTE_IRQHandler
-        B .
-        PUBWEAK  ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler
-        B .
-        PUBWEAK  TIMER0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER0_IRQHandler
-        B .
-        PUBWEAK  TIMER1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER1_IRQHandler
-        B .
-        PUBWEAK  TIMER2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER2_IRQHandler
-        B .
-        PUBWEAK  RTC0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC0_IRQHandler
-        B .
-        PUBWEAK  TEMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TEMP_IRQHandler
-        B .
-        PUBWEAK  RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RNG_IRQHandler
-        B .
-        PUBWEAK  ECB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ECB_IRQHandler
-        B .
-        PUBWEAK  CCM_AAR_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CCM_AAR_IRQHandler
-        B .
-        PUBWEAK  WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B .
-        PUBWEAK  RTC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC1_IRQHandler
-        B .
-        PUBWEAK  QDEC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-QDEC_IRQHandler
-        B .
-        PUBWEAK  LPCOMP_COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LPCOMP_COMP_IRQHandler
-        B .
-        PUBWEAK  SWI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SWI0_IRQHandler
-        B .
-        PUBWEAK  SWI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SWI1_IRQHandler
-        B .
-        PUBWEAK  SWI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SWI2_IRQHandler
-        B .
-        PUBWEAK  SWI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SWI3_IRQHandler
-        B .
-        PUBWEAK  SWI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SWI4_IRQHandler
-        B .
-        PUBWEAK  SWI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SWI5_IRQHandler
-        B .
-
-
-        END
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/startup_NRF51822_IAR.S
similarity index 77%
rename from targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S
rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/startup_NRF51822_IAR.S
index c0a2b08eabd..4021495366f 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/startup_NRF51822_IAR.S
@@ -20,6 +20,7 @@
 
         EXTERN  __iar_program_start
         EXTERN  SystemInit
+        EXTERN  nrf_reloc_vector_table
         PUBLIC  __vector_table
         PUBLIC  __Vectors
         PUBLIC  __Vectors_End
@@ -49,36 +50,30 @@ __vector_table
         ; External Interrupts
         DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
         DCD      RADIO_IRQHandler ;RADIO
-        DCD      UART0_IRQHandler ;UART0
-        DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
-        DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+        DCD      UART0_IRQHandler_v ;UART0
+        DCD      SPI0_TWI0_IRQHandler_v ;SPI0_TWI0
+        DCD      SPI1_TWI1_IRQHandler_v ;SPI1_TWI1
         DCD      0 ;Reserved
-        DCD      GPIOTE_IRQHandler ;GPIOTE
-        DCD      ADC_IRQHandler ;ADC
+        DCD      GPIOTE_IRQHandler_v ;GPIOTE
+        DCD      ADC_IRQHandler_v ;ADC
         DCD      TIMER0_IRQHandler ;TIMER0
-        DCD      TIMER1_IRQHandler ;TIMER1
-        DCD      TIMER2_IRQHandler ;TIMER2
+        DCD      TIMER1_IRQHandler_v ;TIMER1
+        DCD      TIMER2_IRQHandler_v ;TIMER2
         DCD      RTC0_IRQHandler ;RTC0
         DCD      TEMP_IRQHandler ;TEMP
         DCD      RNG_IRQHandler ;RNG
         DCD      ECB_IRQHandler ;ECB
         DCD      CCM_AAR_IRQHandler ;CCM_AAR
-        DCD      WDT_IRQHandler ;WDT
-        DCD      RTC1_IRQHandler ;RTC1
-        DCD      QDEC_IRQHandler ;QDEC
-        DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+        DCD      WDT_IRQHandler_v ;WDT
+        DCD      RTC1_IRQHandler_v ;RTC1
+        DCD      QDEC_IRQHandler_v ;QDEC
+        DCD      LPCOMP_IRQHandler_v ;LPCOMP_COMP
         DCD      SWI0_IRQHandler ;SWI0
-        DCD      SWI1_IRQHandler ;SWI1
-        DCD      SWI2_IRQHandler ;SWI2
-        DCD      SWI3_IRQHandler ;SWI3
+        DCD      SWI1_IRQHandler_v ;SWI1
+        DCD      SWI2_IRQHandler_v ;SWI2
+        DCD      SWI3_IRQHandler_v ;SWI3
         DCD      SWI4_IRQHandler ;SWI4
         DCD      SWI5_IRQHandler ;SWI5
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
-        DCD      0 ;Reserved
 
 
 __Vectors_End
@@ -100,6 +95,8 @@ Reset_Handler
         STR     R2, [R0]
         LDR     R0, =SystemInit
         BLX     R0
+        LDR     R0, =nrf_reloc_vector_table
+        BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
 
@@ -140,37 +137,37 @@ POWER_CLOCK_IRQHandler
         SECTION .text:CODE:REORDER:NOROOT(1)
 RADIO_IRQHandler
         B .
-        PUBWEAK  UART0_IRQHandler
+        PUBWEAK  UART0_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
+UART0_IRQHandler_v
         B .
-        PUBWEAK  SPI0_TWI0_IRQHandler
+        PUBWEAK  SPI0_TWI0_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-SPI0_TWI0_IRQHandler
+SPI0_TWI0_IRQHandler_v
         B .
-        PUBWEAK  SPI1_TWI1_IRQHandler
+        PUBWEAK  SPI1_TWI1_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_TWI1_IRQHandler
+SPI1_TWI1_IRQHandler_v
         B .
-        PUBWEAK  GPIOTE_IRQHandler
+        PUBWEAK  GPIOTE_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-GPIOTE_IRQHandler
+GPIOTE_IRQHandler_v
         B .
-        PUBWEAK  ADC_IRQHandler
+        PUBWEAK  ADC_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler
+ADC_IRQHandler_v
         B .
         PUBWEAK  TIMER0_IRQHandler
         SECTION .text:CODE:REORDER:NOROOT(1)
 TIMER0_IRQHandler
         B .
-        PUBWEAK  TIMER1_IRQHandler
+        PUBWEAK  TIMER1_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER1_IRQHandler
+TIMER1_IRQHandler_v
         B .
-        PUBWEAK  TIMER2_IRQHandler
+        PUBWEAK  TIMER2_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER2_IRQHandler
+TIMER2_IRQHandler_v
         B .
         PUBWEAK  RTC0_IRQHandler
         SECTION .text:CODE:REORDER:NOROOT(1)
@@ -192,37 +189,37 @@ ECB_IRQHandler
         SECTION .text:CODE:REORDER:NOROOT(1)
 CCM_AAR_IRQHandler
         B .
-        PUBWEAK  WDT_IRQHandler
+        PUBWEAK  WDT_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
+WDT_IRQHandler_v
         B .
-        PUBWEAK  RTC1_IRQHandler
+        PUBWEAK  RTC1_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-RTC1_IRQHandler
+RTC1_IRQHandler_v
         B .
-        PUBWEAK  QDEC_IRQHandler
+        PUBWEAK  QDEC_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-QDEC_IRQHandler
+QDEC_IRQHandler_v
         B .
-        PUBWEAK  LPCOMP_COMP_IRQHandler
+        PUBWEAK  LPCOMP_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-LPCOMP_COMP_IRQHandler
+LPCOMP_IRQHandler_v
         B .
         PUBWEAK  SWI0_IRQHandler
         SECTION .text:CODE:REORDER:NOROOT(1)
 SWI0_IRQHandler
         B .
-        PUBWEAK  SWI1_IRQHandler
+        PUBWEAK  SWI1_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-SWI1_IRQHandler
+SWI1_IRQHandler_v
         B .
-        PUBWEAK  SWI2_IRQHandler
+        PUBWEAK  SWI2_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-SWI2_IRQHandler
+SWI2_IRQHandler_v
         B .
-        PUBWEAK  SWI3_IRQHandler
+        PUBWEAK  SWI3_IRQHandler_v
         SECTION .text:CODE:REORDER:NOROOT(1)
-SWI3_IRQHandler
+SWI3_IRQHandler_v
         B .
         PUBWEAK  SWI4_IRQHandler
         SECTION .text:CODE:REORDER:NOROOT(1)
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c
index 5fe8d89d6f4..cdaa2042eef 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c
@@ -30,74 +30,14 @@
  */
 #include "cmsis_nvic.h"
 
-/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
- * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), 
- * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF 
- * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
- * 
- * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
- * above the vector table before 0x200 will actually go to RAM. So we need to provide 
- * a solution where the compiler gets the right results based on the memory map
- *
- * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
- *  - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
- *  - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
- * 
- * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there  
- *  - No flash accesses will go to ram, as there will be nothing there
- *  - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
- *  - RAM overhead: 0, FLASH overhead: 320 bytes
- *
- * Option 2 is the one to go for, as RAM is the most valuable resource
- */
-
-
-#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
-/*
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    uint32_t i;
+extern uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
 
-    // Copy and switch to dynamic vectors if the first time called
-    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = vectors;
-        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + 16] = vector;
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
 }
 
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + 16];
-}*/
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-   // int i;
-    // Space for dynamic vectors, initialised to allocate in R/W
-    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-    /*
-    // Copy and switch to dynamic vectors if first time called
-    if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {     
-      uint32_t *old_vectors = (uint32_t *)0;         // FLASH vectors are at 0x0
-      for(i = 0; i < NVIC_NUM_VECTORS; i++) {    
-            vectors[i] = old_vectors[i];
-        }
-        LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
-    }*/
-
-    // Set the vector 
-    vectors[IRQn + 16] = vector; 
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    // We can always read vectors at 0x0, as the addresses are remapped
-    uint32_t *vectors = (uint32_t*)0; 
-
-    // Return the vector
-    return vectors[IRQn + 16];
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    return nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET];
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c
index c4b5b94a76f..c018ee91e3c 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c
@@ -95,6 +95,23 @@ static void pwm_reinit(pwm_t * pwm)
     }
 }
 
+void GPIOTE_IRQHandler(void);// exported from nrf_drv_gpiote.c
+
+void TIMER1_IRQHandler(void);
+void TIMER2_IRQHandler(void);
+
+static const peripheral_handler_desc_t timer_handlers[] =
+{
+    {
+        TIMER1_IRQn,
+        (uint32_t)TIMER1_IRQHandler
+    },
+    {
+        TIMER2_IRQn,
+        (uint32_t)TIMER2_IRQHandler
+    }
+};
+
 void pwmout_init(pwmout_t *obj, PinName pin)
 {
     if (pin == NC) {
@@ -140,6 +157,11 @@ void pwmout_init(pwmout_t *obj, PinName pin)
     m_pwm[free_instance].pins[free_channel] = (uint32_t) pin;
     m_pwm[free_instance].duty_ticks[free_channel] = 0;
     if (!m_pwm[free_instance].channels_allocated) {
+
+        NVIC_SetVector(GPIOTE_IRQn, (uint32_t) GPIOTE_IRQHandler);
+
+        NVIC_SetVector(timer_handlers[free_instance].IRQn, timer_handlers[free_instance].vector);
+        
         m_pwm[free_instance].period_us = PWM_DEFAULT_PERIOD_US;
         for (uint8_t channel = 1; channel < PWM_CHANNELS_PER_INSTANCE; ++channel) {
             m_pwm[free_instance].pins[channel] = APP_PWM_NOPIN;
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c
index c527261e862..e730241c079 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c
@@ -38,10 +38,14 @@ static const nrf_drv_saadc_config_t saadc_config =
     .interrupt_priority = APP_IRQ_PRIORITY_LOW
 };
 
+void SAADC_IRQHandler(void);
+
 void analogin_init(analogin_t *obj, PinName pin)
 {
     ret_code_t ret_code;
     
+    NVIC_SetVector(SAADC_IRQn, (uint32_t)SAADC_IRQHandler);
+    
     ret_code = nrf_drv_saadc_init(&saadc_config, analog_in_event_handler);
     MBED_ASSERT(((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_INVALID_STATE))); //NRF_ERROR_INVALID_STATE expected for multiple channels used.
     
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct
index 70df192ed23..3bb13ec74ac 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct
@@ -18,7 +18,10 @@ LR_IROM1 0x1C000 0x0064000  {
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20002EF8 0x0000D108  {
+  RW_IRAM0 0x20002EF8 UNINIT 0x000000D8  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x20002FD0 0x0000D030  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s
index 4a783efe387..aac3e2c28fb 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s
@@ -57,244 +57,43 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 ; External Interrupts
                 DCD     POWER_CLOCK_IRQHandler
                 DCD     RADIO_IRQHandler
-                DCD     UARTE0_UART0_IRQHandler
-                DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
-                DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
-                DCD     NFCT_IRQHandler
-                DCD     GPIOTE_IRQHandler
-                DCD     SAADC_IRQHandler
-                DCD     TIMER0_IRQHandler
-                DCD     TIMER1_IRQHandler
-                DCD     TIMER2_IRQHandler
+                DCD     UARTE0_UART0_IRQHandler_v
+                DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+                DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+                DCD     NFCT_IRQHandler_v
+                DCD     GPIOTE_IRQHandler_v
+                DCD     SAADC_IRQHandler_v
+                DCD     TIMER0_IRQHandler_v
+                DCD     TIMER1_IRQHandler_v
+                DCD     TIMER2_IRQHandler_v
                 DCD     RTC0_IRQHandler
-                DCD     TEMP_IRQHandler
+                DCD     TEMP_IRQHandler_v
                 DCD     RNG_IRQHandler
                 DCD     ECB_IRQHandler
                 DCD     CCM_AAR_IRQHandler
-                DCD     WDT_IRQHandler
-                DCD     RTC1_IRQHandler
-                DCD     QDEC_IRQHandler
-                DCD     COMP_LPCOMP_IRQHandler
-                DCD     SWI0_EGU0_IRQHandler
-                DCD     SWI1_EGU1_IRQHandler
-                DCD     SWI2_EGU2_IRQHandler
-                DCD     SWI3_EGU3_IRQHandler
+                DCD     WDT_IRQHandler_v
+                DCD     RTC1_IRQHandler_v
+                DCD     QDEC_IRQHandler_v
+                DCD     COMP_LPCOMP_IRQHandler_v
+                DCD     SWI0_EGU0_IRQHandler_v
+                DCD     SWI1_EGU1_IRQHandler_v
+                DCD     SWI2_EGU2_IRQHandler_v
+                DCD     SWI3_EGU3_IRQHandler_v
                 DCD     SWI4_EGU4_IRQHandler
                 DCD     SWI5_EGU5_IRQHandler
-                DCD     TIMER3_IRQHandler
-                DCD     TIMER4_IRQHandler
-                DCD     PWM0_IRQHandler
-                DCD     PDM_IRQHandler
+                DCD     TIMER3_IRQHandler_v
+                DCD     TIMER4_IRQHandler_v
+                DCD     PWM0_IRQHandler_v
+                DCD     PDM_IRQHandler_v
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
                 DCD     MWU_IRQHandler
-                DCD     PWM1_IRQHandler
-                DCD     PWM2_IRQHandler
-                DCD     SPIM2_SPIS2_SPI2_IRQHandler
-                DCD     RTC2_IRQHandler
-                DCD     I2S_IRQHandler
-                DCD     FPU_IRQHandler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
+                DCD     PWM1_IRQHandler_v
+                DCD     PWM2_IRQHandler_v
+                DCD     SPIM2_SPIS2_SPI2_IRQHandler_v
+                DCD     RTC2_IRQHandler_v
+                DCD     I2S_IRQHandler_v
+                DCD     FPU_IRQHandler_v
 
 __Vectors_End
 
@@ -309,10 +108,13 @@ Reset_Handler   PROC
                 EXPORT  Reset_Handler             [WEAK]
                 IMPORT  SystemInit
                 IMPORT  __main
+                IMPORT  nrf_reloc_vector_table
                 
                 
                 LDR     R0, =SystemInit
                 BLX     R0
+                LDR     R0, =nrf_reloc_vector_table
+                BLX     R0
                 LDR     R0, =__main
                 BX      R0
                 ENDP
@@ -365,78 +167,78 @@ Default_Handler PROC
 
                 EXPORT   POWER_CLOCK_IRQHandler [WEAK]
                 EXPORT   RADIO_IRQHandler [WEAK]
-                EXPORT   UARTE0_UART0_IRQHandler [WEAK]
-                EXPORT   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
-                EXPORT   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
-                EXPORT   NFCT_IRQHandler [WEAK]
-                EXPORT   GPIOTE_IRQHandler [WEAK]
-                EXPORT   SAADC_IRQHandler [WEAK]
-                EXPORT   TIMER0_IRQHandler [WEAK]
-                EXPORT   TIMER1_IRQHandler [WEAK]
-                EXPORT   TIMER2_IRQHandler [WEAK]
+                EXPORT   UARTE0_UART0_IRQHandler_v [WEAK]
+                EXPORT   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK]
+                EXPORT   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK]
+                EXPORT   NFCT_IRQHandler_v [WEAK]
+                EXPORT   GPIOTE_IRQHandler_v [WEAK]
+                EXPORT   SAADC_IRQHandler_v [WEAK]
+                EXPORT   TIMER0_IRQHandler_v [WEAK]
+                EXPORT   TIMER1_IRQHandler_v [WEAK]
+                EXPORT   TIMER2_IRQHandler_v [WEAK]
                 EXPORT   RTC0_IRQHandler [WEAK]
-                EXPORT   TEMP_IRQHandler [WEAK]
+                EXPORT   TEMP_IRQHandler_v [WEAK]
                 EXPORT   RNG_IRQHandler [WEAK]
                 EXPORT   ECB_IRQHandler [WEAK]
                 EXPORT   CCM_AAR_IRQHandler [WEAK]
-                EXPORT   WDT_IRQHandler [WEAK]
-                EXPORT   RTC1_IRQHandler [WEAK]
-                EXPORT   QDEC_IRQHandler [WEAK]
-                EXPORT   COMP_LPCOMP_IRQHandler [WEAK]
-                EXPORT   SWI0_EGU0_IRQHandler [WEAK]
-                EXPORT   SWI1_EGU1_IRQHandler [WEAK]
-                EXPORT   SWI2_EGU2_IRQHandler [WEAK]
-                EXPORT   SWI3_EGU3_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler_v [WEAK]
+                EXPORT   RTC1_IRQHandler_v [WEAK]
+                EXPORT   QDEC_IRQHandler_v [WEAK]
+                EXPORT   COMP_LPCOMP_IRQHandler_v [WEAK]
+                EXPORT   SWI0_EGU0_IRQHandler_v [WEAK]
+                EXPORT   SWI1_EGU1_IRQHandler_v [WEAK]
+                EXPORT   SWI2_EGU2_IRQHandler_v [WEAK]
+                EXPORT   SWI3_EGU3_IRQHandler_v [WEAK]
                 EXPORT   SWI4_EGU4_IRQHandler [WEAK]
                 EXPORT   SWI5_EGU5_IRQHandler [WEAK]
-                EXPORT   TIMER3_IRQHandler [WEAK]
-                EXPORT   TIMER4_IRQHandler [WEAK]
-                EXPORT   PWM0_IRQHandler [WEAK]
-                EXPORT   PDM_IRQHandler [WEAK]
+                EXPORT   TIMER3_IRQHandler_v [WEAK]
+                EXPORT   TIMER4_IRQHandler_v [WEAK]
+                EXPORT   PWM0_IRQHandler_v [WEAK]
+                EXPORT   PDM_IRQHandler_v [WEAK]
                 EXPORT   MWU_IRQHandler [WEAK]
-                EXPORT   PWM1_IRQHandler [WEAK]
-                EXPORT   PWM2_IRQHandler [WEAK]
-                EXPORT   SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
-                EXPORT   RTC2_IRQHandler [WEAK]
-                EXPORT   I2S_IRQHandler [WEAK]
-                EXPORT   FPU_IRQHandler [WEAK]
+                EXPORT   PWM1_IRQHandler_v [WEAK]
+                EXPORT   PWM2_IRQHandler_v [WEAK]
+                EXPORT   SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK]
+                EXPORT   RTC2_IRQHandler_v [WEAK]
+                EXPORT   I2S_IRQHandler_v [WEAK]
+                EXPORT   FPU_IRQHandler_v [WEAK]
 POWER_CLOCK_IRQHandler
 RADIO_IRQHandler
-UARTE0_UART0_IRQHandler
-SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
-SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
-NFCT_IRQHandler
-GPIOTE_IRQHandler
-SAADC_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
+UARTE0_UART0_IRQHandler_v
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+NFCT_IRQHandler_v
+GPIOTE_IRQHandler_v
+SAADC_IRQHandler_v
+TIMER0_IRQHandler_v
+TIMER1_IRQHandler_v
+TIMER2_IRQHandler_v
 RTC0_IRQHandler
-TEMP_IRQHandler
+TEMP_IRQHandler_v
 RNG_IRQHandler
 ECB_IRQHandler
 CCM_AAR_IRQHandler
-WDT_IRQHandler
-RTC1_IRQHandler
-QDEC_IRQHandler
-COMP_LPCOMP_IRQHandler
-SWI0_EGU0_IRQHandler
-SWI1_EGU1_IRQHandler
-SWI2_EGU2_IRQHandler
-SWI3_EGU3_IRQHandler
+WDT_IRQHandler_v
+RTC1_IRQHandler_v
+QDEC_IRQHandler_v
+COMP_LPCOMP_IRQHandler_v
+SWI0_EGU0_IRQHandler_v
+SWI1_EGU1_IRQHandler_v
+SWI2_EGU2_IRQHandler_v
+SWI3_EGU3_IRQHandler_v
 SWI4_EGU4_IRQHandler
 SWI5_EGU5_IRQHandler
-TIMER3_IRQHandler
-TIMER4_IRQHandler
-PWM0_IRQHandler
-PDM_IRQHandler
+TIMER3_IRQHandler_v
+TIMER4_IRQHandler_v
+PWM0_IRQHandler_v
+PDM_IRQHandler_v
 MWU_IRQHandler
-PWM1_IRQHandler
-PWM2_IRQHandler
-SPIM2_SPIS2_SPI2_IRQHandler
-RTC2_IRQHandler
-I2S_IRQHandler
-FPU_IRQHandler
+PWM1_IRQHandler_v
+PWM2_IRQHandler_v
+SPIM2_SPIS2_SPI2_IRQHandler_v
+RTC2_IRQHandler_v
+I2S_IRQHandler_v
+FPU_IRQHandler_v
                 B .
                 ENDP
                 ALIGN
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld
index 6e17dd45c9c..d049cd88182 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/NRF52832.ld
@@ -140,6 +140,13 @@ SECTIONS
 
     __edata = .;
 
+    .noinit :
+    {
+      PROVIDE(__start_noinit = .);
+      KEEP(*(.noinit))
+      PROVIDE(__stop_noinit = .);
+    } > RAM
+    
     .bss :
     {
         . = ALIGN(4);
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S
index 0d02b962e89..1c6631e7ddf 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S
@@ -69,244 +69,44 @@ __Vectors:
   /* External Interrupts */
     .long   POWER_CLOCK_IRQHandler
     .long   RADIO_IRQHandler
-    .long   UARTE0_UART0_IRQHandler
-    .long   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
-    .long   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
-    .long   NFCT_IRQHandler
-    .long   GPIOTE_IRQHandler
-    .long   SAADC_IRQHandler
-    .long   TIMER0_IRQHandler
-    .long   TIMER1_IRQHandler
-    .long   TIMER2_IRQHandler
+    .long   UARTE0_UART0_IRQHandler_v
+    .long   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+    .long   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+    .long   NFCT_IRQHandler_v
+    .long   GPIOTE_IRQHandler_v
+    .long   SAADC_IRQHandler_v
+    .long   TIMER0_IRQHandler_v
+    .long   TIMER1_IRQHandler_v
+    .long   TIMER2_IRQHandler_v
     .long   RTC0_IRQHandler
-    .long   TEMP_IRQHandler
+    .long   TEMP_IRQHandler_v
     .long   RNG_IRQHandler
     .long   ECB_IRQHandler
     .long   CCM_AAR_IRQHandler
-    .long   WDT_IRQHandler
-    .long   RTC1_IRQHandler
-    .long   QDEC_IRQHandler
-    .long   COMP_LPCOMP_IRQHandler
-    .long   SWI0_EGU0_IRQHandler
-    .long   SWI1_EGU1_IRQHandler
-    .long   SWI2_EGU2_IRQHandler
-    .long   SWI3_EGU3_IRQHandler
+    .long   WDT_IRQHandler_v
+    .long   RTC1_IRQHandler_v
+    .long   QDEC_IRQHandler_v
+    .long   COMP_LPCOMP_IRQHandler_v
+    .long   SWI0_EGU0_IRQHandler_v
+    .long   SWI1_EGU1_IRQHandler_v
+    .long   SWI2_EGU2_IRQHandler_v
+    .long   SWI3_EGU3_IRQHandler_v
     .long   SWI4_EGU4_IRQHandler
     .long   SWI5_EGU5_IRQHandler
-    .long   TIMER3_IRQHandler
-    .long   TIMER4_IRQHandler
-    .long   PWM0_IRQHandler
-    .long   PDM_IRQHandler
+    .long   TIMER3_IRQHandler_v
+    .long   TIMER4_IRQHandler_v
+    .long   PWM0_IRQHandler_v
+    .long   PDM_IRQHandler_v
     .long   0                           /*Reserved */
     .long   0                           /*Reserved */
     .long   MWU_IRQHandler
-    .long   PWM1_IRQHandler
-    .long   PWM2_IRQHandler
-    .long   SPIM2_SPIS2_SPI2_IRQHandler
-    .long   RTC2_IRQHandler
-    .long   I2S_IRQHandler
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
-    .long   0                           /*Reserved */
+    .long   PWM1_IRQHandler_v
+    .long   PWM2_IRQHandler_v
+    .long   SPIM2_SPIS2_SPI2_IRQHandler_v
+    .long   RTC2_IRQHandler_v
+    .long   I2S_IRQHandler_v
+    .long   FPU_IRQHandler_v
+
 
     .size    __Vectors, . - __Vectors
 
@@ -345,6 +145,8 @@ Reset_Handler:
 
     LDR     R0, =SystemInit
     BLX     R0
+    LDR     R0, =nrf_reloc_vector_table
+    BLX     R0
     LDR     R0, =_start
     BX      R0
 
@@ -427,41 +229,42 @@ Default_Handler:
     .set    \handler, Default_Handler
     .endm
 
-    IRQ  POWER_CLOCK_IRQHandler
-    IRQ  RADIO_IRQHandler
-    IRQ  UARTE0_UART0_IRQHandler
-    IRQ  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
-    IRQ  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
-    IRQ  NFCT_IRQHandler
-    IRQ  GPIOTE_IRQHandler
-    IRQ  SAADC_IRQHandler
-    IRQ  TIMER0_IRQHandler
-    IRQ  TIMER1_IRQHandler
-    IRQ  TIMER2_IRQHandler
-    IRQ  RTC0_IRQHandler
-    IRQ  TEMP_IRQHandler
-    IRQ  RNG_IRQHandler
-    IRQ  ECB_IRQHandler
-    IRQ  CCM_AAR_IRQHandler
-    IRQ  WDT_IRQHandler
-    IRQ  RTC1_IRQHandler
-    IRQ  QDEC_IRQHandler
-    IRQ  COMP_LPCOMP_IRQHandler
-    IRQ  SWI0_EGU0_IRQHandler
-    IRQ  SWI1_EGU1_IRQHandler
-    IRQ  SWI2_EGU2_IRQHandler
-    IRQ  SWI3_EGU3_IRQHandler
-    IRQ  SWI4_EGU4_IRQHandler
-    IRQ  SWI5_EGU5_IRQHandler
-    IRQ  TIMER3_IRQHandler
-    IRQ  TIMER4_IRQHandler
-    IRQ  PWM0_IRQHandler
-    IRQ  PDM_IRQHandler
-    IRQ  MWU_IRQHandler
-    IRQ  PWM1_IRQHandler
-    IRQ  PWM2_IRQHandler
-    IRQ  SPIM2_SPIS2_SPI2_IRQHandler
-    IRQ  RTC2_IRQHandler
-    IRQ  I2S_IRQHandler
-
+    IRQ  POWER_CLOCK_IRQHandler                          /* restricted */
+    IRQ  RADIO_IRQHandler                                /* blocked    */
+    IRQ  UARTE0_UART0_IRQHandler_v
+    IRQ  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+    IRQ  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+    IRQ  NFCT_IRQHandler_v
+    IRQ  GPIOTE_IRQHandler_v
+    IRQ  SAADC_IRQHandler_v
+    IRQ  TIMER0_IRQHandler_v
+    IRQ  TIMER1_IRQHandler_v
+    IRQ  TIMER2_IRQHandler_v
+    IRQ  RTC0_IRQHandler                                 /* blocked    */
+    IRQ  TEMP_IRQHandler_v
+    IRQ  RNG_IRQHandler                                  /* restricted */
+    IRQ  ECB_IRQHandler                                  /* restricted */
+    IRQ  CCM_AAR_IRQHandler                              /* blocked    */
+    IRQ  WDT_IRQHandler_v
+    IRQ  RTC1_IRQHandler_v
+    IRQ  QDEC_IRQHandler_v
+    IRQ  COMP_LPCOMP_IRQHandler_v
+    IRQ  SWI0_EGU0_IRQHandler_v
+    IRQ  SWI1_EGU1_IRQHandler_v                          /* restricted for Radio Notification */
+    IRQ  SWI2_EGU2_IRQHandler_v                          /* blocked for SoftDevice Event */
+    IRQ  SWI3_EGU3_IRQHandler_v
+    IRQ  SWI4_EGU4_IRQHandler                            /* blocked    */
+    IRQ  SWI5_EGU5_IRQHandler                            /* blocked    */
+    IRQ  TIMER3_IRQHandler_v
+    IRQ  TIMER4_IRQHandler_v
+    IRQ  PWM0_IRQHandler_v
+    IRQ  PDM_IRQHandler_v
+    IRQ  MWU_IRQHandler                                  /* restricted */
+    IRQ  PWM1_IRQHandler_v
+    IRQ  PWM2_IRQHandler_v
+    IRQ  SPIM2_SPIS2_SPI2_IRQHandler_v
+    IRQ  RTC2_IRQHandler_v
+    IRQ  I2S_IRQHandler_v
+    IRQ  FPU_IRQHandler_v
+    
   .end
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s
index 823565d9753..b27d189e7d6 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s
@@ -52,6 +52,7 @@
 
         EXTERN  __iar_program_start
         EXTERN  SystemInit
+        EXTERN  nrf_reloc_vector_table
         PUBLIC  __vector_table
         PUBLIC  __Vectors
         PUBLIC  __Vectors_End
@@ -80,244 +81,44 @@ __vector_table
         ; External Interrupts
         DCD     POWER_CLOCK_IRQHandler
         DCD     RADIO_IRQHandler
-        DCD     UARTE0_UART0_IRQHandler
-        DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
-        DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
-        DCD     NFCT_IRQHandler
-        DCD     GPIOTE_IRQHandler
-        DCD     SAADC_IRQHandler
-        DCD     TIMER0_IRQHandler
-        DCD     TIMER1_IRQHandler
-        DCD     TIMER2_IRQHandler
+        DCD     UARTE0_UART0_IRQHandler_v
+        DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+        DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+        DCD     NFCT_IRQHandler_v
+        DCD     GPIOTE_IRQHandler_v
+        DCD     SAADC_IRQHandler_v
+        DCD     TIMER0_IRQHandler_v
+        DCD     TIMER1_IRQHandler_v
+        DCD     TIMER2_IRQHandler_v
         DCD     RTC0_IRQHandler
-        DCD     TEMP_IRQHandler
+        DCD     TEMP_IRQHandler_v
         DCD     RNG_IRQHandler
         DCD     ECB_IRQHandler
         DCD     CCM_AAR_IRQHandler
-        DCD     WDT_IRQHandler
-        DCD     RTC1_IRQHandler
-        DCD     QDEC_IRQHandler
-        DCD     COMP_LPCOMP_IRQHandler
-        DCD     SWI0_EGU0_IRQHandler
-        DCD     SWI1_EGU1_IRQHandler
-        DCD     SWI2_EGU2_IRQHandler
-        DCD     SWI3_EGU3_IRQHandler
+        DCD     WDT_IRQHandler_v
+        DCD     RTC1_IRQHandler_v
+        DCD     QDEC_IRQHandler_v
+        DCD     COMP_LPCOMP_IRQHandler_v
+        DCD     SWI0_EGU0_IRQHandler_v
+        DCD     SWI1_EGU1_IRQHandler_v
+        DCD     SWI2_EGU2_IRQHandler_v
+        DCD     SWI3_EGU3_IRQHandler_v
         DCD     SWI4_EGU4_IRQHandler
         DCD     SWI5_EGU5_IRQHandler
-        DCD     TIMER3_IRQHandler
-        DCD     TIMER4_IRQHandler
-        DCD     PWM0_IRQHandler
-        DCD     PDM_IRQHandler
+        DCD     TIMER3_IRQHandler_v
+        DCD     TIMER4_IRQHandler_v
+        DCD     PWM0_IRQHandler_v
+        DCD     PDM_IRQHandler_v
         DCD     0                         ; Reserved
         DCD     0                         ; Reserved
         DCD     MWU_IRQHandler
-        DCD     PWM1_IRQHandler
-        DCD     PWM2_IRQHandler
-        DCD     SPIM2_SPIS2_SPI2_IRQHandler
-        DCD     RTC2_IRQHandler
-        DCD     I2S_IRQHandler
-        DCD     FPU_IRQHandler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
+        DCD     PWM1_IRQHandler_v
+        DCD     PWM2_IRQHandler_v
+        DCD     SPIM2_SPIS2_SPI2_IRQHandler_v
+        DCD     RTC2_IRQHandler_v
+        DCD     I2S_IRQHandler_v
+        DCD     FPU_IRQHandler_v
+
 
 __Vectors_End
 __Vectors                           EQU   __vector_table
@@ -333,6 +134,8 @@ Reset_Handler
 
         LDR     R0, =SystemInit
         BLX     R0
+        LDR     R0, =nrf_reloc_vector_table
+        BLX     R0
         LDR     R0, =__iar_program_start
         BX      R0
 
@@ -397,49 +200,49 @@ POWER_CLOCK_IRQHandler
 RADIO_IRQHandler
         B .
 
-        PUBWEAK  UARTE0_UART0_IRQHandler
+        PUBWEAK  UARTE0_UART0_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-UARTE0_UART0_IRQHandler
+UARTE0_UART0_IRQHandler_v
         B .
 
-        PUBWEAK  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+        PUBWEAK  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
         B .
 
-        PUBWEAK  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+        PUBWEAK  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
         B .
 
-        PUBWEAK  NFCT_IRQHandler
+        PUBWEAK  NFCT_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-NFCT_IRQHandler
+NFCT_IRQHandler_v
         B .
 
-        PUBWEAK  GPIOTE_IRQHandler
+        PUBWEAK  GPIOTE_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-GPIOTE_IRQHandler
+GPIOTE_IRQHandler_v
         B .
 
-        PUBWEAK  SAADC_IRQHandler
+        PUBWEAK  SAADC_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SAADC_IRQHandler
+SAADC_IRQHandler_v
         B .
 
-        PUBWEAK  TIMER0_IRQHandler
+        PUBWEAK  TIMER0_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-TIMER0_IRQHandler
+TIMER0_IRQHandler_v
         B .
 
-        PUBWEAK  TIMER1_IRQHandler
+        PUBWEAK  TIMER1_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-TIMER1_IRQHandler
+TIMER1_IRQHandler_v
         B .
 
-        PUBWEAK  TIMER2_IRQHandler
+        PUBWEAK  TIMER2_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-TIMER2_IRQHandler
+TIMER2_IRQHandler_v
         B .
 
         PUBWEAK  RTC0_IRQHandler
@@ -447,9 +250,9 @@ TIMER2_IRQHandler
 RTC0_IRQHandler
         B .
 
-        PUBWEAK  TEMP_IRQHandler
+        PUBWEAK  TEMP_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-TEMP_IRQHandler
+TEMP_IRQHandler_v
         B .
 
         PUBWEAK  RNG_IRQHandler
@@ -467,44 +270,44 @@ ECB_IRQHandler
 CCM_AAR_IRQHandler
         B .
 
-        PUBWEAK  WDT_IRQHandler
+        PUBWEAK  WDT_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-WDT_IRQHandler
+WDT_IRQHandler_v
         B .
 
-        PUBWEAK  RTC1_IRQHandler
+        PUBWEAK  RTC1_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-RTC1_IRQHandler
+RTC1_IRQHandler_v
         B .
 
-        PUBWEAK  QDEC_IRQHandler
+        PUBWEAK  QDEC_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-QDEC_IRQHandler
+QDEC_IRQHandler_v
         B .
 
-        PUBWEAK  COMP_LPCOMP_IRQHandler
+        PUBWEAK  COMP_LPCOMP_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-COMP_LPCOMP_IRQHandler
+COMP_LPCOMP_IRQHandler_v
         B .
 
-        PUBWEAK  SWI0_EGU0_IRQHandler
+        PUBWEAK  SWI0_EGU0_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SWI0_EGU0_IRQHandler
+SWI0_EGU0_IRQHandler_v
         B .
 
-        PUBWEAK  SWI1_EGU1_IRQHandler
+        PUBWEAK  SWI1_EGU1_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SWI1_EGU1_IRQHandler
+SWI1_EGU1_IRQHandler_v
         B .
 
-        PUBWEAK  SWI2_EGU2_IRQHandler
+        PUBWEAK  SWI2_EGU2_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SWI2_EGU2_IRQHandler
+SWI2_EGU2_IRQHandler_v
         B .
 
-        PUBWEAK  SWI3_EGU3_IRQHandler
+        PUBWEAK  SWI3_EGU3_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SWI3_EGU3_IRQHandler
+SWI3_EGU3_IRQHandler_v
         B .
 
         PUBWEAK  SWI4_EGU4_IRQHandler
@@ -517,24 +320,24 @@ SWI4_EGU4_IRQHandler
 SWI5_EGU5_IRQHandler
         B .
 
-        PUBWEAK  TIMER3_IRQHandler
+        PUBWEAK  TIMER3_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-TIMER3_IRQHandler
+TIMER3_IRQHandler_v
         B .
 
-        PUBWEAK  TIMER4_IRQHandler
+        PUBWEAK  TIMER4_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-TIMER4_IRQHandler
+TIMER4_IRQHandler_v
         B .
 
-        PUBWEAK  PWM0_IRQHandler
+        PUBWEAK  PWM0_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-PWM0_IRQHandler
+PWM0_IRQHandler_v
         B .
 
-        PUBWEAK  PDM_IRQHandler
+        PUBWEAK  PDM_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-PDM_IRQHandler
+PDM_IRQHandler_v
         B .
 
         PUBWEAK  MWU_IRQHandler
@@ -542,34 +345,34 @@ PDM_IRQHandler
 MWU_IRQHandler
         B .
 
-        PUBWEAK  PWM1_IRQHandler
+        PUBWEAK  PWM1_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-PWM1_IRQHandler
+PWM1_IRQHandler_v
         B .
 
-        PUBWEAK  PWM2_IRQHandler
+        PUBWEAK  PWM2_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-PWM2_IRQHandler
+PWM2_IRQHandler_v
         B .
 
-        PUBWEAK  SPIM2_SPIS2_SPI2_IRQHandler
+        PUBWEAK  SPIM2_SPIS2_SPI2_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-SPIM2_SPIS2_SPI2_IRQHandler
+SPIM2_SPIS2_SPI2_IRQHandler_v
         B .
 
-        PUBWEAK  RTC2_IRQHandler
+        PUBWEAK  RTC2_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-RTC2_IRQHandler
+RTC2_IRQHandler_v
         B .
 
-        PUBWEAK  I2S_IRQHandler
+        PUBWEAK  I2S_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-I2S_IRQHandler
+I2S_IRQHandler_v
         B .
 
-        PUBWEAK  FPU_IRQHandler
+        PUBWEAK  FPU_IRQHandler_v
         SECTION .text:CODE:NOROOT(1)
-FPU_IRQHandler
+FPU_IRQHandler_v
         B .
 
 
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/cmsis_nvic.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/cmsis_nvic.c
index 02f85b1d798..2efb6da48c6 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/cmsis_nvic.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/cmsis_nvic.c
@@ -30,28 +30,14 @@
  */
 #include "cmsis_nvic.h"
 
-#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Vectors positioned at start of SRAM2
-#define NVIC_FLASH_VECTOR_ADDRESS (0x0)  // Initial vector position in flash
+extern uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
 
 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
-    uint32_t *vectors = (uint32_t *) SCB->VTOR;
-    uint32_t i;
-
-    /* Copy and switch to dynamic vectors if the first time called */
-    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
-        vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
-        for (i = 0; i < NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+    nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
 }
 
 uint32_t NVIC_GetVector(IRQn_Type IRQn)
 {
-    uint32_t *vectors = (uint32_t *) SCB->VTOR;
-    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+    return nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET];
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c
index 43cb0cad2dd..095b5dd9435 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c
@@ -107,6 +107,27 @@ typedef struct
     
 static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initialization);
     
+// extern PWM nIRQ handler implementations
+void PWM0_IRQHandler(void);
+void PWM1_IRQHandler(void);
+void PWM2_IRQHandler(void);
+
+static const peripheral_handler_desc_t pwm_handlers[PWM_INSTANCE_COUNT] =
+{
+    {
+        PWM0_IRQn,
+        (uint32_t)PWM0_IRQHandler
+    },
+    {
+        PWM1_IRQn,
+        (uint32_t)PWM1_IRQHandler
+    },
+    {
+        PWM2_IRQn,
+        (uint32_t)PWM2_IRQHandler
+    }
+};
+ 
 void pwmout_init(pwmout_t *obj, PinName pin)
 {
     uint32_t i;
@@ -115,6 +136,8 @@ void pwmout_init(pwmout_t *obj, PinName pin)
     {
         if (m_pwm[i].p_pwm_driver == NULL) // a driver instance not assigned to the obj?
         {
+            NVIC_SetVector(pwm_handlers[i].IRQn, pwm_handlers[i].vector);
+            
             obj->pin         = pin;
             
             obj->pwm_channel = i;
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
index 4c1586c0c31..e8f0952e7ee 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
@@ -58,6 +58,7 @@ static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t a
     }
 }
 
+void GPIOTE_IRQHandler(void);// exported from nrf_drv_gpiote.c
 
 void gpio_init(gpio_t *obj, PinName pin)
 {
@@ -66,6 +67,9 @@ void gpio_init(gpio_t *obj, PinName pin)
         return;
     }
     MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT);
+    
+    NVIC_SetVector(GPIOTE_IRQn, (uint32_t) GPIOTE_IRQHandler);
+    
     (void) nrf_drv_gpiote_init();
 
     m_gpio_cfg[obj->pin].used_as_gpio = true;
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
index c7221533d7e..0c6d28ca33b 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
@@ -107,6 +107,25 @@ static uint8_t twi_address(int i2c_address)
     return (i2c_address >> 1);
 }
 
+void SPI0_TWI0_IRQHandler(void);
+void SPI1_TWI1_IRQHandler(void);
+
+static const peripheral_handler_desc_t twi_handlers[TWI_COUNT] =
+{
+    #if TWI0_ENABLED
+    {
+        SPI0_TWI0_IRQn,
+        (uint32_t) SPI0_TWI0_IRQHandler
+    },
+    #endif
+    #if TWI1_ENABLED
+    {
+        SPI1_TWI1_IRQn,
+        (uint32_t) SPI1_TWI1_IRQHandler
+    }
+    #endif 
+};
+
 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
 {
     int i;
@@ -130,6 +149,9 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
 
     for (i = 0; i < TWI_COUNT; ++i) {
         if (!m_twi_info[i].initialized) {
+
+            NVIC_SetVector(twi_handlers[i].IRQn, twi_handlers[i].vector);
+
             nrf_drv_twi_t const *twi = &m_twi_instances[i];
             ret_code_t ret_code =
                 nrf_drv_twi_init(twi, &config, twi_event_handler, obj);
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/irq_handlers_hw.h b/targets/TARGET_NORDIC/TARGET_NRF5/irq_handlers_hw.h
new file mode 100644
index 00000000000..7eba37ad998
--- /dev/null
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/irq_handlers_hw.h
@@ -0,0 +1,55 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file irq_handlers_hw.h
+ * @brief Heleper file for wiring irq handlers to theirs vectors.
+ */
+ 
+#ifndef IRQ_HANDLERS_HW_H__
+#define IRQ_HANDLERS_HW_H__
+
+
+typedef struct
+{
+    IRQn_Type      IRQn;
+    uint32_t       vector;
+} peripheral_handler_desc_t;
+
+#endif // IRQ_HANDLERS_HW_H__
+
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c b/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c
new file mode 100644
index 00000000000..2862e6c4177
--- /dev/null
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c
@@ -0,0 +1,76 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#include "nrf.h"
+#include "cmsis_nvic.h"
+#include "stdint.h"
+#include "nrf_sdm.h"
+#include "section_vars.h"
+
+#if defined(__CC_ARM)
+    __attribute__ ((section("noinit"),zero_init))
+    uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
+#elif defined(__GNUC__)
+    __attribute__ ((section(".noinit")))
+    uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
+#elif defined(__ICCARM__)
+    uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS] @ ".noinit";
+#endif
+
+
+typedef void (*generic_irq_handler_t)(void);
+
+
+extern uint32_t __Vectors[];
+#define VECTORS_FLASH_START __Vectors
+
+/**
+ * @brief Function for relocation of the vector to RAM on nRF5x devices.
+ * This function is intended to be called during startup.
+ */
+void nrf_reloc_vector_table(void)
+{
+    // Copy and switch to dynamic vectors
+	uint32_t *old_vectors = (uint32_t*)VECTORS_FLASH_START;
+	uint32_t i;
+	for (i = 0; i< NVIC_NUM_VECTORS; i++) {
+		nrf_dispatch_vector[i] = old_vectors[i];
+	}
+
+	sd_softdevice_vector_table_base_set((uint32_t) nrf_dispatch_vector);
+}
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h b/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h
index 94df5c648b1..22948d7b1e6 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h
@@ -68,6 +68,7 @@
     #endif /* NRF51, NRF52 */
 
     #include "compiler_abstraction.h"
+    #include "irq_handlers_hw.h"
 
 #endif /* _WIN32 || __unix || __APPLE__ */
 
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c
index 8b84f5fbfb2..d94e9aecfbe 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c
@@ -246,6 +246,10 @@ void UART_IRQ_HANDLER(void)
 }
 
 void serial_init(serial_t *obj, PinName tx, PinName rx) {
+
+    NVIC_SetVector(UART0_IRQn, (uint32_t) UART0_IRQHandler);
+
+    
     UART_CB.pseltxd =
         (tx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)tx;
     UART_CB.pselrxd =
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c
index 00be9180877..bd8aea839e2 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c
@@ -85,25 +85,52 @@ typedef struct {
     nrf_drv_spi_t  master;
     nrf_drv_spis_t slave;
 } sdk_driver_instances_t;
+
+void SPI0_TWI0_IRQHandler(void);
+void SPI1_TWI1_IRQHandler(void);
+void SPIM2_SPIS2_SPI2_IRQHandler(void);
+
+static const peripheral_handler_desc_t spi_hanlder_desc[SPI_COUNT] = {
+#if SPI0_ENABLED
+    {
+        SPIS0_IRQ,
+        (uint32_t) SPI0_TWI0_IRQHandler
+    },
+#endif
+#if SPI1_ENABLED
+    {
+        SPIS1_IRQ,
+        (uint32_t) SPI1_TWI1_IRQHandler
+    },
+#endif
+#if SPI2_ENABLED
+    {
+        SPIS2_IRQ,
+        (uint32_t) SPIM2_SPIS2_SPI2_IRQHandler
+    },
+#endif    
+};
+
+
 static sdk_driver_instances_t m_instances[SPI_COUNT] = {
-    #if SPI0_ENABLED
+#if SPI0_ENABLED
     {
         NRF_DRV_SPI_INSTANCE(0),
         NRF_DRV_SPIS_INSTANCE(0)
     },
-    #endif
-    #if SPI1_ENABLED
+#endif
+#if SPI1_ENABLED
     {
         NRF_DRV_SPI_INSTANCE(1),
         NRF_DRV_SPIS_INSTANCE(1)
     },
-    #endif
-    #if SPI2_ENABLED
+#endif
+#if SPI2_ENABLED
     {
         NRF_DRV_SPI_INSTANCE(2),
         NRF_DRV_SPIS_INSTANCE(2)
     },
-    #endif
+#endif
 };
 
 static void master_event_handler(uint8_t spi_idx,
@@ -230,6 +257,9 @@ void spi_init(spi_t *obj,
     for (i = 0; i < SPI_COUNT; ++i) {
         spi_info_t *p_spi_info = &m_spi_info[i];
         if (!p_spi_info->initialized) {
+         
+            NVIC_SetVector(spi_hanlder_desc[i].IRQn, spi_hanlder_desc[i].vector);
+            
             p_spi_info->sck_pin   = (uint8_t)sclk;
             p_spi_info->mosi_pin  = (mosi != NC) ?
                 (uint8_t)mosi : NRF_DRV_SPI_PIN_NOT_USED;
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c b/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c
index 35045fdb3f5..e1c028e3ab4 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c
@@ -76,12 +76,19 @@ void COMMON_RTC_IRQ_HANDLER(void)
     }
 }
 
+#if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR
+__stackless __task 
+#endif
+void RTC1_IRQHandler(void);
+
 void common_rtc_init(void)
 {
     if (m_common_rtc_enabled) {
         return;
     }
 
+    NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler);
+    
     // RTC is driven by the low frequency (32.768 kHz) clock, a proper request
     // must be made to have it running.
     // Currently this clock is started in 'SystemInit' (see "system_nrf51.c"