diff --git a/features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM32F769NI.h b/features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM32F769NI.h
new file mode 100644
index 00000000000..4ef5c58c006
--- /dev/null
+++ b/features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM32F769NI.h
@@ -0,0 +1,147 @@
+/* Copyright (c) 2016 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+#ifndef USBHAL_STM32F769NI_H
+#define USBHAL_STM32F769NI_H
+#define USBHAL_IRQn OTG_HS_IRQn
+/* must be multiple of 4 bytes */
+#define NB_ENDPOINT 4
+#define MAXTRANSFER_SIZE 0x200
+#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
+#if (FIFO_USB_RAM_SIZE > 0x500)
+#error "FIFO dimensioning incorrect"
+#endif
+
+typedef struct
+{
+ USBHAL *inst;
+ void (USBHAL::*bus_reset)(void);
+ void (USBHAL::*sof)(int frame);
+ void (USBHAL::*connect_change)(unsigned int connected);
+ void (USBHAL::*suspend_change)(unsigned int suspended);
+ void (USBHAL::*ep0_setup)(void);
+ void (USBHAL::*ep0_in)(void);
+ void (USBHAL::*ep0_out)(void);
+ void (USBHAL::*ep0_read)(void);
+ bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
+ bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
+ /* memorize dummy buffer used for reception */
+ uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
+ uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
+ uint8_t epComplete[2*NB_ENDPOINT];
+}USBHAL_Private_t;
+
+uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
+{
+ uint32_t len;
+ if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
+ else
+ len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
+ return len*4;
+}
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
+ USBHAL *obj= priv->inst;
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
+ void (USBHAL::*func)(int frame) = priv->sof;
+ /* fix me call with same frame number */
+ (obj->*func)(sofnum);
+}
+
+
+USBHAL * USBHAL::instance;
+
+USBHAL::USBHAL(void) {
+ /* init parameter */
+ USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
+ hpcd.Instance = USB_OTG_HS;
+ memset(&hpcd.Init, 0, sizeof(hpcd.Init));
+ hpcd.Init.dev_endpoints = NB_ENDPOINT;
+ hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
+ hpcd.Init.phy_itface = PCD_PHY_ULPI;
+ hpcd.Init.Sof_enable = 0;
+
+ hpcd.Init.speed = PCD_SPEED_HIGH;
+ //hpcd.Init.vbus_sensing_enable = 0;
+ //hpcd.Init.lpm_enable = 0;
+ /* pass instance for usage inside call back */
+ HALPriv->inst = this;
+ HALPriv->bus_reset = &USBHAL::busReset;
+ HALPriv->suspend_change = &USBHAL::suspendStateChanged;
+ HALPriv->connect_change = &USBHAL::connectStateChanged;
+ HALPriv->sof = &USBHAL::SOF;
+ HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
+ HALPriv->ep_realise = &USBHAL::realiseEndpoint;
+ HALPriv->ep0_in = &USBHAL::EP0in;
+ HALPriv->ep0_out = &USBHAL::EP0out;
+ HALPriv->ep0_read = &USBHAL::EP0read;
+ hpcd.pData = (void*)HALPriv;
+ HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
+ HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
+ HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
+ HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
+ HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
+ HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
+ instance = this;
+ /* Enable power and clocking */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOI_CLK_ENABLE();
+
+ pin_function(PA_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // CLK
+ pin_function(PA_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D0
+
+ pin_function(PB_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D1
+ pin_function(PB_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D2
+ pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D3
+ pin_function(PB_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D4
+ pin_function(PB_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D5
+ pin_function(PB_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D6
+ pin_function(PB_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D7
+
+ pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // STP
+ pin_function(PH_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // NXT
+ pin_function(PI_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR
+
+ __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
+ __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ hpcd.State = HAL_PCD_STATE_RESET;
+ HAL_PCD_Init(&hpcd);
+ /* 1.25kbytes */
+ /* min value 16 (= 16 x 4 bytes) */
+ /* max value 256 (= 1K bytes ) */
+ /* maximum sum is 0x140 */
+ HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
+ /* bulk/int 64 bytes in FS */
+ HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
+ /* bulk/int bytes in FS */
+ HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4));
+ HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
+ /* ISOchronous */
+ HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
+ NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
+ NVIC_SetPriority(USBHAL_IRQn, 1);
+ HAL_PCD_Start(&hpcd);
+}
+#endif
+
diff --git a/features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM_TARGET.h b/features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM_TARGET.h
index 7a2af44d1fb..4c67d6b6941 100644
--- a/features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM_TARGET.h
+++ b/features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM_TARGET.h
@@ -26,3 +26,6 @@
#ifdef TARGET_STM32L476VG
#include "USBHAL_STM32L476VG.h"
#endif
+#ifdef TARGET_STM32F769NI
+#include "USBHAL_STM32F769NI.h"
+#endif
diff --git a/features/unsupported/tests/mbed/analog/main.cpp b/features/unsupported/tests/mbed/analog/main.cpp
index dc4eb2428ce..dab9466382e 100644
--- a/features/unsupported/tests/mbed/analog/main.cpp
+++ b/features/unsupported/tests/mbed/analog/main.cpp
@@ -57,6 +57,10 @@ AnalogOut out(A2);
AnalogIn in(A0);
AnalogOut out(A3);
+#elif defined(TARGET_DISCO_F769NI)
+AnalogIn in(A0);
+AnalogOut out(A1);
+
#elif defined(TARGET_NUCLEO_F207ZG) || \
defined(TARGET_NUCLEO_F746ZG) || \
defined(TARGET_NUCLEO_F303ZE) || \
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c
index 3c01e5235ba..5d0967e5eb2 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c
@@ -69,14 +69,15 @@ const PinMap PinMap_DAC[] = {
//*** I2C ***
const PinMap PinMap_I2C_SDA[] = {
- {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // used by Audio_SDA
+// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // used by Audio_SDA
+ {PB_7, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF11_I2C4)}, // used by Audio_SDA // CN1 pin 40
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SDA
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
- {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SCL
- {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // used by Audio_SCL
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D15/SCL
+ {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // used by Audio_SCL // CN1 pin 44
{NC, NC, 0}
};
@@ -118,7 +119,7 @@ const PinMap PinMap_PWM[] = {
const PinMap PinMap_UART_TX[] = {
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by stlink usb)
- // {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D13 - remove SB15 to use it
+ // {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D13 - remove SB15 to use it // LD3
{PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // ARDUINO D14
{PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D12
{PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D1
@@ -139,7 +140,7 @@ const PinMap PinMap_UART_RX[] = {
};
const PinMap PinMap_UART_RTS[] = {
- {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1 )}, // ARDUINO D13
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1 )}, // ARDUINO D13 // LD3
{PB_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4 )}, // ARDUINO D12
// {PB_14, USART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3 )}, // ARDUINO D12
{PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5 )}, // ARDUINO D5
@@ -178,7 +179,7 @@ const PinMap PinMap_SPI_MISO[] = {
};
const PinMap PinMap_SPI_SCLK[] = {
- {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D13
+ {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D13 // LD3
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card
// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
// {PB_3, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)},
@@ -201,13 +202,13 @@ const PinMap PinMap_SPI_SSEL[] = {
//*** CAN ***
const PinMap PinMap_CAN_RD[] = {
- {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D10
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D15
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
- {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D13 // LD3
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D14
{NC, NC, 0}
-};
\ No newline at end of file
+};
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h
index e875a51cdc1..bb905f274af 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h
@@ -43,9 +43,9 @@ typedef enum {
PortF = 5,
PortG = 6,
PortH = 7,
- PortI = 8, // kept for compilation
- PortJ = 9, // kept for compilation
- PortK = 10 // kept for compilation
+ PortI = 8,
+ PortJ = 9,
+ PortK = 10
} PortName;
#ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device.h
deleted file mode 100644
index bdad16c6f18..00000000000
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device.h
+++ /dev/null
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH 24
-
-
-
-
-#include "objects.h"
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.S
new file mode 100644
index 00000000000..1c591e6e56d
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.S
@@ -0,0 +1,500 @@
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name : startup_stm32f769xx.s
+;* Author : MCD Application Team
+;* Version : V1.1.0
+;* Date : 22-April-2016
+;* Description : STM32F769xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM7 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20080000 ; Top of RAM
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD DSI_IRQHandler ; DSI
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2
+ DCD CAN3_TX_IRQHandler ; CAN3 TX
+ DCD CAN3_RX0_IRQHandler ; CAN3 RX0
+ DCD CAN3_RX1_IRQHandler ; CAN3 RX1
+ DCD CAN3_SCE_IRQHandler ; CAN3 SCE
+ DCD JPEG_IRQHandler ; JPEG
+ DCD MDIOS_IRQHandler ; MDIOS
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX0_IRQHandler [WEAK]
+ EXPORT CAN2_RX1_IRQHandler [WEAK]
+ EXPORT CAN2_SCE_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DSI_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT CAN3_TX_IRQHandler [WEAK]
+ EXPORT CAN3_RX0_IRQHandler [WEAK]
+ EXPORT CAN3_RX1_IRQHandler [WEAK]
+ EXPORT CAN3_SCE_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM9_IRQHandler
+TIM1_UP_TIM10_IRQHandler
+TIM1_TRG_COM_TIM11_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DSI_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SDMMC2_IRQHandler
+CAN3_TX_IRQHandler
+CAN3_RX0_IRQHandler
+CAN3_RX1_IRQHandler
+CAN3_SCE_IRQHandler
+JPEG_IRQHandler
+MDIOS_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/stm32f769ni.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/stm32f769ni.sct
new file mode 100644
index 00000000000..1c2ba8fd8d6
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/stm32f769ni.sct
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2016, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F769NI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000)
+LR_IROM1 0x08000000 0x200000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.c
index 367ce072d45..9a7750ddb0d 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.c
@@ -83,9 +83,7 @@
HAL_StatusTypeDef HAL_Init(void);
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
+#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
@@ -132,7 +130,7 @@ HAL_StatusTypeDef HAL_Init(void);
*/
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
/**
@@ -736,6 +734,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
// Enable power clock
__PWR_CLK_ENABLE();
@@ -750,13 +749,14 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
}
- // Warning: this configuration is for a 8 MHz xtal clock only
+ // Warning: this configuration is for a 25 MHz xtal clock only
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
+ RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+ RCC_OscInitStruct.PLL.PLLR = 2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
@@ -768,7 +768,18 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
return 0; // FAIL
}
-
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
+ PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+ if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
@@ -801,7 +812,7 @@ uint8_t SetSysClock_PLL_HSI(void)
__PWR_CLK_ENABLE();
// Enable HSI oscillator and activate PLL with HSI as source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSICalibrationValue = 16;
@@ -811,7 +822,8 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
diff --git a/targets/targets.json b/targets/targets.json
index cdaac0342f9..d3bd36e1144 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -1217,13 +1217,14 @@
"inherits": ["Target"],
"core": "Cortex-M7FD",
"extra_labels": ["STM", "STM32F7", "STM32F769", "STM32F769NI"],
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"default_toolchain": "ARM",
+ "supported_form_factors": ["ARDUINO"],
"detect_code": ["0817"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
"features": ["LWIP"],
- "release_versions": ["2"],
+ "release_versions": ["2", "5"],
"device_name": "STM32F769NI"
},
"DISCO_L476VG": {
diff --git a/tools/tests.py b/tools/tests.py
index 829e8ae66ac..7e05d12062f 100644
--- a/tools/tests.py
+++ b/tools/tests.py
@@ -189,7 +189,7 @@
"NUCLEO_F334R8", "NUCLEO_F303ZE", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE",
"NUCLEO_F410RB", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F429ZI",
"DISCO_F407VG", "NUCLEO_F746ZG", "NUCLEO_L476RG",
- "DISCO_L053C8", "DISCO_F334C8", "DISCO_L476VG", "DISCO_F469NI", "DISCO_F429ZI",
+ "DISCO_L053C8", "DISCO_F334C8", "DISCO_L476VG", "DISCO_F469NI", "DISCO_F429ZI", "DISCO_F769NI",
"ARCH_MAX", "MAX32600MBED", "MOTE_L152RC", "B96B_F446VE"]
},
{