From bc948ca672e2f96c53bc108508916d4963133308 Mon Sep 17 00:00:00 2001 From: Archcady Date: Thu, 16 Feb 2017 11:47:09 +0800 Subject: [PATCH 01/69] Create mbed_rtx.h --- targets/TARGET_Realtek/mbed_rtx.h | 57 +++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 targets/TARGET_Realtek/mbed_rtx.h diff --git a/targets/TARGET_Realtek/mbed_rtx.h b/targets/TARGET_Realtek/mbed_rtx.h new file mode 100644 index 00000000000..ad486168c18 --- /dev/null +++ b/targets/TARGET_Realtek/mbed_rtx.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_RTL8195A) + +#include "rtl8195a.h" + +#if defined(__CC_ARM) +#ifdef CONFIG_RTL8195A + #define INITIAL_SP 0x10070000 + #define ISR_STACK_START 0x1FFFEFFC +#else + #ERROR "NOT SUPPORT NOW" +#endif +#elif defined(__GNUC__) + extern uint32_t __StackTop[]; + extern uint32_t __StackLimit[]; + extern uint32_t __end__[]; + extern uint32_t __HeapLimit[]; + #define INITIAL_SP (__StackTop) +#endif + + +#if defined(__CC_ARM) || defined(__GNUC__) +#ifndef ISR_STACK_SIZE +#define ISR_STACK_SIZE (0x1000) +#endif +#endif + +#ifndef OS_TASKCNT +#define OS_TASKCNT 14 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 256 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK PLATFORM_CLK +#endif + +#endif +#endif + From bbbecd70907c8a87de59d697a0e8aa85a2076371 Mon Sep 17 00:00:00 2001 From: Archcady Date: Thu, 16 Feb 2017 11:48:04 +0800 Subject: [PATCH 02/69] Update targets.json --- targets/targets.json | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index d01649c9e9c..ced5c96269f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2903,5 +2903,23 @@ "SARA_NBIOT_EVK": { "inherits": ["SARA_NBIOT"], "extra_labels": ["ublox", "HI2110", "SARA_NBIOT"] + }, + "REALTEK_RTL8195AM": { + "core": "Cortex-M3", + "default_toolchain": "GCC_ARM", + "inherits": ["Target"], + "extra_labels": ["Realtek", "AMEBA", "RTL8195A"], + "macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS"], + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "progen": {"target": "rtl8195a"}, + "progen_target": "rtl8195a", + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "TRNG", "EMAC"], + "default_build": "standard", + "features": ["IPV4", "LWIP"], + "post_binary_hook": { + "function": "RTL8195ACode.binary_hook", + "toolchains": ["ARM_STD", "GCC_ARM", "IAR"] + }, + "release_versions": ["5"] } } From 53e837bce2a92931d60703d50a5718744ae21424 Mon Sep 17 00:00:00 2001 From: Yuguo Zou Date: Thu, 16 Feb 2017 17:37:24 +0800 Subject: [PATCH 03/69] add support for REALTEK_RTL8195AM --- .../TARGET_RTL8195A/PeripheralNames.h | 108 + .../TARGET_AMEBA/TARGET_RTL8195A/PinNames.h | 229 ++ .../TARGET_AMEBA/TARGET_RTL8195A/PortNames.h | 38 + .../TARGET_AMEBA/TARGET_RTL8195A/device.h | 49 + .../device/TOOLCHAIN_ARM_STD/rtl8195a.sct | 48 + .../device/TOOLCHAIN_ARM_STD/sys.cpp | 63 + .../rlx8195A-symbol-v02-img2.ld | 864 +++++++ .../device/TOOLCHAIN_IAR/rom.a | Bin 0 -> 383620 bytes .../device/TOOLCHAIN_IAR/rtl8195a.icf | 191 ++ .../TARGET_RTL8195A/device/cmsis.h | 38 + .../TARGET_RTL8195A/device/cmsis_nvic.h | 54 + .../TARGET_RTL8195A/device/diag.h | 843 +++++++ .../TARGET_RTL8195A/device/hal_pinmux.h | 74 + .../TARGET_RTL8195A/device/hal_platform.h | 102 + .../device/platform_autoconf.h | 217 ++ .../TARGET_RTL8195A/device/rand.h | 15 + .../TARGET_RTL8195A/device/rtl8195a.h | 286 +++ .../TARGET_RTL8195A/device/rtl8195a_adc.h | 350 +++ .../TARGET_RTL8195A/device/rtl8195a_clk.h | 65 + .../device/rtl8195a_compiler.h | 58 + .../TARGET_RTL8195A/device/rtl8195a_dac.h | 294 +++ .../TARGET_RTL8195A/device/rtl8195a_gdma.h | 528 +++++ .../TARGET_RTL8195A/device/rtl8195a_gpio.h | 337 +++ .../TARGET_RTL8195A/device/rtl8195a_i2c.h | 862 +++++++ .../TARGET_RTL8195A/device/rtl8195a_init.c | 292 +++ .../TARGET_RTL8195A/device/rtl8195a_misc.h | 32 + .../TARGET_RTL8195A/device/rtl8195a_peri_on.h | 1251 ++++++++++ .../device/rtl8195a_platform.h | 1310 +++++++++++ .../TARGET_RTL8195A/device/rtl8195a_pwm.h | 61 + .../TARGET_RTL8195A/device/rtl8195a_rom.h | 748 ++++++ .../TARGET_RTL8195A/device/rtl8195a_sdio.h | 58 + .../device/rtl8195a_spi_flash.h | 1143 +++++++++ .../TARGET_RTL8195A/device/rtl8195a_ssi.h | 530 +++++ .../TARGET_RTL8195A/device/rtl8195a_sys_on.h | 1093 +++++++++ .../TARGET_RTL8195A/device/rtl8195a_timer.h | 257 ++ .../TARGET_RTL8195A/device/rtl8195a_trap.h | 172 ++ .../TARGET_RTL8195A/device/rtl8195a_uart.h | 656 ++++++ .../TARGET_RTL8195A/device/rtl8195a_wdt.h | 86 + .../TARGET_RTL8195A/device/rtl_utility.h | 70 + .../TARGET_RTL8195A/device/system_8195a.h | 77 + .../TARGET_RTL8195A/device/va_list.h | 36 + .../TARGET_AMEBA/TARGET_RTL8195A/objects.h | 209 ++ .../TARGET_AMEBA/analogin_api.c | 193 ++ .../TARGET_AMEBA/analogin_ext.h | 31 + .../TARGET_AMEBA/analogout_api.c | 182 ++ .../TARGET_Realtek/TARGET_AMEBA/flash_api.c | 582 +++++ .../TARGET_Realtek/TARGET_AMEBA/flash_api.h | 59 + .../TARGET_Realtek/TARGET_AMEBA/gpio_api.c | 198 ++ .../TARGET_AMEBA/gpio_irq_api.c | 146 ++ targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c | 752 ++++++ .../TARGET_AMEBA/lib_peripheral_mbed.a | Bin 0 -> 728204 bytes .../TARGET_AMEBA/lib_peripheral_mbed.ar | Bin 0 -> 291546 bytes .../TARGET_AMEBA/lib_wlan_mbed.a | Bin 0 -> 6427150 bytes .../TARGET_AMEBA/lib_wlan_mbed.ar | Bin 0 -> 938624 bytes .../TARGET_AMEBA/log_uart_api.c | 515 ++++ .../TARGET_AMEBA/log_uart_api.h | 67 + .../TARGET_Realtek/TARGET_AMEBA/port_api.c | 218 ++ .../TARGET_Realtek/TARGET_AMEBA/pwmout_api.c | 145 ++ targets/TARGET_Realtek/TARGET_AMEBA/rtc_api.c | 128 + .../sdk/common/api/platform/dlist.h | 262 +++ .../sdk/common/api/platform/platform_stdlib.h | 269 +++ .../sdk/common/api/wifi/wifi_conf.c | 1925 +++++++++++++++ .../sdk/common/api/wifi/wifi_conf.h | 841 +++++++ .../sdk/common/api/wifi/wifi_ind.c | 258 ++ .../sdk/common/api/wifi/wifi_ind.h | 80 + .../sdk/common/api/wifi/wifi_promisc.c | 465 ++++ .../sdk/common/api/wifi/wifi_util.c | 1334 +++++++++++ .../sdk/common/api/wifi/wifi_util.h | 75 + .../drivers/wlan/realtek/RTWInterface.cpp | 266 +++ .../drivers/wlan/realtek/RTWInterface.h | 164 ++ .../wlan/realtek/include/HalPwrSeqCmd.h | 136 ++ .../drivers/wlan/realtek/include/HalVerDef.h | 178 ++ .../drivers/wlan/realtek/include/autoconf.h | 513 ++++ .../wlan/realtek/include/byteorder/generic.h | 223 ++ .../realtek/include/byteorder/little_endian.h | 97 + .../wlan/realtek/include/byteorder/swab.h | 145 ++ .../drivers/wlan/realtek/include/drv_conf.h | 106 + .../drivers/wlan/realtek/include/drv_types.h | 863 +++++++ .../drivers/wlan/realtek/include/ethernet.h | 42 + .../drivers/wlan/realtek/include/hal_com.h | 287 +++ .../wlan/realtek/include/hal_com_phycfg.h | 288 +++ .../wlan/realtek/include/hal_com_reg.h | 2075 ++++++++++++++++ .../drivers/wlan/realtek/include/hal_intf.h | 666 ++++++ .../drivers/wlan/realtek/include/hal_pg.h | 81 + .../drivers/wlan/realtek/include/hal_phy.h | 99 + .../wlan/realtek/include/hal_phy_reg.h | 31 + .../drivers/wlan/realtek/include/ieee80211.h | 1527 ++++++++++++ .../drivers/wlan/realtek/include/if_ether.h | 115 + .../common/drivers/wlan/realtek/include/ip.h | 142 ++ .../drivers/wlan/realtek/include/lxbus_hal.h | 24 + .../drivers/wlan/realtek/include/lxbus_ops.h | 80 + .../wlan/realtek/include/lxbus_osintf.h | 29 + .../drivers/wlan/realtek/include/pack_begin.h | 18 + .../drivers/wlan/realtek/include/pack_end.h | 16 + .../drivers/wlan/realtek/include/rom_aes.h | 38 + .../drivers/wlan/realtek/include/rom_arc4.h | 24 + .../wlan/realtek/include/rom_ieee80211.h | 127 + .../drivers/wlan/realtek/include/rom_md5.h | 30 + .../drivers/wlan/realtek/include/rom_rc4.h | 89 + .../wlan/realtek/include/rom_rtw_message.h | 29 + .../wlan/realtek/include/rom_rtw_message_e.h | 155 ++ .../wlan/realtek/include/rom_rtw_psk.h | 29 + .../wlan/realtek/include/rom_rtw_security.h | 89 + .../drivers/wlan/realtek/include/rom_sha1.h | 52 + .../wlan/realtek/include/rtl8195a_hal.h | 618 +++++ .../wlan/realtek/include/rtl8711b_hal.h | 595 +++++ .../drivers/wlan/realtek/include/rtw_ap.h | 65 + .../wlan/realtek/include/rtw_byteorder.h | 53 + .../drivers/wlan/realtek/include/rtw_cmd.h | 1184 ++++++++++ .../drivers/wlan/realtek/include/rtw_debug.h | 456 ++++ .../drivers/wlan/realtek/include/rtw_eeprom.h | 158 ++ .../drivers/wlan/realtek/include/rtw_efuse.h | 163 ++ .../drivers/wlan/realtek/include/rtw_event.h | 151 ++ .../drivers/wlan/realtek/include/rtw_ht.h | 66 + .../drivers/wlan/realtek/include/rtw_intfs.h | 20 + .../drivers/wlan/realtek/include/rtw_io.h | 140 ++ .../wlan/realtek/include/rtw_ioctl_set.h | 75 + .../drivers/wlan/realtek/include/rtw_led.h | 250 ++ .../drivers/wlan/realtek/include/rtw_mlme.h | 795 +++++++ .../wlan/realtek/include/rtw_mlme_ext.h | 1014 ++++++++ .../drivers/wlan/realtek/include/rtw_mp.h | 722 ++++++ .../drivers/wlan/realtek/include/rtw_p2p.h | 39 + .../wlan/realtek/include/rtw_promisc.h | 38 + .../drivers/wlan/realtek/include/rtw_psk.h | 333 +++ .../wlan/realtek/include/rtw_pwrctrl.h | 386 +++ .../drivers/wlan/realtek/include/rtw_qos.h | 33 + .../drivers/wlan/realtek/include/rtw_recv.h | 918 ++++++++ .../drivers/wlan/realtek/include/rtw_rf.h | 175 ++ .../wlan/realtek/include/rtw_security.h | 446 ++++ .../drivers/wlan/realtek/include/rtw_xmit.h | 839 +++++++ .../drivers/wlan/realtek/include/sta_info.h | 400 ++++ .../drivers/wlan/realtek/include/wifi.h | 1369 +++++++++++ .../wlan/realtek/include/wifi_constants.h | 516 ++++ .../wlan/realtek/include/wifi_structures.h | 225 ++ .../wlan/realtek/include/wlan_basic_types.h | 610 +++++ .../wlan/realtek/include/wlan_bssdef.h | 756 ++++++ .../common/drivers/wlan/realtek/rtw_emac.cpp | 244 ++ .../common/drivers/wlan/realtek/rtw_emac.h | 28 + .../wlan/realtek/src/hal/OUTSRC/HalPhyRf.h | 102 + .../realtek/src/hal/OUTSRC/PhyDM_Adaptivity.h | 162 ++ .../wlan/realtek/src/hal/OUTSRC/mp_precomp.h | 24 + .../wlan/realtek/src/hal/OUTSRC/phydm.h | 2088 +++++++++++++++++ .../wlan/realtek/src/hal/OUTSRC/phydm_ACS.h | 97 + .../realtek/src/hal/OUTSRC/phydm_AntDect.h | 76 + .../realtek/src/hal/OUTSRC/phydm_AntDiv.h | 144 ++ .../src/hal/OUTSRC/phydm_CfoTracking.h | 73 + .../wlan/realtek/src/hal/OUTSRC/phydm_DIG.h | 476 ++++ .../hal/OUTSRC/phydm_DynamicBBPowerSaving.h | 63 + .../src/hal/OUTSRC/phydm_DynamicTxPower.h | 89 + .../src/hal/OUTSRC/phydm_EdcaTurboCheck.h | 152 ++ .../realtek/src/hal/OUTSRC/phydm_HWConfig.h | 508 ++++ .../src/hal/OUTSRC/phydm_NoiseMonitor.h | 49 + .../realtek/src/hal/OUTSRC/phydm_PathDiv.h | 193 ++ .../src/hal/OUTSRC/phydm_PowerTracking.h | 306 +++ .../wlan/realtek/src/hal/OUTSRC/phydm_RXHP.h | 105 + .../realtek/src/hal/OUTSRC/phydm_RaInfo.h | 210 ++ .../src/hal/OUTSRC/phydm_RegDefine11AC.h | 81 + .../src/hal/OUTSRC/phydm_RegDefine11N.h | 186 ++ .../wlan/realtek/src/hal/OUTSRC/phydm_debug.h | 900 +++++++ .../realtek/src/hal/OUTSRC/phydm_interface.h | 413 ++++ .../realtek/src/hal/OUTSRC/phydm_precomp.h | 349 +++ .../wlan/realtek/src/hal/OUTSRC/phydm_reg.h | 208 ++ .../wlan/realtek/src/hal/OUTSRC/phydm_types.h | 442 ++++ .../src/hal/OUTSRC/rom_odm_interface.h | 59 + .../OUTSRC/rtl8195a/Hal8195ARateAdaptive.h | 289 +++ .../src/hal/OUTSRC/rtl8195a/Hal8195AReg.h | 1354 +++++++++++ .../src/hal/OUTSRC/rtl8195a/HalPhyRf_8195A.h | 127 + .../hal/OUTSRC/rtl8195a/ROM_RTL8195A_PHYDM.h | 128 + .../hal/OUTSRC/rtl8195a/halhwimg8195a_bb.h | 59 + .../hal/OUTSRC/rtl8195a/halhwimg8195a_mac.h | 39 + .../hal/OUTSRC/rtl8195a/halhwimg8195a_rf.h | 104 + .../src/hal/OUTSRC/rtl8195a/phydm_RTL8195A.h | 69 + .../OUTSRC/rtl8195a/phydm_RegConfig8195A.h | 89 + .../drivers/wlan/realtek/src/hal/hal_data.h | 483 ++++ .../realtek/src/hal/rtl8195a/Hal8192CPhyReg.h | 1125 +++++++++ .../realtek/src/hal/rtl8195a/Hal8195APhyCfg.h | 186 ++ .../realtek/src/hal/rtl8195a/Hal8195APhyReg.h | 272 +++ .../realtek/src/hal/rtl8195a/Hal8195APwrSeq.h | 378 +++ .../src/hal/rtl8195a/rom_Hal8195APhyCfg.h | 56 + .../realtek/src/hal/rtl8195a/rtl8195a_cmd.h | 337 +++ .../realtek/src/hal/rtl8195a/rtl8195a_dm.h | 81 + .../realtek/src/hal/rtl8195a/rtl8195a_led.h | 35 + .../src/hal/rtl8195a/rtl8195a_pmu_cmd.h | 130 + .../src/hal/rtl8195a/rtl8195a_pmu_task.h | 491 ++++ .../realtek/src/hal/rtl8195a/rtl8195a_recv.h | 232 ++ .../realtek/src/hal/rtl8195a/rtl8195a_rf.h | 32 + .../realtek/src/hal/rtl8195a/rtl8195a_spec.h | 345 +++ .../src/hal/rtl8195a/rtl8195a_sreset.h | 30 + .../realtek/src/hal/rtl8195a/rtl8195a_xmit.h | 473 ++++ .../wlan/realtek/src/hci/gspi/gspi_intf.c | 493 ++++ .../wlan/realtek/src/hci/gspi/gspi_io.c | 566 +++++ .../wlan/realtek/src/hci/gspi/gspi_isr.c | 236 ++ .../wlan/realtek/src/hci/gspi/gspi_spec.h | 257 ++ .../drivers/wlan/realtek/src/hci/hci_intfs.h | 68 + .../drivers/wlan/realtek/src/hci/hci_spec.h | 433 ++++ .../wlan/realtek/src/hci/lxbus/lxbus_spec.h | 55 + .../wlan/realtek/src/hci/sdio/sdio_drvio.c | 818 +++++++ .../wlan/realtek/src/hci/sdio/sdio_intf.c | 264 +++ .../wlan/realtek/src/hci/sdio/sdio_isr.c | 223 ++ .../wlan/realtek/src/hci/sdio/sdio_spec.h | 193 ++ .../src/osdep/freertos/freertos_intfs.h | 161 ++ .../src/osdep/freertos/freertos_recv.h | 55 + .../src/osdep/freertos/freertos_skbuff.h | 53 + .../src/osdep/freertos/freertos_xmit.h | 62 + .../wlan/realtek/src/osdep/freertos/wrapper.h | 443 ++++ .../wlan/realtek/src/osdep/lwip_intf.c | 278 +++ .../wlan/realtek/src/osdep/lwip_intf.h | 84 + .../drivers/wlan/realtek/src/osdep/netdev.h | 113 + .../wlan/realtek/src/osdep/osdep_intf.h | 116 + .../drivers/wlan/realtek/src/osdep/skbuff.h | 57 + .../drivers/wlan/realtek/src/osdep/wireless.h | 1209 ++++++++++ .../wlan/realtek/src/osdep/wlan_intf.h | 66 + .../wlan_ram_map/rom/rom_wlan_ram_map.h | 24 + .../sdk/common/network/dhcp/dhcps.c | 738 ++++++ .../sdk/common/network/dhcp/dhcps.h | 143 ++ .../TARGET_AMEBA/sdk/os/os_dep/device_lock.c | 64 + .../sdk/os/os_dep/include/device_lock.h | 24 + .../sdk/os/os_dep/include/osdep_service.h | 594 +++++ .../sdk/os/os_dep/include/tcm_heap.h | 66 + .../sdk/os/os_dep/osdep_service.c | 1231 ++++++++++ .../TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c | 356 +++ .../TARGET_AMEBA/sdk/os/rtx/rtx_service.c | 1108 +++++++++ .../TARGET_AMEBA/sdk/os/rtx/rtx_service.h | 309 +++ .../TARGET_AMEBA/sdk/platform_opts.h | 386 +++ .../soc/realtek/8195a/cmsis/device/strproc.h | 104 + .../sdk/soc/realtek/8195a/fwlib/hal_adc.h | 320 +++ .../sdk/soc/realtek/8195a/fwlib/hal_api.h | 126 + .../sdk/soc/realtek/8195a/fwlib/hal_dac.h | 313 +++ .../sdk/soc/realtek/8195a/fwlib/hal_diag.h | 107 + .../sdk/soc/realtek/8195a/fwlib/hal_efuse.h | 22 + .../sdk/soc/realtek/8195a/fwlib/hal_gdma.h | 141 ++ .../sdk/soc/realtek/8195a/fwlib/hal_gpio.h | 242 ++ .../sdk/soc/realtek/8195a/fwlib/hal_i2c.h | 594 +++++ .../sdk/soc/realtek/8195a/fwlib/hal_irqn.h | 112 + .../soc/realtek/8195a/fwlib/hal_log_uart.h | 150 ++ .../sdk/soc/realtek/8195a/fwlib/hal_misc.h | 43 + .../sdk/soc/realtek/8195a/fwlib/hal_peri_on.h | 451 ++++ .../sdk/soc/realtek/8195a/fwlib/hal_pwm.h | 58 + .../realtek/8195a/fwlib/hal_soc_ps_monitor.h | 342 +++ .../soc/realtek/8195a/fwlib/hal_spi_flash.h | 352 +++ .../sdk/soc/realtek/8195a/fwlib/hal_ssi.h | 337 +++ .../sdk/soc/realtek/8195a/fwlib/hal_timer.h | 98 + .../sdk/soc/realtek/8195a/fwlib/hal_uart.h | 260 ++ .../sdk/soc/realtek/8195a/fwlib/hal_util.h | 252 ++ .../realtek/8195a/fwlib/hal_vector_table.h | 53 + .../realtek/8195a/misc/driver/rtl_consol.c | 380 +++ .../realtek/8195a/misc/driver/rtl_consol.h | 135 ++ .../sdk/soc/realtek/common/bsp/basic_types.h | 527 +++++ .../soc/realtek/common/bsp/section_config.h | 333 +++ .../common/rtl_std_lib/include/rtl_lib.h | 143 ++ .../TARGET_Realtek/TARGET_AMEBA/serial_api.c | 875 +++++++ targets/TARGET_Realtek/TARGET_AMEBA/sleep.c | 292 +++ .../TARGET_Realtek/TARGET_AMEBA/sleep_api.c | 36 + targets/TARGET_Realtek/TARGET_AMEBA/spi_api.c | 1101 +++++++++ .../TARGET_Realtek/TARGET_AMEBA/timer_api.c | 151 ++ .../TARGET_Realtek/TARGET_AMEBA/timer_api.h | 46 + .../TARGET_Realtek/TARGET_AMEBA/trng_api.c | 68 + .../TARGET_Realtek/TARGET_AMEBA/us_ticker.c | 144 ++ tools/REALTEK_RTL8195AM.py | 161 ++ .../REALTEK_RTL8195AM/ram_1_prepend.bin | Bin 0 -> 45056 bytes tools/targets/__init__.py | 7 + tools/toolchains/arm.py | 3 + tools/toolchains/iar.py | 4 + 263 files changed, 80000 insertions(+) create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PeripheralNames.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PortNames.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rlx8195A-symbol-v02-img2.ld create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rom.a create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis_nvic.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/diag.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_pinmux.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_platform.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rand.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_adc.h 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targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hci/hci_intfs.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hci/hci_spec.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hci/lxbus/lxbus_spec.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hci/sdio/sdio_drvio.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hci/sdio/sdio_intf.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hci/sdio/sdio_isr.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/hci/sdio/sdio_spec.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/freertos_intfs.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/freertos_recv.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/freertos_skbuff.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/freertos_xmit.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/lwip_intf.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/netdev.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/osdep_intf.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/skbuff.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wlan_intf.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/wlan_ram_map/rom/rom_wlan_ram_map.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/network/dhcp/dhcps.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/device_lock.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/device_lock.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/osdep_service.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/include/tcm_heap.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx/rtx_service.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx/rtx_service.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/platform_opts.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/cmsis/device/strproc.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_api.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_dac.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_diag.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_efuse.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gdma.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_gpio.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_i2c.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_irqn.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_log_uart.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_misc.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_peri_on.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pwm.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_soc_ps_monitor.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_spi_flash.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_ssi.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_uart.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_util.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_vector_table.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/driver/rtl_consol.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/misc/driver/rtl_consol.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/section_config.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/rtl_std_lib/include/rtl_lib.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/serial_api.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sleep.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/sleep_api.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/spi_api.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/timer_api.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/timer_api.h create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/trng_api.c create mode 100644 targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c create mode 100644 tools/REALTEK_RTL8195AM.py create mode 100644 tools/bootloaders/REALTEK_RTL8195AM/ram_1_prepend.bin diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PeripheralNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PeripheralNames.h new file mode 100644 index 00000000000..ead38f19b83 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PeripheralNames.h @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +typedef enum { + ADC0_0 = 0, + ADC0_1, + ADC0_2, + ADC0_3, + ADC0_4, + ADC0_5, + ADC0_6, + ADC0_7, + ADC0_8, + ADC0_9, + ADC0_10, + ADC0_11, + ADC0_12, + ADC0_13, + ADC0_14, + ADC0_15 +} ADCName; + +typedef enum { + DAC_0 = 0, + DAC_1 +} DACName; + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = 1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6 +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE +} CANName; +#endif + + +//#define STDIO_UART_TX PA_6 +//#define STDIO_UART_RX PA_7 +//#define STDIO_UART UART0 + +// modified by jimmysqf +#define UART_3 3 +#define STDIO_UART_TX PB_0 +#define STDIO_UART_RX PB_1 +#define STDIO_UART UART_3 + + +typedef enum { + DAC_0 = 0, + DAC_1 +} DACName; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h new file mode 100644 index 00000000000..ad6b4b376a8 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h @@ -0,0 +1,229 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _PINNAMES_H_ +#define _PINNAMES_H_ + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PORT_A = 0, + PORT_B = 1, + PORT_C = 2, + PORT_D = 3, + PORT_E = 4, + PORT_F = 5, + PORT_G = 6, + PORT_H = 7, + PORT_I = 8, + PORT_J = 9, + PORT_K = 10, + + PORT_V = 11, + PORT_U = 12, + PORT_MAX +} GPIO_PORT; + +#define RTL_PIN_PERI(FUN, IDX, SEL) ((int)(((FUN) << 8) | ((IDX)<<4) | (SEL))) +#define RTL_PIN_FUNC(FUN, SEL) ((int)(((FUN) << 7) | (SEL))) +#define RTL_GET_PERI_SEL(peri) ((int)((peri)&0x0F)) +#define RTL_GET_PERI_IDX(peri) ((int)(((peri) >> 4)&0x0F)) + +typedef enum { + PIN_INPUT=0, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = (PORT_A<<4|0), + PA_1 = (PORT_A<<4|1), + PA_2 = (PORT_A<<4|2), + PA_3 = (PORT_A<<4|3), + PA_4 = (PORT_A<<4|4), + PA_5 = (PORT_A<<4|5), + PA_6 = (PORT_A<<4|6), + PA_7 = (PORT_A<<4|7), + + PB_0 = (PORT_B<<4|0), + PB_1 = (PORT_B<<4|1), + PB_2 = (PORT_B<<4|2), + PB_3 = (PORT_B<<4|3), + PB_4 = (PORT_B<<4|4), + PB_5 = (PORT_B<<4|5), + PB_6 = (PORT_B<<4|6), + PB_7 = (PORT_B<<4|7), + + PC_0 = (PORT_C<<4|0), + PC_1 = (PORT_C<<4|1), + PC_2 = (PORT_C<<4|2), + PC_3 = (PORT_C<<4|3), + PC_4 = (PORT_C<<4|4), + PC_5 = (PORT_C<<4|5), + PC_6 = (PORT_C<<4|6), + PC_7 = (PORT_C<<4|7), + PC_8 = (PORT_C<<4|8), + PC_9 = (PORT_C<<4|9), + + PD_0 = (PORT_D<<4|0), + PD_1 = (PORT_D<<4|1), + PD_2 = (PORT_D<<4|2), + PD_3 = (PORT_D<<4|3), + PD_4 = (PORT_D<<4|4), + PD_5 = (PORT_D<<4|5), + PD_6 = (PORT_D<<4|6), + PD_7 = (PORT_D<<4|7), + PD_8 = (PORT_D<<4|8), + PD_9 = (PORT_D<<4|9), + + PE_0 = (PORT_E<<4|0), + PE_1 = (PORT_E<<4|1), + PE_2 = (PORT_E<<4|2), + PE_3 = (PORT_E<<4|3), + PE_4 = (PORT_E<<4|4), + PE_5 = (PORT_E<<4|5), + PE_6 = (PORT_E<<4|6), + PE_7 = (PORT_E<<4|7), + PE_8 = (PORT_E<<4|8), + PE_9 = (PORT_E<<4|9), + PE_A = (PORT_E<<4|10), + + PF_0 = (PORT_F<<4|0), + PF_1 = (PORT_F<<4|1), + PF_2 = (PORT_F<<4|2), + PF_3 = (PORT_F<<4|3), + PF_4 = (PORT_F<<4|4), + PF_5 = (PORT_F<<4|5), +// PF_6 = (PORT_F<<4|6), +// PF_7 = (PORT_F<<4|7), + + PG_0 = (PORT_G<<4|0), + PG_1 = (PORT_G<<4|1), + PG_2 = (PORT_G<<4|2), + PG_3 = (PORT_G<<4|3), + PG_4 = (PORT_G<<4|4), + PG_5 = (PORT_G<<4|5), + PG_6 = (PORT_G<<4|6), + PG_7 = (PORT_G<<4|7), + + PH_0 = (PORT_H<<4|0), + PH_1 = (PORT_H<<4|1), + PH_2 = (PORT_H<<4|2), + PH_3 = (PORT_H<<4|3), + PH_4 = (PORT_H<<4|4), + PH_5 = (PORT_H<<4|5), + PH_6 = (PORT_H<<4|6), + PH_7 = (PORT_H<<4|7), + + PI_0 = (PORT_I<<4|0), + PI_1 = (PORT_I<<4|1), + PI_2 = (PORT_I<<4|2), + PI_3 = (PORT_I<<4|3), + PI_4 = (PORT_I<<4|4), + PI_5 = (PORT_I<<4|5), + PI_6 = (PORT_I<<4|6), + PI_7 = (PORT_I<<4|7), + + PJ_0 = (PORT_J<<4|0), + PJ_1 = (PORT_J<<4|1), + PJ_2 = (PORT_J<<4|2), + PJ_3 = (PORT_J<<4|3), + PJ_4 = (PORT_J<<4|4), + PJ_5 = (PORT_J<<4|5), + PJ_6 = (PORT_J<<4|6), +// PJ_7 = (PORT_J<<4|7), + + PK_0 = (PORT_K<<4|0), + PK_1 = (PORT_K<<4|1), + PK_2 = (PORT_K<<4|2), + PK_3 = (PORT_K<<4|3), + PK_4 = (PORT_K<<4|4), + PK_5 = (PORT_K<<4|5), + PK_6 = (PORT_K<<4|6), +// PK_7 = (PORT_K<<4|7), + + AD_1 = (PORT_V<<4|1), + AD_2 = (PORT_V<<4|2), + AD_3 = (PORT_V<<4|3), + + DA_0 = (PORT_U<<4|0), + DA_1 = (PORT_U<<4|1), + // Arduino connector namings +/* + A0 = PA_0, + A1 = PA_1, + A2 = PA_4, + A3 = PB_0, + A4 = PC_1, + A5 = PC_0, + D0 = PA_3, + D1 = PA_2, + D2 = PA_10, + D3 = PB_3, + D4 = PB_5, + D5 = PB_4, + D6 = PB_10, + D7 = PA_8, + D8 = PA_9, + D9 = PC_7, + D10 = PB_6, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, +*/ + + // Generic signals namings + LED1 = PB_4, + LED2 = PB_5, + LED3 = PB_6, + LED4 = PB_7, + USER_BUTTON = PA_3, + SERIAL_TX = PA_7, + SERIAL_RX = PA_6, + USBTX = PB_0, //PA_7 + USBRX = PB_1, //PA_6 + I2C_SCL = PC_5, + I2C_SDA = PC_4, + SPI_MOSI = PC_2, + SPI_MISO = PC_3, + SPI_SCK = PC_1, + SPI_CS = PC_0, + PWM_OUT = PD_4, + + // Not connected + NC = (uint32_t)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#define PORT_NUM(pin) (((uint32_t)(pin) >> 4) & 0xF) +#define PIN_NUM(pin) ((uint32_t)(pin) & 0xF) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PortNames.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PortNames.h new file mode 100644 index 00000000000..29a53243712 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PortNames.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7, + PortI = 8 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device.h new file mode 100644 index 00000000000..a9434cd19a7 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#ifndef CONFIG_MBED_ENABLED +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 +#endif +#include "objects.h" + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct new file mode 100644 index 00000000000..ccb96ae00ac --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -0,0 +1,48 @@ +; ************************************************************* +; *** Scatter-Loading Description File for RTL8195A *** +; ************************************************************* +LR_ROM 0x00000000 0x00030000{ + _ROM_CODE 0x00000000 0x00030000 { + ;*.o (RESET, +First) + ;*(InRoot$$Sections) + } +} + +LR_RAM 0x10006000 0x6FFFF { +;LR_RAM 0x10000000 0x6FFFF { + ;ROM_BSS 0x10000000 0x0005FFF{ + ;rtl_console.o(.mon.ram.bss*) + ;} + + .image2.table.1 0x10006000 FIXED { + rtl8195a_init.o(.image2.ram.data*) + } + + .image2.table.2 +0 FIXED{ + rtl8195a_init.o(.image2.validate.rodata*) + } + + .text +0 FIXED{ + rtl8195a_init.o(.infra.ram.start) + ;*.o(.mon.ram.text*) + ;*.o(.hal.flash.text*) + ;*.o(.hal.sdrc.text*) + ;*.o(.hal.gpio.text*) + ;*.o(.text*) + ;*.o(.rodata*) + .ANY (+RO) + } + + .data +0 FIXED{ + .ANY (+RW) + } + + RW_IRAM1 +0 UNINIT FIXED { + .ANY (+ZI) + } +} + +LR_DRAM 0x30000000 0x1FFFFF{ + _DRAM_CODE 0x30000000 0x1FFFFF{ + } +} \ No newline at end of file diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..cf2b07e681e --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2016 Realtek Semiconductor Corp. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + //push down stack pointer to recycle some of the stack space that are not use in future + __asm volatile + ( + "MRS IP, MSP \n" + "ADD IP, #64 \n" + "BIC IP, IP, #7 \n" + "MSR MSP, IP \n" + ); + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rlx8195A-symbol-v02-img2.ld b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rlx8195A-symbol-v02-img2.ld new file mode 100644 index 00000000000..e1cd068df97 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rlx8195A-symbol-v02-img2.ld @@ -0,0 +1,864 @@ + + +ENTRY(Reset_Handler) + +/*INCLUDE "mbed-os/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/export-rom_v02.txt"*/ +SECTIONS +{ + __vectors_table = 0x0; + Reset_Handler = 0x101; + NMI_Handler = 0x109; + HardFault_Handler = 0x10d; + MemManage_Handler = 0x121; + BusFault_Handler = 0x125; + UsageFault_Handler = 0x129; + HalLogUartInit = 0x201; + HalSerialGetcRtl8195a = 0x309; + HalSerialGetIsrEnRegRtl8195a = 0x329; + HalSerialSetIrqEnRegRtl8195a = 0x335; + HalCpuClkConfig = 0x341; + HalGetCpuClk = 0x355; + HalRomInfo = 0x39d; + HalGetRomInfo = 0x3b5; + HalResetVsr = 0x3c5; + HalDelayUs = 0x899; + HalNMIHandler = 0x8e1; + HalHardFaultHandler = 0x911; + HalMemManageHandler = 0xc09; + HalBusFaultHandler = 0xc39; + HalUsageFaultHandler = 0xc69; + HalUart0PinCtrlRtl8195A = 0xcfd; + HalUart1PinCtrlRtl8195A = 0xdc9; + HalUart2PinCtrlRtl8195A = 0xe9d; + HalSPI0PinCtrlRtl8195A = 0xf75; + HalSPI1PinCtrlRtl8195A = 0x1015; + HalSPI2PinCtrlRtl8195A = 0x10e5; + HalSPI0MCSPinCtrlRtl8195A = 0x11b5; + HalI2C0PinCtrlRtl8195A = 0x1275; + HalI2C1PinCtrlRtl8195A = 0x1381; + HalI2C2PinCtrlRtl8195A = 0x1459; + HalI2C3PinCtrlRtl8195A = 0x1529; + HalI2S0PinCtrlRtl8195A = 0x1639; + HalI2S1PinCtrlRtl8195A = 0x176d; + HalPCM0PinCtrlRtl8195A = 0x1845; + HalPCM1PinCtrlRtl8195A = 0x1949; + HalSDIODPinCtrlRtl8195A = 0x1a1d; + HalSDIOHPinCtrlRtl8195A = 0x1a6d; + HalMIIPinCtrlRtl8195A = 0x1ab9; + HalWLLEDPinCtrlRtl8195A = 0x1b51; + HalWLANT0PinCtrlRtl8195A = 0x1c0d; + HalWLANT1PinCtrlRtl8195A = 0x1c61; + HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5; + HalWLBTCMDPinCtrlRtl8195A = 0x1d05; + HalNFCPinCtrlRtl8195A = 0x1d59; + HalPWM0PinCtrlRtl8195A = 0x1da9; + HalPWM1PinCtrlRtl8195A = 0x1ead; + HalPWM2PinCtrlRtl8195A = 0x1fb5; + HalPWM3PinCtrlRtl8195A = 0x20b1; + HalETE0PinCtrlRtl8195A = 0x21b9; + HalETE1PinCtrlRtl8195A = 0x22c1; + HalETE2PinCtrlRtl8195A = 0x23c9; + HalETE3PinCtrlRtl8195A = 0x24d1; + HalEGTIMPinCtrlRtl8195A = 0x25d9; + HalSPIFlashPinCtrlRtl8195A = 0x2679; + HalSDRPinCtrlRtl8195A = 0x2725; + HalJTAGPinCtrlRtl8195A = 0x280d; + HalTRACEPinCtrlRtl8195A = 0x2861; + HalLOGUartPinCtrlRtl8195A = 0x28b9; + HalLOGUartIRPinCtrlRtl8195A = 0x291d; + HalSICPinCtrlRtl8195A = 0x2981; + HalEEPROMPinCtrlRtl8195A = 0x29d9; + HalDEBUGPinCtrlRtl8195A = 0x2a31; + HalPinCtrlRtl8195A = 0x2b39; + SpicRxCmdRtl8195A = 0x2e5d; + SpicWaitBusyDoneRtl8195A = 0x2ea5; + SpicGetFlashStatusRtl8195A = 0x2eb5; + SpicWaitWipDoneRtl8195A = 0x2f55; + SpicTxCmdRtl8195A = 0x2f6d; + SpicSetFlashStatusRtl8195A = 0x2fc1; + SpicCmpDataForCalibrationRtl8195A = 0x3049; + SpicLoadInitParaFromClockRtl8195A = 0x3081; + SpicInitRtl8195A = 0x30e5; + SpicEraseFlashRtl8195A = 0x31bd; + SpiFlashApp = 0x3279; + HalPeripheralIntrHandle = 0x33b5; + HalSysOnIntrHandle = 0x3439; + HalWdgIntrHandle = 0x3485; + HalTimer0IntrHandle = 0x34d5; + HalTimer1IntrHandle = 0x3525; + HalI2C3IntrHandle = 0x3575; + HalTimer2To7IntrHandle = 0x35c5; + HalSpi0IntrHandle = 0x3615; + HalGpioIntrHandle = 0x3665; + HalUart0IntrHandle = 0x36b5; + HalSpiFlashIntrHandle = 0x3705; + HalUsbOtgIntrHandle = 0x3755; + HalSdioHostIntrHandle = 0x37a5; + HalI2s0OrPcm0IntrHandle = 0x37f5; + HalI2s1OrPcm1IntrHandle = 0x3845; + HalWlDmaIntrHandle = 0x3895; + HalWlProtocolIntrHandle = 0x38e5; + HalCryptoIntrHandle = 0x3935; + HalGmacIntrHandle = 0x3985; + HalGdma0Ch0IntrHandle = 0x39d5; + HalGdma0Ch1IntrHandle = 0x3a25; + HalGdma0Ch2IntrHandle = 0x3a75; + HalGdma0Ch3IntrHandle = 0x3ac5; + HalGdma0Ch4IntrHandle = 0x3b15; + HalGdma0Ch5IntrHandle = 0x3b65; + HalGdma1Ch0IntrHandle = 0x3bb5; + HalGdma1Ch1IntrHandle = 0x3c05; + HalGdma1Ch2IntrHandle = 0x3c55; + HalGdma1Ch3IntrHandle = 0x3ca5; + HalGdma1Ch4IntrHandle = 0x3cf5; + HalGdma1Ch5IntrHandle = 0x3d45; + HalSdioDeviceIntrHandle = 0x3d95; + VectorTableInitRtl8195A = 0x3de5; + VectorTableInitForOSRtl8195A = 0x4019; + VectorIrqRegisterRtl8195A = 0x4029; + VectorIrqUnRegisterRtl8195A = 0x4091; + VectorIrqEnRtl8195A = 0x40f1; + VectorIrqDisRtl8195A = 0x418d; + _UartRxDmaIrqHandle = 0x422d; + HalRuartPutCRtl8195a = 0x4281; + HalRuartGetCRtl8195a = 0x429d; + HalRuartRTSCtrlRtl8195a = 0x42bd; + HalRuartGetDebugValueRtl8195a = 0x42e1; + HalRuartGetIMRRtl8195a = 0x43e1; + HalRuartSetIMRRtl8195a = 0x442d; + _UartIrqHandle = 0x4465; + HalRuartDmaInitRtl8195a = 0x4681; + HalRuartIntDisableRtl8195a = 0x4845; + HalRuartDeInitRtl8195a = 0x4855; + HalRuartIntEnableRtl8195a = 0x4985; + _UartTxDmaIrqHandle = 0x4995; + HalRuartRegIrqRtl8195a = 0x49d1; + HalRuartAdapterLoadDefRtl8195a = 0x4a4d; + HalRuartTxGdmaLoadDefRtl8195a = 0x4add; + HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9; + RuartLock = 0x4cc9; + RuartUnLock = 0x4ced; + HalRuartIntSendRtl8195a = 0x4d09; + HalRuartDmaSendRtl8195a = 0x4e35; + HalRuartStopSendRtl8195a = 0x4f89; + HalRuartIntRecvRtl8195a = 0x504d; + HalRuartDmaRecvRtl8195a = 0x51ad; + HalRuartStopRecvRtl8195a = 0x52cd; + RuartIsTimeout = 0x5385; + HalRuartSendRtl8195a = 0x53b1; + HalRuartRecvRtl8195a = 0x5599; + RuartResetRxFifoRtl8195a = 0x5751; + HalRuartResetRxFifoRtl8195a = 0x5775; + HalRuartInitRtl8195a = 0x5829; + HalGdmaOnOffRtl8195a = 0x5df1; + HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d; + HalGdmaChEnRtl8195a = 0x5e51; + HalGdmaChDisRtl8195a = 0x5e6d; + HalGdamChInitRtl8195a = 0x5e91; + HalGdmaChSetingRtl8195a = 0x5ebd; + HalGdmaChBlockSetingRtl8195a = 0x000060dd; + HalGdmaChIsrCleanRtl8195a = 0x6419; + HalGdmaChCleanAutoSrcRtl8195a = 0x64a1; + HalGdmaChCleanAutoDstRtl8195a = 0x6501; + HalEFUSEPowerSwitch8195AROM = 0x6561; + HALEFUSEOneByteReadROM = 0x65f9; + HALEFUSEOneByteWriteROM = 0x6699; + __rtl_memcmpb_v1_00 = 0x681d; + __rtl_random_v1_00 = 0x6861; + __rtl_align_to_be32_v1_00 = 0x6881; + __rtl_memsetw_v1_00 = 0x6899; + __rtl_memsetb_v1_00 = 0x68ad; + __rtl_memcpyw_v1_00 = 0x68bd; + __rtl_memcpyb_v1_00 = 0x68dd; + __rtl_memDump_v1_00 = 0x68f5; + __rtl_AES_set_encrypt_key = 0x6901; + __rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11; + __rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95; + __rtl_cryptoEngine_init_v1_00 = 0x6ea9; + __rtl_cryptoEngine_exit_v1_00 = 0x7055; + __rtl_cryptoEngine_reset_v1_00 = 0x70b1; + __rtl_cryptoEngine_v1_00 = 0x70ed; + __rtl_crypto_cipher_init_v1_00 = 0x7c69; + __rtl_crypto_cipher_encrypt_v1_00 = 0x7c89; + __rtl_crypto_cipher_decrypt_v1_00 = 0x7cad; + HalSsiPinmuxEnableRtl8195a = 0x7cd5; + HalSsiEnableRtl8195a = 0x7e45; + HalSsiDisableRtl8195a = 0x7ef9; + HalSsiLoadSettingRtl8195a = 0x7fad; + HalSsiSetInterruptMaskRtl8195a = 0x8521; + HalSsiGetInterruptMaskRtl8195a = 0x85c9; + HalSsiSetSclkPolarityRtl8195a = 0x863d; + HalSsiSetSclkPhaseRtl8195a = 0x8715; + HalSsiWriteRtl8195a = 0x87e9; + HalSsiSetDeviceRoleRtl8195a = 0x8861; + HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9; + HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941; + HalSsiReadRtl8195a = 0x89b9; + HalSsiGetRxFifoLevelRtl8195a = 0x8a2d; + HalSsiGetTxFifoLevelRtl8195a = 0x8aa5; + HalSsiGetStatusRtl8195a = 0x8b1d; + HalSsiWriteableRtl8195a = 0x8b91; + HalSsiReadableRtl8195a = 0x8c09; + HalSsiBusyRtl8195a = 0x8c81; + HalSsiReadInterruptRtl8195a = 0x8cf9; + HalSsiWriteInterruptRtl8195a = 0x8efd; + HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009; + HalSsiGetInterruptStatusRtl8195a = 0x90d9; + HalSsiInterruptEnableRtl8195a = 0x914d; + HalSsiInterruptDisableRtl8195a = 0x9299; + HalSsiGetRawInterruptStatusRtl8195a = 0x93e9; + HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d; + HalSsiInitRtl8195a = 0x94d1; + _SsiReadInterrupt = 0x9ba5; + _SsiWriteInterrupt = 0x9db1; + _SsiIrqHandle = 0x9eb1; + HalI2CWrite32 = 0xa061; + HalI2CRead32 = 0xa09d; + HalI2CDeInit8195a = 0xa0dd; + HalI2CSendRtl8195a = 0xa1f1; + HalI2CReceiveRtl8195a = 0xa25d; + HalI2CEnableRtl8195a = 0xa271; + HalI2CIntrCtrl8195a = 0xa389; + HalI2CReadRegRtl8195a = 0xa3a1; + HalI2CWriteRegRtl8195a = 0xa3b1; + HalI2CSetCLKRtl8195a = 0xa3c5; + HalI2CMassSendRtl8195a = 0xa6e9; + HalI2CClrIntrRtl8195a = 0xa749; + HalI2CClrAllIntrRtl8195a = 0xa761; + HalI2CInit8195a = 0xa775; + HalI2CDMACtrl8195a = 0xaa31; + RtkI2CIoCtrl = 0xaa61; + RtkI2CPowerCtrl = 0xaa65; + HalI2COpInit = 0xaa69; + I2CIsTimeout = 0xac65; + I2CTXGDMAISRHandle = 0xb435; + I2CRXGDMAISRHandle = 0xb4c1; + RtkI2CIrqInit = 0xb54d; + RtkI2CIrqDeInit = 0xb611; + RtkI2CPinMuxInit = 0xb675; + RtkI2CPinMuxDeInit = 0xb7c9; + RtkI2CDMAInit = 0xb955; + RtkI2CInit = 0xbc95; + RtkI2CDMADeInit = 0xbdad; + RtkI2CDeInit = 0xbe4d; + RtkI2CSendUserAddr = 0xbee5; + RtkI2CSend = 0xc07d; + RtkI2CLoadDefault = 0xce51; + RtkSalI2COpInit = 0xcf21; + HalI2SWrite32 = 0xcf65; + HalI2SRead32 = 0xcf85; + HalI2SDeInitRtl8195a = 0xcfa9; + HalI2STxRtl8195a = 0xcfc9; + HalI2SRxRtl8195a = 0xd011; + HalI2SEnableRtl8195a = 0xd05d; + HalI2SIntrCtrlRtl8195a = 0xd0b1; + HalI2SReadRegRtl8195a = 0xd0d1; + HalI2SClrIntrRtl8195a = 0xd0dd; + HalI2SClrAllIntrRtl8195a = 0xd0fd; + HalI2SInitRtl8195a = 0xd11d; + GPIO_GetIPPinName_8195a = 0xd2e5; + GPIO_GetChipPinName_8195a = 0xd331; + GPIO_PullCtrl_8195a = 0xd39d; + GPIO_FuncOn_8195a = 0xd421; + GPIO_FuncOff_8195a = 0xd481; + GPIO_Int_Mask_8195a = 0xd4e9; + GPIO_Int_SetType_8195a = 0xd511; + HAL_GPIO_IrqHandler_8195a = 0xd5fd; + HAL_GPIO_MbedIrqHandler_8195a = 0xd645; + HAL_GPIO_UserIrqHandler_8195a = 0xd6a1; + HAL_GPIO_IntCtrl_8195a = 0xd6cd; + HAL_GPIO_Init_8195a = 0xd805; + HAL_GPIO_DeInit_8195a = 0xdac1; + HAL_GPIO_ReadPin_8195a = 0xdbd1; + HAL_GPIO_WritePin_8195a = 0xdc91; + HAL_GPIO_RegIrq_8195a = 0xddad; + HAL_GPIO_UnRegIrq_8195a = 0xddf5; + HAL_GPIO_UserRegIrq_8195a = 0xde15; + HAL_GPIO_UserUnRegIrq_8195a = 0xdef9; + HAL_GPIO_MaskIrq_8195a = 0xdfc1; + HAL_GPIO_UnMaskIrq_8195a = 0xe061; + HAL_GPIO_IntDebounce_8195a = 0xe101; + HAL_GPIO_GetIPPinName_8195a = 0xe1c1; + HAL_GPIO_PullCtrl_8195a = 0xe1c9; + DumpForOneBytes = 0xe259; + CmdRomHelp = 0xe419; + CmdWriteWord = 0xe491; + CmdDumpHelfWord = 0xe505; + CmdDumpWord = 0xe5f1; + CmdDumpByte = 0xe6f5; + CmdSpiFlashTool = 0xe751; + GetRomCmdNum = 0xe7a9; + CmdWriteByte = 0xe7ad; + Isspace = 0xe7ed; + Strtoul = 0xe801; + ArrayInitialize = 0xe8b1; + GetArgc = 0xe8c9; + GetArgv = 0xe8f9; + UartLogCmdExecute = 0xe95d; + UartLogShowBackSpace = 0xe9fd; + UartLogRecallOldCmd = 0xea39; + UartLogHistoryCmd = 0xea71; + UartLogCmdChk = 0xeadd; + UartLogIrqHandle = 0xebf5; + RtlConsolInit = 0xecc5; + RtlConsolTaskRom = 0xed49; + RtlExitConsol = 0xed79; + RtlConsolRom = 0xedcd; + HalTimerOpInit = 0xee0d; + HalTimerIrq2To7Handle = 0xee59; + HalGetTimerIdRtl8195a = 0xef09; + HalTimerInitRtl8195a = 0xef3d; + HalTimerDisRtl8195a = 0xf069; + HalTimerEnRtl8195a = 0xf089; + HalTimerReadCountRtl8195a = 0xf0a9; + HalTimerIrqClearRtl8195a = 0xf0bd; + HalTimerDumpRegRtl8195a = 0xf0d1; + VSprintf = 0xf129; + DiagPrintf = 0xf39d; + DiagSPrintf = 0xf3b9; + DiagSnPrintf = 0xf3d1; + prvDiagPrintf = 0xf3ed; + prvDiagSPrintf = 0xf40d; + _memcmp = 0xf429; + _memcpy = 0xf465; + _memset = 0xf511; + Rand = 0xf585; + _strncpy = 0xf60d; + _strcpy = 0xf629; + prvStrCpy = 0xf639; + _strlen = 0xf651; + _strnlen = 0xf669; + prvStrLen = 0xf699; + _strcmp = 0xf6b1; + _strncmp = 0xf6d1; + prvStrCmp = 0xf719; + StrUpr = 0xf749; + prvAtoi = 0xf769; + prvStrStr = 0xf7bd; + _strsep = 0xf7d5; + skip_spaces = 0xf815; + skip_atoi = 0xf831; + _parse_integer_fixup_radix = 0xf869; + _parse_integer = 0xf8bd; + simple_strtoull = 0xf915; + simple_strtoll = 0xf945; + simple_strtoul = 0xf965; + simple_strtol = 0xf96d; + _vsscanf = 0xf985; + _sscanf = 0xff71; + div_u64 = 0xff91; + div_s64 = 0xff99; + div_u64_rem = 0xffa1; + div_s64_rem = 0xffb1; + _strpbrk = 0xffc1; + _strchr = 0xffed; + aes_set_key = 0x10005; + aes_encrypt = 0x103d1; + aes_decrypt = 0x114a5; + AES_WRAP = 0x125c9; + AES_UnWRAP = 0x12701; + crc32_get = 0x12861; + arc4_byte = 0x12895; + rt_arc4_init = 0x128bd; + rt_arc4_crypt = 0x12901; + rt_md5_init = 0x131c1; + rt_md5_append = 0x131f5; + rt_md5_final = 0x1327d; + rt_md5_hmac = 0x132d5; + rtw_get_bit_value_from_ieee_value = 0x13449; + rtw_is_cckrates_included = 0x13475; + rtw_is_cckratesonly_included = 0x134b5; + rtw_check_network_type = 0x134dd; + rtw_set_fixed_ie = 0x1350d; + rtw_set_ie = 0x1352d; + rtw_get_ie = 0x1355d; + rtw_set_supported_rate = 0x13591; + rtw_get_rateset_len = 0x13611; + rtw_get_wpa_ie = 0x1362d; + rtw_get_wpa2_ie = 0x136c9; + rtw_get_wpa_cipher_suite = 0x13701; + rtw_get_wpa2_cipher_suite = 0x13769; + rtw_parse_wpa_ie = 0x137d1; + rtw_parse_wpa2_ie = 0x138ad; + rtw_get_sec_ie = 0x13965; + rtw_get_wps_ie = 0x13a15; + rtw_get_wps_attr = 0x13a99; + rtw_get_wps_attr_content = 0x13b49; + rtw_ieee802_11_parse_elems = 0x13b91; + str_2char2num = 0x13d9d; + key_2char2num = 0x13db9; + convert_ip_addr = 0x13dd1; + rom_psk_PasswordHash = 0x13e9d; + rom_psk_CalcGTK = 0x13ed5; + rom_psk_CalcPTK = 0x13f69; + wep_80211_encrypt = 0x14295; + wep_80211_decrypt = 0x142f5; + tkip_micappendbyte = 0x14389; + rtw_secmicsetkey = 0x143d9; + rtw_secmicappend = 0x14419; + rtw_secgetmic = 0x14435; + rtw_seccalctkipmic = 0x1449d; + tkip_phase1 = 0x145a5; + tkip_phase2 = 0x14725; + tkip_80211_encrypt = 0x14941; + tkip_80211_decrypt = 0x149d5; + aes1_encrypt = 0x14a8d; + aesccmp_construct_mic_iv = 0x14c65; + aesccmp_construct_mic_header1 = 0x14ccd; + aesccmp_construct_mic_header2 = 0x14d21; + aesccmp_construct_ctr_preload = 0x14db5; + aes_80211_encrypt = 0x14e29; + aes_80211_decrypt = 0x151ad; + _sha1_process_message_block = 0x155b9; + _sha1_pad_message = 0x15749; + rt_sha1_init = 0x157e5; + rt_sha1_update = 0x15831; + rt_sha1_finish = 0x158a9; + rt_hmac_sha1 = 0x15909; + rom_aes_128_cbc_encrypt = 0x15a65; + rom_aes_128_cbc_decrypt = 0x15ae1; + rom_rijndaelKeySetupEnc = 0x15b5d; + rom_aes_decrypt_init = 0x15c39; + rom_aes_internal_decrypt = 0x15d15; + rom_aes_decrypt_deinit = 0x16071; + rom_aes_encrypt_init = 0x16085; + rom_aes_internal_encrypt = 0x1609d; + rom_aes_encrypt_deinit = 0x16451; + bignum_init = 0x17b35; + bignum_deinit = 0x17b61; + bignum_get_unsigned_bin_len = 0x17b81; + bignum_get_unsigned_bin = 0x17b85; + bignum_set_unsigned_bin = 0x17c21; + bignum_cmp = 0x17cd1; + bignum_cmp_d = 0x17cd5; + bignum_add = 0x17cfd; + bignum_sub = 0x17d0d; + bignum_mul = 0x17d1d; + bignum_exptmod = 0x17d2d; + WPS_realloc = 0x17d51; + os_zalloc = 0x17d99; + rom_hmac_sha256_vector = 0x17dc1; + rom_hmac_sha256 = 0x17ebd; + rom_sha256_vector = 0x18009; + phy_CalculateBitShift = 0x18221; + PHY_SetBBReg_8195A = 0x18239; + PHY_QueryBBReg_8195A = 0x18279; + ROM_odm_QueryRxPwrPercentage = 0x1829d; + ROM_odm_EVMdbToPercentage = 0x182bd; + ROM_odm_SignalScaleMapping_8195A = 0x182e5; + ROM_odm_FalseAlarmCounterStatistics = 0x183cd; + ROM_odm_SetEDCCAThreshold = 0x18721; + ROM_odm_SetTRxMux = 0x18749; + ROM_odm_SetCrystalCap = 0x18771; + ROM_odm_GetDefaultCrytaltalCap = 0x187d5; + ROM_ODM_CfoTrackingReset = 0x187e9; + ROM_odm_CfoTrackingFlow = 0x18811; + curve25519_donna = 0x1965d; + aes_test_alignment_detection = 0x1a391; + aes_mode_reset = 0x1a3ed; + aes_ecb_encrypt = 0x1a3f9; + aes_ecb_decrypt = 0x1a431; + aes_cbc_encrypt = 0x1a469; + aes_cbc_decrypt = 0x1a579; + aes_cfb_encrypt = 0x1a701; + aes_cfb_decrypt = 0x1a9e5; + aes_ofb_crypt = 0x1acc9; + aes_ctr_crypt = 0x1af7d; + aes_encrypt_key128 = 0x1b289; + aes_encrypt_key192 = 0x1b2a5; + aes_encrypt_key256 = 0x1b2c1; + aes_encrypt_key = 0x1b2e1; + aes_decrypt_key128 = 0x1b351; + aes_decrypt_key192 = 0x1b36d; + aes_decrypt_key256 = 0x1b389; + aes_decrypt_key = 0x1b3a9; + aes_init = 0x1b419; + CRYPTO_chacha_20 = 0x1b41d; + CRYPTO_poly1305_init = 0x1bc25; + CRYPTO_poly1305_update = 0x1bd09; + CRYPTO_poly1305_finish = 0x1bd8d; + rom_sha512_starts = 0x1ceb5; + rom_sha512_update = 0x1d009; + rom_sha512_finish = 0x1d011; + rom_sha512 = 0x1d261; + rom_sha512_hmac_starts = 0x1d299; + rom_sha512_hmac_update = 0x1d35d; + rom_sha512_hmac_finish = 0x1d365; + rom_sha512_hmac_reset = 0x1d3b5; + rom_sha512_hmac = 0x1d3d1; + rom_sha512_hkdf = 0x1d40d; + rom_ed25519_gen_keypair = 0x1d501; + rom_ed25519_gen_signature = 0x1d505; + rom_ed25519_verify_signature = 0x1d51d; + rom_ed25519_crypto_sign_seed_keypair = 0x1d521; + rom_ed25519_crypto_sign_detached = 0x1d579; + rom_ed25519_crypto_sign_verify_detached = 0x1d655; + rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d; + rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35; + rom_ed25519_ge_p3_tobytes = 0x207d5; + rom_ed25519_ge_scalarmult_base = 0x20821; + rom_ed25519_ge_tobytes = 0x209e1; + rom_ed25519_sc_muladd = 0x20a2d; + rom_ed25519_sc_reduce = 0x2603d; + __rtl_memchr_v1_00 = 0x28a4d; + __rtl_memcmp_v1_00 = 0x28ae1; + __rtl_memcpy_v1_00 = 0x28b49; + __rtl_memmove_v1_00 = 0x28bed; + __rtl_memset_v1_00 = 0x28cb5; + __rtl_strcat_v1_00 = 0x28d49; + __rtl_strchr_v1_00 = 0x28d91; + __rtl_strcmp_v1_00 = 0x28e55; + __rtl_strcpy_v1_00 = 0x28ec9; + __rtl_strlen_v1_00 = 0x28f15; + __rtl_strncat_v1_00 = 0x28f69; + __rtl_strncmp_v1_00 = 0x28fc5; + __rtl_strncpy_v1_00 = 0x2907d; + __rtl_strstr_v1_00 = 0x293cd; + __rtl_strsep_v1_00 = 0x2960d; + __rtl_strtok_v1_00 = 0x29619; + __rtl__strtok_r_v1_00 = 0x2962d; + __rtl_strtok_r_v1_00 = 0x29691; + __rtl_close_v1_00 = 0x29699; + __rtl_fstat_v1_00 = 0x296ad; + __rtl_isatty_v1_00 = 0x296c1; + __rtl_lseek_v1_00 = 0x296d5; + __rtl_open_v1_00 = 0x296e9; + __rtl_read_v1_00 = 0x296fd; + __rtl_write_v1_00 = 0x29711; + __rtl_sbrk_v1_00 = 0x29725; + __rtl_ltoa_v1_00 = 0x297bd; + __rtl_ultoa_v1_00 = 0x29855; + __rtl_dtoi_v1_00 = 0x298c5; + __rtl_dtoi64_v1_00 = 0x29945; + __rtl_dtoui_v1_00 = 0x299dd; + __rtl_ftol_v1_00 = 0x299e5; + __rtl_itof_v1_00 = 0x29a51; + __rtl_itod_v1_00 = 0x29ae9; + __rtl_i64tod_v1_00 = 0x29b79; + __rtl_uitod_v1_00 = 0x29c55; + __rtl_ftod_v1_00 = 0x29d2d; + __rtl_dtof_v1_00 = 0x29de9; + __rtl_uitof_v1_00 = 0x29e89; + __rtl_fadd_v1_00 = 0x29f65; + __rtl_fsub_v1_00 = 0x2a261; + __rtl_fmul_v1_00 = 0x2a559; + __rtl_fdiv_v1_00 = 0x2a695; + __rtl_dadd_v1_00 = 0x2a825; + __rtl_dsub_v1_00 = 0x2aed9; + __rtl_dmul_v1_00 = 0x2b555; + __rtl_ddiv_v1_00 = 0x2b8ad; + __rtl_dcmpeq_v1_00 = 0x2be4d; + __rtl_dcmplt_v1_00 = 0x2bebd; + __rtl_dcmpgt_v1_00 = 0x2bf51; + __rtl_dcmple_v1_00 = 0x2c049; + __rtl_fcmplt_v1_00 = 0x2c139; + __rtl_fcmpgt_v1_00 = 0x2c195; + __rtl_cos_f32_v1_00 = 0x2c229; + __rtl_sin_f32_v1_00 = 0x2c435; + __rtl_fabs_v1_00 = 0x2c639; + __rtl_fabsf_v1_00 = 0x2c641; + __rtl_dtoa_r_v1_00 = 0x2c77d; + __rom_mallocr_init_v1_00 = 0x2d7d1; + __rtl_free_r_v1_00 = 0x2d841; + __rtl_malloc_r_v1_00 = 0x2da31; + __rtl_realloc_r_v1_00 = 0x2df55; + __rtl_memalign_r_v1_00 = 0x2e331; + __rtl_valloc_r_v1_00 = 0x2e421; + __rtl_pvalloc_r_v1_00 = 0x2e42d; + __rtl_calloc_r_v1_00 = 0x2e441; + __rtl_cfree_r_v1_00 = 0x2e4a9; + __rtl_Balloc_v1_00 = 0x2e515; + __rtl_Bfree_v1_00 = 0x2e571; + __rtl_i2b_v1_00 = 0x2e585; + __rtl_multadd_v1_00 = 0x2e599; + __rtl_mult_v1_00 = 0x2e629; + __rtl_pow5mult_v1_00 = 0x2e769; + __rtl_hi0bits_v1_00 = 0x2e809; + __rtl_d2b_v1_00 = 0x2e845; + __rtl_lshift_v1_00 = 0x2e901; + __rtl_cmp_v1_00 = 0x2e9bd; + __rtl_diff_v1_00 = 0x2ea01; + __rtl_sread_v1_00 = 0x2eae9; + __rtl_seofread_v1_00 = 0x2eb39; + __rtl_swrite_v1_00 = 0x2eb3d; + __rtl_sseek_v1_00 = 0x2ebc1; + __rtl_sclose_v1_00 = 0x2ec11; + __rtl_sbrk_r_v1_00 = 0x2ec41; + __rtl_fflush_r_v1_00 = 0x2ef8d; + __rtl_vfprintf_r_v1_00 = 0x2f661; + __rtl_fpclassifyd = 0x30c15; + CpkClkTbl = 0x30c68; + ROM_IMG1_VALID_PATTEN = 0x30c80; + SpicCalibrationPattern = 0x30c88; + SpicInitCPUCLK = 0x30c98; + BAUDRATE = 0x30ca8; + OVSR = 0x30d1c; + DIV = 0x30d90; + OVSR_ADJ = 0x30e04; + __AES_rcon = 0x30e78; + __AES_Te4 = 0x30ea0; + I2CDmaChNo = 0x312a0; + UartLogRomCmdTable = 0x316a0; + _HalRuartOp = 0x31700; + _HalGdmaOp = 0x31760; + RTW_WPA_OUI_TYPE = 0x3540c; + WPA_CIPHER_SUITE_NONE = 0x35410; + WPA_CIPHER_SUITE_WEP40 = 0x35414; + WPA_CIPHER_SUITE_TKIP = 0x35418; + WPA_CIPHER_SUITE_CCMP = 0x3541c; + WPA_CIPHER_SUITE_WEP104 = 0x35420; + RSN_CIPHER_SUITE_NONE = 0x35424; + RSN_CIPHER_SUITE_WEP40 = 0x35428; + RSN_CIPHER_SUITE_TKIP = 0x3542c; + RSN_CIPHER_SUITE_CCMP = 0x35430; + RSN_CIPHER_SUITE_WEP104 = 0x35434; + RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444; + RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448; + RSN_VERSION_BSD = 0x3544c; + rom_wps_Te0 = 0x35988; + rom_wps_rcons = 0x35d88; + rom_wps_Td4s = 0x35d94; + rom_wps_Td0 = 0x35e94; + NewVectorTable = 0x10000000; + UserIrqFunTable = 0x10000100; + UserIrqDataTable = 0x10000200; + __rom_bss_start__ = 0x10000300; + CfgSysDebugWarn = 0x10000300; + CfgSysDebugInfo = 0x10000304; + CfgSysDebugErr = 0x10000308; + ConfigDebugWarn = 0x1000030c; + ConfigDebugInfo = 0x10000310; + ConfigDebugErr = 0x10000314; + HalTimerOp = 0x10000318; + GPIOState = 0x10000334; + gTimerRecord = 0x1000034c; + SSI_DBG_CONFIG = 0x10000350; + _pHAL_Gpio_Adapter = 0x10000354; + Timer2To7VectorTable = 0x10000358; + pUartLogCtl = 0x10000384; + UartLogBuf = 0x10000388; + UartLogCtl = 0x10000408; + UartLogHistoryBuf = 0x10000430; + ArgvArray = 0x100006ac; + rom_wlan_ram_map = 0x100006d4; + FalseAlmCnt = 0x100006e0; + ROMInfo = 0x10000720; + DM_CfoTrack = 0x10000738; + rom_libgloss_ram_map = 0x10000760; + __rtl_errno = 0x10000bc4; + _rtl_impure_ptr = 0x10001c60; +} + +/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader). + But we can put .data/.bss of Image2 in this region */ +MEMORY +{ + TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + DATA_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 0x10006000 - 0x10002100 + BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 0x10070000 - 0x10006000 + SD_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * _reset_init : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + __rom_bss_start__ = 0x10000300; + __rom_bss_end__ = 0x10000bc8; + __ram_table_start__ = 0x10000bc8; + + .image2.table : + { + __image2_start__ = .; + __image2_entry_func__ = .; + KEEP(*(SORT(.image2.ram.data*))) + __image2_validate_code__ = .; + KEEP(*(.image2.validate.rodata*)) + } > BD_RAM + + .text : + { + . = ALIGN(4); + *(.infra.ram.start*) + *(.mon.ram.text*) + *(.hal.flash.text*) + *(.hal.sdrc.text*) + *(.hal.gpio.text*) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + *(.rodata*) + KEEP(*(.eh_frame*)) + } > BD_RAM + __etext = .; + + + __data_start__ = .; + .data : + { + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + + /* All data end */ + } > BD_RAM + __data_end__ = .; + __image2_end__ = .; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > BD_RAM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > BD_RAM + __exidx_end = .; + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(.bdsram.data*) + *(COMMON) + __bss_end__ = .; + } > BD_RAM + + + .bf_data : + { + __buffer_data_start__ = .; + *(.bfsram.data*) + __buffer_data_end__ = .; + } > BD_RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > BD_RAM + + .TCM_overlay : + { + *(.tcm.heap*) + } > TCM + + + .sdr_text : + { + __image3_start__ = .; + *(.sdram.text*) + *(.p2p.text*) + *(.wps.text*) + *(.websocket.text*) + } > SD_RAM + + .sdr_rodata : + { + *(.sdram.rodata*) + *(.p2p.rodata*) + *(.wps.rodata*) + *(.websocket.rodata*) + } > SD_RAM + + .sdr_bss : + { + __sdram_bss_start__ = .; + *(.sdram.bss*) + *(.p2p.bss*) + *(.wps.bss*) + *(.websocket.bss*) + __sdram_bss_end__ = .; + } > SD_RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > BD_RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit") + + .sdr_data : + { + __sdram_data_start__ = .; + *(.sdram.data*) + __sdram_data_end__ = .; + } > SD_RAM +} + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rom.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rom.a new file mode 100644 index 0000000000000000000000000000000000000000..4978f11c11e301719d93d4ecdd437ec011b7b57d GIT binary patch literal 383620 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IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ + +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; +define symbol __ICFEDIT_region_TCM_start__ = 0x1FFF0000; +define symbol __ICFEDIT_region_TCM_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_ROM_USED_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF; +define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10006000; +define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF; +define symbol __ICFEDIT_region_SDRAM_RAM_start__ = 0x30000000; +define symbol __ICFEDIT_region_SDRAM_RAM_end__ = 0x301FFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; // 8K +define symbol __ICFEDIT_size_heap__ = 0xF000; // 60K +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__]; +define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__]; +define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +//initialize by copy { readwrite }; +do not initialize { section .noinit }; + + +/**************************************** + * ROM Section config * + ****************************************/ +keep { section .rom }; +//place at start of ROM_region { readonly, section .rom }; +place at start of ROM_region {section .rom }; + +/**************************************** + * BD RAM Section config * + ****************************************/ +keep { section .ram_dedecated_vector_table* }; +define block .vector_table with fixed order{section .ram_dedecated_vector_table*}; + +keep { section .ram_user_define_irq_table* }; +define block .user_vector_table with fixed order{section .ram_user_define_irq_table*}; + +keep { section .ram_user_define_data_table* }; +define block .user_data_table with fixed order{section .ram_user_define_data_table*}; + +define block .rom.bss with fixed order{ section .hal.ram.bss* object hal_misc.o, + section .hal.ram.bss* object hal_pinmux.o, + section .hal.ram.bss* object diag.o, + section .hal.ram.bss* object rtl8195a_ssi_rom.o, + section .hal.ram.bss* object rtl8195a_gpio.o, + section .hal.ram.bss*, + section .timer2_7_vector_table.data*, + section .infra.ram.bss*, + section .mon.ram.bss*, + section .wlan_ram_map* object rom_wlan_ram_map.o, + section .wlan_ram_map*, + section .libc.ram.bss*, + }; +keep { section .start.ram.data* }; +define block .ram.start.table with fixed order{ section .start.ram.data* }; + +keep { section .image1.validate.rodata* }; +//keep { section .infra.ram.data* }; +//keep { section .timer.ram.data* }; +keep { section .hal.ram.data* }; +define block .ram_image1.data with fixed order{ section .image1.validate.rodata*, + section .infra.ram.data*, + //section .timer.ram.data*, + section .cutb.ram.data*, + section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr + section .cutc.ram.data*, + section .hal.ram.data* + }; +//define block .ram_image1.bss with fixed order{ //section .hal.flash.data*, +// section .hal.sdrc.data* +// }; + +define block .ram_image1.text with fixed order{ section .hal.ram.text*, + section .hal.sdrc.text*, + //section .text* object startup.o, + section .infra.ram.text*, + }; + +define block IMAGE1 with fixed order { section LOADER }; +define block IMAGE1_DBG with fixed order { block .ram.start.table, + block .ram_image1.data, + //block .ram_image1.bss, + block .ram_image1.text }; + +place at start of ROM_USED_RAM_region { //readwrite, + block .vector_table, + block .user_vector_table, + block .user_data_table, + block .rom.bss, + block IMAGE1 + }; +/** + IMAGE2 +**/ +keep { section .image2.ram.data* }; +define block .image2.start.table1 with fixed order{ section .image2.ram.data* }; + +keep { section .image2.validate.rodata*, section .custom.validate.rodata* }; +define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*, section .custom.validate.rodata* }; + +/* +define block SHT$$PREINIT_ARRAY { preinit_array }; +define block SHT$$INIT_ARRAY { init_array }; +define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY, + block SHT$$INIT_ARRAY }; +*/ +define block .ram_image2.text with fixed order{ section .infra.ram.start*, + section .rodata*, + //block CPP_INIT, + section .mon.ram.text*, + section .hal.flash.text*, + section .hal.gpio.text*, + section .text* object main.o, + section .text*, + section CODE, + section .otg.rom.text, + section Veneer object startup.o, + section __DLIB_PERTHREAD + }; + +define block .ram.data with fixed order{ section .data*, + section DATA, + section .iar.init_table, + section .data object vector_table_M.o + }; +define block IMAGE2 with fixed order { block .image2.start.table1, + block .image2.start.table2, + block .ram_image2.text, + block .ram.data, + readonly, + }; +define block .ram.bss with fixed order{ section .bss*, + //section .ssl_ram_map, + section .hal.flash.data*, + section .hal.gpio.data*, + section COMMON, + section .bdsram.data*, + }; + + +place at start of BD_RAM_region { + block IMAGE2, + readwrite, + block .ram.bss, + }; +place at end of BD_RAM_region{ + block HEAP, + //block CSTACK + }; + +/**************************************** + * BD RAM Section config * + ****************************************/ +define block .heap with fixed order{ section .heap* }; +define block .stack_dummy with fixed order { section .stack }; +/*TCM placement */ +define overlay TCM_overlay { //section .tcm.heap, + //section .bss object mem.o, + //section .bss object memp.o, + block .heap, + block .stack_dummy + }; +/* dummy code placement */ +define overlay TCM_overlay { block IMAGE1_DBG }; +place at start of TCM_region { //readwrite, + overlay TCM_overlay + }; + +/* modify by Ian - for mbed stack isr start address setting*/ +place at end of TCM_region { block CSTACK }; + +define exported symbol __rom_bss_start__ = 0x10000300; // use in rom +define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom +define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom +define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code +define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis.h new file mode 100644 index 00000000000..420fd53ae6b --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "rtl8195a.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis_nvic.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis_nvic.h new file mode 100644 index 00000000000..ca0b5b972c7 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 64 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ... +// Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM +#define NVIC_NUM_VECTORS 128 +#define NVIC_USER_IRQ_OFFSET 64 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/diag.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/diag.h new file mode 100644 index 00000000000..b42387890fa --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/diag.h @@ -0,0 +1,843 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _DIAG_H_ +#define _DIAG_H_ + +#include "platform_autoconf.h" +#include "basic_types.h" + +#include /* for size_t */ + +extern u32 ConfigDebugErr; +extern u32 ConfigDebugInfo; +extern u32 ConfigDebugWarn; + +extern u32 CfgSysDebugErr; +extern u32 CfgSysDebugInfo; +extern u32 CfgSysDebugWarn; + +#define DBG_ERR_MSG_ON(x) (ConfigDebugErr |= (x)) +#define DBG_WARN_MSG_ON(x) (ConfigDebugWarn |= (x)) +#define DBG_INFO_MSG_ON(x) (ConfigDebugInfo |= (x)) + +#define DBG_ERR_MSG_OFF(x) (ConfigDebugErr &= ~(x)) +#define DBG_WARN_MSG_OFF(x) (ConfigDebugWarn &= ~(x)) +#define DBG_INFO_MSG_OFF(x) (ConfigDebugInfo &= ~(x)) + +// Define debug group +#define _DBG_BOOT_ 0x00000001 +#define _DBG_GDMA_ 0x00000002 +#define _DBG_GPIO_ 0x00000004 +#define _DBG_TIMER_ 0x00000008 +#define _DBG_I2C_ 0x00000010 +#define _DBG_I2S_ 0x00000020 +#define _DBG_MII_ 0x00000040 +#define _DBG_NFC_ 0x00000080 +#define _DBG_PCM_ 0x00000100 +#define _DBG_PWM_ 0x00000200 +#define _DBG_SDIO_ 0x00000400 +#define _DBG_SSI_ 0x00000800 +#define _DBG_SPI_FLASH_ 0x00001000 +#define _DBG_SDR_ 0x00002000 +#define _DBG_UART_ 0x00004000 +#define _DBG_USB_OTG_ 0x00008000 +#define _DBG_USB_CORE_ 0x00010000 +#define _DBG_CRYPTO_ 0x00020000 +#define _DBG_ADC_ 0x00040000 +#define _DBG_DAC_ 0x00080000 + +#define _DBG_MISC_ 0x40000000 +#define _DBG_FAULT_ 0x80000000 + +typedef enum _SYSTEM_DBG_DEFINE_ { + _SYSDBG_MISC_ = 1<<0, + _SYSDBG_MAILBOX_ = 1<<1, + _SYSDBG_TIMER_ = 1<<2 + +} SYSTEM_DBG; + +extern +_LONG_CALL_ROM_ u32 +DiagPrintf( + IN const char *fmt, ... +); + +u32 +DiagSPrintf( + IN u8 *buf, + IN const char *fmt, ... +); + +int +prvDiagPrintf( + IN const char *fmt, ... +); + +int +prvDiagSPrintf( + IN char *buf, + IN const char *fmt, ... +); + + +#define _DbgDump DiagPrintf + +#define DRIVER_PREFIX "RTL8195A[Driver]: " +#define HAL_PREFIX "RTL8195A[HAL]: " +#define DMA_PREFIX "RTL8195A[DMA]: " +#define SDIO_PREFIX "RTL8195A[SDIO]" +#define MBOX_PREFIX "[OS-MBOX]" +#define TIMER_PREFIX "[OS-TMR]" + +#define BOOT_ERR_PREFIX "[BOOT Err]" +#define BOOT_WARN_PREFIX "[BOOT Wrn]" +#define BOOT_INFO_PREFIX "[BOOT Inf]" + +#define GDMA_ERR_PREFIX "[GDMA Err]" +#define GDMA_WARN_PREFIX "[GDMA Wrn]" +#define GDMA_INFO_PREFIX "[GDMA Inf]" + +#define GPIO_ERR_PREFIX "[GPIO Err]" +#define GPIO_WARN_PREFIX "[GPIO Wrn]" +#define GPIO_INFO_PREFIX "[GPIO Inf]" + +#define TIMER_ERR_PREFIX "[TIMR Err]" +#define TIMER_WARN_PREFIX "[TIMR Wrn]" +#define TIMER_INFO_PREFIX "[TIMR Inf]" + +#define I2C_ERR_PREFIX "[I2C Err]" +#define I2C_WARN_PREFIX "[I2C Wrn]" +#define I2C_INFO_PREFIX "[I2C Inf]" + +#define I2S_ERR_PREFIX "[I2S Err]" +#define I2S_WARN_PREFIX "[I2S Wrn]" +#define I2S_INFO_PREFIX "[I2S Inf]" + +#define MII_ERR_PREFIX "[MII Err]" +#define MII_WARN_PREFIX "[MII Wrn]" +#define MII_INFO_PREFIX "[MII Inf]" + +#define NFC_ERR_PREFIX "[NFC Err]" +#define NFC_WARN_PREFIX "[NFC Wrn]" +#define NFC_INFO_PREFIX "[NFC Inf]" + +#define PCM_ERR_PREFIX "[PCM Err]" +#define PCM_WARN_PREFIX "[PCM Wrn]" +#define PCM_INFO_PREFIX "[PCM Inf]" + +#define PWM_ERR_PREFIX "[PWM Err]" +#define PWM_WARN_PREFIX "[PWM Wrn]" +#define PWM_INFO_PREFIX "[PWM Inf]" + +#define SSI_ERR_PREFIX "[SSI Err]" +#define SSI_WARN_PREFIX "[SSI Wrn]" +#define SSI_INFO_PREFIX "[SSI Inf]" + +#define SDIO_ERR_PREFIX "[SDIO Err]" +#define SDIO_WARN_PREFIX "[SDIO Wrn]" +#define SDIO_INFO_PREFIX "[SDIO Inf]" + +#define SPIF_ERR_PREFIX "[SPIF Err]" +#define SPIF_WARN_PREFIX "[SPIF Wrn]" +#define SPIF_INFO_PREFIX "[SPIF Inf]" + +#define SDR_ERR_PREFIX "[SDR Err]" +#define SDR_WARN_PREFIX "[SDR Wrn]" +#define SDR_INFO_PREFIX "[SDR Inf]" + +#define UART_ERR_PREFIX "[UART Err]" +#define UART_WARN_PREFIX "[UART Wrn]" +#define UART_INFO_PREFIX "[UART Inf]" + +#define USB_ERR_PREFIX "[USB Err]" +#define USB_WARN_PREFIX "[USB Wrn]" +#define USB_INFO_PREFIX "[USB Inf]" + +#define IPSEC_ERR_PREFIX "[CRYP Err]" +#define IPSEC_WARN_PREFIX "[CRYP Wrn]" +#define IPSEC_INFO_PREFIX "[CRYP Inf]" + +#define ADC_ERR_PREFIX "[ADC Err]" +#define ADC_WARN_PREFIX "[ADC Wrn]" +#define ADC_INFO_PREFIX "[ADC Inf]" + +#define DAC_ERR_PREFIX "[DAC Err]" +#define DAC_WARN_PREFIX "[DAC Wrn]" +#define DAC_INFO_PREFIX "[DAC Inf]" + +#define MISC_ERR_PREFIX "[MISC Err]" +#define MISC_WARN_PREFIX "[MISC Wrn]" +#define MISC_INFO_PREFIX "[MISC Inf]" + +#define OTG_ERR_PREFIX "[OTG Err]" +#define OTG_WARN_PREFIX "[OTG Wrn]" +#define OTG_INFO_PREFIX "[OTG Inf]" + +#define OTG_PREFIX "RTL8195A[OTG]: " +#define OTG_PREFIX_LVL "RTL8195A[OTG_LVL_%2x]: " + +//#ifdef +#define CONFIG_DEBUG_ERROR 1 +#define CONFIG_DEBUG_WARN 1 +#define CONFIG_DEBUG_INFO 1 + +#ifndef likely +#define likely(x) (x) +#define unlikely(x) (x) +#endif + +#ifdef CONFIG_DEBUG_LOG + +#if CONFIG_DEBUG_ERROR // if Build-In Debug Error Message + +#define DBG_BOOT_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_BOOT_)) \ + _DbgDump("\r"BOOT_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_GDMA_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_GDMA_)) \ + _DbgDump("\r"GDMA_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_GPIO_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_GPIO_)) \ + _DbgDump("\r"GPIO_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_TIMER_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_TIMER_)) \ + _DbgDump("\r"TIMER_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_I2C_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_I2C_)) \ + _DbgDump("\r"I2C_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_I2S_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_I2S_)) \ + _DbgDump("\r"I2S_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_MII_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_MII_)) \ + _DbgDump("\r"MII_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_NFC_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_NFC_)) \ + _DbgDump("\r"NFC_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_PCM_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_PCM_)) \ + _DbgDump("\r"PCM_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_PWM_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_PWM_)) \ + _DbgDump("\r"PWM_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SSI_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_SSI_)) \ + _DbgDump("\r"SSI_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SDIO_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_SDIO_)) \ + _DbgDump("\r"SDIO_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SPIF_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_SPI_FLASH_)) \ + _DbgDump("\r"SPIF_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SDR_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_SDR_)) \ + _DbgDump("\r"SDR_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_UART_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_UART_)) \ + _DbgDump("\r"UART_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_USBOTG_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_USB_OTG_)) \ + _DbgDump("\r" __VA_ARGS__);\ +}while(0) + +#define DBG_USBCOR_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_USB_CORE_)) \ + _DbgDump("\r"USB_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_CRYPTO_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_CRYPTO_)) \ + _DbgDump("\r"IPSEC_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_ADC_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_ADC_)) \ + _DbgDump("\r"ADC_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_DAC_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_DAC_)) \ + _DbgDump("\r"DAC_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#define MSG_MBOX_ERR(...) do {\ + if (likely(CfgSysDebugErr & _SYSDBG_MAILBOX_)) \ + _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\ +}while(0) + +#define MSG_TIMER_ERR(...) do {\ + if (likely(CfgSysDebugErr & _SYSDBG_TIMER_)) \ + _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_8195A_OTG(...) do{\ + if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \ + _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\ + }while(0) + +#define DBG_8195A_OTG_INFO(...) do{\ + if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \ + _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\ + }while(0) + +#define DBG_8195A_OTG_WARN(...) do{\ + if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \ + _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\ + }while(0) + +#define DBG_8195A_OTG_ERR(...) do{\ + if (unlikely(ConfigDebugErr & _DBG_USB_OTG_)) \ + _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\ + }while(0) + +#define DBG_8195A_OTG_LVL(LVL,...) do{\ + if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)){ \ + _DbgDump("\r"OTG_PREFIX_LVL,LVL);\ + _DbgDump(__VA_ARGS__);\ + }\ +}while(0) + +#define DBG_MISC_ERR(...) do {\ + if (likely(ConfigDebugErr & _DBG_MISC_)) \ + _DbgDump("\r"MISC_ERR_PREFIX __VA_ARGS__);\ +}while(0) + +#else // else of "#if CONFIG_DEBUG_ERROR" + +#define DBG_BOOT_ERR(...) +#define DBG_GDMA_ERR(...) +#define DBG_GPIO_ERR(...) +#define DBG_TIMER_ERR(...) +#define DBG_I2C_ERR(...) +#define DBG_I2S_ERR(...) +#define DBG_MII_ERR(...) +#define DBG_NFC_ERR(...) +#define DBG_PCM_ERR(...) +#define DBG_PWM_ERR(...) +#define DBG_SSI_ERR(...) +#define DBG_SDIO_ERR(...) +#define DBG_SPIF_ERR(...) +#define DBG_SDR_ERR(...) +#define DBG_UART_ERR(...) +#define DBG_USBOTG_ERR(...) +#define DBG_USBCOR_ERR(...) +#define DBG_CRYPTO_ERR(...) +#define DBG_ADC_ERR(...) +#define DBG_DAC_ERR(...) + +#define MSG_MBOX_ERR(...) +#define MSG_TIMER_ERR(...) +#define DBG_8195A_OTG(...) +#define DBG_8195A_OTG_LVL(LVL,...) +#define DBG_8195A_OTG_INFO(...) +#define DBG_8195A_OTG_WARN(...) +#define DBG_8195A_OTG_ERR(...) + + +#endif // end of else of "#if CONFIG_DEBUG_ERROR" + +// ============================================================= + +#if CONFIG_DEBUG_WARN // if Build-In Debug Warring Message + +#define DBG_BOOT_WARN(...) do {\ + if (unlikely(ConfigDebugWarn& _DBG_BOOT_)) \ + _DbgDump("\r"BOOT_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_GDMA_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_GDMA_)) \ + _DbgDump("\r"GDMA_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_GPIO_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_GPIO_)) \ + _DbgDump("\r"GPIO_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_TIMER_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_TIMER_)) \ + _DbgDump("\r"TIMER_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_I2C_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_I2C_)) \ + _DbgDump("\r"I2C_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_I2S_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_I2S_)) \ + _DbgDump("\r"I2S_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_MII_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_MII_)) \ + _DbgDump("\r"MII_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_NFC_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_NFC_)) \ + _DbgDump("\r"NFC_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_PCM_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_PCM_)) \ + _DbgDump("\r"PCM_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_PWM_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_PWM_)) \ + _DbgDump("\r"PWM_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SSI_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_SSI_)) \ + _DbgDump("\r"SSI_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SDIO_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_SDIO_)) \ + _DbgDump("\r"SDIO_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SPIF_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_SPI_FLASH_)) \ + _DbgDump("\r"SPIF_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SDR_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_SDR_)) \ + _DbgDump("\r"SDR_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_UART_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_UART_)) \ + _DbgDump("\r"UART_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_USBOTG_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \ + _DbgDump("\r" __VA_ARGS__);\ +}while(0) + +#define DBG_USBCOR_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_USB_CORE_)) \ + _DbgDump("\r"USB_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_CRYPTO_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_CRYPTO_)) \ + _DbgDump("\r"IPSEC_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_ADC_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_ADC_)) \ + _DbgDump("\r"ADC_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_DAC_WARN(...) do {\ + if (unlikely(ConfigDebugWarn & _DBG_DAC_)) \ + _DbgDump("\r"DAC_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#define MSG_MBOX_WARN(...) do {\ + if (unlikely(CfgSysDebugWarn& _SYSDBG_MAILBOX_)) \ + _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\ +}while(0) + +#define MSG_TIMER_WARN(...) do {\ + if (unlikely(CfgSysDebugWarn & _SYSDBG_TIMER_)) \ + _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_MISC_WARN(...) do {\ + if (likely(ConfigDebugWarn & _DBG_MISC_)) \ + _DbgDump("\r"MISC_WARN_PREFIX __VA_ARGS__);\ +}while(0) + +#else // else of "#if CONFIG_DEBUG_WARN" + +#define DBG_BOOT_WARN(...) +#define DBG_GDMA_WARN(...) +#define DBG_GPIO_WARN(...) +#define DBG_TIMER_WARN(...) +#define DBG_I2C_WARN(...) +#define DBG_I2S_WARN(...) +#define DBG_MII_WARN(...) +#define DBG_NFC_WARN(...) +#define DBG_PCM_WARN(...) +#define DBG_PWM_WARN(...) +#define DBG_SSI_WARN(...) +#define DBG_SDIO_WARN(...) +#define DBG_SPIF_WARN(...) +#define DBG_SDR_WARN(...) +#define DBG_UART_WARN(...) +#define DBG_USBOTG_WARN(...) +#define DBG_USBCOR_WARN(...) +#define DBG_CRYPTO_WARN(...) +#define DBG_ADC_WARN(...) +#define DBG_DAC_WARN(...) +#define DBG_MISC_WARN(...) + +#define MSG_MBOX_WARN(...) +#define MSG_TIMER_WARN(...) + +#endif // end of else of "#if CONFIG_DEBUG_WARN" + +// ============================================================= + +#if CONFIG_DEBUG_INFO // if Build-In Debug Information Message + +#define DBG_BOOT_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_BOOT_)) \ + _DbgDump("\r"BOOT_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_GDMA_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_GDMA_)) \ + _DbgDump("\r"GDMA_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_GPIO_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_GPIO_)) \ + _DbgDump("\r"GPIO_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_TIMER_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_TIMER_)) \ + _DbgDump("\r"TIMER_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_I2C_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_I2C_)) \ + _DbgDump("\r"I2C_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_I2S_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_I2S_)) \ + _DbgDump("\r"I2S_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_MII_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_MII_)) \ + _DbgDump("\r"MII_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_NFC_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_NFC_)) \ + _DbgDump("\r"NFC_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_PCM_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_PCM_)) \ + _DbgDump("\r"PCM_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_PWM_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_PWM_)) \ + _DbgDump("\r"PWM_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SSI_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_SSI_)) \ + _DbgDump("\r"SSI_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SDIO_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_SDIO_)) \ + _DbgDump("\r"SDIO_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SPIF_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_SPI_FLASH_)) \ + _DbgDump("\r"SPIF_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_SDR_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_SDR_)) \ + _DbgDump("\r"SDR_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_UART_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_UART_)) \ + _DbgDump("\r"UART_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_USBOTG_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \ + _DbgDump("\r" __VA_ARGS__);\ +}while(0) + +#define DBG_USBCOR_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_USB_CORE_)) \ + _DbgDump("\r"USB_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_CRYPTO_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_CRYPTO_)) \ + _DbgDump("\r"IPSEC_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_ADC_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_ADC_)) \ + _DbgDump("\r"ADC_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_DAC_INFO(...) do {\ + if (unlikely(ConfigDebugInfo & _DBG_DAC_)) \ + _DbgDump("\r"DAC_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#define MSG_MBOX_INFO(...) do {\ + if (unlikely(CfgSysDebugInfo & _SYSDBG_MAILBOX_)) \ + _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\ +}while(0) + +#define MSG_TIMER_INFO(...) do {\ + if (unlikely(CfgSysDebugInfo & _SYSDBG_TIMER_)) \ + _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_MISC_INFO(...) do {\ + if (likely(ConfigDebugInfo & _DBG_MISC_)) \ + _DbgDump("\r"MISC_INFO_PREFIX __VA_ARGS__);\ +}while(0) + +#else // else of "#if CONFIG_DEBUG_INFO" + +#define DBG_BOOT_INFO(...) +#define DBG_GDMA_INFO(...) +#define DBG_GPIO_INFO(...) +#define DBG_TIMER_INFO(...) +#define DBG_I2C_INFO(...) +#define DBG_I2S_INFO(...) +#define DBG_MII_INFO(...) +#define DBG_NFC_INFO(...) +#define DBG_PCM_INFO(...) +#define DBG_PWM_INFO(...) +#define DBG_SSI_INFO(...) +#define DBG_SDIO_INFO(...) +#define DBG_SPIF_INFO(...) +#define DBG_SDR_INFO(...) +#define DBG_UART_INFO(...) +#define DBG_USBOTG_INFO(...) +#define DBG_USBCOR_INFO(...) +#define DBG_CRYPTO_INFO(...) +#define DBG_ADC_INFO(...) +#define DBG_DAC_INFO(...) +#define DBG_MISC_INFO(...) + +#define MSG_MBOX_INFO(...) +#define MSG_TIMER_INFO(...) + +#endif // end of else of "#if CONFIG_DEBUG_INFO" + +#define DBG_8195A_DRIVER(...) do {\ + if (unlikely(ConfigDebugErr & (_DBG_I2S_|_DBG_PCM_|_DBG_TIMER_))) \ + _DbgDump("\r"DRIVER_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_8195A_HAL(...) do {\ + if (unlikely(ConfigDebugErr & (_DBG_SDR_|_DBG_MISC_))) \ + _DbgDump("\r"HAL_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_8195A_DMA(...) do {\ + if (unlikely(ConfigDebugErr & _DBG_GDMA_)) \ + _DbgDump("\r"DMA_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_8195A_SDIO(...) do {\ + if (unlikely(ConfigDebugErr & _DBG_SDIO_)) \ + _DbgDump("\r"SDIO_PREFIX __VA_ARGS__);\ +}while(0) + +#define DBG_8195A(...) do {\ + if (unlikely(ConfigDebugErr & _DBG_MISC_)) \ + _DbgDump("\r" __VA_ARGS__);\ +}while(0) + +#define MONITOR_LOG(...) do {\ + if (unlikely(ConfigDebugErr & _DBG_MISC_)) \ + _DbgDump( __VA_ARGS__);\ +}while(0) + +#define DBG_ERROR_LOG(...) do {\ + if (unlikely(ConfigDebugErr & _DBG_FAULT_)) \ + _DbgDump( __VA_ARGS__);\ +}while(0) + +#ifdef __GNUC__ +#define DBG_ASSERT(x) do {\ + if (unlikely(!(x))) \ + _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\ + }while(0) +#endif + +#ifdef __ICCARM__ +#define DBG_ASSERT(x) do {\ + if (unlikely(!(x))) \ + _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\ + }while(0) +#endif + +#else // else of "#if CONFIG_DEBUG_LOG" +#define DBG_8195A_DRIVER(...) + +#define DBG_8195A_HAL(...) + +#define DBG_8195A(...) + +#define DBG_8195A_DMA(...) + +#define MONITOR_LOG(...) + +#define DBG_ERROR_LOG(...) + +#define DBG_8195A_SDIO(...) + +#define DBG_BOOT_ERR(...) +#define DBG_GDMA_ERR(...) +#define DBG_GPIO_ERR(...) +#define DBG_TIMER_ERR(...) +#define DBG_I2C_ERR(...) +#define DBG_I2S_ERR(...) +#define DBG_MII_ERR(...) +#define DBG_NFC_ERR(...) +#define DBG_PCM_ERR(...) +#define DBG_PWM_ERR(...) +#define DBG_SSI_ERR(...) +#define DBG_SDIO_ERR(...) +#define DBG_SPIF_ERR(...) +#define DBG_SDR_ERR(...) +#define DBG_UART_ERR(...) +#define DBG_USBOTG_ERR(...) +#define DBG_USBCOR_ERR(...) +#define DBG_CRYPTO_ERR(...) +#define DBG_ADC_ERR(...) +#define DBG_DAC_ERR(...) +#define MSG_MBOX_ERR(...) +#define MSG_TIMER_ERR(...) + +#define DBG_BOOT_WARN(...) +#define DBG_GDMA_WARN(...) +#define DBG_GPIO_WARN(...) +#define DBG_TIMER_WARN(...) +#define DBG_I2C_WARN(...) +#define DBG_I2S_WARN(...) +#define DBG_MII_WARN(...) +#define DBG_NFC_WARN(...) +#define DBG_PCM_WARN(...) +#define DBG_PWM_WARN(...) +#define DBG_SSI_WARN(...) +#define DBG_SDIO_WARN(...) +#define DBG_SPIF_WARN(...) +#define DBG_SDR_WARN(...) +#define DBG_UART_WARN(...) +#define DBG_USBOTG_WARN(...) +#define DBG_USBCOR_WARN(...) +#define DBG_CRYPTO_WARN(...) +#define DBG_ADC_WARN(...) +#define DBG_DAC_WARN(...) +#define MSG_MBOX_WARN(...) +#define MSG_TIMER_WARN(...) + +#define DBG_BOOT_INFO(...) +#define DBG_GDMA_INFO(...) +#define DBG_GPIO_INFO(...) +#define DBG_TIMER_INFO(...) +#define DBG_I2C_INFO(...) +#define DBG_I2S_INFO(...) +#define DBG_MII_INFO(...) +#define DBG_NFC_INFO(...) +#define DBG_PCM_INFO(...) +#define DBG_PWM_INFO(...) +#define DBG_SSI_INFO(...) +#define DBG_SDIO_INFO(...) +#define DBG_SPIF_INFO(...) +#define DBG_SDR_INFO(...) +#define DBG_UART_INFO(...) +#define DBG_USBOTG_INFO(...) +#define DBG_USBCOR_INFO(...) +#define DBG_CRYPTO_INFO(...) +#define DBG_ADC_INFO(...) +#define DBG_DAC_INFO(...) + +#define MSG_MBOX_INFO(...) +#define MSG_TIMER_INFO(...) + +#define DBG_ASSERT(x) + +#endif + +#define ANSI_COLOR_GREEN "\x1b[32m" +#define ANSI_COLOR_CYAN "\x1b[36m" +#define ANSI_COLOR_YELLOW "\x1b[33m" +#define ANSI_COLOR_MAGENTA "\x1b[35m" +#define ANSI_COLOR_RED "\x1b[31m" +#define ANSI_COLOR_BLUE "\x1b[34m" +#define ANSI_COLOR_RESET "\x1b[0m" + +#define IDENT_ONE_SPACE " " +#define IDENT_TWO_SPACE " " +#define IDENT_FOUR_SPACE " " +#define IDENT_SIX_SPACE " " +#define IDENT_EIGHT_SPACE " " + +#ifdef CONFIG_DEBUG_LOG +typedef enum _DBG_CFG_TYPE_ { + DBG_CFG_ERR=0, + DBG_CFG_WARN=1, + DBG_CFG_INFO=2 +} DBG_CFG_TYPE; + +typedef struct _DBG_CFG_CMD_ { + u8 cmd_name[16]; + u32 cmd_type; +} DBG_CFG_CMD, *PDBG_CFG_CMD; + +#endif + +typedef enum _CONSOLE_OP_STAGE_ { + ROM_STAGE = 0, + RAM_STAGE = 1 +}CONSOLE_OP_STAGE; + +#endif //_DIAG_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_pinmux.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_pinmux.h new file mode 100644 index 00000000000..e7dbe5fc3d9 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_pinmux.h @@ -0,0 +1,74 @@ +#ifndef _HAL_PINMUX_ +#define _HAL_PINMUX_ + + +//Function Index +#define UART0 0 +#define UART1 1 +#define UART2 2 +#define SPI0 8 +#define SPI1 9 +#define SPI2 10 +#define SPI0_MCS 15 +#define I2C0 16 +#define I2C1 17 +#define I2C2 18 +#define I2C3 19 +#define I2S0 24 +#define I2S1 25 +#define PCM0 28 +#define PCM1 29 +#define ADC0 32 +#define DAC0 36 +#define DAC1 37 +#define SDIOD 64 +#define SDIOH 65 +#define USBOTG 66 +#define MII 88 +#define WL_LED 96 +#define WL_ANT0 104 +#define WL_ANT1 105 +#define WL_BTCOEX 108 +#define WL_BTCMD 109 +#define NFC 112 +#define PWM0 160 +#define PWM1 161 +#define PWM2 162 +#define PWM3 163 +#define ETE0 164 +#define ETE1 165 +#define ETE2 166 +#define ETE3 167 +#define EGTIM 168 +#define SPI_FLASH 196 +#define SDR 200 +#define JTAG 216 +#define TRACE 217 +#define LOG_UART 220 +#define LOG_UART_IR 221 +#define SIC 224 +#define EEPROM 225 +#define DEBUG 226 + +//Location Index(Pin Mux Selection) +#define S0 0 +#define S1 1 +#define S2 2 +#define S3 3 + +_LONG_CALL_ u8 +HalPinCtrlRtl8195A( + IN u32 Function, + IN u32 PinLocation, + IN BOOL Operation); + +u8 GpioFunctionChk( + IN u32 chip_pin, + IN u8 Operation); + +u8 +FunctionChk( + IN u32 Function, + IN u32 PinLocation +); +#endif //_HAL_PINMUX_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_platform.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_platform.h new file mode 100644 index 00000000000..d0979d75373 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_platform.h @@ -0,0 +1,102 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _HAL_PLATFORM_ +#define _HAL_PLATFORM_ + +#define ROMVERSION 0x03 +#define ROMINFORMATION (ROMVERSION) + +#define SYSTEM_CLK PLATFORM_CLOCK + +#define SDR_SDRAM_BASE 0x30000000 +#define SYSTEM_CTRL_BASE 0x40000000 +#define PERI_ON_BASE 0x40000000 +#define VENDOR_REG_BASE 0x40002800 +#define SPI_FLASH_BASE 0x98000000 +#define SDR_CTRL_BASE 0x40005000 + +#define PERIPHERAL_IRQ_STATUS 0x04 +#define PERIPHERAL_IRQ_MODE 0x08 +#define PERIPHERAL_IRQ_EN 0x0C +#define LP_PERI_EXT_IRQ_STATUS 0x24 +#define LP_PERI_EXT_IRQ_MODE 0x28 +#define LP_PERI_EXT_IRQ_EN 0x2C + +#define PERIPHERAL_IRQ_ALL_LEVEL 0 + +#define TIMER_CLK 32*1000 + +//3 Peripheral IP Base Address +#define GPIO_REG_BASE 0x40001000 +#define TIMER_REG_BASE 0x40002000 +#define NFC_INTERFACE_BASE 0x40002400 +#define LOG_UART_REG_BASE 0x40003000 +#define I2C2_REG_BASE 0x40003400 +#define I2C3_REG_BASE 0x40003800 +#define SPI_FLASH_CTRL_BASE 0x40006000 +#define ADC_REG_BASE 0x40010000 +#define DAC_REG_BASE 0x40011000 +#define UART0_REG_BASE 0x40040000 +#define UART1_REG_BASE 0x40040400 +#define UART2_REG_BASE 0x40040800 +#define SPI0_REG_BASE 0x40042000 +#define SPI1_REG_BASE 0x40042400 +#define SPI2_REG_BASE 0x40042800 +#define I2C0_REG_BASE 0x40044000 +#define I2C1_REG_BASE 0x40044400 +#define SDIO_DEVICE_REG_BASE 0x40050000 +#define MII_REG_BASE 0x40050000 +#define SDIO_HOST_REG_BASE 0x40058000 +#define GDMA0_REG_BASE 0x40060000 +#define GDMA1_REG_BASE 0x40061000 +#define I2S0_REG_BASE 0x40062000 +#define I2S1_REG_BASE 0x40063000 +#define PCM0_REG_BASE 0x40064000 +#define PCM1_REG_BASE 0x40065000 +#define CRYPTO_REG_BASE 0x40070000 +#define WIFI_REG_BASE 0x40080000 +#define USB_OTG_REG_BASE 0x400C0000 + +#define GDMA1_REG_OFF 0x1000 +#define I2S1_REG_OFF 0x1000 +#define PCM1_REG_OFF 0x1000 +#define SSI_REG_OFF 0x400 +#define RUART_REG_OFF 0x400 + +#define CPU_CLK_TYPE_NO 6 + +enum _BOOT_TYPE_ { + BOOT_FROM_FLASH = 0, + BOOT_FROM_SDIO = 1, + BOOT_FROM_USB = 2, + BOOT_FROM_RSVD = 3, +}; + +enum _EFUSE_CPU_CLK_ { + #if 1 + CLK_200M = 0, + CLK_100M = 1, + CLK_50M = 2, + CLK_25M = 3, + CLK_12_5M = 4, + CLK_4M = 5, + #else + CLK_25M = 0, + CLK_200M = 1, + CLK_100M = 2, + CLK_50M = 3, + CLK_12_5M = 4, + CLK_4M = 5, + #endif +}; + + +#endif //_HAL_PLATFORM_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h new file mode 100644 index 00000000000..5bb99dd8d50 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_autoconf.h @@ -0,0 +1,217 @@ +/* + * Automatically generated by make menuconfig: don't edit + */ +#define AUTOCONF_INCLUDED + +/* + * Target Platform Selection + */ +#define CONFIG_WITHOUT_MONITOR 1 + +#undef CONFIG_RTL8195A +#define CONFIG_RTL8195A 1 +#undef CONFIG_FPGA +#undef CONFIG_RTL_SIM +#undef CONFIG_POST_SIM + +/* + * < Mass Production Option + */ +#undef CONFIG_MP +#undef CONFIG_CP +#undef CONFIG_FT +#define RTL8195A 1 +#define CONFIG_CPU_CLK 1 +#define CONFIG_CPU_166_6MHZ 1 +#undef CONFIG_CPU_83_3MHZ +#undef CONFIG_CPU_41_6MHZ +#undef CONFIG_CPU_20_8MHZ +#undef CONFIG_CPU_10_4MHZ +#undef CONFIG_CPU_4MHZ +#undef CONFIG_FPGA_CLK +#define PLATFORM_CLOCK (166666666) +#define CPU_CLOCK_SEL_VALUE (0) +#define CONFIG_SDR_CLK 1 +#define CONFIG_SDR_100MHZ 1 +#undef CONFIG_SDR_50MHZ +#undef CONFIG_SDR_25MHZ +#undef CONFIG_SDR_12_5MHZ +#define SDR_CLOCK_SEL_VALUE (0) +#define CONFIG_BOOT_PROCEDURE 1 +#define CONFIG_IMAGE_PAGE_LOAD 1 +#undef CONFIG_IMAGE_AUTO_LOAD +//#undef CONFIG_IMAGE_PAGE_LOAD +//#define CONFIG_IMAGE_AUTO_LOAD 1 +#define CONFIG_BOOT_TO_UPGRADE_IMG2 1 +#undef CONFIG_PERI_UPDATE_IMG +#define CONFIG_BOOT_FROM_JTAG 1 +#undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE +#define CONFIG_KERNEL 1 +#define PLATFORM_FREERTOS 1 +#undef PLATFORM_UCOSII +#undef PLATFORM_ECOS +#undef CONFIG_TASK_SCHEDUL_DIS +#define TASK_SCHEDULER_DISABLED (0) +#define CONFIG_NORMALL_MODE 1 +#undef CONFIG_MEMORY_VERIFY_MODE +#define CONFIG_TIMER_EN 1 +#define CONFIG_TIMER_NORMAL 1 +#undef CONFIG_TIMER_TEST +#define CONFIG_TIMER_MODULE 1 +#define CONFIG_WDG 1 +#undef CONFIG_WDG_NON +#define CONFIG_WDG_NORMAL 1 +#define CONFIG_GDMA_EN 1 +#define CONFIG_GDMA_NORMAL 1 +#undef CONFIG_GDMA_TEST +#define CONFIG_GDMA_MODULE 1 +#define CONFIG_WIFI_EN 1 +#define CONFIG_WIFI_NORMAL 1 +#undef CONFIG_WIFI_TEST +#define CONFIG_WIFI_MODULE 1 +#define CONFIG_GPIO_EN 1 +#define CONFIG_GPIO_NORMAL 1 +#undef CONFIG_GPIO_TEST +#define CONFIG_GPIO_MODULE 1 +#if defined(CONFIG_INIC) || (CONFIG_SDIOD) +#define CONFIG_SDIO_DEVICE_EN 1 +#define CONFIG_SDIO_DEVICE_NORMAL 1 +#undef CONFIG_SDIO_DEVICE_TEST +#define CONFIG_SDIO_DEVICE_MODULE 1 +#else +#undef CONFIG_SDIO_DEVICE_EN +#endif +#define CONFIG_SDIO_HOST_EN 1 +#define CONFIG_USB_EN 1 +#undef CONFIG_USB_NORMAL +#define CONFIG_USB_TEST 1 +#define CONFIG_USB_MODULE 1 +#define CONFIG_USB_VERIFY 1 +#undef CONFIG_USB_ROM_LIB +//#define CONFIG_USB_DBGINFO_EN 1 +#if defined(CONFIG_INIC) || (CONFIG_USBD) +#define DWC_DEVICE_ONLY 1 +#else +#define DWC_HOST_ONLY 1 +#define CONFIG_USB_HOST_ONLY 1 +#endif +#define CONFIG_SPI_COM_EN 1 +#define CONFIG_SPI_COM_NORMAL 1 +#undef CONFIG_SPI_COM_TEST +#define CONFIG_SPI_COM_MODULE 1 +#define CONFIG_UART_EN 1 +#define CONFIG_UART_NORMAL 1 +#undef CONFIG_UART_TEST +#define CONFIG_UART_MODULE 1 +#define CONFIG_I2C_EN 1 +#define CONFIG_I2C_NORMAL 1 +#undef CONFIG_I2C_TEST +#define CONFIG_I2C_MODULE 1 +#undef CONFIG_DEBUG_LOG_I2C_HAL +#undef CONFIG_PCM_EN +#undef CONFIG_I2S_EN +#undef CONFIG_I2S_NORMAL +#undef CONFIG_I2S_TEST +#undef CONFIG_I2S_MODULE +#undef CONFIG_DEBUG_LOG_I2S_HAL +#undef CONFIG_NFC_EN +#undef CONFIG_NFC_NORMAL +#undef CONFIG_NFC_TEST +#undef CONFIG_NFC_MODULE +#define CONFIG_SOC_PS_EN 1 +#define CONFIG_SOC_PS_NORMAL 1 +#undef CONFIG_SOC_PS_TEST +//#define CONFIG_SOC_PS_MODULE 1 +#define CONFIG_CRYPTO_EN 1 +#define CONFIG_CRYPTO_NORMAL 1 +#undef CONFIG_CRYPTO_TEST +#define CONFIG_CRYPTO_MODULE 1 +#define CONFIG_MII_EN 1 +#define CONFIG_PWM_EN 1 +#define CONFIG_PWM_NORMAL 1 +#undef CONFIG_PWM_TEST +#define CONFIG_PWM_MODULE 1 +#define CONFIG_EFUSE_EN 1 +#define CONFIG_EFUSE_NORMAL 1 +#undef CONFIG_EFUSE_TEST +#define CONFIG_EFUSE_MODULE 1 +#define CONFIG_SDR_EN 1 +#define CONFIG_SDR_NORMAL 1 +#undef CONFIG_SDR_TEST +#define CONFIG_SDR_MODULE 1 +#define CONFIG_SPIC_EN 1 +#define CONFIG_SPIC_NORMAL 1 +#undef CONFIG_SPIC_TEST +#define CONFIG_SPIC_MODULE 1 +#define CONFIG_ADC_EN 1 +#define CONFIG_DAC_EN 1 +#define CONFIG_NOR_FLASH 1 +#undef CONFIG_SPI_FLASH +#undef CONFIG_NAND_FLASH +#undef CONFIG_NONE_FLASH +#undef CONFIG_BTBX_EN + +/* + * < Engineer Mode Config + */ +#undef CONFIG_JTAG +#undef CONFIG_COMPILE_FLASH_DOWNLOAD_CODE +#undef CONIFG_COMPILE_EXTERNAL_SRAM_CALIBRATE +#undef CONFIG_CMSIS_MATH_LIB_EN + +/* + * < Application Config + */ +#define CONFIG_NETWORK 1 +#define CONFIG_RTLIB_EN 1 +#define CONFIG_RTLIB_NORMAL 1 +#undef CONFIG_RTLIB_TEST +#define CONFIG_RTLIB_MODULE 1 + +/* + * < System Debug Message Config + */ +#define CONFIG_UART_LOG_HISTORY 1 +#undef CONFIG_CONSOLE_NORMALL_MODE +#define CONFIG_CONSOLE_VERIFY_MODE 1 +#define CONFIG_DEBUG_LOG 1 +#define CONFIG_DEBUG_ERR_MSG 1 +#undef CONFIG_DEBUG_WARN_MSG +#undef CONFIG_DEBUG_INFO_MSG + +/* + * < SDK Option Config + */ +//#undef CONFIG_MBED_ENABLED +#ifdef CONFIG_MBED_ENABLED +#undef PLATFORM_FREERTOS +#define PLATFORM_CMSIS_RTOS 1 +#endif +#undef CONFIG_APP_DEMO + +/* + * < Select Chip Version + */ +#undef CONFIG_CHIP_A_CUT +#define CONFIG_CHIP_B_CUT 1 +#undef CONFIG_CHIP_C_CUT +#undef CONFIG_CHIP_E_CUT + +/* + * < Select toolchain + */ +#undef CONFIG_TOOLCHAIN_ASDK +#undef CONFIG_TOOLCHAIN_ARM_GCC + +/* + * < Build Option + */ +#define CONFIG_LINK_ROM_LIB 1 +#undef CONFIG_LINK_ROM_SYMB +#undef CONFIG_NORMAL_BUILD +#undef CONFIG_RELEASE_BUILD +#undef CONFIG_RELEASE_BUILD_LIBRARIES +#undef CONFIG_LIB_BUILD_RAM +#define CONFIG_RELEASE_BUILD_RAM_ALL 1 +#undef CONFIG_IMAGE_ALL +#define CONFIG_IMAGE_SEPARATE 1 diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rand.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rand.h new file mode 100644 index 00000000000..47ac51e0b65 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rand.h @@ -0,0 +1,15 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +u32 +Rand ( + VOID +); + + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h new file mode 100644 index 00000000000..5eb92993e57 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h @@ -0,0 +1,286 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ +#ifndef _HAL_8195A_H_ +#define _HAL_8195A_H_ + +#include "platform_autoconf.h" +#include "basic_types.h" +#include "section_config.h" +#include "rtl8195a_sys_on.h" +#include "rtl8195a_peri_on.h" +#include "hal_platform.h" +#include "hal_pinmux.h" +#include "hal_api.h" +#include "hal_peri_on.h" +#include "hal_misc.h" +#include "hal_irqn.h" +#include "hal_vector_table.h" +#include "hal_diag.h" +#include "hal_spi_flash.h" +#include "rtl8195a_spi_flash.h" +//#include "hal_timer.h" +#include "hal_util.h" +#include "hal_efuse.h" +#include "hal_soc_ps_monitor.h" +#include "diag.h" +//#include "hal_common.h" +//#include "hal_soc_ps_monitor.h" + + +// from RDC team +#ifdef CONFIG_MBED_ENABLED +// Add for Mbed -OS +#include +#include +#include + +#include "rtl8195a_compiler.h" +#include "rtl8195a_platform.h" + + + +#define REG32(reg) (*(volatile uint32_t *)(reg)) +#define REG16(reg) (*(volatile uint16_t *)(reg)) +#define REG08(reg) (*(volatile uint8_t *)(reg)) + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) +#define ABS(x) ((x > 0) ? x : -x) +#define MAX(x,y) ((x) < (y) ? (y) : (x)) +#ifndef MIN +#define MIN(x,y) ((x) > (y) ? (y) : (x)) +#endif + +#define __RTK_READ32(B,A) (REG32((B) + (A))) +#define __RTK_READ16(B,A) (REG16((B) + (A))) +#define __RTK_READ08(B,A) (REG08((B) + (A))) +#define __RTK_WRITE32(B,A,V) (REG32((B) + (A)) = (V)) +#define __RTK_WRITE16(B,A,V) (REG32((B) + (A)) = (V)) +#define __RTK_WRITE08(B,A,V) (REG32((B) + (A)) = (V)) + +#define __RTK_SETBIT(A,V) (REG32(A) |= V) +#define __RTK_CLRBIT(A,V) (REG32(A) &= ~V) +#define __RTK_SETMSK(A,M,V) (REG32(A) = ((REG32(A) & (~M)) | V)) + +#define PERI_BASE 0x40000000 + +#define __BUILD_MACRO(name,ctrl) \ +static inline uint32_t \ +__##name##_READ32(uint32_t addr) \ +{ \ + return __RTK_READ32(ctrl##_BASE,addr); \ +} \ +static inline uint16_t \ +__##name##_READ16(uint32_t addr) \ +{ \ + return __RTK_READ16(ctrl##_BASE,addr); \ +} \ +static inline uint8_t \ +__##name##_READ08(uint32_t addr) \ +{ \ + return __RTK_READ08(ctrl##_BASE,addr); \ +} \ +static inline void \ +__##name##_WRITE32(uint32_t addr, uint32_t val) \ +{ \ + __RTK_WRITE32(ctrl##_BASE,addr,val); \ +} \ +static inline void \ +__##name##_WRITE16(uint32_t addr, uint16_t val) \ +{ \ + __RTK_WRITE16(ctrl##_BASE,addr,val); \ +} \ +static inline void \ +__##name##_WRITE08(uint32_t addr, uint8_t val) \ +{ \ + __RTK_WRITE08(ctrl##_BASE,addr,val); \ +} \ +static inline void \ +__##name##_SETBIT(uint32_t addr, uint32_t val) \ +{ \ + __RTK_SETBIT(ctrl##_BASE+addr,val); \ +} \ +static inline void \ +__##name##_CLRBIT(uint32_t addr, uint32_t val) \ +{ \ + __RTK_CLRBIT(ctrl##_BASE+addr,val); \ +} \ +static inline void \ +__##name##_SETMSK(uint32_t addr, uint32_t msk, uint32_t val) \ +{ \ + __RTK_SETMSK(ctrl##_BASE+addr,msk,val); \ +} \ + +//__BUILD_MACRO(RTK_CTRL, CTRL) +//__BUILD_MACRO(RTK_PERI, PERI) +//__BUILD_MACRO(RTK_VENDOR, VENDOR) +//__BUILD_MACRO(RTK_SDRC, SDRC) + +__BUILD_MACRO(RTK_CTRL, SYSTEM_CTRL) +__BUILD_MACRO(RTK_PERI, PERI) +__BUILD_MACRO(RTK_SDRC, SDR_CTRL) +__BUILD_MACRO(RTK_VENDOR, VENDOR_REG) + + +#define __BUILD_FCTRL_MACRO(name,ctrl) \ +static inline void \ +__##name##_Enable(void) \ +{ \ + __RTK_PERI_SETBIT(ctrl, BIT_FCTRL_##name); \ +} \ +static inline void \ +__##name##_Disable(void) \ +{ \ + __RTK_READ32(name##_BASE, 0); \ + __RTK_PERI_CLRBIT(ctrl, BIT_FCTRL_##name); \ +} + + + +#include "rtl8195a_trap.h" +#include "rtl8195a_clk.h" +#include "rtl8195a_misc.h" +#include "rtl8195a_sdio.h" +//#include "rtl8195a_luart.h" + +#endif + + +/* ---------------------------------------------------------------------------- + -- Cortex M3 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration + * @{ + */ + +#define __CM3_REV 0x0200 /**< Core revision r0p0 */ +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm3.h" + +#ifdef CONFIG_TIMER_EN +#include "hal_timer.h" +#endif + +#ifdef CONFIG_GDMA_EN +#include "hal_gdma.h" +#include "rtl8195a_gdma.h" +#endif + +#ifdef CONFIG_GPIO_EN +#include "hal_gpio.h" +#include "rtl8195a_gpio.h" +#endif + +#ifdef CONFIG_SPI_COM_EN +#include "hal_ssi.h" +#include "rtl8195a_ssi.h" +#endif + +#ifdef CONFIG_UART_EN +#include "hal_uart.h" +#include "rtl8195a_uart.h" +#endif + +#ifdef CONFIG_I2C_EN +#include "hal_i2c.h" +#include "rtl8195a_i2c.h" +#endif + +//#ifdef CONFIG_PCM_EN +//#include "hal_pcm.h" +//#include "rtl8195a_pcm.h" +//#endif + +#ifdef CONFIG_PWM_EN +#include "hal_pwm.h" +#include "rtl8195a_pwm.h" +#endif + +#ifdef CONFIG_I2S_EN +#include "hal_i2s.h" +#include "rtl8195a_i2s.h" +#endif + +#ifdef CONFIG_DAC_EN +#include "hal_dac.h" +#include "rtl8195a_dac.h" +#endif + +#ifdef CONFIG_ADC_EN +#include "hal_adc.h" +#include "rtl8195a_adc.h" +#endif + +#ifdef CONFIG_SDR_EN +#endif + +#ifdef CONFIG_SPIC_EN +#endif + +#ifdef CONFIG_SDIO_DEVICE_EN +//#include "hal_sdio.h" +#endif + +#ifdef CONFIG_NFC_EN +//#include "hal_nfc.h" +//#include "rtl8195a_nfc.h" +#endif + +#ifdef CONFIG_WDG +#include "rtl8195a_wdt.h" +#endif + +#ifdef CONFIG_USB_EN +//#include "hal_usb.h" +//#include "rtl8195a_usb.h" +#endif + +#include "hal_log_uart.h" + +#ifdef CONFIG_MII_EN +//#include "hal_mii.h" +//#include "rtl8195a_mii.h" +#endif + +// firmware information, located at the header of Image2 +#define FW_VERSION (0x0100) +#define FW_SUBVERSION (0x0001) +#define FW_CHIP_ID (0x8195) +#define FW_CHIP_VER (0x01) +#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO +#define FW_INFO_RSV1 (0x00) // the firmware information reserved +#define FW_INFO_RSV2 (0x00) // the firmware information reserved +#define FW_INFO_RSV3 (0x00) // the firmware information reserved +#define FW_INFO_RSV4 (0x00) // the firmware information reserved + +#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1 +#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data +// Flash Map for Calibration data +#define FLASH_CAL_DATA_BASE 0xA000 +#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset) +#define FLASH_CAL_DATA_SIZE 0x1000 +#define FLASH_SECTOR_SIZE 0x1000 +// SPIC Calibration Data +#define FLASH_SPIC_PARA_OFFSET 0x80 +#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET) +// SDRC Calibration Data +#define FLASH_SDRC_PARA_OFFSET 0x180 +#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET) +// ADC Calibration Data +#define FLASH_ADC_PARA_OFFSET 0x200 +#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET) + +#endif //_HAL_8195A_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_adc.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_adc.h new file mode 100644 index 00000000000..48240b09332 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_adc.h @@ -0,0 +1,350 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_ADC_H_ +#define _RTL8195A_ADC_H_ + + +//================ Register Bit Field ========================== +//2 REG_ADC_FIFO_READ + +#define BIT_SHIFT_ADC_FIFO_RO 0 +#define BIT_MASK_ADC_FIFO_RO 0xffffffffL +#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO) +#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO) +#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO) + + +//2 REG_ADC_CONTROL + +#define BIT_SHIFT_ADC_DBG_SEL 24 +#define BIT_MASK_ADC_DBG_SEL 0x7 +#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL) +#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL) +#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL) + + +#define BIT_SHIFT_ADC_THRESHOLD 16 +#define BIT_MASK_ADC_THRESHOLD 0x3f +#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD) +#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD) +#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD) + + +#define BIT_SHIFT_ADC_BURST_SIZE 8 +#define BIT_MASK_ADC_BURST_SIZE 0x1f +#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE) +#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE) +#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE) + +#define BIT_ADC_ENDIAN BIT(3) +#define BIT_SHIFT_ADC_ENDIAN 3 +#define BIT_MASK_ADC_ENDIAN 0x1 +#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN) + +#define BIT_ADC_OVERWRITE BIT(2) +#define BIT_SHIFT_ADC_OVERWRITE 2 +#define BIT_MASK_ADC_OVERWRITE 0x1 +#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE) + +#define BIT_ADC_ONESHOT BIT(1) +#define BIT_SHIFT_ADC_ONESHOT 1 +#define BIT_MASK_ADC_ONESHOT 0x1 +#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT) + +#define BIT_ADC_COMP_ONLY BIT(0) +#define BIT_SHIFT_ADC_COMP_ONLY 0 +#define BIT_MASK_ADC_COMP_ONLY 0x1 +#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY) + + +//2 REG_ADC_INTR_EN +#define BIT_ADC_AWAKE_CPU_EN BIT(7) +#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7 +#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1 +#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN) + +#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6) +#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6 +#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1 +#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN) + +#define BIT_ADC_FIFO_RD_REQ_EN BIT(5) +#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5 +#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1 +#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN) + +#define BIT_ADC_FIFO_FULL_EN BIT(4) +#define BIT_SHIFT_ADC_FIFO_FULL_EN 4 +#define BIT_MASK_ADC_FIFO_FULL_EN 0x1 +#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN) + +#define BIT_ADC_COMP_3_EN BIT(3) +#define BIT_SHIFT_ADC_COMP_3_EN 3 +#define BIT_MASK_ADC_COMP_3_EN 0x1 +#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN) + +#define BIT_ADC_COMP_2_EN BIT(2) +#define BIT_SHIFT_ADC_COMP_2_EN 2 +#define BIT_MASK_ADC_COMP_2_EN 0x1 +#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN) + +#define BIT_ADC_COMP_1_EN BIT(1) +#define BIT_SHIFT_ADC_COMP_1_EN 1 +#define BIT_MASK_ADC_COMP_1_EN 0x1 +#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN) + +#define BIT_ADC_COMP_0_EN BIT(0) +#define BIT_SHIFT_ADC_COMP_0_EN 0 +#define BIT_MASK_ADC_COMP_0_EN 0x1 +#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN) + + +//2 REG_ADC_INTR_STS +#define BIT_ADC_FIFO_THRESHOLD BIT(7) +#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7 +#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1 +#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD) + +#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6) +#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6 +#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1 +#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST) + +#define BIT_ADC_FIFO_RD_REQ_ST BIT(5) +#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5 +#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1 +#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST) + +#define BIT_ADC_FIFO_FULL_ST BIT(4) +#define BIT_SHIFT_ADC_FIFO_FULL_ST 4 +#define BIT_MASK_ADC_FIFO_FULL_ST 0x1 +#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST) + +#define BIT_ADC_COMP_3_ST BIT(3) +#define BIT_SHIFT_ADC_COMP_3_ST 3 +#define BIT_MASK_ADC_COMP_3_ST 0x1 +#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST) + +#define BIT_ADC_COMP_2_ST BIT(2) +#define BIT_SHIFT_ADC_COMP_2_ST 2 +#define BIT_MASK_ADC_COMP_2_ST 0x1 +#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST) + +#define BIT_ADC_COMP_1_ST BIT(1) +#define BIT_SHIFT_ADC_COMP_1_ST 1 +#define BIT_MASK_ADC_COMP_1_ST 0x1 +#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST) + +#define BIT_ADC_COMP_0_ST BIT(0) +#define BIT_SHIFT_ADC_COMP_0_ST 0 +#define BIT_MASK_ADC_COMP_0_ST 0x1 +#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST) + + +//2 REG_ADC_COMP_VALUE_L + +#define BIT_SHIFT_ADC_COMP_TH_1 16 +#define BIT_MASK_ADC_COMP_TH_1 0xffff +#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1) +#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1) +#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1) + + +#define BIT_SHIFT_ADC_COMP_TH_0 0 +#define BIT_MASK_ADC_COMP_TH_0 0xffff +#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0) +#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0) +#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0) + + +//2 REG_ADC_COMP_VALUE_H + +#define BIT_SHIFT_ADC_COMP_TH_3 16 +#define BIT_MASK_ADC_COMP_TH_3 0xffff +#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3) +#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3) +#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3) + + +#define BIT_SHIFT_ADC_COMP_TH_2 0 +#define BIT_MASK_ADC_COMP_TH_2 0xffff +#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2) +#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2) +#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2) + + +//2 REG_ADC_COMP_SET + +#define BIT_SHIFT_ADC_GREATER_THAN 0 +#define BIT_MASK_ADC_GREATER_THAN 0xf +#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN) +#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN) +#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN) + + +//2 REG_ADC_POWER + +#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16 +#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff +#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR) +#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR) +#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR) + +#define BIT_ADC_FIFO_ON_ST BIT(11) +#define BIT_SHIFT_ADC_FIFO_ON_ST 11 +#define BIT_MASK_ADC_FIFO_ON_ST 0x1 +#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST) + +#define BIT_ADC_ISO_ON_ST BIT(10) +#define BIT_SHIFT_ADC_ISO_ON_ST 10 +#define BIT_MASK_ADC_ISO_ON_ST 0x1 +#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST) + +#define BIT_ADC_PWR33_ON_ST BIT(9) +#define BIT_SHIFT_ADC_PWR33_ON_ST 9 +#define BIT_MASK_ADC_PWR33_ON_ST 0x1 +#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST) + +#define BIT_ADC_PWR12_ON_ST BIT(8) +#define BIT_SHIFT_ADC_PWR12_ON_ST 8 +#define BIT_MASK_ADC_PWR12_ON_ST 0x1 +#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST) + +#define BIT_ADC_ISO_MANUAL BIT(3) +#define BIT_SHIFT_ADC_ISO_MANUAL 3 +#define BIT_MASK_ADC_ISO_MANUAL 0x1 +#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL) + +#define BIT_ADC_PWR33_MANUAL BIT(2) +#define BIT_SHIFT_ADC_PWR33_MANUAL 2 +#define BIT_MASK_ADC_PWR33_MANUAL 0x1 +#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL) + +#define BIT_ADC_PWR12_MANUAL BIT(1) +#define BIT_SHIFT_ADC_PWR12_MANUAL 1 +#define BIT_MASK_ADC_PWR12_MANUAL 0x1 +#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL) + +#define BIT_ADC_PWR_AUTO BIT(0) +#define BIT_SHIFT_ADC_PWR_AUTO 0 +#define BIT_MASK_ADC_PWR_AUTO 0x1 +#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO) + + +//2 REG_ADC_ANAPAR_AD0 + +#define BIT_SHIFT_ADC_ANAPAR_AD0 2 +#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff +#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0) +#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0) +#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0) + +#define BIT_ADC_AUDIO_EN BIT(1) +#define BIT_SHIFT_ADC_AUDIO_EN 1 +#define BIT_MASK_ADC_AUDIO_EN 0x1 +#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN) + +#define BIT_ADC_EN_MANUAL BIT(0) +#define BIT_SHIFT_ADC_EN_MANUAL 0 +#define BIT_MASK_ADC_EN_MANUAL 0x1 +#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL) + + +//2 REG_ADC_ANAPAR_AD1 + +#define BIT_SHIFT_ADC_ANAPAR_AD1 0 +#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL +#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1) +#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1) +#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1) + + +//2 REG_ADC_ANAPAR_AD2 + +#define BIT_SHIFT_ADC_ANAPAR_AD2 0 +#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL +#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2) +#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2) +#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2) + + +//2 REG_ADC_ANAPAR_AD3 + +#define BIT_SHIFT_ADC_ANAPAR_AD3 0 +#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL +#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3) +#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3) +#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3) + + +//2 REG_ADC_ANAPAR_AD4 + +#define BIT_SHIFT_ADC_ANAPAR_AD4 0 +#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL +#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4) +#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4) +#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4) + + +//2 REG_ADC_ANAPAR_AD5 + +#define BIT_SHIFT_ADC_ANAPAR_AD5 0 +#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL +#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5) +#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5) +#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5) + + +//2 REG_ADC_CALI_DATA + +#define BIT_SHIFT_ADC_CALI_DATA_6 16 +#define BIT_MASK_ADC_CALI_DATA_6 0xffff +#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6) +#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6) +#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6) + + +#define BIT_SHIFT_ADC_CALI_DATA_0 0 +#define BIT_MASK_ADC_CALI_DATA_0 0xffff +#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0) +#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0) +#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0) + +//================ Register Reg Field ========================= +#define REG_ADC_FIFO_READ 0x0000 +#define REG_ADC_CONTROL 0x0004 +#define REG_ADC_INTR_EN 0x0008 +#define REG_ADC_INTR_STS 0x000C +#define REG_ADC_COMP_VALUE_L 0x0010 +#define REG_ADC_COMP_VALUE_H 0x0014 +#define REG_ADC_COMP_SET 0x0018 +#define REG_ADC_POWER 0x001C +#define REG_ADC_ANAPAR_AD0 0x0020 +#define REG_ADC_ANAPAR_AD1 0x0024 +#define REG_ADC_ANAPAR_AD2 0x0028 +#define REG_ADC_ANAPAR_AD3 0x002C +#define REG_ADC_ANAPAR_AD4 0x0030 +#define REG_ADC_ANAPAR_AD5 0x0034 +#define REG_ADC_CALI_DATA 0x0038 + +//================ ADC HAL related enumeration ================== + +//================ ADC Function Prototypes ===================== +#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value) +#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr) + +RTK_STATUS HalADCInit8195a(IN VOID *Data); +RTK_STATUS HalADCDeInit8195a(IN VOID *Data); +RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data); +RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data); +u32 HalADCReceiveRtl8195a(IN VOID *Data); +u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg); + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_clk.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_clk.h new file mode 100644 index 00000000000..cb97516dbed --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_clk.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_RTL8195A_CLK_H +#define MBED_RTL8195A_CLK_H + +#define PLATFORM_CLK (200000000UL/6*5) // 166MHz +//#define SYSTEM_CLK PLATFORM_CLK +//#define TIMER_CLK (32*1000) + +#define __BUILD_CCTRL_MACRO(name,ctrl) \ +static inline void \ +__##name##_ACTCK_Enable(void) \ +{ \ + __RTK_PERI_SETBIT(ctrl, BIT_ACTCK_##name); \ +} \ +static inline void \ +__##name##_SLPCK_Enable(void) \ +{ \ + __RTK_PERI_SETBIT(ctrl, BIT_SLPCK_##name); \ +} \ +static inline void \ +__##name##_ACTCK_Disable(void) \ +{ \ + __RTK_PERI_CLRBIT(ctrl, BIT_ACTCK_##name); \ +} \ +static inline void \ +__##name##_SLPCK_Disable(void) \ +{ \ + __RTK_PERI_CLRBIT(ctrl, BIT_SLPCK_##name); \ +} \ + +//enum clk_idx { +// CLK_ANACK = 0, +// CLK_A33CK = 1, +//}; + +// Interface to ROM functions +extern __longcall uint32_t HalGetCpuClk(void); + +#define __CLK_GetCPUClk HalGetCpuClk + +// Interface for HAL functions +static inline uint32_t CLK_GetCPUClk(void) +{ + return __CLK_GetCPUClk(); +} + +extern void CLK_BackupCPUClk(void); +extern void CLK_ReFillCPUClk(void); +extern uint32_t CLK_Calculate(uint8_t clksel); + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h new file mode 100644 index 00000000000..0f8e9f9bc82 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_RTL8195A_COMPILER_H +#define MBED_RTL8195A_COMPILER_H + +#if defined (__ICCARM__) +#ifndef STRINGIFY +#define STRINGIFY(s) #s +#endif +#ifndef SECTION +#define SECTION(_name) _Pragma( STRINGIFY(location=##_name##)) +#endif +#ifndef ALIGNMTO +#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=##_bound##)) +#endif +#define __romcall +#define __longcall + +#elif defined(__CC_ARM) + +#ifndef __longcall +#define __longcall __attribute__ ((long_call)) +#endif + +#else +#define SECTION(_name) __attribute__ ((__section__(_name))) +#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound))) + +#ifndef __packed +#define __packed __attribute__ ((packed)) +#endif + +#ifndef __romcall +#define __romcall __attribute__ ((long_call)) +#endif +#ifndef __longcall +#define __longcall __attribute__ ((long_call)) +#endif +#ifndef __weak +#define __weak __attribute__ ((weak)) +#endif + +#endif + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_dac.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_dac.h new file mode 100644 index 00000000000..c3a9861d1b3 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_dac.h @@ -0,0 +1,294 @@ +#ifndef _RTL8195A_DAC_H_ +#define _RTL8195A_DAC_H_ + +//================ Register Bit Field ========================== +//2 REG_DAC0_FIFO_WR + +#define BIT_SHIFT_DAC0_FIFO_WO 0 +#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL +#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) +#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) +#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO) + + +//2 REG_DAC_CTRL + +#define BIT_SHIFT_DAC_DELTA_SIGMA 25 +#define BIT_MASK_DAC_DELTA_SIGMA 0x7 +#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) +#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) +#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA) + +#define BIT_DAC_BYPASS_DSC BIT(24) +#define BIT_SHIFT_DAC_BYPASS_DSC 24 +#define BIT_MASK_DAC_BYPASS_DSC 0x1 +#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC) + + +#define BIT_SHIFT_DAC_DSC_DBG_SEL 19 +#define BIT_MASK_DAC_DSC_DBG_SEL 0x3 +#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) +#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) +#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL) + + +#define BIT_SHIFT_DAC_DBG_SEL 16 +#define BIT_MASK_DAC_DBG_SEL 0x7 +#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) +#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) +#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL) + + +#define BIT_SHIFT_DAC_BURST_SIZE 8 +#define BIT_MASK_DAC_BURST_SIZE 0xf +#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) +#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) +#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE) + +#define BIT_DAC_FILTER_SETTLE BIT(4) +#define BIT_SHIFT_DAC_FILTER_SETTLE 4 +#define BIT_MASK_DAC_FILTER_SETTLE 0x1 +#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE) + +#define BIT_DAC_OV_OPTION BIT(3) +#define BIT_SHIFT_DAC_OV_OPTION 3 +#define BIT_MASK_DAC_OV_OPTION 0x1 +#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION) + +#define BIT_DAC_ENDIAN BIT(2) +#define BIT_SHIFT_DAC_ENDIAN 2 +#define BIT_MASK_DAC_ENDIAN 0x1 +#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN) + +#define BIT_DAC_SPEED BIT(1) +#define BIT_SHIFT_DAC_SPEED 1 +#define BIT_MASK_DAC_SPEED 0x1 +#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED) + +#define BIT_DAC_FIFO_EN BIT(0) +#define BIT_SHIFT_DAC_FIFO_EN 0 +#define BIT_MASK_DAC_FIFO_EN 0x1 +#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN) + + +//2 REG_DAC_INTR_CTRL +#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6) +#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6 +#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN) + +#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5) +#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5 +#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN) + +#define BIT_DAC__WRITE_ERROR_EN BIT(4) +#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4 +#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1 +#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN) + +#define BIT_DAC_FIFO_STOP_EN BIT(3) +#define BIT_SHIFT_DAC_FIFO_STOP_EN 3 +#define BIT_MASK_DAC_FIFO_STOP_EN 0x1 +#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN) + +#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2) +#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2 +#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1 +#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN) + +#define BIT_DAC_FIFO_WR_REQ_EN BIT(1) +#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1 +#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1 +#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN) + +#define BIT_DAC_FIFO_FULL_EN BIT(0) +#define BIT_SHIFT_DAC_FIFO_FULL_EN 0 +#define BIT_MASK_DAC_FIFO_FULL_EN 0x1 +#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN) + + +//2 REG_DAC_INTR_STS +#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6) +#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6 +#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST) + +#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5) +#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5 +#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST) + +#define BIT_DAC__WRITE_ERROR_ST BIT(4) +#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4 +#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1 +#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST) + +#define BIT_DAC_FIFO_STOP_ST BIT(3) +#define BIT_SHIFT_DAC_FIFO_STOP_ST 3 +#define BIT_MASK_DAC_FIFO_STOP_ST 0x1 +#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST) + +#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2) +#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2 +#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1 +#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST) + +#define BIT_DAC_FIFO_WR_REQ_ST BIT(1) +#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1 +#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1 +#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST) + +#define BIT_DAC_FIFO_FULL_ST BIT(0) +#define BIT_SHIFT_DAC_FIFO_FULL_ST 0 +#define BIT_MASK_DAC_FIFO_FULL_ST 0x1 +#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST) + + +//2 REG_DAC_PWR_CTRL + +#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16 +#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff +#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) +#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) +#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR) + +#define BIT_ST_DAC_FIFO_ON BIT(11) +#define BIT_SHIFT_ST_DAC_FIFO_ON 11 +#define BIT_MASK_ST_DAC_FIFO_ON 0x1 +#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON) + +#define BIT_ST_DAC_ISO_ON BIT(10) +#define BIT_SHIFT_ST_DAC_ISO_ON 10 +#define BIT_MASK_ST_DAC_ISO_ON 0x1 +#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON) + +#define BIT_ST_DAC_PWR33_ON BIT(9) +#define BIT_SHIFT_ST_DAC_PWR33_ON 9 +#define BIT_MASK_ST_DAC_PWR33_ON 0x1 +#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON) + +#define BIT_ST_DAC_PWR12_ON BIT(8) +#define BIT_SHIFT_ST_DAC_PWR12_ON 8 +#define BIT_MASK_ST_DAC_PWR12_ON 0x1 +#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON) + +#define BIT_DAC_ISO_MANU BIT(3) +#define BIT_SHIFT_DAC_ISO_MANU 3 +#define BIT_MASK_DAC_ISO_MANU 0x1 +#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU) + +#define BIT_DAC_PWR33_MANU BIT(2) +#define BIT_SHIFT_DAC_PWR33_MANU 2 +#define BIT_MASK_DAC_PWR33_MANU 0x1 +#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU) + +#define BIT_DAC_PWR12_MANU BIT(1) +#define BIT_SHIFT_DAC_PWR12_MANU 1 +#define BIT_MASK_DAC_PWR12_MANU 0x1 +#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU) + +#define BIT_DAC_PWR_AUTO BIT(0) +#define BIT_SHIFT_DAC_PWR_AUTO 0 +#define BIT_MASK_DAC_PWR_AUTO 0x1 +#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO) + + +//2 REG_DAC_ANAPAR_DA0 + +#define BIT_SHIFT_PWR_ALL_CNTR 12 +#define BIT_MASK_PWR_ALL_CNTR 0xfffff +#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) +#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) +#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR) + + +#define BIT_SHIFT_PWR_FUP_CNTR 0 +#define BIT_MASK_PWR_FUP_CNTR 0xfff +#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) +#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) +#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR) + + +//2 REG_DAC_ANAPAR_DA1 +#define BIT_FUP_EN BIT(31) +#define BIT_SHIFT_FUP_EN 31 +#define BIT_MASK_FUP_EN 0x1 +#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN) + + +#define BIT_SHIFT_ANAPAR_DA 8 +#define BIT_MASK_ANAPAR_DA 0x7fffff +#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) +#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) +#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA) + +#define BIT_D_POW_DACVREF BIT(7) +#define BIT_SHIFT_D_POW_DACVREF 7 +#define BIT_MASK_D_POW_DACVREF 0x1 +#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF) + +#define BIT_D_POW_VREF2 BIT(6) +#define BIT_SHIFT_D_POW_VREF2 6 +#define BIT_MASK_D_POW_VREF2 0x1 +#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2) + +#define BIT_D_POW_MBIAS BIT(5) +#define BIT_SHIFT_D_POW_MBIAS 5 +#define BIT_MASK_D_POW_MBIAS 0x1 +#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS) + +#define BIT_D_POW_DIV4 BIT(4) +#define BIT_SHIFT_D_POW_DIV4 4 +#define BIT_MASK_D_POW_DIV4 0x1 +#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4) + +#define BIT_D_POW_DF1SE_R BIT(3) +#define BIT_SHIFT_D_POW_DF1SE_R 3 +#define BIT_MASK_D_POW_DF1SE_R 0x1 +#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R) + +#define BIT_D_POW_DF2SE_L BIT(2) +#define BIT_SHIFT_D_POW_DF2SE_L 2 +#define BIT_MASK_D_POW_DF2SE_L 0x1 +#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L) + +#define BIT_D_POW_DAC_R BIT(1) +#define BIT_SHIFT_D_POW_DAC_R 1 +#define BIT_MASK_D_POW_DAC_R 0x1 +#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R) + +#define BIT_D_POW_DAC_L BIT(0) +#define BIT_SHIFT_D_POW_DAC_L 0 +#define BIT_MASK_D_POW_DAC_L 0x1 +#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L) + + +//================ Register Reg Field ========================= +#define REG_DAC0_FIFO_WR 0x0000 +#define REG_DAC_CTRL 0x0004 +#define REG_DAC_INTR_CTRL 0x0008 +#define REG_DAC_INTR_STS 0x000C +#define REG_DAC_PWR_CTRL 0x0010 +#define REG_DAC_ANAPAR_DA0 0x0014 +#define REG_DAC_ANAPAR_DA1 0x0018 + + +//================ DAC HAL related enumeration ================== + + +//================ DAC HAL Macro =========================== +#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \ + ,addr,value) +#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr) + + +//================ DAC Function Prototypes ===================== +RTK_STATUS HalDACInit8195a(IN VOID *Data); +RTK_STATUS HalDACDeInit8195a(IN VOID *Data); +RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data); +RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data); +u8 HalDACSendRtl8195a(IN VOID *Data); +u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg); + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h new file mode 100644 index 00000000000..b384942cef9 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h @@ -0,0 +1,528 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_GDMA_H_ +#define _RTL8195A_GDMA_H_ + +// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1 +// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL +#define GDMA_HANDSHAKE_UART0_TX 0 +#define GDMA_HANDSHAKE_UART0_RX 1 +#define GDMA_HANDSHAKE_UART1_TX 2 +#define GDMA_HANDSHAKE_UART1_RX 3 +#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed +#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed + +#define GDMA_HANDSHAKE_SSI0_TX 4 +#define GDMA_HANDSHAKE_SSI0_RX 5 +#define GDMA_HANDSHAKE_SSI1_TX 6 +#define GDMA_HANDSHAKE_SSI1_RX 7 +#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed +#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed + +#define GDMA_HANDSHAKE_I2C0_TX 8 +#define GDMA_HANDSHAKE_I2C0_RX 9 +#define GDMA_HANDSHAKE_I2C1_TX 10 +#define GDMA_HANDSHAKE_I2C1_RX 11 + +#define GDMA_HANDSHAKE_ADC 12 +#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed +#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed + +#define HAL_GDMAX_READ32(GdmaIndex, addr) \ + HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) +#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \ + HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value) +#define HAL_GDMAX_READ16(GdmaIndex, addr) \ + HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) +#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \ + HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value) +#define HAL_GDMAX_READ8(GdmaIndex, addr) \ + HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) +#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \ + HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value) + + +#define GDMA_CH_MAX 0x06 + +#define REG_GDMA_CH_OFF 0x058 +#define REG_GDMA_CH_SAR 0x000 +#define REG_GDMA_CH_DAR 0x008 +#define REG_GDMA_CH_LLP 0x010 +#define REG_GDMA_CH_CTL 0x018 +#define REG_GDMA_CH_SSTAT 0x020 +#define REG_GDMA_CH_DSTAT 0x028 +#define REG_GDMA_CH_SSTATAR 0x030 +#define REG_GDMA_CH_DSTATAR 0x038 +#define REG_GDMA_CH_CFG 0x040 +#define REG_GDMA_CH_SGR 0x048 +#define REG_GDMA_CH_DSR 0x050 + +#define MAX_DMA_BLOCK_SIZE 4092 + +//3 Interrupt Registers +#define REG_GDMA_RAW_INT_BASE 0x2C0 +#define REG_GDMA_RAW_INT_TFR 0x2C0 +#define REG_GDMA_RAW_INT_BLOCK 0x2c8 +#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0 +#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8 +#define REG_GDMA_RAW_INT_ERR 0x2E0 + +#define REG_GDMA_STATUS_INT_BASE 0x2E8 +#define REG_GDMA_STATUS_INT_TFR 0x2E8 +#define REG_GDMA_STATUS_INT_BLOCK 0x2F0 +#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8 +#define REG_GDMA_STATUS_INT_DST_TRAN 0x300 +#define REG_GDMA_STATUS_INT_ERR 0x308 + +#define REG_GDMA_MASK_INT_BASE 0x310 +#define REG_GDMA_MASK_INT_TFR 0x310 +#define REG_GDMA_MASK_INT_BLOCK 0x318 +#define REG_GDMA_MASK_INT_SRC_TRAN 0x320 +#define REG_GDMA_MASK_INT_DST_TRAN 0x328 +#define REG_GDMA_MASK_INT_INT_ERR 0x330 + +#define REG_GDMA_CLEAR_INT_BASE 0x338 +#define REG_GDMA_CLEAR_INT_TFR 0x338 +#define REG_GDMA_CLEAR_INT_BLOCK 0x340 +#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348 +#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350 +#define REG_GDMA_CLEAR_INT_ERR 0x358 +#define REG_GDMA_STATUS_INT 0x360 + +//3 Software handshaking Registers +#define REG_GDMA_REQ_SRC 0x368 +#define REG_GDMA_REQ_DST 0x370 +#define REG_GDMA_REQ_SGL_REQ 0x378 +#define REG_GDMA_REQ_DST_REQ 0x380 +#define REG_GDMA_REQ_LST_SRC 0x388 +#define REG_GDMA_REQ_LST_DST 0x390 + +//3 Miscellaneous Registers +#define REG_GDMA_DMAC_CFG 0x398 +#define REG_GDMA_CH_EN 0x3A0 +#define REG_GDMA_DMA_ID 0x3A8 +#define REG_GDMA_DMA_TEST 0x3B0 +#define REG_GDMA_DMA_COM_PARAMS6 0x3C8 +#define REG_GDMA_DMA_COM_PARAMS5 0x3D0 +#define REG_GDMA_DMA_COM_PARAMS4 0x3D8 +#define REG_GDMA_DMA_COM_PARAMS3 0x3E0 +#define REG_GDMA_DMA_COM_PARAMS2 0x3E8 +#define REG_GDMA_DMA_COM_PARAMS1 0x3F0 +#define REG_GDMA_DMA_COM_PARAMS0 0x3F8 + +//3 CTL Register Bit Control +#define BIT_SHIFT_CTLX_LO_INT_EN 0 +#define BIT_MASK_CTLX_LO_INT_EN 0x1 +#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN) +#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN)) + +#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1 +#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7 +#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH) +#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)) + +#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4 +#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7 +#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH) +#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)) + +#define BIT_SHIFT_CTLX_LO_DINC 7 +#define BIT_MASK_CTLX_LO_DINC 0x3 +#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC) +#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC)) + +#define BIT_SHIFT_CTLX_LO_SINC 9 +#define BIT_MASK_CTLX_LO_SINC 0x3 +#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC) +#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC)) + +#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11 +#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7 +#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE) +#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE)) + +#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14 +#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7 +#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE) +#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE)) + + +#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17 +#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1 +#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN) +#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)) + + +#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18 +#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1 +#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN) +#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)) + + +#define BIT_SHIFT_CTLX_LO_TT_FC 20 +#define BIT_MASK_CTLX_LO_TT_FC 0x7 +#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC) +#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC)) + + +#define BIT_SHIFT_CTLX_LO_DMS 23 +#define BIT_MASK_CTLX_LO_DMS 0x3 +#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS) +#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS)) + + +#define BIT_SHIFT_CTLX_LO_SMS 25 +#define BIT_MASK_CTLX_LO_SMS 0x3 +#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS) +#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS)) + + +#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27 +#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1 +#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN) +#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN)) + +#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28 +#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1 +#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN) +#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)) + + +#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0 +#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF +#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS) +#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS)) + + +#define BIT_SHIFT_CTLX_UP_DONE 12 +#define BIT_MASK_CTLX_UP_DONE 0x1 +#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE) +#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE)) + + +//3 CFG Register Bit Control +#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5 +#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7 +#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR) +#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR)) + + +#define BIT_SHIFT_CFGX_LO_CH_SUSP 8 +#define BIT_MASK_CFGX_LO_CH_SUSP 0x1 +#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP) +#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP)) + + +#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9 +#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1 +#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY) +#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)) + + +#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10 +#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1 +#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST) +#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST)) + +#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11 +#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1 +#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC) +#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)) + +#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12 +#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3 +#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L) +#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L)) + +#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14 +#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3 +#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L) +#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L)) + +#define BIT_SHIFT_CFGX_LO_LOCK_CH 16 +#define BIT_MASK_CFGX_LO_LOCK_CH 0x1 +#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH) +#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH)) + +#define BIT_SHIFT_CFGX_LO_LOCK_B 17 +#define BIT_MASK_CFGX_LO_LOCK_B 0x1 +#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B) +#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B)) + +#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18 +#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1 +#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL) +#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL)) + +#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19 +#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1 +#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL) +#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL)) + +#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20 +#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF +#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST) +#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST)) + +#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30 +#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1 +#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC) +#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC)) + +#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31 +#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1 +#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST) +#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST)) + +#define BIT_SHIFT_CFGX_UP_FCMODE 0 +#define BIT_MASK_CFGX_UP_FCMODE 0x1 +#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE) +#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE)) + +#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1 +#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1 +#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE) +#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE)) + +#define BIT_SHIFT_CFGX_UP_PROTCTL 2 +#define BIT_MASK_CFGX_UP_PROTCTL 0x7 +#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL) +#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL)) + +#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5 +#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1 +#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN) +#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN)) + +#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6 +#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1 +#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN) +#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN)) + +#define BIT_SHIFT_CFGX_UP_SRC_PER 7 +#define BIT_MASK_CFGX_UP_SRC_PER 0xF +#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER) +#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER)) + +#define BIT_SHIFT_CFGX_UP_DEST_PER 11 +#define BIT_MASK_CFGX_UP_DEST_PER 0xF +#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER) +#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER)) + +typedef enum _GDMA_CHANNEL_NUM_ { + GdmaNoCh = 0x0000, + GdmaCh0 = 0x0101, + GdmaCh1 = 0x0202, + GdmaCh2 = 0x0404, + GdmaCh3 = 0x0808, + GdmaCh4 = 0x1010, + GdmaCh5 = 0x2020, + GdmaCh6 = 0x4040, + GdmaCh7 = 0x8080, + GdmaAllCh = 0xffff +}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM; + + +//3 CTL register struct + +typedef enum _GDMA_CTL_TT_FC_TYPE_ { + TTFCMemToMem = 0x00, + TTFCMemToPeri = 0x01, + TTFCPeriToMem = 0x02 +}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE; + +//Max type = Bus Width +typedef enum _GDMA_CTL_TR_WIDTH_ { + TrWidthOneByte = 0x00, + TrWidthTwoBytes = 0x01, + TrWidthFourBytes = 0x02 +}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH; + +typedef enum _GDMA_CTL_MSIZE_ { + MsizeOne = 0x00, + MsizeFour = 0x01, + MsizeEight = 0x02 +}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE; + +typedef enum _GDMA_INC_TYPE_ { + IncType = 0x00, + DecType = 0x01, + NoChange = 0x02 +}GDMA_INC_TYPE, *PGDMA_INC_TYPE; + + +typedef struct _GDMA_CTL_REG_ { + GDMA_CTL_TT_FC_TYPE TtFc; + GDMA_CTL_TR_WIDTH DstTrWidth; + GDMA_CTL_TR_WIDTH SrcTrWidth; + GDMA_INC_TYPE Dinc; + GDMA_INC_TYPE Sinc; + GDMA_CTL_MSIZE DestMsize; + GDMA_CTL_MSIZE SrcMsize; + + u8 IntEn :1; // Bit 0 + u8 SrcGatherEn :1; // Bit 1 + u8 DstScatterEn :1; // Bit 2 + u8 LlpDstEn :1; // Bit 3 + u8 LlpSrcEn :1; // Bit 4 + u8 Done :1; // Bit 5 + u8 Rsvd6To7 :2; //Bit 6 -7 + u16 BlockSize; + +}GDMA_CTL_REG, *PGDMA_CTL_REG; + + +//3 CFG Register Structure + +typedef enum _GDMA_CH_PRIORITY_ { + Prior0 = 0, + Prior1 = 1, + Prior2 = 2, + Prior3 = 3, + Prior4 = 4, + Prior5 = 5, + Prior6 = 6, + Prior7 = 7 +}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY; + +typedef enum _GDMA_LOCK_LEVEL_ { + OverComplDmaTransfer = 0x00, + OverComplDmaBlockTransfer = 0x01, + OverComplDmaTransation = 0x02 +}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL; + + +typedef struct _GDMA_CFG_REG_ { + GDMA_CH_PRIORITY ChPrior; + GDMA_LOCK_LEVEL LockBL; + GDMA_LOCK_LEVEL LockChL; + u16 MaxAbrst; + u8 SrcPer; + u8 DestPer; + u16 ChSusp :1; //Bit 0 + u16 FifoEmpty :1; //Bit 1 + u16 HsSelDst :1; //Bit 2 + u16 HsSelSrc :1; //Bit 3 + u16 LockCh :1; //Bit 4 + u16 LockB :1; //Bit 5 + u16 DstHsPol :1; //Bit 6 + u16 SrcHsPol :1; //Bit 7 + u16 ReloadSrc :1; //Bit 8 + u16 ReloadDst :1; //Bit 9 + u16 FifoMode :1; //Bit 10 + u16 DsUpdEn :1; //Bit 11 + u16 SsUpdEn :1; //Bit 12 + u16 Rsvd13To15 :3; +}GDMA_CFG_REG, *PGDMA_CFG_REG; + +typedef enum _GDMA_ISR_TYPE_ { + TransferType = 0x1, + BlockType = 0x2, + SrcTransferType = 0x4, + DstTransferType = 0x8, + ErrType = 0x10 +}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE; + + +VOID +HalGdmaOnOffRtl8195a ( + IN VOID *Data +); + +BOOL +HalGdamChInitRtl8195a( + IN VOID *Data +); + +BOOL +HalGdmaChSetingRtl8195a( + IN VOID *Data +); + +BOOL +HalGdmaChBlockSetingRtl8195a( + IN VOID *Data +); + +BOOL +HalGdmaChBlockSetingRtl8195a_Patch( + IN VOID *Data +); + +VOID +HalGdmaChDisRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChEnRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChIsrEnAndDisRtl8195a ( + IN VOID *Data +); + +u8 +HalGdmaChIsrCleanRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChCleanAutoSrcRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChCleanAutoDstRtl8195a ( + IN VOID *Data +); + +u32 +HalGdmaQueryDArRtl8195a( + IN VOID *Data +); + +u32 +HalGdmaQuerySArRtl8195a( + IN VOID *Data +); + +BOOL +HalGdmaQueryChEnRtl8195a ( + IN VOID *Data +); + +#ifdef CONFIG_CHIP_E_CUT +_LONG_CALL_ BOOL +HalGdmaChBlockSetingRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ u32 +HalGdmaQueryDArRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ u32 +HalGdmaQuerySArRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ BOOL +HalGdmaQueryChEnRtl8195a_V04 ( + IN VOID *Data +); + +#endif // #ifdef CONFIG_CHIP_E_CUT + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gpio.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gpio.h new file mode 100644 index 00000000000..0fd3d8dd799 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gpio.h @@ -0,0 +1,337 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_GPIO_H_ +#define _RTL8195A_GPIO_H_ + +#include "hal_api.h" +#include "hal_gpio.h" + +#define GPIO_PORTA_DR 0x00 // data register +#define GPIO_PORTA_DDR 0x04 // data direction +#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software + +#define GPIO_PORTB_DR 0x0c // data register +#define GPIO_PORTB_DDR 0x10 // data direction +#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software + +#define GPIO_PORTC_DR 0x18 // data register +#define GPIO_PORTC_DDR 0x1c // data direction +#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software + +//1 Only the PORTA can be configured to generate interrupts +#define GPIO_INT_EN 0x30 // Interrupt enable register +#define GPIO_INT_MASK 0x34 // Interrupt mask +#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register +#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register +#define GPIO_INT_STATUS 0x40 // Interrupt status +#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask +#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce +#define GPIO_PORTA_EOI 0x4c // Clear interrupt + +#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back +#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back +#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back + +#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK + +enum { + HAL_GPIO_HIGHZ = 0, + HAL_GPIO_PULL_LOW = 1, + HAL_GPIO_PULL_HIGH = 2 +}; + +//====================================================== +// ROM Function prototype +extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; +#ifndef CONFIG_RELEASE_BUILD_LIBRARIES +static __inline HAL_Status +GPIO_Lock ( + VOID +) +{ + HAL_Status Status; + + if (_pHAL_Gpio_Adapter->EnterCritical) { + _pHAL_Gpio_Adapter->EnterCritical(); + } + + if(_pHAL_Gpio_Adapter->Locked) { + Status = HAL_BUSY; + } + else { + _pHAL_Gpio_Adapter->Locked = 1; + Status = HAL_OK; + } + + if (_pHAL_Gpio_Adapter->ExitCritical) { + _pHAL_Gpio_Adapter->ExitCritical(); + } + + return Status; +} + + +static __inline VOID +GPIO_UnLock ( + VOID +) +{ + if (_pHAL_Gpio_Adapter->EnterCritical) { + _pHAL_Gpio_Adapter->EnterCritical(); + } + + _pHAL_Gpio_Adapter->Locked = 0; + + if (_pHAL_Gpio_Adapter->ExitCritical) { + _pHAL_Gpio_Adapter->ExitCritical(); + } +} +#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES + +_LONG_CALL_ extern u32 +HAL_GPIO_IrqHandler_8195a( + IN VOID *pData +); + +_LONG_CALL_ extern u32 +HAL_GPIO_MbedIrqHandler_8195a( + IN VOID *pData +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_IntCtrl_8195a( + HAL_GPIO_PIN *GPIO_Pin, + u32 En +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_Init_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_DeInit_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_GPIO_PIN_STATE +HAL_GPIO_ReadPin_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_WritePin_8195a( + HAL_GPIO_PIN *GPIO_Pin, + HAL_GPIO_PIN_STATE Pin_State +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_RegIrq_8195a( + IN PIRQ_HANDLE pIrqHandle +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UnRegIrq_8195a( + IN PIRQ_HANDLE pIrqHandle +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UserRegIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin, + VOID *IrqHandler, + VOID *IrqData +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UserUnRegIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_MaskIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UnMaskIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_IntDebounce_8195a( + HAL_GPIO_PIN *GPIO_Pin, + u8 Enable +); + +_LONG_CALL_ u32 +HAL_GPIO_GetIPPinName_8195a( + u32 chip_pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_PullCtrl_8195a( + u32 chip_pin, + u8 pull_type +); + +_LONG_CALL_ u32 +GPIO_GetChipPinName_8195a( + u32 port, + u32 pin +); + +_LONG_CALL_ VOID +GPIO_PullCtrl_8195a( + u32 chip_pin, + u8 pull_type +); + +_LONG_CALL_ VOID +GPIO_Int_SetType_8195a( + u8 pin_num, + u8 int_mode +); + + +_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En); +_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr); + +HAL_Status +HAL_GPIO_ClearISR_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + + +/********** HAL In-Line Functions **********/ + +/** + * @brief Reads the specified input port pin. + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval The input port pin current status(High or Low). + */ +static __inline s32 +HAL_GPIO_ReadPin( + HAL_GPIO_PIN *GPIO_Pin +) +{ + return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin); +} + +/** + * @brief Write the specified output port pin. + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @param Pin_State: The state going to be set to the assigned GPIO pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_WritePin( + HAL_GPIO_PIN *GPIO_Pin, + u32 Value +) +{ + HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value); +} + +/** + * @brief To register a user interrupt handler for a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @param IrqHandler: The IRQ handler to be assigned to the specified pin + * + * @param IrqData: The pointer will be pass the the IRQ handler + * + * @retval None + */ +static __inline VOID +HAL_GPIO_UserRegIrq( + HAL_GPIO_PIN *GPIO_Pin, + VOID *IrqHandler, + VOID *IrqData +) +{ + HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData); +} + +/** + * @brief To un-register a user interrupt handler for a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_UserUnRegIrq( + HAL_GPIO_PIN *GPIO_Pin +) +{ + HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin); +} + + +/** + * @brief Enable/Disable GPIO interrupt + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization. + * + * @param En: Enable (1) or Disable (0) + * + * @retval HAL_Status + */ +static __inline VOID +HAL_GPIO_IntCtrl( + HAL_GPIO_PIN *GPIO_Pin, + u32 En +) +{ + HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En); +} + +/** + * @brief Mask the interrupt of a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_MaskIrq( + HAL_GPIO_PIN *GPIO_Pin +) +{ + HAL_GPIO_MaskIrq_8195a(GPIO_Pin); +} + + +/** + * @brief UnMask the interrupt of a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_UnMaskIrq( + HAL_GPIO_PIN *GPIO_Pin +) +{ + HAL_GPIO_ClearISR_8195a(GPIO_Pin); + HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin); +} + + +#endif // end of "#define _RTL8195A_GPIO_H_" + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h new file mode 100644 index 00000000000..d38e4d25ede --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h @@ -0,0 +1,862 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_I2C_H_ +#define _RTL8195A_I2C_H_ + +#include "hal_api.h" + +//================ Register Bit Field ================== +//2 REG_DW_I2C_IC_CON +#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6) +#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6 +#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1 +#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE) + +#define BIT_IC_CON_IC_RESTART_EN BIT(5) +#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5 +#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1 +#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN) + +#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4) +#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4 +#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1 +#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER) + +#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3) +#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3 +#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1 +#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE) + + +#define BIT_SHIFT_IC_CON_SPEED 1 +#define BIT_MASK_IC_CON_SPEED 0x3 +#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED) +#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED) +#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED) + +#define BIT_IC_CON_MASTER_MODE BIT(0) +#define BIT_SHIFT_IC_CON_MASTER_MODE 0 +#define BIT_MASK_IC_CON_MASTER_MODE 0x1 +#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE) + + +//2 REG_DW_I2C_IC_TAR +#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12) +#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12 +#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1 +#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER) + +#define BIT_IC_TAR_SPECIAL BIT(11) +#define BIT_SHIFT_IC_TAR_SPECIAL 11 +#define BIT_MASK_IC_TAR_SPECIAL 0x1 +#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL) + +#define BIT_IC_TAR_GC_OR_START BIT(10) +#define BIT_SHIFT_IC_TAR_GC_OR_START 10 +#define BIT_MASK_IC_TAR_GC_OR_START 0x1 +#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START) + + +#define BIT_SHIFT_IC_TAR 0 +#define BIT_MASK_IC_TAR 0x3ff +#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR) +#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR) +#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR) + + +//2 REG_DW_I2C_IC_SAR + +#define BIT_SHIFT_IC_SAR 0 +#define BIT_MASK_IC_SAR 0x3ff +#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR) +#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR) +#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR) + + +//2 REG_DW_I2C_IC_HS_MADDR + +#define BIT_SHIFT_IC_HS_MADDR 0 +#define BIT_MASK_IC_HS_MADDR 0x7 +#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR) +#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR) +#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR) + + +//2 REG_DW_I2C_IC_DATA_CMD +#define BIT_IC_DATA_CMD_RESTART BIT(10) +#define BIT_SHIFT_IC_DATA_CMD_RESTART 10 +#define BIT_MASK_IC_DATA_CMD_RESTART 0x1 +#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART) + +#define BIT_IC_DATA_CMD_STOP BIT(9) +#define BIT_SHIFT_IC_DATA_CMD_STOP 9 +#define BIT_MASK_IC_DATA_CMD_STOP 0x1 +#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP) + +#define BIT_IC_DATA_CMD_CMD BIT(8) +#define BIT_SHIFT_IC_DATA_CMD_CMD 8 +#define BIT_MASK_IC_DATA_CMD_CMD 0x1 +#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD) + + +#define BIT_SHIFT_IC_DATA_CMD_DAT 0 +#define BIT_MASK_IC_DATA_CMD_DAT 0xff +#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT) +#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT) +#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT) + + +//2 REG_DW_I2C_IC_SS_SCL_HCNT + +#define BIT_SHIFT_IC_SS_SCL_HCNT 0 +#define BIT_MASK_IC_SS_SCL_HCNT 0xffff +#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT) +#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT) +#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT) + + +//2 REG_DW_I2C_IC_SS_SCL_LCNT + +#define BIT_SHIFT_IC_SS_SCL_LCNT 0 +#define BIT_MASK_IC_SS_SCL_LCNT 0xffff +#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT) +#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT) +#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT) + + +//2 REG_DW_I2C_IC_FS_SCL_HCNT + +#define BIT_SHIFT_IC_FS_SCL_HCNT 0 +#define BIT_MASK_IC_FS_SCL_HCNT 0xffff +#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT) +#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT) +#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT) + + +//2 REG_DW_I2C_IC_FS_SCL_LCNT + +#define BIT_SHIFT_IC_FS_SCL_LCNT 0 +#define BIT_MASK_IC_FS_SCL_LCNT 0xffff +#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT) +#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT) +#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT) + + +//2 REG_DW_I2C_IC_HS_SCL_HCNT + +#define BIT_SHIFT_IC_HS_SCL_HCNT 0 +#define BIT_MASK_IC_HS_SCL_HCNT 0xffff +#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT) +#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT) +#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT) + + +//2 REG_DW_I2C_IC_HS_SCL_LCNT + +#define BIT_SHIFT_IC_HS_SCL_LCNT 0 +#define BIT_MASK_IC_HS_SCL_LCNT 0xffff +#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT) +#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT) +#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT) + + +//2 REG_DW_I2C_IC_INTR_STAT +#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11) +#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11 +#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL) + +#define BIT_IC_INTR_STAT_R_START_DET BIT(10) +#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10 +#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET) + +#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9) +#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9 +#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET) + +#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8) +#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8 +#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY) + +#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7 +#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE) + +#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6) +#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6 +#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT) + +#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5) +#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5 +#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ) + +#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4) +#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4 +#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY) + +#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3) +#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3 +#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER) + +#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2 +#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL) + +#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1 +#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER) + +#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0 +#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER) + + +//2 REG_DW_I2C_IC_INTR_MASK +#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11) +#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11 +#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL) + +#define BIT_IC_INTR_MASK_M_START_DET BIT(10) +#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10 +#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET) + +#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9) +#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9 +#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET) + +#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8) +#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8 +#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY) + +#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7 +#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE) + +#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6) +#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6 +#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT) + +#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5) +#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5 +#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ) + +#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4) +#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4 +#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY) + +#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3) +#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3 +#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER) + +#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2 +#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL) + +#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1 +#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER) + +#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0 +#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER) + + +//2 REG_DW_I2C_IC_RAW_INTR_STAT +#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11) +#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11 +#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL) + +#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10) +#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10 +#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET) + +#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9) +#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9 +#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET) + +#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8) +#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8 +#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY) + +#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE) + +#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6) +#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6 +#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT) + +#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5 +#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ) + +#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4) +#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4 +#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY) + +#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3) +#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3 +#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER) + +#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL) + +#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER) + +#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER) + + +//2 REG_DW_I2C_IC_RX_TL + +#define BIT_SHIFT_IC_RX_TL 0 +#define BIT_MASK_IC_RX_TL 0xff +#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL) +#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL) +#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL) + + +//2 REG_DW_I2C_IC_TX_TL + +#define BIT_SHIFT_IC_TX_TL 0 +#define BIT_MASK_IC_TX_TL 0xff +#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL) +#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL) +#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL) + + +//2 REG_DW_I2C_IC_CLR_INTR +#define BIT_IC_CLR_INTR BIT(0) +#define BIT_SHIFT_IC_CLR_INTR 0 +#define BIT_MASK_IC_CLR_INTR 0x1 +#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR) + + +//2 REG_DW_I2C_IC_CLR_RX_UNDER +#define BIT_IC_CLR_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_CLR_RX_UNDER 0 +#define BIT_MASK_IC_CLR_RX_UNDER 0x1 +#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER) + + +//2 REG_DW_I2C_IC_CLR_RX_OVER +#define BIT_IC_CLR_RX_OVER BIT(0) +#define BIT_SHIFT_IC_CLR_RX_OVER 0 +#define BIT_MASK_IC_CLR_RX_OVER 0x1 +#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER) + + +//2 REG_DW_I2C_IC_CLR_TX_OVER +#define BIT_IC_CLR_TX_OVER BIT(0) +#define BIT_SHIFT_IC_CLR_TX_OVER 0 +#define BIT_MASK_IC_CLR_TX_OVER 0x1 +#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER) + + +//2 REG_DW_I2C_IC_CLR_RD_REQ +#define BIT_IC_CLR_RD_REQ BIT(0) +#define BIT_SHIFT_IC_CLR_RD_REQ 0 +#define BIT_MASK_IC_CLR_RD_REQ 0x1 +#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ) + + +//2 REG_DW_I2C_IC_CLR_TX_ABRT +#define BIT_CLR_RD_REQ BIT(0) +#define BIT_SHIFT_CLR_RD_REQ 0 +#define BIT_MASK_CLR_RD_REQ 0x1 +#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ) + + +//2 REG_DW_I2C_IC_CLR_RX_DONE +#define BIT_IC_CLR_RX_DONE BIT(0) +#define BIT_SHIFT_IC_CLR_RX_DONE 0 +#define BIT_MASK_IC_CLR_RX_DONE 0x1 +#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE) + + +//2 REG_DW_I2C_IC_CLR_ACTIVITY +#define BIT_IC_CLR_ACTIVITY BIT(0) +#define BIT_SHIFT_IC_CLR_ACTIVITY 0 +#define BIT_MASK_IC_CLR_ACTIVITY 0x1 +#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY) + + +//2 REG_DW_I2C_IC_CLR_STOP_DET +#define BIT_IC_CLR_STOP_DET BIT(0) +#define BIT_SHIFT_IC_CLR_STOP_DET 0 +#define BIT_MASK_IC_CLR_STOP_DET 0x1 +#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET) + + +//2 REG_DW_I2C_IC_CLR_START_DET +#define BIT_IC_CLR_START_DET BIT(0) +#define BIT_SHIFT_IC_CLR_START_DET 0 +#define BIT_MASK_IC_CLR_START_DET 0x1 +#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET) + + +//2 REG_DW_I2C_IC_CLR_GEN_CALL +#define BIT_IC_CLR_GEN_CALL BIT(0) +#define BIT_SHIFT_IC_CLR_GEN_CALL 0 +#define BIT_MASK_IC_CLR_GEN_CALL 0x1 +#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL) + + +//2 REG_DW_I2C_IC_ENABLE +#define BIT_IC_ENABLE BIT(0) +#define BIT_SHIFT_IC_ENABLE 0 +#define BIT_MASK_IC_ENABLE 0x1 +#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE) + + +//2 REG_DW_I2C_IC_STATUS +#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6) +#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6 +#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1 +#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY) + +#define BIT_IC_STATUS_MST_ACTIVITY BIT(5) +#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5 +#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1 +#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY) + +#define BIT_IC_STATUS_RFF BIT(4) +#define BIT_SHIFT_IC_STATUS_RFF 4 +#define BIT_MASK_IC_STATUS_RFF 0x1 +#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF) + +#define BIT_IC_STATUS_RFNE BIT(3) +#define BIT_SHIFT_IC_STATUS_RFNE 3 +#define BIT_MASK_IC_STATUS_RFNE 0x1 +#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE) + +#define BIT_IC_STATUS_TFE BIT(2) +#define BIT_SHIFT_IC_STATUS_TFE 2 +#define BIT_MASK_IC_STATUS_TFE 0x1 +#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE) + +#define BIT_IC_STATUS_TFNF BIT(1) +#define BIT_SHIFT_IC_STATUS_TFNF 1 +#define BIT_MASK_IC_STATUS_TFNF 0x1 +#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF) + +#define BIT_IC_STATUS_ACTIVITY BIT(0) +#define BIT_SHIFT_IC_STATUS_ACTIVITY 0 +#define BIT_MASK_IC_STATUS_ACTIVITY 0x1 +#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY) + + +//2 REG_DW_I2C_IC_TXFLR + +#define BIT_SHIFT_IC_TXFLR 0 +#define BIT_MASK_IC_TXFLR 0x3f +#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR) +#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR) +#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR) + + +//2 REG_DW_I2C_IC_RXFLR + +#define BIT_SHIFT_IC_RXFLR 0 +#define BIT_MASK_IC_RXFLR 0x1f +#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR) +#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR) +#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR) + + +//2 REG_DW_I2C_IC_SDA_HOLD + +#define BIT_SHIFT_IC_SDA_HOLD 0 +#define BIT_MASK_IC_SDA_HOLD 0xffff +#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD) +#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD) +#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD) + + +//2 REG_DW_I2C_IC_TX_ABRT_SOURCE +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) + +#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) + + +//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY +#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0) +#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0 +#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1 +#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY) + + +//2 REG_DW_I2C_IC_DMA_CR +#define BIT_IC_DMA_CR_TDMAE BIT(1) +#define BIT_SHIFT_IC_DMA_CR_TDMAE 1 +#define BIT_MASK_IC_DMA_CR_TDMAE 0x1 +#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE) + +#define BIT_IC_DMA_CR_RDMAE BIT(0) +#define BIT_SHIFT_IC_DMA_CR_RDMAE 0 +#define BIT_MASK_IC_DMA_CR_RDMAE 0x1 +#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE) + + +//2 REG_DW_I2C_IC_DMA_TDLR + +#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0 +#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f +#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL) +#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL) +#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL) + + +//2 REG_DW_I2C_IC_DMA_RDLR + +#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0 +#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf +#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL) +#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL) +#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL) + + +//2 REG_DW_I2C_IC_SDA_SETUP + +#define BIT_SHIFT_IC_SDA_SETUP 0 +#define BIT_MASK_IC_SDA_SETUP 0xff +#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP) +#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP) +#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP) + + +//2 REG_DW_I2C_IC_ACK_GENERAL_CALL +#define BIT_IC_ACK_GENERAL_CALL BIT(0) +#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0 +#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1 +#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL) + + +//2 REG_DW_I2C_IC_ENABLE_STATUS +#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2) +#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2 +#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1 +#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) + +#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1) +#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1 +#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1 +#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) + +#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0) +#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0 +#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1 +#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN) + + +//2 REG_DW_I2C_IC_COMP_PARAM_1 + +#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16 +#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff +#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) +#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) +#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) + + +#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8 +#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff +#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) +#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) +#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) + +#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7) +#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7 +#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) + +#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6) +#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6 +#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA) + +#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5) +#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5 +#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO) + +#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4) +#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4 +#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES) + + +#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2 +#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3 +#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) +#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) +#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) + + +#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0 +#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3 +#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) +#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) +#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) + + +//2 REG_DW_I2C_IC_COMP_VERSION + +#define BIT_SHIFT_IC_COMP_VERSION 0 +#define BIT_MASK_IC_COMP_VERSION 0xffffffffL +#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION) +#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION) +#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION) + + +//2 REG_DW_I2C_IC_COMP_TYPE + +#define BIT_SHIFT_IC_COMP_TYPE 0 +#define BIT_MASK_IC_COMP_TYPE 0xffffffffL +#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE) +#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE) +#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE) + +//======================== Register Address Definition ======================== +#define REG_DW_I2C_IC_CON 0x0000 +#define REG_DW_I2C_IC_TAR 0x0004 +#define REG_DW_I2C_IC_SAR 0x0008 +#define REG_DW_I2C_IC_HS_MADDR 0x000C +#define REG_DW_I2C_IC_DATA_CMD 0x0010 +#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014 +#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018 +#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C +#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020 +#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024 +#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028 +#define REG_DW_I2C_IC_INTR_STAT 0x002C +#define REG_DW_I2C_IC_INTR_MASK 0x0030 +#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034 +#define REG_DW_I2C_IC_RX_TL 0x0038 +#define REG_DW_I2C_IC_TX_TL 0x003C +#define REG_DW_I2C_IC_CLR_INTR 0x0040 +#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044 +#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048 +#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C +#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050 +#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054 +#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058 +#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C +#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060 +#define REG_DW_I2C_IC_CLR_START_DET 0x0064 +#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068 +#define REG_DW_I2C_IC_ENABLE 0x006C +#define REG_DW_I2C_IC_STATUS 0x0070 +#define REG_DW_I2C_IC_TXFLR 0x0074 +#define REG_DW_I2C_IC_RXFLR 0x0078 +#define REG_DW_I2C_IC_SDA_HOLD 0x007C +#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080 +#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084 +#define REG_DW_I2C_IC_DMA_CR 0x0088 +#define REG_DW_I2C_IC_DMA_TDLR 0x008C +#define REG_DW_I2C_IC_DMA_RDLR 0x0090 +#define REG_DW_I2C_IC_SDA_SETUP 0x0094 +#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098 +#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C +#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4 +#define REG_DW_I2C_IC_COMP_VERSION 0x00F8 +#define REG_DW_I2C_IC_COMP_TYPE 0x00FC + +//====================================================== +// I2C related enumeration +// I2C Address Mode +typedef enum _I2C_ADDR_MODE_ { + I2C_ADDR_7BIT = 0, + I2C_ADDR_10BIT = 1, +}I2C_ADDR_MODE,*PI2C_ADDR_MODE; + +// I2C Speed Mode +typedef enum _I2C_SPD_MODE_ { + I2C_SS_MODE = 1, + I2C_FS_MODE = 2, + I2C_HS_MODE = 3, +}I2C_SPD_MODE,*PI2C_SPD_MODE; + +//I2C Timing Parameters +#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns. +#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns. + +#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns. +#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns. + +#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf +#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf + +#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf +#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf + + +//====================================================== +//I2C Essential functions and macros +_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal); +_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg); + +#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value) +#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr) + +// Rtl8195a I2C function prototypes +_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data); +_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data); +_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg); +_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal); + +//Rtl8195a I2C V02 function prototype +_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data); +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) +_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data); +#elif defined(CONFIG_CHIP_E_CUT) +_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data); +#endif +//Rtl8195a I2C V02 function prototype END + +//Rtl8195a I2C V04 function prototype +_LONG_CALL_ HAL_Status HalI2CSendRtl8195a_V04(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a_V04(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CInit8195a_V04(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195a_V04(IN VOID *Data); +//Rtl8195a I2C V04 function prototype END + +HAL_Status HalI2CInit8195a_Patch(IN VOID *Data); +HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data); +HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data); +HAL_Status HalI2CMassSendRtl8195a_Patch(IN VOID *Data); +HAL_Status HalI2CEnableRtl8195a_Patch(IN VOID *Data); +HAL_Status HalI2CSetTarRtl8195a(IN VOID *Data); +HAL_Status HalI2CSetSarRtl8195a(IN VOID *Data); + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c new file mode 100644 index 00000000000..bb1a353d25c --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtl8195a.h" +#include "system_8195a.h" +#if defined ( __CC_ARM ) /* ARM Compiler 4/5 */ +extern uint8_t Image$$RW_IRAM1$$ZI$$Base[]; +#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base +extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[]; +#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */ +extern uint8_t Image$$RW_IRAM1$$ZI$$Base[]; +#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base +extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[]; +#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit + +#elif defined ( __ICCARM__ ) +#pragma section=".ram.bss" +#pragma section=".rom.bss" +#pragma section=".ram.start.table" +#pragma section=".ram_image1.bss" +#pragma section=".image2.start.table1" +#pragma section=".image2.start.table2" + +uint8_t *__bss_start__; +uint8_t *__bss_end__; + +void __iar_data_init_app(void) +{ + __bss_start__ = (uint8_t *)__section_begin(".ram.bss"); + __bss_end__ = (uint8_t *)__section_end(".ram.bss"); +} +#else +extern uint8_t __bss_start__[]; +extern uint8_t __bss_end__[]; +extern uint8_t __image1_bss_start__[]; +extern uint8_t __image1_bss_end__[]; +extern uint8_t __image2_entry_func__[]; +extern uint8_t __image2_validate_code__[]; +#endif + +extern VECTOR_Func NewVectorTable[]; +extern void SystemCoreClockUpdate(void); +extern void PLAT_Start(void); +extern void PLAT_Main(void); +extern HAL_TIMER_OP HalTimerOp; + +IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 = { + PLAT_Start +}; + +IMAGE1_VALID_PATTEN_SECTION const uint8_t RAM_IMG1_VALID_PATTEN[] = { + 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff +}; + +IMAGE2_VALID_PATTEN_SECTION const uint8_t RAM_IMG2_VALID_PATTEN[20] = { + 'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff, + (FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff), + (FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff), + (FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff), + (FW_CHIP_VER), + (FW_BUS_TYPE), + (FW_INFO_RSV1), + (FW_INFO_RSV2), + (FW_INFO_RSV3), + (FW_INFO_RSV4) +}; + +void TRAP_NMIHandler(void) +{ +#ifdef CONFIG_WDG_NORMAL + uint32_t val; + WDG_REG *ctl; + + // Check if this NMI is triggered by Watchdog Timer + val = __RTK_READ32(VENDOR_REG_BASE, 0); + ctl = (WDG_REG*) &val; + if (ctl->WdgToISR) { + INTR_WatchdogHandler(); + } +#endif +} + +#if defined ( __ICCARM__ ) +void __TRAP_HardFaultHandler_Patch(uint32_t addr) +{ + uint32_t cfsr; + uint32_t bfar; + + uint32_t stackpc; + uint16_t asmcode; + + cfsr = HAL_READ32(0xE000ED28, 0x0); + + // Violation to memory access protection + if (cfsr & 0x82) { + + bfar = HAL_READ32(0xE000ED38, 0x0); + + // invalid access to wifi register, usually happened in LPS 32K or IPS + if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) { + + //__BKPT(0); + + /* Get the MemManage fault PC, and step to next command. + * Otherwise it will keep hitting MemMange Fault on the same assembly code. + * + * To step to next command, we need parse the assembly code to check if + * it is 16-bit or 32-bit command. + * Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition), + * Chapter A6 - Thumb Instruction Set Encoding + * + * However, the fault assembly code (Ex. LDR or ADR) is not actually executed, + * So the register value is un-predictable. + **/ + stackpc = HAL_READ32(addr, 0x18); + asmcode = HAL_READ16(stackpc, 0); + if ((asmcode & 0xF800) > 0xE000) { + // 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101) + HAL_WRITE32(addr, 0x18, stackpc + 4); + } else { + // 16-bit instruction + HAL_WRITE32(addr, 0x18, stackpc + 2); + } + + // clear Hard Fault Status Register + HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0)); + return; + } + } + + __TRAP_HardFaultHandler(addr); +} + +void TRAP_HardFaultHandler_Patch(void) +{ + __asm("TST LR, #4 \n" + "ITE EQ \n" + "MRSEQ R0, MSP \n" + "MRSNE R0, PSP \n" + "B __TRAP_HardFaultHandler_Patch "); +} +#endif + +// Override original Interrupt Vector Table +INFRA_START_SECTION void TRAP_OverrideTable(uint32_t stackp) +{ + // Override NMI Handler + NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler; + + #if defined ( __ICCARM__ ) + NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch; + #endif +} + +INFRA_START_SECTION void PLAT_Init(void) +{ + uint32_t val; + + //Set SPS lower voltage + val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0); + val &= 0xf0ffffff; + val |= 0x6000000; + __RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val); + + //xtal buffer driving current + val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1); + val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1); + val |= BIT_SYS_XTAL_DRV_RF1(1); + __RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val); +} + +//3 Image 2 +extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n); + +//extern uint32_t mbed_stack_isr_start; +//extern uint32_t mbed_stack_isr_size; +INFRA_START_SECTION void PLAT_Start(void) +{ + u8 isFlashEn; +#if defined ( __ICCARM__ ) + __iar_data_init_app(); +#endif + // Clear RAM BSS + __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__); + + TRAP_OverrideTable(0x1FFFFFFC); +/* add by Ian --for mbed isr stack address setting */ + __set_MSP(0x1fffffbc); + + +#ifdef CONFIG_SPIC_MODULE + if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) { + isFlashEn = 1; + } else { + isFlashEn = 0; + } +#endif + +#ifdef CONFIG_TIMER_MODULE + HalTimerOpInit_Patch(&HalTimerOp); +#endif + + DBG_8195A("===== Enter Image 2 ====\n"); + + + SystemCoreClockUpdate(); + + if (isFlashEn) { +#if CONFIG_SPIC_EN && SPIC_CALIBRATION_IN_NVM + SpicNVMCalLoadAll(); +#endif + SpicReadIDRtl8195A(); + // turn off SPIC for power saving + SpicDisableRtl8195A(); + } + + + PLAT_Init(); +#ifdef CONFIG_TIMER_MODULE + Calibration32k(); + +#ifdef CONFIG_WDG +#ifdef CONFIG_WDG_TEST + WDGInit(); +#endif //CONFIG_WDG_TEST +#endif //CONFIG_WDG +#endif //CONFIG_TIMER_MODULE + +#ifdef CONFIG_SOC_PS_MODULE + //InitSoCPM(); +#endif + /* GPIOA_7 does not pull high at power on. It causes SDIO Device + * hardware to enable automatically and occupy GPIOA[7:0] */ +#ifndef CONFIG_SDIO_DEVICE_EN + SDIO_DEV_Disable(); +#endif + + // Enter App start function + PLAT_Main(); +} + +extern void SVC_Handler(void); +extern void PendSV_Handler(void); +extern void SysTick_Handler(void); + +#if defined (__CC_ARM) +__asm void ARM_PLAT_Main(void) +{ + IMPORT SystemInit + IMPORT __main + BL SystemInit + BL __main +} +#endif + +extern void __iar_program_start( void ); +// The Main App entry point +void PLAT_Main(void) +{ + TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler); + +#if defined (__ICCARM__) + //IAR_PLAT_Main(); + SystemInit(); + __iar_program_start(); +#elif defined (__CC_ARM) + ARM_PLAT_Main(); + +#elif defined (__GNUC__) + __asm ( + "ldr r0, =SystemInit \n" + "blx r0 \n" + "ldr r0, =_start \n" + "bx r0 \n" + ); +#endif + // Never reached + for(;;); +} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_misc.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_misc.h new file mode 100644 index 00000000000..a2df233452c --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_misc.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_RTL8195A_MISC_H +#define MBED_RTL8195A_MISC_H + +// Interface to ROM functions +extern __longcall void *_memset( void *s, int c, size_t n); +extern __longcall void *_memcpy( void *s1, const void *s2, size_t n ); +extern __longcall int _memcmp( const void *av, const void *bv, size_t len); +extern __longcall size_t _strlen(const char *s); +extern __longcall int _strcmp(const char *cs, const char *ct); + +#define __memset _memset +#define __memcpy _memcpy +#define __memcmp _memcmp +#define __strlen _strlen +#define __strcmp _strcmp + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_peri_on.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_peri_on.h new file mode 100644 index 00000000000..da99b985c75 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_peri_on.h @@ -0,0 +1,1251 @@ +#ifndef __INC_RTL8195A_PERI_ON_H +#define __INC_RTL8195A_PERI_ON_H + +#define CPU_OPT_WIDTH 0x1F + +//2 REG_NOT_VALID + +//2 REG_PEON_PWR_CTRL +#define BIT_SOC_UAHV_EN BIT(2) +#define BIT_SOC_UALV_EN BIT(1) +#define BIT_SOC_USBD_EN BIT(0) + +//2 REG_PON_ISO_CTRL + +//2 REG_NOT_VALID +#define BIT_ISO_OSC32K_EN BIT(4) +//#define BIT_ISO_USBA_EN BIT(1) +//#define BIT_ISO_USBD_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SOC_FUNC_EN +#define BIT_SOC_SECURITY_ENGINE_EN BIT(20) +#define BIT_SOC_GTIMER_EN BIT(16) +#define BIT_SOC_GDMA1_EN BIT(14) +#define BIT_SOC_GDMA0_EN BIT(13) +#define BIT_SOC_LOG_UART_EN BIT(12) +#define BIT_SOC_CPU_EN BIT(8) +#define BIT_SOC_MEM_CTRL_EN BIT(6) +#define BIT_SOC_FLASH_EN BIT(4) +#define BIT_SOC_LXBUS_EN BIT(2) +#define BIT_SOC_OCP_EN BIT(1) +#define BiT_SOC_FUN_EN BIT(0) + +//2 REG_SOC_HCI_COM_FUNC_EN +#define BIT_SOC_HCI_WL_MACON_EN BIT(16) +#define BIT_SOC_HCI_SM_SEL BIT(13) +#define BIT_SOC_HCI_MII_EN BIT(12) +#define BIT_SOC_HCI_OTG_RST_MUX BIT(5) +#define BIT_SOC_HCI_OTG_EN BIT(4) +#define BIT_SOC_HCI_SDIOD_ON_RST_MUX BIT(3) +#define BIT_SOC_HCI_SDIOH_EN BIT(2) +#define BIT_SOC_HCI_SDIOD_OFF_EN BIT(1) +#define BIT_SOC_HCI_SDIOD_ON_EN BIT(0) + +//2 REG_SOC_PERI_FUNC0_EN +#define BIT_PERI_PCM1_EN BIT(29) +#define BIT_PERI_PCM0_EN BIT(28) +#define BIT_PERI_I2S1_EN BIT(25) +#define BIT_PERI_I2S0_EN BIT(24) +#define BIT_PERI_I2C3_EN BIT(19) +#define BIT_PERI_I2C2_EN BIT(18) +#define BIT_PERI_I2C1_EN BIT(17) +#define BIT_PERI_I2C0_EN BIT(16) +#define BIT_PERI_SPI2_EN BIT(10) +#define BIT_PERI_SPI1_EN BIT(9) +#define BIT_PERI_SPI0_EN BIT(8) +#define BIT_PERI_UART2_EN BIT(2) +#define BIT_PERI_UART1_EN BIT(1) +#define BIT_PERI_UART0_EN BIT(0) + +//2 REG_SOC_PERI_FUNC1_EN +#define BIT_PERI_GPIO_EN BIT(8) +#define BIT_PERI_DAC1_EN BIT(5) +#define BIT_PERI_DAC0_EN BIT(4) +#define BIT_PERI_ADC0_EN BIT(0) + +//2 REG_SOC_PERI_BD_FUNC0_EN +#define BIT_PERI_UART2_BD_EN BIT(2) +#define BIT_PERI_UART1_BD_EN BIT(1) +#define BIT_PERI_UART0_BD_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_PESOC_CLK_CTRL +#define BIT_SOC_SLPCK_BTCMD_EN BIT(29) +#define BIT_SOC_ACTCK_BTCMD_EN BIT(28) +#define BIT_SOC_SLPCK_GPIO_EN BIT(25) +#define BIT_SOC_ACTCK_GPIO_EN BIT(24) +#define BIT_SOC_SLPCK_GDMA1_EN BIT(19) +#define BIT_SOC_ACTCK_GDMA1_EN BIT(18) +#define BIT_SOC_SLPCK_GDMA0_EN BIT(17) +#define BIT_SOC_ACTCK_GDMA0_EN BIT(16) +#define BIT_SOC_SLPCK_TIMER_EN BIT(15) +#define BIT_SOC_ACTCK_TIMER_EN BIT(14) +#define BIT_SOC_SLPCK_LOG_UART_EN BIT(13) +#define BIT_SOC_ACTCK_LOG_UART_EN BIT(12) +#define BIT_SOC_SLPCK_SDR_EN BIT(11) +#define BIT_SOC_ACTCK_SDR_EN BIT(10) +#define BIT_SOC_SLPCK_FLASH_EN BIT(9) +#define BIT_SOC_ACTCK_FLASH_EN BIT(8) +#define BIT_SOC_SLPCK_VENDOR_REG_EN BIT(7) +#define BIT_SOC_ACTCK_VENDOR_REG_EN BIT(6) +#define BIT_SOC_SLPCK_TRACE_EN BIT(5) +#define BIT_SOC_ACTCK_TRACE_EN BIT(4) +#define BIT_SOC_CKE_PLFM BIT(2) +#define BIT_SOC_CKE_OCP BIT(0) + +//2 REG_PESOC_PERI_CLK_CTRL0 +#define BIT_SOC_SLPCK_SPI2_EN BIT(21) +#define BIT_SOC_ACTCK_SPI2_EN BIT(20) +#define BIT_SOC_SLPCK_SPI1_EN BIT(19) +#define BIT_SOC_ACTCK_SPI1_EN BIT(18) +#define BIT_SOC_SLPCK_SPI0_EN BIT(17) +#define BIT_SOC_ACTCK_SPI0_EN BIT(16) +#define BIT_SOC_SLPCK_UART2_EN BIT(5) +#define BIT_SOC_ACTCK_UART2_EN BIT(4) +#define BIT_SOC_SLPCK_UART1_EN BIT(3) +#define BIT_SOC_ACTCK_UART1_EN BIT(2) +#define BIT_SOC_SLPCK_UART0_EN BIT(1) +#define BIT_SOC_ACTCK_UART0_EN BIT(0) + +//2 REG_PESOC_PERI_CLK_CTRL1 +#define BIT_SOC_SLPCK_DAC_EN BIT(29) +#define BIT_SOC_ACTCK_DAC_EN BIT(28) +#define BIT_SOC_SLPCK_ADC_EN BIT(25) +#define BIT_SOC_ACTCK_ADC_EN BIT(24) +#define BIT_SOC_SLPCK_PCM_EN BIT(21) +#define BIT_SOC_ACTCK_PCM_EN BIT(20) +#define BIT_SOC_SLPCK_I2S_EN BIT(17) +#define BIT_SOC_ACTCK_I2S_EN BIT(16) +#define BIT_SOC_SLPCK_I2C3_EN BIT(7) +#define BIT_SOC_ACTCK_I2C3_EN BIT(6) +#define BIT_SOC_SLPCK_I2C2_EN BIT(5) +#define BIT_SOC_ACTCK_I2C2_EN BIT(4) +#define BIT_SOC_SLPCK_I2C1_EN BIT(3) +#define BIT_SOC_ACTCK_I2C1_EN BIT(2) +#define BIT_SOC_SLPCK_I2C0_EN BIT(1) +#define BIT_SOC_ACTCK_I2C0_EN BIT(0) + +//2 REG_PESOC_CLK_CTRL3 + +//2 REG_PESOC_HCI_CLK_CTRL0 +#define BIT_SOC_SLPCK_MII_MPHY_EN BIT(25) +#define BIT_SOC_ACTCK_MII_MPHY_EN BIT(24) +#define BIT_SOC_SLPCK_OTG_EN BIT(5) +#define BIT_SOC_ACTCK_OTG_EN BIT(4) +#define BIT_SOC_SLPCK_SDIO_HST_EN BIT(3) +#define BIT_SOC_ACTCK_SDIO_HST_EN BIT(2) +#define BIT_SOC_SLPCK_SDIO_DEV_EN BIT(1) +#define BIT_SOC_ACTCK_SDIO_DEV_EN BIT(0) + +//2 REG_PESOC_COM_CLK_CTRL1 +#define BIT_SOC_NFC_CAL_EN BIT(18) +#define BIT_SOC_SLPCK_NFC_EN BIT(17) +#define BIT_SOC_ACTCK_NFC_EN BIT(16) +#define BIT_SOC_SLPCK_SECURITY_ENG_EN BIT(5) +#define BIT_SOC_ACTCK_SECURITY_ENG_EN BIT(4) +#define BIT_SOC_SLPCK_WL_EN BIT(1) +#define BIT_SOC_ACTCK_WL_EN BIT(0) + +//2 REG_PESOC_HW_ENG_CLK_CTRL + +//2 REG_RSVD + +//2 REG_PESOC_CLK_SEL +#define BIT_PESOC_SPI1_SCLK_SEL BIT(18) + +#define BIT_SHIFT_PESOC_PERI_SCLK_SEL 16 +#define BIT_MASK_PESOC_PERI_SCLK_SEL 0x3 +#define BIT_PESOC_PERI_SCLK_SEL(x) (((x) & BIT_MASK_PESOC_PERI_SCLK_SEL) << BIT_SHIFT_PESOC_PERI_SCLK_SEL) + + +#define BIT_SHIFT_PESOC_SDR_CK_SEL 10 +#define BIT_MASK_PESOC_SDR_CK_SEL 0x3 +#define BIT_PESOC_SDR_CK_SEL(x) (((x) & BIT_MASK_PESOC_SDR_CK_SEL) << BIT_SHIFT_PESOC_SDR_CK_SEL) + + +#define BIT_SHIFT_PESOC_FLASH_CK_SEL 8 +#define BIT_MASK_PESOC_FLASH_CK_SEL 0x3 +#define BIT_PESOC_FLASH_CK_SEL(x) (((x) & BIT_MASK_PESOC_FLASH_CK_SEL) << BIT_SHIFT_PESOC_FLASH_CK_SEL) + + +#define BIT_SHIFT_PESOC_TRACE_CK_SEL 4 +#define BIT_MASK_PESOC_TRACE_CK_SEL 0x3 +#define BIT_PESOC_TRACE_CK_SEL(x) (((x) & BIT_MASK_PESOC_TRACE_CK_SEL) << BIT_SHIFT_PESOC_TRACE_CK_SEL) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_SYS_ANACK_CAL_CTRL +#define BIT_SYS_ANACK_CAL_CMD BIT(15) +#define BIT_SYS_ANACK_CAL_SEL BIT(14) + +#define BIT_SHIFT_SYS_ANACK_CAL_RPT 0 +#define BIT_MASK_SYS_ANACK_CAL_RPT 0x3fff +#define BIT_SYS_ANACK_CAL_RPT(x) (((x) & BIT_MASK_SYS_ANACK_CAL_RPT) << BIT_SHIFT_SYS_ANACK_CAL_RPT) + + +//2 REG_OSC32K_CTRL + +#define BIT_SHIFT_32K_BIAS_CURRENT 16 +#define BIT_MASK_32K_BIAS_CURRENT 0xffff +#define BIT_32K_BIAS_CURRENT(x) (((x) & BIT_MASK_32K_BIAS_CURRENT) << BIT_SHIFT_32K_BIAS_CURRENT) + + +#define BIT_SHIFT_32K_RESISTOR_COM 2 +#define BIT_MASK_32K_RESISTOR_COM 0x3 +#define BIT_32K_RESISTOR_COM(x) (((x) & BIT_MASK_32K_RESISTOR_COM) << BIT_SHIFT_32K_RESISTOR_COM) + +#define BIT_32K_DBG_SEL BIT(1) +#define BIT_32K_POW_CKGEN_EN BIT(0) + +//2 REG_OSC32K_REG_CTRL0 +#define BIT_32K_REG_INDIRT_CMD BIT(23) + +#define BIT_SHIFT_32K_REG_INDIRT_ADDR 16 +#define BIT_MASK_32K_REG_INDIRT_ADDR 0x3f +#define BIT_32K_REG_INDIRT_ADDR(x) (((x) & BIT_MASK_32K_REG_INDIRT_ADDR) << BIT_SHIFT_32K_REG_INDIRT_ADDR) + + +#define BIT_SHIFT_32K_REG_INDIRT_WDATA 0 +#define BIT_MASK_32K_REG_INDIRT_WDATA 0xffff +#define BIT_32K_REG_INDIRT_WDATA(x) (((x) & BIT_MASK_32K_REG_INDIRT_WDATA) << BIT_SHIFT_32K_REG_INDIRT_WDATA) + + +//2 REG_OSC32K_REG_CTRL1 + +#define BIT_SHIFT_32K_REG_INDIRT_RDATA 0 +#define BIT_MASK_32K_REG_INDIRT_RDATA 0xffff +#define BIT_32K_REG_INDIRT_RDATA(x) (((x) & BIT_MASK_32K_REG_INDIRT_RDATA) << BIT_SHIFT_32K_REG_INDIRT_RDATA) + + +//2 REG_THERMAL_METER_CTRL + +#define BIT_SHIFT_TEMP_VALUE 24 +#define BIT_MASK_TEMP_VALUE 0x3f +#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) + + +#define BIT_SHIFT_TEMP_DELTA 16 +#define BIT_MASK_TEMP_DELTA 0x3f +#define BIT_TEMP_DELTA(x) (((x) & BIT_MASK_TEMP_DELTA) << BIT_SHIFT_TEMP_DELTA) + +#define BIT_THERMAL_METER_EN BIT(15) +#define BIT_THERMAL_METER_VALID BIT(14) + +#define BIT_SHIFT_THERMAL_METER_TIMER 0 +#define BIT_MASK_THERMAL_METER_TIMER 0xfff +#define BIT_THERMAL_METER_TIMER(x) (((x) & BIT_MASK_THERMAL_METER_TIMER) << BIT_SHIFT_THERMAL_METER_TIMER) + + +//2 REG_UART_MUX_CTRL + +#define BIT_SHIFT_UART2_PIN_SEL 9 +#define BIT_MASK_UART2_PIN_SEL 0x7 +#define BIT_UART2_PIN_SEL(x) (((x) & BIT_MASK_UART2_PIN_SEL) << BIT_SHIFT_UART2_PIN_SEL) + +#define BIT_UART2_PIN_EN BIT(8) + +#define BIT_SHIFT_UART1_PIN_SEL 5 +#define BIT_MASK_UART1_PIN_SEL 0x7 +#define BIT_UART1_PIN_SEL(x) (((x) & BIT_MASK_UART1_PIN_SEL) << BIT_SHIFT_UART1_PIN_SEL) + +#define BIT_UART1_PIN_EN BIT(4) + +#define BIT_SHIFT_UART0_PIN_SEL 1 +#define BIT_MASK_UART0_PIN_SEL 0x7 +#define BIT_UART0_PIN_SEL(x) (((x) & BIT_MASK_UART0_PIN_SEL) << BIT_SHIFT_UART0_PIN_SEL) + +#define BIT_UART0_PIN_EN BIT(0) + +//2 REG_SPI_MUX_CTRL +#define BIT_SPI0_MULTI_CS_EN BIT(28) + +#define BIT_SHIFT_SPI2_PIN_SEL 9 +#define BIT_MASK_SPI2_PIN_SEL 0x7 +#define BIT_SPI2_PIN_SEL(x) (((x) & BIT_MASK_SPI2_PIN_SEL) << BIT_SHIFT_SPI2_PIN_SEL) + +#define BIT_SPI2_PIN_EN BIT(8) + +#define BIT_SHIFT_SPI1_PIN_SEL 5 +#define BIT_MASK_SPI1_PIN_SEL 0x7 +#define BIT_SPI1_PIN_SEL(x) (((x) & BIT_MASK_SPI1_PIN_SEL) << BIT_SHIFT_SPI1_PIN_SEL) + +#define BIT_SPI1_PIN_EN BIT(4) + +#define BIT_SHIFT_SPI0_PIN_SEL 1 +#define BIT_MASK_SPI0_PIN_SEL 0x7 +#define BIT_SPI0_PIN_SEL(x) (((x) & BIT_MASK_SPI0_PIN_SEL) << BIT_SHIFT_SPI0_PIN_SEL) + +#define BIT_SPI0_PIN_EN BIT(0) + +//2 REG_I2C_MUX_CTRL + +#define BIT_SHIFT_I2C3_PIN_SEL 13 +#define BIT_MASK_I2C3_PIN_SEL 0x7 +#define BIT_I2C3_PIN_SEL(x) (((x) & BIT_MASK_I2C3_PIN_SEL) << BIT_SHIFT_I2C3_PIN_SEL) + +#define BIT_I2C3_PIN_EN BIT(12) + +#define BIT_SHIFT_I2C2_PIN_SEL 9 +#define BIT_MASK_I2C2_PIN_SEL 0x7 +#define BIT_I2C2_PIN_SEL(x) (((x) & BIT_MASK_I2C2_PIN_SEL) << BIT_SHIFT_I2C2_PIN_SEL) + +#define BIT_I2C2_PIN_EN BIT(8) + +#define BIT_SHIFT_I2C1_PIN_SEL 5 +#define BIT_MASK_I2C1_PIN_SEL 0x7 +#define BIT_I2C1_PIN_SEL(x) (((x) & BIT_MASK_I2C1_PIN_SEL) << BIT_SHIFT_I2C1_PIN_SEL) + +#define BIT_I2C1_PIN_EN BIT(4) + +#define BIT_SHIFT_I2C0_PIN_SEL 1 +#define BIT_MASK_I2C0_PIN_SEL 0x7 +#define BIT_I2C0_PIN_SEL(x) (((x) & BIT_MASK_I2C0_PIN_SEL) << BIT_SHIFT_I2C0_PIN_SEL) + +#define BIT_I2C0_PIN_EN BIT(0) + +//2 REG_I2S_MUX_CTRL/ REG_PCM_MUX_CTRL + +//2 REG_NOT_VALID + +#define BIT_SHIFT_PCM1_PIN_SEL 21 +#define BIT_MASK_PCM1_PIN_SEL 0x7 +#define BIT_PCM1_PIN_SEL(x) (((x) & BIT_MASK_PCM1_PIN_SEL) << BIT_SHIFT_PCM1_PIN_SEL) + +#define BIT_PCM1_PIN_EN BIT(20) + +#define BIT_SHIFT_PCM0_PIN_SEL 17 +#define BIT_MASK_PCM0_PIN_SEL 0x7 +#define BIT_PCM0_PIN_SEL(x) (((x) & BIT_MASK_PCM0_PIN_SEL) << BIT_SHIFT_PCM0_PIN_SEL) + +#define BIT_PCM0_PIN_EN BIT(16) + +//2 REG_NOT_VALID + +#define BIT_SHIFT_I2S1_PIN_SEL 6 +#define BIT_MASK_I2S1_PIN_SEL 0x3 +#define BIT_I2S1_PIN_SEL(x) (((x) & BIT_MASK_I2S1_PIN_SEL) << BIT_SHIFT_I2S1_PIN_SEL) + +#define BIT_I2S1_MCK_EN BIT(5) +#define BIT_I2S1_PIN_EN BIT(4) + +#define BIT_SHIFT_I2S0_PIN_SEL 2 +#define BIT_MASK_I2S0_PIN_SEL 0x3 +#define BIT_I2S0_PIN_SEL(x) (((x) & BIT_MASK_I2S0_PIN_SEL) << BIT_SHIFT_I2S0_PIN_SEL) + +#define BIT_I2S0_MCK_EN BIT(1) +#define BIT_I2S0_PIN_EN BIT(0) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_HCI_PINMUX_CTRL +#define BIT_HCI_MII_PIN_EN BIT(24) +#define BIT_HCI_SDIOH_PIN_EN BIT(1) +#define BIT_HCI_SDIOD_PIN_EN BIT(0) + +//2 REG_WL_PINMUX_CTRL +#define BIT_NFC_PIN_EN BIT(16) +#define BIT_WL_BTCMD_PIN_EN BIT(13) +#define BIT_WL_BTCOEX_PIN_EN BIT(12) +#define BIT_WL_ANT1_PIN_EN BIT(9) +#define BIT_WL_ANT0_PIN_EN BIT(8) + +#define BIT_SHIFT_WL_LED_PIN_SEL 1 +#define BIT_MASK_WL_LED_PIN_SEL 0x3 +#define BIT_WL_LED_PIN_SEL(x) (((x) & BIT_MASK_WL_LED_PIN_SEL) << BIT_SHIFT_WL_LED_PIN_SEL) + +#define BIT_WL_LED_PIN_EN BIT(0) + +//2 REG_BT_PINMUX_CTRL + +//2 REG_PWM_PINMUX_CTRL + +#define BIT_SHIFT_ETE3_PIN_SEL 29 +#define BIT_MASK_ETE3_PIN_SEL 0x3 +#define BIT_ETE3_PIN_SEL(x) (((x) & BIT_MASK_ETE3_PIN_SEL) << BIT_SHIFT_ETE3_PIN_SEL) + +#define BIT_ETE3_PIN_EN BIT(28) + +#define BIT_SHIFT_ETE2_PIN_SEL 25 +#define BIT_MASK_ETE2_PIN_SEL 0x3 +#define BIT_ETE2_PIN_SEL(x) (((x) & BIT_MASK_ETE2_PIN_SEL) << BIT_SHIFT_ETE2_PIN_SEL) + +#define BIT_ETE2_PIN_EN BIT(24) + +#define BIT_SHIFT_ETE1_PIN_SEL 21 +#define BIT_MASK_ETE1_PIN_SEL 0x3 +#define BIT_ETE1_PIN_SEL(x) (((x) & BIT_MASK_ETE1_PIN_SEL) << BIT_SHIFT_ETE1_PIN_SEL) + +#define BIT_ETE1_PIN_EN BIT(20) + +#define BIT_SHIFT_ETE0_PIN_SEL 17 +#define BIT_MASK_ETE0_PIN_SEL 0x3 +#define BIT_ETE0_PIN_SEL(x) (((x) & BIT_MASK_ETE0_PIN_SEL) << BIT_SHIFT_ETE0_PIN_SEL) + +#define BIT_ETE0_PIN_EN BIT(16) + +#define BIT_SHIFT_PWM3_PIN_SEL 13 +#define BIT_MASK_PWM3_PIN_SEL 0x3 +#define BIT_PWM3_PIN_SEL(x) (((x) & BIT_MASK_PWM3_PIN_SEL) << BIT_SHIFT_PWM3_PIN_SEL) + +#define BIT_PWM3_PIN_EN BIT(12) + +#define BIT_SHIFT_PWM2_PIN_SEL 9 +#define BIT_MASK_PWM2_PIN_SEL 0x3 +#define BIT_PWM2_PIN_SEL(x) (((x) & BIT_MASK_PWM2_PIN_SEL) << BIT_SHIFT_PWM2_PIN_SEL) + +#define BIT_PWM2_PIN_EN BIT(8) + +#define BIT_SHIFT_PWM1_PIN_SEL 5 +#define BIT_MASK_PWM1_PIN_SEL 0x3 +#define BIT_PWM1_PIN_SEL(x) (((x) & BIT_MASK_PWM1_PIN_SEL) << BIT_SHIFT_PWM1_PIN_SEL) + +#define BIT_PWM1_PIN_EN BIT(4) + +#define BIT_SHIFT_PWM0_PIN_SEL 1 +#define BIT_MASK_PWM0_PIN_SEL 0x3 +#define BIT_PWM0_PIN_SEL(x) (((x) & BIT_MASK_PWM0_PIN_SEL) << BIT_SHIFT_PWM0_PIN_SEL) + +#define BIT_PWM0_PIN_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_CPU_PERIPHERAL_CTRL + +#define BIT_SHIFT_LOG_UART_PIN_SEL 22 +#define BIT_MASK_LOG_UART_PIN_SEL 0x3 +#define BIT_LOG_UART_PIN_SEL(x) (((x) & BIT_MASK_LOG_UART_PIN_SEL) << BIT_SHIFT_LOG_UART_PIN_SEL) + +#define BIT_LOG_UART_IR_EN BIT(21) +#define BIT_LOG_UART_PIN_EN BIT(20) +#define BIT_TRACE_PIN_EN BIT(17) +#define BIT_SDR_PIN_EN BIT(4) + +#define BIT_SHIFT_SPI_FLSH_PIN_SEL 1 +#define BIT_MASK_SPI_FLSH_PIN_SEL 0x3 +#define BIT_SPI_FLSH_PIN_SEL(x) (((x) & BIT_MASK_SPI_FLSH_PIN_SEL) << BIT_SHIFT_SPI_FLSH_PIN_SEL) + +#define BIT_SPI_FLSH_PIN_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_HCI_CTRL_STATUS_0 + +//2 REG_HCI_CTRL_STATUS_1 + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_PESOC_MEM_CTRL + +#define BIT_SHIFT_PESOC_SDR_DDL_CTRL 16 +#define BIT_MASK_PESOC_SDR_DDL_CTRL 0xff +#define BIT_PESOC_SDR_DDL_CTRL(x) (((x) & BIT_MASK_PESOC_SDR_DDL_CTRL) << BIT_SHIFT_PESOC_SDR_DDL_CTRL) + + +#define BIT_SHIFT_PESOC_FLASH_DDL_CTRL 0 +#define BIT_MASK_PESOC_FLASH_DDL_CTRL 0xff +#define BIT_PESOC_FLASH_DDL_CTRL(x) (((x) & BIT_MASK_PESOC_FLASH_DDL_CTRL) << BIT_SHIFT_PESOC_FLASH_DDL_CTRL) + + +//2 REG_PESOC_SOC_CTRL + +#define BIT_SHIFT_PESOC_GDMA_CFG 16 +#define BIT_MASK_PESOC_GDMA_CFG 0x1fff +#define BIT_PESOC_GDMA_CFG(x) (((x) & BIT_MASK_PESOC_GDMA_CFG) << BIT_SHIFT_PESOC_GDMA_CFG) + +#define BIT_PESOC_MII_LX_SLV_SWAP_SEL BIT(13) +#define BIT_PESOC_MII_LX_MST_SWAP_SEL BIT(12) +#define BIT_PESOC_MII_LX_WRAPPER_EN BIT(11) +#define BIT_PESOC_LX_SLV_SWAP_SEL BIT(10) +#define BIT_PESOC_LX_MST_SWAP_SEL BIT(9) +#define BIT_PESOC_LX_WL_SWAP_SEL BIT(8) + +#define BIT_SHIFT_PESOC_SRAM_MUX_CFG 0 +#define BIT_MASK_PESOC_SRAM_MUX_CFG 0x7 +#define BIT_PESOC_SRAM_MUX_CFG(x) (((x) & BIT_MASK_PESOC_SRAM_MUX_CFG) << BIT_SHIFT_PESOC_SRAM_MUX_CFG) + + +//2 REG_PESOC_PERI_CTRL +#define BIT_SOC_FUNC_SPI_RN BIT(8) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_FW_CTRL_INT0 BIT(24) + +//2 REG_NOT_VALID + +//2 REG_GPIO_SHTDN_CTRL +#define BIT_GPIO_GPK_SHTDN_N BIT(10) +#define BIT_GPIO_GPJ_SHTDN_N BIT(9) +#define BIT_GPIO_GPI_SHTDN_N BIT(8) +#define BIT_GPIO_GPH_SHTDN_N BIT(7) +#define BIT_GPIO_GPG_SHTDN_N BIT(6) +#define BIT_GPIO_GPF_SHTDN_N BIT(5) +#define BIT_GPIO_GPE_SHTDN_N BIT(4) +#define BIT_GPIO_GPD_SHTDN_N BIT(3) +#define BIT_GPIO_GPC_SHTDN_N BIT(2) +#define BIT_GPIO_GPB_SHTDN_N BIT(1) +#define BIT_GPIO_GPA_SHTDN_N BIT(0) + +//2 REG_GPIO_DRIVING_CTRL +#define BIT_GPIO_GPK_DRV_SEL BIT(20) +#define BIT_GPIO_GPJ_DRV_SEL BIT(18) +#define BIT_GPIO_GPI_DRV_SEL BIT(16) +#define BIT_GPIO_GPH_DRV_SEL BIT(14) +#define BIT_GPIO_GPG_DRV_SEL BIT(12) +#define BIT_GPIO_GPF_DRV_SEL BIT(10) +#define BIT_GPIO_GPE_DRV_SEL BIT(8) +#define BIT_GPIO_GPD_DRV_SEL BIT(6) +#define BIT_GPIO_GPC_DRV_SEL BIT(4) +#define BIT_GPIO_GPB_DRV_SEL BIT(2) +#define BIT_GPIO_GPA_DRV_SEL BIT(0) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_GPIO_PULL_CTRL0 + +#define BIT_SHIFT_GPIO_GPB7_PULL_CTRL 30 +#define BIT_MASK_GPIO_GPB7_PULL_CTRL 0x3 +#define BIT_GPIO_GPB7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB7_PULL_CTRL) << BIT_SHIFT_GPIO_GPB7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPB6_PULL_CTRL 0x3 +#define BIT_GPIO_GPB6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB6_PULL_CTRL) << BIT_SHIFT_GPIO_GPB6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPB5_PULL_CTRL 0x3 +#define BIT_GPIO_GPB5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB5_PULL_CTRL) << BIT_SHIFT_GPIO_GPB5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPB4_PULL_CTRL 0x3 +#define BIT_GPIO_GPB4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB4_PULL_CTRL) << BIT_SHIFT_GPIO_GPB4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPB3_PULL_CTRL 0x3 +#define BIT_GPIO_GPB3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB3_PULL_CTRL) << BIT_SHIFT_GPIO_GPB3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPB2_PULL_CTRL 0x3 +#define BIT_GPIO_GPB2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB2_PULL_CTRL) << BIT_SHIFT_GPIO_GPB2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPB1_PULL_CTRL 0x3 +#define BIT_GPIO_GPB1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB1_PULL_CTRL) << BIT_SHIFT_GPIO_GPB1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPB0_PULL_CTRL 0x3 +#define BIT_GPIO_GPB0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB0_PULL_CTRL) << BIT_SHIFT_GPIO_GPB0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPA7_PULL_CTRL 0x3 +#define BIT_GPIO_GPA7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA7_PULL_CTRL) << BIT_SHIFT_GPIO_GPA7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPA6_PULL_CTRL 0x3 +#define BIT_GPIO_GPA6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA6_PULL_CTRL) << BIT_SHIFT_GPIO_GPA6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPA5_PULL_CTRL 0x3 +#define BIT_GPIO_GPA5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA5_PULL_CTRL) << BIT_SHIFT_GPIO_GPA5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPA4_PULL_CTRL 0x3 +#define BIT_GPIO_GPA4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA4_PULL_CTRL) << BIT_SHIFT_GPIO_GPA4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPA3_PULL_CTRL 0x3 +#define BIT_GPIO_GPA3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA3_PULL_CTRL) << BIT_SHIFT_GPIO_GPA3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPA2_PULL_CTRL 0x3 +#define BIT_GPIO_GPA2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA2_PULL_CTRL) << BIT_SHIFT_GPIO_GPA2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPA1_PULL_CTRL 0x3 +#define BIT_GPIO_GPA1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA1_PULL_CTRL) << BIT_SHIFT_GPIO_GPA1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPA0_PULL_CTRL 0x3 +#define BIT_GPIO_GPA0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA0_PULL_CTRL) << BIT_SHIFT_GPIO_GPA0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL1 + +#define BIT_SHIFT_GPIO_GPD7_PULL_CTRL 29 +#define BIT_MASK_GPIO_GPD7_PULL_CTRL 0x7 +#define BIT_GPIO_GPD7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD7_PULL_CTRL) << BIT_SHIFT_GPIO_GPD7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPD6_PULL_CTRL 0x3 +#define BIT_GPIO_GPD6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD6_PULL_CTRL) << BIT_SHIFT_GPIO_GPD6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPD5_PULL_CTRL 0x3 +#define BIT_GPIO_GPD5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD5_PULL_CTRL) << BIT_SHIFT_GPIO_GPD5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPD4_PULL_CTRL 0x3 +#define BIT_GPIO_GPD4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD4_PULL_CTRL) << BIT_SHIFT_GPIO_GPD4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPD3_PULL_CTRL 0x3 +#define BIT_GPIO_GPD3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD3_PULL_CTRL) << BIT_SHIFT_GPIO_GPD3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPD2_PULL_CTRL 0x3 +#define BIT_GPIO_GPD2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD2_PULL_CTRL) << BIT_SHIFT_GPIO_GPD2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPD1_PULL_CTRL 0x3 +#define BIT_GPIO_GPD1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD1_PULL_CTRL) << BIT_SHIFT_GPIO_GPD1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPD0_PULL_CTRL 0x3 +#define BIT_GPIO_GPD0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD0_PULL_CTRL) << BIT_SHIFT_GPIO_GPD0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPC7_PULL_CTRL 0x3 +#define BIT_GPIO_GPC7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC7_PULL_CTRL) << BIT_SHIFT_GPIO_GPC7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPC6_PULL_CTRL 0x3 +#define BIT_GPIO_GPC6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC6_PULL_CTRL) << BIT_SHIFT_GPIO_GPC6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPC5_PULL_CTRL 0x3 +#define BIT_GPIO_GPC5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC5_PULL_CTRL) << BIT_SHIFT_GPIO_GPC5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPC4_PULL_CTRL 0x3 +#define BIT_GPIO_GPC4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC4_PULL_CTRL) << BIT_SHIFT_GPIO_GPC4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPC3_PULL_CTRL 0x3 +#define BIT_GPIO_GPC3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC3_PULL_CTRL) << BIT_SHIFT_GPIO_GPC3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPC2_PULL_CTRL 0x3 +#define BIT_GPIO_GPC2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC2_PULL_CTRL) << BIT_SHIFT_GPIO_GPC2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPC1_PULL_CTRL 0x3 +#define BIT_GPIO_GPC1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC1_PULL_CTRL) << BIT_SHIFT_GPIO_GPC1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPC0_PULL_CTRL 0x3 +#define BIT_GPIO_GPC0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC0_PULL_CTRL) << BIT_SHIFT_GPIO_GPC0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL2 + +#define BIT_SHIFT_GPIO_GPF5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPF5_PULL_CTRL 0x3 +#define BIT_GPIO_GPF5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF5_PULL_CTRL) << BIT_SHIFT_GPIO_GPF5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPF4_PULL_CTRL 0x3 +#define BIT_GPIO_GPF4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF4_PULL_CTRL) << BIT_SHIFT_GPIO_GPF4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPF3_PULL_CTRL 0x3 +#define BIT_GPIO_GPF3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF3_PULL_CTRL) << BIT_SHIFT_GPIO_GPF3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPF2_PULL_CTRL 0x3 +#define BIT_GPIO_GPF2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF2_PULL_CTRL) << BIT_SHIFT_GPIO_GPF2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPF1_PULL_CTRL 0x3 +#define BIT_GPIO_GPF1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF1_PULL_CTRL) << BIT_SHIFT_GPIO_GPF1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPF0_PULL_CTRL 0x3 +#define BIT_GPIO_GPF0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF0_PULL_CTRL) << BIT_SHIFT_GPIO_GPF0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPE7_PULL_CTRL 0x3 +#define BIT_GPIO_GPE7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE7_PULL_CTRL) << BIT_SHIFT_GPIO_GPE7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPE6_PULL_CTRL 0x3 +#define BIT_GPIO_GPE6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE6_PULL_CTRL) << BIT_SHIFT_GPIO_GPE6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPE5_PULL_CTRL 0x3 +#define BIT_GPIO_GPE5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE5_PULL_CTRL) << BIT_SHIFT_GPIO_GPE5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPE4_PULL_CTRL 0x3 +#define BIT_GPIO_GPE4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE4_PULL_CTRL) << BIT_SHIFT_GPIO_GPE4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPE3_PULL_CTRL 0x3 +#define BIT_GPIO_GPE3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE3_PULL_CTRL) << BIT_SHIFT_GPIO_GPE3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPE2_PULL_CTRL 0x3 +#define BIT_GPIO_GPE2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE2_PULL_CTRL) << BIT_SHIFT_GPIO_GPE2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPE1_PULL_CTRL 0x3 +#define BIT_GPIO_GPE1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE1_PULL_CTRL) << BIT_SHIFT_GPIO_GPE1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPE0_PULL_CTRL 0x3 +#define BIT_GPIO_GPE0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE0_PULL_CTRL) << BIT_SHIFT_GPIO_GPE0_PULL_CTRL) + + +//2 REG_NOT_VALID + +#define BIT_SHIFT_GPIO_GPH7_PULL_CTRL 30 +#define BIT_MASK_GPIO_GPH7_PULL_CTRL 0x3 +#define BIT_GPIO_GPH7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH7_PULL_CTRL) << BIT_SHIFT_GPIO_GPH7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPH6_PULL_CTRL 0x3 +#define BIT_GPIO_GPH6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH6_PULL_CTRL) << BIT_SHIFT_GPIO_GPH6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPH5_PULL_CTRL 0x3 +#define BIT_GPIO_GPH5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH5_PULL_CTRL) << BIT_SHIFT_GPIO_GPH5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPH4_PULL_CTRL 0x3 +#define BIT_GPIO_GPH4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH4_PULL_CTRL) << BIT_SHIFT_GPIO_GPH4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPH3_PULL_CTRL 0x3 +#define BIT_GPIO_GPH3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH3_PULL_CTRL) << BIT_SHIFT_GPIO_GPH3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPH2_PULL_CTRL 0x3 +#define BIT_GPIO_GPH2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH2_PULL_CTRL) << BIT_SHIFT_GPIO_GPH2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPH1_PULL_CTRL 0x3 +#define BIT_GPIO_GPH1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH1_PULL_CTRL) << BIT_SHIFT_GPIO_GPH1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPH0_PULL_CTRL 0x3 +#define BIT_GPIO_GPH0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH0_PULL_CTRL) << BIT_SHIFT_GPIO_GPH0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPG7_PULL_CTRL 0x3 +#define BIT_GPIO_GPG7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG7_PULL_CTRL) << BIT_SHIFT_GPIO_GPG7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPG6_PULL_CTRL 0x3 +#define BIT_GPIO_GPG6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG6_PULL_CTRL) << BIT_SHIFT_GPIO_GPG6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPG5_PULL_CTRL 0x3 +#define BIT_GPIO_GPG5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG5_PULL_CTRL) << BIT_SHIFT_GPIO_GPG5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPG4_PULL_CTRL 0x3 +#define BIT_GPIO_GPG4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG4_PULL_CTRL) << BIT_SHIFT_GPIO_GPG4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPG3_PULL_CTRL 0x3 +#define BIT_GPIO_GPG3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG3_PULL_CTRL) << BIT_SHIFT_GPIO_GPG3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPG2_PULL_CTRL 0x3 +#define BIT_GPIO_GPG2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG2_PULL_CTRL) << BIT_SHIFT_GPIO_GPG2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPG1_PULL_CTRL 0x3 +#define BIT_GPIO_GPG1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG1_PULL_CTRL) << BIT_SHIFT_GPIO_GPG1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPG0_PULL_CTRL 0x3 +#define BIT_GPIO_GPG0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG0_PULL_CTRL) << BIT_SHIFT_GPIO_GPG0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL4 + +#define BIT_SHIFT_GPIO_GPJ6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPJ6_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ6_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPJ5_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ5_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPJ4_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ4_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPJ3_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ3_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPJ2_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ2_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPJ1_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ1_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPJ0_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ0_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPI7_PULL_CTRL 0x3 +#define BIT_GPIO_GPI7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI7_PULL_CTRL) << BIT_SHIFT_GPIO_GPI7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPI6_PULL_CTRL 0x3 +#define BIT_GPIO_GPI6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI6_PULL_CTRL) << BIT_SHIFT_GPIO_GPI6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPI5_PULL_CTRL 0x3 +#define BIT_GPIO_GPI5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI5_PULL_CTRL) << BIT_SHIFT_GPIO_GPI5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPI4_PULL_CTRL 0x3 +#define BIT_GPIO_GPI4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI4_PULL_CTRL) << BIT_SHIFT_GPIO_GPI4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPI3_PULL_CTRL 0x3 +#define BIT_GPIO_GPI3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI3_PULL_CTRL) << BIT_SHIFT_GPIO_GPI3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPI2_PULL_CTRL 0x3 +#define BIT_GPIO_GPI2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI2_PULL_CTRL) << BIT_SHIFT_GPIO_GPI2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPI1_PULL_CTRL 0x3 +#define BIT_GPIO_GPI1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI1_PULL_CTRL) << BIT_SHIFT_GPIO_GPI1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPI0_PULL_CTRL 0x3 +#define BIT_GPIO_GPI0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI0_PULL_CTRL) << BIT_SHIFT_GPIO_GPI0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL5 + +#define BIT_SHIFT_GPIO_GPEA_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPEA_PULL_CTRL 0x3 +#define BIT_GPIO_GPEA_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPEA_PULL_CTRL) << BIT_SHIFT_GPIO_GPEA_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE9_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPE9_PULL_CTRL 0x3 +#define BIT_GPIO_GPE9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE9_PULL_CTRL) << BIT_SHIFT_GPIO_GPE9_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE8_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPE8_PULL_CTRL 0x3 +#define BIT_GPIO_GPE8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE8_PULL_CTRL) << BIT_SHIFT_GPIO_GPE8_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK7_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPK7_PULL_CTRL 0x3 +#define BIT_GPIO_GPK7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK7_PULL_CTRL) << BIT_SHIFT_GPIO_GPK7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPK5_PULL_CTRL 0x3 +#define BIT_GPIO_GPK5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK5_PULL_CTRL) << BIT_SHIFT_GPIO_GPK5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPK4_PULL_CTRL 0x3 +#define BIT_GPIO_GPK4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK4_PULL_CTRL) << BIT_SHIFT_GPIO_GPK4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPK3_PULL_CTRL 0x3 +#define BIT_GPIO_GPK3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK3_PULL_CTRL) << BIT_SHIFT_GPIO_GPK3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPK2_PULL_CTRL 0x3 +#define BIT_GPIO_GPK2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK2_PULL_CTRL) << BIT_SHIFT_GPIO_GPK2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPK1_PULL_CTRL 0x3 +#define BIT_GPIO_GPK1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK1_PULL_CTRL) << BIT_SHIFT_GPIO_GPK1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPK0_PULL_CTRL 0x3 +#define BIT_GPIO_GPK0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK0_PULL_CTRL) << BIT_SHIFT_GPIO_GPK0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL6 + +#define BIT_SHIFT_GPIO_GPD9_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPD9_PULL_CTRL 0x3 +#define BIT_GPIO_GPD9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD9_PULL_CTRL) << BIT_SHIFT_GPIO_GPD9_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD8_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPD8_PULL_CTRL 0x3 +#define BIT_GPIO_GPD8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD8_PULL_CTRL) << BIT_SHIFT_GPIO_GPD8_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC9_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPC9_PULL_CTRL 0x3 +#define BIT_GPIO_GPC9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC9_PULL_CTRL) << BIT_SHIFT_GPIO_GPC9_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC8_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPC8_PULL_CTRL 0x3 +#define BIT_GPIO_GPC8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC8_PULL_CTRL) << BIT_SHIFT_GPIO_GPC8_PULL_CTRL) + + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_PERI_PWM0_CTRL +#define BIT_PERI_PWM0_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM0_GT_SEL 24 +#define BIT_MASK_PERI_PWM0_GT_SEL 0xf +#define BIT_PERI_PWM0_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM0_GT_SEL) << BIT_SHIFT_PERI_PWM0_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM0_DUTY 12 +#define BIT_MASK_PERI_PWM0_DUTY 0x3ff +#define BIT_PERI_PWM0_DUTY(x) (((x) & BIT_MASK_PERI_PWM0_DUTY) << BIT_SHIFT_PERI_PWM0_DUTY) + + +#define BIT_SHIFT_PERI_PWM0_PERIOD 0 +#define BIT_MASK_PERI_PWM0_PERIOD 0x3ff +#define BIT_PERI_PWM0_PERIOD(x) (((x) & BIT_MASK_PERI_PWM0_PERIOD) << BIT_SHIFT_PERI_PWM0_PERIOD) + + +//2 REG_PERI_PWM1_CTRL +#define BIT_PERI_PWM1_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM1_GT_SEL 24 +#define BIT_MASK_PERI_PWM1_GT_SEL 0xf +#define BIT_PERI_PWM1_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM1_GT_SEL) << BIT_SHIFT_PERI_PWM1_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM1_DUTY 12 +#define BIT_MASK_PERI_PWM1_DUTY 0x3ff +#define BIT_PERI_PWM1_DUTY(x) (((x) & BIT_MASK_PERI_PWM1_DUTY) << BIT_SHIFT_PERI_PWM1_DUTY) + + +#define BIT_SHIFT_PERI_PWM1_PERIOD 0 +#define BIT_MASK_PERI_PWM1_PERIOD 0x3ff +#define BIT_PERI_PWM1_PERIOD(x) (((x) & BIT_MASK_PERI_PWM1_PERIOD) << BIT_SHIFT_PERI_PWM1_PERIOD) + + +//2 REG_PERI_PWM2_CTRL +#define BIT_PERI_PWM2_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM2_GT_SEL 24 +#define BIT_MASK_PERI_PWM2_GT_SEL 0xf +#define BIT_PERI_PWM2_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM2_GT_SEL) << BIT_SHIFT_PERI_PWM2_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM2_DUTY 12 +#define BIT_MASK_PERI_PWM2_DUTY 0x3ff +#define BIT_PERI_PWM2_DUTY(x) (((x) & BIT_MASK_PERI_PWM2_DUTY) << BIT_SHIFT_PERI_PWM2_DUTY) + + +#define BIT_SHIFT_PERI_PWM2_PERIOD 0 +#define BIT_MASK_PERI_PWM2_PERIOD 0x3ff +#define BIT_PERI_PWM2_PERIOD(x) (((x) & BIT_MASK_PERI_PWM2_PERIOD) << BIT_SHIFT_PERI_PWM2_PERIOD) + + +//2 REG_PERI_PWM3_CTRL +#define BIT_PERI_PWM3_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM3_GT_SEL 24 +#define BIT_MASK_PERI_PWM3_GT_SEL 0xf +#define BIT_PERI_PWM3_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM3_GT_SEL) << BIT_SHIFT_PERI_PWM3_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM3_DUTY 12 +#define BIT_MASK_PERI_PWM3_DUTY 0x3ff +#define BIT_PERI_PWM3_DUTY(x) (((x) & BIT_MASK_PERI_PWM3_DUTY) << BIT_SHIFT_PERI_PWM3_DUTY) + + +#define BIT_SHIFT_PERI_PWM3_PERIOD 0 +#define BIT_MASK_PERI_PWM3_PERIOD 0x3ff +#define BIT_PERI_PWM3_PERIOD(x) (((x) & BIT_MASK_PERI_PWM3_PERIOD) << BIT_SHIFT_PERI_PWM3_PERIOD) + + +//2 REG_PERI_TIM_EVT_CTRL +#define BIT_PERI_GT_EVT3_EN BIT(31) + +#define BIT_SHIFT_PERI_GT_EVT3_SRC_SEL 28 +#define BIT_MASK_PERI_GT_EVT3_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT3_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT3_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT3_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT3_PULSE_DUR 24 +#define BIT_MASK_PERI_GT_EVT3_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT3_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT3_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT3_PULSE_DUR) + +#define BIT_PERI_GT_EVT2_EN BIT(23) + +#define BIT_SHIFT_PERI_GT_EVT2_SRC_SEL 20 +#define BIT_MASK_PERI_GT_EVT2_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT2_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT2_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT2_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT2_PULSE_DUR 16 +#define BIT_MASK_PERI_GT_EVT2_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT2_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT2_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT2_PULSE_DUR) + +#define BIT_PERI_GT_EVT1_EN BIT(15) + +#define BIT_SHIFT_PERI_GT_EVT1_SRC_SEL 12 +#define BIT_MASK_PERI_GT_EVT1_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT1_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT1_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT1_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT1_PULSE_DUR 8 +#define BIT_MASK_PERI_GT_EVT1_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT1_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT1_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT1_PULSE_DUR) + +#define BIT_PERI_GT_EVT0_EN BIT(7) + +#define BIT_SHIFT_PERI_GT_EVT0_SRC_SEL 4 +#define BIT_MASK_PERI_GT_EVT0_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT0_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT0_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT0_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT0_PULSE_DUR 0 +#define BIT_MASK_PERI_GT_EVT0_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT0_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT0_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT0_PULSE_DUR) + + +//2 REG_PERI_EGTIM_CTRL + +#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL 12 +#define BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL 0x3 +#define BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL) + + +#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL 10 +#define BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL 0x3 +#define BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL) + + +#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL 8 +#define BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL 0x3 +#define BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL) + + +//2 REG_NOT_VALID + +#define BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL 4 +#define BIT_MASK_PERI_EGTIM_REF_SIG_SEL 0x3 +#define BIT_PERI_EGTIM_REF_SIG_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_REF_SIG_SEL) << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL) + +#define BIT_PERI_EGTIM_EN BIT(0) + +//2 REG_NOT_VALID + +//2 REG_PEON_CFG + +//2 REG_PEON_STATUS +#define BIT_PEON_SDIO_ALDN BIT(0) + + +//========== Register Address Definition ==================// +#define REG_PEON_PWR_CTRL 0x0200 +#define REG_PON_ISO_CTRL 0x0204 +#define REG_SOC_FUNC_EN 0x0210 +#define REG_SOC_HCI_COM_FUNC_EN 0x0214 +#define REG_SOC_PERI_FUNC0_EN 0x0218 +#define REG_SOC_PERI_FUNC1_EN 0x021C +#define REG_SOC_PERI_BD_FUNC0_EN 0x0220 +#define REG_PESOC_CLK_CTRL 0x0230 +#define REG_PESOC_PERI_CLK_CTRL0 0x0234 +#define REG_PESOC_PERI_CLK_CTRL1 0x0238 +#define REG_PESOC_CLK_CTRL3 0x023C +#define REG_PESOC_HCI_CLK_CTRL0 0x0240 +#define REG_PESOC_COM_CLK_CTRL1 0x0244 +#define REG_PESOC_HW_ENG_CLK_CTRL 0x0248 +#define REG_PESOC_CLK_SEL 0x0250 +#define REG_SYS_ANACK_CAL_CTRL 0x026C +#define REG_OSC32K_CTRL 0x0270 +#define REG_OSC32K_REG_CTRL0 0x0274 +#define REG_OSC32K_REG_CTRL1 0x0278 +#define REG_THERMAL_METER_CTRL 0x027C +#define REG_UART_MUX_CTRL 0x0280 +#define REG_SPI_MUX_CTRL 0x0284 +#define REG_I2C_MUX_CTRL 0x0288 +#define REG_I2S_MUX_CTRL 0x028C +#define REG_HCI_PINMUX_CTRL 0x02A0 +#define REG_WL_PINMUX_CTRL 0x02A4 +#define REG_BT_PINMUX_CTRL 0x02A8 +#define REG_PWM_PINMUX_CTRL 0x02AC +#define REG_CPU_PERIPHERAL_CTRL 0x02C0 +#define REG_HCI_CTRL_STATUS_0 0x02E0 +#define REG_HCI_CTRL_STATUS_1 0x02E4 +#define REG_PESOC_MEM_CTRL 0x0300 +#define REG_PESOC_SOC_CTRL 0x0304 +#define REG_PESOC_PERI_CTRL 0x0308 +#define REG_GPIO_SHTDN_CTRL 0x0320 +#define REG_GPIO_DRIVING_CTRL 0x0324 +#define REG_GPIO_PULL_CTRL0 0x0330 +#define REG_GPIO_PULL_CTRL1 0x0334 +#define REG_GPIO_PULL_CTRL2 0x0338 +#define REG_GPIO_PULL_CTRL3 0x033C +#define REG_GPIO_PULL_CTRL4 0x0340 +#define REG_GPIO_PULL_CTRL5 0x0344 +#define REG_GPIO_PULL_CTRL6 0x0348 +#define REG_PERI_PWM0_CTRL 0x0360 +#define REG_PERI_PWM1_CTRL 0x0364 +#define REG_PERI_PWM2_CTRL 0x0368 +#define REG_PERI_PWM3_CTRL 0x036C +#define REG_PERI_TIM_EVT_CTRL 0x0370 +#define REG_PERI_EGTIM_CTRL 0x0374 +#define REG_PEON_CFG 0x03F0 +#define REG_PEON_STATUS 0x03F4 + + +#endif // end of "#ifndef __INC_RTL8195A_PERI_ON_H" diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_platform.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_platform.h new file mode 100644 index 00000000000..78391806572 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_platform.h @@ -0,0 +1,1310 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if 0 +#ifndef MBED_RTL8195A_PLATFORM_H +#define MBED_RTL8195A_PLATFORM_H + +#define CHIP_ID_8711AM 0xFF +#define CHIP_ID_8195AM 0xFE +#define CHIP_ID_8711AF 0xFD +#define CHIP_ID_8710AF 0xFC +#define CHIP_ID_8711AN 0xFB +#define CHIP_ID_8710AM 0xFA + +#define FW_VERSION (0x0100) +#define FW_SUBVERSION (0x0001) +#define FW_CHIP_ID (0x8195) +#define FW_CHIP_VER (0x01) +#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO +#define FW_INFO_RSV1 (0x00) // the firmware information reserved +#define FW_INFO_RSV2 (0x00) // the firmware information reserved +#define FW_INFO_RSV3 (0x00) // the firmware information reserved +#define FW_INFO_RSV4 (0x00) // the firmware information reserved + +///// ** wlan ** ///// +#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1 +#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data +// Flash Map for Calibration data +#define FLASH_CAL_DATA_BASE 0xA000 +#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset) +#define FLASH_CAL_DATA_SIZE 0x1000 +#define FLASH_SECTOR_SIZE 0x1000 +// SPIC Calibration Data +#define FLASH_SPIC_PARA_OFFSET 0x80 +#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET) +// SDRC Calibration Data +#define FLASH_SDRC_PARA_OFFSET 0x180 +#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET) +// ADC Calibration Data +#define FLASH_ADC_PARA_OFFSET 0x200 +#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET) +/**********/ + +#define ROMVERSION 0x03 +#define ROMINFORMATION ROMVERSION + +//#define SYSTEM_CLK PLATFORM_CLK +//#define TIMER_CLK (32*1000) +//#define PLATFORM_CLK (200000000UL/6*5) // 166MHz + +#define PERIPHERAL_IRQ_ALL_LEVEL 0 +#define PERIPHERAL_IRQ_STATUS 0x04 +#define PERIPHERAL_IRQ_MODE 0x08 +#define PERIPHERAL_IRQ_EN 0x0C +#define LP_PERI_EXT_IRQ_STATUS 0x24 +#define LP_PERI_EXT_IRQ_MODE 0x28 +#define LP_PERI_EXT_IRQ_EN 0x2C + +//3 Peripheral IP Base Address +#define DRAM_BASE 0x30000000 +#define CTRL_BASE 0x40000000 +//#define SYSTEM_CTRL_BASE (CTRL_BASE) +#define PERI_BASE 0x40000000 +//#define PERI_ON_BASE (PERI_BASE) +#define GPIO_BASE 0x40001000 +#define TIMER_BASE 0x40002000 +#define NFC_BASE 0x40002400 +#define VENDOR_BASE 0x40002800 +#define UART3_BASE 0x40003000 +#define LUART_BASE (UART3_BASE) +#define I2C2_BASE 0x40003400 +#define I2C3_BASE 0x40003800 +#define SDRC_BASE 0x40005000 +#define SPIC_BASE 0x40006000 +//#define SPI_FLASH_CTRL_BASE (SPIC_BASE) +#define ADC_BASE 0x40010000 +#define DAC_BASE 0x40011000 +#define UART0_BASE 0x40040000 +#define UART1_BASE 0x40040400 +#define UART2_BASE 0x40040800 +#define RUART_BASE (UART0_BASE) +#define SPI0_BASE 0x40042000 +#define SPI1_BASE 0x40042400 +#define SPI2_BASE 0x40042800 +#define SPI_BASE (SPI0_BASE) +#define SSI0_BASE 0x40042000 +#define SSI1_BASE 0x40042400 +#define SSI2_BASE 0x40042800 +#define SSI_BASE (SSI0_BASE) +#define I2C0_BASE 0x40044000 +#define I2C1_BASE 0x40044400 +#define MII_BASE 0x40050000 +#define SDIOD_BASE 0x40050000 +#define SDIOH_BASE 0x40058000 +#define GDMA0_BASE 0x40060000 +#define GDMA1_BASE 0x40061000 +#define GDMA_BASE (GDMA0_BASE) +#define I2S0_BASE 0x40062000 +#define I2S1_BASE 0x40063000 +#define PCM0_BASE 0x40064000 +#define PCM1_BASE 0x40065000 +#define CRYPTO_BASE 0x40070000 +#define WIFI_BASE 0x40080000 +#define USB_OTG_BASE 0x400C0000 +#define SPI_FLASH_BASE 0x98000000 + +#define GDMA_OFFSET 0x1000 +#define I2S1_OFFSET 0x1000 +#define PCM1_OFFSET 0x1000 +#define SSI_OFFSET 0x400 +#define RUART_OFFSET 0x400 + +#define GDMA_SIZE (GDMA_OFFSET) +#define SSI_SIZE (SSI_OFFSET) +#define RUART_SIZE (RUART_OFFSET) + +#define CPU_CLK_TYPE_NO 6 +#if 0 +enum _BOOT_TYPE_ { + BOOT_FROM_FLASH = 0, + BOOT_FROM_SDIO = 1, + BOOT_FROM_USB = 2, + BOOT_FROM_RSVD = 3, +}; + +enum _EFUSE_CPU_CLK_ { + CLK_200M = 0, + CLK_100M = 1, + CLK_50M = 2, + CLK_25M = 3, + CLK_12_5M = 4, + CLK_4M = 5, +}; +#endif + +// Clock Control Register 0 (REG_PESOC_CLK_CTRL) +#define BIT_CKE_OCP BIT(0) +#define BIT_CKE_PLFM BIT(2) +#define BIT_ACTCK_TRACE BIT(4) +#define BIT_SLPCK_TRACE BIT(5) +#define BIT_SLPCK_VENDOR BIT(7) +#define BIT_ACTCK_VENDOR BIT(6) +#define BIT_ACTCK_FLASH BIT(8) +#define BIT_SLPCK_FLASH BIT(9) +#define BIT_ACTCK_SDRC BIT(10) +#define BIT_SLPCK_SDRC BIT(11) +#define BIT_ACTCK_UART3 BIT(12) +#define BIT_ACTCK_LUART BIT(12) +#define BIT_SLPCK_UART3 BIT(13) +#define BIT_SLPCK_LUART BIT(13) +#define BIT_ACTCK_TIMER BIT(14) +#define BIT_SLPCK_TIMER BIT(15) +#define BIT_ACTCK_GDMA0 BIT(16) +#define BIT_SLPCK_GDMA0 BIT(17) +#define BIT_ACTCK_GDMA1 BIT(18) +#define BIT_SLPCK_GDMA1 BIT(19) +#define BIT_ACTCK_GPIO BIT(24) +#define BIT_SLPCK_GPIO BIT(25) +#define BIT_ACTCK_BTCMD BIT(28) +#define BIT_SLPCK_BTCMD BIT(29) + +// Clock Control Register 1 (REG_PESOC_PERI_CLK_CTRL0) +#define BIT_ACTCK_UART0 BIT(0) +#define BIT_ACTCK_RUART0 BIT(0) +#define BIT_SLPCK_UART0 BIT(1) +#define BIT_SLPCK_RUART0 BIT(1) +#define BIT_ACTCK_UART1 BIT(2) +#define BIT_ACTCK_RUART1 BIT(2) +#define BIT_SLPCK_UART1 BIT(3) +#define BIT_SLPCK_RUART1 BIT(3) +#define BIT_ACTCK_UART2 BIT(4) +#define BIT_ACTCK_RUART2 BIT(4) +#define BIT_SLPCK_UART2 BIT(5) +#define BIT_SLPCK_RUART2 BIT(5) +#define BIT_ACTCK_SPI0 BIT(16) +#define BIT_SLPCK_SPI0 BIT(17) +#define BIT_ACTCK_SPI1 BIT(18) +#define BIT_SLPCK_SPI1 BIT(19) +#define BIT_ACTCK_SPI2 BIT(20) +#define BIT_SLPCK_SPI2 BIT(21) + +// Clock Control Register 2 (REG_PESOC_PERI_CLK_CTRL1) +#define BIT_ACTCK_I2C0 BIT(0) +#define BIT_SLPCK_I2C0 BIT(1) +#define BIT_ACTCK_I2C1 BIT(2) +#define BIT_SLPCK_I2C1 BIT(3) +#define BIT_ACTCK_I2C2 BIT(4) +#define BIT_SLPCK_I2C2 BIT(5) +#define BIT_ACTCK_I2C3 BIT(6) +#define BIT_SLPCK_I2C3 BIT(7) +#define BIT_ACTCK_I2S BIT(16) +#define BIT_SLPCK_I2S BIT(17) +#define BIT_ACTCK_PCM BIT(20) +#define BIT_SLPCK_PCM BIT(21) +#define BIT_ACTCK_ADC BIT(24) +#define BIT_SLPCK_ADC BIT(25) +#define BIT_ACTCK_DAC BIT(28) +#define BIT_SLPCK_DAC BIT(29) + +// Clock Control Register 3 (REG_PESOC_CLK_CTRL3) + +// HCI_CLK_CTRL0 +#define BIT_ACTCK_SDIOD BIT(0) +#define BIT_SLPCK_SDIOD BIT(1) +#define BIT_ACTCK_SDIOH BIT(2) +#define BIT_SLPCK_SDIOH BIT(3) +#define BIT_ACTCK_HCI_OTG BIT(4) +#define BIT_SLPCK_HCI_OTG BIT(5) +#define BIT_ACTCK_MII_MPHY BIT(24) +#define BIT_SLPCK_MII_MPHY BIT(25) + +// COM_CLK_CTRL1 +#define BIT_ACTCK_WLAN BIT(0) +#define BIT_SLPCK_WLAN BIT(1) +#define BIT_ACTCK_SEC_ENG BIT(4) +#define BIT_SLPCK_SEC_ENG BIT(5) +#define BIT_ACTCK_NFC BIT(16) +#define BIT_SLPCK_NFC BIT(17) +#define BIT_CAL_NFC BIT(18) + +//2 REG_PESOC_CLK_SEL +#define BIT_CSEL_SPI1 BIT(18) +#define BIT_CSEL_SCLK_SHF 16 +#define BIT_CSEL_SCLK_MSK 0x3 +#define BIT_CSEL_SCLK(x) (((x) & BIT_CSEL_SCLK_MSK) << BIT_CSEL_SCLK_SHF) + +#define BIT_CSEL_SDR_SHF 10 +#define BIT_CSEL_SDR_MSK 0x3 +#define BIT_CSEL_SDR(x) (((x) & BIT_CSEL_SDR_MSK) << BIT_CSEL_SDR_SHF) + +#define BIT_CSEL_FLASH_SHF 8 +#define BIT_CSEL_FLASH_MSK 0x3 +#define BIT_CSEL_FLASH(x) (((x) & BIT_CSEL_FLASH_MSK) << BIT_CSEL_FLASH_SHF) + +#define BIT_CSEL_TRACE_SHF 4 +#define BIT_CSEL_TRACE_MSK 0x3 +#define BIT_CSEL_TRACE(x) (((x) & BIT_CSEL_TRACE_MSK) << BIT_CSEL_TRACE_SHF) + +// REG_SYS_ANACK_CAL_CTRL +#define BIT_SYS_ANACK_CAL_CMD BIT(15) +#define BIT_SYS_ANACK_CAL_SEL BIT(14) +#define BIT_SYS_ANACK_CAL_RPT_SHF 0 +#define BIT_SYS_ANACK_CAL_RPT_MSK 0x3fff +#define BIT_SYS_ANACK_CAL_RPT(x) (((x) & BIT_SYS_ANACK_CAL_RPT_MSK) << BIT_SYS_ANACK_CAL_RPT_SHF) + +// REG_OSC32K_CTRL +#define BIT_32K_BIAS_CURRENT_SHF 16 +#define BIT_32K_BIAS_CURRENT_MSK 0xffff +#define BIT_32K_BIAS_CURRENT(x) (((x) & BIT_32K_BIAS_CURRENT_MSK) << BIT_32K_BIAS_CURRENT_SHF) + +#define BIT_32K_RESISTOR_COM_SHF 2 +#define BIT_32K_RESISTOR_COM_MSK 0x3 +#define BIT_32K_RESISTOR_COM(x) (((x) & BIT_32K_RESISTOR_COM_MSK) << BIT_32K_RESISTOR_COM_SHF) + +#define BIT_32K_DBG_SEL BIT(1) +#define BIT_32K_POW_CKGEN_EN BIT(0) + +// Function Control Register 0 (REG_SOC_FUNC_EN) +#define BIT_FCTRL_ENABLE BIT(0) +#define BIT_FCTRL_OCP BIT(1) +#define BIT_FCTRL_LXBUS BIT(2) +#define BIT_FCTRL_FLASH BIT(4) +#define BIT_FCTRL_MEM_CTRL BIT(6) +#define BIT_FCTRL_CPU BIT(8) +#define BIT_FCTRL_UART3 BIT(12) +#define BIT_FCTRL_LUART BIT(12) +#define BIT_FCTRL_GDMA0 BIT(13) +#define BIT_FCTRL_GDMA1 BIT(14) +#define BIT_FCTRL_GTIMER BIT(16) +#define BIT_FCTRL_SEC_ENG BIT(20) + +// Function Control Register 1 (REG_SOC_HCI_COM_FUNC_EN) +#define BIT_FCTRL_HCI_SDIOD_ON BIT(0) +#define BIT_FCTRL_HCI_SDIOD_OFF BIT(1) +#define BIT_FCTRL_HCI_SDIOH_ON BIT(2) +#define BIT_FCTRL_HCI_SDIOD_ON_RST_MUX BIT(3) +#define BIT_FCTRL_HCI_OTG BIT(4) +#define BIT_FCTRL_HCI_OTG_RST_MUX BIT(5) +#define BIT_FCTRL_HCI_MII BIT(12) +#define BIT_FCTRL_HCI_SM_SEL BIT(13) +#define BIT_FCTRL_HCI_WL_MACON BIT(16) + +// Function Control Register 1 (REG_SOC_PERI_FUNC0_EN) +#define BIT_FCTRL_UART0 BIT(0) +#define BIT_FCTRL_UART1 BIT(1) +#define BIT_FCTRL_UART2 BIT(2) +#define BIT_FCTRL_SPI0 BIT(8) +#define BIT_FCTRL_SPI1 BIT(9) +#define BIT_FCTRL_SPI2 BIT(10) +#define BIT_FCTRL_I2C0 BIT(16) +#define BIT_FCTRL_I2C1 BIT(17) +#define BIT_FCTRL_I2C2 BIT(18) +#define BIT_FCTRL_I2C3 BIT(19) +#define BIT_FCTRL_I2S0 BIT(24) +#define BIT_FCTRL_I2S1 BIT(25) +#define BIT_FCTRL_PCM0 BIT(28) +#define BIT_FCTRL_PCM1 BIT(29) + +// Function Control Register 1 (REG_SOC_PERI_FUNC1_EN) +#define BIT_FCTRL_ADC0 BIT(0) +#define BIT_FCTRL_DAC0 BIT(4) +#define BIT_FCTRL_DAC1 BIT(5) +#define BIT_FCTRL_GPIO BIT(8) + +// Function Control BD (REG_SOC_PERI_BD_FUNC0_EN) +#define BIT_FCTRL_BD_UART0 BIT(0) +#define BIT_FCTRL_BD_UART1 BIT(1) +#define BIT_FCTRL_BD_UART2 BIT(2) + +#define PERI_PWR_CTRL 0x0200 // REG_PEON_PWR_CTRL +#define PERI_PON_ISO_CTRL 0x0204 // REG_PON_ISO_CTRL +#define PERI_FCTRL_CTRL0 0x0210 // REG_SOC_FUNC_EN +#define PERI_FCTRL_HCI_COM 0x0214 // REG_SOC_HCI_COM_FUNC_EN +#define PERI_FCTRL_CTRL1 0x0218 // REG_SOC_PERI_FUNC0_EN +#define PERI_FCTRL_CTRL2 0x021C // REG_SOC_PERI_FUNC1_EN +#define PERI_FCTRL_BD 0x0220 // REG_SOC_PERI_BD_FUNC0_EN +#define PERI_CCTRL_CTRL0 0x0230 // REG_PESOC_CLK_CTRL +#define PERI_CCTRL_CTRL1 0x0234 // REG_PESOC_PERI_CLK_CTRL0 +#define PERI_CCTRL_CTRL2 0x0238 // REG_PESOC_PERI_CLK_CTRL1 +#define PERI_CCTRL_CTRL3 0x023C // REG_PESOC_CLK_CTRL3 +#define PERI_CCTRL_HCI 0x0240 // REG_PESOC_HCI_CLK_CTRL0 +#define PERI_CCTRL_COM 0x0244 // REG_PESOC_HCI_CLK_CTRL1 +#define PERI_CCTRL_HW_ENG 0x0248 // REG_PESOC_HW_ENG_CLK_CTRL + +#define PERI_CSEL_CTRL0 0x0250 // REG_PESOC_CLK_SEL +#define SYS_ANACK_CAL_CTRL 0x026C +#define OSC32K_CTRL 0x0270 +#define OSC32K_CTRL0 0x0274 +#define OSC32K_CTRL1 0x0278 +#define THERMAL_METER_CTRL 0x027C +#define PERI_MCTRL_UART 0x0280 +#define PERI_MCTRL_SPI 0x0284 +#define PERI_MCTRL_I2C 0x0288 // REG_I2C_MUX_CTRL +#define PERI_MCTRL_I2S 0x028C // REG_I2S_MUX_CTRL +#define PERI_MCTRL_HCI 0x02A0 +#define PERI_MCTRL_WL 0x02A4 +#define PERI_MCTRL_BT 0x02A8 +#define PERI_MCTRL_PWM 0x02AC +#define PERI_FCTRL_CPU 0x02C0 +#define HCI_CTRL_STATUS_0 0x02E0 +#define HCI_CTRL_STATUS_1 0x02E4 +#define PESOC_MEM_CTRL 0x0300 +#define REG_PESOC_MEM_CTRL (PESOC_MEM_CTRL) +#define PESOC_SOC_CTRL 0x0304 // REG_PESOC_SOC_CTRL +#define PESOC_PERI_CTRL 0x0308 +#define GPIO_SHTDN_CTRL 0x0320 +#define GPIO_DRIVING_CTRL 0x0324 +#define GPIO_PULL_CTRL0 0x0330 +#define GPIO_PULL_CTRL1 0x0334 +#define GPIO_PULL_CTRL2 0x0338 +#define GPIO_PULL_CTRL3 0x033C +#define GPIO_PULL_CTRL4 0x0340 +#define GPIO_PULL_CTRL5 0x0344 +#define GPIO_PULL_CTRL6 0x0348 +#define PERI_PWM0_CTRL 0x0360 +#define PERI_PWM1_CTRL 0x0364 +#define PERI_PWM2_CTRL 0x0368 +#define PERI_PWM3_CTRL 0x036C +#define PERI_TIM_EVT_CTRL 0x0370 +#define PERI_EGTIM_CTRL 0x0374 +#define PEON_CFG 0x03F0 +#define PEON_STATUS 0x03F4 + +#define CPU_OPT_WIDTH 0x1F +#define BIT_SYS_PWR_SOC BIT(2) +#define BIT_SYS_PWR_RET_MEM BIT(1) +#define BIT_SYS_PWR_PEON BIT(0) +#define BIT_SYS_ISO_SYSPLL BIT(7) +#define BIT_SYS_ISO_SOC BIT(2) +#define BIT_SYS_ISO_RET_MEM BIT(1) +#define BIT_SYS_ISO_PEON BIT(0) +#define BIT_SYS_AMACRO BIT(31) +#define BIT_SYS_PWRON_TRAP_SHTDN_N BIT(30) +#define BIT_SYS_FEN_SIC_MST BIT(25) +#define BIT_SYS_FEN_SIC BIT(24) +#define BIT_SOC_SYSPEON BIT(4) +#define BIT_SYS_FEN_EELDR BIT(0) +#define BIT_SOC_OCP_IOBUS_CK BIT(2) +#define BIT_SYS_CK_EELDR BIT(1) +#define BIT_SYS_CK_SYSREG BIT(0) + +#define BIT_PESOC_OCP_CPU_CK_SEL_SHF 4 +#define BIT_PESOC_OCP_CPU_CK_SEL_MSK 0x7 +#define BIT_PESOC_OCP_CPU_CK_SEL(x) (((x) & BIT_PESOC_OCP_CPU_CK_SEL_MSK) << BIT_PESOC_OCP_CPU_CK_SEL_SHF) + +#define BIT_PESOC_EELDR_CK_SEL BIT(0) +#define BIT_SYS_EEROM_SWR_PAR_05_00_SHF 24 +#define BIT_SYS_EEROM_SWR_PAR_05_00_MSK 0x3f +#define BIT_SYS_EEROM_SWR_PAR_05_00(x) (((x) & BIT_SYS_EEROM_SWR_PAR_05_00_MSK) << BIT_SYS_EEROM_SWR_PAR_05_00_SHF) + +#define BIT_SYS_EEROM_LDO_PAR_07_04_SHF 20 +#define BIT_SYS_EEROM_LDO_PAR_07_04_MSK 0xf +#define BIT_SYS_EEROM_LDO_PAR_07_04(x) (((x) & BIT_SYS_EEROM_LDO_PAR_07_04_MSK) << BIT_SYS_EEROM_LDO_PAR_07_04_SHF) + +#define BIT_SYS_CHIPPDN_EN BIT(17) +#define BIT_SYS_EEROM_B12V_EN BIT(16) + +#define BIT_SYS_EEROM_VID1_SHF 8 +#define BIT_SYS_EEROM_VID1_MSK 0xff +#define BIT_SYS_EEROM_VID1(x) (((x) & BIT_SYS_EEROM_VID1_MSK) << BIT_SYS_EEROM_VID1_SHF) + +#define BIT_SYS_EEROM_VID0_SHF 0 +#define BIT_SYS_EEROM_VID0_MSK 0xff +#define BIT_SYS_EEROM_VID0(x) (((x) & BIT_SYS_EEROM_VID0_MSK) << BIT_SYS_EEROM_VID0_SHF) + +//2 REG_SYS_EFUSE_SYSCFG1 + +#define BIT_SYS_PDSPL_STL_SHF 24 +#define BIT_SYS_PDSPL_STL_MSK 0x3 +#define BIT_SYS_PDSPL_STL(x) (((x) & BIT_SYS_PDSPL_STL_MSK) << BIT_SYS_PDSPL_STL_SHF) + +#define BIT_SYS_PDSOC_STL_SHF 22 +#define BIT_SYS_PDSOC_STL_MSK 0x3 +#define BIT_SYS_PDSOC_STL(x) (((x) & BIT_SYS_PDSOC_STL_MSK) << BIT_SYS_PDSOC_STL_SHF) + +#define BIT_SYS_PDPON_STL_SHF 20 +#define BIT_SYS_PDPON_STL_MSK 0x3 +#define BIT_SYS_PDPON_STL(x) (((x) & BIT_SYS_PDPON_STL_MSK) << BIT_SYS_PDPON_STL_SHF) + +#define BIT_SYS_SWREG_XRT_SHF 18 +#define BIT_SYS_SWREG_XRT_MSK 0x3 +#define BIT_SYS_SWREG_XRT(x) (((x) & BIT_SYS_SWREG_XRT_MSK) << BIT_SYS_SWREG_XRT_SHF) + +#define BIT_SYS_SWSLC_STL_SHF 16 +#define BIT_SYS_SWSLC_STL_MSK 0x3 +#define BIT_SYS_SWSLC_STL(x) (((x) & BIT_SYS_SWSLC_STL_MSK) << BIT_SYS_SWSLC_STL_SHF) + +#define BIT_SYS_EEROM_SWR_PAR_46_45_SHF 14 +#define BIT_SYS_EEROM_SWR_PAR_46_45_MSK 0x3 +#define BIT_SYS_EEROM_SWR_PAR_46_45(x) (((x) & BIT_SYS_EEROM_SWR_PAR_46_45_MSK) << BIT_SYS_EEROM_SWR_PAR_46_45_SHF) + +#define BIT_SYS_EEROM_SWR_PAR_40_39_SHF 12 +#define BIT_SYS_EEROM_SWR_PAR_40_39_MSK 0x3 +#define BIT_SYS_EEROM_SWR_PAR_40_39(x) (((x) & BIT_SYS_EEROM_SWR_PAR_40_39_MSK) << BIT_SYS_EEROM_SWR_PAR_40_39_SHF) + +#define BIT_SYS_EEROM_SWR_PAR_33_26_SHF 4 +#define BIT_SYS_EEROM_SWR_PAR_33_26_MSK 0xff +#define BIT_SYS_EEROM_SWR_PAR_33_26(x) (((x) & BIT_SYS_EEROM_SWR_PAR_33_26_MSK) << BIT_SYS_EEROM_SWR_PAR_33_26_SHF) + +#define BIT_SYS_EEROM_SWSLD_VOL_SHF 0 +#define BIT_SYS_EEROM_SWSLD_VOL_MSK 0x7 +#define BIT_SYS_EEROM_SWSLD_VOL(x) (((x) & BIT_SYS_EEROM_SWSLD_VOL_MSK) << BIT_SYS_EEROM_SWSLD_VOL_SHF) + +//2 REG_SYS_EFUSE_SYSCFG2 + +#define BIT_SYS_EERROM_ANAPAR_SPLL_24_15_SHF 21 +#define BIT_SYS_EERROM_ANAPAR_SPLL_24_15_MSK 0x3ff +#define BIT_SYS_EERROM_ANAPAR_SPLL_24_15(x) (((x) & BIT_SYS_EERROM_ANAPAR_SPLL_24_15_MSK) << BIT_SYS_EERROM_ANAPAR_SPLL_24_15_SHF) + +#define BIT_SYS_EEROM_ANAPAR_SPLL_05_02_SHF 16 +#define BIT_SYS_EEROM_ANAPAR_SPLL_05_02_MSK 0xf +#define BIT_SYS_EEROM_ANAPAR_SPLL_05_02(x) (((x) & BIT_SYS_EEROM_ANAPAR_SPLL_05_02_MSK) << BIT_SYS_EEROM_ANAPAR_SPLL_05_02_SHF) + +#define BIT_SYS_EEROM_XTAL_STEL_SEL_SHF 12 +#define BIT_SYS_EEROM_XTAL_STEL_SEL_MSK 0x3 +#define BIT_SYS_EEROM_XTAL_STEL_SEL(x) (((x) & BIT_SYS_EEROM_XTAL_STEL_SEL_MSK) << BIT_SYS_EEROM_XTAL_STEL_SEL_SHF) + +#define BIT_SYS_EEROM_XTAL_FREQ_SEL_SHF 8 +#define BIT_SYS_EEROM_XTAL_FREQ_SEL_MSK 0xf +#define BIT_SYS_EEROM_XTAL_FREQ_SEL(x) (((x) & BIT_SYS_EEROM_XTAL_FREQ_SEL_MSK) << BIT_SYS_EEROM_XTAL_FREQ_SEL_SHF) + +//2 REG_SYS_EFUSE_SYSCFG3 +#define BIT_SYS_DBG_PINGP_SHF 28 +#define BIT_SYS_DBG_PINGP_MSK 0xf +#define BIT_SYS_DBG_PINGP(x) (((x) & BIT_SYS_DBG_PINGP_MSK) << BIT_SYS_DBG_PINGP_SHF) + +#define BIT_SYS_DBG_SEL_SHF 16 +#define BIT_SYS_DBG_SEL_MSK 0xfff +#define BIT_SYS_DBG_SEL(x) (((x) & BIT_SYS_DBG_SEL_MSK) << BIT_SYS_DBG_SEL_SHF) + +#define BIT_SYS_DBGBY3_LOC_SEL_SHF 14 +#define BIT_SYS_DBGBY3_LOC_SEL_MSK 0x3 +#define BIT_SYS_DBGBY3_LOC_SEL(x) (((x) & BIT_SYS_DBGBY3_LOC_SEL_MSK) << BIT_SYS_DBGBY3_LOC_SEL_SHF) + +#define BIT_SYS_DBGBY2_LOC_SEL_SHF 12 +#define BIT_SYS_DBGBY2_LOC_SEL_MSK 0x3 +#define BIT_SYS_DBGBY2_LOC_SEL(x) (((x) & BIT_SYS_DBGBY2_LOC_SEL_MSK) << BIT_SYS_DBGBY2_LOC_SEL_SHF) + +#define BIT_SYS_DBGBY1_LOC_SEL_SHF 10 +#define BIT_SYS_DBGBY1_LOC_SEL_MSK 0x3 +#define BIT_SYS_DBGBY1_LOC_SEL(x) (((x) & BIT_SYS_DBGBY1_LOC_SEL_MSK) << BIT_SYS_DBGBY1_LOC_SEL_SHF) + +#define BIT_SYS_DBGBY0_LOC_SEL_SHF 8 +#define BIT_SYS_DBGBY0_LOC_SEL_MSK 0x3 +#define BIT_SYS_DBGBY0_LOC_SEL(x) (((x) & BIT_SYS_DBGBY0_LOC_SEL_MSK) << BIT_SYS_DBGBY0_LOC_SEL_SHF) + +#define BIT_SYS_EEROM_ANAPAR_SPLL_49 BIT(3) + +#define BIT_SYS_EEROM_ANAPAR_SPLL_27_25_SHF 0 +#define BIT_SYS_EEROM_ANAPAR_SPLL_27_25_MSK 0x7 +#define BIT_SYS_EEROM_ANAPAR_SPLL_27_25(x) (((x) & BIT_SYS_EEROM_ANAPAR_SPLL_27_25_MSK) << BIT_SYS_EEROM_ANAPAR_SPLL_27_25_SHF) + +#define BIT_SYS_GPIOA_E2_SHF 1 +#define BIT_SYS_GPIOA_E2_MSK 0x7 +#define BIT_SYS_GPIOA_E2(x) (((x) & BIT_SYS_GPIOA_E2_MSK) << BIT_SYS_GPIOA_E2_SHF) + +#define BIT_SYS_GPIOA_H3L1 BIT(0) + +#define BIT_SYS_SPIC_INIT_BAUD_RATE_SEL_SHF 26 +#define BIT_SYS_SPIC_INIT_BAUD_RATE_SEL_MSK 0x3 +#define BIT_SYS_SPIC_INIT_BAUD_RATE_SEL(x) (((x) & BIT_SYS_SPIC_INIT_BAUD_RATE_SEL_MSK) << BIT_SYS_SPIC_INIT_BAUD_RATE_SEL_SHF) + +#define BIT_SYS_CPU_CLK_SEL_SHF 24 +#define BIT_SYS_CPU_CLK_SEL_MSK 0x3 +#define BIT_SYS_CPU_CLK_SEL(x) (((x) & BIT_SYS_CPU_CLK_SEL_MSK) << BIT_SYS_CPU_CLK_SEL_SHF) + +//2 REG_SYS_EFUSE_SYSCFG7 +#define BIT_SYS_MEM_RMV_SIGN BIT(31) +#define BIT_SYS_MEM_RMV_1PRF1 BIT(29) +#define BIT_SYS_MEM_RMV_1PRF0 BIT(28) +#define BIT_SYS_MEM_RMV_1PSR BIT(27) +#define BIT_SYS_MEM_RMV_1PHSR BIT(26) +#define BIT_SYS_MEM_RMV_ROM BIT(25) + +#define BIT_SYS_MEM_RME_CPU_SHF 22 +#define BIT_SYS_MEM_RME_CPU_MSK 0x7 +#define BIT_SYS_MEM_RME_CPU(x) (((x) & BIT_SYS_MEM_RME_CPU_MSK) << BIT_SYS_MEM_RME_CPU_SHF) + +#define BIT_SYS_MEM_RME_WLAN_SHF 19 +#define BIT_SYS_MEM_RME_WLAN_MSK 0x7 +#define BIT_SYS_MEM_RME_WLAN(x) (((x) & BIT_SYS_MEM_RME_WLAN_MSK) << BIT_SYS_MEM_RME_WLAN_SHF) + +#define BIT_SYS_MEM_RME_USB BIT(18) +#define BIT_SYS_MEM_RME_SDIO BIT(17) + +//2 REG_SYS_REGU_CTRL0 +#define BIT_SYS_REGU_LDO25M_ADJ_SHF 20 +#define BIT_SYS_REGU_LDO25M_ADJ_MSK 0xf +#define BIT_SYS_REGU_LDO25M_ADJ(x) (((x) & BIT_SYS_REGU_LDO25M_ADJ_MSK) << BIT_SYS_REGU_LDO25M_ADJ_SHF) + +#define BIT_SYS_REGU_ANACK_4M_EN BIT(19) +#define BIT_SYS_REGU_ANACK_4M_SEL BIT(18) +#define BIT_SYS_REGU_PC_EF_EN BIT(17) +#define BIT_SYS_REGU_LDOH12_SLP_EN BIT(16) + +#define BIT_SYS_REGU_LDOH12_ADJ_SHF 12 +#define BIT_SYS_REGU_LDOH12_ADJ_MSK 0xf +#define BIT_SYS_REGU_LDOH12_ADJ(x) (((x) & BIT_SYS_REGU_LDOH12_ADJ_MSK) << BIT_SYS_REGU_LDOH12_ADJ_SHF) + +#define BIT_SYS_REGU_LDO25E_ADJ_SHF 8 +#define BIT_SYS_REGU_LDO25E_ADJ_MSK 0xf +#define BIT_SYS_REGU_LDO25E_ADJ(x) (((x) & BIT_SYS_REGU_LDO25E_ADJ_MSK) << BIT_SYS_REGU_LDO25E_ADJ_SHF) + +#define BIT_SYS_REGU_DSLEPM_EN BIT(7) +#define BIT_SYS_REGU_PC_33V_EN BIT(3) +#define BIT_SYS_REGU_PC_EF25_EN BIT(2) +#define BIT_SYS_REGU_LDO25M_EN BIT(1) +#define BIT_SYS_REGU_LDO25E_EN BIT(0) + +#define BIT_SYS_SWR12_COMP_R2_SHF 30 +#define BIT_SYS_SWR12_COMP_R2_MSK 0x3 +#define BIT_SYS_SWR12_COMP_R2(x) (((x) & BIT_SYS_SWR12_COMP_R2_MSK) << BIT_SYS_SWR12_COMP_R2_SHF) + +#define BIT_SYS_SWR12_COMP_R1_SHF 28 +#define BIT_SYS_SWR12_COMP_R1_MSK 0x3 +#define BIT_SYS_SWR12_COMP_R1(x) (((x) & BIT_SYS_SWR12_COMP_R1_MSK) << BIT_SYS_SWR12_COMP_R1_SHF) + +#define BIT_SYS_SWR12_COMP_C3_SHF 26 +#define BIT_SYS_SWR12_COMP_C3_MSK 0x3 +#define BIT_SYS_SWR12_COMP_C3(x) (((x) & BIT_SYS_SWR12_COMP_C3_MSK) << BIT_SYS_SWR12_COMP_C3_SHF) + +#define BIT_SYS_SWR12_COMP_C2_SHF 24 +#define BIT_SYS_SWR12_COMP_C2_MSK 0x3 +#define BIT_SYS_SWR12_COMP_C2(x) (((x) & BIT_SYS_SWR12_COMP_C2_MSK) << BIT_SYS_SWR12_COMP_C2_SHF) + +#define BIT_SYS_SWR12_COMP_C1_SHF 22 +#define BIT_SYS_SWR12_COMP_C1_MSK 0x3 +#define BIT_SYS_SWR12_COMP_C1(x) (((x) & BIT_SYS_SWR12_COMP_C1_MSK) << BIT_SYS_SWR12_COMP_C1_SHF) + +#define BIT_SYS_SWR12_COMP_TYPE_L BIT(21) +#define BIT_SYS_SWR12_FPWM_MD BIT(20) + +#define BIT_SYS_SPSLDO_VOL_SHF 17 +#define BIT_SYS_SPSLDO_VOL_MSK 0x7 +#define BIT_SYS_SPSLDO_VOL(x) (((x) & BIT_SYS_SPSLDO_VOL_MSK) << BIT_SYS_SPSLDO_VOL_SHF) + +#define BIT_SYS_SWR12_IN_SHF 14 +#define BIT_SYS_SWR12_IN_MSK 0x7 +#define BIT_SYS_SWR12_IN(x) (((x) & BIT_SYS_SWR12_IN_MSK) << BIT_SYS_SWR12_IN_SHF) + +#define BIT_SYS_SWR12_STD_SHF 12 +#define BIT_SYS_SWR12_STD_MSK 0x3 +#define BIT_SYS_SWR12_STD(x) (((x) & BIT_SYS_SWR12_STD_MSK) << BIT_SYS_SWR12_STD_SHF) + +#define BIT_SYS_SWR12_VOL_SHF 8 +#define BIT_SYS_SWR12_VOL_MSK 0xf +#define BIT_SYS_SWR12_VOL(x) (((x) & BIT_SYS_SWR12_VOL_MSK) << BIT_SYS_SWR12_VOL_SHF) + +#define BIT_SYS_SWR_LDO BIT(0) +#define BIT_SYS_SWR BIT(1) + +//2 REG_SYS_SWR_CTRL1 +#define BIT_SYS_SW12_PFM_SEL BIT(25) +#define BIT_SYS_SW12_AUTO_ZCD_L BIT(24) +#define BIT_SYS_SW12_AUTO_MODE BIT(23) +#define BIT_SYS_SW12_LDOF_L BIT(22) +#define BIT_SYS_SW12_OCPS_L BIT(21) + +#define BIT_SYS_SW12_TBOX_SHF 17 +#define BIT_SYS_SW12_TBOX_MSK 0x3 +#define BIT_SYS_SW12_TBOX(x) (((x) & BIT_SYS_SW12_TBOX_MSK) << BIT_SYS_SW12_TBOX_SHF) + +#define BIT_SYS_SW12_NONOVRLAP_DLY_SHF 15 +#define BIT_SYS_SW12_NONOVRLAP_DLY_MSK 0x3 +#define BIT_SYS_SW12_NONOVRLAP_DLY(x) (((x) & BIT_SYS_SW12_NONOVRLAP_DLY_MSK) << BIT_SYS_SW12_NONOVRLAP_DLY_SHF) + +#define BIT_SYS_SW12_CLAMP_DUTY BIT(14) +#define BIT_SYS_SWR12_BYPASS_SSR BIT(13) +#define BIT_SYS_SWR12_ZCDOUT_EN BIT(12) +#define BIT_SYS_SWR12_POW_ZCD BIT(11) +#define BIT_SYS_SW12_AREN BIT(10) + +#define BIT_SYS_SWR12_OCP_CUR_SHF 7 +#define BIT_SYS_SWR12_OCP_CUR_MSK 0x7 +#define BIT_SYS_SWR12_OCP_CUR(x) (((x) & BIT_SYS_SWR12_OCP_CUR_MSK) << BIT_SYS_SWR12_OCP_CUR_SHF) + +#define BIT_SYS_SWR12_OCP_EN BIT(6) + +#define BIT_SYS_SWR12_SAWTOOTH_CF_L_SHF 4 +#define BIT_SYS_SWR12_SAWTOOTH_CF_L_MSK 0x3 +#define BIT_SYS_SWR12_SAWTOOTH_CF_L(x) (((x) & BIT_SYS_SWR12_SAWTOOTH_CF_L_MSK) << BIT_SYS_SWR12_SAWTOOTH_CF_L_SHF) + +#define BIT_SYS_SWR12_SAWTOOTH_CFC_L_SHF 2 +#define BIT_SYS_SWR12_SAWTOOTH_CFC_L_MSK 0x3 +#define BIT_SYS_SWR12_SAWTOOTH_CFC_L(x) (((x) & BIT_SYS_SWR12_SAWTOOTH_CFC_L_MSK) << BIT_SYS_SWR12_SAWTOOTH_CFC_L_SHF) + +#define BIT_SYS_SWR12_COMP_R3_SHF 0 +#define BIT_SYS_SWR12_COMP_R3_MSK 0x3 +#define BIT_SYS_SWR12_COMP_R3(x) (((x) & BIT_SYS_SWR12_COMP_R3_MSK) << BIT_SYS_SWR12_COMP_R3_SHF) + +//2 REG_SYS_XTAL_CTRL0 +#define BIT_SYS_XTAL_BGMB BIT(0) +#define BIT_SYS_XTAL BIT(1) + +#define BIT_SYS_XTAL_GMP_SHF 8 +#define BIT_SYS_XTAL_GMP_MSK 0x1f +#define BIT_SYS_XTAL_GMP(x) (((x) & BIT_SYS_XTAL_GMP_MSK) << BIT_SYS_XTAL_GMP_SHF) + +#define BIT_SYS_XTAL_GMN_SHF 13 +#define BIT_SYS_XTAL_GMN_MSK 0x1f +#define BIT_SYS_XTAL_GMN(x) (((x) & BIT_SYS_XTAL_GMN_MSK) << BIT_SYS_XTAL_GMN_SHF) + +#define BIT_SYS_XTAL_SC_XI_SHF 18 +#define BIT_SYS_XTAL_SC_XI_MSK 0x3f +#define BIT_SYS_XTAL_SC_XI(x) (((x) & BIT_SYS_XTAL_SC_XI_MSK) << BIT_SYS_XTAL_SC_XI_SHF) + +#define BIT_SYS_XTAL_SC_XO_SHF 24 +#define BIT_SYS_XTAL_SC_XO_MSK 0x3f +#define BIT_SYS_XTAL_SC_XO(x) (((x) & BIT_SYS_XTAL_SC_XO_MSK) << BIT_SYS_XTAL_SC_XO_SHF) + +#define BIT_SYS_XTAL_XQSEL_RF BIT(30) +#define BIT_SYS_XTAL_XQSEL BIT(31) + +//2 REG_SYS_XTAL_CTRL1 +#define BIT_SYS_XTAL_DRV_AGPIO_SHF 19 +#define BIT_SYS_XTAL_DRV_AGPIO_MSK 0x3 +#define BIT_SYS_XTAL_DRV_AGPIO(x) ((x & BIT_SYS_XTAL_DRV_AGPIO_MSK) << BIT_SYS_XTAL_DRV_AGPIO_SHF) +#define BIT_SYS_XTAL_AGPIO_SEL BIT(21) +#define BIT_SYS_XTAL_DELAY_WLAFE BIT(22) +#define BIT_SYS_XTAL_DELAY_USB BIT(23) +#define BIT_SYS_XTAL_DELAY_SYSPLL BIT(24) + +#define BIT_SYS_XTAL_COUNTER_MUX_SHF 25 +#define BIT_SYS_XTAL_COUNTER_MUX_MSK 0x3 +#define BIT_SYS_XTAL_COUNTER_MUX(x) ((x & BIT_SYS_XTAL_COUNTER_MUX_MSK) << BIT_SYS_XTAL_COUNTER_MUX_SHF) + +#define BIT_SYS_XTAL_AGPIO_SHF 16 +#define BIT_SYS_XTAL_AGPIO_MSK 0x7 +#define BIT_SYS_XTAL_AGPIO(x) ((x & BIT_SYS_XTAL_AGPIO_MSK) << BIT_SYS_XTAL_AGPIO_SHF) + +#define BIT_SYS_XTAL_DRV_SYSPLL_SHF 14 +#define BIT_SYS_XTAL_DRV_SYSPLL_MSK 0x3 +#define BIT_SYS_XTAL_DRV_SYSPLL(x) ((x & BIT_SYS_XTAL_DRV_SYSPLL_MSK) << BIT_SYS_XTAL_DRV_SYSPLL_SHF) + +#define BIT_SYS_XTAL_GATE_SYSPLL BIT(13) + +#define BIT_SYS_XTAL_DRV_USB_SHF 11 +#define BIT_SYS_XTAL_DRV_USB_MSK 0x3 +#define BIT_SYS_XTAL_DRV_USB(x) (((x) & BIT_SYS_XTAL_DRV_USB_MSK) << BIT_SYS_XTAL_DRV_USB_SHF) + +#define BIT_SYS_XTAL_GATE_USB BIT(10) + +#define BIT_SYS_XTAL_DRV_WLAFE_SHF 8 +#define BIT_SYS_XTAL_DRV_WLAFE_MSK 0x3 +#define BIT_SYS_XTAL_DRV_WLAFE(x) (((x) & BIT_SYS_XTAL_DRV_WLAFE_MSK) << BIT_SYS_XTAL_DRV_WLAFE_SHF) + +#define BIT_SYS_XTAL_GATE_WLAFE BIT(7) + +#define BIT_SYS_XTAL_DRV_RF2_SHF 5 +#define BIT_SYS_XTAL_DRV_RF2_MSK 0x3 +#define BIT_SYS_XTAL_DRV_RF2(x) (((x) & BIT_SYS_XTAL_DRV_RF2_MSK) << BIT_SYS_XTAL_DRV_RF2_SHF) + +#define BIT_SYS_XTAL_GATE_RF2 BIT(4) + +#define BIT_SYS_XTAL_DRV_RF1_SHF 3 +#define BIT_SYS_XTAL_DRV_RF1_MSK 0x3 +#define BIT_SYS_XTAL_DRV_RF1(x) (((x) & BIT_SYS_XTAL_DRV_RF1_MSK) << BIT_SYS_XTAL_DRV_RF1_SHF) + +#define BIT_SYS_XTAL_GATE_RF1 BIT(1) + +#define BIT_SYS_XTAL_LDO_SHF 0 +#define BIT_SYS_XTAL_LDO_MSK 0x3 +#define BIT_SYS_XTAL_LDO(x) (((x) & BIT_SYS_XTAL_LDO_MSK) << BIT_SYS_XTAL_LDO_SHF) + +#define BIT_SYS_SYSPLL_LPF_R3_SHF 29 +#define BIT_SYS_SYSPLL_LPF_R3_MSK 0x7 +#define BIT_SYS_SYSPLL_LPF_R3(x) (((x) & BIT_SYS_SYSPLL_LPF_R3_MSK) << BIT_SYS_SYSPLL_LPF_R3_SHF) + +#define BIT_SYS_SYSPLL_LPF_CS_SHF 27 +#define BIT_SYS_SYSPLL_LPF_CS_MSK 0x3 +#define BIT_SYS_SYSPLL_LPF_CS(x) (((x) & BIT_SYS_SYSPLL_LPF_CS_MSK) << BIT_SYS_SYSPLL_LPF_CS_SHF) + +#define BIT_SYS_SYSPLL_LPF_CP_SHF 25 +#define BIT_SYS_SYSPLL_LPF_CP_MSK 0x3 +#define BIT_SYS_SYSPLL_LPF_CP(x) (((x) & BIT_SYS_SYSPLL_LPF_CP_MSK) << BIT_SYS_SYSPLL_LPF_CP_SHF) + +#define BIT_SYS_SYSPLL_LPF_C3_SHF 23 +#define BIT_SYS_SYSPLL_LPF_C3_MSK 0x3 +#define BIT_SYS_SYSPLL_LPF_C3(x) (((x) & BIT_SYS_SYSPLL_LPF_C3_MSK) << BIT_SYS_SYSPLL_LPF_C3_SHF) + +#define BIT_SYS_SYSPLL_WDOG_ENB BIT(22) +#define BIT_SYS_SYSPLL_CKTST_EN BIT(21) + +#define BIT_SYS_SYSPLL_MONCK_SEL_SHF 18 +#define BIT_SYS_SYSPLL_MONCK_SEL_MSK 0x7 +#define BIT_SYS_SYSPLL_MONCK_SEL(x) (((x) & BIT_SYS_SYSPLL_MONCK_SEL_MSK) << BIT_SYS_SYSPLL_MONCK_SEL_SHF) + +#define BIT_SYS_SYSPLL_CP_IOFFSET_SHF 13 +#define BIT_SYS_SYSPLL_CP_IOFFSET_MSK 0x1f +#define BIT_SYS_SYSPLL_CP_IOFFSET(x) (((x) & BIT_SYS_SYSPLL_CP_IOFFSET_MSK) << BIT_SYS_SYSPLL_CP_IOFFSET_SHF) + +#define BIT_SYS_SYSPLL_CP_IDOUBLE BIT(12) + +#define BIT_SYS_SYSPLL_CP_BIAS_SHF 9 +#define BIT_SYS_SYSPLL_CP_BIAS_MSK 0x7 +#define BIT_SYS_SYSPLL_CP_BIAS(x) (((x) & BIT_SYS_SYSPLL_CP_BIAS_MSK) << BIT_SYS_SYSPLL_CP_BIAS_SHF) + +#define BIT_SYS_SYSPLL_FREF_EDGE BIT(8) +#define BIT_SYS_SYSPLL_EN BIT(1) +#define BIT_SYS_SYSPLL_LVPC_EN BIT(0) + +//2 REG_SYS_SYSPLL_CTRL1 +#define BIT_SYS_SYSPLL_CK500K_SEL BIT(15) +#define BIT_SYS_SYSPLL_CK200M_EN BIT(14) +#define BIT_SYS_SYSPLL_CKSDR_EN BIT(13) + +#define BIT_SYS_SYSPLL_CKSDR_DIV_SHF 11 +#define BIT_SYS_SYSPLL_CKSDR_DIV_MSK 0x3 +#define BIT_SYS_SYSPLL_CKSDR_DIV(x) (((x) & BIT_SYS_SYSPLL_CKSDR_DIV_MSK) << BIT_SYS_SYSPLL_CKSDR_DIV_SHF) + +#define BIT_SYS_SYSPLL_CK24P576_EN BIT(9) +#define BIT_SYS_SYSPLL_CK22P5792_EN BIT(8) +#define BIT_SYS_SYSPLL_CK_PS_EN BIT(6) + +#define BIT_SYS_SYSPLL_CK_PS_SEL_SHF 3 +#define BIT_SYS_SYSPLL_CK_PS_SEL_MSK 0x7 +#define BIT_SYS_SYSPLL_CK_PS_SEL(x) (((x) & BIT_SYS_SYSPLL_CK_PS_SEL_MSK) << BIT_SYS_SYSPLL_CK_PS_SEL_SHF) + +#define BIT_SYS_SYSPLL_LPF_RS_SHF 0 +#define BIT_SYS_SYSPLL_LPF_RS_MSK 0x7 +#define BIT_SYS_SYSPLL_LPF_RS(x) (((x) & BIT_SYS_SYSPLL_LPF_RS_MSK) << BIT_SYS_SYSPLL_LPF_RS_SHF) + +//2 REG_SYS_SYSPLL_CTRL2 +#define BIT_XTAL_DRV_RF_LATCH_SHF 0 +#define BIT_XTAL_DRV_RF_LATCH_MSK 0xffffffffL +#define BIT_XTAL_DRV_RF_LATCH(x) (((x) & BIT_XTAL_DRV_RF_LATCH_MSK) << BIT_XTAL_DRV_RF_LATCH_SHF) + +#define BIT_PESOC_CPU_OCP_CK_SEL_SHF 0 +#define BIT_PESOC_CPU_OCP_CK_SEL_MSK 0x7 +#define BIT_PESOC_CPU_OCP_CK_SEL(x) (((x) & BIT_PESOC_CPU_OCP_CK_SEL_MSK) << BIT_PESOC_CPU_OCP_CK_SEL_SHF) + +//2 REG_SYS_ANA_TIM_CTRL +#define BIT_SYS_ANACK_TU_TIME_SHF 16 +#define BIT_SYS_ANACK_TU_TIME_MSK 0x3f +#define BIT_SYS_ANACK_TU_TIME(x) (((x) & BIT_SYS_ANACK_TU_TIME_MSK) << BIT_SYS_ANACK_TU_TIME_SHF) + +#define BIT_SYS_DSBYCNT_EN BIT(15) + +#define BIT_SYS_DSTDY_TIM_SCAL_SHF 8 +#define BIT_SYS_DSTDY_TIM_SCAL_MSK 0xf +#define BIT_SYS_DSTDY_TIM_SCAL(x) (((x) & BIT_SYS_DSTDY_TIM_SCAL_MSK) << BIT_SYS_DSTDY_TIM_SCAL_SHF) + +#define BIT_SYS_DSTBY_TIM_PERIOD_SHF 0 +#define BIT_SYS_DSTBY_TIM_PERIOD_MSK 0xff +#define BIT_SYS_DSTBY_TIM_PERIOD(x) (((x) & BIT_SYS_DSTBY_TIM_PERIOD_MSK) << BIT_SYS_DSTBY_TIM_PERIOD_SHF) + +#define BIT_SYS_REGU_ASIF_EN_SHF 24 +#define BIT_SYS_REGU_ASIF_EN_MSK 0xff +#define BIT_SYS_REGU_ASIF_EN(x) (((x) & BIT_SYS_REGU_ASIF_EN_MSK) << BIT_SYS_REGU_ASIF_EN_SHF) + +#define BIT_SYS_REGU_ASIF_THP_DA_SHF 20 +#define BIT_SYS_REGU_ASIF_THP_DA_MSK 0x3 +#define BIT_SYS_REGU_ASIF_THP_DA(x) (((x) & BIT_SYS_REGU_ASIF_THP_DA_MSK) << BIT_SYS_REGU_ASIF_THP_DA_SHF) + +#define BIT_SYS_REGU_ASIF_TPD_CK_SHF 18 +#define BIT_SYS_REGU_ASIF_TPD_CK_MSK 0x3 +#define BIT_SYS_REGU_ASIF_TPD_CK(x) (((x) & BIT_SYS_REGU_ASIF_TPD_CK_MSK) << BIT_SYS_REGU_ASIF_TPD_CK_SHF) + +#define BIT_SYS_REGU_ASIF_TSP_DA_SHF 16 +#define BIT_SYS_REGU_ASIF_TSP_DA_MSK 0x3 +#define BIT_SYS_REGU_ASIF_TSP_DA(x) (((x) & BIT_SYS_REGU_ASIF_TSP_DA_MSK) << BIT_SYS_REGU_ASIF_TSP_DA_SHF) + +#define BIT_SYS_REGU_ASIF_POLL BIT(15) +#define BIT_SYS_REGU_ASIF_MODE BIT(14) +#define BIT_SYS_REGU_ASIF_WE BIT(12) + +#define BIT_SYS_REGU_ASIF_AD_SHF 8 +#define BIT_SYS_REGU_ASIF_AD_MSK 0xf +#define BIT_SYS_REGU_ASIF_AD(x) (((x) & BIT_SYS_REGU_ASIF_AD_MSK) << BIT_SYS_REGU_ASIF_AD_SHF) + +#define BIT_SYS_REGU_ASIF_WD_SHF 0 +#define BIT_SYS_REGU_ASIF_WD_MSK 0xff +#define BIT_SYS_REGU_ASIF_WD(x) (((x) & BIT_SYS_REGU_ASIF_WD_MSK) << BIT_SYS_REGU_ASIF_WD_SHF) + +//2 REG_SYS_DSLP_TIM_CAL_CTRL +#define BIT_SYS_DSLP_TIM_EN BIT(24) + +#define BIT_SYS_DSLP_TIM_PERIOD_SHF 0 +#define BIT_SYS_DSLP_TIM_PERIOD_MSK 0x7fffff +#define BIT_SYS_DSLP_TIM_PERIOD(x) (((x) & BIT_SYS_DSLP_TIM_PERIOD_MSK) << BIT_SYS_DSLP_TIM_PERIOD_SHF) + +//2 REG_SYS_DEBUG_CTRL +#define BIT_MCTRL_DBG BIT(0) + +//2 REG_SYS_PINMUX_CTRL +#define BIT_MCTRL_SIC BIT(0) +#define BIT_MCTRL_EEPROM BIT(4) + +#define BIT_MCTRL_I2S0_PIN BIT(0) +#define BIT_MCTRL_I2S0_MCK BIT(1) +#define BIT_MCTRL_I2S1_PIN BIT(4) +#define BIT_MCTRL_I2S1_MCK BIT(5) +#define BIT_MCTRL_PCM0 BIT(16) +#define BIT_MCTRL_PCM1 BIT(20) + +//2 REG_HCI_PINMUX_CTRL +#define BIT_MCTRL_HCI_SDIOD BIT(0) +#define BIT_MCTRL_HCI_SDIOH BIT(1) +#define BIT_MCTRL_HCI_MII BIT(24) + +//2 REG_WL_PINMUX_CTRL +#define BIT_MCTRL_WL_ANT0 BIT(8) +#define BIT_MCTRL_WL_ANT1 BIT(9) +#define BIT_MCTRL_WL_BTCOEX BIT(12) +#define BIT_MCTRL_WL_BTCMD BIT(13) +#define BIT_MCTRL_NFC BIT(16) + +#define BIT_MCTRL_WL_LED BIT(0) +#define BIT_MCTRL_WL_LED_SEL_SHF 1 +#define BIT_MCTRL_WL_LED_SEL_MSK 0x3 +#define BIT_MCTRL_WL_LED_SEL(x) (((x) & BIT_WL_LED_SEL_MSK) << BIT_WL_LED_SEL_SHF) + +//2 REG_CPU_PERIPHERAL_CTRL +#define BIT_CPU_SPIC BIT(0) +#define BIT_CPU_SPIC_SHF 1 +#define BIT_CPU_SPIC_MSK 0x3 +#define BIT_CPU_SPIC_SEL(x) (((x) & BIT_CPU_SPIC_SEL_MSK) << BIT_CPU_SPI_SEL_SHF) + +#define BIT_CPU_SDRC BIT(4) +#define BIT_CPU_TRACE BIT(17) + +#define BIT_CPU_LUART_SEL_SHF 22 +#define BIT_CPU_LUART_SEL_MSK 0x3 +#define BIT_CPU_LUART_SEL(x) (((x) & BIT_LUART_SEL_MSK) << BIT_LUART_SEL_SHF) +#define BIT_CPU_LUART BIT(20) +#define BIT_CPU_LUART_IR BIT(21) + +//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL0 +#define BIT_SYS_GPIOE3_WEVENT_STS BIT(27) +#define BIT_SYS_GPIOD5_WEVENT_STS BIT(26) +#define BIT_SYS_GPIOC7_WEVENT_STS BIT(25) +#define BIT_SYS_GPIOA5_WEVENT_STS BIT(24) +#define BIT_SYS_GPIO_GPE3_PULL_CTRL BIT(19) +#define BIT_SYS_GPIO_GPD5_PULL_CTRL BIT(18) +#define BIT_SYS_GPIO_GPC7_PULL_CTRL BIT(17) +#define BIT_SYS_GPIO_GPA5_PULL_CTRL BIT(16) +#define BIT_SYS_GPIOE3_WINT_MODE BIT(11) +#define BIT_SYS_GPIOD5_WINT_MODE BIT(10) +#define BIT_SYS_GPIOC7_WINT_MODE BIT(9) +#define BIT_SYS_GPIOA5_WINT_MODE BIT(8) +#define BIT_SYS_GPIOE3 BIT(3) +#define BIT_SYS_GPIOD5 BIT(2) +#define BIT_SYS_GPIOC7 BIT(1) +#define BIT_SYS_GPIOA5 BIT(0) + +//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL1 +#define BIT_SYS_GPIOA5_SHTDN_N BIT(16) +#define BIT_SYS_GPIOC7_SHTDN_N BIT(17) +#define BIT_SYS_GPIOD5_SHTDN_N BIT(18) +#define BIT_SYS_GPIOE3_SHTDN_N BIT(19) + +#define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL_SHF 8 +#define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL_MSK 0x3 +#define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL(x) (((x) & BIT_SYS_WINT_DEBOUNCE_TIM_SCAL_MSK) << BIT_SYS_WINT_DEBOUNCE_TIM_SCAL_SHF) + +#define BIT_SYS_GPIOA5_WINT_DEBOUNCE_EN BIT(0) +#define BIT_SYS_GPIOC7_WINT_DEBOUNCE_EN BIT(1) +#define BIT_SYS_GPIOD5_WINT_DEBOUNCE_EN BIT(2) +#define BIT_SYS_GPIOE3_WINT_DEBOUNCE_EN BIT(3) + +#define BIT_SYS_DBG_VALUE_SHF 0 +#define BIT_SYS_DBG_VALUE_MSK 0xffffffffL +#define BIT_SYS_DBG_VALUE(x) (((x) & BIT_SYS_DBG_VALUE_MSK) << BIT_SYS_DBG_VALUE_SHF) + +#define BIT_SYS_EFUSE_UNLOCK_SHF 24 +#define BIT_SYS_EFUSE_UNLOCK_MSK 0xff +#define BIT_SYS_EFUSE_UNLOCK(x) (((x) & BIT_EFUSE_UNLOCK_MSK) << BIT_EFUSE_UNLOCK_SHF) +#define BIT_SYS_EFUSE_LDALL BIT(16) +#define BIT_SYS_EEPROM_VPDIDX_SHF 8 +#define BIT_SYS_EEPROM_VPDIDX_MSK 0xff +#define BIT_SYS_EEPROM_VPDIDX(x) (((x) & BIT_SYS_EEPROM_VPDIDX_MSK) << BIT_SYS_EEPROM_VPDIDX_SHF) + +#define BIT_SYS_EEPROM_MD_SHF 6 +#define BIT_SYS_EEPROM_MD_MSK 0x3 +#define BIT_SYS_EEPROM_MD(x) (((x) & BIT_SYS_EEPROM_MD_MSK) << BIT_SYS_EEPROM_MD_SHF) + +#define BIT_SYS_AUTOLOAD_SUS BIT(5) +#define BIT_SYS_EEPROM_SEL BIT(4) +#define BIT_SYS_EEPROM_EECS BIT(3) +#define BIT_SYS_EEPROM_EESK BIT(2) +#define BIT_SYS_EEPROM_EEDI BIT(1) +#define BIT_SYS_EEPROM_EEDO BIT(0) + +//2 REG_SYS_EEPROM_CTRL1 +#define BIT_SYS_EEPROM_VPD_SHF 0 +#define BIT_SYS_EEPROM_VPD_MSK 0xffffffffL +#define BIT_SYS_EEPROM_VPD(x) (((x) & BIT_SYS_EEPROM_VPD_MSK) << BIT_SYS_EEPROM_VPD_SHF) + +//2 REG_SYS_EFUSE_CTRL +#define BIT_SYS_EF_RWFLAG BIT(31) + +#define BIT_SYS_EF_PGPD_SHF 28 +#define BIT_SYS_EF_PGPD_MSK 0x7 +#define BIT_SYS_EF_PGPD(x) (((x) & BIT_SYS_EF_PGPD_MSK) << BIT_SYS_EF_PGPD_SHF) + +#define BIT_SYS_EF_RDT_SHF 24 +#define BIT_SYS_EF_RDT_MSK 0xf +#define BIT_SYS_EF_RDT(x) (((x) & BIT_SYS_EF_RDT_MSK) << BIT_SYS_EF_RDT_SHF) + +#define BIT_SYS_EF_PGTS_SHF 20 +#define BIT_SYS_EF_PGTS_MSK 0xf +#define BIT_SYS_EF_PGTS(x) (((x) & BIT_SYS_EF_PGTS_MSK) << BIT_SYS_EF_PGTS_SHF) + +#define BIT_SYS_EF_PDWN BIT(19) +#define BIT_SYS_EF_ALDEN BIT(18) + +#define BIT_SYS_EF_ADDR_SHF 8 +#define BIT_SYS_EF_ADDR_MSK 0x3ff +#define BIT_SYS_EF_ADDR(x) (((x) & BIT_SYS_EF_ADDR_MSK) << BIT_SYS_EF_ADDR_SHF) + +#define BIT_SYS_EF_DATA_SHF 0 +#define BIT_SYS_EF_DATA_MSK 0xff +#define BIT_SYS_EF_DATA(x) (((x) & BIT_SYS_EF_DATA_MSK) << BIT_SYS_EF_DATA_SHF) + +//2 REG_SYS_EFUSE_TEST +#define BIT_SYS_EF_CRES_SEL BIT(26) + +#define BIT_SYS_EF_SCAN_START_SHF 16 +#define BIT_SYS_EF_SCAN_START_MSK 0x1ff +#define BIT_SYS_EF_SCAN_START(x) (((x) & BIT_SYS_EF_SCAN_START_MSK) << BIT_SYS_EF_SCAN_START_SHF) + +#define BIT_SYS_EF_SCAN_END_SHF 12 +#define BIT_SYS_EF_SCAN_END_MSK 0xf +#define BIT_SYS_EF_SCAN_END(x) (((x) & BIT_SYS_EF_SCAN_END_MSK) << BIT_SYS_EF_SCAN_END_SHF) + +#define BIT_SYS_EF_FORCE_PGMEN BIT(11) + +#define BIT_SYS_EF_CELL_SEL_SHF 8 +#define BIT_SYS_EF_CELL_SEL_MSK 0x3 +#define BIT_SYS_EF_CELL_SEL(x) (((x) & BIT_SYS_EF_CELL_SEL_MSK) << BIT_SYS_EF_CELL_SEL_SHF) + +#define BIT_SYS_EF_TRPT BIT(7) + +#define BIT_SYS_EF_SCAN_TTHD_SHF 0 +#define BIT_SYS_EF_SCAN_TTHD_MSK 0x7f +#define BIT_SYS_EF_SCAN_TTHD(x) (((x) & BIT_SYS_EF_SCAN_TTHD_MSK) << BIT_SYS_EF_SCAN_TTHD_SHF) + +// REG_SYS_SLP_WAKE_EVENT_MSK0 +#define BIT_SYS_WEVT_SYSTIM_MSK BIT(0) +#define BIT_SYS_WEVT_GTIM_MSK BIT(1) +#define BIT_SYS_WEVT_OVER_CURRENT_MSK BIT(2) +#define BIT_SYS_WEVT_CHIP_EN_MSK BIT(3) +#define BIT_SYS_WEVT_GPIO_MSK BIT(4) +#define BIT_SYS_WEVT_WLAN_MSK BIT(8) +#define BIT_SYS_WEVT_NFC_MSK BIT(9) +#define BIT_SYS_WEVT_SDIO_MSK BIT(14) +#define BIT_SYS_WEVT_USB_MSK BIT(16) +#define BIT_SYS_WEVT_UART_MSK BIT(20) +#define BIT_SYS_WEVT_SPI_MSK BIT(22) +#define BIT_SYS_WEVT_I2C_MSK BIT(24) +#define BIT_SYS_WEVT_ADC_MSK BIT(26) +#define BIT_SYS_WEVT_A33_MSK BIT(28) +#define BIT_SYS_WEVT_GPIO_DSTBY_MSK BIT(29) + +// REG_SYS_SLP_WAKE_EVENT_MSK1 + +// REG_SYS_SLP_WAKE_EVENT_STATUS0 +#define BIT_SYS_WEVT_SYSTIM_STS BIT(0) +#define BIT_SYS_WEVT_GTIM_STS BIT(1) +#define BIT_SYS_WEVT_OVER_CURRENT_STS BIT(2) +#define BIT_SYS_WEVT_CHIP_EN_STS BIT(3) +#define BIT_SYS_WEVT_GPIO_STS BIT(4) +#define BIT_SYS_WEVT_WLAN_STS BIT(8) +#define BIT_SYS_WEVT_NFC_STS BIT(9) +#define BIT_SYS_WEVT_SDIO_STS BIT(14) +#define BIT_SYS_WEVT_USB_STS BIT(16) +#define BIT_SYS_WEVT_UART_STS BIT(20) +#define BIT_SYS_WEVT_SPI_STS BIT(22) +#define BIT_SYS_WEVT_I2C_STS BIT(24) +#define BIT_SYS_WEVT_ADC_STS BIT(26) +#define BIT_SYS_WEVT_A33_STS BIT(28) +#define BIT_SYS_WEVT_GPIO_DSTBY_STS BIT(29) + +#define BIT_SYS_WKPERI_IMR0_SHF 1 +#define BIT_SYS_WKPERI_IMR0_MSK 0x7fffffffL +#define BIT_SYS_WKPERI_IMR0(x) (((x) & BIT_SYS_WKPERI_IMR0_MSK) << BIT_SYS_WKPERI_IMR0_SHF) + +#define BIT_SYS_SNFEVT_ADC_MSK BIT(0) + +#define BIT_SYS_WKPERI_ISR0_SHF 1 +#define BIT_SYS_WKPERI_ISR0_MSK 0x7fffffffL +#define BIT_SYS_WKPERI_ISR0(x) (((x) & BIT_SYS_WKPERI_ISR0_MSK) << BIT_SYS_WKPERI_ISR0_SHF) + +#define BIT_SYS_SNFEVT_ADC_STS BIT(0) + +// REG_SYS_PWRMGT_CTRL +#define BIT_SYS_REGU_DSLP BIT(7) + +// REG_NOT_VALID +#define BIT_SYS_PM_CMD_DSLP BIT(0) +#define BIT_SYS_PM_CMD_DSTBY BIT(1) +#define BIT_SYS_PM_CMD_SLP BIT(2) + +//2 REG_SYS_PWRMGT_OPTION +#define BIT_SYS_PMOPT_DSTBY_LPLDO_SEL BIT(0) +#define BIT_SYS_PMOPT_DSTBY_EN_SWR BIT(1) +#define BIT_SYS_PMOPT_DSTBY_EN_PWM BIT(2) +#define BIT_SYS_PMOPT_DSTBY_EN_SOC BIT(3) +#define BIT_SYS_PMOPT_DSTBY_XTAL_EN BIT(4) +#define BIT_SYS_PMOPT_DSTBY_SYSPLL_EN BIT(5) +#define BIT_SYS_PMOPT_DSTBY_SYSCLK_SEL BIT(6) +#define BIT_SYS_PMOPT_SLP_LPLDO_SEL BIT(8) +#define BIT_SYS_PMOPT_SLP_EN_SWR BIT(9) +#define BIT_SYS_PMOPT_SLP_EN_PWM BIT(10) +#define BIT_SYS_PMOPT_SLP_EN_SOC BIT(11) +#define BIT_SYS_PMOPT_SNZ_EN_SWR BIT(17) +#define BIT_SYS_PMOPT_SNZ_EN_PWM BIT(18) +#define BIT_SYS_PMOPT_SNZ_EN_SOC BIT(19) +#define BIT_SYS_PMOPT_SNZ_XTAL_EN BIT(20) +#define BIT_SYS_PMOPT_SNZ_SYSPLL_EN BIT(21) +#define BIT_SYS_PMOPT_SNZ_SYSCLK_SEL BIT(22) +#define BIT_SYS_PMOPT_NORM_LPLDO_SEL BIT(24) +#define BIT_SYS_PMOPT_NORM_EN_SWR BIT(25) +#define BIT_SYS_PMOPT_NORM_EN_PWM BIT(26) +#define BIT_SYS_PMOPT_NORM_EN_SOC BIT(27) +#define BIT_SYS_PMOPT_NORM_XTAL_EN BIT(28) +#define BIT_SYS_PMOPT_NORM_SYSPLL_EN BIT(29) +#define BIT_SYS_PMOPT_NORM_SYSCLK_SEL BIT(30) +#define BIT_SYS_PMOPT_SNZ_LPLDO_SEL BIT(16) +#define BIT_SYS_PMOPT_SLP_XTAL_EN BIT(12) +#define BIT_SYS_PMOPT_SLP_SYSPLL_EN BIT(13) +#define BIT_SYS_PMOPT_SLP_SYSCLK_SEL BIT(14) + +// REG_SYS_PWRMGT_OPTION_EXT +#define BIT_SYS_PMOPT_SLP_SWR_ADJ BIT(0) +#define BIT_SYS_PMOPT_SLP_ANACK_EN BIT(1) +#define BIT_SYS_PMOPT_SLP_ANACK_SEL BIT(2) + +// REG_SYS_DSLP_WEVENT +#define BIT_SYS_DSLP_GPIO BIT(2) +#define BIT_SYS_DSLP_NFC BIT(1) +#define BIT_SYS_DSLP_WTIMER33 BIT(0) + +#define BIT_SYS_ISO33_NFC BIT(0) +#define BIT_SYS_BD_PKG_SEL BIT(31) + +#define BIT_VENDOR_ID_SHF 8 +#define BIT_VENDOR_ID_MSK 0xf +#define BIT_VENDOR_ID(x) (((x) & BIT_VENDOR_ID_MSK) << BIT_VENDOR_ID_SHF) + +#define BIT_CHIP_VER_SHF 4 +#define BIT_CHIP_VER_MSK 0xf +#define BIT_CHIP_VER(x) (((x) & BIT_CHIP_VER_MSK) << BIT_CHIP_VER_SHF) + +#define BIT_RF_RL_ID_SHF 0 +#define BIT_RF_RL_ID_MSK 0xf +#define BIT_RF_RL_ID(x) (((x) & BIT_RF_RL_ID_MSK) << BIT_RF_RL_ID_SHF) + +#define BIT_SYS_TRP_ICFG_SHF 28 +#define BIT_SYS_TRP_ICFG_MSK 0xf +#define BIT_SYS_TRP_ICFG(x) (((x) & BIT_SYS_TRP_ICFG_MSK) << BIT_SYS_TRP_ICFG_SHF) + +#define BIT_SYS_ALDN_STS BIT(0) +#define BIT_SYS_XCLK_VLD BIT(8) +#define BIT_SYS_PLL_CLK_RDY BIT(9) +#define BIT_V15_VLD BIT(16) +#define BIT_SYS_TRP_SPSLDO_SEL BIT(26) +#define BIT_SYS_TRP_BOOT_SEL BIT(27) + +// REG_PERI_PWM0_CTRL +#define BIT_PWM0_PERIOD_SHF 0 +#define BIT_PWM0_PERIOD_MSK 0x3ff +#define BIT_PWM0_PERIOD(x) ((x & BIT_PWM0_PERIOD_MSK) << BIT_PWM0_PERIOD_SHF) +#define BIT_PWM0_DUTY_SHF 12 +#define BIT_PWM0_DUTY_MSK 0x3ff +#define BIT_PWM0_DUTY(x) ((x & BIT_PWM0_DUTY_MSK) << BIT_PWM0_DUTY_SHF) +#define BIT_PWM0_GT_SEL_SHF 24 +#define BIT_PWM0_GT_SEL_MSK 0xf +#define BIT_PWM0_GT_SEL(x) ((x & BIT_PWM0_GT_SEL_MSK) << BIT_PWM0_GT_SEL_SHF) +#define BIT_FCTRL_PWM0 BIT(31) + +// REG_PERI_PWM1_CTRL +#define BIT_PWM1_PERIOD_SHF 0 +#define BIT_PWM1_PERIOD_MSK 0x3ff +#define BIT_PWM1_PERIOD(x) ((x & BIT_PWM1_PERIOD_MSK) << BIT_PWM1_PERIOD_SHF) +#define BIT_PWM1_DUTY_SHF 12 +#define BIT_PWM1_DUTY_MSK 0x3ff +#define BIT_PWM1_DUTY(x) ((x & BIT_PWM1_DUTY_MSK) << BIT_PWM1_DUTY_SHF) +#define BIT_PWM1_GT_SEL_SHF 24 +#define BIT_PWM1_GT_SEL_MSK 0xf +#define BIT_PWM1_GT_SEL(x) ((x & BIT_PWM1_GT_SEL_MSK) << BIT_PWM1_GT_SEL_SHF) +#define BIT_FCTRL_PWM1 BIT(31) + +// REG_PERI_PWM2_CTRL +#define BIT_PWM2_PERIOD_SHF 0 +#define BIT_PWM2_PERIOD_MSK 0x3ff +#define BIT_PWM2_PERIOD(x) ((x & BIT_PWM2_PERIOD_MSK) << BIT_PWM2_PERIOD_SHF) +#define BIT_PWM2_DUTY_SHF 12 +#define BIT_PWM2_DUTY_MSK 0x3ff +#define BIT_PWM2_DUTY(x) ((x & BIT_PWM2_DUTY_MSK) << BIT_PWM2_DUTY_SHF) +#define BIT_PWM2_GT_SEL_SHF 24 +#define BIT_PWM2_GT_SEL_MSK 0xf +#define BIT_PWM2_GT_SEL(x) ((x & BIT_PWM2_GT_SEL_MSK) << BIT_PWM2_GT_SEL_SHF) +#define BIT_FCTRL_PWM2 BIT(31) + +// REG_PERI_PWM3_CTRL +#define BIT_PWM3_PERIOD_SHF 0 +#define BIT_PWM3_PERIOD_MSK 0x3ff +#define BIT_PWM3_PERIOD(x) ((x & BIT_PWM3_PERIOD_MSK) << BIT_PWM3_PERIOD_SHF) +#define BIT_PWM3_DUTY_SHF 12 +#define BIT_PWM3_DUTY_MSK 0x3ff +#define BIT_PWM3_DUTY(x) ((x & BIT_PWM3_DUTY_MSK) << BIT_PWM3_DUTY_SHF) +#define BIT_PWM3_GT_SEL_SHF 24 +#define BIT_PWM3_GT_SEL_MSK 0xf +#define BIT_PWM3_GT_SEL(x) ((x & BIT_PWM3_GT_SEL_MSK) << BIT_PWM3_GT_SEL_SHF) +#define BIT_FCTRL_PWM3 BIT(31) + +// REG_PERI_TIM_EVT_CTRL +#define BIT_FCTRL_GT_EVT0 BIT(7) +#define BIT_GT_EVT0_PULSE_DUR_SHF 0 +#define BIT_GT_EVT0_PULSE_DUR_MSK 0xf +#define BIT_GT_EVT0_PULSE_DUR(x) ((x & BIT_GT_EVT0_PULSE_DUR_MSK) << BIT_GT_EVT0_PULSE_DUR_SHF) +#define BIT_GT_EVT0_SRC_SEL_SHF 4 +#define BIT_GT_EVT0_SRC_SEL_MSK 0x7 +#define BIT_GT_EVT0_SRC_SEL(x) ((x & BIT_GT_EVT0_SRC_SEL_MSK) << BIT_GT_EVT0_SRC_SEL_SHF) + +#define BIT_FCTRL_GT_EVT1 BIT(15) +#define BIT_GT_EVT1_PULSE_DUR_SHF 8 +#define BIT_GT_EVT1_PULSE_DUR_MSK 0xf +#define BIT_GT_EVT1_PULSE_DUR(x) ((x & BIT_GT_EVT1_PULSE_DUR_MSK) << BIT_GT_EVT1_PULSE_DUR_SHF) +#define BIT_GT_EVT1_SRC_SEL_SHF 12 +#define BIT_GT_EVT1_SRC_SEL_MSK 0x7 +#define BIT_GT_EVT1_SRC_SEL(x) ((x & BIT_GT_EVT1_SRC_SEL_MSK) << BIT_GT_EVT1_SRC_SEL_SHF) + +#define BIT_FCTRL_GT_EVT2 BIT(23) +#define BIT_GT_EVT2_PULSE_DUR_SHF 16 +#define BIT_GT_EVT2_PULSE_DUR_MSK 0xf +#define BIT_GT_EVT2_PULSE_DUR(x) ((x & BIT_GT_EVT2_PULSE_DUR_MSK) << BIT_GT_EVT2_PULSE_DUR_SHF) +#define BIT_GT_EVT2_SRC_SEL_SHF 20 +#define BIT_GT_EVT2_SRC_SEL_MSK 0x7 +#define BIT_GT_EVT2_SRC_SEL(x) ((x & BIT_GT_EVT2_SRC_SEL_MSK) << BIT_GT_EVT2_SRC_SEL_SHF) + +#define BIT_FCTRL_GT_EVT3 BIT(31) +#define BIT_GT_EVT3_PULSE_DUR_SHF 24 +#define BIT_GT_EVT3_PULSE_DUR_MSK 0xf +#define BIT_GT_EVT3_PULSE_DUR(x) ((x & BIT_GT_EVT3_PULSE_DUR_MSK) << BIT_GT_EVT3_PULSE_DUR_SHF) +#define BIT_GT_EVT3_SRC_SEL_SHF 28 +#define BIT_GT_EVT3_SRC_SEL_MSK 0x7 +#define BIT_GT_EVT3_SRC_SEL(x) ((x & BIT_GT_EVT3_SRC_SEL_MSK) << BIT_GT_EVT3_SRC_SEL_SHF) + +// REG_PERI_EGTIM_CTRL +#define BIT_FCTRL_EGTIM BIT(0) +#define BIT_EGTIM_REF_SIG_SEL_SHF 4 +#define BIT_EGTIM_REF_SIG_SEL_MSK 0x3 +#define BIT_EGTIM_REF_SIG_SEL(x) ((x & BIT_EGTIM_REF_SIG_SEL_MSK) << BIT_EGTIM_REF_SIG_SEL_SHF) + +#define BIT_EGTIM_PIN_GROUP0_OPT_SEL_SHF 8 +#define BIT_EGTIM_PIN_GROUP0_OPT_SEL_MSK 0x3 +#define BIT_EGTIM_PIN_GROUP0_OPT_SEL(x) ((x & BIT_EGTIM_PIN_GROUP0_OPT_SEL_MSK) << BIT_EGTIM_PIN_GROUP0_OPT_SEL_SHF) + +#define BIT_EGTIM_PIN_GROUP1_OPT_SEL_SHF 10 +#define BIT_EGTIM_PIN_GROUP1_OPT_SEL_MSK 0x3 +#define BIT_EGTIM_PIN_GROUP1_OPT_SEL(x) ((x & BIT_EGTIM_PIN_GROUP1_OPT_SEL_MSK) << BIT_EGTIM_PIN_GROUP1_OPT_SEL_SHF) + +#define BIT_EGTIM_PIN_GROUP2_OPT_SEL_SHF 12 +#define BIT_EGTIM_PIN_GROUP2_OPT_SEL_MSK 0x3 +#define BIT_EGTIM_PIN_GROUP2_OPT_SEL(x) ((x & BIT_EGTIM_PIN_GROUP2_OPT_SEL_MSK) << BIT_EGTIM_PIN_GROUP2_OPT_SEL_SHF) + +//================= Register Address Definition =====================// +#define SYS_PWR_CTRL 0x0000 +#define SYS_ISO_CTRL 0x0002 +#define SYS_FUNC_EN 0x0008 +#define SYS_CLK_CTRL0 0x0010 +#define SYS_CLK_CTRL1 0x0014 +#define REG_SYS_CLK_CTRL1 (SYS_CLK_CTRL1) +#define SYS_EFUSE_CFG0 0x0020 +#define SYS_EFUSE_CFG1 0x0024 +#define SYS_EFUSE_CFG2 0x0028 +#define SYS_EFUSE_CFG3 0x002C +#define SYS_EFUSE_CFG4 0x0030 +#define SYS_EFUSE_CFG5 0x0034 +#define SYS_EFUSE_CFG6 0x0038 +#define REG_SYS_EFUSE_SYSCFG6 (SYS_EFUSE_CFG6) +#define SYS_EFUSE_CFG7 0x003C +#define SYS_REGU_CTRL0 0x0040 // REG_SYS_REGU_CTRL0 +#define SYS_SWR_CTRL0 0x0048 +#define SYS_SWR_CTRL1 0x004C +#define SYS_XTAL_CTRL0 0x0060 +#define SYS_XTAL_CTRL1 0x0064 +#define SYS_SYSPLL_CTRL0 0x0070 +#define SYS_SYSPLL_CTRL1 0x0074 +#define SYS_SYSPLL_CTRL2 0x0078 +#define SYS_ANA_TIM_CTRL 0x0090 +#define SYS_DSLP_TIM_CTRL 0x0094 +#define SYS_DSLP_TIM_CAL_CTRL 0x0098 +#define SYS_DEBUG_CTRL 0x00A0 +#define SYS_PINMUX_CTRL 0x00A4 +#define SYS_GPIO_DSTBY_WAKE_CTRL0 0x00A8 +#define SYS_GPIO_DSTBY_WAKE_CTRL1 0x00AC +#define SYS_DEBUG_REG 0x00BC +#define SYS_EEPROM_CTRL0 0x00E0 +#define REG_SYS_EEPROM_CTRL0 (SYS_EEPROM_CTRL0) +#define SYS_EEPROM_CTRL1 0x00E4 +#define SYS_EFUSE_CTRL 0x00E8 +#define REG_SYS_EFUSE_CTRL (SYS_EFUSE_CTRL) +#define SYS_EFUSE_TEST 0x00EC +#define REG_SYS_EFUSE_TEST (SYS_EFUSE_TEST) +#define SYS_DSTBY_INFO0 0x00F0 +#define SYS_DSTBY_INFO1 0x00F4 +#define SYS_DSTBY_INFO2 0x00F8 +#define SYS_DSTBY_INFO3 0x00FC +#define REG_SYS_DSTBY_INFO3 (SYS_DSTBY_INFO3) +#define SYS_SLP_WAKE_EVENT_MSK0 0x0100 +#define SYS_SLP_WAKE_EVENT_MSK1 0x0104 +#define SYS_SLP_WAKE_EVENT_STATUS0 0x0108 +#define SYS_SLP_WAKE_EVENT_STATUS1 0x010C +#define SYS_SNF_WAKE_EVENT_MSK0 0x0110 +#define SYS_SNF_WAKE_EVENT_STATUS 0x0114 +#define SYS_PWRMGT_CTRL 0x0118 +#define SYS_PWRMGT_OPTION 0x0120 +#define SYS_PWRMGT_OPTION_EXT 0x0124 +#define SYS_DSLP_WEVENT 0x0130 +#define SYS_PERI_MONITOR 0x0134 +#define SYS_SYSTEM_CFG0 0x01F0 +#define REG_SYS_SYSTEM_CFG0 (SYS_SYSTEM_CFG0) +#define SYS_SYSTEM_CFG1 0x01F4 +#define REG_SYS_SYSTEM_CFG1 (SYS_SYSTEM_CFG1) +#define SYS_SYSTEM_CFG2 0x01F8 + +#define __LXBUS_Enable() __RTK_PERI_SETBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_LXBUS) +#define __LXBUS_Disable() __RTK_PERI_CLRBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_LXBUS) +#define __FLASH_Enable() __RTK_PERI_SETBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_FLASH) +#define __FLASH_Disable() \ + do { \ + __RTK_READ32(SPI_FLASH_BASE, 0); \ + __RTK_PERI_CLRBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_FLASH); \ + } while (0) + +#define __GTIMER_Enable() __RTK_PERI_SETBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_GTIMER) +#define __GTIMER_Disable() \ + do { \ + __RTK_READ32(TIMER_BASE, 0); \ + __RTK_PERI_CLRBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_GTIMER); \ + } while (0) + +#define __CRYPTO_Enable() __RTK_PERI_SETBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_GTIMER) +#define __CRYPTO_Disable() \ + do { \ + __RTK_READ32(CRYPTO_BASE, 0); \ + __RTK_PERI_SETBIT(PERI_FCTRL_CTRL0, BIT_FCTRL_SEC_ENG); \ + } while (0) + +#endif +#endif + +// Clock Control Register 3 (REG_PESOC_CLK_CTRL3) + +// HCI_CLK_CTRL0 +#define BIT_ACTCK_SDIOD BIT(0) +#define BIT_SLPCK_SDIOD BIT(1) +#define BIT_ACTCK_SDIOH BIT(2) +#define BIT_SLPCK_SDIOH BIT(3) +#define BIT_ACTCK_HCI_OTG BIT(4) +#define BIT_SLPCK_HCI_OTG BIT(5) +#define BIT_ACTCK_MII_MPHY BIT(24) +#define BIT_SLPCK_MII_MPHY BIT(25) + + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_pwm.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_pwm.h new file mode 100644 index 00000000000..264bbffbe23 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_pwm.h @@ -0,0 +1,61 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_PWM_H_ +#define _RTL8195A_PWM_H_ + +extern void +HAL_Pwm_SetDuty_8195a( + HAL_PWM_ADAPTER *pPwmAdapt, + u32 period, + u32 pulse_width +); + +extern HAL_Status +HAL_Pwm_Init_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +); + +extern void +HAL_Pwm_Enable_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +); + +extern void +HAL_Pwm_Disable_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +); + + +#ifdef CONFIG_CHIP_E_CUT +extern _LONG_CALL_ void +HAL_Pwm_SetDuty_8195a_V04( + HAL_PWM_ADAPTER *pPwmAdapt, + u32 period, + u32 pulse_width +); + +extern _LONG_CALL_ HAL_Status +HAL_Pwm_Init_8195a_V04( + HAL_PWM_ADAPTER *pPwmAdapt +); + +extern _LONG_CALL_ void +HAL_Pwm_Enable_8195a_V04( + HAL_PWM_ADAPTER *pPwmAdapt +); + +extern _LONG_CALL_ void +HAL_Pwm_Disable_8195a_V04( + HAL_PWM_ADAPTER *pPwmAdapt +); +#endif + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h new file mode 100644 index 00000000000..8b55a13e17c --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h @@ -0,0 +1,748 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +SECTIONS +{ + __vectors_table = 0x0; + Reset_Handler = 0x101; + NMI_Handler = 0x109; + HardFault_Handler = 0x10d; + MemManage_Handler = 0x121; + BusFault_Handler = 0x125; + UsageFault_Handler = 0x129; + HalLogUartInit = 0x201; + HalSerialPutcRtl8195a = 0x2d9; + HalSerialGetcRtl8195a = 0x309; + HalSerialGetIsrEnRegRtl8195a = 0x329; + HalSerialSetIrqEnRegRtl8195a = 0x335; + HalCpuClkConfig = 0x341; + HalGetCpuClk = 0x355; + HalRomInfo = 0x39d; + HalGetRomInfo = 0x3b5; + HalResetVsr = 0x3c5; + HalDelayUs = 0x899; + HalNMIHandler = 0x8e1; + HalHardFaultHandler = 0x911; + HalMemManageHandler = 0xc09; + HalBusFaultHandler = 0xc39; + HalUsageFaultHandler = 0xc69; + HalUart0PinCtrlRtl8195A = 0xcfd; + HalUart1PinCtrlRtl8195A = 0xdc9; + HalUart2PinCtrlRtl8195A = 0xe9d; + HalSPI0PinCtrlRtl8195A = 0xf75; + HalSPI1PinCtrlRtl8195A = 0x1015; + HalSPI2PinCtrlRtl8195A = 0x10e5; + HalSPI0MCSPinCtrlRtl8195A = 0x11b5; + HalI2C0PinCtrlRtl8195A = 0x1275; + HalI2C1PinCtrlRtl8195A = 0x1381; + HalI2C2PinCtrlRtl8195A = 0x1459; + HalI2C3PinCtrlRtl8195A = 0x1529; + HalI2S0PinCtrlRtl8195A = 0x1639; + HalI2S1PinCtrlRtl8195A = 0x176d; + HalPCM0PinCtrlRtl8195A = 0x1845; + HalPCM1PinCtrlRtl8195A = 0x1949; + HalSDIODPinCtrlRtl8195A = 0x1a1d; + HalSDIOHPinCtrlRtl8195A = 0x1a6d; + HalMIIPinCtrlRtl8195A = 0x1ab9; + HalWLLEDPinCtrlRtl8195A = 0x1b51; + HalWLANT0PinCtrlRtl8195A = 0x1c0d; + HalWLANT1PinCtrlRtl8195A = 0x1c61; + HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5; + HalWLBTCMDPinCtrlRtl8195A = 0x1d05; + HalNFCPinCtrlRtl8195A = 0x1d59; + HalPWM0PinCtrlRtl8195A = 0x1da9; + HalPWM1PinCtrlRtl8195A = 0x1ead; + HalPWM2PinCtrlRtl8195A = 0x1fb5; + HalPWM3PinCtrlRtl8195A = 0x20b1; + HalETE0PinCtrlRtl8195A = 0x21b9; + HalETE1PinCtrlRtl8195A = 0x22c1; + HalETE2PinCtrlRtl8195A = 0x23c9; + HalETE3PinCtrlRtl8195A = 0x24d1; + HalEGTIMPinCtrlRtl8195A = 0x25d9; + HalSPIFlashPinCtrlRtl8195A = 0x2679; + HalSDRPinCtrlRtl8195A = 0x2725; + HalJTAGPinCtrlRtl8195A = 0x280d; + HalTRACEPinCtrlRtl8195A = 0x2861; + HalLOGUartPinCtrlRtl8195A = 0x28b9; + HalLOGUartIRPinCtrlRtl8195A = 0x291d; + HalSICPinCtrlRtl8195A = 0x2981; + HalEEPROMPinCtrlRtl8195A = 0x29d9; + HalDEBUGPinCtrlRtl8195A = 0x2a31; + HalPinCtrlRtl8195A = 0x2b39; + SpicRxCmdRtl8195A = 0x2e5d; + SpicWaitBusyDoneRtl8195A = 0x2ea5; + SpicGetFlashStatusRtl8195A = 0x2eb5; + SpicWaitWipDoneRtl8195A = 0x2f55; + SpicTxCmdRtl8195A = 0x2f6d; + SpicSetFlashStatusRtl8195A = 0x2fc1; + SpicCmpDataForCalibrationRtl8195A = 0x3049; + SpicLoadInitParaFromClockRtl8195A = 0x3081; + SpicInitRtl8195A = 0x30e5; + SpicEraseFlashRtl8195A = 0x31bd; + SpiFlashApp = 0x3279; + HalPeripheralIntrHandle = 0x33b5; + HalSysOnIntrHandle = 0x3439; + HalWdgIntrHandle = 0x3485; + HalTimer0IntrHandle = 0x34d5; + HalTimer1IntrHandle = 0x3525; + HalI2C3IntrHandle = 0x3575; + HalTimer2To7IntrHandle = 0x35c5; + HalSpi0IntrHandle = 0x3615; + HalGpioIntrHandle = 0x3665; + HalUart0IntrHandle = 0x36b5; + HalSpiFlashIntrHandle = 0x3705; + HalUsbOtgIntrHandle = 0x3755; + HalSdioHostIntrHandle = 0x37a5; + HalI2s0OrPcm0IntrHandle = 0x37f5; + HalI2s1OrPcm1IntrHandle = 0x3845; + HalWlDmaIntrHandle = 0x3895; + HalWlProtocolIntrHandle = 0x38e5; + HalCryptoIntrHandle = 0x3935; + HalGmacIntrHandle = 0x3985; + HalGdma0Ch0IntrHandle = 0x39d5; + HalGdma0Ch1IntrHandle = 0x3a25; + HalGdma0Ch2IntrHandle = 0x3a75; + HalGdma0Ch3IntrHandle = 0x3ac5; + HalGdma0Ch4IntrHandle = 0x3b15; + HalGdma0Ch5IntrHandle = 0x3b65; + HalGdma1Ch0IntrHandle = 0x3bb5; + HalGdma1Ch1IntrHandle = 0x3c05; + HalGdma1Ch2IntrHandle = 0x3c55; + HalGdma1Ch3IntrHandle = 0x3ca5; + HalGdma1Ch4IntrHandle = 0x3cf5; + HalGdma1Ch5IntrHandle = 0x3d45; + HalSdioDeviceIntrHandle = 0x3d95; + VectorTableInitRtl8195A = 0x3de5; + VectorTableInitForOSRtl8195A = 0x4019; + VectorIrqRegisterRtl8195A = 0x4029; + VectorIrqUnRegisterRtl8195A = 0x4091; + VectorIrqEnRtl8195A = 0x40f1; + VectorIrqDisRtl8195A = 0x418d; + _UartRxDmaIrqHandle = 0x422d; + HalRuartPutCRtl8195a = 0x4281; + HalRuartGetCRtl8195a = 0x429d; + HalRuartRTSCtrlRtl8195a = 0x42bd; + HalRuartGetDebugValueRtl8195a = 0x42e1; + HalRuartGetIMRRtl8195a = 0x43e1; + HalRuartSetIMRRtl8195a = 0x442d; + _UartIrqHandle = 0x4465; + HalRuartDmaInitRtl8195a = 0x4681; + HalRuartIntDisableRtl8195a = 0x4845; + HalRuartDeInitRtl8195a = 0x4855; + HalRuartIntEnableRtl8195a = 0x4985; + _UartTxDmaIrqHandle = 0x4995; + HalRuartRegIrqRtl8195a = 0x49d1; + HalRuartAdapterLoadDefRtl8195a = 0x4a4d; + HalRuartTxGdmaLoadDefRtl8195a = 0x4add; + HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9; + RuartLock = 0x4cc9; + RuartUnLock = 0x4ced; + HalRuartIntSendRtl8195a = 0x4d09; + HalRuartDmaSendRtl8195a = 0x4e35; + HalRuartStopSendRtl8195a = 0x4f89; + HalRuartIntRecvRtl8195a = 0x504d; + HalRuartDmaRecvRtl8195a = 0x51ad; + HalRuartStopRecvRtl8195a = 0x52cd; + RuartIsTimeout = 0x5385; + HalRuartSendRtl8195a = 0x53b1; + HalRuartRecvRtl8195a = 0x5599; + RuartResetRxFifoRtl8195a = 0x5751; + HalRuartResetRxFifoRtl8195a = 0x5775; + HalRuartInitRtl8195a = 0x5829; + HalGdmaOnOffRtl8195a = 0x5df1; + HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d; + HalGdmaChEnRtl8195a = 0x5e51; + HalGdmaChDisRtl8195a = 0x5e6d; + HalGdamChInitRtl8195a = 0x5e91; + HalGdmaChSetingRtl8195a = 0x5ebd; + HalGdmaChIsrCleanRtl8195a = 0x6419; + HalGdmaChCleanAutoSrcRtl8195a = 0x64a1; + HalGdmaChCleanAutoDstRtl8195a = 0x6501; + HalEFUSEPowerSwitch8195AROM = 0x6561; + HALEFUSEOneByteReadROM = 0x65f9; + HALEFUSEOneByteWriteROM = 0x6699; + __rtl_memcmpb_v1_00 = 0x681d; + __rtl_random_v1_00 = 0x6861; + __rtl_align_to_be32_v1_00 = 0x6881; + __rtl_memsetw_v1_00 = 0x6899; + __rtl_memsetb_v1_00 = 0x68ad; + __rtl_memcpyw_v1_00 = 0x68bd; + __rtl_memcpyb_v1_00 = 0x68dd; + __rtl_memDump_v1_00 = 0x68f5; + __rtl_AES_set_encrypt_key = 0x6901; + __rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11; + __rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95; + __rtl_cryptoEngine_init_v1_00 = 0x6ea9; + __rtl_cryptoEngine_exit_v1_00 = 0x7055; + __rtl_cryptoEngine_reset_v1_00 = 0x70b1; + __rtl_cryptoEngine_v1_00 = 0x70ed; + __rtl_crypto_cipher_init_v1_00 = 0x7c69; + __rtl_crypto_cipher_encrypt_v1_00 = 0x7c89; + __rtl_crypto_cipher_decrypt_v1_00 = 0x7cad; + HalSsiPinmuxEnableRtl8195a = 0x7cd5; + HalSsiEnableRtl8195a = 0x7e45; + HalSsiDisableRtl8195a = 0x7ef9; + HalSsiLoadSettingRtl8195a = 0x7fad; + HalSsiSetInterruptMaskRtl8195a = 0x8521; + HalSsiGetInterruptMaskRtl8195a = 0x85c9; + HalSsiSetSclkPolarityRtl8195a = 0x863d; + HalSsiSetSclkPhaseRtl8195a = 0x8715; + HalSsiWriteRtl8195a = 0x87e9; + HalSsiSetDeviceRoleRtl8195a = 0x8861; + HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9; + HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941; + HalSsiReadRtl8195a = 0x89b9; + HalSsiGetRxFifoLevelRtl8195a = 0x8a2d; + HalSsiGetTxFifoLevelRtl8195a = 0x8aa5; + HalSsiGetStatusRtl8195a = 0x8b1d; + HalSsiWriteableRtl8195a = 0x8b91; + HalSsiReadableRtl8195a = 0x8c09; + HalSsiBusyRtl8195a = 0x8c81; + HalSsiReadInterruptRtl8195a = 0x8cf9; + HalSsiWriteInterruptRtl8195a = 0x8efd; + HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009; + HalSsiGetInterruptStatusRtl8195a = 0x90d9; + HalSsiInterruptEnableRtl8195a = 0x914d; + HalSsiInterruptDisableRtl8195a = 0x9299; + HalSsiGetRawInterruptStatusRtl8195a = 0x93e9; + HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d; + HalSsiInitRtl8195a = 0x94d1; + _SsiReadInterrupt = 0x9ba5; + _SsiWriteInterrupt = 0x9db1; + _SsiIrqHandle = 0x9eb1; + HalI2CWrite32 = 0xa061; + HalI2CRead32 = 0xa09d; + HalI2CDeInit8195a = 0xa0dd; + HalI2CSendRtl8195a = 0xa1f1; + HalI2CReceiveRtl8195a = 0xa25d; + HalI2CEnableRtl8195a = 0xa271; + HalI2CIntrCtrl8195a = 0xa389; + HalI2CReadRegRtl8195a = 0xa3a1; + HalI2CWriteRegRtl8195a = 0xa3b1; + HalI2CSetCLKRtl8195a = 0xa3c5; + HalI2CMassSendRtl8195a = 0xa6e9; + HalI2CClrIntrRtl8195a = 0xa749; + HalI2CClrAllIntrRtl8195a = 0xa761; + HalI2CInit8195a = 0xa775; + HalI2CDMACtrl8195a = 0xaa31; + RtkI2CIoCtrl = 0xaa61; + RtkI2CPowerCtrl = 0xaa65; + HalI2COpInit = 0xaa69; + I2CIsTimeout = 0xac65; + I2CTXGDMAISRHandle = 0xb435; + I2CRXGDMAISRHandle = 0xb4c1; + RtkI2CIrqInit = 0xb54d; + RtkI2CIrqDeInit = 0xb611; + RtkI2CPinMuxInit = 0xb675; + RtkI2CPinMuxDeInit = 0xb7c9; + RtkI2CDMAInit = 0xb955; + RtkI2CInit = 0xbc95; + RtkI2CDMADeInit = 0xbdad; + RtkI2CDeInit = 0xbe4d; + RtkI2CSendUserAddr = 0xbee5; + RtkI2CSend = 0xc07d; + RtkI2CLoadDefault = 0xce51; + RtkSalI2COpInit = 0xcf21; + HalI2SWrite32 = 0xcf65; + HalI2SRead32 = 0xcf85; + HalI2SDeInitRtl8195a = 0xcfa9; + HalI2STxRtl8195a = 0xcfc9; + HalI2SRxRtl8195a = 0xd011; + HalI2SEnableRtl8195a = 0xd05d; + HalI2SIntrCtrlRtl8195a = 0xd0b1; + HalI2SReadRegRtl8195a = 0xd0d1; + HalI2SClrIntrRtl8195a = 0xd0dd; + HalI2SClrAllIntrRtl8195a = 0xd0fd; + HalI2SInitRtl8195a = 0xd11d; + GPIO_GetIPPinName_8195a = 0xd2e5; + GPIO_GetChipPinName_8195a = 0xd331; + GPIO_PullCtrl_8195a = 0xd39d; + GPIO_FuncOn_8195a = 0xd421; + GPIO_FuncOff_8195a = 0xd481; + GPIO_Int_Mask_8195a = 0xd4e9; + GPIO_Int_SetType_8195a = 0xd511; + HAL_GPIO_IrqHandler_8195a = 0xd5fd; + HAL_GPIO_MbedIrqHandler_8195a = 0xd645; + HAL_GPIO_UserIrqHandler_8195a = 0xd6a1; + HAL_GPIO_IntCtrl_8195a = 0xd6cd; + HAL_GPIO_Init_8195a = 0xd805; + HAL_GPIO_DeInit_8195a = 0xdac1; + HAL_GPIO_ReadPin_8195a = 0xdbd1; + HAL_GPIO_WritePin_8195a = 0xdc91; + HAL_GPIO_RegIrq_8195a = 0xddad; + HAL_GPIO_UnRegIrq_8195a = 0xddf5; + HAL_GPIO_UserRegIrq_8195a = 0xde15; + HAL_GPIO_UserUnRegIrq_8195a = 0xdef9; + HAL_GPIO_MaskIrq_8195a = 0xdfc1; + HAL_GPIO_UnMaskIrq_8195a = 0xe061; + HAL_GPIO_IntDebounce_8195a = 0xe101; + HAL_GPIO_GetIPPinName_8195a = 0xe1c1; + HAL_GPIO_PullCtrl_8195a = 0xe1c9; + DumpForOneBytes = 0xe259; + CmdRomHelp = 0xe419; + CmdWriteWord = 0xe491; + CmdDumpHelfWord = 0xe505; + CmdDumpWord = 0xe5f1; + CmdDumpByte = 0xe6f5; + CmdSpiFlashTool = 0xe751; + GetRomCmdNum = 0xe7a9; + CmdWriteByte = 0xe7ad; + Isspace = 0xe7ed; + Strtoul = 0xe801; + ArrayInitialize = 0xe8b1; + GetArgc = 0xe8c9; + GetArgv = 0xe8f9; + UartLogCmdExecute = 0xe95d; + UartLogShowBackSpace = 0xe9fd; + UartLogRecallOldCmd = 0xea39; + UartLogHistoryCmd = 0xea71; + UartLogCmdChk = 0xeadd; + UartLogIrqHandle = 0xebf5; + RtlConsolInit = 0xecc5; + RtlConsolTaskRom = 0xed49; + RtlExitConsol = 0xed79; + RtlConsolRom = 0xedcd; + HalTimerOpInit = 0xee0d; + HalTimerIrq2To7Handle = 0xee59; + HalGetTimerIdRtl8195a = 0xef09; + HalTimerInitRtl8195a = 0xef3d; + HalTimerDisRtl8195a = 0xf069; + HalTimerEnRtl8195a = 0xf089; + HalTimerReadCountRtl8195a = 0xf0a9; + HalTimerIrqClearRtl8195a = 0xf0bd; + HalTimerDumpRegRtl8195a = 0xf0d1; + VSprintf = 0xf129; + DiagPrintf = 0xf39d; + DiagSPrintf = 0xf3b9; + DiagSnPrintf = 0xf3d1; + prvDiagPrintf = 0xf3ed; + prvDiagSPrintf = 0xf40d; + _memcmp = 0xf429; + _memcpy = 0xf465; + _memset = 0xf511; + Rand = 0xf585; + _strncpy = 0xf60d; + _strcpy = 0xf629; + prvStrCpy = 0xf639; + _strlen = 0xf651; + _strnlen = 0xf669; + prvStrLen = 0xf699; + _strcmp = 0xf6b1; + _strncmp = 0xf6d1; + prvStrCmp = 0xf719; + StrUpr = 0xf749; + prvAtoi = 0xf769; + prvStrStr = 0xf7bd; + _strsep = 0xf7d5; + skip_spaces = 0xf815; + skip_atoi = 0xf831; + _parse_integer_fixup_radix = 0xf869; + _parse_integer = 0xf8bd; + simple_strtoull = 0xf915; + simple_strtoll = 0xf945; + simple_strtoul = 0xf965; + simple_strtol = 0xf96d; + _vsscanf = 0xf985; + _sscanf = 0xff71; + div_u64 = 0xff91; + div_s64 = 0xff99; + div_u64_rem = 0xffa1; + div_s64_rem = 0xffb1; + _strpbrk = 0xffc1; + _strchr = 0xffed; + aes_set_key = 0x10005; + aes_encrypt = 0x103d1; + aes_decrypt = 0x114a5; + AES_WRAP = 0x125c9; + AES_UnWRAP = 0x12701; + crc32_get = 0x12861; + arc4_byte = 0x12895; + rt_arc4_init = 0x128bd; + rt_arc4_crypt = 0x12901; + rt_md5_init = 0x131c1; + rt_md5_append = 0x131f5; + rt_md5_final = 0x1327d; + rt_md5_hmac = 0x132d5; + rtw_get_bit_value_from_ieee_value = 0x13449; + rtw_is_cckrates_included = 0x13475; + rtw_is_cckratesonly_included = 0x134b5; + rtw_check_network_type = 0x134dd; + rtw_set_fixed_ie = 0x1350d; + rtw_set_ie = 0x1352d; + rtw_get_ie = 0x1355d; + rtw_set_supported_rate = 0x13591; + rtw_get_rateset_len = 0x13611; + rtw_get_wpa_ie = 0x1362d; + rtw_get_wpa2_ie = 0x136c9; + rtw_get_wpa_cipher_suite = 0x13701; + rtw_get_wpa2_cipher_suite = 0x13769; + rtw_parse_wpa_ie = 0x137d1; + rtw_parse_wpa2_ie = 0x138ad; + rtw_get_sec_ie = 0x13965; + rtw_get_wps_ie = 0x13a15; + rtw_get_wps_attr = 0x13a99; + rtw_get_wps_attr_content = 0x13b49; + rtw_ieee802_11_parse_elems = 0x13b91; + str_2char2num = 0x13d9d; + key_2char2num = 0x13db9; + convert_ip_addr = 0x13dd1; + rom_psk_PasswordHash = 0x13e9d; + rom_psk_CalcGTK = 0x13ed5; + rom_psk_CalcPTK = 0x13f69; + wep_80211_encrypt = 0x14295; + wep_80211_decrypt = 0x142f5; + tkip_micappendbyte = 0x14389; + rtw_secmicsetkey = 0x143d9; + rtw_secmicappend = 0x14419; + rtw_secgetmic = 0x14435; + rtw_seccalctkipmic = 0x1449d; + tkip_phase1 = 0x145a5; + tkip_phase2 = 0x14725; + tkip_80211_encrypt = 0x14941; + tkip_80211_decrypt = 0x149d5; + aes1_encrypt = 0x14a8d; + aesccmp_construct_mic_iv = 0x14c65; + aesccmp_construct_mic_header1 = 0x14ccd; + aesccmp_construct_mic_header2 = 0x14d21; + aesccmp_construct_ctr_preload = 0x14db5; + aes_80211_encrypt = 0x14e29; + aes_80211_decrypt = 0x151ad; + _sha1_process_message_block = 0x155b9; + _sha1_pad_message = 0x15749; + rt_sha1_init = 0x157e5; + rt_sha1_update = 0x15831; + rt_sha1_finish = 0x158a9; + rt_hmac_sha1 = 0x15909; + rom_aes_128_cbc_encrypt = 0x15a65; + rom_aes_128_cbc_decrypt = 0x15ae1; + rom_rijndaelKeySetupEnc = 0x15b5d; + rom_aes_decrypt_init = 0x15c39; + rom_aes_internal_decrypt = 0x15d15; + rom_aes_decrypt_deinit = 0x16071; + rom_aes_encrypt_init = 0x16085; + rom_aes_internal_encrypt = 0x1609d; + rom_aes_encrypt_deinit = 0x16451; + bignum_init = 0x17b35; + bignum_deinit = 0x17b61; + bignum_get_unsigned_bin_len = 0x17b81; + bignum_get_unsigned_bin = 0x17b85; + bignum_set_unsigned_bin = 0x17c21; + bignum_cmp = 0x17cd1; + bignum_cmp_d = 0x17cd5; + bignum_add = 0x17cfd; + bignum_sub = 0x17d0d; + bignum_mul = 0x17d1d; + bignum_exptmod = 0x17d2d; + WPS_realloc = 0x17d51; + os_zalloc = 0x17d99; + rom_hmac_sha256_vector = 0x17dc1; + rom_hmac_sha256 = 0x17ebd; + rom_sha256_vector = 0x18009; + phy_CalculateBitShift = 0x18221; + PHY_SetBBReg_8195A = 0x18239; + PHY_QueryBBReg_8195A = 0x18279; + ROM_odm_QueryRxPwrPercentage = 0x1829d; + ROM_odm_EVMdbToPercentage = 0x182bd; + ROM_odm_SignalScaleMapping_8195A = 0x182e5; + ROM_odm_FalseAlarmCounterStatistics = 0x183cd; + ROM_odm_SetEDCCAThreshold = 0x18721; + ROM_odm_SetTRxMux = 0x18749; + ROM_odm_SetCrystalCap = 0x18771; + ROM_odm_GetDefaultCrytaltalCap = 0x187d5; + ROM_ODM_CfoTrackingReset = 0x187e9; + ROM_odm_CfoTrackingFlow = 0x18811; + curve25519_donna = 0x1965d; + aes_test_alignment_detection = 0x1a391; + aes_mode_reset = 0x1a3ed; + aes_ecb_encrypt = 0x1a3f9; + aes_ecb_decrypt = 0x1a431; + aes_cbc_encrypt = 0x1a469; + aes_cbc_decrypt = 0x1a579; + aes_cfb_encrypt = 0x1a701; + aes_cfb_decrypt = 0x1a9e5; + aes_ofb_crypt = 0x1acc9; + aes_ctr_crypt = 0x1af7d; + aes_encrypt_key128 = 0x1b289; + aes_encrypt_key192 = 0x1b2a5; + aes_encrypt_key256 = 0x1b2c1; + aes_encrypt_key = 0x1b2e1; + aes_decrypt_key128 = 0x1b351; + aes_decrypt_key192 = 0x1b36d; + aes_decrypt_key256 = 0x1b389; + aes_decrypt_key = 0x1b3a9; + aes_init = 0x1b419; + CRYPTO_chacha_20 = 0x1b41d; + CRYPTO_poly1305_init = 0x1bc25; + CRYPTO_poly1305_update = 0x1bd09; + CRYPTO_poly1305_finish = 0x1bd8d; + rom_sha512_starts = 0x1ceb5; + rom_sha512_update = 0x1d009; + rom_sha512_finish = 0x1d011; + rom_sha512 = 0x1d261; + rom_sha512_hmac_starts = 0x1d299; + rom_sha512_hmac_update = 0x1d35d; + rom_sha512_hmac_finish = 0x1d365; + rom_sha512_hmac_reset = 0x1d3b5; + rom_sha512_hmac = 0x1d3d1; + rom_sha512_hkdf = 0x1d40d; + rom_ed25519_gen_keypair = 0x1d501; + rom_ed25519_gen_signature = 0x1d505; + rom_ed25519_verify_signature = 0x1d51d; + rom_ed25519_crypto_sign_seed_keypair = 0x1d521; + rom_ed25519_crypto_sign_detached = 0x1d579; + rom_ed25519_crypto_sign_verify_detached = 0x1d655; + rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d; + rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35; + rom_ed25519_ge_p3_tobytes = 0x207d5; + rom_ed25519_ge_scalarmult_base = 0x20821; + rom_ed25519_ge_tobytes = 0x209e1; + rom_ed25519_sc_muladd = 0x20a2d; + rom_ed25519_sc_reduce = 0x2603d; + __rtl_memchr_v1_00 = 0x28a4d; + __rtl_memcmp_v1_00 = 0x28ae1; + __rtl_memcpy_v1_00 = 0x28b49; + __rtl_memmove_v1_00 = 0x28bed; + __rtl_memset_v1_00 = 0x28cb5; + __rtl_strcat_v1_00 = 0x28d49; + __rtl_strchr_v1_00 = 0x28d91; + __rtl_strcmp_v1_00 = 0x28e55; + __rtl_strcpy_v1_00 = 0x28ec9; + __rtl_strlen_v1_00 = 0x28f15; + __rtl_strncat_v1_00 = 0x28f69; + __rtl_strncmp_v1_00 = 0x28fc5; + __rtl_strncpy_v1_00 = 0x2907d; + __rtl_strstr_v1_00 = 0x293cd; + __rtl_strsep_v1_00 = 0x2960d; + __rtl_strtok_v1_00 = 0x29619; + __rtl__strtok_r_v1_00 = 0x2962d; + __rtl_strtok_r_v1_00 = 0x29691; + __rtl_close_v1_00 = 0x29699; + __rtl_fstat_v1_00 = 0x296ad; + __rtl_isatty_v1_00 = 0x296c1; + __rtl_lseek_v1_00 = 0x296d5; + __rtl_open_v1_00 = 0x296e9; + __rtl_read_v1_00 = 0x296fd; + __rtl_write_v1_00 = 0x29711; + __rtl_sbrk_v1_00 = 0x29725; + __rtl_ltoa_v1_00 = 0x297bd; + __rtl_ultoa_v1_00 = 0x29855; + __rtl_dtoi_v1_00 = 0x298c5; + __rtl_dtoi64_v1_00 = 0x29945; + __rtl_dtoui_v1_00 = 0x299dd; + __rtl_ftol_v1_00 = 0x299e5; + __rtl_itof_v1_00 = 0x29a51; + __rtl_itod_v1_00 = 0x29ae9; + __rtl_i64tod_v1_00 = 0x29b79; + __rtl_uitod_v1_00 = 0x29c55; + __rtl_ftod_v1_00 = 0x29d2d; + __rtl_dtof_v1_00 = 0x29de9; + __rtl_uitof_v1_00 = 0x29e89; + __rtl_fadd_v1_00 = 0x29f65; + __rtl_fsub_v1_00 = 0x2a261; + __rtl_fmul_v1_00 = 0x2a559; + __rtl_fdiv_v1_00 = 0x2a695; + __rtl_dadd_v1_00 = 0x2a825; + __rtl_dsub_v1_00 = 0x2aed9; + __rtl_dmul_v1_00 = 0x2b555; + __rtl_ddiv_v1_00 = 0x2b8ad; + __rtl_dcmpeq_v1_00 = 0x2be4d; + __rtl_dcmplt_v1_00 = 0x2bebd; + __rtl_dcmpgt_v1_00 = 0x2bf51; + __rtl_dcmple_v1_00 = 0x2c049; + __rtl_fcmplt_v1_00 = 0x2c139; + __rtl_fcmpgt_v1_00 = 0x2c195; + __rtl_cos_f32_v1_00 = 0x2c229; + __rtl_sin_f32_v1_00 = 0x2c435; + __rtl_fabs_v1_00 = 0x2c639; + __rtl_fabsf_v1_00 = 0x2c641; + __rtl_dtoa_r_v1_00 = 0x2c77d; + __rom_mallocr_init_v1_00 = 0x2d7d1; + __rtl_free_r_v1_00 = 0x2d841; + __rtl_malloc_r_v1_00 = 0x2da31; + __rtl_realloc_r_v1_00 = 0x2df55; + __rtl_memalign_r_v1_00 = 0x2e331; + __rtl_valloc_r_v1_00 = 0x2e421; + __rtl_pvalloc_r_v1_00 = 0x2e42d; + __rtl_calloc_r_v1_00 = 0x2e441; + __rtl_cfree_r_v1_00 = 0x2e4a9; + __rtl_Balloc_v1_00 = 0x2e515; + __rtl_Bfree_v1_00 = 0x2e571; + __rtl_i2b_v1_00 = 0x2e585; + __rtl_multadd_v1_00 = 0x2e599; + __rtl_mult_v1_00 = 0x2e629; + __rtl_pow5mult_v1_00 = 0x2e769; + __rtl_hi0bits_v1_00 = 0x2e809; + __rtl_d2b_v1_00 = 0x2e845; + __rtl_lshift_v1_00 = 0x2e901; + __rtl_cmp_v1_00 = 0x2e9bd; + __rtl_diff_v1_00 = 0x2ea01; + __rtl_sread_v1_00 = 0x2eae9; + __rtl_seofread_v1_00 = 0x2eb39; + __rtl_swrite_v1_00 = 0x2eb3d; + __rtl_sseek_v1_00 = 0x2ebc1; + __rtl_sclose_v1_00 = 0x2ec11; + __rtl_sbrk_r_v1_00 = 0x2ec41; + __rtl_fflush_r_v1_00 = 0x2ef8d; + __rtl_vfprintf_r_v1_00 = 0x2f661; + __rtl_fpclassifyd = 0x30c15; + CpkClkTbl = 0x30c68; + ROM_IMG1_VALID_PATTEN = 0x30c80; + SpicCalibrationPattern = 0x30c88; + SpicInitCPUCLK = 0x30c98; + BAUDRATE = 0x30ca8; + OVSR = 0x30d1c; + DIV = 0x30d90; + OVSR_ADJ = 0x30e04; + __AES_rcon = 0x30e78; + __AES_Te4 = 0x30ea0; + I2CDmaChNo = 0x312a0; + _GPIO_PinMap_Chip2IP_8195a = 0x312b4; + _GPIO_PinMap_PullCtrl_8195a = 0x3136c; + _GPIO_SWPORT_DDR_TBL = 0x31594; + _GPIO_EXT_PORT_TBL = 0x31598; + _GPIO_SWPORT_DR_TBL = 0x3159c; + UartLogRomCmdTable = 0x316a0; + _HalRuartOp = 0x31700; + _HalGdmaOp = 0x31760; + RTW_WPA_OUI_TYPE = 0x3540c; + WPA_CIPHER_SUITE_NONE = 0x35410; + WPA_CIPHER_SUITE_WEP40 = 0x35414; + WPA_CIPHER_SUITE_TKIP = 0x35418; + WPA_CIPHER_SUITE_CCMP = 0x3541c; + WPA_CIPHER_SUITE_WEP104 = 0x35420; + RSN_CIPHER_SUITE_NONE = 0x35424; + RSN_CIPHER_SUITE_WEP40 = 0x35428; + RSN_CIPHER_SUITE_TKIP = 0x3542c; + RSN_CIPHER_SUITE_CCMP = 0x35430; + RSN_CIPHER_SUITE_WEP104 = 0x35434; + RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444; + RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448; + RSN_VERSION_BSD = 0x3544c; + rom_wps_Te0 = 0x35988; + rom_wps_rcons = 0x35d88; + rom_wps_Td4s = 0x35d94; + rom_wps_Td0 = 0x35e94; + __rom_b_cut_end__ = 0x4467c; + __rom_c_cut_text_start__ = 0x4467c; + HalInitPlatformLogUartV02 = 0x4467d; + HalReInitPlatformLogUartV02 = 0x4471d; + HalInitPlatformTimerV02 = 0x44755; + HalShowBuildInfoV02 = 0x447cd; + SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831; + HalSpiInitV02 = 0x4488d; + HalBootFlowV02 = 0x44a29; + HalInitialROMCodeGlobalVarV02 = 0x44ae5; + HalResetVsrV02 = 0x44b41; + HalI2CSendRtl8195aV02 = 0x44ce1; + HalI2CSetCLKRtl8195aV02 = 0x44d59; + RtkI2CSendV02 = 0x4508d; + RtkI2CReceiveV02 = 0x459a1; + HalI2COpInitV02 = 0x461ed; + I2CISRHandleV02 = 0x463e9; + RtkSalI2COpInitV02 = 0x46be1; + SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25; + SpiFlashAppV02 = 0x46c85; + SpicInitRtl8195AV02 = 0x46dc5; + SpicEraseFlashRtl8195AV02 = 0x46ea1; + HalTimerIrq2To7HandleV02 = 0x46f5d; + HalTimerIrqRegisterRtl8195aV02 = 0x46fe1; + HalTimerInitRtl8195aV02 = 0x4706d; + HalTimerReadCountRtl8195aV02 = 0x471b5; + HalTimerReLoadRtl8195aV02 = 0x471d1; + HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d; + HalTimerDeInitRtl8195aV02 = 0x472c1; + HalTimerOpInitV02 = 0x472f9; + GPIO_LockV02 = 0x47345; + GPIO_UnLockV02 = 0x47379; + GPIO_Int_Clear_8195aV02 = 0x473a5; + HAL_GPIO_IntCtrl_8195aV02 = 0x473b5; + FindElementIndexV02 = 0x47541; + HalRuartInitRtl8195aV02 = 0x4756d; + DramInit_rom = 0x47619; + ChangeRandSeed_rom = 0x47979; + Sdr_Rand2_rom = 0x47985; + MemTest_rom = 0x479dd; + SdrCalibration_rom = 0x47a45; + SdrControllerInit_rom = 0x47d99; + SDIO_EnterCritical = 0x47e39; + SDIO_ExitCritical = 0x47e85; + SDIO_IRQ_Handler_Rom = 0x47ec5; + SDIO_Interrupt_Init_Rom = 0x47f31; + SDIO_Device_Init_Rom = 0x47f81; + SDIO_Interrupt_DeInit_Rom = 0x48215; + SDIO_Device_DeInit_Rom = 0x48255; + SDIO_Enable_Interrupt_Rom = 0x48281; + SDIO_Disable_Interrupt_Rom = 0x482a1; + SDIO_Clear_ISR_Rom = 0x482c1; + SDIO_Alloc_Rx_Pkt_Rom = 0x482d9; + SDIO_Free_Rx_Pkt_Rom = 0x48331; + SDIO_Recycle_Rx_BD_Rom = 0x48355; + SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1; + SDIO_RxTask_Rom = 0x4851d; + SDIO_Process_H2C_IOMsg_Rom = 0x4856d; + SDIO_Send_C2H_IOMsg_Rom = 0x4859d; + SDIO_Process_RPWM_Rom = 0x485b5; + SDIO_Reset_Cmd_Rom = 0x485e9; + SDIO_Rx_Data_Transaction_Rom = 0x48611; + SDIO_Send_C2H_PktMsg_Rom = 0x48829; + SDIO_Register_Tx_Callback_Rom = 0x488f5; + SDIO_ReadMem_Rom = 0x488fd; + SDIO_WriteMem_Rom = 0x489a9; + SDIO_SetMem_Rom = 0x48a69; + SDIO_TX_Pkt_Handle_Rom = 0x48b29; + SDIO_TX_FIFO_DataReady_Rom = 0x48c69; + SDIO_IRQ_Handler_BH_Rom = 0x48d95; + SDIO_TxTask_Rom = 0x48e9d; + SDIO_TaskUp_Rom = 0x48eed; + SDIO_Boot_Up = 0x48f55; + __rom_c_cut_text_end__ = 0x49070; + __rom_c_cut_rodata_start__ = 0x49070; + BAUDRATE_v02 = 0x49070; + OVSR_v02 = 0x490fc; + DIV_v02 = 0x49188; + OVSR_ADJ_v02 = 0x49214; + SdrDramInfo_rom = 0x492a0; + SdrDramTiming_rom = 0x492b4; + SdrDramModeReg_rom = 0x492e8; + SdrDramDev_rom = 0x49304; + __rom_c_cut_rodata_end__ = 0x49314; + NewVectorTable = 0x10000000; + UserhandlerTable = 0x10000100; + UserIrqDataTable = 0x10000200; + __rom_bss_start__ = 0x10000300; + CfgSysDebugWarn = 0x10000300; + CfgSysDebugInfo = 0x10000304; + CfgSysDebugErr = 0x10000308; + ConfigDebugWarn = 0x1000030c; + ConfigDebugInfo = 0x10000310; + ConfigDebugErr = 0x10000314; + HalTimerOp = 0x10000318; + GPIOState = 0x10000334; + gTimerRecord = 0x1000034c; + SSI_DBG_CONFIG = 0x10000350; + _pHAL_Gpio_Adapter = 0x10000354; + Timer2To7VectorTable = 0x10000358; + pUartLogCtl = 0x10000384; + UartLogBuf = 0x10000388; + UartLogCtl = 0x10000408; + UartLogHistoryBuf = 0x10000430; + ArgvArray = 0x100006ac; + rom_wlan_ram_map = 0x100006d4; + FalseAlmCnt = 0x100006e0; + ROMInfo = 0x10000720; + DM_CfoTrack = 0x10000738; + rom_libgloss_ram_map = 0x10000760; + __rtl_errno = 0x10000bc4; +} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sdio.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sdio.h new file mode 100644 index 00000000000..788413fea1a --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sdio.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_RTL8195A_SDIO_H +#define MBED_RTL8195A_SDIO_H + +__BUILD_CCTRL_MACRO(SDIOD, REG_PESOC_HCI_CLK_CTRL0) +__BUILD_CCTRL_MACRO(SDIOH, REG_PESOC_HCI_CLK_CTRL0) + +#define __SDIOD_Enable() \ + do { \ + __RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN); \ + __RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN); \ + } while (0) + +#define __SDIOH_Enable() \ + do { \ + __RTK_PERI_SETBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN); \ + } while (0) + +#define __SDIOD_Disable() \ + do { \ + __RTK_READ32(SDIO_DEVICE_REG_BASE, 0); \ + __RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN); \ + __RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN); \ + } while (0) + +#define __SDIOH_Disable() \ + do { \ + __RTK_READ32(SDIO_HOST_REG_BASE, 0); \ + __RTK_PERI_CLRBIT(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN); \ + } while (0) + +// PERI_MCTRL_HCI +#define __SDIOD_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN) +#define __SDIOH_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN) +#define __SDIOD_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN) +#define __SDIOH_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN) +#define __MII_PINMUX_Enable() __RTK_PERI_SETBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN) +#define __MII_PINMUX_Disable() __RTK_PERI_CLRBIT(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN) + +// Interface for HAL functions +extern void SDIO_HST_Disable(void); +extern void SDIO_DEV_Disable(void); + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_spi_flash.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_spi_flash.h new file mode 100644 index 00000000000..e2127b789af --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_spi_flash.h @@ -0,0 +1,1143 @@ +#ifndef _RTL8195A_SPI_FLASH_H +#define _RTL8195A_SPI_FLASH_H + +#define CPU_OPT_WIDTH 0x1F + +//2 REG_NOT_VALID + +//2 REG_SPIC_CTRLR0 + +#define BIT_SHIFT_CK_MTIMES 23 +#define BIT_MASK_CK_MTIMES 0x1f +#define BIT_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES) +#define BIT_CTRL_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES) +#define BIT_GET_CK_MTIMES(x) (((x) >> BIT_SHIFT_CK_MTIMES) & BIT_MASK_CK_MTIMES) + +#define BIT_FAST_RD BIT(22) +#define BIT_SHIFT_FAST_RD 22 +#define BIT_MASK_FAST_RD 0x1 +#define BIT_CTRL_FAST_RD(x) (((x) & BIT_MASK_FAST_RD) << BIT_SHIFT_FAST_RD) + + +#define BIT_SHIFT_CMD_CH 20 +#define BIT_MASK_CMD_CH 0x3 +#define BIT_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH) +#define BIT_CTRL_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH) +#define BIT_GET_CMD_CH(x) (((x) >> BIT_SHIFT_CMD_CH) & BIT_MASK_CMD_CH) + + +#define BIT_SHIFT_DATA_CH 18 +#define BIT_MASK_DATA_CH 0x3 +#define BIT_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH) +#define BIT_CTRL_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH) +#define BIT_GET_DATA_CH(x) (((x) >> BIT_SHIFT_DATA_CH) & BIT_MASK_DATA_CH) + + +#define BIT_SHIFT_ADDR_CH 16 +#define BIT_MASK_ADDR_CH 0x3 +#define BIT_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH) +#define BIT_CTRL_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH) +#define BIT_GET_ADDR_CH(x) (((x) >> BIT_SHIFT_ADDR_CH) & BIT_MASK_ADDR_CH) + + +#define BIT_SHIFT_TMOD 8 +#define BIT_MASK_TMOD 0x3 +#define BIT_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD) +#define BIT_CTRL_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD) +#define BIT_GET_TMOD(x) (((x) >> BIT_SHIFT_TMOD) & BIT_MASK_TMOD) + +#define BIT_SCPOL BIT(7) +#define BIT_SHIFT_SCPOL 7 +#define BIT_MASK_SCPOL 0x1 +#define BIT_CTRL_SCPOL(x) (((x) & BIT_MASK_SCPOL) << BIT_SHIFT_SCPOL) + +#define BIT_SCPH BIT(6) +#define BIT_SHIFT_SCPH 6 +#define BIT_MASK_SCPH 0x1 +#define BIT_CTRL_SCPH(x) (((x) & BIT_MASK_SCPH) << BIT_SHIFT_SCPH) + +//2 REG_SPIC_CTRLR1 + +#define BIT_SHIFT_NDF 0 +#define BIT_MASK_NDF 0xfff +#define BIT_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF) +#define BIT_CTRL_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF) +#define BIT_GET_NDF(x) (((x) >> BIT_SHIFT_NDF) & BIT_MASK_NDF) + + +//2 REG_SPIC_SSIENR +#define BIT_ATCK_CMD BIT(1) +#define BIT_SHIFT_ATCK_CMD 1 +#define BIT_MASK_ATCK_CMD 0x1 +#define BIT_CTRL_ATCK_CMD(x) (((x) & BIT_MASK_ATCK_CMD) << BIT_SHIFT_ATCK_CMD) + +#define BIT_SPIC_EN BIT(0) +#define BIT_SHIFT_SPIC_EN 0 +#define BIT_MASK_SPIC_EN 0x1 +#define BIT_CTRL_SPIC_EN(x) (((x) & BIT_MASK_SPIC_EN) << BIT_SHIFT_SPIC_EN) + +//2 REG_SPIC_MWCR + +//2 REG_SPIC_SER +#define BIT_SER BIT(0) +#define BIT_SHIFT_SER 0 +#define BIT_MASK_SER 0x1 +#define BIT_CTRL_SER(x) (((x) & BIT_MASK_SER) << BIT_SHIFT_SER) + +//2 REG_SPIC_BAUDR + +#define BIT_SHIFT_SCKDV 0 +#define BIT_MASK_SCKDV 0xffff +#define BIT_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV) +#define BIT_CTRL_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV) +#define BIT_GET_SCKDV(x) (((x) >> BIT_SHIFT_SCKDV) & BIT_MASK_SCKDV) + + +//2 REG_SPIC_TXFTLR + +#define BIT_SHIFT_TFT 0 +#define BIT_MASK_TFT 0x1f +#define BIT_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT) +#define BIT_CTRL_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT) +#define BIT_GET_TFT(x) (((x) >> BIT_SHIFT_TFT) & BIT_MASK_TFT) + + +//2 REG_SPIC_RXFTLR + +#define BIT_SHIFT_RFT 0 +#define BIT_MASK_RFT 0x1f +#define BIT_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT) +#define BIT_CTRL_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT) +#define BIT_GET_RFT(x) (((x) >> BIT_SHIFT_RFT) & BIT_MASK_RFT) + + +//2 REG_SPIC_TXFLR + +#define BIT_SHIFT_TXFL 0 +#define BIT_MASK_TXFL 0x3f +#define BIT_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL) +#define BIT_CTRL_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL) +#define BIT_GET_TXFL(x) (((x) >> BIT_SHIFT_TXFL) & BIT_MASK_TXFL) + + +//2 REG_SPIC_RXFLR + +#define BIT_SHIFT_RXFL 0 +#define BIT_MASK_RXFL 0x3f +#define BIT_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL) +#define BIT_CTRL_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL) +#define BIT_GET_RXFL(x) (((x) >> BIT_SHIFT_RXFL) & BIT_MASK_RXFL) + + +//2 REG_SPIC_SR +#define BIT_TXE BIT(5) +#define BIT_SHIFT_TXE 5 +#define BIT_MASK_TXE 0x1 +#define BIT_CTRL_TXE(x) (((x) & BIT_MASK_TXE) << BIT_SHIFT_TXE) + +#define BIT_RFF BIT(4) +#define BIT_SHIFT_RFF 4 +#define BIT_MASK_RFF 0x1 +#define BIT_CTRL_RFF(x) (((x) & BIT_MASK_RFF) << BIT_SHIFT_RFF) + +#define BIT_RFNE BIT(3) +#define BIT_SHIFT_RFNE 3 +#define BIT_MASK_RFNE 0x1 +#define BIT_CTRL_RFNE(x) (((x) & BIT_MASK_RFNE) << BIT_SHIFT_RFNE) + +#define BIT_TFE BIT(2) +#define BIT_SHIFT_TFE 2 +#define BIT_MASK_TFE 0x1 +#define BIT_CTRL_TFE(x) (((x) & BIT_MASK_TFE) << BIT_SHIFT_TFE) + +#define BIT_TFNF BIT(1) +#define BIT_SHIFT_TFNF 1 +#define BIT_MASK_TFNF 0x1 +#define BIT_CTRL_TFNF(x) (((x) & BIT_MASK_TFNF) << BIT_SHIFT_TFNF) + +#define BIT_BUSY BIT(0) +#define BIT_SHIFT_BUSY 0 +#define BIT_MASK_BUSY 0x1 +#define BIT_CTRL_BUSY(x) (((x) & BIT_MASK_BUSY) << BIT_SHIFT_BUSY) + +//2 REG_SPIC_IMR +#define BIT_TXSIM BIT(9) +#define BIT_SHIFT_TXSIM 9 +#define BIT_MASK_TXSIM 0x1 +#define BIT_CTRL_TXSIM(x) (((x) & BIT_MASK_TXSIM) << BIT_SHIFT_TXSIM) + +#define BIT_ACEIM BIT(8) +#define BIT_SHIFT_ACEIM 8 +#define BIT_MASK_ACEIM 0x1 +#define BIT_CTRL_ACEIM(x) (((x) & BIT_MASK_ACEIM) << BIT_SHIFT_ACEIM) + +#define BIT_BYEIM BIT(7) +#define BIT_SHIFT_BYEIM 7 +#define BIT_MASK_BYEIM 0x1 +#define BIT_CTRL_BYEIM(x) (((x) & BIT_MASK_BYEIM) << BIT_SHIFT_BYEIM) + +#define BIT_WBEIM BIT(6) +#define BIT_SHIFT_WBEIM 6 +#define BIT_MASK_WBEIM 0x1 +#define BIT_CTRL_WBEIM(x) (((x) & BIT_MASK_WBEIM) << BIT_SHIFT_WBEIM) + +#define BIT_FSEIM BIT(5) +#define BIT_SHIFT_FSEIM 5 +#define BIT_MASK_FSEIM 0x1 +#define BIT_CTRL_FSEIM(x) (((x) & BIT_MASK_FSEIM) << BIT_SHIFT_FSEIM) + +#define BIT_RXFIM BIT(4) +#define BIT_SHIFT_RXFIM 4 +#define BIT_MASK_RXFIM 0x1 +#define BIT_CTRL_RXFIM(x) (((x) & BIT_MASK_RXFIM) << BIT_SHIFT_RXFIM) + +#define BIT_RXOIM BIT(3) +#define BIT_SHIFT_RXOIM 3 +#define BIT_MASK_RXOIM 0x1 +#define BIT_CTRL_RXOIM(x) (((x) & BIT_MASK_RXOIM) << BIT_SHIFT_RXOIM) + +#define BIT_RXUIM BIT(2) +#define BIT_SHIFT_RXUIM 2 +#define BIT_MASK_RXUIM 0x1 +#define BIT_CTRL_RXUIM(x) (((x) & BIT_MASK_RXUIM) << BIT_SHIFT_RXUIM) + +#define BIT_TXOIM BIT(1) +#define BIT_SHIFT_TXOIM 1 +#define BIT_MASK_TXOIM 0x1 +#define BIT_CTRL_TXOIM(x) (((x) & BIT_MASK_TXOIM) << BIT_SHIFT_TXOIM) + +#define BIT_TXEIM BIT(0) +#define BIT_SHIFT_TXEIM 0 +#define BIT_MASK_TXEIM 0x1 +#define BIT_CTRL_TXEIM(x) (((x) & BIT_MASK_TXEIM) << BIT_SHIFT_TXEIM) + +//2 REG_SPIC_ISR +#define BIT_TXSIS BIT(9) +#define BIT_SHIFT_TXSIS 9 +#define BIT_MASK_TXSIS 0x1 +#define BIT_CTRL_TXSIS(x) (((x) & BIT_MASK_TXSIS) << BIT_SHIFT_TXSIS) + +#define BIT_ACEIS BIT(8) +#define BIT_SHIFT_ACEIS 8 +#define BIT_MASK_ACEIS 0x1 +#define BIT_CTRL_ACEIS(x) (((x) & BIT_MASK_ACEIS) << BIT_SHIFT_ACEIS) + +#define BIT_BYEIS BIT(7) +#define BIT_SHIFT_BYEIS 7 +#define BIT_MASK_BYEIS 0x1 +#define BIT_CTRL_BYEIS(x) (((x) & BIT_MASK_BYEIS) << BIT_SHIFT_BYEIS) + +#define BIT_WBEIS BIT(6) +#define BIT_SHIFT_WBEIS 6 +#define BIT_MASK_WBEIS 0x1 +#define BIT_CTRL_WBEIS(x) (((x) & BIT_MASK_WBEIS) << BIT_SHIFT_WBEIS) + +#define BIT_FSEIS BIT(5) +#define BIT_SHIFT_FSEIS 5 +#define BIT_MASK_FSEIS 0x1 +#define BIT_CTRL_FSEIS(x) (((x) & BIT_MASK_FSEIS) << BIT_SHIFT_FSEIS) + +#define BIT_RXFIS BIT(4) +#define BIT_SHIFT_RXFIS 4 +#define BIT_MASK_RXFIS 0x1 +#define BIT_CTRL_RXFIS(x) (((x) & BIT_MASK_RXFIS) << BIT_SHIFT_RXFIS) + +#define BIT_RXOIS BIT(3) +#define BIT_SHIFT_RXOIS 3 +#define BIT_MASK_RXOIS 0x1 +#define BIT_CTRL_RXOIS(x) (((x) & BIT_MASK_RXOIS) << BIT_SHIFT_RXOIS) + +#define BIT_RXUIS BIT(2) +#define BIT_SHIFT_RXUIS 2 +#define BIT_MASK_RXUIS 0x1 +#define BIT_CTRL_RXUIS(x) (((x) & BIT_MASK_RXUIS) << BIT_SHIFT_RXUIS) + +#define BIT_TXOIS BIT(1) +#define BIT_SHIFT_TXOIS 1 +#define BIT_MASK_TXOIS 0x1 +#define BIT_CTRL_TXOIS(x) (((x) & BIT_MASK_TXOIS) << BIT_SHIFT_TXOIS) + +#define BIT_TXEIS BIT(0) +#define BIT_SHIFT_TXEIS 0 +#define BIT_MASK_TXEIS 0x1 +#define BIT_CTRL_TXEIS(x) (((x) & BIT_MASK_TXEIS) << BIT_SHIFT_TXEIS) + +//2 REG_SPIC_RISR +#define BIT_ACEIR BIT(8) +#define BIT_SHIFT_ACEIR 8 +#define BIT_MASK_ACEIR 0x1 +#define BIT_CTRL_ACEIR(x) (((x) & BIT_MASK_ACEIR) << BIT_SHIFT_ACEIR) + +#define BIT_BYEIR BIT(7) +#define BIT_SHIFT_BYEIR 7 +#define BIT_MASK_BYEIR 0x1 +#define BIT_CTRL_BYEIR(x) (((x) & BIT_MASK_BYEIR) << BIT_SHIFT_BYEIR) + +#define BIT_WBEIR BIT(6) +#define BIT_SHIFT_WBEIR 6 +#define BIT_MASK_WBEIR 0x1 +#define BIT_CTRL_WBEIR(x) (((x) & BIT_MASK_WBEIR) << BIT_SHIFT_WBEIR) + +#define BIT_FSEIR BIT(5) +#define BIT_SHIFT_FSEIR 5 +#define BIT_MASK_FSEIR 0x1 +#define BIT_CTRL_FSEIR(x) (((x) & BIT_MASK_FSEIR) << BIT_SHIFT_FSEIR) + +#define BIT_RXFIR BIT(4) +#define BIT_SHIFT_RXFIR 4 +#define BIT_MASK_RXFIR 0x1 +#define BIT_CTRL_RXFIR(x) (((x) & BIT_MASK_RXFIR) << BIT_SHIFT_RXFIR) + +#define BIT_RXOIR BIT(3) +#define BIT_SHIFT_RXOIR 3 +#define BIT_MASK_RXOIR 0x1 +#define BIT_CTRL_RXOIR(x) (((x) & BIT_MASK_RXOIR) << BIT_SHIFT_RXOIR) + +#define BIT_RXUIR BIT(2) +#define BIT_SHIFT_RXUIR 2 +#define BIT_MASK_RXUIR 0x1 +#define BIT_CTRL_RXUIR(x) (((x) & BIT_MASK_RXUIR) << BIT_SHIFT_RXUIR) + +#define BIT_TXOIR BIT(1) +#define BIT_SHIFT_TXOIR 1 +#define BIT_MASK_TXOIR 0x1 +#define BIT_CTRL_TXOIR(x) (((x) & BIT_MASK_TXOIR) << BIT_SHIFT_TXOIR) + +#define BIT_TXEIR BIT(0) +#define BIT_SHIFT_TXEIR 0 +#define BIT_MASK_TXEIR 0x1 +#define BIT_CTRL_TXEIR(x) (((x) & BIT_MASK_TXEIR) << BIT_SHIFT_TXEIR) + +//2 REG_SPIC_TXOICR +#define BIT_TXOICR BIT(0) +#define BIT_SHIFT_TXOICR 0 +#define BIT_MASK_TXOICR 0x1 +#define BIT_CTRL_TXOICR(x) (((x) & BIT_MASK_TXOICR) << BIT_SHIFT_TXOICR) + +//2 REG_SPIC_RXOICR +#define BIT_RXOCIR BIT(0) +#define BIT_SHIFT_RXOCIR 0 +#define BIT_MASK_RXOCIR 0x1 +#define BIT_CTRL_RXOCIR(x) (((x) & BIT_MASK_RXOCIR) << BIT_SHIFT_RXOCIR) + +//2 REG_SPC_RXUICR +#define BIT_RXUICR BIT(0) +#define BIT_SHIFT_RXUICR 0 +#define BIT_MASK_RXUICR 0x1 +#define BIT_CTRL_RXUICR(x) (((x) & BIT_MASK_RXUICR) << BIT_SHIFT_RXUICR) + +//2 REG_SPIC_MSTICR +#define BIT_MSTICR BIT(0) +#define BIT_SHIFT_MSTICR 0 +#define BIT_MASK_MSTICR 0x1 +#define BIT_CTRL_MSTICR(x) (((x) & BIT_MASK_MSTICR) << BIT_SHIFT_MSTICR) + +//2 REG_SPIC_ICR + +#define BIT_SHIFT_ICR 0 +#define BIT_MASK_ICR 0xff +#define BIT_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR) +#define BIT_CTRL_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR) +#define BIT_GET_ICR(x) (((x) >> BIT_SHIFT_ICR) & BIT_MASK_ICR) + + +//2 REG_SPIC_DMACR + +//2 REG_SPIC_DMATDLR0 + +//2 REG_SPIC_DMATDLR1 + +//2 REG_SPIC_IDR + +#define BIT_SHIFT_IDCODE 0 +#define BIT_MASK_IDCODE 0xffffffffL +#define BIT_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE) +#define BIT_CTRL_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE) +#define BIT_GET_IDCODE(x) (((x) >> BIT_SHIFT_IDCODE) & BIT_MASK_IDCODE) + + +//2 REG_SPIC_VERSION + +#define BIT_SHIFT_SPIC_VERSION 0 +#define BIT_MASK_SPIC_VERSION 0xffffffffL +#define BIT_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION) +#define BIT_CTRL_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION) +#define BIT_GET_SPIC_VERSION(x) (((x) >> BIT_SHIFT_SPIC_VERSION) & BIT_MASK_SPIC_VERSION) + + +//2 REG_SPIC_DR0 + +#define BIT_SHIFT_DR0 0 +#define BIT_MASK_DR0 0xffffffffL +#define BIT_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0) +#define BIT_CTRL_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0) +#define BIT_GET_DR0(x) (((x) >> BIT_SHIFT_DR0) & BIT_MASK_DR0) + + +//2 REG_SPIC_DR1 + +#define BIT_SHIFT_DR1 0 +#define BIT_MASK_DR1 0xffffffffL +#define BIT_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1) +#define BIT_CTRL_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1) +#define BIT_GET_DR1(x) (((x) >> BIT_SHIFT_DR1) & BIT_MASK_DR1) + + +//2 REG_SPIC_DR2 + +#define BIT_SHIFT_DR2 0 +#define BIT_MASK_DR2 0xffffffffL +#define BIT_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2) +#define BIT_CTRL_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2) +#define BIT_GET_DR2(x) (((x) >> BIT_SHIFT_DR2) & BIT_MASK_DR2) + + +//2 REG_SPIC_DR3 + +#define BIT_SHIFT_DR3 0 +#define BIT_MASK_DR3 0xffffffffL +#define BIT_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3) +#define BIT_CTRL_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3) +#define BIT_GET_DR3(x) (((x) >> BIT_SHIFT_DR3) & BIT_MASK_DR3) + + +//2 REG_SPIC_DR4 + +#define BIT_SHIFT_DR4 0 +#define BIT_MASK_DR4 0xffffffffL +#define BIT_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4) +#define BIT_CTRL_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4) +#define BIT_GET_DR4(x) (((x) >> BIT_SHIFT_DR4) & BIT_MASK_DR4) + + +//2 REG_SPIC_DR5 + +#define BIT_SHIFT_DR5 0 +#define BIT_MASK_DR5 0xffffffffL +#define BIT_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5) +#define BIT_CTRL_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5) +#define BIT_GET_DR5(x) (((x) >> BIT_SHIFT_DR5) & BIT_MASK_DR5) + + +//2 REG_SPIC_DR6 + +#define BIT_SHIFT_DR6 0 +#define BIT_MASK_DR6 0xffffffffL +#define BIT_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6) +#define BIT_CTRL_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6) +#define BIT_GET_DR6(x) (((x) >> BIT_SHIFT_DR6) & BIT_MASK_DR6) + + +//2 REG_SPIC_DR7 + +#define BIT_SHIFT_DR7 0 +#define BIT_MASK_DR7 0xffffffffL +#define BIT_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7) +#define BIT_CTRL_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7) +#define BIT_GET_DR7(x) (((x) >> BIT_SHIFT_DR7) & BIT_MASK_DR7) + + +//2 REG_SPIC_DR8 + +#define BIT_SHIFT_DR8 0 +#define BIT_MASK_DR8 0xffffffffL +#define BIT_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8) +#define BIT_CTRL_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8) +#define BIT_GET_DR8(x) (((x) >> BIT_SHIFT_DR8) & BIT_MASK_DR8) + + +//2 REG_SPIC_DR9 + +#define BIT_SHIFT_DR9 0 +#define BIT_MASK_DR9 0xffffffffL +#define BIT_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9) +#define BIT_CTRL_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9) +#define BIT_GET_DR9(x) (((x) >> BIT_SHIFT_DR9) & BIT_MASK_DR9) + + +//2 REG_SPIC_DR10 + +#define BIT_SHIFT_DR10 0 +#define BIT_MASK_DR10 0xffffffffL +#define BIT_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10) +#define BIT_CTRL_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10) +#define BIT_GET_DR10(x) (((x) >> BIT_SHIFT_DR10) & BIT_MASK_DR10) + + +//2 REG_SPIC_DR11 + +#define BIT_SHIFT_DR11 0 +#define BIT_MASK_DR11 0xffffffffL +#define BIT_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11) +#define BIT_CTRL_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11) +#define BIT_GET_DR11(x) (((x) >> BIT_SHIFT_DR11) & BIT_MASK_DR11) + + +//2 REG_SPIC_DR12 + +#define BIT_SHIFT_DR12 0 +#define BIT_MASK_DR12 0xffffffffL +#define BIT_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12) +#define BIT_CTRL_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12) +#define BIT_GET_DR12(x) (((x) >> BIT_SHIFT_DR12) & BIT_MASK_DR12) + + +//2 REG_SPIC_DR13 + +#define BIT_SHIFT_DR13 0 +#define BIT_MASK_DR13 0xffffffffL +#define BIT_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13) +#define BIT_CTRL_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13) +#define BIT_GET_DR13(x) (((x) >> BIT_SHIFT_DR13) & BIT_MASK_DR13) + + +//2 REG_SPIC_DR14 + +#define BIT_SHIFT_DR14 0 +#define BIT_MASK_DR14 0xffffffffL +#define BIT_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14) +#define BIT_CTRL_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14) +#define BIT_GET_DR14(x) (((x) >> BIT_SHIFT_DR14) & BIT_MASK_DR14) + + +//2 REG_SPIC_DR15 + +#define BIT_SHIFT_DR15 0 +#define BIT_MASK_DR15 0xffffffffL +#define BIT_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15) +#define BIT_CTRL_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15) +#define BIT_GET_DR15(x) (((x) >> BIT_SHIFT_DR15) & BIT_MASK_DR15) + + +//2 REG_SPIC_DR16 + +#define BIT_SHIFT_DR16 0 +#define BIT_MASK_DR16 0xffffffffL +#define BIT_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16) +#define BIT_CTRL_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16) +#define BIT_GET_DR16(x) (((x) >> BIT_SHIFT_DR16) & BIT_MASK_DR16) + + +//2 REG_SPIC_DR17 + +#define BIT_SHIFT_DR17 0 +#define BIT_MASK_DR17 0xffffffffL +#define BIT_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17) +#define BIT_CTRL_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17) +#define BIT_GET_DR17(x) (((x) >> BIT_SHIFT_DR17) & BIT_MASK_DR17) + + +//2 REG_SPIC_DR18 + +#define BIT_SHIFT_DR18 0 +#define BIT_MASK_DR18 0xffffffffL +#define BIT_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18) +#define BIT_CTRL_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18) +#define BIT_GET_DR18(x) (((x) >> BIT_SHIFT_DR18) & BIT_MASK_DR18) + + +//2 REG_SPIC_DR19 + +#define BIT_SHIFT_DR19 0 +#define BIT_MASK_DR19 0xffffffffL +#define BIT_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19) +#define BIT_CTRL_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19) +#define BIT_GET_DR19(x) (((x) >> BIT_SHIFT_DR19) & BIT_MASK_DR19) + + +//2 REG_SPIC_DR20 + +#define BIT_SHIFT_DR20 0 +#define BIT_MASK_DR20 0xffffffffL +#define BIT_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20) +#define BIT_CTRL_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20) +#define BIT_GET_DR20(x) (((x) >> BIT_SHIFT_DR20) & BIT_MASK_DR20) + + +//2 REG_SPIC_DR21 + +#define BIT_SHIFT_DR21 0 +#define BIT_MASK_DR21 0xffffffffL +#define BIT_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21) +#define BIT_CTRL_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21) +#define BIT_GET_DR21(x) (((x) >> BIT_SHIFT_DR21) & BIT_MASK_DR21) + + +//2 REG_SPIC_DR22 + +#define BIT_SHIFT_DR22 0 +#define BIT_MASK_DR22 0xffffffffL +#define BIT_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22) +#define BIT_CTRL_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22) +#define BIT_GET_DR22(x) (((x) >> BIT_SHIFT_DR22) & BIT_MASK_DR22) + + +//2 REG_SPIC_DR23 + +#define BIT_SHIFT_DR23 0 +#define BIT_MASK_DR23 0xffffffffL +#define BIT_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23) +#define BIT_CTRL_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23) +#define BIT_GET_DR23(x) (((x) >> BIT_SHIFT_DR23) & BIT_MASK_DR23) + + +//2 REG_SPIC_DR24 + +#define BIT_SHIFT_DR24 0 +#define BIT_MASK_DR24 0xffffffffL +#define BIT_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24) +#define BIT_CTRL_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24) +#define BIT_GET_DR24(x) (((x) >> BIT_SHIFT_DR24) & BIT_MASK_DR24) + + +//2 REG_SPIC_DR25 + +#define BIT_SHIFT_DR25 0 +#define BIT_MASK_DR25 0xffffffffL +#define BIT_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25) +#define BIT_CTRL_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25) +#define BIT_GET_DR25(x) (((x) >> BIT_SHIFT_DR25) & BIT_MASK_DR25) + + +//2 REG_SPIC_DR26 + +#define BIT_SHIFT_DR26 0 +#define BIT_MASK_DR26 0xffffffffL +#define BIT_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26) +#define BIT_CTRL_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26) +#define BIT_GET_DR26(x) (((x) >> BIT_SHIFT_DR26) & BIT_MASK_DR26) + + +//2 REG_SPIC_DR27 + +#define BIT_SHIFT_DR27 0 +#define BIT_MASK_DR27 0xffffffffL +#define BIT_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27) +#define BIT_CTRL_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27) +#define BIT_GET_DR27(x) (((x) >> BIT_SHIFT_DR27) & BIT_MASK_DR27) + + +//2 REG_SPIC_DR28 + +#define BIT_SHIFT_DR28 0 +#define BIT_MASK_DR28 0xffffffffL +#define BIT_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28) +#define BIT_CTRL_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28) +#define BIT_GET_DR28(x) (((x) >> BIT_SHIFT_DR28) & BIT_MASK_DR28) + + +//2 REG_SPIC_DR29 + +#define BIT_SHIFT_DR29 0 +#define BIT_MASK_DR29 0xffffffffL +#define BIT_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29) +#define BIT_CTRL_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29) +#define BIT_GET_DR29(x) (((x) >> BIT_SHIFT_DR29) & BIT_MASK_DR29) + + +//2 REG_SPIC_DR30 + +#define BIT_SHIFT_DR30 0 +#define BIT_MASK_DR30 0xffffffffL +#define BIT_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30) +#define BIT_CTRL_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30) +#define BIT_GET_DR30(x) (((x) >> BIT_SHIFT_DR30) & BIT_MASK_DR30) + + +//2 REG_SPIC_DR31 + +#define BIT_SHIFT_DR31 0 +#define BIT_MASK_DR31 0xffffffffL +#define BIT_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31) +#define BIT_CTRL_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31) +#define BIT_GET_DR31(x) (((x) >> BIT_SHIFT_DR31) & BIT_MASK_DR31) + + +//2 REG_SPIC_READ_FAST_SINGLE + +#define BIT_SHIFT_FRD_CMD 0 +#define BIT_MASK_FRD_CMD 0xff +#define BIT_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD) +#define BIT_CTRL_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD) +#define BIT_GET_FRD_CMD(x) (((x) >> BIT_SHIFT_FRD_CMD) & BIT_MASK_FRD_CMD) + + +//2 REG_SPIC_READ_DUAL_DATA + +#define BIT_SHIFT_RD_DUAL_O_CMD 0 +#define BIT_MASK_RD_DUAL_O_CMD 0xff +#define BIT_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD) +#define BIT_CTRL_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD) +#define BIT_GET_RD_DUAL_O_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_O_CMD) & BIT_MASK_RD_DUAL_O_CMD) + + +//2 REG_SPIC_READ_DUAL_ADDR_DATA + +#define BIT_SHIFT_RD_DUAL_IO_CMD 0 +#define BIT_MASK_RD_DUAL_IO_CMD 0xff +#define BIT_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD) +#define BIT_CTRL_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD) +#define BIT_GET_RD_DUAL_IO_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_IO_CMD) & BIT_MASK_RD_DUAL_IO_CMD) + + +//2 REG_SPIC_READ_QUAD_DATA + +#define BIT_SHIFT_RD_QUAD_O_CMD 0 +#define BIT_MASK_RD_QUAD_O_CMD 0xff +#define BIT_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD) +#define BIT_CTRL_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD) +#define BIT_GET_RD_QUAD_O_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_O_CMD) & BIT_MASK_RD_QUAD_O_CMD) + + +//2 REG_SPIC_READ_QUAD_ADDR_DATA + +#define BIT_SHIFT_RD_QUAD_IO_CMD 0 +#define BIT_MASK_RD_QUAD_IO_CMD 0xff +#define BIT_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD) +#define BIT_CTRL_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD) +#define BIT_GET_RD_QUAD_IO_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_IO_CMD) & BIT_MASK_RD_QUAD_IO_CMD) + + +//2 REG_SPIC_WRITE_SIGNLE + +#define BIT_SHIFT_WR_CMD 0 +#define BIT_MASK_WR_CMD 0xff +#define BIT_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD) +#define BIT_CTRL_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD) +#define BIT_GET_WR_CMD(x) (((x) >> BIT_SHIFT_WR_CMD) & BIT_MASK_WR_CMD) + + +//2 REG_SPIC_WRITE_DUAL_DATA + +#define BIT_SHIFT_WR_DUAL_I_CMD 0 +#define BIT_MASK_WR_DUAL_I_CMD 0xff +#define BIT_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD) +#define BIT_CTRL_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD) +#define BIT_GET_WR_DUAL_I_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_I_CMD) & BIT_MASK_WR_DUAL_I_CMD) + + +//2 REG_SPIC_WRITE_DUAL_ADDR_DATA + +#define BIT_SHIFT_WR_DUAL_II_CMD 0 +#define BIT_MASK_WR_DUAL_II_CMD 0xff +#define BIT_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD) +#define BIT_CTRL_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD) +#define BIT_GET_WR_DUAL_II_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_II_CMD) & BIT_MASK_WR_DUAL_II_CMD) + + +//2 REG_SPIC_WRITE_QUAD_DATA + +#define BIT_SHIFT_WR_QUAD_I_CMD 0 +#define BIT_MASK_WR_QUAD_I_CMD 0xff +#define BIT_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD) +#define BIT_CTRL_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD) +#define BIT_GET_WR_QUAD_I_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_I_CMD) & BIT_MASK_WR_QUAD_I_CMD) + + +//2 REG_SPIC_WRITE_QUAD_ADDR_DATA + +#define BIT_SHIFT_WR_QUAD_II_CMD 0 +#define BIT_MASK_WR_QUAD_II_CMD 0xff +#define BIT_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD) +#define BIT_CTRL_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD) +#define BIT_GET_WR_QUAD_II_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_II_CMD) & BIT_MASK_WR_QUAD_II_CMD) + + +//2 REG_SPIC_WRITE_ENABLE + +#define BIT_SHIFT_WR_EN_CMD 0 +#define BIT_MASK_WR_EN_CMD 0xff +#define BIT_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD) +#define BIT_CTRL_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD) +#define BIT_GET_WR_EN_CMD(x) (((x) >> BIT_SHIFT_WR_EN_CMD) & BIT_MASK_WR_EN_CMD) + + +//2 REG_SPIC_READ_STATUS + +#define BIT_SHIFT_RD_ST_CMD 0 +#define BIT_MASK_RD_ST_CMD 0xff +#define BIT_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD) +#define BIT_CTRL_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD) +#define BIT_GET_RD_ST_CMD(x) (((x) >> BIT_SHIFT_RD_ST_CMD) & BIT_MASK_RD_ST_CMD) + + +//2 REG_SPIC_CTRLR2 + +#define BIT_SHIFT_FIFO_ENTRY 4 +#define BIT_MASK_FIFO_ENTRY 0xf +#define BIT_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY) +#define BIT_CTRL_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY) +#define BIT_GET_FIFO_ENTRY(x) (((x) >> BIT_SHIFT_FIFO_ENTRY) & BIT_MASK_FIFO_ENTRY) + +#define BIT_WR_SEQ BIT(3) +#define BIT_SHIFT_WR_SEQ 3 +#define BIT_MASK_WR_SEQ 0x1 +#define BIT_CTRL_WR_SEQ(x) (((x) & BIT_MASK_WR_SEQ) << BIT_SHIFT_WR_SEQ) + +#define BIT_WPN_DNUM BIT(2) +#define BIT_SHIFT_WPN_DNUM 2 +#define BIT_MASK_WPN_DNUM 0x1 +#define BIT_CTRL_WPN_DNUM(x) (((x) & BIT_MASK_WPN_DNUM) << BIT_SHIFT_WPN_DNUM) + +#define BIT_WPN_SET BIT(1) +#define BIT_SHIFT_WPN_SET 1 +#define BIT_MASK_WPN_SET 0x1 +#define BIT_CTRL_WPN_SET(x) (((x) & BIT_MASK_WPN_SET) << BIT_SHIFT_WPN_SET) + +#define BIT_SO_DUM BIT(0) +#define BIT_SHIFT_SO_DUM 0 +#define BIT_MASK_SO_DUM 0x1 +#define BIT_CTRL_SO_DUM(x) (((x) & BIT_MASK_SO_DUM) << BIT_SHIFT_SO_DUM) + +//2 REG_SPIC_FBAUDR + +#define BIT_SHIFT_FSCKDV 0 +#define BIT_MASK_FSCKDV 0xfff +#define BIT_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV) +#define BIT_CTRL_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV) +#define BIT_GET_FSCKDV(x) (((x) >> BIT_SHIFT_FSCKDV) & BIT_MASK_FSCKDV) + + +//2 REG_SPIC_ADDR_LENGTH + +#define BIT_SHIFT_ADDR_PHASE_LENGTH 0 +#define BIT_MASK_ADDR_PHASE_LENGTH 0x3 +#define BIT_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH) +#define BIT_CTRL_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH) +#define BIT_GET_ADDR_PHASE_LENGTH(x) (((x) >> BIT_SHIFT_ADDR_PHASE_LENGTH) & BIT_MASK_ADDR_PHASE_LENGTH) + + +//2 REG_SPIC_AUTO_LENGTH + +#define BIT_SHIFT_CS_H_WR_DUM_LEN 28 +#define BIT_MASK_CS_H_WR_DUM_LEN 0xf +#define BIT_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN) +#define BIT_CTRL_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN) +#define BIT_GET_CS_H_WR_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_WR_DUM_LEN) & BIT_MASK_CS_H_WR_DUM_LEN) + + +#define BIT_SHIFT_CS_H_RD_DUM_LEN 26 +#define BIT_MASK_CS_H_RD_DUM_LEN 0x3 +#define BIT_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN) +#define BIT_CTRL_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN) +#define BIT_GET_CS_H_RD_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_RD_DUM_LEN) & BIT_MASK_CS_H_RD_DUM_LEN) + + +#define BIT_SHIFT_AUTO_DUM_LEN 18 +#define BIT_MASK_AUTO_DUM_LEN 0xff +#define BIT_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN) +#define BIT_CTRL_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN) +#define BIT_GET_AUTO_DUM_LEN(x) (((x) >> BIT_SHIFT_AUTO_DUM_LEN) & BIT_MASK_AUTO_DUM_LEN) + + +#define BIT_SHIFT_AUTO_ADDR__LENGTH 16 +#define BIT_MASK_AUTO_ADDR__LENGTH 0x3 +#define BIT_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH) +#define BIT_CTRL_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH) +#define BIT_GET_AUTO_ADDR__LENGTH(x) (((x) >> BIT_SHIFT_AUTO_ADDR__LENGTH) & BIT_MASK_AUTO_ADDR__LENGTH) + + +#define BIT_SHIFT_RD_DUMMY_LENGTH 0 +#define BIT_MASK_RD_DUMMY_LENGTH 0xffff +#define BIT_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH) +#define BIT_CTRL_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH) +#define BIT_GET_RD_DUMMY_LENGTH(x) (((x) >> BIT_SHIFT_RD_DUMMY_LENGTH) & BIT_MASK_RD_DUMMY_LENGTH) + + +//2 REG_SPIC_VALID_CMD +#define BIT_WR_BLOCKING BIT(9) +#define BIT_SHIFT_WR_BLOCKING 9 +#define BIT_MASK_WR_BLOCKING 0x1 +#define BIT_CTRL_WR_BLOCKING(x) (((x) & BIT_MASK_WR_BLOCKING) << BIT_SHIFT_WR_BLOCKING) + +#define BIT_WR_QUAD_II BIT(8) +#define BIT_SHIFT_WR_QUAD_II 8 +#define BIT_MASK_WR_QUAD_II 0x1 +#define BIT_CTRL_WR_QUAD_II(x) (((x) & BIT_MASK_WR_QUAD_II) << BIT_SHIFT_WR_QUAD_II) + +#define BIT_WR_QUAD_I BIT(7) +#define BIT_SHIFT_WR_QUAD_I 7 +#define BIT_MASK_WR_QUAD_I 0x1 +#define BIT_CTRL_WR_QUAD_I(x) (((x) & BIT_MASK_WR_QUAD_I) << BIT_SHIFT_WR_QUAD_I) + +#define BIT_WR_DUAL_II BIT(6) +#define BIT_SHIFT_WR_DUAL_II 6 +#define BIT_MASK_WR_DUAL_II 0x1 +#define BIT_CTRL_WR_DUAL_II(x) (((x) & BIT_MASK_WR_DUAL_II) << BIT_SHIFT_WR_DUAL_II) + +#define BIT_WR_DUAL_I BIT(5) +#define BIT_SHIFT_WR_DUAL_I 5 +#define BIT_MASK_WR_DUAL_I 0x1 +#define BIT_CTRL_WR_DUAL_I(x) (((x) & BIT_MASK_WR_DUAL_I) << BIT_SHIFT_WR_DUAL_I) + +#define BIT_RD_QUAD_IO BIT(4) +#define BIT_SHIFT_RD_QUAD_IO 4 +#define BIT_MASK_RD_QUAD_IO 0x1 +#define BIT_CTRL_RD_QUAD_IO(x) (((x) & BIT_MASK_RD_QUAD_IO) << BIT_SHIFT_RD_QUAD_IO) + +#define BIT_RD_QUAD_O BIT(3) +#define BIT_SHIFT_RD_QUAD_O 3 +#define BIT_MASK_RD_QUAD_O 0x1 +#define BIT_CTRL_RD_QUAD_O(x) (((x) & BIT_MASK_RD_QUAD_O) << BIT_SHIFT_RD_QUAD_O) + +#define BIT_RD_DUAL_IO BIT(2) +#define BIT_SHIFT_RD_DUAL_IO 2 +#define BIT_MASK_RD_DUAL_IO 0x1 +#define BIT_CTRL_RD_DUAL_IO(x) (((x) & BIT_MASK_RD_DUAL_IO) << BIT_SHIFT_RD_DUAL_IO) + +#define BIT_RD_DUAL_I BIT(1) +#define BIT_SHIFT_RD_DUAL_I 1 +#define BIT_MASK_RD_DUAL_I 0x1 +#define BIT_CTRL_RD_DUAL_I(x) (((x) & BIT_MASK_RD_DUAL_I) << BIT_SHIFT_RD_DUAL_I) + +#define BIT_FRD_SINGEL BIT(0) +#define BIT_SHIFT_FRD_SINGEL 0 +#define BIT_MASK_FRD_SINGEL 0x1 +#define BIT_CTRL_FRD_SINGEL(x) (((x) & BIT_MASK_FRD_SINGEL) << BIT_SHIFT_FRD_SINGEL) + +//2 REG_SPIC_FLASE_SIZE + +#define BIT_SHIFT_FLASE_SIZE 0 +#define BIT_MASK_FLASE_SIZE 0xf +#define BIT_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE) +#define BIT_CTRL_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE) +#define BIT_GET_FLASE_SIZE(x) (((x) >> BIT_SHIFT_FLASE_SIZE) & BIT_MASK_FLASE_SIZE) + + +//2 REG_SPIC_FLUSH_FIFO +#define BIT_FLUSH_FIFO BIT(0) +#define BIT_SHIFT_FLUSH_FIFO 0 +#define BIT_MASK_FLUSH_FIFO 0x1 +#define BIT_CTRL_FLUSH_FIFO(x) (((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO) + +//=================== Register Address Definition ============================// +#define REG_SPIC_CTRLR0 0x0000//O +#define REG_SPIC_CTRLR1 0x0004//O +#define REG_SPIC_SSIENR 0x0008//O +#define REG_SPIC_MWCR 0x000C +#define REG_SPIC_SER 0x0010//O +#define REG_SPIC_BAUDR 0x0014//O +#define REG_SPIC_TXFTLR 0x0018 +#define REG_SPIC_RXFTLR 0x001C//O +#define REG_SPIC_TXFLR 0x0020//O +#define REG_SPIC_RXFLR 0x0024 +#define REG_SPIC_SR 0x0028 +#define REG_SPIC_IMR 0x002C//O +#define REG_SPIC_ISR 0x0030 +#define REG_SPIC_RISR 0x0034 +#define REG_SPIC_TXOICR 0x0038 +#define REG_SPIC_RXOICR 0x003C +#define REG_SPC_RXUICR 0x0040 +#define REG_SPIC_MSTICR 0x0044 +#define REG_SPIC_ICR 0x0048 +#define REG_SPIC_DMACR 0x004C +#define REG_SPIC_DMATDLR0 0x0050 +#define REG_SPIC_DMATDLR1 0x0054 +#define REG_SPIC_IDR 0x0058 +#define REG_SPIC_VERSION 0x005C +#define REG_SPIC_DR0 0x0060 +#define REG_SPIC_DR1 0x0064 +#define REG_SPIC_DR2 0x0068 +#define REG_SPIC_DR3 0x006C +#define REG_SPIC_DR4 0x0070 +#define REG_SPIC_DR5 0x0074 +#define REG_SPIC_DR6 0x0078 +#define REG_SPIC_DR7 0x007C +#define REG_SPIC_DR8 0x0080 +#define REG_SPIC_DR9 0x0084 +#define REG_SPIC_DR10 0x0088 +#define REG_SPIC_DR11 0x008C +#define REG_SPIC_DR12 0x0090 +#define REG_SPIC_DR13 0x0094 +#define REG_SPIC_DR14 0x0098 +#define REG_SPIC_DR15 0x009C +#define REG_SPIC_DR16 0x00A0 +#define REG_SPIC_DR17 0x00A4 +#define REG_SPIC_DR18 0x00A8 +#define REG_SPIC_DR19 0x00AC +#define REG_SPIC_DR20 0x00B0 +#define REG_SPIC_DR21 0x00B4 +#define REG_SPIC_DR22 0x00B8 +#define REG_SPIC_DR23 0x00BC +#define REG_SPIC_DR24 0x00C0 +#define REG_SPIC_DR25 0x00C4 +#define REG_SPIC_DR26 0x00C8 +#define REG_SPIC_DR27 0x00CC +#define REG_SPIC_DR28 0x00D0 +#define REG_SPIC_DR29 0x00D4 +#define REG_SPIC_DR30 0x00D8 +#define REG_SPIC_DR31 0x00DC +#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O +#define REG_SPIC_READ_DUAL_DATA 0x00E4//O +#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O +#define REG_SPIC_READ_QUAD_DATA 0x00EC//O +#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O +#define REG_SPIC_WRITE_SIGNLE 0x00F4//O +#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O +#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O +#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O +#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O +#define REG_SPIC_WRITE_ENABLE 0x0108//O +#define REG_SPIC_READ_STATUS 0x010C//O +#define REG_SPIC_CTRLR2 0x0110//O +#define REG_SPIC_FBAUDR 0x0114//O +#define REG_SPIC_ADDR_LENGTH 0x0118//O +#define REG_SPIC_AUTO_LENGTH 0x011C//O +#define REG_SPIC_VALID_CMD 0x0120//O +#define REG_SPIC_FLASE_SIZE 0x0124//O +#define REG_SPIC_FLUSH_FIFO 0x0128//O + +VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); // spi-flash controller initialization +VOID SpicRxCmdRtl8195A(u8); // recieve command +VOID SpicTxCmdRtl8195A(u8 cmd, SPIC_INIT_PARA SpicInitPara); // transfer command +u8 SpicGetFlashStatusRtl8195A(SPIC_INIT_PARA SpicInitPara); // RDSR, read spi-flash status register +VOID SpicSetFlashStatusRtl8195A(u32 data, SPIC_INIT_PARA SpicInitPara); // WRSR, write spi-flash status register +VOID SpicWaitBusyDoneRtl8195A(VOID); // wait sr[0] = 0, wait transmission done +VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0 +VOID SpicEraseFlashRtl8195A(VOID); // CE, flash chip erase +u32 SpicCmpDataForCalibrationRtl8195A(VOID); // compare read_data and golden_data +VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); + +#if 1//CONFIG_CHIP_E_CUT + +VOID +SpicTxCmdWithDataRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u8 cmd, + IN u8 DataPhaseLen, + IN u8* pData +); + +VOID +SpicTxFlashInstRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u8 cmd, + IN u8 DataPhaseLen, + IN u8* pData +); + +VOID +SpicDeepPowerDownFlashRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara +); + +VOID +SpicBlockEraseFlashRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u32 Address +); + +VOID +SpicSectorEraseFlashRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u32 Address +); + +VOID +SpicWriteProtectFlashRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u32 Protect +); + +BOOLEAN +SpicFlashInitRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u8 SpicBitMode +); + +u32 +SpicCalibrationRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u8 SpicBitMode, + IN u32 DefRdDummyCycle +); + +VOID +SpicConfigAutoModeRtl8195A_V04( + IN u8 SpicBitMode +); + +VOID +SpicWaitWipDoneRefinedRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara +); + +VOID +SpicRxCmdRefinedRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u8 cmd +); + +u8 +SpicGetFlashStatusRefinedRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara +); + +VOID +SpicInitRefinedRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u8 InitBaudRate, + IN u8 SpicBitMode +); + +VOID +SpicEraseFlashRefinedRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara +); + +VOID +SpicSetFlashStatusRefinedRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u32 data +); + +u32 +SpicWaitWipRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara +); + +u32 +SpicOneBitCalibrationRtl8195A_V04( + IN SPIC_INIT_PARA *pSpicInitPara, + IN u8 SysCpuClk +); + +VOID +SpicLoadInitParaFromClockRtl8195A_V04( + IN u8 CpuClkMode, + IN u8 BaudRate, + IN PSPIC_INIT_PARA pSpicInitPara +) ; + +u8 +SpicGetFlashFlagRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); + +VOID +SpicWaitOperationDoneRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); + +VOID +SpicUserProgramRtl8195A_V04(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo); + +VOID +SpicUserReadRtl8195A_V04(IN u32 Length, IN u32 addr, IN u8 * data); + +VOID +SpicUserReadFourByteRtl8195A_V04(IN u32 Length, IN u32 addr, IN u32 * data, IN u8 BitMode); + +VOID +SpicSetExtendAddrRtl8195A_V04(IN u32 data, IN SPIC_INIT_PARA * pSpicInitPara); + +u8 +SpicGetExtendAddrRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); + +VOID +SpicReadIDRtl8195A_V04(VOID); + +VOID +SpicDieEraseFlashRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara, IN u32 Address); + +u8 +SpicGetConfigRegRtl8195A_V04(IN SPIC_INIT_PARA * pSpicInitPara); +#endif // #if CONFIG_CHIP_E_CUT + +#endif // end of "#ifndef _RTL8195A_SPI_FLASH_H" diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h new file mode 100644 index 00000000000..2e4bcc3feaf --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h @@ -0,0 +1,530 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_SSI_H_ +#define _RTL8195A_SSI_H_ + +#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read + +#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2) +#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4) + +/* Parameters of DW_apb_ssi for RTL8195A */ +#define SSI_TX_FIFO_DEPTH 64 +#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH) +#define SSI_RX_FIFO_DEPTH 64 +#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH) + +#define SSI0_REG_BASE 0x40042000 +#define SSI1_REG_BASE 0x40042400 +#define SSI2_REG_BASE 0x40042800 + +/* Memory Map of DW_apb_ssi */ +#define REG_DW_SSI_CTRLR0 0x00 // 16 bits +#define REG_DW_SSI_CTRLR1 0x04 // 16 bits +#define REG_DW_SSI_SSIENR 0x08 // 1 bit +#define REG_DW_SSI_MWCR 0x0C // 3 bits +#define REG_DW_SSI_SER 0x10 // +#define REG_DW_SSI_BAUDR 0x14 // 16 bits +#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW +#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW +#define REG_DW_SSI_TXFLR 0x20 // +#define REG_DW_SSI_RXFLR 0x24 // +#define REG_DW_SSI_SR 0x28 // 7 bits +#define REG_DW_SSI_IMR 0x2C // +#define REG_DW_SSI_ISR 0x30 // 6 bits +#define REG_DW_SSI_RISR 0x34 // 6 bits +#define REG_DW_SSI_TXOICR 0x38 // 1 bits +#define REG_DW_SSI_RXOICR 0x3C // 1 bits +#define REG_DW_SSI_RXUICR 0x40 // 1 bits +#define REG_DW_SSI_MSTICR 0x44 // 1 bits +#define REG_DW_SSI_ICR 0x48 // 1 bits +#define REG_DW_SSI_DMACR 0x4C // 2 bits +#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW +#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW +#define REG_DW_SSI_IDR 0x58 // 32 bits +#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits +#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC +#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits +#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits +#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits +#define REG_DW_SSI_RSVD_2 0xFC // 32 bits + +// CTRLR0 0x00 // 16 bits, 6.2.1 +// DFS Reset Value: 0x7 +#define BIT_SHIFT_CTRLR0_DFS 0 +#define BIT_MASK_CTRLR0_DFS 0xF +#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS) +#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS)) + +#define BIT_SHIFT_CTRLR0_FRF 4 +#define BIT_MASK_CTRLR0_FRF 0x3 +#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF) +#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF)) + +#define BIT_SHIFT_CTRLR0_SCPH 6 +#define BIT_MASK_CTRLR0_SCPH 0x1 +#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH) +#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH)) + +#define BIT_SHIFT_CTRLR0_SCPOL 7 +#define BIT_MASK_CTRLR0_SCPOL 0x1 +#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL) +#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL)) + +#define BIT_SHIFT_CTRLR0_TMOD 8 +#define BIT_MASK_CTRLR0_TMOD 0x3 +#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD) +#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD)) + +#define BIT_SHIFT_CTRLR0_SLV_OE 10 +#define BIT_MASK_CTRLR0_SLV_OE 0x1 +#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE) +#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE)) + +#define BIT_SHIFT_CTRLR0_SRL 11 +#define BIT_MASK_CTRLR0_SRL 0x1 +#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL) +#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL)) + +#define BIT_SHIFT_CTRLR0_CFS 12 +#define BIT_MASK_CTRLR0_CFS 0xF +#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS) +#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS)) + +// CTRLR1 0x04 // 16 bits +#define BIT_SHIFT_CTRLR1_NDF 0 +#define BIT_MASK_CTRLR1_NDF 0xFFFF +#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF) +#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF)) + +// SSIENR 0x08 // 1 bit +#define BIT_SHIFT_SSIENR_SSI_EN 0 +#define BIT_MASK_SSIENR_SSI_EN 0x1 +#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN) +#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN)) + +// MWCR 0x0c // 3 bits +#define BIT_SHIFT_MWCR_MWMOD 0 +#define BIT_MASK_MWCR_MWMOD 0x1 +#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD) +#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD)) + +#define BIT_SHIFT_MWCR_MDD 1 +#define BIT_MASK_MWCR_MDD 0x1 +#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD) +#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD)) + +#define BIT_SHIFT_MWCR_MHS 2 +#define BIT_MASK_MWCR_MHS 0x1 +#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS) +#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS)) + +// SER 0x10 // Variable Length +#define BIT_SHIFT_SER_SER 0 +#define BIT_MASK_SER_SER 0xFF +#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER) +#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER)) + +// BAUDR 0x14 // 16 bits +#define BIT_SHIFT_BAUDR_SCKDV 0 +#define BIT_MASK_BAUDR_SCKDV 0xFFFF +#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV) +#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV)) + +// TXFLTR 0x18 // Variable Length +#define BIT_SHIFT_TXFTLR_TFT 0 +#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0 +#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT) +#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT)) + +// RXFLTR 0x1c // Variable Length +#define BIT_SHIFT_RXFTLR_RFT 0 +#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0 +#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT) +#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT)) + +// TXFLR 0x20 // see [READ ONLY] +#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0 + +// RXFLR 0x24 // see [READ ONLY] +#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0 + +// SR 0x28 // 7 bits [READ ONLY] +#define BIT_SR_BUSY BIT0 +#define BIT_SR_TFNF BIT1 +#define BIT_SR_TFE BIT2 +#define BIT_SR_RFNE BIT3 +#define BIT_SR_RFF BIT4 +#define BIT_SR_TXE BIT5 +#define BIT_SR_DCOL BIT6 + +// IMR 0x2c // see +#define BIT_SHIFT_IMR_TXEIM 0 +#define BIT_MASK_IMR_TXEIM 0x1 +// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM) +#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM)) + +#define BIT_SHIFT_IMR_TXOIM 1 +#define BIT_MASK_IMR_TXOIM 0x1 +// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM) +#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM)) + +#define BIT_SHIFT_IMR_RXUIM 2 +#define BIT_MASK_IMR_RXUIM 0x1 +// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM) +#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM)) + +#define BIT_SHIFT_IMR_RXOIM 3 +#define BIT_MASK_IMR_RXOIM 0x1 +// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM) +#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM)) + +#define BIT_SHIFT_IMR_RXFIM 4 +#define BIT_MASK_IMR_RXFIM 0x1 +// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM) +#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM)) + +#define BIT_SHIFT_IMR_MSTIM 5 +#define BIT_MASK_IMR_MSTIM 0x1 +// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM) +#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM)) + +#define BIT_IMR_TXEIM BIT0 +#define BIT_IMR_TXOIM BIT1 +#define BIT_IMR_RXUIM BIT2 +#define BIT_IMR_RXOIM BIT3 +#define BIT_IMR_RXFIM BIT4 +#define BIT_IMR_MSTIM BIT5 + +// ISR 0x30 // 6 bits [READ ONLY] +#define BIT_ISR_TXEIS BIT0 +#define BIT_ISR_TXOIS BIT1 +#define BIT_ISR_RXUIS BIT2 +#define BIT_ISR_RXOIS BIT3 +#define BIT_ISR_RXFIS BIT4 +#define BIT_ISR_MSTIS BIT5 + +// RISR 0x34 // 6 bits [READ ONLY] +#define BIT_RISR_TXEIR BIT0 +#define BIT_RISR_TXOIR BIT1 +#define BIT_RISR_RXUIR BIT2 +#define BIT_RISR_RXOIR BIT3 +#define BIT_RISR_RXFIR BIT4 +#define BIT_RISR_MSTIR BIT5 + +// TXOICR 0x38 // 1 bits [READ ONLY] +// RXOICR 0x3c // 1 bits [READ ONLY] +// RXUICR 0x40 // 1 bits [READ ONLY] +// MSTICR 0x44 // 1 bits [READ ONLY] +// ICR 0x48 // 1 bits [READ ONLY] + +// DMACR 0x4c // 2 bits +#define BIT_SHIFT_DMACR_RDMAE 0 +#define BIT_MASK_DMACR_RDMAE 0x1 +#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE) +#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE)) + +#define BIT_SHIFT_DMACR_TDMAE 1 +#define BIT_MASK_DMACR_TDMAE 0x1 +#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE) +#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE)) + +// DMATDLR 0x50 +#define BIT_SHIFT_DMATDLR_DMATDL 0 +#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0 +#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL) +#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL)) + +// DMARDLR 0x54 +#define BIT_SHIFT_DMARDLR_DMARDL 0 +#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0 +#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL) +#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL)) + +// IDR 0x58 // 32 bits [READ ONLY] +// COMP_VERSION 0x5c // 32 bits [READ ONLY] + +// DR 0x60 // 16 bits 0x60-0xEC +#define BIT_SHIFT_DR_DR 0 +#define BIT_MASK_DR_DR 0xFFFF +#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR) +#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR)) + +// RX_SAMPLE_DLY 0xF0 // 8 bits +#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0 +#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF +#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD) +#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD)) + +// RSVD_0 0xF4 // 32 bits +// RSVD_1 0xF8 // 32 bits +// RSVD_2 0xFC // 32 bits + +// SSI0 Pinmux +#define BIT_SHIFT_SSI0_PIN_EN 0 +#define BIT_MASK_SSI0_PIN_EN 0x1 +#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN) +#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN)) + +#define BIT_SHIFT_SSI0_PIN_SEL 1 +#define BIT_MASK_SSI0_PIN_SEL 0x7 +#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL) +#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL)) + +// SSI1 Pinmux +#define BIT_SHIFT_SSI1_PIN_EN 4 +#define BIT_MASK_SSI1_PIN_EN 0x1 +#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN) +#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN)) + +#define BIT_SHIFT_SSI1_PIN_SEL 5 +#define BIT_MASK_SSI1_PIN_SEL 0x7 +#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL) +#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL)) + +// SSI2 Pinmux +#define BIT_SHIFT_SSI2_PIN_EN 8 +#define BIT_MASK_SSI2_PIN_EN 0x1 +#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN) +#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN)) + +#define BIT_SHIFT_SSI2_PIN_SEL 9 +#define BIT_MASK_SSI2_PIN_SEL 0x7 +#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL) +#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL)) + +// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL) +#define BIT_SHIFT_SSI0_MULTI_CS_EN 28 +#define BIT_MASK_SSI0_MULTI_CS_EN 0x1 +#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN) +#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN)) + + +#define HAL_SSI_READ32(SsiIndex, addr) \ + HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) +#define HAL_SSI_WRITE32(SsiIndex, addr, value) \ + HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) +#define HAL_SSI_READ16(SsiIndex, addr) \ + HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) +#define HAL_SSI_WRITE16(SsiIndex, addr, value) \ + HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) +#define HAL_SSI_READ8(SsiIndex, addr) \ + HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) +#define HAL_SSI_WRITE8(SsiIndex, addr, value) \ + HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) + + +// SSI Pinmux Select +typedef enum _SSI0_PINMUX_SELECT_ { + SSI0_MUX_TO_GPIOE = S0, + SSI0_MUX_TO_GPIOC = S1 +}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT; + +typedef enum _SSI1_PINMUX_SELECT_ { + SSI1_MUX_TO_GPIOA = S0, + SSI1_MUX_TO_GPIOB = S1, + SSI1_MUX_TO_GPIOD = S2 +}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT; + +typedef enum _SSI2_PINMUX_SELECT_ { + SSI2_MUX_TO_GPIOG = S0, + SSI2_MUX_TO_GPIOE = S1, + SSI2_MUX_TO_GPIOD = S2 +}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT; + +typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ { + SSI0_CS_MUX_TO_GPIOE = S0, + SSI0_CS_MUX_TO_GPIOC = S1 +}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT; + +typedef enum _SSI_CTRLR0_TMOD_ { + TMOD_TR = 0, + TMOD_TO = 1, + TMOD_RO = 2, + TMOD_EEPROM_R = 3 +}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD; + +typedef enum _SSI_CTRLR0_SCPOL_ { + SCPOL_INACTIVE_IS_LOW = 0, + SCPOL_INACTIVE_IS_HIGH = 1 +}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL; + +typedef enum _SSI_CTRLR0_SCPH_ { + SCPH_TOGGLES_IN_MIDDLE = 0, + SCPH_TOGGLES_AT_START = 1 +}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH; + +typedef enum _SSI_CTRLR0_DFS_ { + DFS_4_BITS = 3, + DFS_5_BITS = 4, + DFS_6_BITS = 5, + DFS_7_BITS = 6, + DFS_8_BITS = 7, + DFS_9_BITS = 8, + DFS_10_BITS = 9, + DFS_11_BITS = 10, + DFS_12_BITS = 11, + DFS_13_BITS = 12, + DFS_14_BITS = 13, + DFS_15_BITS = 14, + DFS_16_BITS = 15, +}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS; + +typedef enum _SSI_CTRLR0_CFS_ { + CFS_1_BIT = 0, + CFS_2_BITS = 1, + CFS_3_BITS = 2, + CFS_4_BITS = 3, + CFS_5_BITS = 4, + CFS_6_BITS = 5, + CFS_7_BITS = 6, + CFS_8_BITS = 7, + CFS_9_BITS = 8, + CFS_10_BITS = 9, + CFS_11_BITS = 10, + CFS_12_BITS = 11, + CFS_13_BITS = 12, + CFS_14_BITS = 13, + CFS_15_BITS = 14, + CFS_16_BITS = 15 +}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS; + +typedef enum _SSI_CTRLR0_SLV_OE_ { + SLV_TXD_ENABLE = 0, + SLV_TXD_DISABLE = 1 +}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE; + +typedef enum _SSI_ROLE_SELECT_ { + SSI_SLAVE = 0, + SSI_MASTER = 1 +}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT; + +typedef enum _SSI_FRAME_FORMAT_ { + FRF_MOTOROLA_SPI = 0, + FRF_TI_SSP = 1, + FRF_NS_MICROWIRE = 2, + FRF_RSVD = 3 +}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT; + +typedef enum _SSI_DMACR_ENABLE_ { + SSI_NODMA = 0, + SSI_RXDMA_ENABLE = 1, + SSI_TXDMA_ENABLE = 2, + SSI_TRDMA_ENABLE = 3 +}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE; + +typedef enum _SSI_MWCR_HANDSHAKE_ { + MW_HANDSHAKE_DISABLE = 0, + MW_HANDSHAKE_ENABLE = 1 +}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE; + +typedef enum _SSI_MWCR_DIRECTION_ { + MW_DIRECTION_SLAVE_TO_MASTER = 0, + MW_DIRECTION_MASTER_TO_SLAVE = 1 +}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION; + +typedef enum _SSI_MWCR_TMOD_ { + MW_TMOD_NONSEQUENTIAL = 0, + MW_TMOD_SEQUENTIAL = 1 +}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD; + +typedef enum _SSI_DATA_TRANSFER_MECHANISM_ { + SSI_DTM_BASIC, + SSI_DTM_INTERRUPT, + SSI_DTM_DMA +}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM; + + +_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value); +_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting); +_LONG_CALL_ROM_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role); +_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length); +_LONG_CALL_ROM_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length); +_LONG_CALL_ROM_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex); +_LONG_CALL_ROM_ u32 HalSsiBusyRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ u32 HalSsiReadableRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor); +_LONG_CALL_ROM_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor); + +_LONG_CALL_ROM_ VOID _SsiReadInterrupt(VOID *Adaptor); +_LONG_CALL_ROM_ VOID _SsiWriteInterrupt(VOID *Adaptor); +_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor); + +// ROM code patch +VOID _SsiReadInterruptRtl8195a(VOID *Adapter); +VOID _SsiWriteInterruptRtl8195a(VOID *Adapter); +HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor); +HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor); +HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor); +HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter); +HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter); +HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter); +VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate); +HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length); +HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length); +VOID HalSsiTxFIFOThresholdRtl8195a(VOID *Adaptor, u32 txftl); +HAL_Status HalSsiEnterCriticalRtl8195a(VOID * Data); +HAL_Status HalSsiExitCriticalRtl8195a(VOID * Data); +HAL_Status HalSsiIsTimeoutRtl8195a(u32 StartCount, u32 TimeoutCnt); +HAL_Status HalSsiStopRecvRtl8195a(VOID * Data); + +#if CONFIG_CHIP_E_CUT +HAL_Status HalSsiPinmuxEnableRtl8195a_V04(VOID *Adaptor); +HAL_Status HalSsiPinmuxDisableRtl8195a_V04(VOID * Adaptor); +VOID _SsiReadInterruptRtl8195a_V04(VOID *Adapter); +VOID _SsiWriteInterruptRtl8195a_V04(VOID *Adapter); +HAL_Status HalSsiInitRtl8195a_V04(VOID *Adaptor); +HAL_Status HalSsiSetFormatRtl8195a_V04(VOID * Adaptor); +HAL_Status HalSsiDeInitRtl8195a_V04(VOID *Adapter); +HAL_Status HalSsiIntReadRtl8195a_V04(VOID *Adapter, VOID *RxData, u32 Length); +HAL_Status HalSsiIntWriteRtl8195a_V04(VOID *Adapter, u8 *pTxData, u32 Length); +HAL_Status HalSsiClockOffRtl8195a_V04(VOID * Adapter); +HAL_Status HalSsiClockOnRtl8195a_V04(VOID * Adapter); +VOID HalSsiSetSclkRtl8195a_V04(VOID *Adapter, u32 ClkRate); +VOID HalSsiTxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter); +VOID HalSsiRxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter); +VOID HalSsiDmaInitRtl8195a_V04(VOID *Adapter); +HAL_Status HalSsiDmaSendRtl8195a_V04(IN VOID * Adapter, IN u8 * pTxData, IN u32 Length); +HAL_Status HalSsiDmaRecvRtl8195a_V04(IN VOID * Adapter, IN u8 * pRxData, IN u32 Length); +HAL_Status HalSsiDmaSendMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pTxData, u32 Length); +HAL_Status HalSsiDmaRecvMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pRxData, u32 Length); + +#endif + +#ifdef CONFIG_GDMA_EN +VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter); +VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter); +VOID HalSsiDmaInitRtl8195a(VOID *Adapter); +HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length); +HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length); +HAL_Status HalSsiDmaSendMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length); +HAL_Status HalSsiDmaRecvMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length); + +#endif // end of "#ifdef CONFIG_GDMA_EN" + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sys_on.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sys_on.h new file mode 100644 index 00000000000..2c5ef62b422 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sys_on.h @@ -0,0 +1,1093 @@ +#ifndef __INC_RTL8195A_SYS_ON_BIT_H +#define __INC_RTL8195A_SYS_ON_BIT_H + +#define CPU_OPT_WIDTH 0x1F + +//2 REG_NOT_VALID + +//2 REG_SYS_PWR_CTRL + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_PWR_SOC_EN BIT(2) +#define BIT_SYS_PWR_RET_MEM_EN BIT(1) +#define BIT_SYS_PWR_PEON_EN BIT(0) + +//2 REG_SYS_ISO_CTRL + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_ISO_SYSPLL BIT(7) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_ISO_SOC BIT(2) +#define BIT_SYS_ISO_RET_MEM BIT(1) +#define BIT_SYS_ISO_PEON BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_FUNC_EN +#define BIT_SYS_AMACRO_EN BIT(31) +#define BIT_SYS_PWRON_TRAP_SHTDN_N BIT(30) +#define BIT_SYS_FEN_SIC_MST BIT(25) +#define BIT_SYS_FEN_SIC BIT(24) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SOC_SYSPEON_EN BIT(4) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_FEN_EELDR BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_CLK_CTRL0 + +//2 REG_NOT_VALID +#define BIT_SOC_OCP_IOBUS_CK_EN BIT(2) +#define BIT_SYSON_CK_EELDR_EN BIT(1) +#define BIT_SYSON_CK_SYSREG_EN BIT(0) + +//2 REG_SYS_CLK_CTRL1 + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +#define BIT_SHIFT_PESOC_OCP_CPU_CK_SEL 4 +#define BIT_MASK_PESOC_OCP_CPU_CK_SEL 0x7 +#define BIT_PESOC_OCP_CPU_CK_SEL(x) (((x) & BIT_MASK_PESOC_OCP_CPU_CK_SEL) << BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) + + +//2 REG_NOT_VALID +#define BIT_PESOC_EELDR_CK_SEL BIT(0) + +//2 REG_SYS_SWR_CTRL3 + +//2 REG_RSV_CTRL + +//2 REG_RF_CTRL + +//2 REG_SYS_EFUSE_SYSCFG0 + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00 24 +#define BIT_MASK_SYS_EEROM_SWR_PAR_05_00 0x3f +#define BIT_SYS_EEROM_SWR_PAR_05_00(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_05_00) << BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00) + + +#define BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04 20 +#define BIT_MASK_SYS_EEROM_LDO_PAR_07_04 0xf +#define BIT_SYS_EEROM_LDO_PAR_07_04(x) (((x) & BIT_MASK_SYS_EEROM_LDO_PAR_07_04) << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04) + +#define BIT_SYS_CHIPPDN_EN BIT(17) +#define BIT_SYS_EEROM_B12V_EN BIT(16) + +#define BIT_SHIFT_SYS_EEROM_VID1 8 +#define BIT_MASK_SYS_EEROM_VID1 0xff +#define BIT_SYS_EEROM_VID1(x) (((x) & BIT_MASK_SYS_EEROM_VID1) << BIT_SHIFT_SYS_EEROM_VID1) + + +#define BIT_SHIFT_SYS_EEROM_VID0 0 +#define BIT_MASK_SYS_EEROM_VID0 0xff +#define BIT_SYS_EEROM_VID0(x) (((x) & BIT_MASK_SYS_EEROM_VID0) << BIT_SHIFT_SYS_EEROM_VID0) + + +//2 REG_SYS_EFUSE_SYSCFG1 + +#define BIT_SHIFT_SYS_PDSPL_STL 24 +#define BIT_MASK_SYS_PDSPL_STL 0x3 +#define BIT_SYS_PDSPL_STL(x) (((x) & BIT_MASK_SYS_PDSPL_STL) << BIT_SHIFT_SYS_PDSPL_STL) + + +#define BIT_SHIFT_SYS_PDSOC_STL 22 +#define BIT_MASK_SYS_PDSOC_STL 0x3 +#define BIT_SYS_PDSOC_STL(x) (((x) & BIT_MASK_SYS_PDSOC_STL) << BIT_SHIFT_SYS_PDSOC_STL) + + +#define BIT_SHIFT_SYS_PDPON_STL 20 +#define BIT_MASK_SYS_PDPON_STL 0x3 +#define BIT_SYS_PDPON_STL(x) (((x) & BIT_MASK_SYS_PDPON_STL) << BIT_SHIFT_SYS_PDPON_STL) + + +#define BIT_SHIFT_SYS_SWREG_XRT 18 +#define BIT_MASK_SYS_SWREG_XRT 0x3 +#define BIT_SYS_SWREG_XRT(x) (((x) & BIT_MASK_SYS_SWREG_XRT) << BIT_SHIFT_SYS_SWREG_XRT) + + +#define BIT_SHIFT_SYS_SWSLC_STL 16 +#define BIT_MASK_SYS_SWSLC_STL 0x3 +#define BIT_SYS_SWSLC_STL(x) (((x) & BIT_MASK_SYS_SWSLC_STL) << BIT_SHIFT_SYS_SWSLC_STL) + + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45 14 +#define BIT_MASK_SYS_EEROM_SWR_PAR_46_45 0x3 +#define BIT_SYS_EEROM_SWR_PAR_46_45(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_46_45) << BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45) + + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39 12 +#define BIT_MASK_SYS_EEROM_SWR_PAR_40_39 0x3 +#define BIT_SYS_EEROM_SWR_PAR_40_39(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_40_39) << BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39) + + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26 4 +#define BIT_MASK_SYS_EEROM_SWR_PAR_33_26 0xff +#define BIT_SYS_EEROM_SWR_PAR_33_26(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_33_26) << BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26) + + +#define BIT_SHIFT_SYS_EEROM_SWSLD_VOL 0 +#define BIT_MASK_SYS_EEROM_SWSLD_VOL 0x7 +#define BIT_SYS_EEROM_SWSLD_VOL(x) (((x) & BIT_MASK_SYS_EEROM_SWSLD_VOL) << BIT_SHIFT_SYS_EEROM_SWSLD_VOL) + + +//2 REG_SYS_EFUSE_SYSCFG2 + +#define BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15 21 +#define BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15 0x3ff +#define BIT_SYS_EERROM_ANAPAR_SPLL_24_15(x) (((x) & BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15) << BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15) + + +#define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02 16 +#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02 0xf +#define BIT_SYS_EEROM_ANAPAR_SPLL_05_02(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02) + + +#define BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL 12 +#define BIT_MASK_SYS_EEROM_XTAL_STEL_SEL 0x3 +#define BIT_SYS_EEROM_XTAL_STEL_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_STEL_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL) + + +#define BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL 8 +#define BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL 0xf +#define BIT_SYS_EEROM_XTAL_FREQ_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL) + + +//2 REG_SYS_EFUSE_SYSCFG3 + +#define BIT_SHIFT_SYS_DBG_PINGP_EN 28 +#define BIT_MASK_SYS_DBG_PINGP_EN 0xf +#define BIT_SYS_DBG_PINGP_EN(x) (((x) & BIT_MASK_SYS_DBG_PINGP_EN) << BIT_SHIFT_SYS_DBG_PINGP_EN) + + +#define BIT_SHIFT_SYS_DBG_SEL 16 +#define BIT_MASK_SYS_DBG_SEL 0xfff +#define BIT_SYS_DBG_SEL(x) (((x) & BIT_MASK_SYS_DBG_SEL) << BIT_SHIFT_SYS_DBG_SEL) + + +#define BIT_SHIFT_SYS_DBGBY3_LOC_SEL 14 +#define BIT_MASK_SYS_DBGBY3_LOC_SEL 0x3 +#define BIT_SYS_DBGBY3_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY3_LOC_SEL) << BIT_SHIFT_SYS_DBGBY3_LOC_SEL) + + +#define BIT_SHIFT_SYS_DBGBY2_LOC_SEL 12 +#define BIT_MASK_SYS_DBGBY2_LOC_SEL 0x3 +#define BIT_SYS_DBGBY2_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY2_LOC_SEL) << BIT_SHIFT_SYS_DBGBY2_LOC_SEL) + + +#define BIT_SHIFT_SYS_DBGBY1_LOC_SEL 10 +#define BIT_MASK_SYS_DBGBY1_LOC_SEL 0x3 +#define BIT_SYS_DBGBY1_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY1_LOC_SEL) << BIT_SHIFT_SYS_DBGBY1_LOC_SEL) + + +#define BIT_SHIFT_SYS_DBGBY0_LOC_SEL 8 +#define BIT_MASK_SYS_DBGBY0_LOC_SEL 0x3 +#define BIT_SYS_DBGBY0_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY0_LOC_SEL) << BIT_SHIFT_SYS_DBGBY0_LOC_SEL) + +#define BIT_SYS_EEROM_ANAPAR_SPLL_49 BIT(3) + +#define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25 0 +#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25 0x7 +#define BIT_SYS_EEROM_ANAPAR_SPLL_27_25(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25) + + +//2 REG_SYS_EFUSE_SYSCFG4 + +#define BIT_SHIFT_SYS_GPIOA_E2 1 +#define BIT_MASK_SYS_GPIOA_E2 0x7 +#define BIT_SYS_GPIOA_E2(x) (((x) & BIT_MASK_SYS_GPIOA_E2) << BIT_SHIFT_SYS_GPIOA_E2) + +#define BIT_SYS_GPIOA_H3L1 BIT(0) + +//2 REG_SYS_EFUSE_SYSCFG5 + +//2 REG_NOT_VALID + +//2 REG_SYS_EFUSE_SYSCFG6 + +#define BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL 26 +#define BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL 0x3 +#define BIT_SYS_SPIC_INIT_BAUD_RATE_SEL(x) (((x) & BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL) << BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL) + + +#define BIT_SHIFT_SYS_CPU_CLK_SEL 24 +#define BIT_MASK_SYS_CPU_CLK_SEL 0x3 +#define BIT_SYS_CPU_CLK_SEL(x) (((x) & BIT_MASK_SYS_CPU_CLK_SEL) << BIT_SHIFT_SYS_CPU_CLK_SEL) + + +//2 REG_SYS_EFUSE_SYSCFG7 +#define BIT_SYS_MEM_RMV_SIGN BIT(31) +#define BIT_SYS_MEM_RMV_1PRF1 BIT(29) +#define BIT_SYS_MEM_RMV_1PRF0 BIT(28) +#define BIT_SYS_MEM_RMV_1PSR BIT(27) +#define BIT_SYS_MEM_RMV_1PHSR BIT(26) +#define BIT_SYS_MEM_RMV_ROM BIT(25) + +#define BIT_SHIFT_SYS_MEM_RME_CPU 22 +#define BIT_MASK_SYS_MEM_RME_CPU 0x7 +#define BIT_SYS_MEM_RME_CPU(x) (((x) & BIT_MASK_SYS_MEM_RME_CPU) << BIT_SHIFT_SYS_MEM_RME_CPU) + + +#define BIT_SHIFT_SYS_MEM_RME_WLAN 19 +#define BIT_MASK_SYS_MEM_RME_WLAN 0x7 +#define BIT_SYS_MEM_RME_WLAN(x) (((x) & BIT_MASK_SYS_MEM_RME_WLAN) << BIT_SHIFT_SYS_MEM_RME_WLAN) + +#define BIT_SYS_MEM_RME_USB BIT(18) +#define BIT_SYS_MEM_RME_SDIO BIT(17) + +//2 REG_SYS_REGU_CTRL0 + +#define BIT_SHIFT_SYS_REGU_LDO25M_ADJ 20 +#define BIT_MASK_SYS_REGU_LDO25M_ADJ 0xf +#define BIT_SYS_REGU_LDO25M_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25M_ADJ) << BIT_SHIFT_SYS_REGU_LDO25M_ADJ) + +#define BIT_SYS_REGU_ANACK_4M_EN BIT(19) +#define BIT_SYS_REGU_ANACK_4M_SEL BIT(18) +#define BIT_SYS_REGU_PC_EF_EN BIT(17) +#define BIT_SYS_REGU_LDOH12_SLP_EN BIT(16) + +#define BIT_SHIFT_SYS_REGU_LDOH12_ADJ 12 +#define BIT_MASK_SYS_REGU_LDOH12_ADJ 0xf +#define BIT_SYS_REGU_LDOH12_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDOH12_ADJ) << BIT_SHIFT_SYS_REGU_LDOH12_ADJ) + + +#define BIT_SHIFT_SYS_REGU_LDO25E_ADJ 8 +#define BIT_MASK_SYS_REGU_LDO25E_ADJ 0xf +#define BIT_SYS_REGU_LDO25E_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25E_ADJ) << BIT_SHIFT_SYS_REGU_LDO25E_ADJ) + +#define BIT_SYS_REGU_DSLEPM_EN BIT(7) +#define BIT_SYS_REGU_PC_33V_EN BIT(3) +#define BIT_SYS_REGU_PC_EF25_EN BIT(2) +#define BIT_SYS_REGU_LDO25M_EN BIT(1) +#define BIT_SYS_REGU_LDO25E_EN BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_SWR_CTRL0 + +#define BIT_SHIFT_SYS_SWR12_COMP_R2 30 +#define BIT_MASK_SYS_SWR12_COMP_R2 0x3 +#define BIT_SYS_SWR12_COMP_R2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R2) << BIT_SHIFT_SYS_SWR12_COMP_R2) + + +#define BIT_SHIFT_SYS_SWR12_COMP_R1 28 +#define BIT_MASK_SYS_SWR12_COMP_R1 0x3 +#define BIT_SYS_SWR12_COMP_R1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R1) << BIT_SHIFT_SYS_SWR12_COMP_R1) + + +#define BIT_SHIFT_SYS_SWR12_COMP_C3 26 +#define BIT_MASK_SYS_SWR12_COMP_C3 0x3 +#define BIT_SYS_SWR12_COMP_C3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C3) << BIT_SHIFT_SYS_SWR12_COMP_C3) + + +#define BIT_SHIFT_SYS_SWR12_COMP_C2 24 +#define BIT_MASK_SYS_SWR12_COMP_C2 0x3 +#define BIT_SYS_SWR12_COMP_C2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C2) << BIT_SHIFT_SYS_SWR12_COMP_C2) + + +#define BIT_SHIFT_SYS_SWR12_COMP_C1 22 +#define BIT_MASK_SYS_SWR12_COMP_C1 0x3 +#define BIT_SYS_SWR12_COMP_C1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C1) << BIT_SHIFT_SYS_SWR12_COMP_C1) + +#define BIT_SYS_SWR12_COMP_TYPE_L BIT(21) +#define BIT_SYS_SWR12_FPWM_MD BIT(20) + +#define BIT_SHIFT_SYS_SPSLDO_VOL 17 +#define BIT_MASK_SYS_SPSLDO_VOL 0x7 +#define BIT_SYS_SPSLDO_VOL(x) (((x) & BIT_MASK_SYS_SPSLDO_VOL) << BIT_SHIFT_SYS_SPSLDO_VOL) + + +#define BIT_SHIFT_SYS_SWR12_IN 14 +#define BIT_MASK_SYS_SWR12_IN 0x7 +#define BIT_SYS_SWR12_IN(x) (((x) & BIT_MASK_SYS_SWR12_IN) << BIT_SHIFT_SYS_SWR12_IN) + + +#define BIT_SHIFT_SYS_SWR12_STD 12 +#define BIT_MASK_SYS_SWR12_STD 0x3 +#define BIT_SYS_SWR12_STD(x) (((x) & BIT_MASK_SYS_SWR12_STD) << BIT_SHIFT_SYS_SWR12_STD) + + +#define BIT_SHIFT_SYS_SWR12_VOL 8 +#define BIT_MASK_SYS_SWR12_VOL 0xf +#define BIT_SYS_SWR12_VOL(x) (((x) & BIT_MASK_SYS_SWR12_VOL) << BIT_SHIFT_SYS_SWR12_VOL) + + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_SWR_EN BIT(1) +#define BIT_SYS_SWR_LDO_EN BIT(0) + +//2 REG_SYS_SWR_CTRL1 +#define BIT_SYS_SW12_PFM_SEL BIT(25) +#define BIT_SYS_SW12_AUTO_ZCD_L BIT(24) +#define BIT_SYS_SW12_AUTO_MODE BIT(23) +#define BIT_SYS_SW12_LDOF_L BIT(22) +#define BIT_SYS_SW12_OCPS_L BIT(21) + +#define BIT_SHIFT_SYS_SW12_TBOX 17 +#define BIT_MASK_SYS_SW12_TBOX 0x3 +#define BIT_SYS_SW12_TBOX(x) (((x) & BIT_MASK_SYS_SW12_TBOX) << BIT_SHIFT_SYS_SW12_TBOX) + + +#define BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY 15 +#define BIT_MASK_SYS_SW12_NONOVRLAP_DLY 0x3 +#define BIT_SYS_SW12_NONOVRLAP_DLY(x) (((x) & BIT_MASK_SYS_SW12_NONOVRLAP_DLY) << BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY) + +#define BIT_SYS_SW12_CLAMP_DUTY BIT(14) +#define BIT_SYS_SWR12_BYPASS_SSR BIT(13) +#define BIT_SYS_SWR12_ZCDOUT_EN BIT(12) +#define BIT_SYS_SWR12_POW_ZCD BIT(11) +#define BIT_SYS_SW12_AREN BIT(10) + +#define BIT_SHIFT_SYS_SWR12_OCP_CUR 7 +#define BIT_MASK_SYS_SWR12_OCP_CUR 0x7 +#define BIT_SYS_SWR12_OCP_CUR(x) (((x) & BIT_MASK_SYS_SWR12_OCP_CUR) << BIT_SHIFT_SYS_SWR12_OCP_CUR) + +#define BIT_SYS_SWR12_OCP_EN BIT(6) + +#define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L 4 +#define BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L 0x3 +#define BIT_SYS_SWR12_SAWTOOTH_CF_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L) + + +#define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L 2 +#define BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L 0x3 +#define BIT_SYS_SWR12_SAWTOOTH_CFC_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L) + + +#define BIT_SHIFT_SYS_SWR12_COMP_R3 0 +#define BIT_MASK_SYS_SWR12_COMP_R3 0x3 +#define BIT_SYS_SWR12_COMP_R3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R3) << BIT_SHIFT_SYS_SWR12_COMP_R3) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_SYS_XTAL_CTRL0 +#define BIT_SYS_XTAL_XQSEL BIT(31) +#define BIT_SYS_XTAL_XQSEL_RF BIT(30) + +#define BIT_SHIFT_SYS_XTAL_SC_XO 24 +#define BIT_MASK_SYS_XTAL_SC_XO 0x3f +#define BIT_SYS_XTAL_SC_XO(x) (((x) & BIT_MASK_SYS_XTAL_SC_XO) << BIT_SHIFT_SYS_XTAL_SC_XO) + + +#define BIT_SHIFT_SYS_XTAL_SC_XI 18 +#define BIT_MASK_SYS_XTAL_SC_XI 0x3f +#define BIT_SYS_XTAL_SC_XI(x) (((x) & BIT_MASK_SYS_XTAL_SC_XI) << BIT_SHIFT_SYS_XTAL_SC_XI) + + +#define BIT_SHIFT_SYS_XTAL_GMN 13 +#define BIT_MASK_SYS_XTAL_GMN 0x1f +#define BIT_SYS_XTAL_GMN(x) (((x) & BIT_MASK_SYS_XTAL_GMN) << BIT_SHIFT_SYS_XTAL_GMN) + + +#define BIT_SHIFT_SYS_XTAL_GMP 8 +#define BIT_MASK_SYS_XTAL_GMP 0x1f +#define BIT_SYS_XTAL_GMP(x) (((x) & BIT_MASK_SYS_XTAL_GMP) << BIT_SHIFT_SYS_XTAL_GMP) + +#define BIT_SYS_XTAL_EN BIT(1) +#define BIT_SYS_XTAL_BGMB_EN BIT(0) + +//2 REG_SYS_XTAL_CTRL1 + +#define BIT_SHIFT_SYS_XTAL_COUNTER_MUX 25 +#define BIT_MASK_SYS_XTAL_COUNTER_MUX 0x3 +#define BIT_SYS_XTAL_COUNTER_MUX(x) (((x) & BIT_MASK_SYS_XTAL_COUNTER_MUX) << BIT_SHIFT_SYS_XTAL_COUNTER_MUX) + +#define BIT_SYS_XTAL_DELAY_SYSPLL BIT(24) +#define BIT_SYS_XTAL_DELAY_USB BIT(23) +#define BIT_SYS_XTAL_DELAY_WLAFE BIT(22) +#define BIT_SYS_XTAL_AGPIO_SEL BIT(21) + +#define BIT_SHIFT_SYS_XTAL_DRV_AGPIO 19 +#define BIT_MASK_SYS_XTAL_DRV_AGPIO 0x3 +#define BIT_SYS_XTAL_DRV_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_DRV_AGPIO) << BIT_SHIFT_SYS_XTAL_DRV_AGPIO) + + +#define BIT_SHIFT_SYS_XTAL_AGPIO 16 +#define BIT_MASK_SYS_XTAL_AGPIO 0x7 +#define BIT_SYS_XTAL_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_AGPIO) << BIT_SHIFT_SYS_XTAL_AGPIO) + + +#define BIT_SHIFT_SYS_XTAL_DRV_SYSPLL 14 +#define BIT_MASK_SYS_XTAL_DRV_SYSPLL 0x3 +#define BIT_SYS_XTAL_DRV_SYSPLL(x) (((x) & BIT_MASK_SYS_XTAL_DRV_SYSPLL) << BIT_SHIFT_SYS_XTAL_DRV_SYSPLL) + +#define BIT_SYS_XTAL_GATE_SYSPLL BIT(13) + +#define BIT_SHIFT_SYS_XTAL_DRV_USB 11 +#define BIT_MASK_SYS_XTAL_DRV_USB 0x3 +#define BIT_SYS_XTAL_DRV_USB(x) (((x) & BIT_MASK_SYS_XTAL_DRV_USB) << BIT_SHIFT_SYS_XTAL_DRV_USB) + +#define BIT_SYS_XTAL_GATE_USB BIT(10) + +#define BIT_SHIFT_SYS_XTAL_DRV_WLAFE 8 +#define BIT_MASK_SYS_XTAL_DRV_WLAFE 0x3 +#define BIT_SYS_XTAL_DRV_WLAFE(x) (((x) & BIT_MASK_SYS_XTAL_DRV_WLAFE) << BIT_SHIFT_SYS_XTAL_DRV_WLAFE) + +#define BIT_SYS_XTAL_GATE_WLAFE BIT(7) + +#define BIT_SHIFT_SYS_XTAL_DRV_RF2 5 +#define BIT_MASK_SYS_XTAL_DRV_RF2 0x3 +#define BIT_SYS_XTAL_DRV_RF2(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF2) << BIT_SHIFT_SYS_XTAL_DRV_RF2) + +#define BIT_SYS_XTAL_GATE_RF2 BIT(4) + +#define BIT_SHIFT_SYS_XTAL_DRV_RF1 3 +#define BIT_MASK_SYS_XTAL_DRV_RF1 0x3 +#define BIT_SYS_XTAL_DRV_RF1(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF1) << BIT_SHIFT_SYS_XTAL_DRV_RF1) + +#define BIT_SYS_XTAL_GATE_RF1 BIT(1) + +#define BIT_SHIFT_SYS_XTAL_LDO 0 +#define BIT_MASK_SYS_XTAL_LDO 0x3 +#define BIT_SYS_XTAL_LDO(x) (((x) & BIT_MASK_SYS_XTAL_LDO) << BIT_SHIFT_SYS_XTAL_LDO) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_SYS_SYSPLL_CTRL0 + +#define BIT_SHIFT_SYS_SYSPLL_LPF_R3 29 +#define BIT_MASK_SYS_SYSPLL_LPF_R3 0x7 +#define BIT_SYS_SYSPLL_LPF_R3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_R3) << BIT_SHIFT_SYS_SYSPLL_LPF_R3) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_CS 27 +#define BIT_MASK_SYS_SYSPLL_LPF_CS 0x3 +#define BIT_SYS_SYSPLL_LPF_CS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CS) << BIT_SHIFT_SYS_SYSPLL_LPF_CS) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_CP 25 +#define BIT_MASK_SYS_SYSPLL_LPF_CP 0x3 +#define BIT_SYS_SYSPLL_LPF_CP(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CP) << BIT_SHIFT_SYS_SYSPLL_LPF_CP) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_C3 23 +#define BIT_MASK_SYS_SYSPLL_LPF_C3 0x3 +#define BIT_SYS_SYSPLL_LPF_C3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_C3) << BIT_SHIFT_SYS_SYSPLL_LPF_C3) + +#define BIT_SYS_SYSPLL_WDOG_ENB BIT(22) +#define BIT_SYS_SYSPLL_CKTST_EN BIT(21) + +#define BIT_SHIFT_SYS_SYSPLL_MONCK_SEL 18 +#define BIT_MASK_SYS_SYSPLL_MONCK_SEL 0x7 +#define BIT_SYS_SYSPLL_MONCK_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_MONCK_SEL) << BIT_SHIFT_SYS_SYSPLL_MONCK_SEL) + + +#define BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET 13 +#define BIT_MASK_SYS_SYSPLL_CP_IOFFSET 0x1f +#define BIT_SYS_SYSPLL_CP_IOFFSET(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_IOFFSET) << BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET) + +#define BIT_SYS_SYSPLL_CP_IDOUBLE BIT(12) + +#define BIT_SHIFT_SYS_SYSPLL_CP_BIAS 9 +#define BIT_MASK_SYS_SYSPLL_CP_BIAS 0x7 +#define BIT_SYS_SYSPLL_CP_BIAS(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_BIAS) << BIT_SHIFT_SYS_SYSPLL_CP_BIAS) + +#define BIT_SYS_SYSPLL_FREF_EDGE BIT(8) +#define BIT_SYS_SYSPLL_EN BIT(1) +#define BIT_SYS_SYSPLL_LVPC_EN BIT(0) + +//2 REG_SYS_SYSPLL_CTRL1 +#define BIT_SYS_SYSPLL_CK500K_SEL BIT(15) +#define BIT_SYS_SYSPLL_CK200M_EN BIT(14) +#define BIT_SYS_SYSPLL_CKSDR_EN BIT(13) + +#define BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV 11 +#define BIT_MASK_SYS_SYSPLL_CKSDR_DIV 0x3 +#define BIT_SYS_SYSPLL_CKSDR_DIV(x) (((x) & BIT_MASK_SYS_SYSPLL_CKSDR_DIV) << BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV) + +#define BIT_SYS_SYSPLL_CK24P576_EN BIT(9) +#define BIT_SYS_SYSPLL_CK22P5792_EN BIT(8) +#define BIT_SYS_SYSPLL_CK_PS_EN BIT(6) + +#define BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL 3 +#define BIT_MASK_SYS_SYSPLL_CK_PS_SEL 0x7 +#define BIT_SYS_SYSPLL_CK_PS_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_CK_PS_SEL) << BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_RS 0 +#define BIT_MASK_SYS_SYSPLL_LPF_RS 0x7 +#define BIT_SYS_SYSPLL_LPF_RS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_RS) << BIT_SHIFT_SYS_SYSPLL_LPF_RS) + + +//2 REG_SYS_SYSPLL_CTRL2 + +#define BIT_SHIFT_XTAL_DRV_RF_LATCH 0 +#define BIT_MASK_XTAL_DRV_RF_LATCH 0xffffffffL +#define BIT_XTAL_DRV_RF_LATCH(x) (((x) & BIT_MASK_XTAL_DRV_RF_LATCH) << BIT_SHIFT_XTAL_DRV_RF_LATCH) + + +//2 REG_RSVD + +//2 REG_RSVD + +#define BIT_SHIFT_PESOC_CPU_OCP_CK_SEL 0 +#define BIT_MASK_PESOC_CPU_OCP_CK_SEL 0x7 +#define BIT_PESOC_CPU_OCP_CK_SEL(x) (((x) & BIT_MASK_PESOC_CPU_OCP_CK_SEL) << BIT_SHIFT_PESOC_CPU_OCP_CK_SEL) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_ + +//2 REG_SYS_ANA_TIM_CTRL + +#define BIT_SHIFT_SYS_ANACK_TU_TIME 16 +#define BIT_MASK_SYS_ANACK_TU_TIME 0x3f +#define BIT_SYS_ANACK_TU_TIME(x) (((x) & BIT_MASK_SYS_ANACK_TU_TIME) << BIT_SHIFT_SYS_ANACK_TU_TIME) + +#define BIT_SYS_DSBYCNT_EN BIT(15) + +#define BIT_SHIFT_SYS_DSTDY_TIM_SCAL 8 +#define BIT_MASK_SYS_DSTDY_TIM_SCAL 0xf +#define BIT_SYS_DSTDY_TIM_SCAL(x) (((x) & BIT_MASK_SYS_DSTDY_TIM_SCAL) << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) + + +#define BIT_SHIFT_SYS_DSTBY_TIM_PERIOD 0 +#define BIT_MASK_SYS_DSTBY_TIM_PERIOD 0xff +#define BIT_SYS_DSTBY_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSTBY_TIM_PERIOD) << BIT_SHIFT_SYS_DSTBY_TIM_PERIOD) + + +//2 REG_SYS_DSLP_TIM_CTRL + +#define BIT_SHIFT_SYS_REGU_ASIF_EN 24 +#define BIT_MASK_SYS_REGU_ASIF_EN 0xff +#define BIT_SYS_REGU_ASIF_EN(x) (((x) & BIT_MASK_SYS_REGU_ASIF_EN) << BIT_SHIFT_SYS_REGU_ASIF_EN) + + +#define BIT_SHIFT_SYS_REGU_ASIF_THP_DA 20 +#define BIT_MASK_SYS_REGU_ASIF_THP_DA 0x3 +#define BIT_SYS_REGU_ASIF_THP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_THP_DA) << BIT_SHIFT_SYS_REGU_ASIF_THP_DA) + + +#define BIT_SHIFT_SYS_REGU_ASIF_TPD_CK 18 +#define BIT_MASK_SYS_REGU_ASIF_TPD_CK 0x3 +#define BIT_SYS_REGU_ASIF_TPD_CK(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TPD_CK) << BIT_SHIFT_SYS_REGU_ASIF_TPD_CK) + + +#define BIT_SHIFT_SYS_REGU_ASIF_TSP_DA 16 +#define BIT_MASK_SYS_REGU_ASIF_TSP_DA 0x3 +#define BIT_SYS_REGU_ASIF_TSP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TSP_DA) << BIT_SHIFT_SYS_REGU_ASIF_TSP_DA) + +#define BIT_SYS_REGU_ASIF_POLL BIT(15) +#define BIT_SYS_REGU_ASIF_MODE BIT(14) +#define BIT_SYS_REGU_ASIF_WE BIT(12) + +#define BIT_SHIFT_SYS_REGU_ASIF_AD 8 +#define BIT_MASK_SYS_REGU_ASIF_AD 0xf +#define BIT_SYS_REGU_ASIF_AD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_AD) << BIT_SHIFT_SYS_REGU_ASIF_AD) + + +#define BIT_SHIFT_SYS_REGU_ASIF_WD 0 +#define BIT_MASK_SYS_REGU_ASIF_WD 0xff +#define BIT_SYS_REGU_ASIF_WD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_WD) << BIT_SHIFT_SYS_REGU_ASIF_WD) + + +//2 REG_SYS_DSLP_TIM_CAL_CTRL +#define BIT_SYS_DSLP_TIM_EN BIT(24) + +#define BIT_SHIFT_SYS_DSLP_TIM_PERIOD 0 +#define BIT_MASK_SYS_DSLP_TIM_PERIOD 0x7fffff +#define BIT_SYS_DSLP_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSLP_TIM_PERIOD) << BIT_SHIFT_SYS_DSLP_TIM_PERIOD) + + +//2 REG_RSVD + +//2 REG_SYS_DEBUG_CTRL +#define BIT_SYS_DBG_PIN_EN BIT(0) + +//2 REG_SYS_PINMUX_CTRL +#define BIT_EEPROM_PIN_EN BIT(4) +#define BIT_SIC_PIN_EN BIT(0) + +//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL0 +#define BIT_SYS_GPIOE3_WEVENT_STS BIT(27) +#define BIT_SYS_GPIOD5_WEVENT_STS BIT(26) +#define BIT_SYS_GPIOC7_WEVENT_STS BIT(25) +#define BIT_SYS_GPIOA5_WEVENT_STS BIT(24) +#define BIT_SYS_GPIO_GPE3_PULL_CTRL_EN BIT(19) +#define BIT_SYS_GPIO_GPD5_PULL_CTRL_EN BIT(18) +#define BIT_SYS_GPIO_GPC7_PULL_CTRL_EN BIT(17) +#define BIT_SYS_GPIO_GPA5_PULL_CTRL_EN BIT(16) +#define BIT_SYS_GPIOE3_WINT_MODE BIT(11) +#define BIT_SYS_GPIOD5_WINT_MODE BIT(10) +#define BIT_SYS_GPIOC7_WINT_MODE BIT(9) +#define BIT_SYS_GPIOA5_WINT_MODE BIT(8) +#define BIT_SYS_GPIOE3_PIN_EN BIT(3) +#define BIT_SYS_GPIOD5_PIN_EN BIT(2) +#define BIT_SYS_GPIOC7_PIN_EN BIT(1) +#define BIT_SYS_GPIOA5_PIN_EN BIT(0) + +//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL1 +#define BIT_SYS_GPIOE3_SHTDN_N BIT(19) +#define BIT_SYS_GPIOD5_SHTDN_N BIT(18) +#define BIT_SYS_GPIOC7_SHTDN_N BIT(17) +#define BIT_SYS_GPIOA5_SHTDN_N BIT(16) + +#define BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL 8 +#define BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL 0x3 +#define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL(x) (((x) & BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL) << BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL) + +#define BIT_SYS_GPIOE3_WINT_DEBOUNCE_EN BIT(3) +#define BIT_SYS_GPIOD5_WINT_DEBOUNCE_EN BIT(2) +#define BIT_SYS_GPIOC7_WINT_DEBOUNCE_EN BIT(1) +#define BIT_SYS_GPIOA5_WINT_DEBOUNCE_EN BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_DEBUG_REG + +#define BIT_SHIFT_SYS_DBG_VALUE 0 +#define BIT_MASK_SYS_DBG_VALUE 0xffffffffL +#define BIT_SYS_DBG_VALUE(x) (((x) & BIT_MASK_SYS_DBG_VALUE) << BIT_SHIFT_SYS_DBG_VALUE) + + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_EEPROM_CTRL0 + +#define BIT_SHIFT_EFUSE_UNLOCK 24 +#define BIT_MASK_EFUSE_UNLOCK 0xff +#define BIT_EFUSE_UNLOCK(x) (((x) & BIT_MASK_EFUSE_UNLOCK) << BIT_SHIFT_EFUSE_UNLOCK) + + +//2 REG_NOT_VALID +#define BIT_SYS_EFUSE_LDALL BIT(16) + +#define BIT_SHIFT_SYS_EEPROM_VPDIDX 8 +#define BIT_MASK_SYS_EEPROM_VPDIDX 0xff +#define BIT_SYS_EEPROM_VPDIDX(x) (((x) & BIT_MASK_SYS_EEPROM_VPDIDX) << BIT_SHIFT_SYS_EEPROM_VPDIDX) + + +#define BIT_SHIFT_SYS_EEPROM_MD 6 +#define BIT_MASK_SYS_EEPROM_MD 0x3 +#define BIT_SYS_EEPROM_MD(x) (((x) & BIT_MASK_SYS_EEPROM_MD) << BIT_SHIFT_SYS_EEPROM_MD) + +#define BIT_SYS_AUTOLOAD_SUS BIT(5) +#define BIT_SYS_EEPROM_SEL BIT(4) +#define BIT_SYS_EEPROM_EECS BIT(3) +#define BIT_SYS_EEPROM_EESK BIT(2) +#define BIT_SYS_EEPROM_EEDI BIT(1) +#define BIT_SYS_EEPROM_EEDO BIT(0) + +//2 REG_SYS_EEPROM_CTRL1 + +#define BIT_SHIFT_SYS_EEPROM_VPD 0 +#define BIT_MASK_SYS_EEPROM_VPD 0xffffffffL +#define BIT_SYS_EEPROM_VPD(x) (((x) & BIT_MASK_SYS_EEPROM_VPD) << BIT_SHIFT_SYS_EEPROM_VPD) + + +//2 REG_SYS_EFUSE_CTRL +#define BIT_SYS_EF_RWFLAG BIT(31) + +#define BIT_SHIFT_SYS_EF_PGPD 28 +#define BIT_MASK_SYS_EF_PGPD 0x7 +#define BIT_SYS_EF_PGPD(x) (((x) & BIT_MASK_SYS_EF_PGPD) << BIT_SHIFT_SYS_EF_PGPD) + + +#define BIT_SHIFT_SYS_EF_RDT 24 +#define BIT_MASK_SYS_EF_RDT 0xf +#define BIT_SYS_EF_RDT(x) (((x) & BIT_MASK_SYS_EF_RDT) << BIT_SHIFT_SYS_EF_RDT) + + +#define BIT_SHIFT_SYS_EF_PGTS 20 +#define BIT_MASK_SYS_EF_PGTS 0xf +#define BIT_SYS_EF_PGTS(x) (((x) & BIT_MASK_SYS_EF_PGTS) << BIT_SHIFT_SYS_EF_PGTS) + +#define BIT_SYS_EF_PDWN BIT(19) +#define BIT_SYS_EF_ALDEN BIT(18) + +#define BIT_SHIFT_SYS_EF_ADDR 8 +#define BIT_MASK_SYS_EF_ADDR 0x3ff +#define BIT_SYS_EF_ADDR(x) (((x) & BIT_MASK_SYS_EF_ADDR) << BIT_SHIFT_SYS_EF_ADDR) + + +#define BIT_SHIFT_SYS_EF_DATA 0 +#define BIT_MASK_SYS_EF_DATA 0xff +#define BIT_SYS_EF_DATA(x) (((x) & BIT_MASK_SYS_EF_DATA) << BIT_SHIFT_SYS_EF_DATA) + + +//2 REG_SYS_EFUSE_TEST +#define BIT_SYS_EF_CRES_SEL BIT(26) + +#define BIT_SHIFT_SYS_EF_SCAN_START 16 +#define BIT_MASK_SYS_EF_SCAN_START 0x1ff +#define BIT_SYS_EF_SCAN_START(x) (((x) & BIT_MASK_SYS_EF_SCAN_START) << BIT_SHIFT_SYS_EF_SCAN_START) + + +#define BIT_SHIFT_SYS_EF_SCAN_END 12 +#define BIT_MASK_SYS_EF_SCAN_END 0xf +#define BIT_SYS_EF_SCAN_END(x) (((x) & BIT_MASK_SYS_EF_SCAN_END) << BIT_SHIFT_SYS_EF_SCAN_END) + +#define BIT_SYS_EF_FORCE_PGMEN BIT(11) + +#define BIT_SHIFT_SYS_EF_CELL_SEL 8 +#define BIT_MASK_SYS_EF_CELL_SEL 0x3 +#define BIT_SYS_EF_CELL_SEL(x) (((x) & BIT_MASK_SYS_EF_CELL_SEL) << BIT_SHIFT_SYS_EF_CELL_SEL) + +#define BIT_SYS_EF_TRPT BIT(7) + +#define BIT_SHIFT_SYS_EF_SCAN_TTHD 0 +#define BIT_MASK_SYS_EF_SCAN_TTHD 0x7f +#define BIT_SYS_EF_SCAN_TTHD(x) (((x) & BIT_MASK_SYS_EF_SCAN_TTHD) << BIT_SHIFT_SYS_EF_SCAN_TTHD) + + +//2 REG_SYS_DSTBY_INFO0 + +//2 REG_NOT_VALID + +//2 REG_SYS_DSTBY_INFO1 + +//2 REG_SYS_DSTBY_INFO2 + +//2 REG_NOT_VALID + +//2 REG_SYS_DSTBY_INFO3 + +//2 REG_SYS_SLP_WAKE_EVENT_MSK0 +#define BIT_SYSON_WEVT_GPIO_DSTBY_MSK BIT(29) +#define BIT_SYSON_WEVT_A33_MSK BIT(28) +#define BIT_SYSON_WEVT_ADC_MSK BIT(26) +#define BIT_SYSON_WEVT_I2C_MSK BIT(24) +#define BIT_SYSON_WEVT_SPI_MSK BIT(22) +#define BIT_SYSON_WEVT_UART_MSK BIT(20) +#define BIT_SYSON_WEVT_USB_MSK BIT(16) +#define BIT_SYSON_WEVT_SDIO_MSK BIT(14) +#define BIT_SYSON_WEVT_NFC_MSK BIT(9) +#define BIT_SYSON_WEVT_WLAN_MSK BIT(8) +#define BIT_SYSON_WEVT_GPIO_MSK BIT(4) +#define BIT_SYSON_WEVT_CHIP_EN_MSK BIT(3) +#define BIT_SYSON_WEVT_OVER_CURRENT_MSK BIT(2) +#define BIT_SYSON_WEVT_GTIM_MSK BIT(1) +#define BIT_SYSON_WEVT_SYSTIM_MSK BIT(0) + +//2 REG_SYS_SLP_WAKE_EVENT_MSK1 + +//2 REG_SYS_SLP_WAKE_EVENT_STATUS0 +#define BIT_SYSON_WEVT_GPIO_DSTBY_STS BIT(29) +#define BIT_SYSON_WEVT_A33_STS BIT(28) +#define BIT_SYSON_WEVT_ADC_STS BIT(26) +#define BIT_SYSON_WEVT_I2C_STS BIT(24) +#define BIT_SYSON_WEVT_SPI_STS BIT(22) +#define BIT_SYSON_WEVT_UART_STS BIT(20) +#define BIT_SYSON_WEVT_USB_STS BIT(16) +#define BIT_SYSON_WEVT_SDIO_STS BIT(14) +#define BIT_SYSON_WEVT_NFC_STS BIT(9) +#define BIT_SYSON_WEVT_WLAN_STS BIT(8) +#define BIT_SYSON_WEVT_GPIO_STS BIT(4) +#define BIT_SYSON_WEVT_CHIP_EN_STS BIT(3) +#define BIT_SYSON_WEVT_OVER_CURRENT_STS BIT(2) +#define BIT_SYSON_WEVT_GTIM_STS BIT(1) +#define BIT_SYSON_WEVT_SYSTIM_STS BIT(0) + +//2 REG_SYS_SLP_WAKE_EVENT_STATUS1 + +//2 REG_SYS_SNF_WAKE_EVENT_MSK0 + +#define BIT_SHIFT_SYS_WKPERI_IMR0 1 +#define BIT_MASK_SYS_WKPERI_IMR0 0x7fffffffL +#define BIT_SYS_WKPERI_IMR0(x) (((x) & BIT_MASK_SYS_WKPERI_IMR0) << BIT_SHIFT_SYS_WKPERI_IMR0) + +#define BIT_SYSON_SNFEVT_ADC_MSK BIT(0) + +//2 REG_SYS_SNF_WAKE_EVENT_STATUS + +#define BIT_SHIFT_SYS_WKPERI_ISR0 1 +#define BIT_MASK_SYS_WKPERI_ISR0 0x7fffffffL +#define BIT_SYS_WKPERI_ISR0(x) (((x) & BIT_MASK_SYS_WKPERI_ISR0) << BIT_SHIFT_SYS_WKPERI_ISR0) + +#define BIT_SYSON_SNFEVT_ADC_STS BIT(0) + +//2 REG_SYS_PWRMGT_CTRL +#define BIT_SYSON_REGU_DSLP BIT(7) + +//2 REG_NOT_VALID +#define BIT_SYSON_PM_CMD_SLP BIT(2) +#define BIT_SYSON_PM_CMD_DSTBY BIT(1) +#define BIT_SYSON_PM_CMD_DSLP BIT(0) + +//2 REG_RSVD + +//2 REG_SYS_PWRMGT_OPTION +#define BIT_SYSON_PMOPT_NORM_SYSCLK_SEL BIT(30) +#define BIT_SYSON_PMOPT_NORM_SYSPLL_EN BIT(29) +#define BIT_SYSON_PMOPT_NORM_XTAL_EN BIT(28) +#define BIT_SYSON_PMOPT_NORM_EN_SOC BIT(27) +#define BIT_SYSON_PMOPT_NORM_EN_PWM BIT(26) +#define BIT_SYSON_PMOPT_NORM_EN_SWR BIT(25) +#define BIT_SYSON_PMOPT_NORM_LPLDO_SEL BIT(24) +#define BIT_SYSON_PMOPT_SNZ_SYSCLK_SEL BIT(22) +#define BIT_SYSON_PMOPT_SNZ_SYSPLL_EN BIT(21) +#define BIT_SYSON_PMOPT_SNZ_XTAL_EN BIT(20) +#define BIT_SYSON_PMOPT_SNZ_EN_SOC BIT(19) +#define BIT_SYSON_PMOPT_SNZ_EN_PWM BIT(18) +#define BIT_SYSON_PMOPT_SNZ_EN_SWR BIT(17) +#define BIT_SYSON_PMOPT_SNZ_LPLDO_SEL BIT(16) +#define BIT_SYSON_PMOPT_SLP_SYSCLK_SEL BIT(14) +#define BIT_SYSON_PMOPT_SLP_SYSPLL_EN BIT(13) +#define BIT_SYSON_PMOPT_SLP_XTAL_EN BIT(12) +#define BIT_SYSON_PMOPT_SLP_EN_SOC BIT(11) +#define BIT_SYSON_PMOPT_SLP_EN_PWM BIT(10) +#define BIT_SYSON_PMOPT_SLP_EN_SWR BIT(9) +#define BIT_SYSON_PMOPT_SLP_LPLDO_SEL BIT(8) +#define BIT_SYSON_PMOPT_DSTBY_SYSCLK_SEL BIT(6) +#define BIT_SYSON_PMOPT_DSTBY_SYSPLL_EN BIT(5) +#define BIT_SYSON_PMOPT_DSTBY_XTAL_EN BIT(4) +#define BIT_SYSON_PMOPT_DSTBY_EN_SOC BIT(3) +#define BIT_SYSON_PMOPT_DSTBY_EN_PWM BIT(2) +#define BIT_SYSON_PMOPT_DSTBY_EN_SWR BIT(1) +#define BIT_SYSON_PMOPT_DSTBY_LPLDO_SEL BIT(0) + +//2 REG_SYS_PWRMGT_OPTION_EXT +#define BIT_SYSON_PMOPT_SLP_ANACK_SEL BIT(2) +#define BIT_SYSON_PMOPT_SLP_ANACK_EN BIT(1) +#define BIT_SYSON_PMOPT_SLP_SWR_ADJ BIT(0) + +//2 REG_SYS_DSLP_WEVENT +#define BIT_SYSON_DSLP_GPIO BIT(2) +#define BIT_SYSON_DSLP_NFC BIT(1) +#define BIT_SYSON_DSLP_WTIMER33 BIT(0) + +//2 REG_SYS_PERI_MONITOR +#define BIT_SYSON_ISO33_NFC BIT(0) + +//2 REG_SYS_SYSTEM_CFG0 +#define BIT_SYSCFG_BD_PKG_SEL BIT(31) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +#define BIT_SHIFT_VENDOR_ID 8 +#define BIT_MASK_VENDOR_ID 0xf +#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) + + +#define BIT_SHIFT_CHIP_VER 4 +#define BIT_MASK_CHIP_VER 0xf +#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) + + +#define BIT_SHIFT_RF_RL_ID 0 +#define BIT_MASK_RF_RL_ID 0xf +#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) + + +//2 REG_SYS_SYSTEM_CFG1 + +#define BIT_SHIFT_SYSCFG_TRP_ICFG 28 +#define BIT_MASK_SYSCFG_TRP_ICFG 0xf +#define BIT_SYSCFG_TRP_ICFG(x) (((x) & BIT_MASK_SYSCFG_TRP_ICFG) << BIT_SHIFT_SYSCFG_TRP_ICFG) + +#define BIT_SYSCFG_TRP_BOOT_SEL_ BIT(27) +#define BIT_SysCFG_TRP_SPSLDO_SEL BIT(26) +#define BIT_V15_VLD BIT(16) +#define BIT_SYS_SYSPLL_CLK_RDY BIT(9) +#define BIT_SYS_XCLK_VLD BIT(8) +#define BIT_SYSCFG_ALDN_STS BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + + +//================= Register Address Definition =====================// +#define REG_SYS_PWR_CTRL 0x0000 +#define REG_SYS_ISO_CTRL 0x0002 +#define REG_SYS_FUNC_EN 0x0008 +#define REG_SYS_CLK_CTRL0 0x0010 +#define REG_SYS_CLK_CTRL1 0x0014 +#define REG_SYS_EFUSE_SYSCFG0 0x0020 +#define REG_SYS_EFUSE_SYSCFG1 0x0024 +#define REG_SYS_EFUSE_SYSCFG2 0x0028 +#define REG_SYS_EFUSE_SYSCFG3 0x002C +#define REG_SYS_EFUSE_SYSCFG4 0x0030 +#define REG_SYS_EFUSE_SYSCFG5 0x0034 +#define REG_SYS_EFUSE_SYSCFG6 0x0038 +#define REG_SYS_EFUSE_SYSCFG7 0x003C +#define REG_SYS_REGU_CTRL0 0x0040 +#define REG_SYS_SWR_CTRL0 0x0048 +#define REG_SYS_SWR_CTRL1 0x004C +#define REG_SYS_XTAL_CTRL0 0x0060 +#define REG_SYS_XTAL_CTRL1 0x0064 +#define REG_SYS_SYSPLL_CTRL0 0x0070 +#define REG_SYS_SYSPLL_CTRL1 0x0074 +#define REG_SYS_SYSPLL_CTRL2 0x0078 +#define REG_SYS_ANA_TIM_CTRL 0x0090 +#define REG_SYS_DSLP_TIM_CTRL 0x0094 +#define REG_SYS_DSLP_TIM_CAL_CTRL 0x0098 +#define REG_SYS_DEBUG_CTRL 0x00A0 +#define REG_SYS_PINMUX_CTRL 0x00A4 +#define REG_SYS_GPIO_DSTBY_WAKE_CTRL0 0x00A8 +#define REG_SYS_GPIO_DSTBY_WAKE_CTRL1 0x00AC +#define REG_SYS_DEBUG_REG 0x00BC +#define REG_SYS_EEPROM_CTRL0 0x00E0 +#define REG_SYS_EEPROM_CTRL1 0x00E4 +#define REG_SYS_EFUSE_CTRL 0x00E8 +#define REG_SYS_EFUSE_TEST 0x00EC +#define REG_SYS_DSTBY_INFO0 0x00F0 +#define REG_SYS_DSTBY_INFO1 0x00F4 +#define REG_SYS_DSTBY_INFO2 0x00F8 +#define REG_SYS_DSTBY_INFO3 0x00FC +#define REG_SYS_SLP_WAKE_EVENT_MSK0 0x0100 +#define REG_SYS_SLP_WAKE_EVENT_MSK1 0x0104 +#define REG_SYS_SLP_WAKE_EVENT_STATUS0 0x0108 +#define REG_SYS_SLP_WAKE_EVENT_STATUS1 0x010C +#define REG_SYS_SNF_WAKE_EVENT_MSK0 0x0110 +#define REG_SYS_SNF_WAKE_EVENT_STATUS 0x0114 +#define REG_SYS_PWRMGT_CTRL 0x0118 +#define REG_SYS_PWRMGT_OPTION 0x0120 +#define REG_SYS_PWRMGT_OPTION_EXT 0x0124 +#define REG_SYS_DSLP_WEVENT 0x0130 +#define REG_SYS_PERI_MONITOR 0x0134 +#define REG_SYS_SYSTEM_CFG0 0x01F0 +#define REG_SYS_SYSTEM_CFG1 0x01F4 +#define REG_SYS_SYSTEM_CFG2 0x01F8 + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h new file mode 100644 index 00000000000..5424a74d4e0 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h @@ -0,0 +1,257 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_TIMER_H_ +#define _RTL8195A_TIMER_H_ + + +#define TIMER_TICK_US 31 + +#define TIMER_LOAD_COUNT_OFF 0x00 +#define TIMER_CURRENT_VAL_OFF 0x04 +#define TIMER_CTL_REG_OFF 0x08 +#define TIMER_EOI_OFF 0x0c +#define TIMER_INT_STATUS_OFF 0x10 +#define TIMER_INTERVAL 0x14 +#define TIMERS_INT_STATUS_OFF 0xa0 +#define TIMERS_EOI_OFF 0xa4 +#define TIMERS_RAW_INT_STATUS_OFF 0xa8 +#define TIMERS_COMP_VER_OFF 0xac + +#define MAX_TIMER_VECTOR_TABLE_NUM 6 + +#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr) +#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value) +#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr) +#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value) +#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr) +#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value) + +_LONG_CALL_ u32 +HalGetTimerIdRtl8195a( + IN u32 *TimerID +); + +_LONG_CALL_ BOOL +HalTimerInitRtl8195a( + IN VOID *Data +); + +_LONG_CALL_ u32 +HalTimerReadCountRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerIrqClearRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerDisRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerEnRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerDumpRegRtl8195a( + IN u32 TimerId +); + +// ROM Code patch +HAL_Status +HalTimerInitRtl8195a_Patch( + IN VOID *Data +); + +u32 +HalTimerReadCountRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerReLoadRtl8195a_Patch( + IN u32 TimerId, + IN u32 LoadUs +); + +u32 +HalTimerReadCountRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerIrqEnRtl8195a( + IN u32 TimerId +); + +VOID +HalTimerIrqDisRtl8195a( + IN u32 TimerId +); + +VOID +HalTimerClearIsrRtl8195a( + IN u32 TimerId +); + +VOID +HalTimerEnRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerDisRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerDeInitRtl8195a_Patch( + IN VOID *Data +); + +#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT) + +__weak _LONG_CALL_ +VOID +HalTimerIrq2To7HandleV02( + IN VOID *Data +); + +__weak _LONG_CALL_ROM_ +HAL_Status +HalTimerIrqRegisterRtl8195aV02( + IN VOID *Data +); + +__weak _LONG_CALL_ +HAL_Status +HalTimerInitRtl8195aV02( + IN VOID *Data +); + +__weak _LONG_CALL_ +u32 +HalTimerReadCountRtl8195aV02( + IN u32 TimerId +); + +__weak _LONG_CALL_ +VOID +HalTimerReLoadRtl8195aV02( + IN u32 TimerId, + IN u32 LoadUs +); + +__weak _LONG_CALL_ROM_ +HAL_Status +HalTimerIrqUnRegisterRtl8195aV02( + IN VOID *Data +); + +__weak _LONG_CALL_ +VOID +HalTimerDeInitRtl8195aV02( + IN VOID *Data +); + +#endif // end of "#ifdef CONFIG_CHIP_C_CUT" + +#ifdef CONFIG_CHIP_E_CUT +_LONG_CALL_ VOID +HalTimerReLoadRtl8195a_V04( + IN u32 TimerId, + IN u32 LoadUs +); + +_LONG_CALL_ HAL_Status +HalTimerInitRtl8195a_V04( + IN VOID *Data +); +#endif // #ifdef CONFIG_CHIP_E_CUT + +// HAL functions wrapper +#ifndef CONFIG_RELEASE_BUILD_LIBRARIES +static __inline HAL_Status +HalTimerInit( + IN VOID *Data +) +{ +#ifdef CONFIG_CHIP_E_CUT + return (HalTimerInitRtl8195a_V04(Data)); +#else + return (HalTimerInitRtl8195a_Patch(Data)); +#endif +} + +static __inline VOID +HalTimerEnable( + IN u32 TimerId +) +{ + HalTimerIrqEnRtl8195a(TimerId); + HalTimerEnRtl8195a_Patch(TimerId); +} + +static __inline VOID +HalTimerDisable( + IN u32 TimerId +) +{ + HalTimerDisRtl8195a_Patch(TimerId); +} + +static __inline VOID +HalTimerClearIsr( + IN u32 TimerId +) +{ + HalTimerClearIsrRtl8195a(TimerId); +} + +static __inline VOID +HalTimerReLoad( + IN u32 TimerId, + IN u32 LoadUs +) +{ +#ifdef CONFIG_CHIP_E_CUT + HalTimerReLoadRtl8195a_V04(TimerId, LoadUs); +#else + HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs); +#endif +} + +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) + +static __inline VOID +HalTimerDeInit( + IN VOID *Data +) +{ + HalTimerDeInitRtl8195a_Patch(Data); +} + +#else + +static __inline VOID +HalTimerDeInit( + IN VOID *Data +) +{ + HalTimerDeInitRtl8195aV02(Data); +} + +#endif // end of "#ifndef CONFIG_CHIP_C_CUT" +#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES +#endif //_RTL8195A_TIMER_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_trap.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_trap.h new file mode 100644 index 00000000000..157e179abec --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_trap.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_RTL8195A_TRAP_H +#define MBED_RTL8195A_TRAP_H + +#if 0 +typedef enum { +/****** Cortex-M3 Processor Exceptions Numbers ********/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** RTL8195A Specific Interrupt Numbers ************/ + SYSTEM_ON_IRQ = 0, + WDG_IRQ = 1, + TIMER0_IRQ = 2, + TIMER1_IRQ = 3, + I2C3_IRQ = 4, + TIMER2_7_IRQ = 5, + SPI0_IRQ = 6, + GPIO_IRQ = 7, + UART0_IRQ = 8, + SPI_FLASH_IRQ = 9, + USB_OTG_IRQ = 10, + SDIO_HOST_IRQ = 11, + SDIO_DEVICE_IRQ = 12, + I2S0_PCM0_IRQ = 13, + I2S1_PCM1_IRQ = 14, + WL_DMA_IRQ = 15, + WL_PROTOCOL_IRQ = 16, + CRYPTO_IRQ = 17, + GMAC_IRQ = 18, + PERIPHERAL_IRQ = 19, + GDMA0_CHANNEL0_IRQ = 20, + GDMA0_CHANNEL1_IRQ = 21, + GDMA0_CHANNEL2_IRQ = 22, + GDMA0_CHANNEL3_IRQ = 23, + GDMA0_CHANNEL4_IRQ = 24, + GDMA0_CHANNEL5_IRQ = 25, + GDMA1_CHANNEL0_IRQ = 26, + GDMA1_CHANNEL1_IRQ = 27, + GDMA1_CHANNEL2_IRQ = 28, + GDMA1_CHANNEL3_IRQ = 29, + GDMA1_CHANNEL4_IRQ = 30, + GDMA1_CHANNEL5_IRQ = 31, + +/****** RTL8195A Peripheral Interrupt Numbers ************/ + I2C0_IRQ = 64,// 0 + 64, + I2C1_IRQ = 65,// 1 + 64, + I2C2_IRQ = 66,// 2 + 64, + SPI1_IRQ = 72,// 8 + 64, + SPI2_IRQ = 73,// 9 + 64, + UART1_IRQ = 80,// 16 + 64, + UART2_IRQ = 81,// 17 + 64, + UART3_IRQ = 88,// 24 + 64, + ADC_IRQ = 89,// 25 + 64, + DAC0_IRQ = 91,// 27 + 64, + DAC1_IRQ = 92,// 28 + 64, + LP_EXTENSION_IRQ = 93,// 29 + 64 + + PTA_TRX_IRQ = 95,// 31 + 64 + RXI300_IRQ = 96,// 0 + 32 + 64 + NFC_IRQ = 97 // 1 + 32 + 64 +} IRQn_Type; + + +typedef void (*IRQn_Func)(void *data); + +typedef struct { + IRQn_Func handler; + IRQn_Type irqnum; + uint32_t data; + uint32_t priority; +} IRQ_Handle; +#endif + +typedef void (*VECTOR_Func)(void *data); + +typedef struct { + void (*RamStartFun)(void); +} RAM_START_FUNCTION; + +typedef struct { + void (*RamStartFun)(void); + void (*RamWakeupFun)(void); + void (*RamPatchFun0)(void); + void (*RamPatchFun1)(void); + void (*RamPatchFun2)(void); +} RAM_START_TABLE; + +extern uint8_t * __ram_table_start__; + +#if 0 +// Interface to ROM functions +extern __longcall void VectorTableInitRtl8195A(uint32_t stackp); +extern __longcall void VectorTableInitForOSRtl8195A(void *svc, void *svh, void *tick); +extern __longcall bool VectorIrqRegisterRtl8195A(IRQ_Handle *handle); +extern __longcall bool VectorIrqUnRegisterRtl8195A(IRQ_Handle *handle); +extern __longcall void VectorIrqEnRtl8195A(IRQ_Handle *handle); +extern __longcall void VectorIrqDisRtl8195A(IRQ_Handle *handle); +extern __longcall void HalPeripheralIntrHandle(void); +extern __longcall void HalHardFaultHandler(uint32_t); +#endif + +extern __longcall void HalWdgIntrHandle(void); +extern __longcall void HalHardFaultHandler(u32); + + +#define __TRAP_Init VectorTableInitForOSRtl8195A +#define __TRAP_SetVector VectorTableInitRtl8195A +#define __TRAP_HardFaultHandler HalHardFaultHandler +#define __INTR_Register VectorIrqRegisterRtl8195A +#define __INTR_Unregister VectorIrqUnRegisterRtl8195A +#define __INTR_Enable VectorIrqEnRtl8195A +#define __INTR_Disable VectorIrqDisRtl8195A +#define __INTR_WatchdogHandler HalWdgIntrHandle + +// Interface for HAL layer +static inline void TRAP_Init(void *svc, void *svh, void *tick) +{ + __TRAP_Init(svc, svh, tick); +} + +static inline void TRAP_SetVector(uint32_t stackp) +{ + __TRAP_SetVector(stackp); +} + +static inline bool INTR_Register(IRQ_Handle *handle) +{ + return __INTR_Register(handle); +} + +static inline bool INTR_Unregister(IRQ_Handle *handle) +{ + return __INTR_Unregister(handle); +} + +static inline void INTR_Enable(IRQ_Handle *handle) +{ + __INTR_Enable(handle); +} + +static inline void INTR_Disable(IRQ_Handle *handle) +{ + __INTR_Disable(handle); +} +static inline void INTR_WatchdogHandler(void) +{ + __INTR_WatchdogHandler(); +} + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_uart.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_uart.h new file mode 100644 index 00000000000..48383524de0 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_uart.h @@ -0,0 +1,656 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _RTL8195A_UART_H_ +#define _RTL8195A_UART_H_ + +#define MAX_UART_INDEX 2 + +#define RUART_DLL_OFF 0x00 +#define RUART_DLM_OFF 0x04 //RW, DLAB = 1 +#define RUART_INTERRUPT_EN_REG_OFF 0x04 +#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger) +#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty) +#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status) +#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition) + +#define RUART_INT_ID_REG_OFF 0x08 //[R] +#define RUART_IIR_INT_PEND 0x01 +#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0) +#define RUART_FIFO_CTL_REG_OFF 0x08 //[W] +#define RUART_FIFO_CTL_REG_FIFO_ENABLE 0x01 //BIT0 +#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear +#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear +#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3 + +#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9 +#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1 + +#define RUART_MODEM_CTL_REG_OFF 0x10 +#define RUART_MCR_RTS BIT1 +#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20 + +#define RUART_LINE_CTL_REG_OFF 0x0C +#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80 + +#define RUART_LINE_STATUS_REG_OFF 0x14 +#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator +#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run +#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error +#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error +#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error +#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable +#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit) +#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error +#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \ + RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \ + RUART_LINE_STATUS_ERR_RXFIFO) //Line status error + +#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register +#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register +#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear +#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection +#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16] + +#define RUART_STS_REG_OFF 0x20 +#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver +#define RUART_STS_REG_XFACTOR 0xF<<4 + +#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register +#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register + +#define RUART_MISC_CTL_REG_OFF 0x28 +#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3 +#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8 + +#define RUART_DEBUG_REG_OFF 0x3C + +// RUART_LINE_CTL_REG_OFF (0x0C) +#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits +#define BIT_MASK_LCR_WLS_8BITS 0x1 +#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS) +#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS)) + +#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit +#define BIT_MASK_LCR_STB_EN 0x1 +#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB) +#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB)) + +#define BIT_SHIFT_LCR_PARITY_EN 3 +#define BIT_MASK_LCR_PARITY_EN 0x1 +#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN) +#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN)) + +#define BIT_SHIFT_LCR_PARITY_TYPE 4 +#define BIT_MASK_LCR_PARITY_TYPE 0x1 +#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE) +#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE)) + +#define BIT_SHIFT_LCR_STICK_PARITY_EN 5 +#define BIT_MASK_LCR_STICK_PARITY_EN 0x1 +#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN) +#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN)) + +#define BIT_SHIFT_LCR_BREAK_CTRL 6 +#define BIT_MASK_LCR_BREAK_CTRL 0x1 +#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL) + +#define RUART_BAUD_RATE_2400 2400 +#define RUART_BAUD_RATE_4800 4800 +#define RUART_BAUD_RATE_9600 9600 +#define RUART_BAUD_RATE_19200 19200 +#define RUART_BAUD_RATE_38400 38400 +#define RUART_BAUD_RATE_57600 57600 +#define RUART_BAUD_RATE_115200 115200 +#define RUART_BAUD_RATE_921600 921600 +#define RUART_BAUD_RATE_1152000 1152000 + +#define HAL_RUART_READ32(UartIndex, addr) \ + HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) +#define HAL_RUART_WRITE32(UartIndex, addr, value) \ + HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) +#define HAL_RUART_READ16(UartIndex, addr) \ + HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) +#define HAL_RUART_WRITE16(UartIndex, addr, value) \ + HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) +#define HAL_RUART_READ8(UartIndex, addr) \ + HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) +#define HAL_RUART_WRITE8(UartIndex, addr, value) \ + HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) + +#define UART_OVSR_POOL_MIN 1000 +#define UART_OVSR_POOL_MAX 2090 +#define DIVISOR_RESOLUTION 10 +#define JITTER_LIMIT 100 +#define UART_SCLK (200000000*5/12) + +typedef struct _RUART_SPEED_SETTING_ { + u32 BaudRate; + u32 Ovsr; + u32 Div; + u32 Ovsr_adj; +#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES)) + u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity + u8 Ovsr_adj_bits; + u16 *Ovsr_adj_map; + u32 max_err; // 10 ~ 100: 30 + u32 Ovsr_min; // 10 ~ 20: 1000 + u32 Ovsr_max; // 10 ~ 20: 2000 + u32 divisor_resolution; // 1 ~ 20: 10 + u32 jitter_lim; // 50 ~ 100: 100 + u32 sclk; // 83.33333 MHz +#endif +}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING; + +typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ { + OneByte = 0x00, + FourBytes = 0x01, + EightBytes = 0x10, + FourteenBytes = 0x11 +}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL; + +typedef enum _RUART0_PINMUX_SELECT_ { + RUART0_MUX_TO_GPIOC = S0, + RUART0_MUX_TO_GPIOE = S1, + RUART0_MUX_TO_GPIOA = S2 +}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT; + +typedef enum _RUART1_PINMUX_SELECT_ { + RUART1_MUX_TO_GPIOD = S0, + RUART1_MUX_TO_GPIOE = S1, + RUART1_MUX_TO_GPIOB = S2 +}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT; + +typedef enum _RUART2_PINMUX_SELECT_ { + RUART2_MUX_TO_GPIOA = S0, + RUART2_MUX_TO_GPIOC = S1, + RUART2_MUX_TO_GPIOD = S2 +}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT; + +typedef enum _RUART_FLOW_CONTROL_ { + AUTOFLOW_DISABLE = 0, + AUTOFLOW_ENABLE = 1 +}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL; + +typedef enum _RUART_WORD_LEN_SEL_ { + RUART_WLS_7BITS = 0, + RUART_WLS_8BITS = 1 +}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL; + +typedef enum _RUART_STOP_BITS_ { + RUART_STOP_BIT_1 = 0, + RUART_STOP_BIT_2 = 1 +}RUART_STOP_BITS, *PRUART_STOP_BITS; + +typedef enum _RUART_PARITY_CONTROL_ { + RUART_PARITY_DISABLE = 0, + RUART_PARITY_ENABLE = 1 +}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL; + +typedef enum _RUART_PARITY_TYPE_ { + RUART_ODD_PARITY = 0, + RUART_EVEN_PARITY = 1 +}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE; + +typedef enum _RUART_STICK_PARITY_CONTROL_ { + RUART_STICK_PARITY_DISABLE = 0, + RUART_STICK_PARITY_ENABLE = 1 +}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL; + +typedef enum _UART_INT_ID_ { + ModemStatus = 0, + TxFifoEmpty = 1, + ReceiverDataAvailable = 2, + ReceivLineStatus = 3, + TimeoutIndication = 6 +}UART_INT_ID, *PUART_INT_ID; + +typedef enum _HAL_UART_State_ +{ + HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet + HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use + HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration + HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX + HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX + HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX + HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout + HAL_UART_STATE_ERROR = 0x40 // UART Error +}HAL_UART_State, *PHAL_UART_State; + +typedef enum _HAL_UART_Status_ +{ + HAL_UART_STATUS_OK = 0x00, // Transfer OK + HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout + HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run + HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error + HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error + HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt + HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error + HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error +}HAL_UART_Status, *PHAL_UART_Status; + +u32 +HalRuartGetDebugValueRtl8195a( + IN VOID* Data, + IN u32 DbgSel + ); + +#if 0 +u32 +FindElementIndex( + u32 Element, + u32* Array + ); +#endif + +VOID +RuartResetRxFifoRtl8195a( + IN u8 UartIndex + ); +#if 0 +VOID +RuartBusDomainEnableRtl8195a( + IN u8 UartIndex + ); +#endif + +HAL_Status +HalRuartResetRxFifoRtl8195a( + IN VOID *Data + ); + +HAL_Status +HalRuartInitRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartDeInitRtl8195a( + IN VOID *Data ///< RUART Adapter + ); + +HAL_Status +HalRuartPutCRtl8195a( + IN VOID *Data, + IN u8 TxData + ); + +u32 +HalRuartSendRtl8195a( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length, + IN u32 Timeout + ); + +HAL_Status +HalRuartIntSendRtl8195a( + IN VOID *Data, // PHAL_RUART_ADAPTER + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send + ); + +HAL_Status +HalRuartDmaSendRtl8195a( + IN VOID *Data, // PHAL_RUART_ADAPTER + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send +); + +HAL_Status +HalRuartStopSendRtl8195a( + IN VOID *Data // PHAL_RUART_ADAPTER +); + +HAL_Status +HalRuartGetCRtl8195a( + IN VOID *Data, + OUT u8 *pRxByte + ); + +u32 +HalRuartRecvRtl8195a( + IN VOID *Data, + IN u8 *pRxData, + IN u32 Length, + IN u32 Timeout + ); + +HAL_Status +HalRuartIntRecvRtl8195a( + IN VOID *Data, ///< RUART Adapter + IN u8 *pRxData, ///< Rx buffer + IN u32 Length // buffer length + ); + +HAL_Status +HalRuartDmaRecvRtl8195a( + IN VOID *Data, ///< RUART Adapter + IN u8 *pRxData, ///< Rx buffer + IN u32 Length // buffer length + ); + +HAL_Status +HalRuartStopRecvRtl8195a( + IN VOID *Data // PHAL_RUART_ADAPTER +); + +u8 +HalRuartGetIMRRtl8195a( + IN VOID *Data + ); + +_LONG_CALL_ROM_ VOID +HalRuartSetIMRRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartDmaInitRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartRTSCtrlRtl8195a( + IN VOID *Data, + IN BOOLEAN RtsCtrl + ); + +VOID +HalRuartRegIrqRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartIntEnableRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartIntDisableRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartAdapterLoadDefRtl8195a( + IN VOID *pAdp, + IN u8 UartIdx +); + +VOID +HalRuartTxGdmaLoadDefRtl8195a( + IN VOID *pAdp, + IN VOID *pCfg +); + +VOID +HalRuartRxGdmaLoadDefRtl8195a( + IN VOID *pAdp, + IN VOID *pCfg +); + +_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02( + IN VOID *Data, // PHAL_RUART_ADAPTER + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send +); + +_LONG_CALL_ HAL_Status +HalRuartIntRecvRtl8195aV02( + IN VOID *Data, ///< RUART Adapter + IN u8 *pRxData, ///< Rx buffer + IN u32 Length // buffer length +); + +_LONG_CALL_ s32 +FindElementIndex_v02( + u32 Element, ///< RUART Baudrate + u32* Array, ///< Pre-defined Baudrate Array + u32 ElementNo +); + +_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data); + +// New added function 2015/04/20 +HAL_Status +HalRuartResetTxFifoRtl8195a( + IN VOID *Data ///< RUART Adapter + ); + +HAL_Status +HalRuartResetRxFifoRtl8195a_Patch( + IN VOID *Data ///< RUART Adapter +); + +HAL_Status +HalRuartResetTRxFifoRtl8195a( + IN VOID *Data ///< RUART Adapter +); + +HAL_Status +HalRuartSetBaudRateRtl8195a( + IN VOID *Data + ); + +HAL_Status +HalRuartEnableRtl8195a( + IN VOID *Data +); + +HAL_Status +HalRuartDisableRtl8195a( + IN VOID *Data +); + +HAL_Status +HalRuartFlowCtrlRtl8195a( + IN VOID *Data +); + +u32 +_UartTxDmaIrqHandle_Patch( + IN VOID *Data +); + +u32 +_UartRxDmaIrqHandle_Patch( + IN VOID *Data +); + +HAL_Status +HalRuartDmaSendRtl8195a_Patch( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length +); + +HAL_Status +HalRuartDmaRecvRtl8195a_Patch( + IN VOID *Data, + IN u8 *pRxData, + IN u32 Length +); + +HAL_Status +HalRuartMultiBlkDmaSendRtl8195a( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length +); + +HAL_Status +HalRuartMultiBlkDmaRecvRtl8195a( + IN VOID *Data, + IN u8 *pRxData, + IN u32 Length +); + +HAL_Status +RuartIsTimeout ( + u32 StartCount, + u32 TimeoutCnt +); + +HAL_Status +HalRuartStopRecvRtl8195a_Patch( + IN VOID *Data +); + +HAL_Status +HalRuartStopSendRtl8195a_Patch( + IN VOID *Data +); + +VOID +HalRuartEnterCriticalRtl8195a( + IN VOID *Data +); + +VOID +HalRuartExitCriticalRtl8195a( + IN VOID *Data +); + +#if CONFIG_CHIP_E_CUT +_LONG_CALL_ HAL_Status +HalRuartResetTxFifoRtl8195a_V04( + IN VOID *Data ///< RUART Adapter +); + +_LONG_CALL_ HAL_Status +HalRuartResetRxFifoRtl8195a_V04( + IN VOID *Data ///< RUART Adapter +); + +_LONG_CALL_ HAL_Status +HalRuartResetTRxFifoRtl8195a_V04( + IN VOID *Data ///< RUART Adapter +); + +_LONG_CALL_ HAL_Status +HalRuartSetBaudRateRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartInitRtl8195a_V04( + IN VOID *Data ///< RUART Adapter +); + +_LONG_CALL_ HAL_Status +HalRuartEnableRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartDisableRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartFlowCtrlRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ u32 +_UartTxDmaIrqHandle_V04( + IN VOID *Data +); + +_LONG_CALL_ u32 +_UartRxDmaIrqHandle_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartDmaSendRtl8195a_V04( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length +); + +_LONG_CALL_ HAL_Status +HalRuartDmaRecvRtl8195a_V04( + IN VOID *Data, + IN u8 *pRxData, + IN u32 Length +); + +_LONG_CALL_ HAL_Status +HalRuartMultiBlkDmaSendRtl8195a_V04( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length +); + +_LONG_CALL_ HAL_Status +HalRuartMultiBlkDmaRecvRtl8195a_V04( + IN VOID *Data, + IN u8 *pRxData, + IN u32 Length +); + +_LONG_CALL_ HAL_Status +HalRuartStopRecvRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartStopSendRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ VOID +HalRuartEnterCriticalRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ VOID +HalRuartExitCriticalRtl8195a_V04( + IN VOID *Data +); + +#endif // #if CONFIG_CHIP_E_CUT + +#ifdef CONFIG_MBED_ENABLED +// Interface to ROM functions +//extern __longcall void HalRuartAdapterLoadDefRtl8195a(UART_Handle *uart, uint8_t idx); +//extern __longcall void HalRuartDeInitRtl8195a(UART_Handle *uart); +//extern __longcall HAL_Status HalRuartDisableRtl8195a(UART_Handle *data); +//extern __longcall HAL_Status HalRuartEnableRtl8195a(UART_Handle *data); +//extern __longcall void HalRuartDmaInitRtl8195a(UART_Handle *data); +//extern __longcall void HalRuartTxGdmaLoadDefRtl8195a(UART_Handle *uart, RUART_DMA_Config *cfg); +//extern __longcall void HalRuartRxGdmaLoadDefRtl8195a(UART_Handle *uart, RUART_DMA_Config *cfg); +//extern __longcall HAL_Status HalRuartGetCRtl8195a(UART_Handle *uart, uint8_t *byte); +//extern __longcall HAL_Status HalRuartPutCRtl8195a(UART_Handle *uart, uint8_t byte); +//extern __longcall HAL_Status RuartLock(UART_Handle * uart); +//extern __longcall void RuartUnlock(UART_Handle * uart); +//extern __longcall void HalRuartSetIMRRtl8195a(UART_Handle *uart); +//extern __longcall uint8_t HalRuartGetIMRRtl8195a(UART_Handle *uart); +//extern __longcall uint32_t HalRuartSendRtl8195a(UART_Handle *, uint8_t *, uint32_t, uint32_t); +//extern __longcall HAL_Status HalRuartIntSendRtl8195a(UART_Handle *, uint8_t *, uint32_t); +//extern __longcall HAL_Status HalRuartIntRecvRtl8195a(UART_Handle *, uint8_t *, uint32_t); +//extern __longcall uint32_t HalRuartRecvRtl8195a(UART_Handle *, uint8_t *, uint32_t, uint32_t); +//extern __longcall void HalRuartRegIrqRtl8195a(UART_Handle *Data); +//extern __longcall void HalRuartIntEnableRtl8195a(UART_Handle *Data); +//extern __longcall void HalRuartIntDisableRtl8195a(UART_Handle *Data); +//extern __longcall uint32_t HalRuartGetDebugValueRtl8195a(HAL_RUART_ADAPTER *Data, uint32_t sel); +//extern __longcall void HalRuartRTSCtrlRtl8195a(UART_Handle *Data, bool val); +extern __longcall HAL_Status RuartIsTimeout(uint32_t StartCount, uint32_t TimeoutCnt); +#endif + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_wdt.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_wdt.h new file mode 100644 index 00000000000..edbedd2fea5 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_wdt.h @@ -0,0 +1,86 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2014 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_WDT_H_ +#define _RTL8195A_WDT_H_ + +#define WDGTIMERELY (10*1024) //us + +typedef struct _WDG_REG_ { + u16 WdgScalar; + u8 WdgEnByte; + u8 WdgClear:1; + u8 WdgCunLimit:4; + u8 Rsvd:1; + u8 WdgMode:1; + u8 WdgToISR:1; +}WDG_REG, *PWDG_REG; + +typedef struct _WDG_ADAPTER_ { + + WDG_REG Ctrl; + IRQ_HANDLE IrqHandle; + TIMER_ADAPTER WdgGTimer; + VOID (*UserCallback)(u32 callback_id); // User callback function + u32 callback_id; +}WDG_ADAPTER, *PWDG_ADAPTER; + +typedef enum _WDG_CNTLMT_ { + CNT1H = 0, + CNT3H = 1, + CNT7H = 2, + CNTFH = 3, + CNT1FH = 4, + CNT3FH = 5, + CNT7FH = 6, + CNTFFH = 7, + CNT1FFH = 8, + CNT3FFH = 9, + CNT7FFH = 10, + CNTFFFH = 11 +}WDG_CNTLMT, *PWDG_CNTLMT; + + +typedef enum _WDG_MODE_ { + INT_MODE = 0, + RESET_MODE = 1 +}WDG_MODE, *PWDG_MODE; + +extern VOID +WDGInitial( + IN u32 Period +); + +extern VOID +WDGIrqInitial( + VOID +); + +extern VOID +WDGIrqInitial( + VOID +); + +extern VOID +WDGStop( + VOID +); + +extern VOID +WDGRefresh( + VOID +); + +extern VOID +WDGIrqCallBackReg( + IN VOID *CallBack, + IN u32 Id +); + +#endif //_RTL8195A_WDT_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl_utility.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl_utility.h new file mode 100644 index 00000000000..6fa22ffbcdb --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl_utility.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL_UTILITY_H_ +#define __RTL_UTILITY_H_ + +VOID RtlMemcpy(VOID* dec, VOID* sour, u32 sz); +u32 RtlMemcmp(VOID *dst, VOID *src, u32 sz); +VOID RtlMemset(VOID *pbuf, u32 c, u32 sz); + +s8 * +RtlStrncpy( + IN s8 *dest, + IN const s8 *src, + IN SIZE_T count +); + +s8 * +RtlStrcpy( + IN s8 *dest, + IN const s8 *src +); + + +SIZE_T +RtlStrlen( + IN const s8 *s +); + + +SIZE_T +RtlStrnlen( + IN const s8 *s, + IN SIZE_T count +); + + +int +RtlStrcmp( + IN const s8 *cs, + IN const s8 *ct + +); + +int +RtlStrncmp( + IN const s8 *cs, + IN const s8 *ct, + IN SIZE_T count +); + +#endif + + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/system_8195a.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/system_8195a.h new file mode 100644 index 00000000000..a730aff7263 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/system_8195a.h @@ -0,0 +1,77 @@ +/**************************************************************************//** + * @file system_ARMCM3.h + * @brief CMSIS Device System Header File for + * ARMCM3 Device Series + * @version V1.08 + * @date 23. November 2012 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef _SYSTEM_8195A_H +#define _SYSTEM_8195A_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); +extern u32 SystemGetCpuClk(void); +extern u32 Rand2(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_8195A_H */ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/va_list.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/va_list.h new file mode 100644 index 00000000000..e3e8b826a1d --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/va_list.h @@ -0,0 +1,36 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _VA_LIST_H_ +#define _VA_LIST_H_ + +#include "basic_types.h" + +#ifndef va_arg + +typedef s32 acpi_native_int; + +#ifndef _VALIST +#define _VALIST +typedef char *va_list; +#endif /* _VALIST */ + +/* Storage alignment properties */ +#define _AUPBND (sizeof (acpi_native_int) - 1) +#define _ADNBND (sizeof (acpi_native_int) - 1) + +/* Variable argument list macro definitions */ +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (ap = (va_list) NULL) +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) + +#endif /* va_arg */ + +#endif //_VA_LIST_H_ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/objects.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/objects.h new file mode 100644 index 00000000000..61ec64ef616 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/objects.h @@ -0,0 +1,209 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_GPIO_EN +struct gpio_irq_s { + PinName pin; + uint32_t event; + HAL_GPIO_PIN hal_pin; + uint8_t hal_port_num; + uint8_t hal_pin_num; +}; + +typedef struct gpio_irq_s gpio_irq_t; + +struct gpio_s { + PinName pin; + PinMode mode; + PinDirection direction; + HAL_GPIO_PIN hal_pin; + uint8_t hal_port_num; + uint8_t hal_pin_num; +}; + +typedef struct gpio_s gpio_t; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + uint8_t *pin_def; +}; +#endif // end of "#ifdef CONFIG_GPIO_EN" + +#ifdef CONFIG_UART_EN +struct serial_s { + int index; + HAL_RUART_OP hal_uart_op; + HAL_RUART_ADAPTER hal_uart_adp; +#ifdef CONFIG_GDMA_EN + UART_DMA_CONFIG uart_gdma_cfg; + HAL_GDMA_ADAPTER uart_gdma_adp_tx; + HAL_GDMA_ADAPTER uart_gdma_adp_rx; + UART_DMA_MULTIBLK gdma_multiblk_list_tx; + UART_DMA_MULTIBLK gdma_multiblk_list_rx; +#endif + uint32_t tx_len; + uint32_t rx_len; +}; +#endif // end of "#ifdef CONFIG_UART_EN" + +struct log_uart_s { + HAL_LOG_UART_ADAPTER log_hal_uart; +}; + +#ifdef CONFIG_SPI_COM_EN + +#endif + +#ifdef CONFIG_PWM_EN +struct pwmout_s { + uint8_t pwm_idx; + uint8_t pin_sel; + uint32_t period; + uint32_t pulse; + HAL_PWM_ADAPTER pwm_hal_adp; +}; +#endif + +#ifdef CONFIG_I2C_EN +struct i2c_s { + SAL_I2C_MNGT_ADPT SalI2CMngtAdpt; + SAL_I2C_HND_PRIV SalI2CHndPriv; + HAL_I2C_INIT_DAT HalI2CInitData; + HAL_I2C_OP HalI2COp; + IRQ_HANDLE I2CIrqHandleDat; + HAL_GDMA_ADAPTER HalI2CTxGdmaAdpt; + HAL_GDMA_ADAPTER HalI2CRxGdmaAdpt; + HAL_GDMA_OP HalI2CGdmaOp; + IRQ_HANDLE I2CTxGdmaIrqHandleDat; + IRQ_HANDLE I2CRxGdmaIrqHandleDat; + SAL_I2C_USER_CB SalI2CUserCB; + SAL_I2C_USERCB_ADPT SalI2CUserCBAdpt[SAL_USER_CB_NUM]; + SAL_I2C_DMA_USER_DEF SalI2CDmaUserDef; +}; +#endif + + +struct flash_s +{ + SPIC_INIT_PARA SpicInitPara; + u32 Length; +}; + + +#ifdef CONFIG_ADC_EN +struct analogin_s { + SAL_ADC_MNGT_ADPT SalADCMngtAdpt; + SAL_ADC_HND_PRIV SalADCHndPriv; + HAL_ADC_INIT_DAT HalADCInitData; + HAL_ADC_OP HalADCOp; + IRQ_HANDLE ADCIrqHandleDat; + HAL_GDMA_ADAPTER HalADCGdmaAdpt; + HAL_GDMA_OP HalADCGdmaOp; + IRQ_HANDLE ADCGdmaIrqHandleDat; + SAL_ADC_USER_CB SalADCUserCB; + SAL_ADC_USERCB_ADPT SalADCUserCBAdpt[SAL_ADC_USER_CB_NUM]; +}; +#endif + +#if 0 +struct i2c_s { + I2C_Type *i2c; +}; + +struct spi_s { + SPI_Type *spi; +}; + +#endif + +#ifdef CONFIG_NFC_EN +struct nfctag_s { + NFC_ADAPTER NFCAdapter; + void *nfc_rd_cb; // read callback function + void *rd_cb_arg; + void *nfc_wr_cb; // write callback function + void *wr_cb_arg; + void *nfc_ev_cb; // event callback function + void *ev_cb_arg; + void *nfc_cache_rd_cb; // cache read callback function + void *cache_read_cb_arg; + unsigned int event_mask; + int pwr_status; +}; +#endif + +#ifdef CONFIG_TIMER_EN +struct gtimer_s { + TIMER_ADAPTER hal_gtimer_adp; + void *handler; + u32 hid; + u8 timer_id; + u8 is_periodcal; +}; +#endif + +#ifdef CONFIG_I2S_EN +struct i2s_s { + HAL_I2S_ADAPTER I2SAdapter; + HAL_I2S_INIT_DAT InitDat; + u8 sampling_rate; + u8 channel_num; + u8 word_length; + u8 direction; +}; + +#endif + +#ifdef CONFIG_DAC_EN +/** \file objects.h + * \brief A Documented file. + * + * A documented file. +*/ + +/** \struct dac_s objects.h "rtl8195a/objects.h" + * \brief This is a dac_s structure. + * + * For analogout APIs, a pointer to dac_s is used as an input paras. + * A DAC initial data structure is the major element of dac_s. + */ +struct dac_s { + HAL_DAC_INIT_DAT DACpara; +}; +#endif + +struct trng_s{ + uint32_t pin; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/analogin_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/analogin_api.c new file mode 100644 index 00000000000..2382513a3eb --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/analogin_api.c @@ -0,0 +1,193 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "objects.h" +#include "PinNames.h" +#include "hal_adc.h" +#include "analogin_api.h" + + + +#if CONFIG_ADC_EN +#include "pinmap.h" + + +extern u32 ConfigDebugErr; +extern u32 ConfigDebuginfo; + + +void analogin_init (analogin_t *obj, PinName pin){ + + uint32_t adc_idx; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PSAL_ADC_USERCB_ADPT pSalADCUserCBAdpt = NULL; + PSAL_ADC_HND pSalADCHND = NULL; + + HAL_ADC_INIT_DAT HalADCInitDataTmp; + PHAL_ADC_INIT_DAT pHalADCInitDataTmp = &HalADCInitDataTmp; + + /* To backup user config first */ + _memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT)); + + _memset(obj, 0x00, sizeof(analogin_t)); + + ConfigDebugErr &= (~(_DBG_ADC_|_DBG_GDMA_)); + ConfigDebugInfo&= (~(_DBG_ADC_|_DBG_GDMA_)); + + adc_idx = pin & 0x0F; + + /* Get I2C device handler */ + pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); + pSalADCUserCBAdpt = (PSAL_ADC_USERCB_ADPT)&(obj->SalADCUserCBAdpt); + + /*To assign the rest pointers*/ + pSalADCMngtAdpt->pSalHndPriv = &(obj->SalADCHndPriv); + pSalADCMngtAdpt->pSalHndPriv->ppSalADCHnd = (void**)&(pSalADCMngtAdpt->pSalHndPriv); + + /* To assign the default (ROM) HAL OP initialization function */ + pSalADCMngtAdpt->pHalOpInit = &HalADCOpInit; + + /* To assign the default (ROM) HAL GDMA OP initialization function */ + pSalADCMngtAdpt->pHalGdmaOpInit = &HalGdmaOpInit; + + /* To assign the default (ROM) SAL interrupt function */ + pSalADCMngtAdpt->pSalIrqFunc = &ADCISRHandle; + + /* To assign the default (ROM) SAL DMA TX interrupt function */ + pSalADCMngtAdpt->pSalDMAIrqFunc = &ADCGDMAISRHandle; + + /* To backup user config first */ + //_memcpy(pHalADCInitDataTmp, &(obj->HalADCInitData), sizeof(HAL_ADC_INIT_DAT)); + + + pSalADCMngtAdpt->pHalInitDat = &(obj->HalADCInitData); + pSalADCMngtAdpt->pHalOp = &(obj->HalADCOp); + pSalADCMngtAdpt->pIrqHnd = &(obj->ADCIrqHandleDat); + pSalADCMngtAdpt->pHalGdmaAdp = &(obj->HalADCGdmaAdpt); + pSalADCMngtAdpt->pHalGdmaOp = &(obj->HalADCGdmaOp); + pSalADCMngtAdpt->pIrqGdmaHnd = &(obj->ADCGdmaIrqHandleDat); + pSalADCMngtAdpt->pUserCB = &(obj->SalADCUserCB); + + /* Assign the private SAL handle to public SAL handle */ + pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); + + /* Assign the internal HAL initial data pointer to the SAL handle */ + pSalADCHND->pInitDat = pSalADCMngtAdpt->pHalInitDat; + + /* Assign the internal user callback pointer to the SAL handle */ + pSalADCHND->pUserCB = pSalADCMngtAdpt->pUserCB; + + /*To assign user callback pointers*/ + pSalADCMngtAdpt->pUserCB->pTXCB = pSalADCUserCBAdpt; + pSalADCMngtAdpt->pUserCB->pTXCCB = (pSalADCUserCBAdpt+1); + pSalADCMngtAdpt->pUserCB->pRXCB = (pSalADCUserCBAdpt+2); + pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+3); + pSalADCMngtAdpt->pUserCB->pRDREQCB = (pSalADCUserCBAdpt+4); + pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+5); + pSalADCMngtAdpt->pUserCB->pDMATXCB = (pSalADCUserCBAdpt+6); + pSalADCMngtAdpt->pUserCB->pDMATXCCB = (pSalADCUserCBAdpt+7); + pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+8); + pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+9); + + /* Set ADC Device Number */ + pSalADCHND->DevNum = adc_idx; + + /* Load ADC default value */ + RtkADCLoadDefault(pSalADCHND); + + /* Assign ADC Pin Mux */ + pSalADCHND->PinMux = 0; + pSalADCHND->OpType = ADC_RDREG_TYPE; + + /* Load user setting */ + if ((pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_LITTLE) || (pHalADCInitDataTmp->ADCEndian == ADC_DATA_ENDIAN_BIG)) { + DBG_8195A("K\n"); + pSalADCHND->pInitDat->ADCEndian = pHalADCInitDataTmp->ADCEndian; + } + + if ((pHalADCInitDataTmp->ADCAudioEn != ADC_FEATURE_DISABLED) && (pHalADCInitDataTmp->ADCAudioEn < 2)) { + DBG_8195A("O\n"); + pSalADCHND->pInitDat->ADCAudioEn = pHalADCInitDataTmp->ADCAudioEn; + } + + /* Init ADC now */ + pSalADCHND->pInitDat->ADCBurstSz = 8; + pSalADCHND->pInitDat->ADCOneShotTD = 8; + RtkADCInit(pSalADCHND); +} + +float analogin_read(analogin_t *obj){ + float value; + uint32_t AnaloginTmp[2] = {0,0}; + uint32_t AnaloginDatMsk = 0xFFFF; + uint8_t AnaloginIdx = 0; + uint32_t AnalogDat = 0; + uint32_t Offset = 0x2C00; + uint32_t AnalogDatFull = 0xAA00; + + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PSAL_ADC_HND pSalADCHND = NULL; + + pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); + pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); + AnaloginIdx = pSalADCHND->DevNum; + RtkADCReceiveBuf(pSalADCHND,&AnaloginTmp[0]); + + AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01)))); + AnalogDat = AnaloginTmp[(AnaloginIdx/2)]; + AnalogDat = (AnalogDat & AnaloginDatMsk); + AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01)))); + AnalogDat -= Offset; + + value = (float)(AnalogDat) / (float)(AnalogDatFull); + return (float)value; +} + +uint16_t analogin_read_u16(analogin_t *obj){ + uint32_t AnaloginTmp[2] = {0,0}; + uint32_t AnaloginDatMsk = 0xFFFF; + uint8_t AnaloginIdx = 0; + uint32_t AnalogDat = 0; + + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PSAL_ADC_HND pSalADCHND = NULL; + + pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); + pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); + AnaloginIdx = pSalADCHND->DevNum; + RtkADCRxManualRotate(pSalADCHND,&AnaloginTmp[0]); + + AnaloginDatMsk = (u32)(AnaloginDatMsk<<((u32)(16*(AnaloginIdx&0x01)))); + AnalogDat = AnaloginTmp[(AnaloginIdx/2)]; + AnalogDat = (AnalogDat & AnaloginDatMsk); + AnalogDat = (AnalogDat>>((u32)(16*(AnaloginIdx&0x01)))); + + return (uint16_t)AnalogDat; + +} + + +void analogin_deinit(analogin_t *obj){ + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PSAL_ADC_HND pSalADCHND = NULL; + + pSalADCMngtAdpt = &(obj->SalADCMngtAdpt); + pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); + + /* To deinit analogin */ + RtkADCDeInit(pSalADCHND); +} +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/analogin_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/analogin_ext.h new file mode 100644 index 00000000000..83846aafd45 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/analogin_ext.h @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ANALOGIN_EXT_H +#define MBED_ANALOGIN_EXT_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern void analogin_deinit(analogin_t *obj); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/analogout_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/analogout_api.c new file mode 100644 index 00000000000..d65051607bb --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/analogout_api.c @@ -0,0 +1,182 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "objects.h" +#include "analogout_api.h" + + +#if CONFIG_DAC_EN + +#include "cmsis.h" +#include "pinmap.h" +#include + +#define DAC_POSITIVE_FULL_SCALE 0x7E0 +#define DAC_NEGATIVE_FULL_SCALE 0x820 + + +/** \brief analogout_init:\n + * to initialize DAC + * + * This function is mainly to initialize a DAC channel. + * \para dac_t *: obj + * \para PinName: pin + */ +void analogout_init(dac_t *obj, PinName pin) { + uint32_t dac_idx; + uint32_t DacTemp; + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); + dac_idx = pin & 0x0F; + + /* Assign dac index */ + pHalDacInitData->DACIdx = dac_idx; + + pHalDacInitData->DACEn = DAC_DISABLE; + pHalDacInitData->DACDataRate = DAC_DATA_RATE_250K; + pHalDacInitData->DACEndian = DAC_DATA_ENDIAN_LITTLE; + pHalDacInitData->DACBurstSz = 10; + pHalDacInitData->DACDbgSel = DAC_DBG_SEL_DISABLE; + pHalDacInitData->DACDscDbgSel = DAC_DSC_DBG_SEL_DISABLE; + pHalDacInitData->DACBPDsc = DAC_BYPASS_DSC_SEL_DISABLE; + pHalDacInitData->DACDeltaSig = 0; + pHalDacInitData->DACAnaCtrl0 = 0; + pHalDacInitData->DACAnaCtrl1 = 0; + pHalDacInitData->DACIntrMSK = DAC_FEATURE_DISABLED; + + /* DAC Function and Clock Enable*/ + HalDACPinMuxInit(pHalDacInitData); + + HalDACInit8195a(pHalDacInitData); + + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, + (BIT_DAC_FIFO_FULL_EN | + BIT_DAC_FIFO_OVERFLOW_EN | + BIT_DAC_FIFO_STOP_EN | + BIT_DAC__WRITE_ERROR_EN | + BIT_DAC_DSC_OVERFLOW0_EN | + BIT_DAC_DSC_OVERFLOW1_EN)); + DBG_DAC_INFO("INTR MSK:%x\n", HAL_DAC_READ32(pHalDacInitData->DACIdx,REG_DAC_INTR_CTRL)); + + DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1); + DacTemp |= (BIT31); + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1, DacTemp); + DBG_DAC_INFO("REG_DAC_ANAPAR_DA1:%08x\n",HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_ANAPAR_DA1)); + + DacTemp = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL); + DacTemp |= BIT3; + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL, DacTemp); + DBG_DAC_INFO("REG_DAC_CTRL:%08x\n",DacTemp); + + pHalDacInitData->DACEn = DAC_ENABLE; + HalDACEnableRtl8195a(pHalDacInitData); +} + +/** \brief analogout_free:\n + * to free DAC + * + * This function is mainly to free a DAC channel. + * \para dac_t *: obj + */ +void analogout_free(dac_t *obj) { + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); + + HalDACPinMuxDeInit(pHalDacInitData); + + pHalDacInitData->DACEn = DAC_DISABLE; + HalDACEnableRtl8195a(pHalDacInitData); +} + +/** \brief analogout_write:\n + * to execute analogout_write + * + * This function is mainly to execute analog output and the value is a ratio. + * The upper/lower bound of DAC register input value is defined by + * DAC_XXXXX_FULL_SCALE. The parameter "value" of this function should be + * transfered to register value. + * + * \para dac_t * : obj + * \para float : value + */ +void analogout_write(dac_t *obj, float value) { + uint32_t dactemp; + uint16_t dacnegtemp; + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); + + if (value < 0.0f) { + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, 0x00000000); + } else if (value > 1.0f) { + dactemp = (DAC_POSITIVE_FULL_SCALE<<16) | DAC_POSITIVE_FULL_SCALE; + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); + } else { + if (value >= 0.5) { + dactemp = (uint32_t)((((value-0.5)/0.5) * (2^12)) * DAC_POSITIVE_FULL_SCALE); + dactemp = dactemp / (2^12); + dactemp = (dactemp<<16) | dactemp; + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); + } else { + dacnegtemp = (DAC_NEGATIVE_FULL_SCALE & 0x7FF); + dacnegtemp = ((~dacnegtemp) + 1) & 0x7FF; + dactemp = (uint32_t)(((0.5-value)/0.5) * (2^12) * dacnegtemp); + dactemp = dactemp / (2^12); + dactemp = 0x1000 - dactemp; //change to 2's complement + dactemp = (dactemp<<16) | dactemp; + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); + } + } +} + +/** \brief analogout_write_u16:\n + * to execute analogout_write_u16 + * + * The register value of DAC input is a format of 2's complement. + * The most maximum value of positive value drives DAC to output a voltage about 3.3V. + * The most mimimum value of negative value drives DAC to output a voltage about 0. + * And the middle value of 0x000 will drive DAC to output a voltage of half of max voltage. + * + * \para dac_t * : obj + * \para float : value + */ +void analogout_write_u16(dac_t *obj, uint16_t value) { + uint32_t dactemp; + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)&(obj->DACpara); + + /* To give a two point data */ + dactemp = (value << 16) | value; + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC0_FIFO_WR, dactemp); +} + +/** \brief analogout_read_u16:\n + * to read back analog output value in float format + * + * This function is NOT available in rtl8195a hardware design. + * It always returns a fixed value of 0.0; + * \para dac_t * : obj + */ +float analogout_read(dac_t *obj) { + return (float)0.0; +} + +/** \brief analogout_read_u16:\n + * to read back analog output register value + * + * This function is NOT available in rtl8195a hardware design. + * It always returns a fixed value of 0xFFFF; + * \para dac_t * : obj + */ +uint16_t analogout_read_u16(dac_t *obj) { + return (uint16_t)0xFFFF; +} + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c new file mode 100644 index 00000000000..5de3e756c98 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c @@ -0,0 +1,582 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "objects.h" +#include "PinNames.h" + + +#include "pinmap.h" + +#include "rtl8195a.h" +#include "hal_spi_flash.h" +#include "hal_platform.h" +#include "rtl8195a_spi_flash.h" +#include "hal_api.h" +#include "flash_api.h" + +extern u32 ConfigDebugInfo; +extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO]; + +_LONG_CALL_ +extern VOID SpicWaitBusyDoneRtl8195A(VOID); + +static int isinit = 0; +static flash_t flashobj; + +static void flash_init(flash_t * obj); +static void flash_turnon(); +/** + * global data structure + */ +//flash_t flash; + +/** + * @brief Control the flash chip write protect enable/disable + * @param protect: 1/0: protect/unprotect + * @retval none + */ +void flash_write_protect(flash_t *obj, uint32_t protect) +{ + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + SpicWriteProtectFlashRtl8195A(protect); + SpicDisableRtl8195A(); +} + +/** + * @brief Init Flash + * @param obj: address of the flash object + * @retval none + */ +void flash_init(flash_t *obj) +{ + //SPIC_INIT_PARA spic_init_para; + + // Init SPI Flash Controller +// DBG_8195A("Initial Spi Flash Controller\n"); + //SPI_FLASH_PIN_FCTRL(ON); + + if (!SpicFlashInitRtl8195A(SpicOneBitMode)){ + + DBG_8195A("SPI Init Fail!!!!!!\n"); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3)|0xf); + } + else { + isinit = 1; + } + flashobj.SpicInitPara.flashtype = SpicInitParaAllClk[0][0].flashtype; + + //DBG_8195A("Flash ID is = %x %x %x \n",SpicInitParaAllClk[0][0].id[0],SpicInitParaAllClk[0][0].id[1],SpicInitParaAllClk[0][0].id[2]); + +} +void flash_turnon() +{ + SPI_FLASH_PIN_FCTRL(ON); + SpicWaitBusyDoneRtl8195A(); +} + +/** + * @brief Erase flash sector + * @param address: Specifies the starting address to be erased. + * @retval none + */ +void flash_erase_sector(flash_t *obj, uint32_t address) +{ + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + SpicSectorEraseFlashRtl8195A(SPI_FLASH_BASE + address); + SpicDisableRtl8195A(); +} + +void flash_erase_block(flash_t *obj, uint32_t address) +{ + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + SpicBlockEraseFlashRtl8195A(SPI_FLASH_BASE + address); + SpicDisableRtl8195A(); +} + + +/** + * @brief Read a word from specified address + * @param obj: Specifies the parameter of flash object. + * @param address: Specifies the address to be read. + * @param data: Specified the address to save the readback data. + * @retval status: Success:1 or Failure: Others. + */ +int flash_read_word(flash_t *obj, uint32_t address, uint32_t * data) +{ + + flash_turnon(); + if(isinit == 0) + flash_init(&flashobj); + // Wait flash busy done (wip=0) + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + * data = HAL_READ32(SPI_FLASH_BASE, address); + SpicDisableRtl8195A(); + + return 1; +} + +/** + * @brief Write a word to specified address + * @param obj: Specifies the parameter of flash object. + * @param address: Specifies the address to be programmed. + * @param data: Specified the data to be programmed. + * @retval status: Success:1 or Failure: Others. + */ +int flash_write_word(flash_t *obj, uint32_t address, uint32_t data) +{ + u8 flashtype = 0; + + flash_turnon(); + if(isinit == 0) + flash_init(&flashobj); + + + flashtype = flashobj.SpicInitPara.flashtype; + + //Write word + HAL_WRITE32(SPI_FLASH_BASE, address, data); + + // Wait spic busy done + SpicWaitBusyDoneRtl8195A(); + + // Wait flash busy done (wip=0) + if(flashtype == FLASH_MICRON){ + SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); + } + else + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + SpicDisableRtl8195A(); + return 1; +} + + +/** + * @brief Read a stream of data from specified address + * @param obj: Specifies the parameter of flash object. + * @param address: Specifies the address to be read. + * @param len: Specifies the length of the data to read. + * @param data: Specified the address to save the readback data. + * @retval status: Success:1 or Failure: Others. + */ +int flash_stream_read(flash_t *obj, uint32_t address, uint32_t len, uint8_t * data) +{ + u32 offset_to_align; + u32 i; + u32 read_word; + uint8_t *ptr; + uint8_t *pbuf; + + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + + // Wait flash busy done (wip=0) + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + offset_to_align = address & 0x03; + pbuf = data; + if (offset_to_align != 0) { + // the start address is not 4-bytes aligned + read_word = HAL_READ32(SPI_FLASH_BASE, (address - offset_to_align)); + ptr = (uint8_t*)&read_word + offset_to_align; + offset_to_align = 4 - offset_to_align; + for (i=0;i> 2) + 1) << 2; // address = next 4-bytes aligned + + ptr = (uint8_t*)&read_word; + if ((u32)pbuf & 0x03) { + while (len >= 4) { + read_word = HAL_READ32(SPI_FLASH_BASE, address); + for (i=0;i<4;i++) { + *pbuf = *(ptr+i); + pbuf++; + } + address += 4; + len -= 4; + } + } + else { + while (len >= 4) { + *((u32 *)pbuf) = HAL_READ32(SPI_FLASH_BASE, address); + pbuf += 4; + address += 4; + len -= 4; + } + } + + if (len > 0) { + read_word = HAL_READ32(SPI_FLASH_BASE, address); + for (i=0;i> 2) + 1) << 2; // address = next 4-bytes aligned + + if ((u32)pbuf & 0x03) { + while (len >= 4) { + write_word = (u32)(*pbuf) | ((u32)(*(pbuf+1)) << 8) | ((u32)(*(pbuf+2)) << 16) | ((u32)(*(pbuf+3)) << 24); + //Write word + HAL_WRITE32(SPI_FLASH_BASE, address, write_word); + // Wait spic busy done + SpicWaitBusyDoneRtl8195A(); + // Wait flash busy done (wip=0) + if(flashtype == FLASH_MICRON){ + SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); + } + else + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + pbuf += 4; + address += 4; + len -= 4; + } + } + else { + while (len >= 4) { + //Write word + HAL_WRITE32(SPI_FLASH_BASE, address, (u32)*((u32 *)pbuf)); + // Wait spic busy done + SpicWaitBusyDoneRtl8195A(); + // Wait flash busy done (wip=0) + if(flashtype == FLASH_MICRON){ + SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); + } + else + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + pbuf += 4; + address += 4; + len -= 4; + } + } + + if (len > 0) { + write_word = HAL_READ32(SPI_FLASH_BASE, address); + ptr = (uint8_t*)&write_word; + for (i=0;i= PageSize) ||((Length + OccuSize) >= PageSize)) + ProgramSize = PageSize - OccuSize; + else + ProgramSize = Length; + + flashobj.Length = Length; + while(Length > 0){ + if(OccuSize){ + SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length)); + // Wait spic busy done + SpicWaitBusyDoneRtl8195A(); + // Wait flash busy done (wip=0) + if(flashtype == FLASH_MICRON){ + SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); + } + else + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + address += ProgramSize; + data+= ProgramSize; + Length -= ProgramSize; + OccuSize = 0; + } + else{ + while((flashobj.Length) >= PageSize){ + SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length)); + // Wait spic busy done + SpicWaitBusyDoneRtl8195A(); + // Wait flash busy done (wip=0) + if(flashtype == FLASH_MICRON){ + SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); + } + else + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + address += PageSize; + data+=PageSize; + Length -= PageSize; + } + flashobj.Length = Length; + if((flashobj.Length) > 0){ + SpicUserProgramRtl8195A(data, flashobj.SpicInitPara, address, &(flashobj.Length)); + // Wait spic busy done + SpicWaitBusyDoneRtl8195A(); + // Wait flash busy done (wip=0) + if(flashtype == FLASH_MICRON){ + SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara); + } + else + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + + break; + } + } + flashobj.Length = Length; + } + + SpicDisableRtl8195A(); + return 1; + +} +/** + * @brief Read a stream of data from specified address + * @param obj: Specifies the parameter of flash object. + * @param address: Specifies the address to be read. + * @param len: Specifies the length of the data to read. + * @param data: Specified the address to save the readback data. + * @retval status: Success:1 or Failure: Others. + */ + +int flash_burst_read(flash_t *obj, uint32_t address, uint32_t Length, uint8_t * data) +{ + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + // Wait flash busy done (wip=0) + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + SpicUserReadRtl8195A(Length, address, data,SpicOneBitMode); + SpicDisableRtl8195A(); + return 1; +} + +int flash_get_status(flash_t *obj) +{ + u8 Status = 0; + + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + Status = SpicGetFlashStatusRefinedRtl8195A(flashobj.SpicInitPara); + + SpicDisableRtl8195A(); + return Status; +} + +/* +Function Description: +Please refer to the datatsheet of flash for more details of the content of status register. +The block protected area and the corresponding control bits are provided in the flash datasheet. + +* @brief Set Status register to enable desired operation +* @param obj: Specifies the parameter of flash object. +* @param data: Specifies which bit users like to set + ex: if users want to set the third bit, data = 0x8. + +*/ +int flash_set_status(flash_t *obj, uint32_t data) +{ + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + SpicSetFlashStatusRefinedRtl8195A(data, flashobj.SpicInitPara); + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + DBG_8195A("Status Register After Setting= %x\n", flash_get_status(&flashobj)); + SpicDisableRtl8195A(); + return 1; +} + +/* +Function Description: +This function aims to reset the status register, please make sure the operation is appropriate. +*/ +void flash_reset_status(flash_t *obj) +{ + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + SpicSetFlashStatusRefinedRtl8195A(0, flashobj.SpicInitPara); + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + SpicDisableRtl8195A(); +} +/* +Function Description: +This function is only for Micron 512Mbit flash to access beyond 128Mbit by switching between four 128 Mbit area. +Please refer to flash datasheet for more information about memory mapping. +*/ + +int flash_set_extend_addr(flash_t *obj, uint32_t data) +{ + flash_turnon(); + + if(isinit == 0) + flash_init(&flashobj); + + SpicSetExtendAddrRtl8195A(data, flashobj.SpicInitPara); + SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara); + DBG_8195A("Extended Address Register After Setting= %x\n", flash_get_extend_addr(&flashobj)); + SpicDisableRtl8195A(); + return 1; +} + +int flash_get_extend_addr(flash_t *obj) +{ + u8 Status = 0; + + flash_turnon(); + if(isinit == 0) + flash_init(&flashobj); + Status = SpicGetExtendAddrRtl8195A(flashobj.SpicInitPara); + + SpicDisableRtl8195A(); + return Status; + +} + + diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.h new file mode 100644 index 00000000000..2f0589ddcf3 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_EXT_FLASH_API_EXT_H +#define MBED_EXT_FLASH_API_EXT_H + +#include "device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct flash_s flash_t; + +/** + * global data structure + */ +extern flash_t flash; + +enum { + FLASH_COMPLETE = 0, + FLASH_ERROR_2 = 1, +}; + +//void flash_init (flash_t *obj); +void flash_erase_sector (flash_t *obj, uint32_t address); +void flash_erase_block(flash_t * obj, uint32_t address); +int flash_read_word (flash_t *obj, uint32_t address, uint32_t * data); +int flash_write_word (flash_t *obj, uint32_t address, uint32_t data); +int flash_stream_read (flash_t *obj, uint32_t address, uint32_t len, uint8_t * data); +int flash_stream_write (flash_t *obj, uint32_t address, uint32_t len, uint8_t * data); +void flash_write_protect (flash_t *obj, uint32_t protect); +int flash_get_status(flash_t * obj); +int flash_set_status(flash_t * obj, uint32_t data); +void flash_reset_status(flash_t * obj); +int flash_burst_write(flash_t * obj, uint32_t address, uint32_t Length, uint8_t * data); +int flash_burst_read(flash_t * obj, uint32_t address, uint32_t Length, uint8_t * data); +int flash_set_extend_addr(flash_t * obj, uint32_t data); +int flash_get_extend_addr(flash_t * obj); + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/gpio_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/gpio_api.c new file mode 100644 index 00000000000..a41226e0d8a --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/gpio_api.c @@ -0,0 +1,198 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "objects.h" +#include "pinmap.h" + +#if CONFIG_GPIO_EN + +#include "gpio_api.h" + +// convert Mbed pin mode to HAL Pin Mode +const u8 GPIO_InPinMode[] = { + DIN_PULL_NONE, // PullNone + DIN_PULL_HIGH, // PullUp + DIN_PULL_LOW, // PullDown + DIN_PULL_NONE // OpenDrain +}; + +const u8 GPIO_SWPORT_DR_TBL[] = { + GPIO_PORTA_DR, + GPIO_PORTB_DR, + GPIO_PORTC_DR +}; + +const u8 GPIO_EXT_PORT_TBL[] = { + GPIO_EXT_PORTA, + GPIO_EXT_PORTB, + GPIO_EXT_PORTC +}; + +const u8 GPIO_SWPORT_DDR_TBL[] = { + GPIO_PORTA_DDR, + GPIO_PORTB_DDR, + GPIO_PORTC_DDR +}; + +void gpio_set_hal_pin_mode(gpio_t *obj) +{ + uint32_t mode; + + mode = obj->mode; + if (obj->direction == PIN_OUTPUT) { + if (mode == OpenDrain) { + obj->hal_pin.pin_mode = DOUT_OPEN_DRAIN; + } else { + obj->hal_pin.pin_mode = DOUT_PUSH_PULL; + } + } else { + if (mode < 4) { + obj->hal_pin.pin_mode = GPIO_InPinMode[mode]; + } else { + obj->hal_pin.pin_mode = DIN_PULL_NONE; + } + } +} + +uint32_t gpio_set(PinName pin) +{ + u32 ip_pin; + + DBG_ASSERT(pin != (PinName)NC); + pin_function(pin, 0); + ip_pin = HAL_GPIO_GetPinName((u32)pin); + + return ip_pin; +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + uint32_t pin_name; + + if (pin == (PinName)NC) + return; + + obj->pin = pin; + obj->mode = PullNone; + obj->direction = PIN_INPUT; + pin_name = gpio_set(pin); // get the IP pin name + obj->hal_pin.pin_name = pin_name; + obj->hal_pin.pin_mode = DIN_PULL_NONE; + obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name); + obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name); + HAL_GPIO_Init(&obj->hal_pin); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + obj->mode = mode; + gpio_set_hal_pin_mode(obj); + HAL_GPIO_Init(&obj->hal_pin); +} + +// Initial the Pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) { + obj->direction = direction; + gpio_set_hal_pin_mode(obj); + HAL_GPIO_Init(&obj->hal_pin); +} + +// Change the pin direction directly +void gpio_change_dir(gpio_t *obj, PinDirection direction) { + uint32_t reg_value; + uint8_t port_num; + uint8_t pin_num; + + obj->direction = direction; + gpio_set_hal_pin_mode(obj); + port_num = obj->hal_port_num; + pin_num = obj->hal_pin_num; + + reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num]); + if (direction) { + // Out + reg_value |= (1 << pin_num); + } else { + // In + reg_value &= ~(1 << pin_num); + } + HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DDR_TBL[port_num], reg_value); +} + +void gpio_write(gpio_t *obj, int value) +{ + HAL_GPIO_PIN *hal_pin=&obj->hal_pin; + volatile uint32_t reg_value; + uint8_t port_num; + uint8_t pin_num; + + if (hal_pin->pin_mode != DOUT_OPEN_DRAIN) { + port_num = obj->hal_port_num; + pin_num = obj->hal_pin_num; + + reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]); + reg_value &= ~(1 << pin_num); + reg_value |= ((value&0x01)<< pin_num); + HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value); + } else { + HAL_GPIO_WritePin(&obj->hal_pin, value); + } +} + +int gpio_read(gpio_t *obj) { + volatile uint32_t reg_value; + uint8_t port_num; + uint8_t pin_num; + HAL_GPIO_PIN_MODE pin_mode; + + port_num = obj->hal_port_num; + pin_num = obj->hal_pin_num; + pin_mode = obj->hal_pin.pin_mode; + + reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_EXT_PORT_TBL[port_num]); + if (pin_mode != DOUT_OPEN_DRAIN) { + return ((reg_value >> pin_num) & 0x01); + } else { + return (!((reg_value >> pin_num) & 0x01)); + } +} + +// This API only works for non-Open-Drain pin +void gpio_direct_write(gpio_t *obj, BOOL value) +{ + uint8_t port_num; + uint8_t pin_num; + uint32_t reg_value; + + port_num = obj->hal_port_num; + pin_num = obj->hal_pin_num; + + reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num]); + reg_value &= ~(1 << pin_num); + reg_value |= (value<< pin_num); + HAL_WRITE32(GPIO_REG_BASE, GPIO_SWPORT_DR_TBL[port_num], reg_value); +} + +void gpio_pull_ctrl(gpio_t *obj, PinMode pull_type) +{ + HAL_GPIO_PullCtrl((u32) obj->pin, (u32)pull_type); +} + + +void gpio_deinit(gpio_t *obj) { + HAL_GPIO_DeInit(&obj->hal_pin); +} + +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/gpio_irq_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/gpio_irq_api.c new file mode 100644 index 00000000000..7578f6afcf9 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/gpio_irq_api.c @@ -0,0 +1,146 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "objects.h" +#include "pinmap.h" + +#if CONFIG_GPIO_EN +#include "gpio_irq_api.h" + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint32_t pin_name; + + if (pin == NC) return -1; + + obj->pin = pin; + pin_name = HAL_GPIO_GetPinName((u32)pin);; // get the IP pin name + obj->hal_pin.pin_name = pin_name; + obj->hal_pin.pin_mode = INT_FALLING; // default use Falling trigger + obj->hal_port_num = HAL_GPIO_GET_PORT_BY_NAME(pin_name); + obj->hal_pin_num = HAL_GPIO_GET_PIN_BY_NAME(pin_name); + HAL_GPIO_Irq_Init(&obj->hal_pin); + HAL_GPIO_UserRegIrq(&obj->hal_pin, (VOID*) handler, (VOID*) id); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + HAL_GPIO_UserUnRegIrq(&obj->hal_pin); + HAL_GPIO_DeInit(&obj->hal_pin); +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + switch((uint32_t)event) { + case IRQ_RISE: + obj->hal_pin.pin_mode = INT_RISING; + break; + + case IRQ_FALL: + obj->hal_pin.pin_mode = INT_FALLING; + break; + +#ifndef CONFIG_MBED_ENABLED + case IRQ_LOW: + obj->hal_pin.pin_mode = INT_LOW; + break; + + case IRQ_HIGH: + obj->hal_pin.pin_mode = INT_HIGH; + break; +#endif + + case IRQ_NONE: + break; + + default: + break; + } + HAL_GPIO_Init_8195a(&obj->hal_pin); + + HAL_GPIO_IntCtrl(&obj->hal_pin, enable); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + HAL_GPIO_UnMaskIrq(&obj->hal_pin); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + HAL_GPIO_MaskIrq(&obj->hal_pin); +} +#ifndef CONFIG_MBED_ENABLED +void gpio_irq_deinit(gpio_irq_t *obj) +{ + HAL_GPIO_DeInit(&obj->hal_pin); +} + +void gpio_irq_pull_ctrl(gpio_irq_t *obj, PinMode pull_type) +{ + HAL_GPIO_PullCtrl((u32) obj->pin, (u32)pull_type); +} + +void gpio_irq_set_event(gpio_irq_t *obj, gpio_irq_event event) +{ + uint32_t reg_value; + uint32_t level_edge; + uint32_t polarity; + uint8_t pin_num; + + pin_num = obj->hal_pin_num & 0x1f; // Max 31 + + switch (event) { + case IRQ_LOW: + level_edge = 0; // level trigger + polarity = 0; // active low + break; + + case IRQ_HIGH: + level_edge = 0; // level trigger + polarity = 1; // active high + break; + + case IRQ_FALL: + level_edge = 1; // edge trigger + polarity = 0; // active low + break; + + case IRQ_RISE: + level_edge = 1; // edge trigger + polarity = 1; // active high + break; + + default: + DBG_GPIO_ERR("Unknow Interrupt Trigger Type(%d)\n", event); + return; + } + + // Config Level or Edge trigger + reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_INT_TYPE); + reg_value &= ~(1 << pin_num); + reg_value |= (level_edge << pin_num); + HAL_WRITE32(GPIO_REG_BASE, GPIO_INT_TYPE, reg_value); + + // Config Low active or Gigh active + reg_value = HAL_READ32(GPIO_REG_BASE, GPIO_INT_POLARITY); + reg_value &= ~(1 << pin_num); + reg_value |= (polarity << pin_num); + HAL_WRITE32(GPIO_REG_BASE, GPIO_INT_POLARITY, reg_value); +} +#endif +#endif diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c new file mode 100644 index 00000000000..fcc51bb22d8 --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c @@ -0,0 +1,752 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "objects.h" +#include "PinNames.h" +#include "hal_i2c.h" +#include "i2c_api.h" + +#if CONFIG_I2C_EN + +#include "pinmap.h" + + +static const PinMap PinMap_I2C_SDA[] = { + {PD_4, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, + {PH_1, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, + {PC_8, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, + {PE_7, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, + + {PC_4, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, + {PH_3, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, + {PD_7, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, + + {PB_7, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, + {PE_1, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, + {PC_7, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, + + {PB_3, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, + {PE_3, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, + {PE_5, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, + {PD_9, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, + + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PD_5, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, + {PH_0, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, + {PC_9, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, + {PE_6, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, + + {PC_5, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, + {PH_2, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, + {PD_6, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, + + {PB_6, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, + {PE_0, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, + {PC_6, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, + + {PB_2, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, + {PE_2, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, + {PE_4, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, + {PD_8, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, + + {NC, NC, 0} +}; + +static uint16_t i2c_target_addr[4]; +static SAL_I2C_TRANSFER_BUF i2ctxtranbuf[4]; +static SAL_I2C_TRANSFER_BUF i2crxtranbuf[4]; +extern u32 ConfigDebugErr; +extern u32 ConfigDebuginfo; +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + + uint32_t i2c_sel; + uint32_t i2c_idx; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_USERCB_ADPT pSalI2CUserCBAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + + // Determine the I2C to use + uint32_t i2c_sda = (uint32_t)pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = (uint32_t)pinmap_peripheral(scl, PinMap_I2C_SCL); + ConfigDebugErr &= (~(_DBG_I2C_|_DBG_GDMA_)); + ConfigDebugInfo&= (~(_DBG_I2C_|_DBG_GDMA_)); + i2c_sel = (uint32_t)pinmap_merge(i2c_sda, i2c_scl); + i2c_idx = RTL_GET_PERI_IDX(i2c_sel); + if (unlikely(i2c_idx == NC)) { + DBG_8195A("%s: Cannot find matched UART\n", __FUNCTION__); + return; + } + + /* Get I2C device handler */ + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&(obj->SalI2CUserCBAdpt); + + + /*To assign the rest pointers*/ + pSalI2CMngtAdpt->MstRDCmdCnt = 0; + pSalI2CMngtAdpt->InnerTimeOut = 2000; // inner time-out count, 2000 ms + pSalI2CMngtAdpt->pSalHndPriv = &(obj->SalI2CHndPriv); + pSalI2CMngtAdpt->pSalHndPriv->ppSalI2CHnd = (void**)&(pSalI2CMngtAdpt->pSalHndPriv); + + /* To assign the default (ROM) HAL OP initialization function */ +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) + pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_Patch; +#elif defined(CONFIG_CHIP_E_CUT) + pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_V04; +#endif + /* To assign the default (ROM) HAL GDMA OP initialization function */ + pSalI2CMngtAdpt->pHalGdmaOpInit = HalGdmaOpInit; + + /* To assign the default (ROM) SAL interrupt function */ +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) + pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_Patch; +#elif defined(CONFIG_CHIP_E_CUT) + pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_V04; +#endif + + /* To assign the default (ROM) SAL DMA TX interrupt function */ + pSalI2CMngtAdpt->pSalDMATxIrqFunc = I2CTXGDMAISRHandle; + + /* To assign the default (ROM) SAL DMA RX interrupt function */ + pSalI2CMngtAdpt->pSalDMARxIrqFunc = I2CRXGDMAISRHandle; + + pSalI2CMngtAdpt->pHalInitDat = &(obj->HalI2CInitData); + pSalI2CMngtAdpt->pHalOp = &(obj->HalI2COp); + pSalI2CMngtAdpt->pIrqHnd = &(obj->I2CIrqHandleDat); + pSalI2CMngtAdpt->pHalTxGdmaAdp = &(obj->HalI2CTxGdmaAdpt); + pSalI2CMngtAdpt->pHalRxGdmaAdp = &(obj->HalI2CRxGdmaAdpt); + pSalI2CMngtAdpt->pHalGdmaOp = &(obj->HalI2CGdmaOp); + pSalI2CMngtAdpt->pIrqTxGdmaHnd = &(obj->I2CTxGdmaIrqHandleDat); + pSalI2CMngtAdpt->pIrqRxGdmaHnd = &(obj->I2CRxGdmaIrqHandleDat); + pSalI2CMngtAdpt->pUserCB = &(obj->SalI2CUserCB); + pSalI2CMngtAdpt->pDMAConf = &(obj->SalI2CDmaUserDef); + + /* Assign the private SAL handle to public SAL handle */ + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + /* Assign the internal HAL initial data pointer to the SAL handle */ + pSalI2CHND->pInitDat = pSalI2CMngtAdpt->pHalInitDat; + + /* Assign the internal user callback pointer to the SAL handle */ + pSalI2CHND->pUserCB = pSalI2CMngtAdpt->pUserCB; + + /* Assign the internal user define DMA configuration to the SAL handle */ + pSalI2CHND->pDMAConf = pSalI2CMngtAdpt->pDMAConf; + + /*To assign user callback pointers*/ + pSalI2CMngtAdpt->pUserCB->pTXCB = pSalI2CUserCBAdpt; + pSalI2CMngtAdpt->pUserCB->pTXCCB = (pSalI2CUserCBAdpt+1); + pSalI2CMngtAdpt->pUserCB->pRXCB = (pSalI2CUserCBAdpt+2); + pSalI2CMngtAdpt->pUserCB->pRXCCB = (pSalI2CUserCBAdpt+3); + pSalI2CMngtAdpt->pUserCB->pRDREQCB = (pSalI2CUserCBAdpt+4); + pSalI2CMngtAdpt->pUserCB->pERRCB = (pSalI2CUserCBAdpt+5); + pSalI2CMngtAdpt->pUserCB->pDMATXCB = (pSalI2CUserCBAdpt+6); + pSalI2CMngtAdpt->pUserCB->pDMATXCCB = (pSalI2CUserCBAdpt+7); + pSalI2CMngtAdpt->pUserCB->pDMARXCB = (pSalI2CUserCBAdpt+8); + pSalI2CMngtAdpt->pUserCB->pDMARXCCB = (pSalI2CUserCBAdpt+9); + pSalI2CMngtAdpt->pUserCB->pGENCALLCB= (pSalI2CUserCBAdpt+10); + + /* Set I2C Device Number */ + pSalI2CHND->DevNum = i2c_idx; + + /* Load I2C default value */ + RtkI2CLoadDefault(pSalI2CHND); + + /* Assign I2C Pin Mux */ + pSalI2CHND->PinMux = RTL_GET_PERI_SEL(i2c_sel); + pSalI2CHND->OpType = I2C_INTR_TYPE; + pSalI2CHND->I2CMaster = I2C_MASTER_MODE; + pSalI2CHND->I2CSpdMod = I2C_SS_MODE; + pSalI2CHND->I2CClk = 100; + pSalI2CHND->I2CAckAddr = 0; + pSalI2CHND->TimeOut = 300; + pSalI2CHND->AddRtyTimeOut = 3000; + pSalI2CHND->I2CExd |= (I2C_EXD_MTR_ADDR_RTY); + + pSalI2CMngtAdpt->InnerTimeOut = pSalI2CHND->TimeOut; + + /* Init I2C now */ + pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum]; + HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); + HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); + RtkI2CInitForPS(pSalI2CHND); +} + +void i2c_frequency(i2c_t *obj, int hz) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + uint16_t i2c_default_clk = (uint16_t) pSalI2CHND->I2CClk; + uint16_t i2c_user_clk = (uint16_t) (hz/1000); + + + if (i2c_default_clk != i2c_user_clk) { + /* Deinit I2C first */ + i2c_reset(obj); + if (i2c_user_clk <= 100) { + pSalI2CHND->I2CSpdMod = I2C_SS_MODE; + } + else if ((i2c_user_clk > 100) && (i2c_user_clk <= 400)) { + pSalI2CHND->I2CSpdMod = I2C_FS_MODE; + } + else if (i2c_user_clk > 400) { + pSalI2CHND->I2CSpdMod = I2C_HS_MODE; + } + else { + pSalI2CHND->I2CSpdMod = I2C_SS_MODE; + } + + /* Load the user defined I2C clock */ + pSalI2CHND->I2CClk = i2c_user_clk; + + /* Init I2C now */ + pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum]; + HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); + HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); + RtkI2CInitForPS(pSalI2CHND); + } +} + +inline int i2c_start(i2c_t *obj) { + return 0; +} + +inline int i2c_stop(i2c_t *obj) { + return 0; +} + +extern u32 +HalDelayUs( + IN u32 us +); + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + u32 I2CInTOTcnt = 0; + u32 InTimeoutCount = 0; + u32 InStartCount = 0; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + if (i2c_target_addr[pSalI2CHND->DevNum] != address) { + pSalI2CHND->pInitDat->I2CAckAddr = address; + i2c_target_addr[pSalI2CHND->DevNum] = address; + HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); + } + + /* Check if the it's the last byte or not */ + pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); + if (!stop) { + pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS; + } + + pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum]; + pSalI2CHND->pRXBuf->DataLen = length; + pSalI2CHND->pRXBuf->TargetAddr= address;//pSalI2CHND->I2CAckAddr; + pSalI2CHND->pRXBuf->RegAddr = 0; + pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data; + + if (RtkI2CReceive(pSalI2CHND) != HAL_OK) { + length = length - pSalI2CHND->pRXBuf->DataLen; + return ((int)length); + } + else { + //DBG_8195A(">\n"); + /* Calculate user time out parameters */ + I2CInTOTcnt = 300; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + while((pSalI2CHND->DevSts != I2C_STS_IDLE) && + (pSalI2CHND->DevSts != I2C_STS_ERROR) && + (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + + return ((int)(length)); + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + + return ((int)(length)); + } + } + } + if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) + return ((int)(length - pSalI2CHND->pRXBuf->DataLen)); + else + return ((int)(length)); + } +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + u32 I2CInTOTcnt = 0; + u32 InTimeoutCount = 0; + u32 InStartCount = 0; + + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + if (i2c_target_addr[pSalI2CHND->DevNum] != address) { + pSalI2CHND->pInitDat->I2CAckAddr = address; + i2c_target_addr[pSalI2CHND->DevNum] = address; + HalI2CSetTarRtl8195a(pSalI2CHND->pInitDat); + } + + /* Check if the it's the last byte or not */ + pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); + if (!stop) { + pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS; + } + + pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum]; + pSalI2CHND->pTXBuf->DataLen = length; + pSalI2CHND->pTXBuf->TargetAddr= address; + pSalI2CHND->pTXBuf->RegAddr = 0; + pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data; + + if (RtkI2CSend(pSalI2CHND) != HAL_OK) { + length = length - pSalI2CHND->pTXBuf->DataLen; + return ((int)length); + } + else { + //DBG_8195A("(\n"); + /* Calculate user time out parameters */ + I2CInTOTcnt = 300; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + while((pSalI2CHND->DevSts != I2C_STS_IDLE) && + (pSalI2CHND->DevSts != I2C_STS_ERROR) && + (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; + return ((int)(length)); + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; + return ((int)(length)); + } + } + } + + if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) + return ((int)(length - pSalI2CHND->pTXBuf->DataLen)); + else + return ((int)(length)); + } +} + +int i2c_byte_read(i2c_t *obj, int last) { + uint8_t i2cdatlocal; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + /* Check if the it's the last byte or not */ + pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); + if (!last) { + pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS; + } + + pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum]; + pSalI2CHND->pRXBuf->DataLen = 1; + pSalI2CHND->pRXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum]; + pSalI2CHND->pRXBuf->RegAddr = 0; + pSalI2CHND->pRXBuf->pDataBuf = &i2cdatlocal; + RtkI2CReceive(pSalI2CHND); + + return (int)i2cdatlocal; +} + +int i2c_byte_write(i2c_t *obj, int data) { + + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + pSalI2CHND->I2CExd &= (~I2C_EXD_MTR_HOLD_BUS); + pSalI2CHND->I2CExd |= I2C_EXD_MTR_HOLD_BUS; + + pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum]; + pSalI2CHND->pTXBuf->DataLen = 1; + pSalI2CHND->pTXBuf->TargetAddr= i2c_target_addr[pSalI2CHND->DevNum]; + pSalI2CHND->pTXBuf->RegAddr = 0; + pSalI2CHND->pTXBuf->pDataBuf = (unsigned char*)&data; + + if (RtkI2CSend(pSalI2CHND) != HAL_OK) { + return 0; + } + + return 1; +} + +void i2c_reset(i2c_t *obj) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + /* Deinit I2C directly */ + RtkI2CDeInitForPS(pSalI2CHND); +} +#ifndef CONFIG_MBED_ENABLED +void i2c_restart_enable(i2c_t *obj) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + uint32_t i2clocaltmp; + uint8_t i2cen; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + i2cen = pSalI2CHND->pInitDat->I2CEn; + + if (i2cen == I2C_ENABLE) { + pSalI2CHND->pInitDat->I2CEn = I2C_DISABLE; + pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat); + } + + i2clocaltmp = HalI2CRead32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON); + i2clocaltmp |= BIT_IC_CON_IC_RESTART_EN; + HalI2CWrite32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON, i2clocaltmp); + + if (i2cen == I2C_ENABLE) { + pSalI2CHND->pInitDat->I2CEn = I2C_ENABLE; + pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat); + } + + pSalI2CHND->pInitDat->I2CReSTR = I2C_ENABLE; + +} + +void i2c_restart_disable(i2c_t *obj) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + uint32_t i2clocaltmp; + uint8_t i2cen; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + i2cen = pSalI2CHND->pInitDat->I2CEn; + + if (i2cen == I2C_ENABLE) { + pSalI2CHND->pInitDat->I2CEn = I2C_DISABLE; + pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat); + } + + i2clocaltmp = HalI2CRead32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON); + i2clocaltmp &= (~BIT_IC_CON_IC_RESTART_EN); + HalI2CWrite32(pSalI2CHND->DevNum, REG_DW_I2C_IC_CON, i2clocaltmp); + + if (i2cen == I2C_ENABLE) { + pSalI2CHND->pInitDat->I2CEn = I2C_ENABLE; + pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat); + } + + pSalI2CHND->pInitDat->I2CReSTR = I2C_DISABLE; + +} + +void i2c_set_user_callback(i2c_t *obj, I2CCallback i2ccb, void(*i2c_callback)(void *)) { + + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + if ((i2ccb >= I2C_TX_COMPLETE) && (i2ccb <= I2C_ERR_OCCURRED)) { + switch (i2ccb) { + case I2C_TX_COMPLETE: + pSalI2CHND->pUserCB->pTXCCB->USERCB = i2c_callback; + break; + case I2C_RX_COMPLETE: + pSalI2CHND->pUserCB->pRXCCB->USERCB = i2c_callback; + break; + case I2C_RD_REQ_COMMAND: + pSalI2CHND->pUserCB->pRDREQCB->USERCB = i2c_callback; + break; + case I2C_ERR_OCCURRED: + pSalI2CHND->pUserCB->pERRCB->USERCB = i2c_callback; + break; + default: + break; + } + } +} + + +void i2c_clear_user_callback(i2c_t *obj, I2CCallback i2ccb) { + + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + if ((i2ccb >= I2C_TX_COMPLETE) && (i2ccb <= I2C_ERR_OCCURRED)) { + switch (i2ccb) { + case I2C_TX_COMPLETE: + pSalI2CHND->pUserCB->pTXCCB = NULL; + break; + case I2C_RX_COMPLETE: + pSalI2CHND->pUserCB->pRXCCB = NULL; + break; + case I2C_ERR_OCCURRED: + pSalI2CHND->pUserCB->pERRCB = NULL; + break; + default: + break; + } + } +} + +int i2c_enable_control(i2c_t *obj, int enable) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + pSalI2CHND->pInitDat->I2CEn = enable; + + if(pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat) != HAL_OK) + return 0; // error + else + return 1; +} +#endif +#if DEVICE_I2CSLAVE + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + uint16_t i2c_default_addr = (uint16_t) pSalI2CHND->I2CAckAddr; + uint16_t i2c_user_addr = (uint16_t) address; + + if (i2c_target_addr[pSalI2CHND->DevNum] != i2c_user_addr) { + pSalI2CHND->pInitDat->I2CAckAddr = address; + i2c_target_addr[pSalI2CHND->DevNum] = address; + HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); + } +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + /* Deinit I2C first */ + i2c_reset(obj); + + /* Load the user defined I2C clock */ + pSalI2CHND->I2CMaster = I2C_MASTER_MODE; + if (enable_slave) + pSalI2CHND->I2CMaster = I2C_SLAVE_MODE; + + /* Init I2C now */ + RtkI2CInitForPS(pSalI2CHND); + + pSalI2CHND->pInitDat->I2CAckAddr = i2c_target_addr[pSalI2CHND->DevNum]; + HalI2CSetSarRtl8195a(pSalI2CHND->pInitDat); +} + +// See I2CSlave.h +#define NoData 0 // the slave has not been addressed +#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +#define WriteGeneral 2 // the master is writing to all slave +#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) + +int i2c_slave_receive(i2c_t *obj) { + + int i2cslvrevsts = NoData; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + i2cslvrevsts = RtkSalI2CSts(pSalI2CHND); + return i2cslvrevsts; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) { + + u32 I2CInTOTcnt = 0; + u32 InTimeoutCount = 0; + u32 InStartCount = 0; + + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + pSalI2CHND->pRXBuf = &i2crxtranbuf[pSalI2CHND->DevNum]; + pSalI2CHND->pRXBuf->DataLen = length; + pSalI2CHND->pRXBuf->pDataBuf = (u8 *)data; + + if (RtkI2CReceive(pSalI2CHND) != HAL_OK) { + return 0; //error + } + else { + /* Calculate user time out parameters */ + I2CInTOTcnt = 300; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + while((pSalI2CHND->DevSts != I2C_STS_IDLE) && + (pSalI2CHND->DevSts != I2C_STS_ERROR) && + (pSalI2CHND->DevSts != I2C_STS_TIMEOUT)) { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + return ((int)(length)); + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + return ((int)(length)); + } + } + } + + if (pSalI2CHND->DevSts != I2C_STS_TIMEOUT) + return ((int)(length - pSalI2CHND->pTXBuf->DataLen)); + else + return ((int)(length)); + } +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + pSalI2CHND->pTXBuf = &i2ctxtranbuf[pSalI2CHND->DevNum]; + pSalI2CHND->pTXBuf->DataLen = length; + pSalI2CHND->pTXBuf->pDataBuf = (u8 *)data; + + if (RtkI2CSend(pSalI2CHND) != HAL_OK) { + return 0; //error + } + + return 1; +} + +/** \brief Description of i2c_slave_set_for_rd_req + * + * i2c_slave_set_for_rd_req is used to set/clear i2c slave RD_REQ interrupt mask. + * If RD_REQ interrupt is set, slave could invoke read request callback when it gets + * a read command from other i2c master. + * + * \param i2c_t *obj : i2c object + * \param int set : set or clear for read request. Once it's set, i2c would invoke read request callback when a + * read command is sent to it. + * \return result + */ +#ifndef CONFIG_MBED_ENABLED +int i2c_slave_set_for_rd_req(i2c_t *obj, int set) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL; + PHAL_I2C_OP pHalI2COP = NULL; + u32 I2CLocalTemp; + + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat; + pHalI2COP = pSalI2CMngtAdpt->pHalOp; + + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + + if (set) { + I2CLocalTemp |= BIT_IC_INTR_MASK_M_RD_REQ; + } else { + I2CLocalTemp &= (~BIT_IC_INTR_MASK_M_RD_REQ); + } + + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + + return 1; +} + +/** \brief Description of i2c_slave_set_for_data_nak + * + * i2c_slave_set_for_data_nak is used to set/clear i2c slave NAK or ACK data part in transfer. + * + * \param i2c_t *obj : i2c object + * \param int set : set or clear for data NAK. + * \return result + */ +int i2c_slave_set_for_data_nak(i2c_t *obj, int set_nak) { + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL; + PHAL_I2C_OP pHalI2COP = NULL; + u32 I2CLocalTemp; + + pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat; + pHalI2COP = pSalI2CMngtAdpt->pHalOp; + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS); + + while (BIT_IC_STATUS_SLV_ACTIVITY & I2CLocalTemp) { + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS); + } + + HAL_I2C_WRITE32(pSalI2CHND->DevNum, REG_DW_I2C_IC_SLV_DATA_NACK_ONLY, set_nak); + return 1; +} +#endif +#endif // CONFIG_I2C_SLAVE_EN + +#endif // CONFIG_I2C_EN + diff --git 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