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That file will make it work under 800-90B TRNG mode. + +## License + +This software is provided under the Apache-2.0 license. Contributions to this project are accepted under the same license. + + +## Release details + +This release contains the ARM TrustZone TRNG software. + +### Prerequisites: + +* To be run on an Ubuntu 14.04 LTS system host for building. + +* gcc version 4.7.3 or arm-ds5 compiler are in your PATH. + +* If using Linux as a host on the H/W, configure the KERNEL_DIR environment variable to point to your Linux (s). + +* The target is running Linux kernel 4.4 or FreeRTOS. + +Download the software bundle from https://github.com/ARM-software/TZ-TRNG. + +### Build procedure + +**Step 1**: Open a terminal on the Ubuntu system, and use 'cd ' to go to the folder where you unpacked the software bundle from the ARM github url. + +**Step 2**: Define environment variables, depending on what the hw system target is running: + +* For a target hw system running FreeRTOS: +```bash + export KERNEL_DIR=/path/to/freertos +``` +or + +* For a target hw system running linux: +```bash + export KERNEL_DIR=/path/to/linux +``` + +**Step 3**: Build all the binaries (common for FreeRTOS and Linux): +```bash + cd /path/to/tztrng + make -C host/src/tztrng_lib/ clean + make -C host/src/tztrng_lib/ + make -C host/src/tests/tztrng_test/ clean + make -C host/src/tests/tztrng_test/ +``` +The tztrng library is located in: +```bash + host/lib/libcc_tztrng.a +``` + +The integration test executable is located in the following path: + - When compiling with gcc: host/bin/tztrng_test. + - When compiling with armcc: host/lib/libtztrng_test.a. + + +**Step 4**: Deploy: +* For a target hw system running linux: + + Copy host/bin/tztrng_test to the target linux file system and exeute: + ```bash + ./tztrng_test + ``` + +* For a target hw system running FreeRTOS: + + ```bash + cp host/lib/libcc_tztrng.a /path/to/your/library/folder + cp host/lib/libtztrng_test.a /path/to/your/library/folder + cp host/src/tests/tztrng_test/tztrng_test.h /path/to/includes + ``` + +## Validation + +1. Tests run + + See "Step 4: Deploy" above. + +1. Known issues + + None + +1. Planned enhancements + + None diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/config_fetrng.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/config_fetrng.h new file mode 100644 index 00000000000..f5572856eb5 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/config_fetrng.h @@ -0,0 +1,34 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#ifndef _CC_CONFIG_FETRNG_H +#define _CC_CONFIG_FETRNG_H + +/* + * This file should be updated according to the characterization process. + * + * sample count for each ring oscillator + * - for unallowed rosc, sample count = 0 + */ + +#define CC_CONFIG_SAMPLE_CNT_ROSC_1 0 +#define CC_CONFIG_SAMPLE_CNT_ROSC_2 150 +#define CC_CONFIG_SAMPLE_CNT_ROSC_3 458 +#define CC_CONFIG_SAMPLE_CNT_ROSC_4 750 + +#endif + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/config_trng90b.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/config_trng90b.h new file mode 100644 index 00000000000..6fa196911b2 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/config_trng90b.h @@ -0,0 +1,33 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#ifndef _CC_CONFIG_TRNG90B_H +#define _CC_CONFIG_TRNG90B_H + +/* +This file should be updated according to the characterization process. +*/ + +/* sample count for each ring oscillator */ +/* for unallowed rosc, sample count = 0 */ +#define CC_CONFIG_SAMPLE_CNT_ROSC_1 200 +#define CC_CONFIG_SAMPLE_CNT_ROSC_2 200 +#define CC_CONFIG_SAMPLE_CNT_ROSC_3 300 +#define CC_CONFIG_SAMPLE_CNT_ROSC_4 100 + +#endif + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng.h new file mode 100644 index 00000000000..817ec5015db --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#ifndef _TZTRNG_H_ +#define _TZTRNG_H_ + +#include + +/*******************************************************************************/ +/** + * @brief The CC_TrngGetSource reads random source of needed size from TRNG. + * + * @param[in] rngRegBase - TRNG base address, given by the system. + * @param[out] *outAddr - The pointer to the buffer address for TRNG data output, + * prepared by the caller. + * @param[out] *outLen - The pointer to size of TRNG returned data. + * @param[in] reqBits - The request size of entropy in bits. + * + * @return uint32_t - On success 0 is returned, on failure, check CC_Error_t codes + * + */ +uint32_t CC_TrngGetSource(unsigned long rngRegBase, /* in */ + uint8_t *outAddr, /* out */ + size_t *outLen, /* out */ + size_t reqBits); /* in */ + +#endif diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng_defs.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng_defs.h new file mode 100644 index 00000000000..df49537611f --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng_defs.h @@ -0,0 +1,249 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#ifndef _TZTRNG_DEFS_H_ +#define _TZTRNG_DEFS_H_ + +#include +#include +#include +#include +#include +#include "dx_reg_base_host.h" +#include "dx_rng.h" + +#if (CC_CONFIG_TRNG_MODE == 1) +#include "config_trng90b.h" +#elif (CC_CONFIG_TRNG_MODE == 0) +#include "config_fetrng.h" +#else +#error "invalid VECT definition in Makefile" +#endif + +#define CC_OK 0 +#define CC_UNUSED_PARAM(prm) ((void)prm) +#define CC_MAX_UINT32_VAL (0xFFFFFFFF) +#define LLF_RND_NUM_OF_ROSCS 4 +#define TRNG_EHR_SIZE 6 + +/* TRNG Error definitions */ +#define TRNG_MAX_CRNGT_ERRORS (12) +#define TRNG_MAX_VN_ERRORS (50) + +extern unsigned long gCcRegBase; + +typedef uint32_t CCError_t; +typedef uint32_t CCBool_t; + +typedef enum { + CC_FALSE = 0, + CC_TRUE = 1 +} CCBool; + +/* +Requirements: +- Required entropy = 384 bits + +Default values for Zynq FPGA: +- entropy per bit = 0.5 +*/ + +/* amount of bytes for the required entropy bits = ROUND_UP(ROUND_UP(((required entropy bits)/(entropy per bit)), 1024), (EHR width in bytes)) / 8 + (multiple of the window size 1024 bits and multiple of the EHR width 192 bits) */ +#define CC_CONFIG_TRNG90B_AMOUNT_OF_BYTES 144 /* ROUND_UP(ROUND_UP((384/0.5), 1024), 192) / 8 = 144 */ + +/*** NIST SP 800-90B (2nd Draft) 4.4.1 ***/ +/* C = ROUND_UP(1+(-log(W)/H)), W = 2^(-40), H=(entropy per bit) */ +#define CC_CONFIG_TRNG90B_REPETITION_COUNTER_CUTOFF 81 /* ROUND_UP(1+(40/0.5)) = 81 */ + +/*** NIST SP 800-90B (2nd Draft) 4.4.2 ***/ +/* C =CRITBINOM(W, power(2,(-H)),1-a), W = 1024, a = 2^(-40), H=(entropy per bit) */ +#define CC_CONFIG_TRNG90B_ADAPTIVE_PROPORTION_CUTOFF 823 /* =CRITBINOM(1024, power(2,(-0.5)),1-2^(-40)) */ + +/*** For Startup Tests ***/ +/* amount of bytes for the startup test = 528 (at least 4096 bits (NIST SP 800-90B (2nd Draft) 4.3.12) = 22 EHRs = 4224 bits) */ +#define CC_CONFIG_TRNG90B_AMOUNT_OF_BYTES_STARTUP 528 +/* Definitions of temp buffer for DMA */ + +#define CC_RND_WORK_BUFFER_SIZE_WORDS CC_CONFIG_TRNG90B_AMOUNT_OF_BYTES_STARTUP/4 /* the maximum possible usage of stack memory in words */ + +/* The CRYS Random Generator Parameters structure CCRndParams_t - + structure containing the user given Parameters */ +typedef struct CCRndParams_t +{ + /* allowed ring oscillator lengths: bits 0,1,2,3 */ + uint32_t RoscsAllowed; + + /* sampling interval: count of ring oscillator cycles between + consecutive bits sampling */ + uint32_t SubSamplingRatio; + uint32_t SubSamplingRatio1; + uint32_t SubSamplingRatio2; + uint32_t SubSamplingRatio3; + uint32_t SubSamplingRatio4; + +} CCRndParams_t; + +/*! RND state structure. Includes internal data that needs to be saved between boots by the user.*/ +typedef struct +{ + /* State flag (see definition of StateFlag above), containing bit-fields, defining: + - b'0: instantiation steps: 0 - not done, 1 - done; + - 2b'9,8: working or testing mode: 0 - working, 1 - KAT DRBG test, 2 - + KAT TRNG test; + b'16: flag defining is Previous random valid or not: + 0 - not valid, 1 - valid */ + /*! State flag used internally in the code.*/ + uint32_t StateFlag; + + /* Trng processing flag - indicates which ROSC lengths are: + - allowed (bits 0-3); + - total started (bits 8-11); + - processed (bits 16-19); + - started, but not processed (bits24-27) */ + /*! TRNG process state used internally in the code */ + uint32_t TrngProcesState; + +} CCRndState_t; + +/* Register Offset macro */ +#define CC_REG_OFFSET(unit_name, reg_name) \ + (DX_ ## reg_name ## _REG_OFFSET) + +/*! + * Read TRNG memory-mapped-IO register. + * + * \param regOffset The offset of the ARM TRNG register to read + * \return uint32_t Return the value of the given register + */ +#define CC_HAL_READ_REGISTER(regOffset) \ + (*((volatile uint32_t *)(gCcRegBase + (regOffset)))) + +/*! + * Write TRNG memory-mapped-IO register. + * \note This macro must be modified to make the operation synchronous, i.e. the write operation must complete, + * and the new value must be written to the register before the macro returns. The mechanisms required to + * achieve this are architecture-dependent (e.g., the memory barrier in ARM architecture). + * + * \param regOffset The offset of the ARM TRNG register to write + * \param val The value to write + */ +#define CC_HAL_WRITE_REGISTER(regOffset, val) \ + (*((volatile uint32_t *)(gCcRegBase + (regOffset))) = (val)) + +#define LLF_RND_HW_TRNG_EHR_WIDTH_IN_WORDS 6 +#define LLF_RND_HW_TRNG_EHR_WIDTH_IN_BYTES (LLF_RND_HW_TRNG_EHR_WIDTH_IN_WORDS * sizeof(uint32_t)) +#define LLF_RND_HW_DMA_EHR_SAMPLES_NUM_ON_TRNG90B_MODE 22UL +#define LLF_RND_HW_DEBUG_CONTROL_VALUE_ON_FE_MODE 0x00000000 +/* ring oscillator offsets and numbers */ +#define LLF_RND_HW_TRNG_ROSC0_BIT 0x1 +#define LLF_RND_HW_TRNG_ROSC1_BIT 0x2 +#define LLF_RND_HW_TRNG_ROSC2_BIT 0x4 +#define LLF_RND_HW_TRNG_ROSC3_BIT 0x8 +#define LLF_RND_HW_TRNG_ROSC0_NUM 0x0 +#define LLF_RND_HW_TRNG_ROSC1_NUM 0x1 +#define LLF_RND_HW_TRNG_ROSC2_NUM 0x2 +#define LLF_RND_HW_TRNG_ROSC3_NUM 0x3 + +#define LLF_RND_HW_RND_SRC_ENABLE_VAL 1UL +#define LLF_RND_HW_RND_SRC_DISABLE_VAL 0UL +#define LLF_RND_HW_TRNG_WITH_DMA_CONFIG_VAL 0x4 +#define LLF_RNG_INT_MASK_ON_TRNG90B_MODE 0xFFFFFFC5 +#define LLF_RNG_INT_MASK_ON_FETRNG_MODE 0xFFFFFFEC + +#define LLF_RND_HW_DMA_EHR_SAMPLES_NUM_ON_FE_MODE 2UL /*for both AES128 and AES256*/ + +/* Logging macros */ +#define TRNG_LOG(format, ...) \ + fprintf(stderr, "tztrng:%s: " format , __func__, ##__VA_ARGS__) + +#ifdef DEBUG +#define TRNG_LOG_DEBUG(format, ...) TRNG_LOG(format, ##__VA_ARGS__) +#else +#define TRNG_LOG_DEBUG(format, ...) do {} while (0) +#endif + +#ifdef TZTRNG_EHR_DUMP +#define TRNG_EHR_DUMP(format, ...) \ + fprintf(stderr, format, ##__VA_ARGS__) +#else +#define TRNG_EHR_DUMP(format, ...) do {} while (0) +#endif + +#define CC_ERROR_BASE 0x00F00000UL +#define CC_ERROR_LAYER_RANGE 0x00010000UL +#define CC_ERROR_MODULE_RANGE 0x00000100UL +#define CC_LAYER_ERROR_IDX 0x00UL +#define LLF_LAYER_ERROR_IDX 0x01UL +#define GENERIC_ERROR_IDX 0x05UL +#define RND_ERROR_IDX 0x0CUL +#define CC_RND_MODULE_ERROR_BASE (CC_ERROR_BASE + \ + (CC_ERROR_LAYER_RANGE * CC_LAYER_ERROR_IDX) + \ + (CC_ERROR_MODULE_RANGE * RND_ERROR_IDX ) ) + +/*! Low level RND module error base address - 0x00F10C00. */ +#define LLF_RND_MODULE_ERROR_BASE (CC_ERROR_BASE + \ + (CC_ERROR_LAYER_RANGE * LLF_LAYER_ERROR_IDX) + \ + (CC_ERROR_MODULE_RANGE * RND_ERROR_IDX ) ) +#define LLF_RND_HW_DEBUG_CONTROL_VALUE_ON_TRNG90B_MODE 0x0000000A /* bypass Von-Neumann balancer and autocorrelation test */ +#define LLF_RND_HW_VERSION_NOT_CORRECT_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x0UL) +#define LLF_RND_CPRNG_TEST_FAIL_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x1UL) +#define LLF_RND_CRNGT_TEST_FAIL_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x2UL) +#define LLF_RND_STATE_PTR_INVALID_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x3UL) +#define LLF_RND_AES_256_NOT_SUPPORTED_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x4UL) + +#define LLF_RND_TRNG_TIME_LIMIT_EXCEEDED_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x20UL) +#define LLF_RND_TRNG_ENTR_ESTIM_SIZE_EXCEED_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x21UL) + +#define LLF_RND_TRNG_PREVIOUS_PARAMS_NOT_MATCH_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x30UL) +#define LLF_RND_TRNG_REQUIRED_ROSCS_NOT_ALLOWED_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x31UL) +#define LLF_RND_TRNG_GENERATION_NOT_COMPLETED_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x32UL) +#define LLF_RND_TRNG_LOW_ENTROPY_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x33UL) +#define LLF_RND_TRNG_NULL_ENTROPY_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x34UL) +#define LLF_RND_TRNG_ILLEGAL_PTR_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x35UL) +#define LLF_RND_TRNG_REPETITION_COUNTER_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x36UL) +#define LLF_RND_TRNG_ADAPTION_PROPORTION_ERROR (LLF_RND_MODULE_ERROR_BASE + 0x37UL) + +#define CC_RND_CPRNG_TEST_FAIL_ERROR (CC_RND_MODULE_ERROR_BASE + 0x2UL) +#define CC_RND_TRNG_KAT_NOT_SUPPORTED_ERROR (CC_RND_MODULE_ERROR_BASE + 0x34UL) + +void LLF_RND_TurnOffTrng(void); +CCError_t LLF_RND_GetFastestRosc( CCRndParams_t *trngParams_ptr, uint32_t *rosc_ptr/*in/out*/); +CCError_t LLF_RND_GetRoscSampleCnt( uint32_t rosc, CCRndParams_t *pTrngParams); +uint32_t LLF_RND_TRNG_RoscMaskToNum(uint32_t mask); + +#define CC_RND_NOT_INSTANTIATED 0UL +#define CC_RND_INSTANTIATED 1UL +#define CC_RND_INSTANTRESEED_AUTOCORR_ERRORS 2UL +#define CC_RND_INSTANTRESEED_TIME_EXCEED 4UL +#define CC_RND_INSTANTRESEED_LESS_ENTROPY 8UL + +CCError_t LLF_RND_RunTrngStartupTest( + CCRndState_t *rndState_ptr, /*in/out*/ + CCRndParams_t *trngParams_ptr, /*out*/ + uint32_t *rndWorkBuff_ptr); /*in*/ + +CCError_t LLF_RND_GetTrngSource( + CCRndState_t *rndState_ptr, /*in/out*/ + CCRndParams_t *trngParams_ptr, /*in/out*/ + CCBool_t isContinued, /*in*/ + uint32_t **sourceOut_ptr_ptr,/*out*/ + uint32_t *sourceOutSize_ptr, /*in/out*/ + uint32_t *rndWorkBuff_ptr); /*in*/ + +#endif + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng_pal.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng_pal.h new file mode 100644 index 00000000000..2536b77f637 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/include/tztrng_pal.h @@ -0,0 +1,26 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#ifndef _TZTRNG_PAL_H_ +#define _TZTRNG_PAL_H_ + +#include +uint32_t CC_HalWaitInterrupt(void); +void tztrng_memcpy(uint8_t *dst, uint8_t *src, size_t size); +void tztrng_memset(uint8_t *dst, uint8_t value, size_t size); + +#endif diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd.c new file mode 100644 index 00000000000..56e51cf5d86 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd.c @@ -0,0 +1,22 @@ +/****************************************************************************** + * Copyright (c) 2017-2017, ARM, All Rights Reserved * + * SPDX-License-Identifier: Apache-2.0 * + * * + * Licensed under the Apache License, Version 2.0 (the "License"); * + * you may not use this file except in compliance with the License. * + * * + * You may obtain a copy of the License at * + * http://www.apache.org/licenses/LICENSE-2.0 * + * * + * Unless required by applicable law or agreed to in writing, software * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * + * * + * See the License for the specific language governing permissions and * + * limitations under the License. * + ******************************************************************************/ +#include "tztrng_defs.h" +#include "tztrng_pal.h" + + + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_common.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_common.c new file mode 100644 index 00000000000..d99d76a70da --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_common.c @@ -0,0 +1,83 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#include "tztrng_defs.h" +#include "tztrng_pal.h" + +CCError_t LLF_RND_GetRoscSampleCnt(uint32_t rosc, CCRndParams_t *pTrngParams) +{ + switch (rosc) { + case 0x1: + pTrngParams->SubSamplingRatio = pTrngParams->SubSamplingRatio1; + break; + case 0x2: + pTrngParams->SubSamplingRatio = pTrngParams->SubSamplingRatio2; + break; + case 0x4: + pTrngParams->SubSamplingRatio = pTrngParams->SubSamplingRatio3; + break; + case 0x8: + pTrngParams->SubSamplingRatio = pTrngParams->SubSamplingRatio4; + break; + default: + return LLF_RND_TRNG_REQUIRED_ROSCS_NOT_ALLOWED_ERROR; + } + + return CC_OK; +} + +uint32_t LLF_RND_TRNG_RoscMaskToNum(uint32_t mask) +{ + return (mask == LLF_RND_HW_TRNG_ROSC3_BIT) ? LLF_RND_HW_TRNG_ROSC3_NUM : + (mask == LLF_RND_HW_TRNG_ROSC2_BIT) ? LLF_RND_HW_TRNG_ROSC2_NUM : + (mask == LLF_RND_HW_TRNG_ROSC1_BIT) ? LLF_RND_HW_TRNG_ROSC1_NUM : + LLF_RND_HW_TRNG_ROSC0_NUM; +} + +/** + * The function gets next allowed rosc + * + * @author reuvenl (9/12/2012) + * + * @param trngParams_ptr - a pointer to params structure. + * @param rosc_ptr - a pointer to previous rosc /in/, and + * to next rosc /out/. + * @param isNext - defines is increment of rosc ID needed or not. + * if isNext = TRUE - the function shifts rosc by one bit; Then + * the function checks is this rosc allowed, if yes - updates + * the rosc, else repeats previous steps. If no roscs allowed - + * returns an error. + * + * @return CCError_t + */ +CCError_t LLF_RND_GetFastestRosc( + CCRndParams_t *trngParams_ptr, + uint32_t *rosc_ptr /*in/out*/) +{ + /* setting rosc */ + do { + if (*rosc_ptr & trngParams_ptr->RoscsAllowed) { + return CC_OK; + } else { + *rosc_ptr <<= 1; + } + + } while (*rosc_ptr <= 0x08); + + return LLF_RND_TRNG_REQUIRED_ROSCS_NOT_ALLOWED_ERROR; +} + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_cont.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_cont.c new file mode 100644 index 00000000000..b8be8db28d2 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_cont.c @@ -0,0 +1,166 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#include "tztrng_defs.h" +#include "tztrng_pal.h" + +#define LLF_RND_TRNG90B_MAX_BYTES ( LLF_RND_HW_DMA_EHR_SAMPLES_NUM_ON_TRNG90B_MODE * LLF_RND_HW_TRNG_EHR_WIDTH_IN_BYTES) +#define CC_CONFIG_TRNG90B_ADAPTIVE_PROPORTION_WINDOW_SIZE 1024 /* binary noise source */ + + +#define UINT8_SIZE_IN_BITS 8 +#define UINT32_SIZE_IN_BITS (sizeof(uint32_t) * UINT8_SIZE_IN_BITS) +uint32_t getBitsFromUint32Array(uint32_t arrayBitsOffset, uint32_t numOfBits, uint32_t* arr) +{ + uint32_t res = 0; + uint32_t byteOffset = arrayBitsOffset / UINT32_SIZE_IN_BITS; + uint32_t bitOffset = arrayBitsOffset % UINT32_SIZE_IN_BITS; + if (numOfBits > UINT32_SIZE_IN_BITS) { + return 0; + } + res = arr[byteOffset] >> bitOffset; + /* (UINT32_SIZE_IN_BITS - bitOffset) bits were taken from the first dword. */ + + if (UINT32_SIZE_IN_BITS - bitOffset > numOfBits) + /* we copied more bits than required. zero the extra bits. */ + { + res &= (0xFFFFFFFF >> (UINT32_SIZE_IN_BITS - numOfBits)); + } else if (UINT32_SIZE_IN_BITS - bitOffset < numOfBits) + /* we copied less bits than required. copy the next bits from the next dword. */ + { + numOfBits -= UINT32_SIZE_IN_BITS - bitOffset; + res |= (arr[byteOffset + 1] & (0xFFFFFFFF >> (UINT32_SIZE_IN_BITS - numOfBits))) << (UINT32_SIZE_IN_BITS - bitOffset); + } + + return res; +} + +/* + implementation of Repetition Counter Test (NIST SP 800-90B (2nd Draft) 4.4.1) + C = the cutoff value at which the Repetition Count Test fails +*/ +CCError_t LLF_RND_RepetitionCounterTest(uint32_t* pData, uint32_t sizeInBytes, uint32_t C) +{ + uint32_t bitOffset=0; + uint32_t newSample = 0; + uint32_t A = 0; /* the most recently seen sample value */ + uint32_t B = 0; /* the number of consecutive times that the value A has been seen */ + uint32_t bitsPerSample = 1; /* always use single bit per sample for repetition counter test */ + + + if (pData == NULL || sizeInBytes == 0 || LLF_RND_TRNG90B_MAX_BYTES < sizeInBytes) { + return LLF_RND_TRNG_REPETITION_COUNTER_ERROR; + } + + /* the repetition count test is performed as follows: */ + for (bitOffset = 0; bitOffset <= (sizeInBytes * UINT8_SIZE_IN_BITS) - bitsPerSample; bitOffset += bitsPerSample) { + newSample = getBitsFromUint32Array(bitOffset, bitsPerSample, (uint32_t*)pData); + + /* 1. Let A be the current sample value. */ + /* 2. Initialize the counter B to 1. */ + if (bitOffset == 0) { + A = newSample; + B = 1; + } + /* 3. If the next sample value is A, increment B by one. */ + else if (A == newSample) { + ++B; + /* If B is equal to C, return an error. */ + if (B == C) { + return LLF_RND_TRNG_REPETITION_COUNTER_ERROR; + } + } else { + /* Let A be the next sample value. */ + A = newSample; + /* Initialize the counter B to 1. */ + B = 1; + /* Repeat Step 3. */ + } + } + return CC_OK; +} + +/* + implementation of Adaptive Proportion Test (NIST SP 800-90B (2nd Draft) 4.4.2) + N = the total number of samples that must be observed in one run of the test, also known as the "window size" of the test + C = the cutoff value above which the test should fail +*/ +static CCError_t LLF_RND_AdaptiveProportionTest(uint32_t* pData, uint32_t sizeInBytes, uint32_t C, uint32_t W) +{ + uint32_t bitOffset=0; + uint32_t currentSample = 0; + uint32_t A = 0; /* the sample value currently being counted */ + uint32_t B = 0; /* the current number of times that A has been seen in the S samples examined so far */ + uint32_t i = 0; /* the counter for the number of samples examined in the current window */ + uint32_t bitsPerSample = 1; /* binary source */ + + if (pData == NULL || sizeInBytes == 0 || LLF_RND_TRNG90B_MAX_BYTES < sizeInBytes || W == 0 || C == 0) { + return LLF_RND_TRNG_ADAPTION_PROPORTION_ERROR; + } + + /* The test is performed as follows: */ + for (bitOffset = 0; bitOffset <= (sizeInBytes * UINT8_SIZE_IN_BITS) - bitsPerSample; bitOffset += bitsPerSample) { + currentSample = getBitsFromUint32Array(bitOffset, bitsPerSample, (uint32_t*)pData); + + /* 1. Let A be the current sample value. */ + /* 2. Initialize the counter B to 1 */ + if ((bitOffset == 0) || (i == W)) { + A = currentSample; + B = 1; + i = 0; + } + /* 3. For i = 1 to W-1 */ + else { + /* If the next sample is equal to A, increment B by 1. */ + if (A == currentSample) { + ++B; + } + } + /* 4. If B > C, return error. */ + if (i == W - 1) { + if (B > C) { + return LLF_RND_TRNG_ADAPTION_PROPORTION_ERROR; + } + } + ++i; + /* 5. Go to Step 1. */ + } + return CC_OK; +} + +/* + implementation of Continuous Testing (NIST SP 800-90B 6.5.1.2) +*/ +CCError_t runContinuousTesting(uint32_t* pData, uint32_t sizeInBytes) +{ + CCError_t error = CC_OK; + uint32_t repC = CC_CONFIG_TRNG90B_REPETITION_COUNTER_CUTOFF; + uint32_t adpW = CC_CONFIG_TRNG90B_ADAPTIVE_PROPORTION_WINDOW_SIZE; + uint32_t adpC = CC_CONFIG_TRNG90B_ADAPTIVE_PROPORTION_CUTOFF; + + error = LLF_RND_RepetitionCounterTest(pData, sizeInBytes, repC); + if (error != CC_OK) { + return error; + } + error = LLF_RND_AdaptiveProportionTest(pData, sizeInBytes, adpC, adpW); + if (error != CC_OK) { + return error; + } + + return CC_OK; +} + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_trng90b.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_trng90b.c new file mode 100644 index 00000000000..b6accb03123 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/llf_rnd_trng90b.c @@ -0,0 +1,386 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#include "tztrng_defs.h" +#include "tztrng_pal.h" + +static CCError_t startTrngHW( + CCRndState_t *rndState_ptr, + CCRndParams_t *trngParams_ptr, + CCBool_t isRestart, + uint32_t *roscsToStart_ptr, + CCBool_t isStartup); +extern CCError_t runContinuousTesting(uint32_t* pData, uint32_t sizeInBytes); + +/************************************************************************************/ +/** + * The function checks that parameters, loaded in the TRNG HW + * are match to parameters, required by trngParams_ptr structures. + * + * @author reuvenl (6/25/2012) + * + * @param trngParams_ptr + * + * @return CCError_t + */ +static CCError_t LLF_RND_TRNG_CheckHwParams(CCRndParams_t *trngParams_ptr) +{ + uint32_t temp; + CCBool_t isTrue = CC_TRUE; + + /* check Debug control - masked TRNG tests according to mode */ + temp = CC_HAL_READ_REGISTER(CC_REG_OFFSET(RNG, TRNG_DEBUG_CONTROL)); + isTrue &= (temp == LLF_RND_HW_DEBUG_CONTROL_VALUE_ON_TRNG90B_MODE); + /* check samplesCount */ + temp = CC_HAL_READ_REGISTER(CC_REG_OFFSET(RNG,SAMPLE_CNT1)); + isTrue &= (temp == trngParams_ptr->SubSamplingRatio); + + /* if any parameters are not match return an Error */ + if (isTrue == CC_FALSE) + return LLF_RND_TRNG_PREVIOUS_PARAMS_NOT_MATCH_ERROR; + else + return CC_OK; +} + +static int32_t readEhrData(uint32_t *sample, + CCRndState_t *rndState_ptr, + CCRndParams_t *trngParams_ptr, + uint32_t *roscsToStart_ptr) +{ + uint32_t i; + CCError_t err = CC_OK; + + err = startTrngHW(rndState_ptr, trngParams_ptr, CC_FALSE, roscsToStart_ptr, CC_FALSE); + if (err) { + TRNG_LOG_DEBUG("startTrngHW() failed..\n"); + return err; + } + + /* Read 1 EHR of random bits */ + if (CC_HalWaitInterrupt()) { + TRNG_LOG_DEBUG("CC_HalWaitInterrupt() failed..\n"); + LLF_RND_TurnOffTrng(); + return (-1); + } + + /* Read EHR into tmp buffer */ + for (i = 0; i < TRNG_EHR_SIZE; i++) { + uint32_t ehr = CC_HAL_READ_REGISTER(DX_EHR_DATA_0_REG_OFFSET + (i * sizeof(uint32_t))); + TRNG_EHR_DUMP("EHR[%i][0x%x]\n", i, ehrp); + sample[i] = ehr; + } + + return CC_OK; +} + +static CCError_t readMultipleEHR(uint32_t inSize, uint8_t *ramAddr, + CCRndState_t *rndState_ptr, + CCRndParams_t *trngParams_ptr, + uint32_t *roscsToStart_ptr) +{ + uint32_t noise_samples[TRNG_EHR_SIZE]; + CCError_t err = CC_OK; + uint32_t read_size = TRNG_EHR_SIZE * sizeof(uint32_t); + + while (inSize) { + + LLF_RND_TurnOffTrng(); + err = readEhrData(noise_samples, rndState_ptr, trngParams_ptr, roscsToStart_ptr); + if (err != CC_OK) + return err; + + /* Copy the needed amount of bytes to the result buffer */ + tztrng_memcpy(ramAddr, (uint8_t *)noise_samples, read_size); + + inSize -= read_size; + ramAddr += read_size; + } + + return CC_OK; +} + +static CCError_t startTrngHW( + CCRndState_t *rndState_ptr, + CCRndParams_t *trngParams_ptr, + CCBool_t isRestart, + uint32_t *roscsToStart_ptr, + CCBool_t isStartup) +{ + /* LOCAL DECLARATIONS */ + + CCError_t error = CC_OK; + uint32_t tmpSamplCnt = 0; + uint32_t roscNum = 0; + + CC_UNUSED_PARAM(isStartup); + + /* FUNCTION LOGIC */ + + /* Check pointers */ + if ((rndState_ptr == NULL) || (trngParams_ptr == NULL) || + (roscsToStart_ptr == NULL)) + return LLF_RND_TRNG_ILLEGAL_PTR_ERROR; + + /*--------------------------------------------------------------*/ + /* 1. If full restart, get semaphore and set initial ROSCs */ + /*--------------------------------------------------------------*/ + if (isRestart) { + /* set ROSC to 1 (fastest) */ + *roscsToStart_ptr = 1UL; + + /* init rndState flags to zero */ + rndState_ptr->TrngProcesState = 0; + } + + + if (*roscsToStart_ptr == 0) + return LLF_RND_TRNG_REQUIRED_ROSCS_NOT_ALLOWED_ERROR; + + /* TRNG90B mode */ + /* Get fastest allowed ROSC */ + error = LLF_RND_GetFastestRosc( + trngParams_ptr, + roscsToStart_ptr /*in/out*/); + if (error) + return error; + + error = LLF_RND_GetRoscSampleCnt(*roscsToStart_ptr, trngParams_ptr); + if (error) + return error; + + roscNum = LLF_RND_TRNG_RoscMaskToNum(*roscsToStart_ptr); + + /*--------------------------------------------------------------*/ + /* 2. Restart the TRNG and set parameters */ + /*--------------------------------------------------------------*/ + + /* in order to verify that the reset has completed the sample count need to be verified */ + do { + /* set sampling ratio (rng_clocks) between consequtive bits */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, SAMPLE_CNT1), trngParams_ptr->SubSamplingRatio); + + /* read the sampling ratio */ + tmpSamplCnt = CC_HAL_READ_REGISTER(CC_REG_OFFSET(RNG, SAMPLE_CNT1)); + + } while (tmpSamplCnt != trngParams_ptr->SubSamplingRatio); + + /* disable the RND source for setting new parameters in HW */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, RND_SOURCE_ENABLE), LLF_RND_HW_RND_SRC_DISABLE_VAL); + + /* set TRNG_CONFIG to choose SOP_SEL = 1 - i.e. EHR output */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, TRNG_CONFIG), roscNum); + + /* Debug Control register: set to 0 - no bypasses */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, TRNG_DEBUG_CONTROL), LLF_RND_HW_DEBUG_CONTROL_VALUE_ON_TRNG90B_MODE); + + /* set interrupt mask */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, RNG_IMR), LLF_RNG_INT_MASK_ON_TRNG90B_MODE); + + /* clear RNG interrupts !!TBD */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, RNG_ICR), 0xFFFFFFFF); + + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, RND_SOURCE_ENABLE), LLF_RND_HW_RND_SRC_ENABLE_VAL); + + /* set indication about current started ROSCs: */ + /*new started*/ + rndState_ptr->TrngProcesState = (rndState_ptr->TrngProcesState & 0x00ffffff) | (*roscsToStart_ptr << 24); + /*total started*/ + rndState_ptr->TrngProcesState |= (*roscsToStart_ptr << 8); + + /* end of function */ + return error; +} + +static CCError_t getTrngSource( + CCRndState_t *rndState_ptr, /*in/out*/ + CCRndParams_t *trngParams_ptr, /*in/out*/ + CCBool_t isContinued, /*in*/ + uint32_t **sourceOut_ptr_ptr, /*out*/ + uint32_t *sourceOutSize_ptr,/*in/out*/ + uint32_t *rndWorkBuff_ptr, /*in*/ + CCBool_t isStartup) /*in*/ +{ + /* LOCAL DECLARATIONS */ + + /* The return error identifier */ + CCError_t error = 0, descrError = 0; + + int32_t i; + uint32_t roscToStart; + uint32_t *ramAddr; + const uint32_t trng90bRequiredBytes = (isStartup == CC_FALSE ? CC_CONFIG_TRNG90B_AMOUNT_OF_BYTES : CC_CONFIG_TRNG90B_AMOUNT_OF_BYTES_STARTUP); + + /* FUNCTION LOGIC */ + + /* ............... local initializations .............................. */ + /* -------------------------------------------------------------------- */ + + /* initializing the Error to O.K */ + error = CC_OK; + + /* Set source RAM address with offset 8 bytes from sourceOut address in + order to remain empty bytes for CC operations */ + *sourceOut_ptr_ptr = rndWorkBuff_ptr; + ramAddr = *sourceOut_ptr_ptr; + + /* init to 0 for FE mode */ + *sourceOutSize_ptr = 0; + + /* If not continued mode, set TRNG parameters and restart TRNG */ + /*--------------------------------------------------------------*/ + if (isContinued == CC_FALSE) { + + /* Full restart TRNG */ + error = startTrngHW( + rndState_ptr, + trngParams_ptr, + CC_TRUE/*isRestart*/, + &roscToStart, + isStartup); + + /*Note: in case of error the TRNG HW is still not started*/ + if (error) + goto End; + } + /* On continued mode check HW TRNG */ + else { + /* check TRNG parameters */ + error = LLF_RND_TRNG_CheckHwParams(trngParams_ptr); + if (error != CC_OK) + goto End; + + /* previously started ROSCs */ + roscToStart = (rndState_ptr->TrngProcesState & 0xff000000) >> 24; + } + + /*====================================================*/ + /*====================================================*/ + /* Processing after previous start */ + /*====================================================*/ + /*====================================================*/ + + /*====================================================*/ + /* TRNG90b mode processing: start Roscs sequentionally - * + * from fast to slow Rosc */ + /*====================================================*/ + + for (i = 0; i < LLF_RND_NUM_OF_ROSCS; ++i) { + + *sourceOutSize_ptr = trng90bRequiredBytes; + + descrError = readMultipleEHR(*sourceOutSize_ptr, (uint8_t *)ramAddr, + rndState_ptr, + trngParams_ptr, + &roscToStart); + + if (descrError == CC_OK) { + error = runContinuousTesting(ramAddr, *sourceOutSize_ptr); + if (error == CC_OK) { + break; + } + *sourceOutSize_ptr = 0; + } + else { + /* Note: Priority to SW error */ + error = descrError; + } + + /* update total processed ROSCs */ + rndState_ptr->TrngProcesState |= ((rndState_ptr->TrngProcesState >> 8) & 0x00FF0000); + /*clean started & not processed*/ + rndState_ptr->TrngProcesState &= 0x00FFFFFF; + + /* case of erors or watchdog exceed - try next rosc */ + /* if no remain roscs to start, return error */ + if (roscToStart == 0x8) { + error = LLF_RND_TRNG_GENERATION_NOT_COMPLETED_ERROR; + break; + } else { + /* Call StartTrng, with next ROSC */ + roscToStart <<= 1; + TRNG_LOG_DEBUG("process with next rosc[%d]\n",(int) roscToStart); + error = startTrngHW( + rndState_ptr, + trngParams_ptr, + CC_FALSE/*isRestart*/, + &roscToStart, + isStartup); + + if (error != CC_OK) + goto End; + } + } + + /* ................. end of function ..................................... */ + /* ----------------------------------------------------------------------- */ + End: + + /* turn the RNG off */ + LLF_RND_TurnOffTrng(); + + return error; +} /* END of getTrngSource */ + +/****************************************************************************************/ +/***************************** Public Functions ******************************/ +/****************************************************************************************/ + +CCError_t LLF_RND_StartTrngHW( + CCRndState_t *rndState_ptr, + CCRndParams_t *trngParams_ptr, + CCBool_t isRestart, + uint32_t *roscsToStart_ptr) +{ + CCError_t error = CC_OK; + + error = startTrngHW(rndState_ptr, trngParams_ptr, isRestart, roscsToStart_ptr, CC_FALSE/*isStartup*/); + + return error; +} + + +CCError_t LLF_RND_GetTrngSource( + CCRndState_t *rndState_ptr, /*in/out*/ + CCRndParams_t *trngParams_ptr, /*in/out*/ + CCBool_t isContinued, /*in*/ + uint32_t **sourceOut_ptr_ptr,/*out*/ + uint32_t *sourceOutSize_ptr, /*in/out*/ + uint32_t *rndWorkBuff_ptr) /*in*/ +{ + CCError_t error = CC_OK; + + error = getTrngSource(rndState_ptr, trngParams_ptr, isContinued, + sourceOut_ptr_ptr, sourceOutSize_ptr, rndWorkBuff_ptr, CC_FALSE/*isStartup*/); + + return error; +} + +CCError_t LLF_RND_RunTrngStartupTest( + CCRndState_t *rndState_ptr, + CCRndParams_t *trngParams_ptr, + uint32_t *rndWorkBuff_ptr) +{ + CCError_t error = CC_OK; + uint32_t *pSourceOut; + uint32_t sourceOutSize; + + error = getTrngSource(rndState_ptr, trngParams_ptr, CC_FALSE/*isContinued*/, + &pSourceOut, &sourceOutSize, rndWorkBuff_ptr, CC_TRUE/* isStartup*/); + + return error; +} + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/tztrng_driver.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/tztrng_driver.c new file mode 100644 index 00000000000..ed342be9e38 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/tztrng_driver.c @@ -0,0 +1,118 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#include "tztrng_defs.h" +#include "tztrng_pal.h" + +unsigned long gCcRegBase = 0; + +static CCError_t RNG_PLAT_SetUserRngParameters(CCRndParams_t *pTrngParams) +{ + CCError_t error = CC_OK; + + /* Set TRNG parameters */ + pTrngParams->SubSamplingRatio1 = CC_CONFIG_SAMPLE_CNT_ROSC_1; + pTrngParams->SubSamplingRatio2 = CC_CONFIG_SAMPLE_CNT_ROSC_2; + pTrngParams->SubSamplingRatio3 = CC_CONFIG_SAMPLE_CNT_ROSC_3; + pTrngParams->SubSamplingRatio4 = CC_CONFIG_SAMPLE_CNT_ROSC_4; + + /* Allowed ROSCs lengths b'0-3. If bit value 1 - appropriate ROSC is allowed. */ + pTrngParams->RoscsAllowed = (((pTrngParams->SubSamplingRatio1 > 0) ? 0x1 : 0x0) | + ((pTrngParams->SubSamplingRatio2 > 0) ? 0x2 : 0x0) | + ((pTrngParams->SubSamplingRatio3 > 0) ? 0x4 : 0x0) | + ((pTrngParams->SubSamplingRatio4 > 0) ? 0x8 : 0x0)); + pTrngParams->SubSamplingRatio = 0; + + if (0 == pTrngParams->RoscsAllowed) { + TRNG_LOG_DEBUG("No ROSC allowed!!\n"); + return LLF_RND_TRNG_REQUIRED_ROSCS_NOT_ALLOWED_ERROR; + } + + return error; +} + +uint32_t CC_TrngGetSource(unsigned long rngRegBase, uint8_t *outAddr, size_t *outLen, size_t reqBits) +{ + CCError_t Err = CC_OK; + uint32_t rndWorkBuff[CC_RND_WORK_BUFFER_SIZE_WORDS]; + CCRndParams_t rndParams; + CCRndState_t rndState = {0}; + uint32_t *rndSrc_ptr; + uint32_t sourceOutSizeBytes = 0; + uint32_t requireBytes = (reqBits % 8) ? (reqBits / 8 + 1) : (reqBits / 8); + + if (NULL == outAddr || NULL == outLen) { + TRNG_LOG_DEBUG("NULL pointer!!\n"); + return LLF_RND_TRNG_ILLEGAL_PTR_ERROR; + } + + /* zeroe the rnd buff */ + tztrng_memset((uint8_t *)rndWorkBuff, 0, sizeof(rndWorkBuff)); + tztrng_memset((uint8_t *)&rndParams, 0, sizeof(CCRndParams_t)); + gCcRegBase = rngRegBase; + + if (gCcRegBase == 0) { + TRNG_LOG_DEBUG("register base not initialized\n"); + return LLF_RND_TRNG_ILLEGAL_PTR_ERROR; + } + + /* Get parameters and set them in the RND structures */ + Err = RNG_PLAT_SetUserRngParameters(&rndParams); + if (Err != CC_OK) + return Err; + + Err = LLF_RND_RunTrngStartupTest(&rndState, &rndParams, rndWorkBuff); + if (Err != CC_OK) + return Err; + + *outLen = requireBytes; + while (requireBytes > 0) { + /* Get TRNG Source */ + Err = LLF_RND_GetTrngSource( + &rndState, + &rndParams, + 0, + &rndSrc_ptr, + &sourceOutSizeBytes, + rndWorkBuff); + + if (Err) { + TRNG_LOG_DEBUG("LLF_RND_GetTrngSource failed, err[0x%X]\n", (unsigned int)Err); + /* memset 0 to outAddr for security concern */ + tztrng_memset(outAddr, 0, *outLen); + *outLen = 0; + return Err; + } + + /* try to reduce the memcpy */ + if (requireBytes < sourceOutSizeBytes) { + tztrng_memcpy(outAddr, (uint8_t *)rndSrc_ptr, requireBytes); + requireBytes = 0; + } else { + tztrng_memcpy(outAddr, (uint8_t *)rndSrc_ptr, sourceOutSizeBytes); + requireBytes -= sourceOutSizeBytes; + } + + outAddr += sourceOutSizeBytes; + } + + /* Clear the rndWorkBuff to not leave entropy on the stack */ + tztrng_memset((uint8_t *)rndWorkBuff, 0, sizeof(rndWorkBuff)); + + return Err; +} + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/tztrng_pal.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/tztrng_pal.c new file mode 100644 index 00000000000..3b2dfae56a3 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/host/src/tztrng_lib/tztrng_pal.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* Copyright (c) 2017-2017, ARM, All Rights Reserved * +* SPDX-License-Identifier: Apache-2.0 * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* * +* You may obtain a copy of the License at * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* * +* See the License for the specific language governing permissions and * +* limitations under the License. * +******************************************************************************/ +#include "tztrng_defs.h" + +uint32_t CC_HalWaitInterrupt(void) +{ + uint32_t isr = 0; + uint32_t crngterr = 0; + uint32_t abort = 0; + + #ifdef CHECK_VN_AC_ERR + uint32_t vnerr = 0; + #endif + + /* Polling ISR value */ + do { + isr = CC_HAL_READ_REGISTER(DX_RNG_ISR_REG_OFFSET); + if (isr & 0x1 << DX_RNG_ISR_EHR_VALID_BIT_SHIFT) { + return 0; + } + + if (isr & 0x1 << DX_RNG_ISR_CRNGT_ERR_BIT_SHIFT) { + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, RNG_ICR), 0x1 << DX_RNG_ISR_CRNGT_ERR_BIT_SHIFT); + crngterr++; + TRNG_LOG_DEBUG("CRNGT error detected[%d]\n", (int)crngterr); + if (crngterr >= TRNG_MAX_CRNGT_ERRORS) + abort = 1; + } + + #ifdef CHECK_VN_AC_ERR + if (isr & 0x1 << DX_RNG_ISR_VN_ERR_BIT_SHIFT) { + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, RNG_ICR), 0x1 << DX_RNG_ISR_VN_ERR_BIT_SHIFT); + vnerr++; + TRNG_LOG_DEBUG("VN error detected[%d]\n", vnerr); + if (vnerr >= TRNG_MAX_VN_ERRORS) + abort = 1; + } + + if (isr & 0x1 << DX_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT) { + TRNG_LOG_DEBUG("AUTOCORR error detected\n"); + abort = 1; + } + #endif + + } while (!abort); + + TRNG_LOG_DEBUG("abort leave..\n"); + + return LLF_RND_CRNGT_TEST_FAIL_ERROR; +} + +/************************************************************************************/ +/** + * @brief The LLF_RND_TurnOffTrng stops the hardware random bits collection + * closes RND clocks and releases HW semaphore. + * + * @return CCError_t - On success CC_OK is returned, on failure a + * value MODULE_* as defined in ... + */ +void LLF_RND_TurnOffTrng(void) +{ + /* disable the RND source */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG,RND_SOURCE_ENABLE), LLF_RND_HW_RND_SRC_DISABLE_VAL); + + /* clear RNG interrupts */ + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(RNG, RNG_ICR), 0xFFFFFFFF); + + return; +} + +void tztrng_memcpy(uint8_t *dst, uint8_t *src, size_t size) +{ + size_t i; + for(i = 0; i < size; i++) + dst[i] = src[i]; +} + +void tztrng_memset(uint8_t *dst, uint8_t value, size_t size) +{ + size_t i; + for(i = 0; i < size; i++) + dst[i] = value; +} + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/mbed-os.py b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/mbed-os.py new file mode 100755 index 00000000000..595d04008db --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/mbed-os.py @@ -0,0 +1,101 @@ +#!/usr/bin/env python + +""" +Copyright (c) 2018 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +""" +This script removes the files inside the TZ-TRNG driver that are unused by +Mbed OS. +The TZ-TRNG driver is an open-source driver (Apache 2.0) available here: +https://github.com/ARM-software/TZ-TRNG + +The driver is used in Mbed OS in 800-90B TRNG mode. +It removes Makefiles, PDF, test files and FE-TRNG C files (the other TRNG mode +not used). + +After the script is executed, this driver can be succesfully integrated and +compiled in a Mbed OS project and the CC_TrngGetSource function can be called, +for example in a Mbed OS HAL implementation for a new target. + +This script needs to be executed at the root of the TZ-TRNG directory. +The .git folder and .gitignore file are not deleted by this script and should be +deleted manually. +""" + +import os +import sys + +# Files that this script will delete, if one of this files do not exist, the +# script will exit and do nothing. If all files of a directory have been +# deleted, then the directory will also be deleted. +FILES_TO_DELETE = ["TRNG_test.c", + "trustzone_trng_characterization_application_note_100685_0000_06_en.pdf", + "host/src/tests/tztrng_test/tztrng_test.c", + "host/src/tests/tztrng_test/Makefile", + "host/src/tests/tztrng_test/pal/tztrng_test_pal_api.h", + "host/src/tests/tztrng_test/pal/linux/tztrng_test_pal.c", + "host/src/tests/tztrng_test/pal/linux/tztrng_test_pal.h", + "host/src/tests/tztrng_test/pal/freertos/tztrng_test_pal.c", + "host/src/tests/tztrng_test/pal/freertos/tztrng_test_pal.h", + "host/src/tests/tztrng_test/tztrng_test.h", + "host/src/tests/tztrng_test/tztrng_test_arm.c", + "host/src/tztrng_lib/Makefile", + "host/src/tztrng_lib/llf_rnd_fetrng.c", + "host/Makefile.defs", + "host/Makefile.rules", + "host/Makefile.pal", + "host/Makefile.freertos", + "host/proj.cfg", + "build.props", + "proj.ext.cfg", + "trustzone_trng_software_integrators_manual_101049_0000_00_en.pdf"] + +def show_help_exit(): + print("mbed-os.py") + print("---------------------------------------------------------------") + print("This script removes the files inside the TZ-TRNG driver that") + print("are unused by Mbed OS. It needs to be executed at the root of") + print("the TZ-TRNG driver directory.") + print("---------------------------------------------------------------") + print("usage: ./mbed-os.py") + exit(1) + +def main(): + + # Check if the help flag has been entered + if len(sys.argv) > 1: + option = sys.argv[1] + if option == "-h" or option == "--help": + show_help_exit() + + # Check if all files exist + for file_to_delete in FILES_TO_DELETE: + if not os.path.exists(file_to_delete): + print("Error: file %s does not exist." % file_to_delete) + exit(2) + + # Delete all the files and the the empty directories + for file_to_delete in FILES_TO_DELETE: + dir_path = os.path.dirname(file_to_delete) + os.remove(file_to_delete) + # Check if the directory containing the file we just deleted has become + # empty and delete it if it is the case + # If dir_path is empty the file to delete is at the root + if dir_path != "" and os.listdir(dir_path) == []: + os.rmdir(dir_path) + +if __name__ == "__main__": + main() diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_env.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_env.h new file mode 100644 index 00000000000..5f2d7876daa --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_env.h @@ -0,0 +1,251 @@ +/****************************************************************************** + * Copyright (c) 2017-2017, ARM, All Rights Reserved * + * SPDX-License-Identifier: Apache-2.0 * + * * + * Licensed under the Apache License, Version 2.0 (the "License"); * + * you may not use this file except in compliance with the License. * + * * + * You may obtain a copy of the License at * + * http://www.apache.org/licenses/LICENSE-2.0 * + * * + * Unless required by applicable law or agreed to in writing, software * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * + * * + * See the License for the specific language governing permissions and * + * limitations under the License. * + ******************************************************************************/ + +#ifndef __DX_ZYNQ_ENV_H__ +#define __DX_ZYNQ_ENV_H__ + +// -------------------------------------- +// BLOCK: ENV_REGS +// -------------------------------------- +#define DX_ENV_PKA_DEBUG_MODE_REG_OFFSET 0x024UL +#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_SCAN_MODE_REG_OFFSET 0x030UL +#define DX_ENV_SCAN_MODE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SCAN_MODE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_ALLOW_SCAN_REG_OFFSET 0x034UL +#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_LOWER_MONITOR_ADDR_REG_ADDR 0x060UL +#define DX_ENV_CC_LOWER_MONITOR_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_LOWER_MONITOR_ADDR_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_UPPER_MONITOR_ADDR_REG_ADDR 0x070UL +#define DX_ENV_CC_UPPER_MONITOR_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_UPPER_MONITOR_ADDR_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_HOST_INT_REG_OFFSET 0x0A0UL +#define DX_ENV_CC_HOST_INT_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_HOST_INT_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_RST_N_REG_OFFSET 0x0A8UL +#define DX_ENV_CC_RST_N_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_RST_N_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_RST_OVERRIDE_REG_OFFSET 0x0ACUL +#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_POR_N_ADDR_REG_OFFSET 0x0E0UL +#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_BM_LOWER_BOUND_ADDR_REG_OFFSET 0x0F0UL +#define DX_ENV_CC_BM_LOWER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_LOWER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_BM_UPPER_BOUND_ADDR_REG_OFFSET 0x0F4UL +#define DX_ENV_CC_BM_UPPER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_UPPER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_BM_ENB_ADDR_REG_OFFSET 0x0F8UL +#define DX_ENV_CC_BM_ENB_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_ENB_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_COLD_RST_REG_OFFSET 0x0FCUL +#define DX_ENV_CC_COLD_RST_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_COLD_RST_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_BM_ERR_ACK_ADDR_REG_OFFSET 0x100UL +#define DX_ENV_CC_BM_ERR_ACK_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_BM_ERR_ACK_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_BM_CC_ERR_ADDR_REG_OFFSET 0x104UL +#define DX_ENV_BM_CC_ERR_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_BM_CC_ERR_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_DUMMY_ADDR_REG_OFFSET 0x108UL +#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_COUNTER_CLR_REG_OFFSET 0x118UL +#define DX_ENV_COUNTER_CLR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_COUNTER_CLR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_COUNTER_RD_REG_OFFSET 0x11CUL +#define DX_ENV_COUNTER_RD_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_COUNTER_RD_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_SECOND_BM_LOWER_BOUND_ADDR_REG_OFFSET 0x120UL +#define DX_ENV_CC_SECOND_BM_LOWER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_LOWER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_SECOND_BM_UPPER_BOUND_ADDR_REG_OFFSET 0x124UL +#define DX_ENV_CC_SECOND_BM_UPPER_BOUND_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_UPPER_BOUND_ADDR_VALUE_BIT_SIZE 0x14UL +#define DX_ENV_CC_SECOND_BM_ENB_ADDR_REG_OFFSET 0x128UL +#define DX_ENV_CC_SECOND_BM_ENB_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_ENB_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_SECOND_BM_ERR_ACK_ADDR_REG_OFFSET 0x12CUL +#define DX_ENV_CC_SECOND_BM_ERR_ACK_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_SECOND_BM_ERR_ACK_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_SECOND_BM_CC_ERR_ADDR_REG_OFFSET 0x130UL +#define DX_ENV_SECOND_BM_CC_ERR_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SECOND_BM_CC_ERR_ADDR_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_RNG_DEBUG_ENABLE_REG_OFFSET 0x430UL +#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_WARM_BOOT_REG_OFFSET 0x434UL +#define DX_ENV_CC_WARM_BOOT_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_WARM_BOOT_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CC_LCS_REG_OFFSET 0x43CUL +#define DX_ENV_CC_LCS_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_LCS_VALUE_BIT_SIZE 0x8UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_REG_OFFSET 0x440UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SHIFT 0x0UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SIZE 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SHIFT 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SIZE 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SHIFT 0x2UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SIZE 0x1UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SHIFT 0x3UL +#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SIZE 0x1UL +#define DX_ENV_DCU_EN_REG_OFFSET 0x444UL +#define DX_ENV_DCU_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_DCU_EN_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CC_LCS_IS_VALID_REG_OFFSET 0x448UL +#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_CRYPTOKEY_0_REG_OFFSET 0x458UL +#define DX_ENV_CRYPTOKEY_0_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_0_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_1_REG_OFFSET 0x45CUL +#define DX_ENV_CRYPTOKEY_1_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_1_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_2_REG_OFFSET 0x460UL +#define DX_ENV_CRYPTOKEY_2_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_2_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_3_REG_OFFSET 0x464UL +#define DX_ENV_CRYPTOKEY_3_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_3_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_4_REG_OFFSET 0x468UL +#define DX_ENV_CRYPTOKEY_4_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_4_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_5_REG_OFFSET 0x46CUL +#define DX_ENV_CRYPTOKEY_5_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_5_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_6_REG_OFFSET 0x470UL +#define DX_ENV_CRYPTOKEY_6_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_6_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_CRYPTOKEY_7_REG_OFFSET 0x474UL +#define DX_ENV_CRYPTOKEY_7_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_CRYPTOKEY_7_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_POWER_DOWN_REG_OFFSET 0x478UL +#define DX_ENV_POWER_DOWN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_POWER_DOWN_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_ROM_BANK_REG_OFFSET 0x47CUL +#define DX_ENV_ROM_BANK_BIT_SHIFT 0x0UL +#define DX_ENV_ROM_BANK_BIT_SIZE 0x1UL +#define DX_ENV_OTF_SECURE_BOOT_DONE_REG_OFFSET 0x480UL +#define DX_ENV_OTF_SECURE_BOOT_DONE_BIT_SHIFT 0x0UL +#define DX_ENV_OTF_SECURE_BOOT_DONE_BIT_SIZE 0x1UL +#define DX_ENV_DCU_H_EN_REG_OFFSET 0x484UL +#define DX_ENV_DCU_H_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_DCU_H_EN_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_VERSION_REG_OFFSET 0x488UL +#define DX_ENV_VERSION_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_VERSION_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_ROSC_WRITE_REG_OFFSET 0x48CUL +#define DX_ENV_ROSC_WRITE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_ROSC_WRITE_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_ROSC_ADDR_REG_OFFSET 0x490UL +#define DX_ENV_ROSC_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_ROSC_ADDR_VALUE_BIT_SIZE 0x8UL +#define DX_ENV_RESET_SESSION_KEY_REG_OFFSET 0x494UL +#define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SIZE 0x2UL +#define DX_ENV_SESSION_KEY_0_REG_OFFSET 0x4A0UL +#define DX_ENV_SESSION_KEY_0_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SESSION_KEY_0_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_SESSION_KEY_1_REG_OFFSET 0x4A4UL +#define DX_ENV_SESSION_KEY_1_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SESSION_KEY_1_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_SESSION_KEY_2_REG_OFFSET 0x4A8UL +#define DX_ENV_SESSION_KEY_2_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SESSION_KEY_2_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_SESSION_KEY_3_REG_OFFSET 0x4ACUL +#define DX_ENV_SESSION_KEY_3_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SESSION_KEY_3_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_SESSION_KEY_VALID_REG_OFFSET 0x4B0UL +#define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_DEBUG_EN_REG_OFFSET 0x4B4UL +#define DX_ENV_DEBUG_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_DEBUG_EN_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_SPIDEN_REG_OFFSET 0x4D0UL +#define DX_ENV_SPIDEN_BIT_SHIFT 0x0UL +#define DX_ENV_SPIDEN_BIT_SIZE 0x1UL +#define DX_ENV_AO_CCP_LCS_IS_SD_REG_OFFSET 0x4D4UL +#define DX_ENV_AO_CCP_LCS_IS_SD_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CCP_LCS_IS_SD_BIT_SIZE 0x1UL +#define DX_ENV_AXIM_USER_PARAMS_REG_OFFSET 0x600UL +#define DX_ENV_AXIM_ARUSER_PARAMS_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_AXIM_ARUSER_PARAMS_VALUE_BIT_SIZE 0x5UL +#define DX_ENV_AXIM_AWUSER_PARAMS_VALUE_BIT_SHIFT 0x5UL +#define DX_ENV_AXIM_AWUSER_PARAMS_VALUE_BIT_SIZE 0x5UL +#define DX_ENV_SECURITY_MODE_OVERRIDE_REG_OFFSET 0x604UL +#define DX_ENV_AWPROT_NS_BIT_SHIFT 0x0UL +#define DX_ENV_AWPROT_NS_BIT_SIZE 0x1UL +#define DX_ENV_AWPROT_NS_OVRD_BIT_SHIFT 0x1UL +#define DX_ENV_AWPROT_NS_OVRD_BIT_SIZE 0x1UL +#define DX_ENV_ARPROT_NS_BIT_SHIFT 0x2UL +#define DX_ENV_ARPROT_NS_BIT_SIZE 0x1UL +#define DX_ENV_ARPROT_NS_OVRD_BIT_SHIFT 0x3UL +#define DX_ENV_ARPROT_NS_OVRD_BIT_SIZE 0x1UL +#define DX_ENV_AO_CC_KPLT_0_REG_OFFSET 0x620UL +#define DX_ENV_AO_CC_KPLT_0_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KPLT_0_BIT_SIZE 0x20UL +#define DX_ENV_AO_CC_KPLT_1_REG_OFFSET 0x624UL +#define DX_ENV_AO_CC_KPLT_1_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KPLT_1_BIT_SIZE 0x20UL +#define DX_ENV_AO_CC_KPLT_2_REG_OFFSET 0x628UL +#define DX_ENV_AO_CC_KPLT_2_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KPLT_2_BIT_SIZE 0x20UL +#define DX_ENV_AO_CC_KPLT_3_REG_OFFSET 0x62CUL +#define DX_ENV_AO_CC_KPLT_3_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KPLT_3_BIT_SIZE 0x20UL +#define DX_ENV_AO_CC_KCST_0_REG_OFFSET 0x630UL +#define DX_ENV_AO_CC_KCST_0_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KCST_0_BIT_SIZE 0x20UL +#define DX_ENV_AO_CC_KCST_1_REG_OFFSET 0x634UL +#define DX_ENV_AO_CC_KCST_1_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KCST_1_BIT_SIZE 0x20UL +#define DX_ENV_AO_CC_KCST_2_REG_OFFSET 0x638UL +#define DX_ENV_AO_CC_KCST_2_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KCST_2_BIT_SIZE 0x20UL +#define DX_ENV_AO_CC_KCST_3_REG_OFFSET 0x63CUL +#define DX_ENV_AO_CC_KCST_3_BIT_SHIFT 0x0UL +#define DX_ENV_AO_CC_KCST_3_BIT_SIZE 0x20UL +// -------------------------------------- +// BLOCK: ENV_CC_MEMORIES +// -------------------------------------- +#define DX_ENV_FUSE_READY_REG_OFFSET 0x414UL +#define DX_ENV_FUSE_READY_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_FUSE_READY_VALUE_BIT_SIZE 0x1UL +//#define DX_ENV_FUSES_RAM_REG_OFFSET 0x800UL //Not connected in RAM controller +//#define DX_ENV_FUSES_RAM_VALUE_BIT_SHIFT 0x0UL +//#define DX_ENV_FUSES_RAM_VALUE_BIT_SIZE 0x20UL +#define DX_ENV_PERF_RAM_MASTER_REG_OFFSET 0x500UL +#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SIZE 0x1UL +#define DX_ENV_PERF_RAM_ADDR_HIGH4_REG_OFFSET 0x504UL +#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SIZE 0x2UL + +// -------------------------------------- +// BLOCK: ENV_PERF_RAM_BASE +// -------------------------------------- +#define DX_ENV_PERF_RAM_BASE_REG_OFFSET 0x000UL +#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SHIFT 0x0UL +#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SIZE 0x20UL + +#endif //__DX_RNG_H__ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_reg_base_host.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_reg_base_host.h new file mode 100644 index 00000000000..cfbcd903ecd --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_reg_base_host.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * Copyright (c) 2017-2017, ARM, All Rights Reserved * + * SPDX-License-Identifier: Apache-2.0 * + * * + * Licensed under the Apache License, Version 2.0 (the "License"); * + * you may not use this file except in compliance with the License. * + * * + * You may obtain a copy of the License at * + * http://www.apache.org/licenses/LICENSE-2.0 * + * * + * Unless required by applicable law or agreed to in writing, software * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * + * * + * See the License for the specific language governing permissions and * + * limitations under the License. * + ******************************************************************************/ + +#ifndef __DX_REG_BASE_HOST_H__ +#define __DX_REG_BASE_HOST_H__ + +/*! +@file +@brief This file contains general HW related definitions. +*/ + +/*! Identify platform: Xilinx Zynq7000 ZC706 */ +#define DX_PLAT_ZYNQ7000 1 +#define DX_PLAT_ZYNQ7000_ZC706 1 + +/*! SEP core clock frequency in MHz */ +#define DX_SEP_FREQ_MHZ 50 + +/*! Base address for Sansa Silicon-Secure registers. It must be modified to match the mapping of Sansa Silicon-Secure on the customer's * +* platform.*/ +#define DX_BASE_RNG 0x40000000 + +/*! Base address for FPGA environment registers */ +#define DX_BASE_ENV_REGS 0x80008000 + +#endif /*__DX_REG_BASE_HOST_H__*/ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_rng.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_rng.h new file mode 100644 index 00000000000..aab4d485d7b --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/TZ-TRNG/shared/hw/include/dx_rng.h @@ -0,0 +1,112 @@ +/****************************************************************************** + * Copyright (c) 2017-2017, ARM, All Rights Reserved * + * SPDX-License-Identifier: Apache-2.0 * + * * + * Licensed under the Apache License, Version 2.0 (the "License"); * + * you may not use this file except in compliance with the License. * + * * + * You may obtain a copy of the License at * + * http://www.apache.org/licenses/LICENSE-2.0 * + * * + * Unless required by applicable law or agreed to in writing, software * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * + * * + * See the License for the specific language governing permissions and * + * limitations under the License. * + ******************************************************************************/ + + #ifndef __DX_RNG_H__ +#define __DX_RNG_H__ + +// -------------------------------------- +// BLOCK: RNG +// -------------------------------------- +#define DX_RNG_IMR_REG_OFFSET 0x100UL +#define DX_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL +#define DX_RNG_IMR_EHR_VALID_INT_MASK_BIT_SIZE 0x1UL +#define DX_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL +#define DX_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SIZE 0x1UL +#define DX_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL +#define DX_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SIZE 0x1UL +#define DX_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL +#define DX_RNG_IMR_VN_ERR_INT_MASK_BIT_SIZE 0x1UL +#define DX_RNG_ISR_REG_OFFSET 0x104UL +#define DX_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL +#define DX_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL +#define DX_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL +#define DX_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL +#define DX_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL +#define DX_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL +#define DX_RNG_ISR_VN_ERR_BIT_SHIFT 0x3UL +#define DX_RNG_ISR_VN_ERR_BIT_SIZE 0x1UL +#define DX_RNG_ICR_REG_OFFSET 0x108UL +#define DX_RNG_ICR_EHR_VALID_BIT_SHIFT 0x0UL +#define DX_RNG_ICR_EHR_VALID_BIT_SIZE 0x1UL +#define DX_RNG_ICR_AUTOCORR_ERR_BIT_SHIFT 0x1UL +#define DX_RNG_ICR_AUTOCORR_ERR_BIT_SIZE 0x1UL +#define DX_RNG_ICR_CRNGT_ERR_BIT_SHIFT 0x2UL +#define DX_RNG_ICR_CRNGT_ERR_BIT_SIZE 0x1UL +#define DX_RNG_ICR_VN_ERR_BIT_SHIFT 0x3UL +#define DX_RNG_ICR_VN_ERR_BIT_SIZE 0x1UL +#define DX_TRNG_CONFIG_REG_OFFSET 0x10CUL +#define DX_TRNG_CONFIG_RND_SRC_SEL_BIT_SHIFT 0x0UL +#define DX_TRNG_CONFIG_RND_SRC_SEL_BIT_SIZE 0x2UL +#define DX_TRNG_VALID_REG_OFFSET 0x110UL +#define DX_TRNG_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_TRNG_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_EHR_DATA_0_REG_OFFSET 0x114UL +#define DX_EHR_DATA_0_VALUE_BIT_SHIFT 0x0UL +#define DX_EHR_DATA_0_VALUE_BIT_SIZE 0x20UL +#define DX_EHR_DATA_1_REG_OFFSET 0x118UL +#define DX_EHR_DATA_1_VALUE_BIT_SHIFT 0x0UL +#define DX_EHR_DATA_1_VALUE_BIT_SIZE 0x20UL +#define DX_EHR_DATA_2_REG_OFFSET 0x11CUL +#define DX_EHR_DATA_2_VALUE_BIT_SHIFT 0x0UL +#define DX_EHR_DATA_2_VALUE_BIT_SIZE 0x20UL +#define DX_EHR_DATA_3_REG_OFFSET 0x120UL +#define DX_EHR_DATA_3_VALUE_BIT_SHIFT 0x0UL +#define DX_EHR_DATA_3_VALUE_BIT_SIZE 0x20UL +#define DX_EHR_DATA_4_REG_OFFSET 0x124UL +#define DX_EHR_DATA_4_VALUE_BIT_SHIFT 0x0UL +#define DX_EHR_DATA_4_VALUE_BIT_SIZE 0x20UL +#define DX_EHR_DATA_5_REG_OFFSET 0x128UL +#define DX_EHR_DATA_5_VALUE_BIT_SHIFT 0x0UL +#define DX_EHR_DATA_5_VALUE_BIT_SIZE 0x20UL +#define DX_RND_SOURCE_ENABLE_REG_OFFSET 0x12CUL +#define DX_RND_SOURCE_ENABLE_VALUE_BIT_SHIFT 0x0UL +#define DX_RND_SOURCE_ENABLE_VALUE_BIT_SIZE 0x1UL +#define DX_SAMPLE_CNT1_REG_OFFSET 0x130UL +#define DX_SAMPLE_CNT1_VALUE_BIT_SHIFT 0x0UL +#define DX_SAMPLE_CNT1_VALUE_BIT_SIZE 0x20UL +#define DX_AUTOCORR_STATISTIC_REG_OFFSET 0x134UL +#define DX_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BIT_SHIFT 0x0UL +#define DX_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BIT_SIZE 0xEUL +#define DX_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BIT_SHIFT 0xEUL +#define DX_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BIT_SIZE 0x8UL +#define DX_TRNG_DEBUG_CONTROL_REG_OFFSET 0x138UL +#define DX_TRNG_DEBUG_CONTROL_VNC_BYPASS_BIT_SHIFT 0x1UL +#define DX_TRNG_DEBUG_CONTROL_VNC_BYPASS_BIT_SIZE 0x1UL +#define DX_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BIT_SHIFT 0x2UL +#define DX_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BIT_SIZE 0x1UL +#define DX_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BIT_SHIFT 0x3UL +#define DX_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BIT_SIZE 0x1UL +#define DX_RNG_SW_RESET_REG_OFFSET 0x140UL +#define DX_RNG_SW_RESET_VALUE_BIT_SHIFT 0x0UL +#define DX_RNG_SW_RESET_VALUE_BIT_SIZE 0x1UL +#define DX_RNG_BUSY_REG_OFFSET 0x1B8UL +#define DX_RNG_BUSY_RNG_BUSY_BIT_SHIFT 0x0UL +#define DX_RNG_BUSY_RNG_BUSY_BIT_SIZE 0x1UL +#define DX_RST_BITS_COUNTER_REG_OFFSET 0x1BCUL +#define DX_RST_BITS_COUNTER_VALUE_BIT_SHIFT 0x0UL +#define DX_RST_BITS_COUNTER_VALUE_BIT_SIZE 0x1UL +#define DX_RNG_BIST_CNTR_0_REG_OFFSET 0x1E0UL +#define DX_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BIT_SHIFT 0x0UL +#define DX_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BIT_SIZE 0x16UL +#define DX_RNG_BIST_CNTR_1_REG_OFFSET 0x1E4UL +#define DX_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BIT_SHIFT 0x0UL +#define DX_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BIT_SIZE 0x16UL +#define DX_RNG_BIST_CNTR_2_REG_OFFSET 0x1E8UL +#define DX_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BIT_SHIFT 0x0UL +#define DX_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BIT_SIZE 0x16UL +#endif //__DX_RNG_H__ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h index 57866628e02..bc073a30c4f 100755 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h @@ -75,6 +75,11 @@ struct analogin_s { uint16_t ctrl_register; /* Control bits with the channel identifier */ }; +/* This TRNG structure is not used by the HAL implementation. */ +struct trng_s { + uint8_t not_used; +}; + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/trng_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/trng_api.c new file mode 100644 index 00000000000..f546a3aa1e0 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/trng_api.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "trng_api.h" +#include "tztrng.h" + +#define BITS_PER_BYTE 8 +/* Base address of the TRNG peripheral */ +#define TRNG_BASE 0x4000F000 + +void trng_init(trng_t *obj) +{ + /* Initialization is made in the driver */ + (void)obj; +} + +void trng_free(trng_t *obj) +{ + /* The current implementation only contains a dummy version of TRNG */ + (void)obj; +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + uint32_t retval; + + (void)obj; + /* The TRNG driver expects a number of bits. */ + retval = CC_TrngGetSource(TRNG_BASE, output, output_length, + length * BITS_PER_BYTE); + + if (retval != 0) { + return -1; + } + return 0; +} diff --git a/targets/targets.json b/targets/targets.json index 5a8f36e17a6..4f464f5720a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2646,7 +2646,7 @@ "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "extra_labels": ["ARM_SSG", "CM3DS_MPS2"], "macros": ["CMSDK_CM3DS"], - "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC", "LOWPOWERTIMER"], + "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC", "LOWPOWERTIMER", "TRNG"], "release_versions": ["2", "5"], "copy_method": "mps2", "reset_method": "reboot.txt"