diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h
index 987ccbe6d37..cf086428440 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/PinNames.h
@@ -88,9 +88,9 @@ typedef enum {
} PinName;
typedef enum {
- PullUp = 0,
- PullDown = 3,
- PullNone = 2,
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
OpenDrain = 4
} PinMode;
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c
index 0858f38ca27..2c13747817c 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/can_api.c
@@ -164,7 +164,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
obj->dev->MOD &= ~(1);
// Enable NVIC if at least 1 interrupt is active
- if(LPC_CAN1->IER | LPC_CAN2->IER != 0) {
+ if((LPC_CAN1->IER | LPC_CAN2->IER) != 0) {
NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
NVIC_EnableIRQ(CAN_IRQn);
}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c
index 8737fce8f18..b51ea723413 100644
--- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c
@@ -962,3 +962,47 @@ void ethernet_set_link(int speed, int duplex) {
break;
}
}
+
+/*
+ * The Embedded Artists LPC4088 QuickStart Board has an eeprom with a unique
+ * 48 bit ID. This ID is used as MAC address.
+ */
+
+#include "i2c_api.h"
+
+static int _macRetrieved = 0;
+static char _macAddr[6] = {0x00,0x02,0xF7,0xF0,0x00,0x00};
+#define EEPROM_24AA02E48_ADDR (0xA0)
+
+void mbed_mac_address(char *mac) {
+
+ if (_macRetrieved == 0) {
+ char tmp[6];
+ i2c_t i2cObj;
+
+ i2c_init(&i2cObj, P0_27, P0_28);
+
+ do {
+ // the unique ID is at offset 0xFA
+ tmp[0] = 0xFA;
+ if (i2c_write(&i2cObj, EEPROM_24AA02E48_ADDR, tmp, 1, 1) != 1) {
+ break; // failed to write
+ }
+
+
+ if (i2c_read(&i2cObj, EEPROM_24AA02E48_ADDR, tmp, 6, 1) != 6) {
+ break; // failed to read
+ }
+
+ memcpy(_macAddr, tmp, 6);
+
+ } while(0);
+
+ // We always consider the MAC address to be retrieved even though
+ // reading from the eeprom failed. If it wasn't possible to read
+ // from eeprom the default address will be used.
+ _macRetrieved = 1;
+ }
+
+ memcpy(mac, _macAddr, 6);
+}
diff --git a/workspace_tools/export/codered.py b/workspace_tools/export/codered.py
index 16d42ec7b61..544cce2a8db 100644
--- a/workspace_tools/export/codered.py
+++ b/workspace_tools/export/codered.py
@@ -20,7 +20,7 @@
class CodeRed(Exporter):
NAME = 'CodeRed'
- TARGETS = ['LPC1768']
+ TARGETS = ['LPC1768', 'LPC4088']
TOOLCHAIN = 'GCC_CR'
def generate(self):
diff --git a/workspace_tools/export/codered_lpc4088_cproject.tmpl b/workspace_tools/export/codered_lpc4088_cproject.tmpl
new file mode 100644
index 00000000000..9b053510861
--- /dev/null
+++ b/workspace_tools/export/codered_lpc4088_cproject.tmpl
@@ -0,0 +1,1922 @@
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+ <?xml version="1.0" encoding="UTF-8"?>
+<TargetConfig>
+<Properties property_0="" property_2="LPC177x_8x_407x_8x_512.cfx" property_3="NXP" property_4="LPC4088" property_count="5" version="1"/>
+<infoList vendor="NXP"><info chip="LPC4088" flash_driver="LPC177x_8x_407x_8x_512.cfx" match_id="0x481D3F47" name="LPC4088" stub="crt_emu_cm3_nxp"><chip><name>LPC4088</name>
+<family>LPC407x_8x</family>
+<vendor>NXP (formerly Philips)</vendor>
+<reset board="None" core="Real" sys="Real"/>
+<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
+<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
+<memory id="RAM" type="RAM"/>
+<memory id="Periph" is_volatile="true" type="Peripheral"/>
+<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/>
+<memoryInstance derived_from="RAM" id="RamLoc64" location="0x10000000" size="0x10000"/>
+<memoryInstance derived_from="RAM" id="RamPeriph32" location="0x20000000" size="0x8000"/>
+<prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
+<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
+<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
+<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
+<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
+<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
+<peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x200000"/>
+<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x20080000"/>
+<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x20084000"/>
+<peripheralInstance derived_from="LCD" id="LCD" location="0x20088000"/>
+<peripheralInstance derived_from="USB" id="USB" location="0x2008c000"/>
+<peripheralInstance derived_from="CRC" id="CRC" location="0x20090000"/>
+<peripheralInstance derived_from="GPIO" id="GPIO" location="0x20098000"/>
+<peripheralInstance derived_from="EMC" id="EMC" location="0x2009c000"/>
+<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/>
+<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40004000"/>
+<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40008000"/>
+<peripheralInstance derived_from="UART0" id="UART0" location="0x4000c000"/>
+<peripheralInstance derived_from="UART1" id="UART1" location="0x40010000"/>
+<peripheralInstance derived_from="PWM0" id="PWM0" location="0x40014000"/>
+<peripheralInstance derived_from="PWM1" id="PWM1" location="0x40018000"/>
+<peripheralInstance derived_from="I2C0" id="I2C0" location="0x4001c000"/>
+<peripheralInstance derived_from="COMPARATOR" id="COMPARATOR" location="0x40020000"/>
+<peripheralInstance derived_from="RTC" id="RTC" location="0x40024000"/>
+<peripheralInstance derived_from="GPIOINT" id="GPIOINT" location="0x40028080"/>
+<peripheralInstance derived_from="IOCON" id="IOCON" location="0x4002c000"/>
+<peripheralInstance derived_from="SSP1" id="SSP1" location="0x40030000"/>
+<peripheralInstance derived_from="ADC" id="ADC" location="0x40034000"/>
+<peripheralInstance derived_from="CANAFRAM" id="CANAFRAM" location="0x40038000"/>
+<peripheralInstance derived_from="CANAF" id="CANAF" location="0x4003c000"/>
+<peripheralInstance derived_from="CCAN" id="CCAN" location="0x40040000"/>
+<peripheralInstance derived_from="CAN1" id="CAN1" location="0x40044000"/>
+<peripheralInstance derived_from="CAN2" id="CAN2" location="0x40048000"/>
+<peripheralInstance derived_from="I2C1" id="I2C1" location="0x4005c000"/>
+<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40088000"/>
+<peripheralInstance derived_from="DAC" id="DAC" location="0x4008c000"/>
+<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x40090000"/>
+<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x40094000"/>
+<peripheralInstance derived_from="UART2" id="UART2" location="0x40098000"/>
+<peripheralInstance derived_from="UART3" id="UART3" location="0x4009c000"/>
+<peripheralInstance derived_from="I2C2" id="I2C2" location="0x400a0000"/>
+<peripheralInstance derived_from="UART4" id="UART4" location="0x400a4000"/>
+<peripheralInstance derived_from="I2S" id="I2S" location="0x400a8000"/>
+<peripheralInstance derived_from="SSP2" id="SSP2" location="0x400ac000"/>
+<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400b8000"/>
+<peripheralInstance derived_from="QEI" id="QEI" location="0x400bc000"/>
+<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x400c0000"/>
+<peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x400fc000"/>
+</chip>
+<processor><name gcc_name="cortex-m4">Cortex-M4</name>
+<family>Cortex-M</family>
+</processor>
+<link href="nxp_lpc407x_8x_peripheral.xme" show="embed" type="simple"/>
+</info>
+</infoList>
+</TargetConfig>
+
+
+
diff --git a/workspace_tools/export/codered_lpc4088_project.tmpl b/workspace_tools/export/codered_lpc4088_project.tmpl
new file mode 100644
index 00000000000..42ef4384def
--- /dev/null
+++ b/workspace_tools/export/codered_lpc4088_project.tmpl
@@ -0,0 +1,84 @@
+
+
+ {{name}}
+ This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+ ?name?
+
+
+
+ org.eclipse.cdt.make.core.append_environment
+ true
+
+
+ org.eclipse.cdt.make.core.autoBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.buildArguments
+
+
+
+ org.eclipse.cdt.make.core.buildCommand
+ make
+
+
+ org.eclipse.cdt.make.core.buildLocation
+ ${workspace_loc:/{{name}}/Debug}
+
+
+ org.eclipse.cdt.make.core.cleanBuildTarget
+ clean
+
+
+ org.eclipse.cdt.make.core.contents
+ org.eclipse.cdt.make.core.activeConfigSettings
+
+
+ org.eclipse.cdt.make.core.enableAutoBuild
+ false
+
+
+ org.eclipse.cdt.make.core.enableCleanBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableFullBuild
+ true
+
+
+ org.eclipse.cdt.make.core.fullBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.stopOnError
+ true
+
+
+ org.eclipse.cdt.make.core.useDefaultBuildCmd
+ true
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.core.ccnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py
index 2859e2df7e5..d1f3432ad41 100644
--- a/workspace_tools/export/uvision4.py
+++ b/workspace_tools/export/uvision4.py
@@ -21,7 +21,7 @@
class Uvision4(Exporter):
NAME = 'uVision4'
TOOLCHAIN = 'ARM'
- TARGETS = ['LPC1768', 'LPC11U24', 'KL25Z', 'LPC1347', 'LPC1114']
+ TARGETS = ['LPC1768', 'LPC11U24', 'KL25Z', 'LPC1347', 'LPC1114', 'LPC4088']
FILE_TYPES = {
'c_sources':'1',
'cpp_sources':'8',
diff --git a/workspace_tools/export/uvision4_lpc4088.uvopt.tmpl b/workspace_tools/export/uvision4_lpc4088.uvopt.tmpl
new file mode 100644
index 00000000000..77400b267ce
--- /dev/null
+++ b/workspace_tools/export/uvision4_lpc4088.uvopt.tmpl
@@ -0,0 +1,230 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+
+
+
+ 0
+ 0
+
+
+
+ mbed NXP LPC1768
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 8
+
+
+ 0
+ Data Sheet
+ DATASHTS\NXP\LPC407x_8x\LPC408X_7X.pdf
+
+
+ 1
+ User Manual
+ DATASHTS\NXP\LPC407x_8x\UM10562.pdf
+
+
+ 2
+ Technical Reference Manual
+ datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF
+
+
+ 3
+ Generic User Guide
+ datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF
+
+
+
+ SARMCM3.DLL
+ -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 14
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ CMSIS_AGDI
+ -X"MBED CMSIS-DAP" -UA000000001 -O4559 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -FO15 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(313=-1,-1,-1,-1,0)(291=-1,-1,-1,-1,0)(302=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(330=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ UL2CM3
+ -UV0218BNE -O463 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000
+
+
+
+
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 3
+ 0
+
+
+ 0
+
+
+
+
+
+
+
+ src
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 8
+ 0
+ 0
+ 0
+ 0
+ 1
+ 7
+ 0
+ main.cpp
+ main.cpp
+ 0
+ 0
+
+
+
+
diff --git a/workspace_tools/export/uvision4_lpc4088.uvproj.tmpl b/workspace_tools/export/uvision4_lpc4088.uvproj.tmpl
new file mode 100644
index 00000000000..c33a436bf80
--- /dev/null
+++ b/workspace_tools/export/uvision4_lpc4088.uvproj.tmpl
@@ -0,0 +1,425 @@
+
+
+
+ 1.1
+
+ ###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+
+
+
+ NXP LPC4088
+ 0x4
+ ARM-ADS
+
+
+ LPC4088
+ NXP (founded by Philips)
+ IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2
+
+ "STARTUP\NXP\LPC407x_8x_177x_8x\startup_LPC407x_8x_177x_8x.s" ("NXP LPC407x_8x_177x_8x Startup Code")
+ UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000)
+ 6493
+ LPC407x_8x_177x_8x.h
+
+
+
+
+
+
+
+
+
+ SFD\NXP\LPC407x_8x_177x_8x\LPC408x_7x.SFR
+ 0
+
+
+
+ NXP\LPC407x_8x_177x_8x\
+ NXP\LPC407x_8x_177x_8x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ {{name}}
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 1
+ 0
+ fromelf --bin -o build\{{name}}_LPC4088.bin build\{{name}}.axf
+
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+
+
+ SARMCM3.DLL
+ -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+
+ 0
+ 14
+
+
+
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4105
+
+ BIN\CMSIS_AGDI.dll
+ "" ()
+
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M4"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 2
+ 1
+ 0
+ 8
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x10000000
+ 0x10000
+
+
+ 1
+ 0x0
+ 0x80000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x80000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x10000000
+ 0x10000
+
+
+ 0
+ 0x20000000
+ 0x8000
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+ --gnu
+ {% for s in symbols %} {{s}}, {% endfor %}
+
+ {% for path in include_paths %} {{path}}; {% endfor %}
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x10000000
+ {{scatter_file}}
+
+
+
+
+ {% for file in object_files %}
+ {{file}}
+ {% endfor %}
+
+
+
+
+
+
+
+
+
+ src
+
+ {% for file in source_files %}
+
+ {{file.name}}
+ {{file.type}}
+ {{file.path}}
+ {%if file.type == "1" %}
+
+
+
+
+ --c99
+
+
+
+
+ {% endif %}
+
+ {% endfor %}
+
+
+
+
+
+
+
+
diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py
index 877f1aeb302..cc1d6eeb356 100644
--- a/workspace_tools/export_test.py
+++ b/workspace_tools/export_test.py
@@ -76,9 +76,9 @@ def test_export(toolchain, target, expected_error=None):
setup_test_user_prj()
for toolchain, target in [
- ('uvision', 'LPC1768'), ('uvision', 'LPC11U24'), ('uvision', 'KL25Z'), ('uvision', 'LPC1347'), ('uvision', 'LPC1114'),
+ ('uvision', 'LPC1768'), ('uvision', 'LPC11U24'), ('uvision', 'KL25Z'), ('uvision', 'LPC1347'), ('uvision', 'LPC1114'), ('uvision', 'LPC4088'),
- ('codered', 'LPC1768'),
+ ('codered', 'LPC1768'), ('codered', 'LPC4088'),
# Linux path: /home/emimon01/bin/gcc-cs/bin/
# Windows path: "C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin/"