diff --git a/TESTS/mbed_platform/stats_sys/main.cpp b/TESTS/mbed_platform/stats_sys/main.cpp index ae3fb3e0c37..0fdbe3849ec 100644 --- a/TESTS/mbed_platform/stats_sys/main.cpp +++ b/TESTS/mbed_platform/stats_sys/main.cpp @@ -39,7 +39,7 @@ void test_sys_info() #if defined(__IAR_SYSTEMS_ICC__) TEST_ASSERT_EQUAL(IAR, stats.compiler_id); -#elif defined(__CC_ARM) +#elif defined(__ARMCC_VERSION) TEST_ASSERT_EQUAL(ARM, stats.compiler_id); #elif defined(__GNUC__) TEST_ASSERT_EQUAL(GCC_ARM, stats.compiler_id); diff --git a/features/storage/FEATURE_STORAGE/cfstore/configuration-store/configuration_store.h b/features/storage/FEATURE_STORAGE/cfstore/configuration-store/configuration_store.h index 7abc9e7aa36..d95e04b19ac 100644 --- a/features/storage/FEATURE_STORAGE/cfstore/configuration-store/configuration_store.h +++ b/features/storage/FEATURE_STORAGE/cfstore/configuration-store/configuration_store.h @@ -163,7 +163,7 @@ typedef struct _ARM_CFSTORE_STATUS { ARM_CFSTORE_HANDLE (__name) = (ARM_CFSTORE_HANDLE) (__name##_buf_cFsToRe); \ memset((__name##_buf_cFsToRe), 0, CFSTORE_HANDLE_BUFSIZE) -#if defined __MBED__ && (defined TOOLCHAIN_GCC_ARM || defined TOOLCHAIN_ARMC6) +#if defined __MBED__ && (defined TOOLCHAIN_GCC_ARM || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) /** @brief Helper macro to swap 2 handles, which is useful for the Find() idiom. */ #define CFSTORE_HANDLE_SWAP(__a_HaNdLe, __b_HaNdLe) \ do{ ARM_CFSTORE_HANDLE __temp_HaNdLe = (__a_HaNdLe); \ @@ -174,6 +174,7 @@ typedef struct _ARM_CFSTORE_STATUS { __asm volatile("" ::: "memory"); \ }while(0) + #elif defined __MBED__ && defined TOOLCHAIN_ARM /** @brief Helper macro to swap 2 handles, which is useful for the Find() idiom. */ #define CFSTORE_HANDLE_SWAP(__a_HaNdLe, __b_HaNdLe) \ diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp index 350e611d097..3e6cbba1fb5 100644 --- a/platform/mbed_retarget.cpp +++ b/platform/mbed_retarget.cpp @@ -55,7 +55,11 @@ static SingletonPtr _mutex; # define PREFIX(x) _sys##x # define OPEN_MAX _SYS_OPEN # ifdef __MICROLIB -# pragma import(__use_full_stdio) +# if __ARMCC_VERSION >= 6010050 +asm(" .global __use_full_stdio\n"); +# else +# pragma import(__use_full_stdio) +# endif # endif #elif defined(__ICCARM__) @@ -1251,7 +1255,7 @@ extern "C" WEAK caddr_t _sbrk(int incr) /* __HeapLimit is end of heap section */ if (new_heap > (uint32_t) &__HeapLimit) { errno = ENOMEM; - return (caddr_t) -1; + return (caddr_t) - 1; } heap = new_heap; diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h index e367c19276c..f202b052b0e 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h @@ -104,26 +104,26 @@ __STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) { /// Get xPSR Register - emulate M profile: SP_usr - (8*4) /// \return xPSR Register value #if defined(__CC_ARM) +#pragma push +#pragma arm static __asm uint32_t __get_PSP (void) { - arm sub sp, sp, #4 stm sp, {sp}^ pop {r0} sub r0, r0, #32 bx lr } +#pragma pop #else #ifdef __ICCARM__ __arm +#else +__attribute__((target("arm"))) #endif __STATIC_INLINE uint32_t __get_PSP (void) { register uint32_t ret; __ASM volatile ( -#ifndef __ICCARM__ - ".syntax unified\n\t" - ".arm\n\t" -#endif "sub sp,sp,#4\n\t" "stm sp,{sp}^\n\t" "pop {%[ret]}\n\t" diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct index 585b1d054f7..94fac30a5a6 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct @@ -53,11 +53,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address *(InRoot$$Sections) - .ANY (+RO) + *(+RO) } ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data - .ANY (+RW +ZI) + *(+RW +ZI) } ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct index 8249c3542a4..e53fcb4e6b8 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct @@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address *(InRoot$$Sections) - .ANY (+RO) + *(+RO) } ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data - .ANY (+RW +ZI) + *(+RW +ZI) } ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct index 8249c3542a4..e53fcb4e6b8 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct @@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address *(InRoot$$Sections) - .ANY (+RO) + *(+RO) } ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data - .ANY (+RW +ZI) + *(+RW +ZI) } ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct index 8249c3542a4..e53fcb4e6b8 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct @@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address *(InRoot$$Sections) - .ANY (+RO) + *(+RO) } ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data - .ANY (+RW +ZI) + *(+RW +ZI) } ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down } diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct index fa3de1650f0..50eb0c83c01 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct @@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE { LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address *(InRoot$$Sections) - .ANY (+RO) + *(+RO) } ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data - .ANY (+RW +ZI) + *(+RW +ZI) } ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_COMMON/softdevice/common/nrf_sdh_ble.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_COMMON/softdevice/common/nrf_sdh_ble.c index 990ba0af0b8..4ebf46e5513 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_COMMON/softdevice/common/nrf_sdh_ble.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_COMMON/softdevice/common/nrf_sdh_ble.c @@ -65,7 +65,7 @@ NRF_SECTION_SET_DEF(sdh_ble_observers, nrf_sdh_ble_evt_observer_t, NRF_SDH_BLE_O //lint -save -e10 -e19 -e40 -e27 Illegal character (0x24) -#if defined(__CC_ARM) +#if defined(__ARMCC_VERSION) extern uint32_t Image$$RW_IRAM1$$Base; uint32_t const * const m_ram_start = &Image$$RW_IRAM1$$Base; #elif defined(__ICCARM__) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section.h index 4ac2b3a4acd..83753e7ea6e 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section.h @@ -66,7 +66,7 @@ extern "C" { * param[in] section_name Name of the section. * @hideinitializer */ -#if defined(__CC_ARM) +#if defined(__ARMCC_VERSION) #define NRF_SECTION_START_ADDR(section_name) &CONCAT_2(section_name, $$Base) #elif defined(__GNUC__) @@ -82,7 +82,7 @@ extern "C" { * @param[in] section_name Name of the section. * @hideinitializer */ -#if defined(__CC_ARM) +#if defined(__ARMCC_VERSION) #define NRF_SECTION_END_ADDR(section_name) &CONCAT_2(section_name, $$Limit) #elif defined(__GNUC__) @@ -111,7 +111,7 @@ extern "C" { * @warning Data type must be word aligned to prevent padding. * @hideinitializer */ -#if defined(__CC_ARM) +#if defined(__ARMCC_VERSION) #define NRF_SECTION_DEF(section_name, data_type) \ extern data_type * CONCAT_2(section_name, $$Base); \ extern void * CONCAT_2(section_name, $$Limit) @@ -140,7 +140,7 @@ extern "C" { * @param[in] section_var Variable to register in the given section. * @hideinitializer */ -#if defined(__CC_ARM) +#if defined(__ARMCC_VERSION) #define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \ section_var __attribute__ ((section(STRINGIFY(section_name)))) __attribute__((used)) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section_iter.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section_iter.h index 61897c976bc..60cf0f6669b 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section_iter.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/libraries/experimental_section_vars/nrf_section_iter.h @@ -87,7 +87,7 @@ typedef struct typedef struct { nrf_section_set_t const * p_set; //!< Pointer to the appropriate section set. -#if !defined(__GNUC__) || defined(__CC_ARM) +#if !defined(__GNUC__) || defined(__ARMCC_VERSION) nrf_section_t const * p_section; //!< Pointer to the selected section. /**< * In case of GCC all sections in the set are sorted and diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h deleted file mode 100644 index d10ed67fc2e..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************//** - * @file mem_RZ_A1LU.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_RZ_A1LU_H -#define __MEM_RZ_A1LU_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// ROM Base Address <0x0-0xFFFFFFFF:8> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ - -/*--------------------- RAM Configuration ----------------------------------- - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00300000 -#define __NC_RAM_SIZE 0x00100000 -#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) -#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) - -#define __UND_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00008000 -#define __ABT_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x0000F000 -#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// TTB Base Address <0x0-0xFFFFFFFF:8> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x20000000 -#define __TTB_SIZE 0x00004000 - -#endif /* __MEM_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.S new file mode 100644 index 00000000000..b12d54d7255 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.S @@ -0,0 +1,151 @@ +;/****************************************************************************** +; * @file startup_RZ_A1H.S +; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series +; * +; * @note +; * +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +__UND_STACK_SIZE EQU 0x00000100 +__SVC_STACK_SIZE EQU 0x00008000 +__ABT_STACK_SIZE EQU 0x00000100 +__FIQ_STACK_SIZE EQU 0x00000100 +__IRQ_STACK_SIZE EQU 0x0000F000 + +USR_MODE EQU 0x10 ; User mode +FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode +IRQ_MODE EQU 0x12 ; Interrupt Request mode +SVC_MODE EQU 0x13 ; Supervisor mode +ABT_MODE EQU 0x17 ; Abort mode +UND_MODE EQU 0x1B ; Undefined Instruction mode +SYS_MODE EQU 0x1F ; System mode + + + PRESERVE8 + ARM + + AREA RESET, CODE, READONLY + +Vectors PROC + EXPORT Vectors + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler + + ENDP + + + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler + IMPORT SystemInit + IMPORT __main + + + ; Mask interrupts + CPSID if + + ; Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + ; Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register + ISB + + ; Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register + + ; Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + ; Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + ;Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + ; Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + ; Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + ; Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + ; Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + ; Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + ; Call SystemInit + IMPORT SystemInit + BL SystemInit + + ; Unmask interrupts + CPSIE if + + ; Call __main + IMPORT __main + BL __main + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c deleted file mode 100644 index 0d8f589779f..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c +++ /dev/null @@ -1,145 +0,0 @@ -/****************************************************************************** - * @file startup_RZ_A1LU.c - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "MBRZA1LU.h" -#include "mem_RZ_A1LU.h" - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((section("RESET"))); -void Reset_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -__ASM void Vectors(void) { - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__ASM void Reset_Handler(void) { - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 // Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exceptional mode - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - //Enter Undefined Instruction Mode and set its Stack Pointer - CPS #UND_MODE - MOV SP, R0 - SUB R0, R0, #__UND_STACK_SIZE - - // Enter Abort Mode and set its Stack Pointer - CPS #ABT_MODE - MOV SP, R0 - SUB R0, R0, #__ABT_STACK_SIZE - - // Enter FIQ Mode and set its Stack Pointer - CPS #FIQ_MODE - MOV SP, R0 - SUB R0, R0, #__FIQ_STACK_SIZE - - // Enter IRQ Mode and set its Stack Pointer - CPS #IRQ_MODE - MOV SP, R0 - SUB R0, R0, #__IRQ_STACK_SIZE - - // Enter Supervisor Mode and set its Stack Pointer - CPS #SVC_MODE - MOV SP, R0 - SUB R0, R0, #__SVC_STACK_SIZE - - // Enter System Mode to complete initialization and enter kernel - CPS #SYS_MODE - MOV SP, R0 - - // Call SystemInit - IMPORT SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __main - IMPORT __main - BL __main -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.S new file mode 100644 index 00000000000..7bfaa35e51b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.S @@ -0,0 +1,91 @@ +;/* +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-A Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + +MODE_SVC EQU 0x13 + + PRESERVE8 + THUMB + + AREA |.text|, CODE, READONLY + +IRQ_Handler PROC + EXPORT IRQ_Handler [WEAK] + + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + ENDP + + +Default_Handler PROC + EXPORT Undef_Handler [WEAK] + EXPORT SVC_Handler [WEAK] + EXPORT PAbt_Handler [WEAK] + EXPORT DAbt_Handler [WEAK] + EXPORT FIQ_Handler [WEAK] + +Undef_Handler +SVC_Handler +PAbt_Handler +DAbt_Handler +FIQ_Handler + + B . + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.c deleted file mode 100644 index 5557af1517b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2013-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: CMSIS-RTOS RTX - * Title: Cortex-A Exception handlers - * - * ----------------------------------------------------------------------------- - */ - -#include "core_ca.h" - -#define MODE_SVC 0x13 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} - -/*---------------------------------------------------------------------------- - Default IRQ Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -__WEAK __ASM void IRQ_Handler(void) { - IMPORT IRQ_GetActiveIRQ - IMPORT IRQ_GetHandler - IMPORT IRQ_EndOfInterrupt - - SUB LR, LR, #4 // Pre-adjust LR - SRSFD SP!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack - CPS #MODE_SVC // Change to SVC mode - PUSH {R0-R3, R12, LR} // Save APCS corruptible registers - - MOV R3, SP // Move SP into R3 - AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment - SUB SP, SP, R3 // Adjust stack - PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4) - - BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0 - MOV R4, R0 // Move interrupt ID to R4 - - BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID - CMP R0, #0 // Check if handler address is 0 - BEQ IRQ_End // If 0, end interrupt and return - - CPSIE i // Re-enable interrupts - BLX R0 // Call IRQ handler - CPSID i // Disable interrupts - -IRQ_End - MOV R0, R4 // Move interrupt ID to R0 - BLX IRQ_EndOfInterrupt // Signal end of interrupt - - POP {R3, R4} // Restore stack adjustment(R3) and user data(R4) - ADD SP, SP, R3 // Unadjust stack - - POP {R0-R3, R12, LR} // Restore stacked APCS registers - RFEFD SP! // Return from IRQ handler -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c index 6d2527824af..94f2c5108fd 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c @@ -38,12 +38,12 @@ const char * boot_loader = (char *)0x18000000; #if defined (__CC_ARM) #pragma arm section rodata = "BOOT_LOADER" const char boot_loader[] __attribute__((used)) = - +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +const char boot_loader[] __attribute__ ((section("BOOT_LOADER"), used)) = #elif defined (__ICCARM__) __root const char boot_loader[] @ 0x18000000 = #else const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) = - #endif { 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5, diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c index 6c3cd9f2b9a..93aa695b69f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c @@ -116,7 +116,7 @@ extern uint32_t Image$$RW_IRAM1$$Base; extern uint32_t Image$$TTB$$ZI$$Base; #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #elif defined( __ICCARM__ ) #else extern uint32_t Image$$RW_DATA_NC$$Base; @@ -127,7 +127,7 @@ extern uint32_t Image$$VECTORS$$Limit; extern uint32_t Image$$RO_DATA$$Limit; extern uint32_t Image$$RW_DATA$$Limit; extern uint32_t Image$$RW_IRAM1$$Limit; -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #else extern uint32_t Image$$RW_DATA_NC$$Limit; extern uint32_t Image$$ZI_DATA_NC$$Limit; @@ -145,7 +145,7 @@ extern uint32_t Image$$ZI_DATA_NC$$Limit; #define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #else #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) #define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) @@ -250,7 +250,7 @@ void MMU_CreateTranslationTable(void) MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); #elif defined ( __ICCARM__ ) MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h deleted file mode 100644 index e7ddd4f1cd5..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************//** - * @file mem_RZ_A1H.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_RZ_A1H_H -#define __MEM_RZ_A1H_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// ROM Base Address <0x0-0xFFFFFFFF:8> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ - -/*--------------------- RAM Configuration ----------------------------------- - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00A00000 -#define __NC_RAM_SIZE 0x00100000 -#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) -#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) - -#define __UND_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00008000 -#define __ABT_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x0000F000 -#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// TTB Base Address <0x0-0xFFFFFFFF:8> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x20000000 -#define __TTB_SIZE 0x00004000 - -#endif /* __MEM_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.S new file mode 100644 index 00000000000..b12d54d7255 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.S @@ -0,0 +1,151 @@ +;/****************************************************************************** +; * @file startup_RZ_A1H.S +; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series +; * +; * @note +; * +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +__UND_STACK_SIZE EQU 0x00000100 +__SVC_STACK_SIZE EQU 0x00008000 +__ABT_STACK_SIZE EQU 0x00000100 +__FIQ_STACK_SIZE EQU 0x00000100 +__IRQ_STACK_SIZE EQU 0x0000F000 + +USR_MODE EQU 0x10 ; User mode +FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode +IRQ_MODE EQU 0x12 ; Interrupt Request mode +SVC_MODE EQU 0x13 ; Supervisor mode +ABT_MODE EQU 0x17 ; Abort mode +UND_MODE EQU 0x1B ; Undefined Instruction mode +SYS_MODE EQU 0x1F ; System mode + + + PRESERVE8 + ARM + + AREA RESET, CODE, READONLY + +Vectors PROC + EXPORT Vectors + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler + + ENDP + + + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler + IMPORT SystemInit + IMPORT __main + + + ; Mask interrupts + CPSID if + + ; Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + ; Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register + ISB + + ; Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register + + ; Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + ; Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + ;Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + ; Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + ; Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + ; Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + ; Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + ; Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + ; Call SystemInit + IMPORT SystemInit + BL SystemInit + + ; Unmask interrupts + CPSIE if + + ; Call __main + IMPORT __main + BL __main + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c deleted file mode 100644 index 6e522d84c43..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c +++ /dev/null @@ -1,145 +0,0 @@ -/****************************************************************************** - * @file startup_RZ_A1H_H.c - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "MBRZA1H.h" -#include "mem_RZ_A1H.h" - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((section("RESET"))); -void Reset_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -__ASM void Vectors(void) { - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__ASM void Reset_Handler(void) { - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 // Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exceptional mode - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - //Enter Undefined Instruction Mode and set its Stack Pointer - CPS #UND_MODE - MOV SP, R0 - SUB R0, R0, #__UND_STACK_SIZE - - // Enter Abort Mode and set its Stack Pointer - CPS #ABT_MODE - MOV SP, R0 - SUB R0, R0, #__ABT_STACK_SIZE - - // Enter FIQ Mode and set its Stack Pointer - CPS #FIQ_MODE - MOV SP, R0 - SUB R0, R0, #__FIQ_STACK_SIZE - - // Enter IRQ Mode and set its Stack Pointer - CPS #IRQ_MODE - MOV SP, R0 - SUB R0, R0, #__IRQ_STACK_SIZE - - // Enter Supervisor Mode and set its Stack Pointer - CPS #SVC_MODE - MOV SP, R0 - SUB R0, R0, #__SVC_STACK_SIZE - - // Enter System Mode to complete initialization and enter kernel - CPS #SYS_MODE - MOV SP, R0 - - // Call SystemInit - IMPORT SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __main - IMPORT __main - BL __main -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S new file mode 100644 index 00000000000..7bfaa35e51b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S @@ -0,0 +1,91 @@ +;/* +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-A Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + +MODE_SVC EQU 0x13 + + PRESERVE8 + THUMB + + AREA |.text|, CODE, READONLY + +IRQ_Handler PROC + EXPORT IRQ_Handler [WEAK] + + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + ENDP + + +Default_Handler PROC + EXPORT Undef_Handler [WEAK] + EXPORT SVC_Handler [WEAK] + EXPORT PAbt_Handler [WEAK] + EXPORT DAbt_Handler [WEAK] + EXPORT FIQ_Handler [WEAK] + +Undef_Handler +SVC_Handler +PAbt_Handler +DAbt_Handler +FIQ_Handler + + B . + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.c deleted file mode 100644 index 5557af1517b..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2013-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: CMSIS-RTOS RTX - * Title: Cortex-A Exception handlers - * - * ----------------------------------------------------------------------------- - */ - -#include "core_ca.h" - -#define MODE_SVC 0x13 - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} - -/*---------------------------------------------------------------------------- - Default IRQ Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -__WEAK __ASM void IRQ_Handler(void) { - IMPORT IRQ_GetActiveIRQ - IMPORT IRQ_GetHandler - IMPORT IRQ_EndOfInterrupt - - SUB LR, LR, #4 // Pre-adjust LR - SRSFD SP!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack - CPS #MODE_SVC // Change to SVC mode - PUSH {R0-R3, R12, LR} // Save APCS corruptible registers - - MOV R3, SP // Move SP into R3 - AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment - SUB SP, SP, R3 // Adjust stack - PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4) - - BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0 - MOV R4, R0 // Move interrupt ID to R4 - - BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID - CMP R0, #0 // Check if handler address is 0 - BEQ IRQ_End // If 0, end interrupt and return - - CPSIE i // Re-enable interrupts - BLX R0 // Call IRQ handler - CPSID i // Disable interrupts - -IRQ_End - MOV R0, R4 // Move interrupt ID to R0 - BLX IRQ_EndOfInterrupt // Signal end of interrupt - - POP {R3, R4} // Restore stack adjustment(R3) and user data(R4) - ADD SP, SP, R3 // Unadjust stack - - POP {R0-R3, R12, LR} // Restore stacked APCS registers - RFEFD SP! // Return from IRQ handler -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c index bc50ddf4eec..a02064403af 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c @@ -38,12 +38,12 @@ const char * boot_loader = (char *)0x18000000; #if defined (__CC_ARM) #pragma arm section rodata = "BOOT_LOADER" const char boot_loader[] __attribute__((used)) = - +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +const char boot_loader[] __attribute__ ((section("BOOT_LOADER"), used)) = #elif defined (__ICCARM__) __root const char boot_loader[] @ 0x18000000 = #else const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) = - #endif { 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5, diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c index b1a5825fe05..46f7217eb3f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c @@ -116,7 +116,7 @@ extern uint32_t Image$$RW_IRAM1$$Base; extern uint32_t Image$$TTB$$ZI$$Base; #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #elif defined( __ICCARM__ ) #else extern uint32_t Image$$RW_DATA_NC$$Base; @@ -127,7 +127,7 @@ extern uint32_t Image$$VECTORS$$Limit; extern uint32_t Image$$RO_DATA$$Limit; extern uint32_t Image$$RW_DATA$$Limit; extern uint32_t Image$$RW_IRAM1$$Limit; -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #else extern uint32_t Image$$RW_DATA_NC$$Limit; extern uint32_t Image$$ZI_DATA_NC$$Limit; @@ -145,7 +145,7 @@ extern uint32_t Image$$ZI_DATA_NC$$Limit; #define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) #endif -#if defined( __CC_ARM ) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) #else #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) #define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) @@ -251,7 +251,7 @@ void MMU_CreateTranslationTable(void) MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); #elif defined ( __ICCARM__ ) MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h deleted file mode 100644 index 63feb75a7a6..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************//** - * @file mem_VK_RZ_A1H.h - * @brief Memory base and size definitions (used in scatter file) - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __MEM_VK_RZ_A1H_H -#define __MEM_VK_RZ_A1H_H - -/*---------------------------------------------------------------------------- - User Stack & Heap size definition - *----------------------------------------------------------------------------*/ -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- ROM Configuration ------------------------------------ -// -// ROM Configuration -// ROM Base Address <0x0-0xFFFFFFFF:8> -// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#ifdef RUN_FROM_SDRAM - #define __ROM_BASE 0x08000000 - #define __ROM_SIZE 0x02000000 - #define __VECTOR_BASE 0x08000000 - #define __DATA_BASE +0 ALIGN 0x100000 -#elif defined (RUN_FROM_SRAM) - #define __ROM_BASE 0x200A0000 - #define __ROM_SIZE 0x00960000 - #define __VECTOR_BASE 0x200A0000 - #define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS -#else - #define __ROM_BASE 0x18020000 - #define __ROM_SIZE 0x01FE0000 - #define __VECTOR_BASE 0x18020000 - #define __DATA_BASE 0x20020000 -#endif - -/*--------------------- RAM Configuration ----------------------------------- - *----------------------------------------------------------------------------*/ -#ifdef RUN_FROM_SDRAM -#define __RAM_BASE 0x08000000 -#define __RAM_SIZE 0x02000000 -#define __NC_RAM_SIZE 0x00200000 -#else -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00A00000 -#define __NC_RAM_SIZE 0x00100000 -#endif -#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) -#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) - -#define __UND_STACK_SIZE 0x00000100 -#define __SVC_STACK_SIZE 0x00008000 -#define __ABT_STACK_SIZE 0x00000100 -#define __FIQ_STACK_SIZE 0x00000100 -#define __IRQ_STACK_SIZE 0x0000F000 -#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) - -/*----------------------------------------------------------------------------*/ - -/*--------------------- TTB Configuration ------------------------------------ -// -// TTB Configuration -// TTB Base Address <0x0-0xFFFFFFFF:8> -// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> -// - *----------------------------------------------------------------------------*/ -#define __TTB_BASE 0x20000000 -#define __TTB_SIZE 0x00004000 - -#endif /* __MEM_VK_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S new file mode 100644 index 00000000000..b12d54d7255 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S @@ -0,0 +1,151 @@ +;/****************************************************************************** +; * @file startup_RZ_A1H.S +; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series +; * +; * @note +; * +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +__UND_STACK_SIZE EQU 0x00000100 +__SVC_STACK_SIZE EQU 0x00008000 +__ABT_STACK_SIZE EQU 0x00000100 +__FIQ_STACK_SIZE EQU 0x00000100 +__IRQ_STACK_SIZE EQU 0x0000F000 + +USR_MODE EQU 0x10 ; User mode +FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode +IRQ_MODE EQU 0x12 ; Interrupt Request mode +SVC_MODE EQU 0x13 ; Supervisor mode +ABT_MODE EQU 0x17 ; Abort mode +UND_MODE EQU 0x1B ; Undefined Instruction mode +SYS_MODE EQU 0x1F ; System mode + + + PRESERVE8 + ARM + + AREA RESET, CODE, READONLY + +Vectors PROC + EXPORT Vectors + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler + + ENDP + + + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler + IMPORT SystemInit + IMPORT __main + + + ; Mask interrupts + CPSID if + + ; Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + ; Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register + ISB + + ; Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register + + ; Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + ; Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + ;Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + ; Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + ; Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + ; Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + ; Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + ; Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + ; Call SystemInit + IMPORT SystemInit + BL SystemInit + + ; Unmask interrupts + CPSIE if + + ; Call __main + IMPORT __main + BL __main + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c deleted file mode 100644 index a83d7a235e4..00000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c +++ /dev/null @@ -1,162 +0,0 @@ -/****************************************************************************** - * @file startup_RZ_A1H_H.c - * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series - * @version V1.00 - * @date 10 Mar 2017 - * - * @note - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "VKRZA1H.h" -#include "mem_VK_RZ_A1H.h" - -/*---------------------------------------------------------------------------- - Definitions - *----------------------------------------------------------------------------*/ -#define USR_MODE 0x10 // User mode -#define FIQ_MODE 0x11 // Fast Interrupt Request mode -#define IRQ_MODE 0x12 // Interrupt Request mode -#define SVC_MODE 0x13 // Supervisor mode -#define ABT_MODE 0x17 // Abort mode -#define UND_MODE 0x1B // Undefined Instruction mode -#define SYS_MODE 0x1F // System mode - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Vectors (void) __attribute__ ((section("RESET"))); -void Reset_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector Table - *----------------------------------------------------------------------------*/ -__ASM void Vectors(void) { - IMPORT Undef_Handler - IMPORT SVC_Handler - IMPORT PAbt_Handler - IMPORT DAbt_Handler - IMPORT IRQ_Handler - IMPORT FIQ_Handler - LDR PC, =Reset_Handler - LDR PC, =Undef_Handler - LDR PC, =SVC_Handler - LDR PC, =PAbt_Handler - LDR PC, =DAbt_Handler - NOP - LDR PC, =IRQ_Handler - LDR PC, =FIQ_Handler -} - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__ASM void Reset_Handler(void) { - - // Mask interrupts - CPSID if - - // Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 // Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - - // Reset SCTLR Settings - MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register - ISB - - // Configure ACTLR - MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register - ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) - MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register - - // Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =Vectors - MCR p15, 0, R0, c12, c0, 0 - - // Setup Stack for each exceptional mode - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| - - //Enter Undefined Instruction Mode and set its Stack Pointer - CPS #UND_MODE - MOV SP, R0 - SUB R0, R0, #__UND_STACK_SIZE - - // Enter Abort Mode and set its Stack Pointer - CPS #ABT_MODE - MOV SP, R0 - SUB R0, R0, #__ABT_STACK_SIZE - - // Enter FIQ Mode and set its Stack Pointer - CPS #FIQ_MODE - MOV SP, R0 - SUB R0, R0, #__FIQ_STACK_SIZE - - // Enter IRQ Mode and set its Stack Pointer - CPS #IRQ_MODE - MOV SP, R0 - SUB R0, R0, #__IRQ_STACK_SIZE - - // Enter Supervisor Mode and set its Stack Pointer - CPS #SVC_MODE - MOV SP, R0 - SUB R0, R0, #__SVC_STACK_SIZE - - // Enter System Mode to complete initialization and enter kernel - CPS #SYS_MODE - MOV SP, R0 - - // Call SystemInit - IMPORT SystemInit - BL SystemInit - - // Unmask interrupts - CPSIE if - - // Call __main - IMPORT __main - BL __main -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) { - while(1); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S new file mode 100644 index 00000000000..7bfaa35e51b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S @@ -0,0 +1,91 @@ +;/* +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-A Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + +MODE_SVC EQU 0x13 + + PRESERVE8 + THUMB + + AREA |.text|, CODE, READONLY + +IRQ_Handler PROC + EXPORT IRQ_Handler [WEAK] + + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + ENDP + + +Default_Handler PROC + EXPORT Undef_Handler [WEAK] + EXPORT SVC_Handler [WEAK] + EXPORT PAbt_Handler [WEAK] + EXPORT DAbt_Handler [WEAK] + EXPORT FIQ_Handler [WEAK] + +Undef_Handler +SVC_Handler +PAbt_Handler +DAbt_Handler +FIQ_Handler + + B . + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c index f97edff22fc..37877ad9a0c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c @@ -116,7 +116,7 @@ extern uint32_t Image$$RW_IRAM1$$Base; extern uint32_t Image$$TTB$$ZI$$Base; #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #elif defined( __ICCARM__ ) #else extern uint32_t Image$$RW_DATA_NC$$Base; @@ -127,7 +127,7 @@ extern uint32_t Image$$VECTORS$$Limit; extern uint32_t Image$$RO_DATA$$Limit; extern uint32_t Image$$RW_DATA$$Limit; extern uint32_t Image$$RW_IRAM1$$Limit; -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #else extern uint32_t Image$$RW_DATA_NC$$Limit; extern uint32_t Image$$ZI_DATA_NC$$Limit; @@ -145,7 +145,7 @@ extern uint32_t Image$$ZI_DATA_NC$$Limit; #define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) #else #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) #define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) @@ -251,7 +251,7 @@ void MMU_CreateTranslationTable(void) MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); #endif -#if defined( __CC_ARM ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); #elif defined ( __ICCARM__ ) MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c index ba24d29d9b7..6cca0ef32e0 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c @@ -40,7 +40,7 @@ #define STREG_BUSY_BIT (0x01u) /* SR.[0]BUSY Erase/Write In Progress (RO) */ /* Definition of the base address for the MMU translation table */ -#if defined(__CC_ARM) || defined(__GNUC__) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) extern uint32_t Image$$TTB$$ZI$$Base; #define TTB ((uint32_t)&Image$$TTB$$ZI$$Base) /* using linker symbol */ #elif defined(__ICCARM__) diff --git a/targets/TARGET_RENESAS/mbed_rtx.h b/targets/TARGET_RENESAS/mbed_rtx.h index 08336e26837..203b1b1b32c 100644 --- a/targets/TARGET_RENESAS/mbed_rtx.h +++ b/targets/TARGET_RENESAS/mbed_rtx.h @@ -18,7 +18,7 @@ #include -#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE) +#if defined(TARGET_RENESAS) #if defined(__ARMCC_VERSION) extern uint32_t Image$$ARM_LIB_STACK$$Base[]; @@ -34,6 +34,7 @@ #else #error "no toolchain defined" #endif + #endif #endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar deleted file mode 100644 index f49e930c649..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar deleted file mode 100644 index 2bae8e26b55..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar deleted file mode 100644 index fcf6f3519ad..00000000000 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar and /dev/null differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar new file mode 100644 index 00000000000..26aa29f3cc6 Binary files /dev/null and b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar new file mode 100644 index 00000000000..140e255509b Binary files /dev/null and b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar new file mode 100644 index 00000000000..3e878840a7e Binary files /dev/null and b/targets/TARGET_WICED/TOOLCHAIN_ARMC6/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar differ diff --git a/targets/targets.json b/targets/targets.json index 278cd63b03f..bee11e25e62 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1327,7 +1327,7 @@ "KW24D": { "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4", - "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "supported_toolchains": ["ARMC5", "GCC_ARM", "IAR"], "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"], "is_disk_virtual": true, "macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"], @@ -7840,7 +7840,7 @@ "inherits": ["Target"], "macros": ["MBED_MPU_CUSTOM"], "default_toolchain": "GCC_ARM", - "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "supported_toolchains": ["GCC_ARM", "IAR", "ARMC5"], "core": "Cortex-M4F", "OUTPUT_EXT": "hex", "device_has": [ @@ -7886,7 +7886,7 @@ "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "supported_form_factors": ["ARDUINO"], - "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"], "release_versions": ["5"], "extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"], "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"], @@ -7903,7 +7903,7 @@ "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "device_has_remove": ["ANALOGOUT"], - "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"], "release_versions": ["5"], "extra_labels_add": ["PSOC6_02", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"], "macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"], @@ -7933,7 +7933,7 @@ }, "CY8CKIT_062_4343W": { "inherits": ["MCU_PSOC6_M4"], - "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"], "release_versions": ["5"], "features": ["BLE"], "supported_form_factors": ["ARDUINO"], @@ -7952,7 +7952,7 @@ "CYW943012P6EVB_01": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], - "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"], "release_versions": ["5"], "extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW43012", "CORDIO"], "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"], @@ -8251,7 +8251,7 @@ "detect_code": ["1703"], "macros_add": ["GD32E10X"], "release_versions": ["5"] - }, + }, "TT_M4G9": { "inherits": ["Target"], "core": "Cortex-M4", @@ -8281,5 +8281,9 @@ "detect_code": ["8013"], "release_versions": ["5"], "bootloader_supported": true + }, + "__build_tools_metadata__": { + "version": "1", + "public": false } } diff --git a/tools/build_api.py b/tools/build_api.py index c7eb9503e87..ceb00141569 100755 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -122,11 +122,26 @@ def add_result_to_report(report, result): report[target][toolchain][id_name].append(result_wrap) def get_toolchain_name(target, toolchain_name): - if toolchain_name == "ARM": - if CORE_ARCH[target.core] == 8: - return "ARMC6" - elif getattr(target, "default_toolchain", None) == "uARM": - return "uARM" + if int(target.build_tools_metadata["version"]) > 0: + if toolchain_name == "ARM" or toolchain_name == "ARMC6" : + if("ARM" in target.supported_toolchains or "ARMC6" in target.supported_toolchains): + return "ARMC6" + elif ("ARMC5" in target.supported_toolchains): + if toolchain_name == "ARM": + return "ARM" #note that returning ARM here means, use ARMC5 toolchain + else: + return "ARMC6" #ARMC6 explicitly specified by user, try ARMC6 anyway although the target doesnt explicitly specify ARMC6, as ARMC6 is our default ARM toolchain + elif toolchain_name == "uARM": + if ("ARMC5" in target.supported_toolchains): + return "uARM" #use ARM_MICRO to use AC5+microlib + else: + return "ARMC6" #use AC6+microlib + else: + if toolchain_name == "ARM": + if CORE_ARCH[target.core] == 8: + return "ARMC6" + elif getattr(target, "default_toolchain", None) == "uARM": + return "uARM" return toolchain_name @@ -176,8 +191,8 @@ def is_official_target(target_name, version): if hasattr(target, 'release_versions') \ and version in target.release_versions: if version == '2': - # For version 2, either ARM or uARM toolchain support is required - required_toolchains = set(['ARM', 'uARM']) + # For version 2, one of the ARM toolchains(ARM, ARMC6, ARMC5 or uARM) support is required + required_toolchains = set(['ARM', 'ARMC5', 'ARMC6', 'uARM']) if not len(required_toolchains.intersection( set(target.supported_toolchains))) > 0: @@ -194,6 +209,7 @@ def is_official_target(target_name, version): # For version 5, ARM, GCC_ARM, and IAR toolchain support is required required_toolchains = [ set(['ARM', 'GCC_ARM']), + set(['ARMC5', 'GCC_ARM']), set(['ARMC6']) ] supported_toolchains = set(target.supported_toolchains) @@ -235,8 +251,8 @@ def is_official_target(target_name, version): return result, reason -def transform_release_toolchains(toolchains, version): - """ Given a list of toolchains and a release version, return a list of +def transform_release_toolchains(target, version): + """ Given a release version and target, return a list of only the supported toolchains for that release Positional arguments: @@ -244,11 +260,19 @@ def transform_release_toolchains(toolchains, version): version - The release version string. Should be a string contained within RELEASE_VERSIONS """ - if version == '5': - return ['ARM', 'GCC_ARM', 'IAR'] + if int(target.build_tools_metadata["version"]) > 0: + if version == '5': + if 'ARMC5' in target.supported_toolchains: + return ['ARMC5', 'GCC_ARM', 'IAR'] + else: + return ['ARM', 'ARMC6', 'GCC_ARM', 'IAR'] + else: + return target.supported_toolchains else: - return toolchains - + if version == '5': + return ['ARM', 'GCC_ARM', 'IAR'] + else: + return target.supported_toolchains def get_mbed_official_release(version): """ Given a release version string, return a tuple that contains a target @@ -267,7 +291,7 @@ def get_mbed_official_release(version): [ TARGET_MAP[target].name, tuple(transform_release_toolchains( - TARGET_MAP[target].supported_toolchains, version)) + TARGET_MAP[target], version)) ] ) for target in TARGET_NAMES \ if (hasattr(TARGET_MAP[target], 'release_versions') @@ -284,13 +308,25 @@ def get_mbed_official_release(version): return mbed_official_release -ARM_COMPILERS = ("ARM", "ARMC6", "uARM") def target_supports_toolchain(target, toolchain_name): - if toolchain_name in ARM_COMPILERS: - return any(tc in target.supported_toolchains for tc in ARM_COMPILERS) + if int(target.build_tools_metadata["version"]) > 0: + if toolchain_name in target.supported_toolchains: + return True + else: + if(toolchain_name == "ARM"): + #we cant find ARM, see if one ARMC5, ARMC6 or uARM listed + return any(tc in target.supported_toolchains for tc in ("ARMC5","ARMC6","uARM")) + if(toolchain_name == "ARMC6"): + #we did not find ARMC6, but check for ARM is listed + return "ARM" in target.supported_toolchains + #return False in other cases + return False else: - return toolchain_name in target.supported_toolchains - + ARM_COMPILERS = ("ARM", "ARMC6", "uARM") + if toolchain_name in ARM_COMPILERS: + return any(tc in target.supported_toolchains for tc in ARM_COMPILERS) + else: + return toolchain_name in target.supported_toolchains def prepare_toolchain(src_paths, build_dir, target, toolchain_name, macros=None, clean=False, jobs=1, @@ -321,12 +357,19 @@ def prepare_toolchain(src_paths, build_dir, target, toolchain_name, # If the configuration object was not yet created, create it now config = config or Config(target, src_paths, app_config=app_config) target = config.target + if not target_supports_toolchain(target, toolchain_name): raise NotSupportedException( "Target {} is not supported by toolchain {}".format( target.name, toolchain_name)) - toolchain_name = get_toolchain_name(target, toolchain_name) + selected_toolchain_name = get_toolchain_name(target, toolchain_name) + + #If a target supports ARMC6 and we want to build UARM with it, + #then set the default_toolchain to uARM to link AC6 microlib. + if(selected_toolchain_name == "ARMC6" and toolchain_name == "uARM"): + target.default_toolchain = "uARM" + toolchain_name = selected_toolchain_name try: cur_tc = TOOLCHAIN_CLASSES[toolchain_name] @@ -965,7 +1008,13 @@ def build_mbed_libs(target, toolchain_name, clean=False, macros=None, Return - True if target + toolchain built correctly, False if not supported """ - toolchain_name = get_toolchain_name(target, toolchain_name) + selected_toolchain_name = get_toolchain_name(target, toolchain_name) + + #If a target supports ARMC6 and we want to build UARM with it, + #then set the default_toolchain to uARM to link AC6 microlib. + if(selected_toolchain_name == "ARMC6" and toolchain_name == "uARM"): + target.default_toolchain = "uARM" + toolchain_name = selected_toolchain_name if report is not None: start = time() @@ -1207,6 +1256,11 @@ def mcu_toolchain_matrix(verbose_html=False, platform_filter=None, unique_supported_toolchains = get_unique_supported_toolchains( release_targets) + #Add ARMC5 column as well to the matrix to help with showing which targets are in ARMC5 + #ARMC5 is not a toolchain class but yet we use that as a toolchain id in supported_toolchains in targets.json + #capture that info in a separate column + unique_supported_toolchains.append('ARMC5') + prepend_columns = ["Target"] + ["mbed OS %s" % x for x in RELEASE_VERSIONS] # All tests status table print @@ -1249,8 +1303,7 @@ def mcu_toolchain_matrix(verbose_html=False, platform_filter=None, (unique_toolchain == "ARMC6" and "ARM" in tgt_obj.supported_toolchains) or (unique_toolchain == "ARM" and - "ARMC6" in tgt_obj.supported_toolchains and - CORE_ARCH[tgt_obj.core] == 8)): + "ARMC6" in tgt_obj.supported_toolchains)): text = "Supported" perm_counter += 1 else: diff --git a/tools/export/cdt/__init__.py b/tools/export/cdt/__init__.py index 21e8a157507..64c3361662b 100644 --- a/tools/export/cdt/__init__.py +++ b/tools/export/cdt/__init__.py @@ -114,6 +114,14 @@ class EclipseGcc(Eclipse, GccArm): class EclipseArmc5(Eclipse, Armc5): LOAD_EXE = False NAME = "Eclipse-Armc5" + + @classmethod + def is_target_supported(cls, target_name): + target = TARGET_MAP[target_name] + if int(target.build_tools_metadata["version"]) > 0: + return "ARMC5" in target.supported_toolchains; + else: + return True class EclipseIAR(Eclipse, IAR): LOAD_EXE = True diff --git a/tools/export/makefile/__init__.py b/tools/export/makefile/__init__.py index 830c2cb252c..c71aac04505 100644 --- a/tools/export/makefile/__init__.py +++ b/tools/export/makefile/__init__.py @@ -273,12 +273,45 @@ class Armc5(Arm): NAME = 'Make-ARMc5' TOOLCHAIN = "ARM" PREPROCESS_ASM = True + + @classmethod + def is_target_supported(cls, target_name): + target = TARGET_MAP[target_name] + + if int(target.build_tools_metadata["version"]) > 0: + #Although toolchain name is set to ARM above we should check for ARMC5 for 5.12/onwards + if "ARMC5" not in target.supported_toolchains: + return False + + return apply_supported_whitelist( + cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target) class Armc6(Arm): """ARM Compiler 6 (armclang) specific generic makefile target""" NAME = 'Make-ARMc6' TOOLCHAIN = "ARMC6" - + + @classmethod + def is_target_supported(cls, target_name): + target = TARGET_MAP[target_name] + + if int(target.build_tools_metadata["version"]) > 0: + if not (len(set(target.supported_toolchains).intersection( + set(["ARM", "ARMC6"]))) > 0): + return False + + if not apply_supported_whitelist( + cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target): + #ARMC6 is not in the list, but also check for ARM as ARM represents ARMC6 for 5.12/onwards + #and still keep cls.TOOLCHAIN as ARMC6 as thats the toolchain we want to use + return apply_supported_whitelist( + "ARM", cls.POST_BINARY_WHITELIST, target) + else: + return True + else: + return apply_supported_whitelist( + cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target) + class IAR(Makefile): """IAR specific makefile target""" diff --git a/tools/export/uvision/__init__.py b/tools/export/uvision/__init__.py index 4a2a114ed2f..55ceab74424 100644 --- a/tools/export/uvision/__init__.py +++ b/tools/export/uvision/__init__.py @@ -315,9 +315,15 @@ class UvisionArmc5(Uvision): @classmethod def is_target_supported(cls, target_name): target = TARGET_MAP[target_name] - if not (set(target.supported_toolchains).intersection( - set(["ARM", "uARM"]))): - return False + if int(target.build_tools_metadata["version"]) > 0: + #Just check for ARMC5 as ARMC5 must be there irrespective of whether uARM is there or not if the target is staying with ARMC5 + if "ARMC5" not in target.supported_toolchains: + return False + else: + if not (set(target.supported_toolchains).intersection( + set(["ARM", "uARM"]))): + return False + if not DeviceCMSIS.check_supported(target_name): return False if "Cortex-A" in target.core: @@ -338,9 +344,14 @@ class UvisionArmc6(Uvision): @classmethod def is_target_supported(cls, target_name): target = TARGET_MAP[target_name] - if not (set(target.supported_toolchains).intersection( - set(["ARMC6"]))): - return False + if int(target.build_tools_metadata["version"]) > 0: + if not len(set(target.supported_toolchains).intersection( + set(["ARM", "ARMC6"]))) > 0: + return False + else: + if "ARMC6" not in target.supported_toolchains: + return False + if not DeviceCMSIS.check_supported(target_name): return False if "Cortex-A" in target.core: diff --git a/tools/targets/REALTEK_RTL8195AM.py b/tools/targets/REALTEK_RTL8195AM.py index a4eb02510fa..a8da29d7248 100644 --- a/tools/targets/REALTEK_RTL8195AM.py +++ b/tools/targets/REALTEK_RTL8195AM.py @@ -84,7 +84,7 @@ def find_symbol(toolchain, mapfile, symbol): HEX = '0x0{,8}(?P[0-9A-Fa-f]{8})' if toolchain == "GCC_ARM": SYM = re.compile(r'^\s+' + HEX + r'\s+' + symbol + '\r?$') - elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]: + elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO", "ARMC6"]: SYM = re.compile(r'^\s+' + HEX + r'\s+0x[0-9A-Fa-f]{8}\s+Code.*\s+i\.' + symbol + r'\s+.*$') elif toolchain == "IAR": SYM = re.compile(r'^' + symbol + r'\s+' + HEX + '\s+.*$') diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 567c6380cc1..6c7fbc642c7 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -103,6 +103,7 @@ def wrapper(*args, **kwargs): # need to be computed differently than regular attributes CUMULATIVE_ATTRIBUTES = ['extra_labels', 'macros', 'device_has', 'features', 'components'] +default_build_tools_metadata = {u'version':0, u'public':False} def get_resolution_order(json_data, target_name, order, level=0): """ Return the order in which target descriptions are searched for @@ -125,6 +126,9 @@ def get_resolution_order(json_data, target_name, order, level=0): def target(name, json_data): """Construct a target object""" + if name.startswith("_"): + raise Exception("Invalid target name '%s' specified, target name should not start with '_'" % name) + try: resolution_order = get_resolution_order(json_data, name, []) except KeyError as exc: @@ -132,11 +136,13 @@ def target(name, json_data): "target {} has an incomplete target definition".format(name) ), exc) resolution_order_names = [tgt for tgt, _ in resolution_order] + return Target(name=name, json_data={key: value for key, value in json_data.items() if key in resolution_order_names}, resolution_order=resolution_order, - resolution_order_names=resolution_order_names) + resolution_order_names=resolution_order_names, + build_tools_metadata=json_data.get("__build_tools_metadata__", default_build_tools_metadata)) def generate_py_target(new_targets, name): """Add one or more new target(s) represented as a Python dictionary @@ -151,9 +157,10 @@ def generate_py_target(new_targets, name): total_data = {} total_data.update(new_targets) total_data.update(base_targets) + return target(name, total_data) -class Target(namedtuple("Target", "name json_data resolution_order resolution_order_names")): +class Target(namedtuple("Target", "name json_data resolution_order resolution_order_names build_tools_metadata")): """An object to represent a Target (MCU/Board)""" # Default location of the 'targets.json' file diff --git a/tools/test/build_api/build_api_test.py b/tools/test/build_api/build_api_test.py index 376d0ea000a..be26b6e16d4 100755 --- a/tools/test/build_api/build_api_test.py +++ b/tools/test/build_api/build_api_test.py @@ -30,8 +30,11 @@ Tests for build_api.py """ make_mock_target = namedtuple( - "Target", "init_hooks name features core supported_toolchains") - + "Target", "init_hooks name features core supported_toolchains build_tools_metadata") +#Add ARMC5 to the supported_toolchains list as ARMC5 actually refers ARM Compiler 5 and is needed by ARM/ARM_STD classes when it checks for supported toolchains +TOOLCHAINS.add("ARMC5") +#Make a mock build_tools_metadata +mock_build_tools_metadata = {u'version':0, u'public':False} class BuildApiTests(unittest.TestCase): """ @@ -92,7 +95,7 @@ def test_prepare_toolchain_app_config(self, mock_config_init): """ app_config = "app_config" mock_target = make_mock_target(lambda _, __ : None, - "Junk", [], "Cortex-M3", TOOLCHAINS) + "Junk", [], "Cortex-M3", TOOLCHAINS, mock_build_tools_metadata) mock_config_init.return_value = namedtuple( "Config", "target has_regions name")(mock_target, False, None) @@ -111,7 +114,7 @@ def test_prepare_toolchain_no_app_config(self, mock_config_init): :return: """ mock_target = make_mock_target(lambda _, __ : None, - "Junk", [], "Cortex-M3", TOOLCHAINS) + "Junk", [], "Cortex-M3", TOOLCHAINS, mock_build_tools_metadata) mock_config_init.return_value = namedtuple( "Config", "target has_regions name")(mock_target, False, None) diff --git a/tools/test/toolchains/api_test.py b/tools/test/toolchains/api_test.py index f8989cf211d..d663973e1a6 100644 --- a/tools/test/toolchains/api_test.py +++ b/tools/test/toolchains/api_test.py @@ -41,9 +41,17 @@ ALPHABET = [char for char in printable if char not in [u'.', u'/', u'\\']] +#Create a global test target +test_target_map = TARGET_MAP["K64F"] +#We have to add ARMC5,UARM here to supported_toolchains, otherwise the creation of ARM class would fail as it won't find ARMC5 entry in supported_toolchains +#We also have to add uARM, cause, ARM_MICRO class would check for both uARM and ARMC5 in supported_toolchains(as ARM_MICRO represents ARMC5+Micro). +#And do this globally here so all tests can use this +test_target_map.supported_toolchains.append("ARMC5") +test_target_map.supported_toolchains.append("uARM") + @patch('tools.toolchains.arm.run_cmd') -def test_arm_version_check(_run_cmd): +def test_armc5_version_check(_run_cmd): set_targets_json_location() _run_cmd.return_value = (""" Product: ARM Compiler 5.06 @@ -51,7 +59,10 @@ def test_arm_version_check(_run_cmd): Tool: armcc [4d3621] """, "", 0) notifier = MockNotifier() - toolchain = TOOLCHAIN_CLASSES["ARM"](TARGET_MAP["K64F"], notify=notifier) + target_map = TARGET_MAP["K64F"] + #We have to add ARMC5 here to supported_toolchains, otherwise the creation of ARM class would fail as it wont find ARMC5 entry in supported_toolchains + target_map.supported_toolchains.append("ARMC5") + toolchain = TOOLCHAIN_CLASSES["ARM"](target_map, notify=notifier) toolchain.version_check() assert notifier.messages == [] _run_cmd.return_value = (""" @@ -69,6 +80,20 @@ def test_arm_version_check(_run_cmd): toolchain.version_check() assert len(notifier.messages) == 1 +@patch('tools.toolchains.arm.run_cmd') +def test_armc6_version_check(_run_cmd): + set_targets_json_location() + notifier = MockNotifier() + print(TARGET_MAP["K64F"]) + toolchain = TOOLCHAIN_CLASSES["ARMC6"](TARGET_MAP["K64F"], notify=notifier) + print(toolchain) + _run_cmd.return_value = (""" + Product: ARM Compiler 6.11 Professional + Component: ARM Compiler 6.11 + Tool: armclang [5d3b4200] + """, "", 0) + toolchain.version_check() + assert notifier.messages == [] @patch('tools.toolchains.iar.run_cmd') def test_iar_version_check(_run_cmd): @@ -141,7 +166,7 @@ def test_toolchain_profile_c(profile, source_file): set_targets_json_location() with patch('os.mkdir') as _mkdir: for _, tc_class in TOOLCHAIN_CLASSES.items(): - toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile, + toolchain = tc_class(test_target_map, build_profile=profile, notify=MockNotifier()) toolchain.inc_md5 = "" toolchain.build_dir = "" @@ -173,7 +198,7 @@ def test_toolchain_profile_cpp(profile, source_file): to_compile = os.path.join(*filename) with patch('os.mkdir') as _mkdir: for _, tc_class in TOOLCHAIN_CLASSES.items(): - toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile, + toolchain = tc_class(test_target_map, build_profile=profile, notify=MockNotifier()) toolchain.inc_md5 = "" toolchain.build_dir = "" @@ -205,7 +230,7 @@ def test_toolchain_profile_asm(profile, source_file): to_compile = os.path.join(*filename) with patch('os.mkdir') as _mkdir: for _, tc_class in TOOLCHAIN_CLASSES.items(): - toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile, + toolchain = tc_class(test_target_map, build_profile=profile, notify=MockNotifier()) toolchain.inc_md5 = "" toolchain.build_dir = "" @@ -225,7 +250,7 @@ def test_toolchain_profile_asm(profile, source_file): parameter) for name, Class in TOOLCHAIN_CLASSES.items(): - CLS = Class(TARGET_MAP["K64F"], notify=MockNotifier()) + CLS = Class(test_target_map, notify=MockNotifier()) assert name == CLS.name or name == LEGACY_TOOLCHAIN_NAMES[CLS.name] @given(fixed_dictionaries({ @@ -245,7 +270,7 @@ def test_toolchain_profile_ld(profile, source_file): with patch('os.mkdir') as _mkdir,\ patch('tools.toolchains.mbedToolchain.default_cmd') as _dflt_cmd: for _, tc_class in TOOLCHAIN_CLASSES.items(): - toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile, + toolchain = tc_class(test_target_map, build_profile=profile, notify=MockNotifier()) toolchain.RESPONSE_FILES = False toolchain.inc_md5 = "" @@ -264,7 +289,7 @@ def test_toolchain_profile_ld(profile, source_file): parameter) for name, Class in TOOLCHAIN_CLASSES.items(): - CLS = Class(TARGET_MAP["K64F"], notify=MockNotifier()) + CLS = Class(test_target_map, notify=MockNotifier()) assert name == CLS.name or name == LEGACY_TOOLCHAIN_NAMES[CLS.name] diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 945bad5bee5..82cfcdce664 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -342,9 +342,13 @@ def __init__(self, target, notify=None, macros=None, build_profile=None, build_dir=None): ARM.__init__(self, target, notify, macros, build_dir=build_dir, build_profile=build_profile) - if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)): - raise NotSupportedException("ARM/uARM compiler support is required for ARM build") - + if int(target.build_tools_metadata["version"]) > 0: + #check only for ARMC5 because ARM_STD means using ARMC5, and thus supported_toolchains must include ARMC5 + if "ARMC5" not in target.supported_toolchains: + raise NotSupportedException("ARM compiler 5 support is required for ARM build") + else: + if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)): + raise NotSupportedException("ARM/uARM compiler support is required for ARM build") class ARM_MICRO(ARM): PATCHED_LIBRARY = False @@ -353,13 +357,20 @@ def __init__(self, target, notify=None, macros=None, silent=False, extra_verbose=False, build_profile=None, build_dir=None): target.default_toolchain = "uARM" + + if int(target.build_tools_metadata["version"]) > 0: + #At this point we already know that we want to use ARMC5+Microlib, so check for if they are supported + #For, AC6+Microlib we still use ARMC6 class + if not set(("ARMC5","uARM")).issubset(set(target.supported_toolchains)): + raise NotSupportedException("ARM/uARM compiler support is required for ARM build") + else: + if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)): + raise NotSupportedException("ARM/uARM compiler support is required for ARM build") ARM.__init__(self, target, notify, macros, build_dir=build_dir, - build_profile=build_profile) - if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)): - raise NotSupportedException("ARM/uARM compiler support is required for ARM build") + build_profile=build_profile) class ARMC6(ARM_STD): - OFFICIALLY_SUPPORTED = False + OFFICIALLY_SUPPORTED = True SHEBANG = "#! armclang -E --target=arm-arm-none-eabi -x c" SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD", @@ -378,8 +389,26 @@ def __init__(self, target, *args, **kwargs): raise NotSupportedException( "this compiler does not support the core %s" % target.core) - if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)): - raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build") + if int(target.build_tools_metadata["version"]) > 0: + if not set(("ARM", "ARMC6", "uARM")).intersection(set(target.supported_toolchains)): + raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build") + else: + if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)): + raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build") + + if getattr(target, "default_toolchain", "ARMC6") == "uARM": + if "-DMBED_RTOS_SINGLE_THREAD" not in self.flags['common']: + self.flags['common'].append("-DMBED_RTOS_SINGLE_THREAD") + if "-D__MICROLIB" not in self.flags['common']: + self.flags['common'].append("-D__MICROLIB") + if "--library_type=microlib" not in self.flags['ld']: + self.flags['ld'].append("--library_type=microlib") + if "-Wl,--library_type=microlib" not in self.flags['c']: + self.flags['c'].append("-Wl,--library_type=microlib") + if "-Wl,--library_type=microlib" not in self.flags['cxx']: + self.flags['cxx'].append("-Wl,--library_type=microlib") + if "--library_type=microlib" not in self.flags['asm']: + self.flags['asm'].append("--library_type=microlib") core = target.core if CORE_ARCH[target.core] == 8: @@ -456,7 +485,10 @@ def __init__(self, target, *args, **kwargs): self.elf2bin = join(TOOLCHAIN_PATHS["ARMC6"], "fromelf") def _get_toolchain_labels(self): - return ["ARM", "ARM_STD", "ARMC6"] + if getattr(self.target, "default_toolchain", "ARM") == "uARM": + return ["ARM", "ARM_MICRO", "ARMC6"] + else: + return ["ARM", "ARM_STD", "ARMC6"] def parse_dependencies(self, dep_path): return mbedToolchain.parse_dependencies(self, dep_path) @@ -471,8 +503,13 @@ def get_config_option(self, config_header): return ["-include", config_header] def get_compile_options(self, defines, includes, for_asm=False): + opts = ['-D%s' % d for d in defines] - opts.extend(["-I%s" % i for i in includes if i]) + if self.RESPONSE_FILES: + opts += ['@{}'.format(self.get_inc_file(includes))] + else: + opts += ["-I%s" % i for i in includes if i] + config_header = self.get_config_header() if config_header: opts.extend(self.get_config_option(config_header))