From cd9db9824e236e2f2feeabd38ebf66db48c08ed2 Mon Sep 17 00:00:00 2001 From: Aaron Christiansen Date: Tue, 19 Mar 2024 23:06:24 +0000 Subject: [PATCH] Let's pick this back up! Fix on latest nightly by replacing `drain_filter` with `extract_if` https://github.com/rust-lang/rust/issues/43244 --- lang/lib/backend-core/src/lib.rs | 2 +- lang/lib/backend-core/src/reg_alloc.rs | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lang/lib/backend-core/src/lib.rs b/lang/lib/backend-core/src/lib.rs index c088602..a3839b1 100644 --- a/lang/lib/backend-core/src/lib.rs +++ b/lang/lib/backend-core/src/lib.rs @@ -1,6 +1,6 @@ //! Language backend targeting the Delta Null's processor soft-core. -#![feature(drain_filter)] +#![feature(extract_if)] use codegen::FunctionGenerator; use delta_null_core_assembler::{BuildError, AssemblyItem}; diff --git a/lang/lib/backend-core/src/reg_alloc.rs b/lang/lib/backend-core/src/reg_alloc.rs index cc0b4b8..f4e90fe 100644 --- a/lang/lib/backend-core/src/reg_alloc.rs +++ b/lang/lib/backend-core/src/reg_alloc.rs @@ -44,9 +44,9 @@ pub fn allocate(func: &Function, cfg: &ControlFlowGraph, liveness: &LivenessAnal // function - it makes accessing them easier! let parameter_passing_registers = [GPR::R0, GPR::R1, GPR::R2, GPR::R3]; for (var, reg) in func.arguments.iter().zip(parameter_passing_registers) { - free_registers.drain_filter(|r| r == ®); + free_registers.extract_if(|r| r == ®).for_each(|_| ()); mapping.insert(*var, Allocation::Register(reg)); - internals_by_increasing_start.drain_filter(|(v, _)| v == &var); + internals_by_increasing_start.extract_if(|(v, _)| v == &var).for_each(|_| ()); } let mut active = vec![];