pfe.t2t

= Packet Forwarding Engine (PFE) =[pfe]

Processor engines (PE):

|| PE ID | PE name ||
| 0 | CLASS0 |
| 1 | CLASS1 |
| 2 | CLASS2 |
| 3 | CLASS3 |
| 4 | CLASS4 |
| 5 | CLASS5 |
| 6 | TMU0 |
| 7 | TMU1 |
| 8 | TMU2 |
| 9 | TMU3 |
| 10 | UTIL |

The //Class// PEs are responsible for //class//ifying packets.

The TMU PEs are responsible for scheduling packets and shaping traffic.

The Util PE is responsible for all the other tasks.

== CBUS (common bus?) memory map ==[pfe_cbus]

The CBUS is shared by the ARM and all PEs.

Warning: All CBUS accesses from the ARM require the PFE_SYS clock to be
running (bit 3 of [AXI_CLK_CNTRL_1 #clkcore_regs_axi_clk_cntrl1] set).

Warning: ARM data accesses to the CBUS are byte-swapped on a 4 bytes boundary.
That means that reading from 32-bit CBUS registers from the ARM directly
returns the value in little-endian byte order. However, this becomes an issue
when accessing memories, such as the LMEM, because every group of 4 bytes will
be byte-swapped, even on non 32 bit accesses.

|| Seen from | CBUS base address ||
| ARM | 0x9c000000 |
| Any PE | 0xc0000000 |

|| Base offset in CBUS | Size | Size (w/o mirrors) | Description ||
| 0x200000 | 0x10000 | ? | [EMAC1 #pfe_emac] |
| 0x210000 | 0x10000 | ? | [EGPI1 #pfe_gpi] |
| 0x220000 | 0x10000 | ? | [EMAC2 #pfe_emac] |
| 0x230000 | 0x10000 | ? | [EGPI2 #pfe_gpi] |
| 0x240000 | 0x10000 | 0x800 | [BMU1 #pfe_bmu] |
| 0x250000 | 0x10000 | 0x800 | [BMU2 #pfe_bmu] |
| 0x260000 | 0x10000 | ? | ARB |
| 0x270000 | 0x10000 | ? | DDR_CONFIG |
| 0x280000 | 0x10000 | ? | [HIF #pfe_hif] |
| 0x290000 | 0x10000 | ? | [HGPI #pfe_gpi] |
| 0x300000 | 0x10000 | ? | LMEM |
| 0x310000 | 0x10000 | ? | [TMU_CSR #pfe_tmu_csr] |
| 0x320000 | 0x10000 | ? | [CLASS_CSR #pfe_class_csr] |
| 0x330000 | 0x10000 | ? | [EMAC3 #pfe_emac] |
| 0x340000 | 0x10000 | ? | [EGPI3 #pfe_gpi] |
| 0x350000 | 0x10000 | ? | [HIF_NOCPY #pfe_hif_nocpy] |
| 0x360000 | 0x10000 | ? | [UTIL_CSR #pfe_util_csr] |
| 0x370000 | 0x10000 | ? | CBUS_GPT |

Note: Do not attempt to perform a byte access at address 0xffff of a
peripheral as it will cause CBUS to hang. Instead, perform a 16-bit access at
address 0xfffe.

== Class PE memory map ==[pfe_class_memmap]

All addresses are given for the Class PE address space.

|| Region | Size (w/o mirrors) | Description ||
| 0x00000000-0x0000ffff | 0x2000 | DMEM (per PE data memory) |
| 0x00010000-0x0001ffff | 0x8000 | PMEM (per PE program memory)
| 0x00020000-0x85ffffff | ? | DDR + ACP + IRAM |
| 0xc0000000-0xc0ffffff | ? | CBUS |
| 0xc1000000-0xc1ffffff | ? | Class APB bus |
| 0xc2000000-0xc2ffffff | ? | Class AHB1 bus |
| 0xc3000000-0xc3ffffff | ? | Class AHB2 bus |

=== Class APB bus map ===[pfe_class_apb]

|| Region | Size (w/o mirrors) | Description ||
| 0xc1000000-0xc100ffff | ? | GPT (General Purpose Timer) |
| 0xc1010000-0xc101ffff | ? | UART |
| 0xc1020000-0xc102ffff | ? | PERG |
| 0xc1030000-0xc103ffff | ? | EFET |

=== Class AHB1 bus map ===[pfe_class_ahb1]

|| Region | Size (w/o mirrors) | Description ||
| 0xc2030000-0xc203ffff | ? | MAC hash |
| 0xc2050000-0xc205ffff | ? | VLAN hash |

=== Class AHB2 bus map ===[pfe_class_ahb2]

|| Region | Size (w/o mirrors) | Description ||
| 0xc3010000-0xc301ffff | 0x8000 | PE LMEM |
| 0xc3020000-0xc302ffff | ? | CCU |

== TMU PE memory map ==[pfe_tmu_memmap]

All addresses are given for the TMU PE address space.

|| Region | Size (w/o mirrors) | Description ||
| 0x00000000-0x0000ffff | 0x800 | DMEM (per PE data memory) |
| 0x00010000-0x0001ffff | 0x2000 | PMEM (per PE program memory)
| 0x00020000-0x85ffffff | ? | DDR + ACP + IRAM (not confirmed) |
| 0xc0000000-0xc0ffffff | ? | CBUS |
| 0xc1000000-0xc1ffffff | ? | TMU APB bus |

=== TMU APB bus map ===[pfe_tmu_apb]

|| Region | Size (w/o mirrors) | Description ||
| 0xc1000000-0xc100ffff | ? | GPT (General Purpose Timer) |
| 0xc1010000-0xc101ffff | ? | UART |
| 0xc1020000-0xc102ffff | ? | SHAPER0 |
| 0xc1030000-0xc103ffff | ? | SHAPER1 |
| 0xc1040000-0xc104ffff | ? | SHAPER2 |
| 0xc1050000-0xc105ffff | ? | SHAPER3 |
| 0xc1060000-0xc106ffff | ? | SHAPER4 |
| 0xc1070000-0xc107ffff | ? | SHAPER5 |
| 0xc1080000-0xc108ffff | ? | SHAPER6 |
| 0xc1090000-0xc109ffff | ? | SHAPER7 |
| 0xc10a0000-0xc10affff | ? | SHAPER8 |
| 0xc10b0000-0xc10bffff | ? | SHAPER9 |
| 0xc11c0000-0xc11cffff | ? | SCHED0 |
| 0xc11d0000-0xc11dffff | ? | SCHED1 |
| 0xc11e0000-0xc11effff | ? | SCHED2 |
| 0xc11f0000-0xc11fffff | ? | SCHED3 |
| 0xc1200000-0xc120ffff | ? | SCHED4 |
| 0xc1210000-0xc121ffff | ? | SCHED5 |
| 0xc1220000-0xc122ffff | ? | SCHED6 |
| 0xc1230000-0xc123ffff | ? | SCHED7 |
| 0xc1260000-0xc126ffff | ? | PHY_QUEUE |
| 0xc1270000-0xc127ffff | ? | SHAPER_STATUS |

== Util PE memory map ==[pfe_util_memmap]

All addresses are given for the Util PE address space.

|| Region | Size (w/o mirrors) | Description ||
| 0x00000000-0x0000ffff | 0x2000 | DMEM (per PE data memory) |
| 0x00020000-0x85ffffff | ? | DDR + ACP + IRAM |
| 0xc0000000-0xc0ffffff | ? | CBUS |
| 0xc1000000-0xc1ffffff | ? | Util APB bus |

=== Util APB bus map ===[pfe_util_apb]

|| Region | Size (w/o mirrors) | Description ||
| 0xc1000000-0xc100ffff | ? | GPT (General Purpose Timer) |
| 0xc1010000-0xc101ffff | ? | UART |
| 0xc1020000-0xc102ffff | ? | EAPE |
| 0xc1030000-0xc103ffff | ? | INQ |
| 0xc1040000-0xc104ffff | ? | EFET1 |
| 0xc1050000-0xc105ffff | ? | EFET2 |
| 0xc1060000-0xc106ffff | ? | EFET3 |

%!include:pfe_emac.t2t

%!include:pfe_gpi.t2t

%!include:pfe_bmu.t2t

%!include:pfe_hif.t2t

%!include:pfe_tmu_csr.t2t

%!include:pfe_class_csr.t2t

%!include:pfe_hif_nocpy.t2t

%!include:pfe_util_csr.t2t

== CBUS general purpose timer (CBUS_GPT) ==


== eSi-RISC architecture ==

The PE cores are implementation of an (32 bit?) eSi-RISC core configured in
Harvard architecture.


== Traffic/Time Management/Multiplexing Unit PE (TMU) ==

eSi-RISC core. Requires firmware.

The TMU does traffic shaping and scheduling.

== Classifier PE (CLASS) ==

eSi-RISC core. Requires firmware.


== UTIL PE (UTIL or UPE) ==

eSi-RISC core. Requires firmware.

Utility PE. Does all tasks that do not fit the other PEs.