From 8ed3e27fdfc9a419d85468403303bdcee55af78c Mon Sep 17 00:00:00 2001
From: Agustin Borgna <agustin.borgna@quantinuum.com>
Date: Thu, 22 Jun 2023 13:57:53 +0100
Subject: [PATCH] s/EdgeKind::Const/EdgeKind::Static/

---
 src/builder/build_traits.rs | 2 +-
 src/hugr.rs                 | 2 +-
 src/hugr/validate.rs        | 6 ++++--
 src/ops/constant.rs         | 2 +-
 src/ops/module.rs           | 4 ++--
 src/types.rs                | 6 +++---
 6 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/builder/build_traits.rs b/src/builder/build_traits.rs
index 9a673580d..e45e2cb45 100644
--- a/src/builder/build_traits.rs
+++ b/src/builder/build_traits.rs
@@ -603,7 +603,7 @@ enum ValueKind {
 fn get_value_kind(base: &Hugr, src: Node, src_offset: Port) -> ValueKind {
     let wire_kind = base.get_optype(src).port_kind(src_offset).unwrap();
     match wire_kind {
-        EdgeKind::Const(_) => ValueKind::Const,
+        EdgeKind::Static(_) => ValueKind::Const,
         EdgeKind::Value(simple_type) => match simple_type {
             SimpleType::Classic(_) => ValueKind::Classic,
             SimpleType::Linear(typ) => ValueKind::Linear(typ),
diff --git a/src/hugr.rs b/src/hugr.rs
index 2131147d0..ecab032a2 100644
--- a/src/hugr.rs
+++ b/src/hugr.rs
@@ -114,7 +114,7 @@ impl Hugr {
                 let optype = self.op_types.get(node);
                 let offset = self.graph.port_offset(port).unwrap();
                 match optype.port_kind(offset).unwrap() {
-                    EdgeKind::Const(ty) => {
+                    EdgeKind::Static(ty) => {
                         PortStyle::new(html_escape::encode_text(&format!("{}", ty)))
                     }
                     EdgeKind::Value(ty) => {
diff --git a/src/hugr/validate.rs b/src/hugr/validate.rs
index c09d0e02d..4002771f2 100644
--- a/src/hugr/validate.rs
+++ b/src/hugr/validate.rs
@@ -228,7 +228,9 @@ impl<'a> ValidationContext<'a> {
         // Input ports and output linear ports must always be connected
         let mut links = self.hugr.graph.port_links(port_index).peekable();
         let must_be_connected = match dir {
-            Direction::Incoming => port_kind.is_linear() || matches!(port_kind, EdgeKind::Const(_)),
+            Direction::Incoming => {
+                port_kind.is_linear() || matches!(port_kind, EdgeKind::Static(_))
+            }
             Direction::Outgoing => port_kind.is_linear(),
         };
         if must_be_connected && links.peek().is_none() {
@@ -470,7 +472,7 @@ impl<'a> ValidationContext<'a> {
 
         match from_optype.port_kind(from_offset).unwrap() {
             // Inter-graph constant wires do not have restrictions
-            EdgeKind::Const(typ) => {
+            EdgeKind::Static(typ) => {
                 if let OpType::Const(ops::Const(val)) = from_optype {
                     return typecheck_const(&typ, val).map_err(ValidationError::from);
                 } else {
diff --git a/src/ops/constant.rs b/src/ops/constant.rs
index 4d0855d9b..c3450ca6c 100644
--- a/src/ops/constant.rs
+++ b/src/ops/constant.rs
@@ -32,7 +32,7 @@ impl OpTrait for Const {
     }
 
     fn other_output(&self) -> Option<EdgeKind> {
-        Some(EdgeKind::Const(self.0.const_type()))
+        Some(EdgeKind::Static(self.0.const_type()))
     }
 }
 
diff --git a/src/ops/module.rs b/src/ops/module.rs
index f240fb5af..739f3072e 100644
--- a/src/ops/module.rs
+++ b/src/ops/module.rs
@@ -44,7 +44,7 @@ impl OpTrait for Def {
     }
 
     fn other_output(&self) -> Option<EdgeKind> {
-        Some(EdgeKind::Const(ClassicType::graph_from_sig(
+        Some(EdgeKind::Static(ClassicType::graph_from_sig(
             self.signature.clone(),
         )))
     }
@@ -71,7 +71,7 @@ impl OpTrait for Declare {
     }
 
     fn other_output(&self) -> Option<EdgeKind> {
-        Some(EdgeKind::Const(ClassicType::graph_from_sig(
+        Some(EdgeKind::Static(ClassicType::graph_from_sig(
             self.signature.clone(),
         )))
     }
diff --git a/src/types.rs b/src/types.rs
index 8fe1966d8..039a4bc35 100644
--- a/src/types.rs
+++ b/src/types.rs
@@ -27,8 +27,8 @@ pub enum EdgeKind {
     ControlFlow,
     /// Data edges of a DDG region, also known as "wires".
     Value(SimpleType),
-    /// A reference to a constant value definition, used in the module region.
-    Const(ClassicType),
+    /// A reference to a static value definition, used in the module region.
+    Static(ClassicType),
     /// Explicitly enforce an ordering between nodes in a DDG.
     StateOrder,
     /// An edge specifying a resource set.
@@ -110,7 +110,7 @@ impl Signature {
                 .clone()
                 .try_into()
                 .ok()
-                .map(EdgeKind::Const)
+                .map(EdgeKind::Static)
         } else {
             self.get_df(port).cloned().map(EdgeKind::Value)
         }