diff --git a/pytket/qir/conversion/api.py b/pytket/qir/conversion/api.py index 27461623..3e142499 100644 --- a/pytket/qir/conversion/api.py +++ b/pytket/qir/conversion/api.py @@ -27,9 +27,9 @@ scratch_reg_resize_pass, ) -from .conversion import QirGenerator from .module import tketqirModule -from .pconversion import PQirGenerator +from .profileqirgenerator import AdaptiveProfileQirGenerator +from .pytketqirgenerator import PytketQirGenerator class QIRFormat(Enum): @@ -41,6 +41,15 @@ class QIRFormat(Enum): STRING = 1 +class QIRProfile(Enum): + """Profile for the QIR generation""" + + BASE = 0 + ADAPTIVE = 1 + ADAPTIVE_CREGSIZE = 2 + PYTKET = 3 + + def pytket_to_qir( circ: Circuit, name: str = "Generated from input pytket circuit", @@ -48,7 +57,7 @@ def pytket_to_qir( wfh: Optional[wasm.WasmFileHandler] = None, int_type: int = 64, cut_pytket_register: bool = False, - profile: bool = False, + profile: QIRProfile = QIRProfile.PYTKET, ) -> Union[str, bytes, None]: """converts given pytket circuit to qir @@ -60,11 +69,17 @@ def pytket_to_qir( :param int_type: size of each integer, allowed value 32 and 64 :param cut_pytket_register: breaks up the internal scratch bit registers into smaller registers, default value false - :param profile: generates QIR corresponding to the adaptive profile - You can find more details about the adaptive profile under: - https://github.com/qir-alliance/qir-spec/pull/35 - and soon at: + :param profile: generates QIR corresponding to the selected profile: + Use QIRProfile.BASE for the base profile, see: + https://github.com/qir-alliance/qir-spec/blob/main/specification/under_development/profiles/Base_Profile.md + Use QIRProfile.ADAPTIVE for the adaptive profile, see: https://github.com/qir-alliance/qir-spec/tree/main/specification/under_development/profiles/Adaptive_Profile.md + Use QIRProfile.ADAPTIVE_CREGSIZE for the adaptive profile with additional + truncation operation to assure that integers matching the classical + registers have no unexpected set bits, see: + https://github.com/qir-alliance/qir-spec/tree/main/specification/under_development/profiles/Adaptive_Profile.md + Use QIRProfile.PYTKET for QIR with additonal function for classical registers. + """ if cut_pytket_register: @@ -78,26 +93,35 @@ def pytket_to_qir( num_qubits=circ.n_qubits, num_results=circ.n_qubits, ) - if not profile: - qir_generator = QirGenerator( + + if profile == QIRProfile.BASE: + raise NotImplementedError("QIRProfile.BASE not implemented") + + trunc = False + if profile == QIRProfile.ADAPTIVE_CREGSIZE: + trunc = True + + if profile == QIRProfile.PYTKET: + qir_generator = PytketQirGenerator( circuit=circ, module=m, wasm_int_type=int_type, qir_int_type=int_type, wfh=wfh, ) - - populated_module = qir_generator.circuit_to_module(qir_generator.circuit, True) - else: - qir_generator = PQirGenerator( # type: ignore + elif profile == QIRProfile.ADAPTIVE or profile == QIRProfile.ADAPTIVE_CREGSIZE: + qir_generator = AdaptiveProfileQirGenerator( # type: ignore circuit=circ, module=m, wasm_int_type=int_type, qir_int_type=int_type, wfh=wfh, + trunc=trunc, ) + else: + raise NotImplementedError("unexpected profile") - populated_module = qir_generator.circuit_to_module(qir_generator.circuit, True) + populated_module = qir_generator.circuit_to_module(qir_generator.circuit, True) if wfh is not None: wasm_sar_dict: dict[str, str] = qir_generator.get_wasm_sar() diff --git a/pytket/qir/conversion/pconversion.py b/pytket/qir/conversion/pconversion.py deleted file mode 100644 index 53f98aa0..00000000 --- a/pytket/qir/conversion/pconversion.py +++ /dev/null @@ -1,1279 +0,0 @@ -# Copyright 2019-2024 Quantinuum -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -This module contains all functionality to generate QIR files -from pytket circuits. -""" - -import math -from collections.abc import Sequence -from functools import partial -from typing import Optional, Union, cast - -import pyqir -from pyqir import BasicBlock, IntPredicate, Value - -from pytket import Bit, Circuit, Qubit, predicates, wasm # type: ignore -from pytket.circuit import ( - BarrierOp, - BitRegister, - ClassicalExpBox, - Command, - Conditional, - CopyBitsOp, - Op, - OpType, - RangePredicateOp, - SetBitsOp, - WASMOp, -) -from pytket.circuit.logic_exp import ( - BitAnd, - BitEq, - BitNeq, - BitNot, - BitOne, - BitOr, - BitWiseOp, - BitXor, - BitZero, - RegAdd, - RegAnd, - RegEq, - RegGeq, - RegGt, - RegLeq, - RegLsh, - RegLt, - RegMul, - RegNeq, - RegOr, - RegRsh, - RegSub, - RegXor, -) -from pytket.qasm.qasm import _retrieve_registers -from pytket.transform import Transform -from pytket.unit_id import UnitType - -from .gatesets import ( - FuncSpec, -) -from .module import tketqirModule - -_TK_CLOPS_TO_PYQIR_REG: dict = { - RegAnd: lambda b: b.and_, - RegOr: lambda b: b.or_, - RegXor: lambda b: b.xor, - RegAdd: lambda b: b.add, - RegSub: lambda b: b.sub, - RegMul: lambda b: b.mul, - RegLsh: lambda b: b.shl, - RegRsh: lambda b: b.lshr, -} - -_TK_CLOPS_TO_PYQIR_REG_BOOL: dict = { - RegEq: lambda b: partial(b.icmp, IntPredicate.EQ), - RegNeq: lambda b: partial(b.icmp, IntPredicate.NE), - RegGt: lambda b: partial(b.icmp, IntPredicate.UGT), - RegGeq: lambda b: partial(b.icmp, IntPredicate.UGE), - RegLt: lambda b: partial(b.icmp, IntPredicate.ULT), - RegLeq: lambda b: partial(b.icmp, IntPredicate.ULE), -} - -_TK_CLOPS_TO_PYQIR_2_BITS: dict = { - BitAnd: lambda b: b.and_, - BitOr: lambda b: b.or_, - BitXor: lambda b: b.xor, - BitNeq: lambda b: partial(b.icmp, IntPredicate.NE), - BitEq: lambda b: partial(b.icmp, IntPredicate.EQ), -} - -_TK_CLOPS_TO_PYQIR_BIT: dict = { - BitNot: lambda b: b.sub, -} - -_TK_CLOPS_TO_PYQIR_2_BITS_NO_PARAM: dict = { - BitOne: 1, - BitZero: 0, -} - - -class PQirGenerator: - """Generate QIR from a pytket circuit.""" - - def __init__( - self, - circuit: Circuit, - module: tketqirModule, - wasm_int_type: int, - qir_int_type: int, - wfh: Optional[wasm.WasmFileHandler] = None, - ) -> None: - self.circuit = circuit - self.module = module - self.wasm_int_type = pyqir.IntType(self.module.context, wasm_int_type) - self.int_size = qir_int_type - self.qir_int_type = pyqir.IntType(self.module.context, qir_int_type) - self.qir_i1p_type = pyqir.PointerType(pyqir.IntType(self.module.context, 1)) - self.qir_bool_type = pyqir.IntType(self.module.context, 1) - self.qubit_type = pyqir.qubit_type(self.module.context) - self.result_type = pyqir.result_type(self.module.context) - self.active_block = None - - self.cregs = _retrieve_registers(self.circuit.bits, BitRegister) - self.creg_size: dict[str, int] = {} - self.target_gateset = self.module.gateset.base_gateset - - self.block_count = 0 - self.block_count_sb = 0 - - self.wasm_sar_dict: dict[str, str] = {} - self.wasm_sar_dict["!llvm.module.flags"] = ( - 'attributes #1 = { "wasm" }\n\n!llvm.module.flags' - ) - self.wasm_sar_dict[ - 'attributes #1 = { "irreversible" }\n\nattributes #1 = { "wasm" }' - ] = 'attributes #1 = { "wasm" }\nattributes #2 = { "irreversible" }' - self.wasm_sar_dict[ - "declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1" - ] = "declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #2" - - self.int_type_str = f"i{qir_int_type}" - - self.target_gateset.add(OpType.PhasedX) - self.target_gateset.add(OpType.ZZPhase) - self.target_gateset.add(OpType.ZZMax) - self.target_gateset.add(OpType.TK2) - - self.getset_predicate = predicates.GateSetPredicate( - set(self.target_gateset) - ) # noqa: E501 - - self.set_cregs: dict[str, list] = {} # Keep track of set registers. - self.ssa_vars: dict[str, list[tuple[Value, BasicBlock]]] = ( - {} - ) # Keep track of set ssa variables. - self.list_of_changed_cregs: list[str] = [] - - # __quantum__qis__read_result__body(result) - self.read_bit_from_result = self.module.module.add_external_function( - "__quantum__qis__read_result__body", - pyqir.FunctionType( - pyqir.IntType(self.module.module.context, 1), - [pyqir.result_type(self.module.module.context)], - ), - ) - - self.reg_const = {} - - for creg in self.circuit.c_registers: - reg_name = creg[0].reg_name - self.reg_const[reg_name] = self.module.module.add_byte_string( - str.encode(reg_name) - ) - - # void __quantum__rt__int_record_output(i64) - self.record_output_i64 = self.module.module.add_external_function( - "__quantum__rt__int_record_output", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - pyqir.IntType(self.module.module.context, qir_int_type), - pyqir.PointerType(pyqir.IntType(self.module.module.context, 8)), - ], - ), - ) - - self.barrier: list[Optional[pyqir.Function]] = [None] * ( - self.circuit.n_qubits + 1 - ) - self.order: list[Optional[pyqir.Function]] = [None] * ( - self.circuit.n_qubits + 1 - ) - self.group: list[Optional[pyqir.Function]] = [None] * ( - self.circuit.n_qubits + 1 - ) - self.sleep: list[Optional[pyqir.Function]] = [None] * ( - self.circuit.n_qubits + 1 - ) - - # void functionname() - if wfh is not None: - self.wasm: dict[str, pyqir.Function] = {} - for fn in wfh._functions: - wasm_func_interface = "declare " - parametertype = [self.qir_int_type] * wfh._functions[fn][0] - if wfh._functions[fn][1] == 0: - returntype = pyqir.Type.void(self.module.module.context) - wasm_func_interface += "void " - elif wfh._functions[fn][1] == 1: - returntype = self.qir_int_type - wasm_func_interface += f"{self.int_type_str} " - else: - raise ValueError( - "wasm function which return more than" - + " one value are not supported yet" - ) - - self.wasm[fn] = self.module.module.add_external_function( - f"{fn}", - pyqir.FunctionType( - returntype, - parametertype, - ), - ) - - wasm_func_interface += f"@{fn}(" - if wfh._functions[fn][0] > 0: - param_str = f"{self.int_type_str}, " * (wfh._functions[fn][0] - 1) - wasm_func_interface += param_str - wasm_func_interface += f"{self.int_type_str})" - else: - wasm_func_interface += ")" - - self.wasm_sar_dict[wasm_func_interface] = f"{wasm_func_interface} #1" - - self.additional_quantum_gates: dict[OpType, pyqir.Function] = {} - - entry = self.module.module.entry_block - self.module.module.builder.insert_at_end(entry) - self.active_block = entry - self.active_block_main = entry - self.active_block_list = [entry] - - # set the prefix for the names of the conditional blocks - self.conditional_bp = "condb" - # set the prefix for the names of the continue blocks - self.continue_bp = "contb" - - assert self.conditional_bp != self.continue_bp - assert self.conditional_bp != "entry" - assert self.continue_bp != "entry" - # the code is assuming that the prefixes have length 5 - assert len(self.conditional_bp) == 5 - assert len(self.continue_bp) == 5 - - for creg in self.circuit.c_registers: - self._reg2ssa_var(creg) - self.list_of_changed_cregs.append(creg) - self.creg_size[creg.name] = creg.size - - def _get_bit_from_creg(self, creg: str, index: int) -> Value: - ssa_index = pyqir.const(self.qir_int_type, 2**index) - - result = self.module.module.builder.icmp( - pyqir.IntPredicate.EQ, - ssa_index, - self.module.module.builder.and_(ssa_index, self.get_ssa_vars(creg)), - ) - - return result - - def _set_bit_in_creg_blocks(self, creg: str, index: int, ssa_bit: Value) -> None: - ssa_int = self.get_ssa_vars(creg) - - ssa_index = pyqir.const(self.qir_int_type, 2**index) - - # it would be better to do an invert here, but that is not - # (yet) available in pyqir - ssa_int_all_1 = pyqir.const(self.qir_int_type, (2 ** (self.int_size - 1) - 1)) - - entry_point = self.module.module.entry_point - - sb_0 = pyqir.BasicBlock( - self.module.module.context, f"sb_0_{self.block_count_sb}", entry_point - ) - sb_1 = pyqir.BasicBlock( - self.module.module.context, f"sb_1_{self.block_count_sb}", entry_point - ) - - continue_block = pyqir.BasicBlock( - self.module.module.context, - f"{self.active_block_main.name}_{self.block_count_sb}", - entry_point, - ) - if self.active_block_main.name[0:5] != self.conditional_bp: - self.active_block_list.append(continue_block) - - self.block_count_sb = self.block_count_sb + 1 - self.module.module.builder.condbr(ssa_bit, sb_1, sb_0) - - # if bit 1 - self.module.module.builder.insert_at_end(sb_1) - result_1 = self.module.module.builder.or_(ssa_index, ssa_int) - self.module.module.builder.br(continue_block) - - # if bit 0 - self.module.module.builder.insert_at_end(sb_0) - result_0 = self.module.module.builder.and_( - self.module.module.builder.xor( - ssa_index, - ssa_int_all_1, - ), - ssa_int, - ) - self.module.module.builder.br(continue_block) - - # phi and continue - self.active_block = continue_block - self.module.module.builder.insert_at_end(continue_block) - phi = self.module.module.builder.phi(self.qir_int_type) - phi.add_incoming(result_0, sb_0) - phi.add_incoming(result_1, sb_1) - - self.set_ssa_vars(creg, phi, False) - - def _set_bit_in_creg_zext(self, creg: str, index: int, ssa_bit: Value) -> None: - ssa_int = self.get_ssa_vars(creg) - ssa_bit_i64 = self.module.module.builder.zext(ssa_bit, self.qir_int_type) - ssa_index = pyqir.const(self.qir_int_type, 2**index) - # it would be better to do an invert here, but that is not - # (yet) available in pyqir - ssa_int_all_1 = pyqir.const(self.qir_int_type, (2 ** (self.int_size - 1) - 1)) - - # if ssa_bit is 1, ((BIT) MUL (2^INDEX) ) OR INT - ssa_result_1 = self.module.module.builder.or_( - self.module.module.builder.mul(ssa_bit_i64, ssa_index), ssa_int - ) - - # if ssa_bit is 0, ((2**63-1) XOR ((1-BIT) MUL (2^INDEX))) and INT - ssa_result_0 = self.module.module.builder.and_( - self.module.module.builder.xor( - ssa_int_all_1, - self.module.module.builder.mul( - self.module.module.builder.sub( - pyqir.const(self.qir_int_type, 1), ssa_bit_i64 - ), - ssa_index, - ), - ), - ssa_result_1, - ) - - # set ssa - self.set_ssa_vars(creg, ssa_result_0, False) - - def _set_bit_in_creg(self, creg: str, index: int, ssa_bit: Value) -> None: - self._set_bit_in_creg_zext(creg, index, ssa_bit) - - def get_ssa_vars(self, reg_name: str) -> Value: - if reg_name not in self.ssa_vars: - raise ValueError(f"{reg_name} is not a valid register") - return self.ssa_vars[reg_name][-1][0] - - def get_ssa_list(self, reg_name: str) -> list: - if reg_name not in self.ssa_vars: - raise ValueError(f"{reg_name} is not a valid register") - return self.ssa_vars[reg_name] - - def set_ssa_vars(self, reg_name: str, ssa_i64: Value, trunc: bool = False) -> None: - # todo set default value for trunc to true, when enough - # classical registers are available - if reg_name not in self.ssa_vars: - raise ValueError(f"{reg_name} is not a valid register") - if trunc and self.creg_size[reg_name] != self.int_size: - type_register = pyqir.IntType(self.module.context, self.creg_size[reg_name]) - ssa_i_trunc = self.module.module.builder.trunc(ssa_i64, type_register) - ssa_i64_zext = self.module.module.builder.zext( - ssa_i_trunc, self.qir_int_type - ) - self.ssa_vars[reg_name].append((ssa_i64_zext, self.active_block)) # type: ignore - else: - self.ssa_vars[reg_name].append((ssa_i64, self.active_block)) # type: ignore - self.list_of_changed_cregs.append(reg_name) - - def _add_barrier_op( - self, module: tketqirModule, index: int, qir_qubits: Sequence - ) -> None: - # __quantum__qis__barrier1__body() - if self.barrier[index] is None: - self.barrier[index] = self.module.module.add_external_function( - f"__quantum__qis__barrier{index}__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [pyqir.qubit_type(self.module.module.context)] * index, - ), - ) - - module.builder.call( - self.barrier[index], # type: ignore - [*qir_qubits], - ) - - def _add_group_op( - self, module: tketqirModule, index: int, qir_qubits: Sequence - ) -> None: - # __quantum__qis__group1__body() - if self.group[index] is None: - self.group[index] = self.module.module.add_external_function( - f"__quantum__qis__group{index}__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [pyqir.qubit_type(self.module.module.context)] * index, - ), - ) - - module.builder.call( - self.group[index], # type: ignore - [*qir_qubits], - ) - - def _add_order_op( - self, module: tketqirModule, index: int, qir_qubits: Sequence - ) -> None: - # __quantum__qis__order1__body() - if self.order[index] is None: - self.order[index] = self.module.module.add_external_function( - f"__quantum__qis__order{index}__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [pyqir.qubit_type(self.module.module.context)] * index, - ), - ) - - module.builder.call( - self.order[index], # type: ignore - [*qir_qubits], - ) - - def _add_sleep_op( - self, module: tketqirModule, index: int, qir_qubits: Sequence, duration: float - ) -> None: - # __quantum__qis__sleep__body() - - if index > 1: - raise ValueError("Sleep operation only allowed on one qubit") - - if self.sleep[index] is None: - paramlist = [pyqir.qubit_type(self.module.module.context)] * index - paramlist.append( - pyqir.Type.double(self.module.module.context) - ) # add float parameter - self.sleep[index] = self.module.module.add_external_function( - "__quantum__qis__sleep__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - paramlist, - ), - ) - - module.builder.call( - self.sleep[index], # type: ignore - [ - *qir_qubits, - pyqir.const(pyqir.Type.double(self.module.module.context), duration), - ], - ) - - def _rebase_command_to_gateset(self, command: Command) -> Optional[Circuit]: - """Rebase to the target gateset if needed.""" - optype = command.op.type - params = command.op.params - args = command.args - if optype not in self.module.gateset.base_gateset: - circuit = Circuit(self.circuit.n_qubits, self.circuit.n_bits) - circuit.add_gate(optype, params, args) - if not self.getset_predicate.verify(circuit): - raise ValueError(f"Gate not supported {optype}, {params}, {args}") - return circuit - return None - - def _decompose_conditional_circ_box(self, op: Op, args: list) -> Optional[Circuit]: - """Rebase an op to the target gateset if needed.""" - circuit = Circuit(self.circuit.n_qubits) - arg_names = set([b.reg_name for b in args if type(b) is Bit]) - for cr_name in arg_names: - circuit.add_c_register(self.circuit.get_c_register(cr_name)) - - circuit.add_circbox(op, args) - Transform.DecomposeBoxes().apply(circuit) - - return circuit - - def _get_optype_and_params(self, op: Op) -> tuple[OpType, Sequence[float]]: - optype: OpType = op.type - params: list = [] - if optype in [OpType.ExplicitPredicate, OpType.Barrier, OpType.CopyBits]: - pass - else: - params = op.params - return (optype, params) - - def _to_qis_qubits(self, qubits: list[Qubit]) -> list[Qubit]: - return [self.module.module.qubits[qubit.index[0]] for qubit in qubits] - - def _to_qis_results(self, bits: list[Bit]) -> Optional[Value]: - if bits: - return self.module.module.results[bits[0].index[0]] # type: ignore - return None - - def _to_qis_bits(self, args: list[Bit]) -> Sequence[Value]: - for b in args: - assert b.name == "c" - if args: - return [self.module.module.results[bit.index[0]] for bit in args[:-1]] - return [] - - def _reg2ssa_var(self, bit_reg: BitRegister) -> Value: - """Convert a BitRegister to an SSA variable using pyqir types.""" - reg_name = bit_reg[0].reg_name - if reg_name not in self.ssa_vars: - if len(bit_reg) > self.int_size: - raise ValueError( - f"Classical register should only have the size of {self.int_size}" - ) - ssa_var = pyqir.const(self.qir_int_type, 0) - self.ssa_vars[reg_name] = [(ssa_var, self.active_block)] # type: ignore - return ssa_var - else: - return cast(Value, self.ssa_vars[reg_name]) - - def _get_c_regs_from_com( - self, op: Op, args: Union[Bit, Qubit] - ) -> tuple[list[str], list[str]]: - """Get classical registers from command op types.""" - inputs: list[str] = [] - outputs: list[str] = [] - - if isinstance(op, WASMOp): - for reglist, sizes in [ - (inputs, op.input_widths), - (outputs, op.output_widths), - ]: - for in_width in sizes: - assert in_width > 0 - com_bits = args[:in_width] - args = args[in_width:] - regname = com_bits[0].reg_name - if com_bits != list(self.cregs[regname]): - raise ValueError("WASM ops must act on entire registers.") - reglist.append(regname) - return inputs, outputs - - def _get_ssa_from_cl_reg_op( - self, reg: Union[BitRegister, RegAnd, RegOr, RegXor, int], module: tketqirModule - ) -> Value: - if type(reg) in _TK_CLOPS_TO_PYQIR_REG: - assert len(reg.args) == 2 # type: ignore - - ssa_left = self._get_ssa_from_cl_reg_op(reg.args[0], module) # type: ignore - ssa_right = self._get_ssa_from_cl_reg_op( - reg.args[1], module # type: ignore - ) - - # add function to module - output_instruction = _TK_CLOPS_TO_PYQIR_REG[type(reg)](module.builder)( - ssa_left, ssa_right - ) - return output_instruction # type: ignore - elif type(reg) is BitRegister: - return self.get_ssa_vars(reg.name) - elif type(reg) is int: - return pyqir.const(self.qir_int_type, reg) - else: - raise ValueError(f"unsupported classical register operation: {type(reg)}") - - def _get_ssa_from_cl_bit_op( - self, bit: Union[Bit, BitAnd, BitOr, BitXor], module: tketqirModule - ) -> Value: - if type(bit) is Bit: - result = self._get_bit_from_creg(bit.reg_name, bit.index[0]) - - return result - elif type(bit) is int: - return pyqir.const(self.qir_bool_type, bit) - elif type(bit) in _TK_CLOPS_TO_PYQIR_BIT: - assert len(bit.args) == 1 - - ssa_left = pyqir.const(self.qir_bool_type, 1) - ssa_right = self._get_ssa_from_cl_bit_op(bit.args[0], module) - - # add function to module - output_instruction = _TK_CLOPS_TO_PYQIR_BIT[type(bit)](module.builder)( - ssa_left, ssa_right - ) - - return output_instruction # type: ignore - elif type(bit) in _TK_CLOPS_TO_PYQIR_2_BITS: - assert len(bit.args) == 2 - - ssa_left = self._get_ssa_from_cl_bit_op(bit.args[0], module) # type: ignore - ssa_right = self._get_ssa_from_cl_bit_op(bit.args[1], module) - - # add function to module - output_instruction = _TK_CLOPS_TO_PYQIR_2_BITS[type(bit)](module.builder)( - ssa_left, ssa_right - ) - - return output_instruction # type: ignore - else: - raise ValueError(f"unsupported bitwise operation {type(bit)}") - - def _add_phi(self) -> None: - """ - add phi nodes for the previously changed registers. - phi requires ssa variables from both predecessor blocks, - these are not necessarily the blocks where the variables - have been set. The second loop searches for the second variable - and adds that with the other predecessor - """ - - for creg in set(self.list_of_changed_cregs): - phi = self.module.module.builder.phi(self.qir_int_type) - ssa_list = self.get_ssa_list(creg) - # the first predecessor if the direct previous (last) entry in the ssa list - phi.add_incoming(ssa_list[-1][0], ssa_list[-1][1]) - - found_second_block = False - - # search for the other ssa variable - for i in range(-2, -len(ssa_list) - 1, -1): - if ( - ssa_list[-1][1].name != ssa_list[i][1].name - and ssa_list[i][1].name[0:5] != self.conditional_bp - ): - assert self.active_block_list[-3].name[0:5] != self.conditional_bp - # self.active_block_list[-3] is the second predecessor - phi.add_incoming(ssa_list[i][0], self.active_block_list[-3]) - found_second_block = True - break - - if not found_second_block: - raise RuntimeError("Second block missing in phi generation") - - self.set_ssa_vars(creg, phi, False) - - def get_wasm_sar(self) -> dict[str, str]: - return self.wasm_sar_dict - - def conv_RangePredicateOp( - self, op: RangePredicateOp, args: Union[Bit, Qubit] - ) -> None: - # special case handling for REG_EQ - - if op.lower == op.upper: - registername = args[0].reg_name - - result = self.module.module.builder.icmp( - pyqir.IntPredicate.EQ, - pyqir.const(self.qir_int_type, op.lower), - self.get_ssa_vars(registername), - ) - - condition_bit_index = args[-1].index[0] - result_registername = args[-1].reg_name - - self._set_bit_in_creg(result_registername, condition_bit_index, result) - - else: - lower_qir = pyqir.const(self.qir_int_type, op.lower) - upper_qir = pyqir.const(self.qir_int_type, op.upper) - - registername = args[0].reg_name - - lower_cond = self.module.module.builder.icmp( - pyqir.IntPredicate.SGT, - lower_qir, - self.get_ssa_vars(registername), - ) - - upper_cond = self.module.module.builder.icmp( - pyqir.IntPredicate.SGT, - self.get_ssa_vars(registername), - upper_qir, - ) - - result = self.module.module.builder.and_(lower_cond, upper_cond) - - condition_bit_index = args[-1].index[0] - registername = args[-1].reg_name - - self._set_bit_in_creg(registername, condition_bit_index, result) - - def conv_conditional(self, command: Command, op: Conditional) -> None: - condition_name = command.args[0].reg_name - - entry_point = self.module.module.entry_point - - condb = pyqir.BasicBlock( - self.module.module.context, - f"{self.conditional_bp}{self.block_count}", - entry_point, - ) - contb = pyqir.BasicBlock( - self.module.module.context, - f"{self.continue_bp}{self.block_count}", - entry_point, - ) - self.block_count = self.block_count + 1 - self.active_block_list.append(condb) - self.active_block_list.append(contb) - - if op.op.type == OpType.CircBox: - conditional_circuit = self._decompose_conditional_circ_box( - op.op, command.args[op.width :] - ) - - condition_name = command.args[0].reg_name - - if op.width == 1: # only one conditional bit - - condition_bit_index = command.args[0].index[0] - - ssa_bool = self._get_bit_from_creg(condition_name, condition_bit_index) - - self.list_of_changed_cregs = [] - self.active_block = condb - self.active_block_main = condb - - if op.value == 1: - self.module.module.builder.condbr(ssa_bool, condb, contb) - self.module.module.builder.insert_at_end(condb) - self.subcircuit_to_module(conditional_circuit) - - if op.value == 0: - self.module.module.builder.condbr(ssa_bool, contb, condb) - self.module.module.builder.insert_at_end(condb) - self.subcircuit_to_module(conditional_circuit) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) - - self.active_block = contb - self.active_block_main = contb - - self._add_phi() - - else: - for i in range(op.width): - if command.args[i].reg_name != condition_name: - raise ValueError( - "conditional can only work with one entire register" - ) - - for i in range(op.width - 1): - if command.args[i].index[0] >= command.args[i + 1].index[0]: - raise ValueError( - "conditional can only work with one entire register" - ) - - if self.circuit.get_c_register(condition_name).size != op.width: - raise ValueError( - "conditional can only work with one entire register" - ) - - ssa_bool = self.module.module.builder.icmp( - pyqir.IntPredicate.EQ, - pyqir.const(self.qir_int_type, op.value), - self.get_ssa_vars(condition_name), - ) - - self.module.module.builder.condbr(ssa_bool, condb, contb) - - self.module.module.builder.insert_at_end(condb) - - self.list_of_changed_cregs = [] - self.active_block = condb - self.active_block_main = condb - - self.subcircuit_to_module(conditional_circuit) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) - - self.active_block = contb - self.active_block_main = contb - - self._add_phi() - - else: - condition_name = command.args[0].reg_name - - if op.width == 1: # only one conditional bit - condition_bit_index = command.args[0].index[0] - - ssa_bool = self._get_bit_from_creg(condition_name, condition_bit_index) - - self.list_of_changed_cregs = [] - self.active_block = condb - self.active_block_main = condb - - if op.value == 1: - self.module.module.builder.condbr(ssa_bool, condb, contb) - self.module.module.builder.insert_at_end(condb) - self.command_to_module(op.op, command.args[op.width :]) - - if op.value == 0: - self.module.module.builder.condbr(ssa_bool, contb, condb) - self.module.module.builder.insert_at_end(condb) - self.command_to_module(op.op, command.args[op.width :]) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) - - self.active_block = contb - self.active_block_main = contb - - self._add_phi() - - else: - for i in range(op.width): - if command.args[i].reg_name != condition_name: - raise ValueError( - "conditional can only work with one entire register" - ) - - for i in range(op.width - 1): - if command.args[i].index[0] >= command.args[i + 1].index[0]: - raise ValueError( - "conditional can only work with one entire register" - ) - - if self.circuit.get_c_register(condition_name).size != op.width: - raise ValueError( - "conditional can only work with one entire register" - ) - - ssa_bool = self.module.module.builder.icmp( - pyqir.IntPredicate.EQ, - pyqir.const(self.qir_int_type, op.value), - self.get_ssa_vars(condition_name), - ) - - self.module.module.builder.condbr(ssa_bool, condb, contb) - self.module.module.builder.insert_at_end(condb) - - self.list_of_changed_cregs = [] - self.active_block = condb - self.active_block_main = condb - - self.command_to_module(op.op, command.args[op.width :]) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) - - self.active_block = contb - self.active_block_main = contb - - self._add_phi() - - def conv_WASMOp(self, op: WASMOp, args: Union[Bit, Qubit]) -> None: - paramreg, resultreg = self._get_c_regs_from_com(op, args) - - ssa_param = [self.get_ssa_vars(p) for p in paramreg] - - result = self.module.builder.call( - self.wasm[op.func_name], - [*ssa_param], - ) - - if len(resultreg) == 1: - self.set_ssa_vars(resultreg[0], result) - - def conv_ZZPhase(self, qubits: list[Qubit], op: Op) -> None: - if OpType.ZZPhase not in self.additional_quantum_gates: - self.additional_quantum_gates[OpType.ZZPhase] = ( - self.module.module.add_external_function( - "__quantum__qis__rzz__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - pyqir.Type.double(self.module.module.context), - pyqir.qubit_type(self.module.module.context), - pyqir.qubit_type(self.module.module.context), - ], - ), - ) - ) - - self.module.builder.call( - self.additional_quantum_gates[OpType.ZZPhase], - [ - pyqir.const( - pyqir.Type.double(self.module.module.context), - (float(op.params[0]) * math.pi), - ), - self.module.module.qubits[qubits[0].index[0]], - self.module.module.qubits[qubits[1].index[0]], - ], - ) - - def conv_phasedx(self, qubits: list[Qubit], op: Op) -> None: - if OpType.PhasedX not in self.additional_quantum_gates: - self.additional_quantum_gates[OpType.PhasedX] = ( - self.module.module.add_external_function( - "__quantum__qis__phasedx__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - pyqir.Type.double(self.module.module.context), - pyqir.Type.double(self.module.module.context), - pyqir.qubit_type(self.module.module.context), - ], - ), - ) - ) - - self.module.builder.call( - self.additional_quantum_gates[OpType.PhasedX], - [ - pyqir.const( - pyqir.Type.double(self.module.module.context), - (float(op.params[0]) * math.pi), - ), - pyqir.const( - pyqir.Type.double(self.module.module.context), - (float(op.params[1]) * math.pi), - ), - self.module.module.qubits[qubits[0].index[0]], - ], - ) - - def conv_tk2(self, qubits: list[Qubit], op: Op) -> None: - if OpType.TK2 not in self.additional_quantum_gates: - self.additional_quantum_gates[OpType.TK2] = ( - self.module.module.add_external_function( - "__quantum__qis__rxxyyzz__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - pyqir.Type.double(self.module.module.context), - pyqir.Type.double(self.module.module.context), - pyqir.Type.double(self.module.module.context), - pyqir.qubit_type(self.module.module.context), - pyqir.qubit_type(self.module.module.context), - ], - ), - ) - ) - - self.module.builder.call( - self.additional_quantum_gates[OpType.TK2], - [ - pyqir.const( - pyqir.Type.double(self.module.module.context), - (float(op.params[0]) * math.pi), - ), - pyqir.const( - pyqir.Type.double(self.module.module.context), - (float(op.params[1]) * math.pi), - ), - pyqir.const( - pyqir.Type.double(self.module.module.context), - (float(op.params[2]) * math.pi), - ), - self.module.module.qubits[qubits[0].index[0]], - self.module.module.qubits[qubits[1].index[0]], - ], - ) - - def conv_zzmax(self, qubits: list[Qubit]) -> None: - if OpType.ZZMax not in self.additional_quantum_gates: - self.additional_quantum_gates[OpType.ZZMax] = ( - self.module.module.add_external_function( - "__quantum__qis__zzmax__body", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - pyqir.qubit_type(self.module.module.context), - pyqir.qubit_type(self.module.module.context), - ], - ), - ) - ) - - self.module.builder.call( - self.additional_quantum_gates[OpType.ZZMax], - [ - self.module.module.qubits[qubits[0].index[0]], - self.module.module.qubits[qubits[1].index[0]], - ], - ) - - def conv_measure(self, bits: list[Bit], qubits: list[Qubit]) -> None: - - qubit_index = qubits[0].index[0] - - self.module.qis.mz( - self.module.module.qubits[qubit_index], - self.module.module.results[qubit_index], - ) - - ssa_measureresult = self.module.builder.call( - self.read_bit_from_result, - [ - self.module.module.results[qubit_index], - ], - ) - - self._set_bit_in_creg(bits[0].reg_name, bits[0].index[0], ssa_measureresult) - - def conv_classicalexpbox(self, op: ClassicalExpBox, args: list) -> None: - returntypebool = False - result_index = ( - 0 # defines the default value for ops that returns bool, see below - ) - - outputs = args[-1].reg_name - - if type(op.get_exp()) in _TK_CLOPS_TO_PYQIR_REG: - # classical ops acting on registers returning register - ssa_left = cast( # type: ignore - Value, - self._get_ssa_from_cl_reg_op( - op.get_exp().args[0], self.module # type: ignore - ), - ) - ssa_right = cast( # type: ignore - Value, - self._get_ssa_from_cl_reg_op( - op.get_exp().args[1], self.module # type: ignore - ), - ) - - # add function to module - output_instruction = _TK_CLOPS_TO_PYQIR_REG[type(op.get_exp())]( - self.module.builder - )(ssa_left, ssa_right) - - elif type(op.get_exp()) in _TK_CLOPS_TO_PYQIR_2_BITS_NO_PARAM: - # classical ops without parameters - output_instruction = pyqir.const( - self.qir_bool_type, - _TK_CLOPS_TO_PYQIR_2_BITS_NO_PARAM[type(op.get_exp())], - ) - returntypebool = True - result_index = args[-1].index[0] - - elif type(op.get_exp()) in _TK_CLOPS_TO_PYQIR_BIT: - # classical ops acting on bits returning bit - ssa_left = pyqir.const(self.qir_bool_type, 1) - ssa_right = cast( # type: ignore - Value, - self._get_ssa_from_cl_bit_op(op.get_exp().args[0], self.module), - ) - - # add function to module - returntypebool = True - result_index = args[-1].index[0] - output_instruction = _TK_CLOPS_TO_PYQIR_BIT[type(op.get_exp())]( - self.module.builder - )(ssa_left, ssa_right) - - elif type(op.get_exp()) in _TK_CLOPS_TO_PYQIR_2_BITS: - # classical ops acting on bits returning bit - ssa_left = cast( # type: ignore - Value, - self._get_ssa_from_cl_bit_op(op.get_exp().args[0], self.module), - ) - ssa_right = cast( # type: ignore - Value, - self._get_ssa_from_cl_bit_op(op.get_exp().args[1], self.module), - ) - - # add function to module - returntypebool = True - result_index = args[-1].index[0] - output_instruction = _TK_CLOPS_TO_PYQIR_2_BITS[type(op.get_exp())]( - self.module.builder - )(ssa_left, ssa_right) - - elif type(op.get_exp()) in _TK_CLOPS_TO_PYQIR_REG_BOOL: - # classical ops acting on registers returning bit - ssa_left = cast( # type: ignore - Value, - self._get_ssa_from_cl_reg_op( - op.get_exp().args[0], self.module # type: ignore - ), - ) - ssa_right = cast( # type: ignore - Value, - self._get_ssa_from_cl_reg_op( - op.get_exp().args[1], self.module # type: ignore - ), - ) - - # add function to module - returntypebool = True - output_instruction = _TK_CLOPS_TO_PYQIR_REG_BOOL[type(op.get_exp())]( - self.module.builder - )(ssa_left, ssa_right) - - else: - raise ValueError(f"unexpected classical op {type(op.get_exp())}") - - if returntypebool: - # the return value of the some classical ops is bool in qir, - # so the return value can only be written to one entry - # of the register this implementation write the value - # to the 0-th entry - # of the register, this could be changed to a user given value - - self._set_bit_in_creg(outputs, result_index, output_instruction) - else: - self.set_ssa_vars(outputs, output_instruction) - - def conv_SetBitsOp(self, bits: list[Bit], op: SetBitsOp) -> None: - assert len(op.values) == len(bits) - - for b, v in zip(bits, op.values): - output_instruction = pyqir.const(self.qir_bool_type, int(v)) - - self._set_bit_in_creg(b.reg_name, b.index[0], output_instruction) - - def conv_CopyBitsOp(self, args: list) -> None: - assert len(args) % 2 == 0 - half_length = len(args) // 2 - - for i, o in zip(args[:half_length], args[half_length:]): - output_instruction = self._get_bit_from_creg(i.reg_name, i.index[0]) - - self._set_bit_in_creg(o.reg_name, o.index[0], output_instruction) - - def conv_BarrierOp(self, qubits: list[Qubit], op: BarrierOp) -> None: - assert qubits[0].reg_name == "q" - - qir_qubits = self._to_qis_qubits(qubits) - - if op.data == "": - self._add_barrier_op(self.module, len(qubits), qir_qubits) - elif op.data[0:5] == "order": - self._add_order_op(self.module, len(qubits), qir_qubits) - elif op.data[0:5] == "group": - self._add_group_op(self.module, len(qubits), qir_qubits) - elif op.data[0:5] == "sleep": - self._add_sleep_op( - self.module, - len(qubits), - qir_qubits, - float(op.data[6:-1]), - ) - else: - raise ValueError("op is not supported yet") - - def conv_other( - self, bits: list[Bit], qubits: list[Qubit], op: Op, args: list - ) -> None: - optype, params = self._get_optype_and_params(op) - pi_params = [p * math.pi for p in params] - qubits_qis = self._to_qis_qubits(qubits) - results = self._to_qis_results(bits) - bits_qis: Optional[Sequence[Value]] = None - if type(optype) is BitWiseOp: - bits_qis = self._to_qis_bits(args) - gate = self.module.gateset.tk_to_gateset(optype) - if gate.func_spec != FuncSpec.BODY: - func_name = gate.func_name.value + "_" + gate.func_spec.value - get_gate = getattr(self.module.qis, func_name) - else: - get_gate = getattr(self.module.qis, gate.func_name.value) - if bits_qis: - get_gate(*bits_qis) - elif params: - get_gate(*pi_params, *qubits_qis) - elif results: - get_gate(*qubits_qis, results) - else: - get_gate(*qubits_qis) - - def command_to_module(self, op: Op, args: list) -> tketqirModule: - """Populate a PyQir module from a pytket command.""" - qubits = [q for q in args if q.type == UnitType.qubit] - bits = [b for b in args if b.type == UnitType.bit] - - if isinstance(op, RangePredicateOp): - self.conv_RangePredicateOp(op, args) - - elif isinstance(op, Conditional): - raise ValueError("conditional ops can't contain conditional ops") - - elif isinstance(op, WASMOp): - self.conv_WASMOp(op, args) - - elif op.type == OpType.ZZPhase: - self.conv_ZZPhase(qubits, op) - - elif op.type == OpType.PhasedX: - self.conv_phasedx(qubits, op) - - elif op.type == OpType.TK2: - self.conv_tk2(qubits, op) - - elif op.type == OpType.ZZMax: - self.conv_zzmax(qubits) - - elif op.type == OpType.Measure: - self.conv_measure(bits, qubits) - - elif op.type == OpType.Phase: - # ignore phase op - pass - - elif isinstance(op, ClassicalExpBox): - self.conv_classicalexpbox(op, args) - - elif isinstance(op, SetBitsOp): - self.conv_SetBitsOp(bits, op) - - elif isinstance(op, CopyBitsOp): - self.conv_CopyBitsOp(args) - - elif isinstance(op, BarrierOp): - self.conv_BarrierOp(qubits, op) - - else: - self.conv_other(bits, qubits, op, args) - - return self.module - - def circuit_to_module( - self, circuit: Circuit, record_output: bool = False - ) -> tketqirModule: - """Populate a PyQir module from a pytket circuit.""" - - for command in circuit: - op = command.op - - if isinstance(op, Conditional): - self.conv_conditional(command, op) - - else: - self.command_to_module(op, command.args) - - if record_output: - - for creg in self.circuit.c_registers: - reg_name = creg[0].reg_name - self.module.builder.call( - self.record_output_i64, - [ - self.get_ssa_vars(reg_name), - self.reg_const[reg_name], - ], - ) - - return self.module - - def subcircuit_to_module( - self, - circuit: Circuit, - ) -> tketqirModule: - """Populate a PyQir module from a pytket subcircuit.""" - - for command in circuit: - self.command_to_module(command.op, command.args) - - return self.module diff --git a/pytket/qir/conversion/profileqirgenerator.py b/pytket/qir/conversion/profileqirgenerator.py new file mode 100644 index 00000000..b70a1c9d --- /dev/null +++ b/pytket/qir/conversion/profileqirgenerator.py @@ -0,0 +1,444 @@ +# Copyright 2019-2024 Quantinuum +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from typing import Optional, cast + +import pyqir +from pyqir import BasicBlock, Value + +from pytket import Bit, Circuit, Qubit, wasm # type: ignore +from pytket.circuit import ( + BitRegister, + Command, + Conditional, + OpType, +) + +from .module import tketqirModule +from .qirgenerator import ( + AbstractQirGenerator, +) + + +class AdaptiveProfileQirGenerator(AbstractQirGenerator): + """Generate QIR from a pytket circuit.""" + + def __init__( + self, + circuit: Circuit, + module: tketqirModule, + wasm_int_type: int, + qir_int_type: int, + trunc: bool, + wfh: Optional[wasm.WasmFileHandler] = None, + ) -> None: + + self.trunc = trunc + + super().__init__(circuit, module, wasm_int_type, qir_int_type, wfh) + + self.set_cregs: dict[str, list] = {} # Keep track of set registers. + self.ssa_vars: dict[str, list[tuple[Value, BasicBlock]]] = ( + {} + ) # Keep track of set ssa variables. + self.list_of_changed_cregs: list[str] = [] + + for creg in self.circuit.c_registers: + reg_name = creg[0].reg_name + self.reg_const[reg_name] = self.module.module.add_byte_string( + str.encode(reg_name) + ) + + entry = self.module.module.entry_block + self.module.module.builder.insert_at_end(entry) + self.active_block = entry + self.active_block_main = entry + self.active_block_list = [entry] + + # set the prefix for the names of the conditional blocks + self.conditional_bp = "condb" + # set the prefix for the names of the continue blocks + self.continue_bp = "contb" + + assert self.conditional_bp != self.continue_bp + assert self.conditional_bp != "entry" + assert self.continue_bp != "entry" + # the code is assuming that the prefixes have length 5 + assert len(self.conditional_bp) == 5 + assert len(self.continue_bp) == 5 + + for creg in self.circuit.c_registers: + self._reg2ssa_var(creg) + self.list_of_changed_cregs.append(creg) + self.creg_size[creg.name] = creg.size + + def _get_bit_from_creg(self, creg: str, index: int) -> Value: + ssa_index = pyqir.const(self.qir_int_type, 2**index) + + result = self.module.module.builder.icmp( + pyqir.IntPredicate.EQ, + ssa_index, + self.module.module.builder.and_(ssa_index, self.get_ssa_vars(creg)), + ) + + return result + + def _set_bit_in_creg_blocks(self, creg: str, index: int, ssa_bit: Value) -> None: + ssa_int = self.get_ssa_vars(creg) + + ssa_index = pyqir.const(self.qir_int_type, 2**index) + + # it would be better to do an invert here, but that is not + # (yet) available in pyqir + ssa_int_all_1 = pyqir.const(self.qir_int_type, (2 ** (self.int_size - 1) - 1)) + + entry_point = self.module.module.entry_point + + sb_0 = pyqir.BasicBlock( + self.module.module.context, f"sb_0_{self.block_count_sb}", entry_point + ) + sb_1 = pyqir.BasicBlock( + self.module.module.context, f"sb_1_{self.block_count_sb}", entry_point + ) + + continue_block = pyqir.BasicBlock( + self.module.module.context, + f"{self.active_block_main.name}_{self.block_count_sb}", + entry_point, + ) + if self.active_block_main.name[0:5] != self.conditional_bp: + self.active_block_list.append(continue_block) + + self.block_count_sb = self.block_count_sb + 1 + self.module.module.builder.condbr(ssa_bit, sb_1, sb_0) + + # if bit 1 + self.module.module.builder.insert_at_end(sb_1) + result_1 = self.module.module.builder.or_(ssa_index, ssa_int) + self.module.module.builder.br(continue_block) + + # if bit 0 + self.module.module.builder.insert_at_end(sb_0) + result_0 = self.module.module.builder.and_( + self.module.module.builder.xor( + ssa_index, + ssa_int_all_1, + ), + ssa_int, + ) + self.module.module.builder.br(continue_block) + + # phi and continue + self.active_block = continue_block + self.module.module.builder.insert_at_end(continue_block) + phi = self.module.module.builder.phi(self.qir_int_type) + phi.add_incoming(result_0, sb_0) + phi.add_incoming(result_1, sb_1) + + self.set_ssa_vars(creg, phi, False) + + def _set_bit_in_creg_zext(self, creg: str, index: int, ssa_bit: Value) -> None: + ssa_int = self.get_ssa_vars(creg) + ssa_bit_i64 = self.module.module.builder.zext(ssa_bit, self.qir_int_type) + ssa_index = pyqir.const(self.qir_int_type, 2**index) + # it would be better to do an invert here, but that is not + # (yet) available in pyqir + ssa_int_all_1 = pyqir.const(self.qir_int_type, (2 ** (self.int_size - 1) - 1)) + + # if ssa_bit is 1, ((BIT) MUL (2^INDEX) ) OR INT + ssa_result_1 = self.module.module.builder.or_( + self.module.module.builder.mul(ssa_bit_i64, ssa_index), ssa_int + ) + + # if ssa_bit is 0, ((2**63-1) XOR ((1-BIT) MUL (2^INDEX))) and INT + ssa_result_0 = self.module.module.builder.and_( + self.module.module.builder.xor( + ssa_int_all_1, + self.module.module.builder.mul( + self.module.module.builder.sub( + pyqir.const(self.qir_int_type, 1), ssa_bit_i64 + ), + ssa_index, + ), + ), + ssa_result_1, + ) + + # set ssa + self.set_ssa_vars(creg, ssa_result_0, False) + + def _set_bit_in_creg(self, creg: str, index: int, ssa_bit: Value) -> None: + self._set_bit_in_creg_zext(creg, index, ssa_bit) + + def get_ssa_vars(self, reg_name: str) -> Value: + if reg_name not in self.ssa_vars: + raise ValueError(f"{reg_name} is not a valid register") + return self.ssa_vars[reg_name][-1][0] + + def _get_i64_ssa_reg(self, reg_name: str) -> Value: + if reg_name not in self.ssa_vars: + raise ValueError(f"{reg_name} is not a valid register") + return self.ssa_vars[reg_name][-1][0] + + def get_ssa_list(self, reg_name: str) -> list: + if reg_name not in self.ssa_vars: + raise ValueError(f"{reg_name} is not a valid register") + return self.ssa_vars[reg_name] + + def set_ssa_vars(self, reg_name: str, ssa_i64: Value, trunc: bool) -> None: + if reg_name not in self.ssa_vars: + raise ValueError(f"{reg_name} is not a valid register") + if self.trunc and trunc and self.creg_size[reg_name] != self.int_size: + type_register = pyqir.IntType(self.module.context, self.creg_size[reg_name]) + ssa_i_trunc = self.module.module.builder.trunc(ssa_i64, type_register) + ssa_i64_zext = self.module.module.builder.zext( + ssa_i_trunc, self.qir_int_type + ) + self.ssa_vars[reg_name].append((ssa_i64_zext, self.active_block)) + else: + self.ssa_vars[reg_name].append((ssa_i64, self.active_block)) + self.list_of_changed_cregs.append(reg_name) + + def _reg2ssa_var(self, bit_reg: BitRegister) -> Value: + """Convert a BitRegister to an SSA variable using pyqir types.""" + reg_name = bit_reg[0].reg_name + if reg_name not in self.ssa_vars: + if len(bit_reg) > self.int_size: + raise ValueError( + f"Classical register should only have the size of {self.int_size}" + ) + ssa_var = pyqir.const(self.qir_int_type, 0) + self.ssa_vars[reg_name] = [(ssa_var, self.active_block)] + return ssa_var + else: + return cast(Value, self.ssa_vars[reg_name]) + + def _add_phi(self) -> None: + """ + add phi nodes for the previously changed registers. + phi requires ssa variables from both predecessor blocks, + these are not necessarily the blocks where the variables + have been set. The second loop searches for the second variable + and adds that with the other predecessor + """ + + for creg in set(self.list_of_changed_cregs): + phi = self.module.module.builder.phi(self.qir_int_type) + ssa_list = self.get_ssa_list(creg) + # the first predecessor if the direct previous (last) entry in the ssa list + phi.add_incoming(ssa_list[-1][0], ssa_list[-1][1]) + + found_second_block = False + + # search for the other ssa variable + for i in range(-2, -len(ssa_list) - 1, -1): + if ( + ssa_list[-1][1].name != ssa_list[i][1].name + and ssa_list[i][1].name[0:5] != self.conditional_bp + ): + assert self.active_block_list[-3].name[0:5] != self.conditional_bp + # self.active_block_list[-3] is the second predecessor + phi.add_incoming(ssa_list[i][0], self.active_block_list[-3]) + found_second_block = True + break + + if not found_second_block: + raise RuntimeError("Second block missing in phi generation") + + self.set_ssa_vars(creg, phi, False) + + def conv_conditional(self, command: Command, op: Conditional) -> None: + condition_name = command.args[0].reg_name + + entry_point = self.module.module.entry_point + + condb = pyqir.BasicBlock( + self.module.module.context, + f"{self.conditional_bp}{self.block_count}", + entry_point, + ) + contb = pyqir.BasicBlock( + self.module.module.context, + f"{self.continue_bp}{self.block_count}", + entry_point, + ) + self.block_count = self.block_count + 1 + self.active_block_list.append(condb) + self.active_block_list.append(contb) + + if op.op.type == OpType.CircBox: + conditional_circuit = self._decompose_conditional_circ_box( + op.op, command.args[op.width :] + ) + + condition_name = command.args[0].reg_name + + if op.width == 1: # only one conditional bit + + condition_bit_index = command.args[0].index[0] + + ssa_bool = self._get_bit_from_creg(condition_name, condition_bit_index) + + self.list_of_changed_cregs = [] + self.active_block = condb + self.active_block_main = condb + + if op.value == 1: + self.module.module.builder.condbr(ssa_bool, condb, contb) + self.module.module.builder.insert_at_end(condb) + self.subcircuit_to_module(conditional_circuit) + + if op.value == 0: + self.module.module.builder.condbr(ssa_bool, contb, condb) + self.module.module.builder.insert_at_end(condb) + self.subcircuit_to_module(conditional_circuit) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + self.active_block = contb + self.active_block_main = contb + + self._add_phi() + + else: + for i in range(op.width): + if command.args[i].reg_name != condition_name: + raise ValueError( + "conditional can only work with one entire register" + ) + + for i in range(op.width - 1): + if command.args[i].index[0] >= command.args[i + 1].index[0]: + raise ValueError( + "conditional can only work with one entire register" + ) + + if self.circuit.get_c_register(condition_name).size != op.width: + raise ValueError( + "conditional can only work with one entire register" + ) + + ssa_bool = self.module.module.builder.icmp( + pyqir.IntPredicate.EQ, + pyqir.const(self.qir_int_type, op.value), + self.get_ssa_vars(condition_name), + ) + + self.module.module.builder.condbr(ssa_bool, condb, contb) + + self.module.module.builder.insert_at_end(condb) + + self.list_of_changed_cregs = [] + self.active_block = condb + self.active_block_main = condb + + self.subcircuit_to_module(conditional_circuit) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + self.active_block = contb + self.active_block_main = contb + + self._add_phi() + + else: + condition_name = command.args[0].reg_name + + if op.width == 1: # only one conditional bit + condition_bit_index = command.args[0].index[0] + + ssa_bool = self._get_bit_from_creg(condition_name, condition_bit_index) + + self.list_of_changed_cregs = [] + self.active_block = condb + self.active_block_main = condb + + if op.value == 1: + self.module.module.builder.condbr(ssa_bool, condb, contb) + self.module.module.builder.insert_at_end(condb) + self.command_to_module(op.op, command.args[op.width :]) + + if op.value == 0: + self.module.module.builder.condbr(ssa_bool, contb, condb) + self.module.module.builder.insert_at_end(condb) + self.command_to_module(op.op, command.args[op.width :]) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + self.active_block = contb + self.active_block_main = contb + + self._add_phi() + + else: + for i in range(op.width): + if command.args[i].reg_name != condition_name: + raise ValueError( + "conditional can only work with one entire register" + ) + + for i in range(op.width - 1): + if command.args[i].index[0] >= command.args[i + 1].index[0]: + raise ValueError( + "conditional can only work with one entire register" + ) + + if self.circuit.get_c_register(condition_name).size != op.width: + raise ValueError( + "conditional can only work with one entire register" + ) + + ssa_bool = self.module.module.builder.icmp( + pyqir.IntPredicate.EQ, + pyqir.const(self.qir_int_type, op.value), + self.get_ssa_vars(condition_name), + ) + + self.module.module.builder.condbr(ssa_bool, condb, contb) + self.module.module.builder.insert_at_end(condb) + + self.list_of_changed_cregs = [] + self.active_block = condb + self.active_block_main = condb + + self.command_to_module(op.op, command.args[op.width :]) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + self.active_block = contb + self.active_block_main = contb + + self._add_phi() + + def conv_measure(self, bits: list[Bit], qubits: list[Qubit]) -> None: + + qubit_index = qubits[0].index[0] + + self.module.qis.mz( + self.module.module.qubits[qubit_index], + self.module.module.results[qubit_index], + ) + + ssa_measureresult = self.module.builder.call( + self.read_bit_from_result, + [ + self.module.module.results[qubit_index], + ], + ) + + self._set_bit_in_creg(bits[0].reg_name, bits[0].index[0], ssa_measureresult) diff --git a/pytket/qir/conversion/pytketqirgenerator.py b/pytket/qir/conversion/pytketqirgenerator.py new file mode 100644 index 00000000..a08bfb38 --- /dev/null +++ b/pytket/qir/conversion/pytketqirgenerator.py @@ -0,0 +1,335 @@ +# Copyright 2019-2024 Quantinuum +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from typing import Optional, cast + +import pyqir +from pyqir import Value + +from pytket import Bit, Circuit, Qubit, wasm # type: ignore +from pytket.circuit import ( + BitRegister, + Command, + Conditional, + OpType, +) + +from .module import tketqirModule +from .qirgenerator import ( + AbstractQirGenerator, +) + + +class PytketQirGenerator(AbstractQirGenerator): + """Generates QIR from a pytket circuit in line with the pytket profile. + This profile uses the functions `get_creg_bit`, `set_creg_bit`, + `set_creg_to_int`, `create_creg`, `get_int_from_creg` and + `mz_to_creg_bit` for the handling of the classical registers. + The other aspects of the QIR file are identical to the adaptive profile. + """ + + def __init__( + self, + circuit: Circuit, + module: tketqirModule, + wasm_int_type: int, + qir_int_type: int, + wfh: Optional[wasm.WasmFileHandler] = None, + ) -> None: + + super().__init__(circuit, module, wasm_int_type, qir_int_type, wfh) + + self.set_cregs: dict[str, list] = {} # Keep track of set registers. + self.ssa_vars: dict[str, Value] = {} # Keep track of set ssa variables. + + # i1 get_creg_bit(i1* creg, i64 index) + self.get_creg_bit = self.module.module.add_external_function( + "get_creg_bit", + pyqir.FunctionType( + pyqir.IntType(self.module.module.context, 1), + [self.qir_i1p_type, self.qir_int_type], + ), + ) + + # void set_creg_bit(i1* creg, i64 index, i1 value) + self.set_creg_bit = self.module.module.add_external_function( + "set_creg_bit", + pyqir.FunctionType( + pyqir.Type.void(self.module.module.context), + [ + self.qir_i1p_type, + self.qir_int_type, + pyqir.IntType(self.module.module.context, 1), + ], + ), + ) + + # void set_creg_to_int(i1* creg, i64 value) + self.set_creg_to_int = self.module.module.add_external_function( + "set_creg_to_int", + pyqir.FunctionType( + pyqir.Type.void(self.module.module.context), + [ + self.qir_i1p_type, + self.qir_int_type, + ], + ), + ) + + # i1* create_creg(i64 size) + self.create_creg = self.module.module.add_external_function( + "create_creg", + pyqir.FunctionType( + self.qir_i1p_type, + [pyqir.IntType(self.module.module.context, qir_int_type)], + ), + ) + + # i64 get_int_from_creg(i1* creg) + self.get_int_from_creg = self.module.module.add_external_function( + "get_int_from_creg", + pyqir.FunctionType( + self.qir_int_type, + [ + self.qir_i1p_type, + ], + ), + ) + + # void mz_to_creg_bit(qubit, i1* creg, int creg_index) + # measures one qubit to one bit entry in a creg + self.mz_to_creg_bit = self.module.module.add_external_function( + "mz_to_creg_bit", + pyqir.FunctionType( + pyqir.Type.void(self.module.module.context), + [ + pyqir.qubit_type(self.module.module.context), + self.qir_i1p_type, + self.qir_int_type, + ], + ), + ) + + for creg in self.circuit.c_registers: + reg_name = creg[0].reg_name + self.reg_const[reg_name] = self.module.module.add_byte_string( + str.encode(reg_name) + ) + + entry = self.module.module.entry_block + self.module.module.builder.insert_at_end(entry) + + for creg in self.circuit.c_registers: + self._reg2ssa_var(creg, qir_int_type) + + def get_ssa_vars(self, reg_name: str) -> Value: + if reg_name not in self.ssa_vars: + raise ValueError(f"{reg_name} is not a valid register") + return self.ssa_vars[reg_name] + + def _get_i64_ssa_reg(self, name: str) -> Value: + ssa_var = self.module.builder.call( + self.get_int_from_creg, + [self.get_ssa_vars(name)], + ) + return ssa_var + + def set_ssa_vars(self, reg_name: str, ssa_i64: Value, trunc: bool) -> None: + + self.module.builder.call( + self.set_creg_to_int, + [self.get_ssa_vars(reg_name), ssa_i64], + ) + + def _set_bit_in_creg(self, creg: str, index: int, ssa_bit: Value) -> None: + self.module.builder.call( + self.set_creg_bit, + [ + self.get_ssa_vars(creg), + pyqir.const(self.qir_int_type, index), + ssa_bit, + ], + ) + + def _get_bit_from_creg(self, creg: str, index: int) -> Value: + return self.module.builder.call( + self.get_creg_bit, + [ + self.get_ssa_vars(creg), + pyqir.const(self.qir_int_type, index), + ], + ) + + def _reg2ssa_var(self, bit_reg: BitRegister, int_size: int) -> Value: + """Convert a BitRegister to an SSA variable using pyqir types.""" + reg_name = bit_reg[0].reg_name + if reg_name not in self.ssa_vars: + if len(bit_reg) > int_size: + raise ValueError( + f"Classical register should only have the size of {int_size}" + ) + ssa_var = self.module.builder.call( + self.create_creg, [pyqir.const(self.qir_int_type, len(bit_reg))] + ) + self.ssa_vars[reg_name] = ssa_var + return ssa_var + else: + return cast(Value, self.ssa_vars[reg_name]) # type: ignore + + def conv_conditional(self, command: Command, op: Conditional) -> None: + condition_name = command.args[0].reg_name + + entry_point = self.module.module.entry_point + + condb = pyqir.BasicBlock( + self.module.module.context, f"condb{self.block_count}", entry_point + ) + contb = pyqir.BasicBlock( + self.module.module.context, f"contb{self.block_count}", entry_point + ) + self.block_count = self.block_count + 1 + + if op.op.type == OpType.CircBox: + conditional_circuit = self._decompose_conditional_circ_box( + op.op, command.args[op.width :] + ) + + condition_name = command.args[0].reg_name + + if op.width == 1: # only one conditional bit + + condition_bit_index = command.args[0].index[0] + + ssabool = self.module.builder.call( + self.get_creg_bit, + [ + self.get_ssa_vars(condition_name), + pyqir.const(self.qir_int_type, condition_bit_index), + ], + ) + + if op.value == 1: + self.module.module.builder.condbr(ssabool, condb, contb) + self.module.module.builder.insert_at_end(condb) + self.subcircuit_to_module(conditional_circuit) + + if op.value == 0: + self.module.module.builder.condbr(ssabool, contb, condb) + self.module.module.builder.insert_at_end(condb) + self.subcircuit_to_module(conditional_circuit) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + else: + for i in range(op.width): + if command.args[i].reg_name != condition_name: + raise ValueError( + "conditional can only work with one entire register" + ) + + for i in range(op.width - 1): + if command.args[i].index[0] >= command.args[i + 1].index[0]: + raise ValueError( + "conditional can only work with one entire register" + ) + + if self.circuit.get_c_register(condition_name).size != op.width: + raise ValueError( + "conditional can only work with one entire register" + ) + + ssabool = self.module.module.builder.icmp( + pyqir.IntPredicate.EQ, + pyqir.const(self.qir_int_type, op.value), + self._get_i64_ssa_reg(condition_name), + ) + + self.module.module.builder.condbr(ssabool, condb, contb) + + self.module.module.builder.insert_at_end(condb) + + self.subcircuit_to_module(conditional_circuit) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + else: + condition_name = command.args[0].reg_name + + if op.width == 1: # only one conditional bit + condition_bit_index = command.args[0].index[0] + + ssabool = self.module.builder.call( + self.get_creg_bit, + [ + self.get_ssa_vars(condition_name), + pyqir.const(self.qir_int_type, condition_bit_index), + ], + ) + + if op.value == 1: + self.module.module.builder.condbr(ssabool, condb, contb) + self.module.module.builder.insert_at_end(condb) + self.command_to_module(op.op, command.args[op.width :]) + + if op.value == 0: + self.module.module.builder.condbr(ssabool, contb, condb) + self.module.module.builder.insert_at_end(condb) + self.command_to_module(op.op, command.args[op.width :]) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + else: + for i in range(op.width): + if command.args[i].reg_name != condition_name: + raise ValueError( + "conditional can only work with one entire register" + ) + + for i in range(op.width - 1): + if command.args[i].index[0] >= command.args[i + 1].index[0]: + raise ValueError( + "conditional can only work with one entire register" + ) + + if self.circuit.get_c_register(condition_name).size != op.width: + raise ValueError( + "conditional can only work with one entire register" + ) + + ssabool = self.module.module.builder.icmp( + pyqir.IntPredicate.EQ, + pyqir.const(self.qir_int_type, op.value), + self._get_i64_ssa_reg(condition_name), + ) + + self.module.module.builder.condbr(ssabool, condb, contb) + self.module.module.builder.insert_at_end(condb) + + self.command_to_module(op.op, command.args[op.width :]) + + self.module.module.builder.br(contb) + self.module.module.builder.insert_at_end(contb) + + def conv_measure(self, bits: list[Bit], qubits: list[Qubit]) -> None: + self.module.builder.call( + self.mz_to_creg_bit, + [ + self.module.module.qubits[qubits[0].index[0]], + self.get_ssa_vars(bits[0].reg_name), + pyqir.const(self.qir_int_type, bits[0].index[0]), + ], + ) diff --git a/pytket/qir/conversion/conversion.py b/pytket/qir/conversion/qirgenerator.py similarity index 68% rename from pytket/qir/conversion/conversion.py rename to pytket/qir/conversion/qirgenerator.py index 2d8bc7da..99c28c04 100644 --- a/pytket/qir/conversion/conversion.py +++ b/pytket/qir/conversion/qirgenerator.py @@ -12,11 +12,7 @@ # See the License for the specific language governing permissions and # limitations under the License. -""" -This module contains all functionality to generate QIR files -from pytket circuits. -""" - +import abc import math from collections.abc import Sequence from functools import partial @@ -99,7 +95,6 @@ BitXor: lambda b: b.xor, BitNeq: lambda b: partial(b.icmp, IntPredicate.NE), BitEq: lambda b: partial(b.icmp, IntPredicate.EQ), - BitNot: lambda b: b.and_, } _TK_CLOPS_TO_PYQIR_BIT: dict = { @@ -112,8 +107,9 @@ } -class QirGenerator: - """Generate QIR from a pytket circuit.""" +class AbstractQirGenerator: + """Abstract Class for the QIR generation from a pytket circuit. + Implementing the functionality that is not specific to any profile""" def __init__( self, @@ -126,6 +122,7 @@ def __init__( self.circuit = circuit self.module = module self.wasm_int_type = pyqir.IntType(self.module.context, wasm_int_type) + self.int_size = qir_int_type self.qir_int_type = pyqir.IntType(self.module.context, qir_int_type) self.qir_i1p_type = pyqir.PointerType(pyqir.IntType(self.module.context, 1)) self.qir_bool_type = pyqir.IntType(self.module.context, 1) @@ -133,14 +130,23 @@ def __init__( self.result_type = pyqir.result_type(self.module.context) self.cregs = _retrieve_registers(self.circuit.bits, BitRegister) + self.creg_size: dict[str, int] = {} self.target_gateset = self.module.gateset.base_gateset self.block_count = 0 + self.block_count_sb = 0 self.wasm_sar_dict: dict[str, str] = {} self.wasm_sar_dict["!llvm.module.flags"] = ( 'attributes #1 = { "wasm" }\n\n!llvm.module.flags' ) + self.wasm_sar_dict[ + 'attributes #1 = { "irreversible" }\n\nattributes #1 = { "wasm" }' + ] = 'attributes #1 = { "wasm" }\nattributes #2 = { "irreversible" }' + self.wasm_sar_dict[ + "declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1" + ] = "declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #2" + self.int_type_str = f"i{qir_int_type}" self.target_gateset.add(OpType.PhasedX) @@ -148,47 +154,12 @@ def __init__( self.target_gateset.add(OpType.ZZMax) self.target_gateset.add(OpType.TK2) + self.reg_const: dict[str, Value] = {} + self.getset_predicate = predicates.GateSetPredicate( set(self.target_gateset) ) # noqa: E501 - self.set_cregs: dict[str, list] = {} # Keep track of set registers. - self.ssa_vars: dict[str, Value] = {} # Keep track of set ssa variables. - - # i1 get_creg_bit(i1* creg, i64 index) - self.get_creg_bit = self.module.module.add_external_function( - "get_creg_bit", - pyqir.FunctionType( - pyqir.IntType(self.module.module.context, 1), - [self.qir_i1p_type, self.qir_int_type], - ), - ) - - # void set_creg_bit(i1* creg, i64 index, i1 value) - self.set_creg_bit = self.module.module.add_external_function( - "set_creg_bit", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - self.qir_i1p_type, - self.qir_int_type, - pyqir.IntType(self.module.module.context, 1), - ], - ), - ) - - # void set_creg_to_int(i1* creg, i64 value) - self.set_creg_to_int = self.module.module.add_external_function( - "set_creg_to_int", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - self.qir_i1p_type, - self.qir_int_type, - ], - ), - ) - # __quantum__qis__read_result__body(result) self.read_bit_from_result = self.module.module.add_external_function( "__quantum__qis__read_result__body", @@ -198,49 +169,7 @@ def __init__( ), ) - # i1* create_creg(i64 size) - self.create_creg = self.module.module.add_external_function( - "create_creg", - pyqir.FunctionType( - self.qir_i1p_type, - [pyqir.IntType(self.module.module.context, qir_int_type)], - ), - ) - - # i64 get_int_from_creg(i1* creg) - self.get_int_from_creg = self.module.module.add_external_function( - "get_int_from_creg", - pyqir.FunctionType( - self.qir_int_type, - [ - self.qir_i1p_type, - ], - ), - ) - - # void mz_to_creg_bit(qubit, i1* creg, int creg_index) - # measures one qubit to one bit entry in a creg - self.mz_to_creg_bit = self.module.module.add_external_function( - "mz_to_creg_bit", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [ - pyqir.qubit_type(self.module.module.context), - self.qir_i1p_type, - self.qir_int_type, - ], - ), - ) - - self.reg_const = {} - - for creg in self.circuit.c_registers: - reg_name = creg[0].reg_name - self.reg_const[reg_name] = self.module.module.add_byte_string( - str.encode(reg_name) - ) - - # void __quantum__rt__int_record_output(i64) + # void __quantum__rt__int_record_output(i64) self.record_output_i64 = self.module.module.add_external_function( "__quantum__rt__int_record_output", pyqir.FunctionType( @@ -252,24 +181,6 @@ def __init__( ), ) - # void __quantum__rt__tuple_start_record_output() - self.record_output_start = self.module.module.add_external_function( - "__quantum__rt__tuple_start_record_output", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [], - ), - ) - - # void __quantum__rt__tuple_end_record_output() - self.record_output_end = self.module.module.add_external_function( - "__quantum__rt__tuple_end_record_output", - pyqir.FunctionType( - pyqir.Type.void(self.module.module.context), - [], - ), - ) - self.barrier: list[Optional[pyqir.Function]] = [None] * ( self.circuit.n_qubits + 1 ) @@ -321,16 +232,25 @@ def __init__( self.additional_quantum_gates: dict[OpType, pyqir.Function] = {} - entry = self.module.module.entry_block - self.module.module.builder.insert_at_end(entry) + @abc.abstractmethod + def _get_bit_from_creg(self, creg: str, index: int) -> Value: + pass - for creg in self.circuit.c_registers: - self._reg2ssa_var(creg, qir_int_type) + @abc.abstractmethod + def _set_bit_in_creg(self, creg: str, index: int, ssa_bit: Value) -> None: + pass + @abc.abstractmethod def get_ssa_vars(self, reg_name: str) -> Value: - if reg_name not in self.ssa_vars: - raise ValueError(f"{reg_name} is not a valid register") - return self.ssa_vars[reg_name] + pass + + @abc.abstractmethod + def _get_i64_ssa_reg(self, name: str) -> Value: + pass + + @abc.abstractmethod + def set_ssa_vars(self, reg_name: str, ssa_i64: Value, trunc: bool) -> None: + pass def _add_barrier_op( self, module: tketqirModule, index: int, qir_qubits: Sequence @@ -415,19 +335,6 @@ def _add_sleep_op( ], ) - def _rebase_command_to_gateset(self, command: Command) -> Optional[Circuit]: - """Rebase to the target gateset if needed.""" - optype = command.op.type - params = command.op.params - args = command.args - if optype not in self.module.gateset.base_gateset: - circuit = Circuit(self.circuit.n_qubits, self.circuit.n_bits) - circuit.add_gate(optype, params, args) - if not self.getset_predicate.verify(circuit): - raise ValueError(f"Gate not supported {optype}, {params}, {args}") - return circuit - return None - def _decompose_conditional_circ_box(self, op: Op, args: list) -> Optional[Circuit]: """Rebase an op to the target gateset if needed.""" circuit = Circuit(self.circuit.n_qubits) @@ -449,13 +356,6 @@ def _get_optype_and_params(self, op: Op) -> tuple[OpType, Sequence[float]]: params = op.params return (optype, params) - def _get_i64_ssa_reg(self, name: str) -> Value: - ssa_var = self.module.builder.call( - self.get_int_from_creg, - [self.get_ssa_vars(name)], - ) - return ssa_var - def _to_qis_qubits(self, qubits: list[Qubit]) -> list[Qubit]: return [self.module.module.qubits[qubit.index[0]] for qubit in qubits] @@ -471,22 +371,6 @@ def _to_qis_bits(self, args: list[Bit]) -> Sequence[Value]: return [self.module.module.results[bit.index[0]] for bit in args[:-1]] return [] - def _reg2ssa_var(self, bit_reg: BitRegister, int_size: int) -> Value: - """Convert a BitRegister to an SSA variable using pyqir types.""" - reg_name = bit_reg[0].reg_name - if reg_name not in self.ssa_vars: - if len(bit_reg) > int_size: - raise ValueError( - f"Classical register should only have the size of {int_size}" - ) - ssa_var = self.module.builder.call( - self.create_creg, [pyqir.const(self.qir_int_type, len(bit_reg))] - ) - self.ssa_vars[reg_name] = ssa_var - return ssa_var - else: - return cast(Value, self.ssa_vars[reg_name]) # type: ignore - def _get_c_regs_from_com( self, op: Op, args: Union[Bit, Qubit] ) -> tuple[list[str], list[str]]: @@ -536,13 +420,7 @@ def _get_ssa_from_cl_bit_op( self, bit: Union[Bit, BitAnd, BitOr, BitXor], module: tketqirModule ) -> Value: if type(bit) is Bit: - result = module.builder.call( - self.get_creg_bit, - [ - self.get_ssa_vars(bit.reg_name), - pyqir.const(self.qir_int_type, bit.index[0]), - ], - ) + result = self._get_bit_from_creg(bit.reg_name, bit.index[0]) return result elif type(bit) is int: @@ -594,14 +472,7 @@ def conv_RangePredicateOp( condition_bit_index = args[-1].index[0] result_registername = args[-1].reg_name - self.module.builder.call( - self.set_creg_bit, - [ - self.get_ssa_vars(result_registername), - pyqir.const(self.qir_int_type, condition_bit_index), - result, - ], - ) + self._set_bit_in_creg(result_registername, condition_bit_index, result) else: lower_qir = pyqir.const(self.qir_int_type, op.lower) @@ -626,167 +497,24 @@ def conv_RangePredicateOp( condition_bit_index = args[-1].index[0] registername = args[-1].reg_name - self.module.builder.call( - self.set_creg_bit, - [ - self.get_ssa_vars(registername), - pyqir.const(self.qir_int_type, condition_bit_index), - result, - ], - ) + self._set_bit_in_creg(registername, condition_bit_index, result) + @abc.abstractmethod def conv_conditional(self, command: Command, op: Conditional) -> None: - condition_name = command.args[0].reg_name - - entry_point = self.module.module.entry_point - - condb = pyqir.BasicBlock( - self.module.module.context, f"condb{self.block_count}", entry_point - ) - contb = pyqir.BasicBlock( - self.module.module.context, f"contb{self.block_count}", entry_point - ) - self.block_count = self.block_count + 1 - - if op.op.type == OpType.CircBox: - conditional_circuit = self._decompose_conditional_circ_box( - op.op, command.args[op.width :] - ) - - condition_name = command.args[0].reg_name - - if op.width == 1: # only one conditional bit - - condition_bit_index = command.args[0].index[0] - - ssabool = self.module.builder.call( - self.get_creg_bit, - [ - self.get_ssa_vars(condition_name), - pyqir.const(self.qir_int_type, condition_bit_index), - ], - ) - - if op.value == 1: - self.module.module.builder.condbr(ssabool, condb, contb) - self.module.module.builder.insert_at_end(condb) - self.subcircuit_to_module(conditional_circuit) - - if op.value == 0: - self.module.module.builder.condbr(ssabool, contb, condb) - self.module.module.builder.insert_at_end(condb) - self.subcircuit_to_module(conditional_circuit) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) - - else: - for i in range(op.width): - if command.args[i].reg_name != condition_name: - raise ValueError( - "conditional can only work with one entire register" - ) - - for i in range(op.width - 1): - if command.args[i].index[0] >= command.args[i + 1].index[0]: - raise ValueError( - "conditional can only work with one entire register" - ) - - if self.circuit.get_c_register(condition_name).size != op.width: - raise ValueError( - "conditional can only work with one entire register" - ) - - ssabool = self.module.module.builder.icmp( - pyqir.IntPredicate.EQ, - pyqir.const(self.qir_int_type, op.value), - self._get_i64_ssa_reg(condition_name), - ) - - self.module.module.builder.condbr(ssabool, condb, contb) - - self.module.module.builder.insert_at_end(condb) - - self.subcircuit_to_module(conditional_circuit) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) - - else: - condition_name = command.args[0].reg_name - - if op.width == 1: # only one conditional bit - condition_bit_index = command.args[0].index[0] - - ssabool = self.module.builder.call( - self.get_creg_bit, - [ - self.get_ssa_vars(condition_name), - pyqir.const(self.qir_int_type, condition_bit_index), - ], - ) - - if op.value == 1: - self.module.module.builder.condbr(ssabool, condb, contb) - self.module.module.builder.insert_at_end(condb) - self.command_to_module(op.op, command.args[op.width :]) - - if op.value == 0: - self.module.module.builder.condbr(ssabool, contb, condb) - self.module.module.builder.insert_at_end(condb) - self.command_to_module(op.op, command.args[op.width :]) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) - - else: - for i in range(op.width): - if command.args[i].reg_name != condition_name: - raise ValueError( - "conditional can only work with one entire register" - ) - - for i in range(op.width - 1): - if command.args[i].index[0] >= command.args[i + 1].index[0]: - raise ValueError( - "conditional can only work with one entire register" - ) - - if self.circuit.get_c_register(condition_name).size != op.width: - raise ValueError( - "conditional can only work with one entire register" - ) - - ssabool = self.module.module.builder.icmp( - pyqir.IntPredicate.EQ, - pyqir.const(self.qir_int_type, op.value), - self._get_i64_ssa_reg(condition_name), - ) - - self.module.module.builder.condbr(ssabool, condb, contb) - self.module.module.builder.insert_at_end(condb) - - self.command_to_module(op.op, command.args[op.width :]) - - self.module.module.builder.br(contb) - self.module.module.builder.insert_at_end(contb) + pass def conv_WASMOp(self, op: WASMOp, args: Union[Bit, Qubit]) -> None: paramreg, resultreg = self._get_c_regs_from_com(op, args) - paramssa = [self._get_i64_ssa_reg(p) for p in paramreg] + ssa_param = [self._get_i64_ssa_reg(p) for p in paramreg] result = self.module.builder.call( self.wasm[op.func_name], - [*paramssa], + [*ssa_param], ) if len(resultreg) == 1: - self.module.builder.call( - self.set_creg_to_int, - [self.get_ssa_vars(resultreg[0]), result], - ) + self.set_ssa_vars(resultreg[0], result, True) def conv_ZZPhase(self, qubits: list[Qubit], op: Op) -> None: if OpType.ZZPhase not in self.additional_quantum_gates: @@ -908,15 +636,9 @@ def conv_zzmax(self, qubits: list[Qubit]) -> None: ], ) + @abc.abstractmethod def conv_measure(self, bits: list[Bit], qubits: list[Qubit]) -> None: - self.module.builder.call( - self.mz_to_creg_bit, - [ - self.module.module.qubits[qubits[0].index[0]], - self.get_ssa_vars(bits[0].reg_name), - pyqir.const(self.qir_int_type, bits[0].index[0]), - ], - ) + pass def conv_classicalexpbox(self, op: ClassicalExpBox, args: list) -> None: returntypebool = False @@ -1019,19 +741,9 @@ def conv_classicalexpbox(self, op: ClassicalExpBox, args: list) -> None: # to the 0-th entry # of the register, this could be changed to a user given value - self.module.builder.call( - self.set_creg_bit, - [ - self.get_ssa_vars(outputs), - pyqir.const(self.qir_int_type, result_index), - output_instruction, - ], - ) + self._set_bit_in_creg(outputs, result_index, output_instruction) else: - self.module.builder.call( - self.set_creg_to_int, - [self.get_ssa_vars(outputs), output_instruction], - ) + self.set_ssa_vars(outputs, output_instruction, True) def conv_SetBitsOp(self, bits: list[Bit], op: SetBitsOp) -> None: assert len(op.values) == len(bits) @@ -1039,36 +751,16 @@ def conv_SetBitsOp(self, bits: list[Bit], op: SetBitsOp) -> None: for b, v in zip(bits, op.values): output_instruction = pyqir.const(self.qir_bool_type, int(v)) - self.module.builder.call( - self.set_creg_bit, - [ - self.get_ssa_vars(b.reg_name), - pyqir.const(self.qir_int_type, b.index[0]), - output_instruction, - ], - ) + self._set_bit_in_creg(b.reg_name, b.index[0], output_instruction) def conv_CopyBitsOp(self, args: list) -> None: assert len(args) % 2 == 0 half_length = len(args) // 2 for i, o in zip(args[:half_length], args[half_length:]): - output_instruction = self.module.builder.call( - self.get_creg_bit, - [ - self.get_ssa_vars(i.reg_name), - pyqir.const(self.qir_int_type, i.index[0]), - ], - ) + output_instruction = self._get_bit_from_creg(i.reg_name, i.index[0]) - self.module.builder.call( - self.set_creg_bit, - [ - self.get_ssa_vars(o.reg_name), - pyqir.const(self.qir_int_type, o.index[0]), - output_instruction, - ], - ) + self._set_bit_in_creg(o.reg_name, o.index[0], output_instruction) def conv_BarrierOp(self, qubits: list[Qubit], op: BarrierOp) -> None: assert qubits[0].reg_name == "q" @@ -1181,10 +873,6 @@ def circuit_to_module( self.command_to_module(op, command.args) if record_output: - self.module.builder.call( - self.record_output_start, - [], - ) for creg in self.circuit.c_registers: reg_name = creg[0].reg_name @@ -1196,11 +884,6 @@ def circuit_to_module( ], ) - self.module.builder.call( - self.record_output_end, - [], - ) - return self.module def subcircuit_to_module( diff --git a/tests/conditional_test.py b/tests/conditional_test.py index 2db689b4..2913aed5 100644 --- a/tests/conditional_test.py +++ b/tests/conditional_test.py @@ -27,17 +27,18 @@ reg_eq, ) from pytket.circuit.logic_exp import BitNot, BitWiseOp, create_bit_logic_exp -from pytket.qir.conversion.api import QIRFormat, pytket_to_qir +from pytket.qir.conversion.api import QIRFormat, QIRProfile, pytket_to_qir @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional(profile: bool) -> None: +def test_pytket_qir_conditional(profile: QIRProfile) -> None: # test conditional handling circ = Circuit(3) @@ -62,11 +63,12 @@ def test_pytket_qir_conditional(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_2(profile: bool) -> None: +def test_pytket_qir_conditional_2(profile: QIRProfile) -> None: # test conditional handling with else case circ = Circuit(3) @@ -93,11 +95,12 @@ def test_pytket_qir_conditional_2(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_3(profile: bool) -> None: +def test_pytket_qir_conditional_3(profile: QIRProfile) -> None: # test complicated conditions and recursive classical op circ = Circuit(1) @@ -122,11 +125,12 @@ def test_pytket_qir_conditional_3(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_4(profile: bool) -> None: +def test_pytket_qir_conditional_4(profile: QIRProfile) -> None: # test complicated conditions and recursive classical op circ = Circuit(2, 2).H(0).H(1).measure_all() @@ -139,11 +143,12 @@ def test_pytket_qir_conditional_4(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_5(profile: bool) -> None: +def test_pytket_qir_conditional_5(profile: QIRProfile) -> None: # test complicated conditions and recursive classical op circ = Circuit(2, 3).H(0).H(1).measure_all() @@ -156,11 +161,12 @@ def test_pytket_qir_conditional_5(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_6(profile: bool) -> None: +def test_pytket_qir_conditional_6(profile: QIRProfile) -> None: # test conditional for manual added gates circ = Circuit(2, 3).H(0).H(1) @@ -175,11 +181,12 @@ def test_pytket_qir_conditional_6(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_7(profile: bool) -> None: +def test_pytket_qir_conditional_7(profile: QIRProfile) -> None: circ = Circuit(7, name="testcirc") syn = circ.add_c_register("syn", 4) @@ -197,11 +204,12 @@ def test_pytket_qir_conditional_7(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_8(profile: bool) -> None: +def test_pytket_qir_conditional_8(profile: QIRProfile) -> None: c = Circuit(4) c.H(0) c.H(1) @@ -218,11 +226,12 @@ def test_pytket_qir_conditional_8(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_9(profile: bool) -> None: +def test_pytket_qir_conditional_9(profile: QIRProfile) -> None: c = Circuit(4) c.X(0) c.Y(1) @@ -239,11 +248,12 @@ def test_pytket_qir_conditional_9(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_10(profile: bool) -> None: +def test_pytket_qir_conditional_10(profile: QIRProfile) -> None: box_circ = Circuit(4) box_circ.X(0) box_circ.Y(1) @@ -265,11 +275,12 @@ def test_pytket_qir_conditional_10(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_11(profile: bool) -> None: +def test_pytket_qir_conditional_11(profile: QIRProfile) -> None: box_circ = Circuit(4) box_circ.X(0) box_circ.Y(1) @@ -293,11 +304,12 @@ def test_pytket_qir_conditional_11(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_12(profile: bool) -> None: +def test_pytket_qir_conditional_12(profile: QIRProfile) -> None: # test conditional with to big scratch register circ = Circuit(7, name="testcirc") @@ -326,11 +338,12 @@ def test_pytket_qir_conditional_12(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_13(profile: bool) -> None: +def test_pytket_qir_conditional_13(profile: QIRProfile) -> None: # test conditional with no register circ = Circuit(7, name="testcirc") @@ -346,11 +359,12 @@ def test_pytket_qir_conditional_13(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_14(profile: bool) -> None: +def test_pytket_qir_conditional_14(profile: QIRProfile) -> None: box_circ = Circuit(4) box_circ.X(0) box_c = box_circ.add_c_register("c", 5) @@ -370,11 +384,12 @@ def test_pytket_qir_conditional_14(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_15(profile: bool) -> None: +def test_pytket_qir_conditional_15(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="ptest_classical") a = c.add_c_register("a", 10) @@ -393,11 +408,12 @@ def test_pytket_qir_conditional_15(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_16(profile: bool) -> None: +def test_pytket_qir_conditional_16(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="ptest_classical") a = c.add_c_register("a", 10) @@ -418,11 +434,12 @@ def test_pytket_qir_conditional_16(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_17(profile: bool) -> None: +def test_pytket_qir_conditional_17(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="ptest_classical") a = c.add_c_register("a", 1) @@ -448,11 +465,12 @@ def test_pytket_qir_conditional_17(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_18(profile: bool) -> None: +def test_pytket_qir_conditional_18(profile: QIRProfile) -> None: c = Circuit(1, 1, name="ptest_classical") c.H(0, condition=BitNot(c.bits[0])) run_qir_gen_and_check(c, "test_pytket_qir_conditional_18", profile=profile) @@ -461,11 +479,12 @@ def test_pytket_qir_conditional_18(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_19(profile: bool) -> None: +def test_pytket_qir_conditional_19(profile: QIRProfile) -> None: c = Circuit(1, 2, name="ptest_classical") c.H(0) @@ -478,11 +497,12 @@ def test_pytket_qir_conditional_19(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_conditional_20(profile: bool) -> None: +def test_pytket_qir_conditional_20(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="ptest_classical") a = c.add_c_register("a", 32) @@ -493,4 +513,4 @@ def test_pytket_qir_conditional_20(profile: bool) -> None: if __name__ == "__main__": - test_pytket_qir_conditional(True) + test_pytket_qir_conditional(QIRProfile.PYTKET) diff --git a/tests/conversion_test.py b/tests/conversion_test.py index 12b90d25..450be101 100644 --- a/tests/conversion_test.py +++ b/tests/conversion_test.py @@ -25,17 +25,18 @@ reg_neq, ) from pytket.passes import FlattenRelabelRegistersPass -from pytket.qir.conversion.api import QIRFormat, pytket_to_qir +from pytket.qir.conversion.api import QIRFormat, QIRProfile, pytket_to_qir @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir(profile: bool) -> None: +def test_pytket_qir(profile: QIRProfile) -> None: circ = Circuit(3) circ.H(0) @@ -45,11 +46,12 @@ def test_pytket_qir(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_2(profile: bool) -> None: +def test_pytket_qir_2(profile: QIRProfile) -> None: circ = Circuit(3) circ.H(0) @@ -59,11 +61,12 @@ def test_pytket_qir_2(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_3(profile: bool) -> None: +def test_pytket_qir_3(profile: QIRProfile) -> None: circ = Circuit(3, 3) circ.H(0) circ.H(1) @@ -75,11 +78,12 @@ def test_pytket_qir_3(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_4(profile: bool) -> None: +def test_pytket_qir_4(profile: QIRProfile) -> None: # test conditional handling circ = Circuit(3) @@ -97,11 +101,12 @@ def test_pytket_qir_4(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_5(profile: bool) -> None: +def test_pytket_qir_5(profile: QIRProfile) -> None: # test conditional handling circ = Circuit(3) @@ -127,11 +132,12 @@ def test_pytket_qir_5(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_6(profile: bool) -> None: +def test_pytket_qir_6(profile: QIRProfile) -> None: # test conditional handling circ = Circuit(3) @@ -153,11 +159,12 @@ def test_pytket_qir_6(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_7(profile: bool) -> None: +def test_pytket_qir_7(profile: QIRProfile) -> None: # test calssical exp box handling circ = Circuit(2) a = circ.add_c_register("a", 3) @@ -186,11 +193,12 @@ def test_pytket_qir_7(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_8(profile: bool) -> None: +def test_pytket_qir_8(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="test_classical") a = c.add_c_register("a", 8) @@ -207,11 +215,12 @@ def test_pytket_qir_8(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_9(profile: bool) -> None: +def test_pytket_qir_9(profile: QIRProfile) -> None: # test copybits op c = Circuit(1, name="test_classical") a = c.add_c_register("a", 2) @@ -225,11 +234,12 @@ def test_pytket_qir_9(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_10(profile: bool) -> None: +def test_pytket_qir_10(profile: QIRProfile) -> None: # test copybits op c = Circuit(1, name="test_classical") a = c.add_c_register("a", 4) @@ -243,11 +253,12 @@ def test_pytket_qir_10(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_11(profile: bool) -> None: +def test_pytket_qir_11(profile: QIRProfile) -> None: # test copybits op c = Circuit(1, name="test_classical") a = c.add_c_register("a", 2) @@ -261,11 +272,12 @@ def test_pytket_qir_11(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_12(profile: bool) -> None: +def test_pytket_qir_12(profile: QIRProfile) -> None: # test << and >> ops c = Circuit(1, name="test_classical") a = c.add_c_register("a", 8) @@ -278,11 +290,12 @@ def test_pytket_qir_12(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_13(profile: bool) -> None: +def test_pytket_qir_13(profile: QIRProfile) -> None: # test << and >> ops c = Circuit(1, name="test_classical") a = c.add_c_register("a", 8) @@ -297,11 +310,12 @@ def test_pytket_qir_13(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_14(profile: bool) -> None: +def test_pytket_qir_14(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="test_classical") a = c.add_c_register("a", 8) @@ -341,11 +355,12 @@ def test_pytket_qir_14(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_15(profile: bool) -> None: +def test_pytket_qir_15(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="test_classical") a = c.add_c_register("a", 32) @@ -385,11 +400,12 @@ def test_pytket_qir_15(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_16(profile: bool) -> None: +def test_pytket_qir_16(profile: QIRProfile) -> None: # test setbits op c = Circuit(1, name="test_classical") a = c.add_c_register("a", 10) @@ -408,11 +424,12 @@ def test_pytket_qir_16(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_17(profile: bool) -> None: +def test_pytket_qir_17(profile: QIRProfile) -> None: # test calssical exp box handling # circuit to cover capabilities covered in example notebook c = Circuit(0, 1, name="test_classical") @@ -425,11 +442,12 @@ def test_pytket_qir_17(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_18(profile: bool) -> None: +def test_pytket_qir_18(profile: QIRProfile) -> None: # try circuit with multi-circuit register c = Circuit() q1 = Qubit("q1", 0) @@ -459,11 +477,12 @@ def test_pytket_qir_18(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_19(profile: bool) -> None: +def test_pytket_qir_19(profile: QIRProfile) -> None: # try circuit with multi-circuit register c = Circuit() q1 = Qubit("q1", 0) @@ -485,22 +504,22 @@ def test_pytket_qir_19(profile: bool) -> None: if __name__ == "__main__": - test_pytket_qir(True) - test_pytket_qir_2(True) - test_pytket_qir_3(True) - test_pytket_qir_4(True) - test_pytket_qir_5(True) - test_pytket_qir_6(True) - test_pytket_qir_7(True) - test_pytket_qir_8(True) - test_pytket_qir_9(True) - test_pytket_qir_10(True) - test_pytket_qir_11(True) - test_pytket_qir_12(True) - test_pytket_qir_13(True) - test_pytket_qir_14(True) - test_pytket_qir_15(True) - test_pytket_qir_16(True) - test_pytket_qir_17(True) - test_pytket_qir_18(True) - test_pytket_qir_19(True) + test_pytket_qir(QIRProfile.PYTKET) + test_pytket_qir_2(QIRProfile.PYTKET) + test_pytket_qir_3(QIRProfile.PYTKET) + test_pytket_qir_4(QIRProfile.PYTKET) + test_pytket_qir_5(QIRProfile.PYTKET) + test_pytket_qir_6(QIRProfile.PYTKET) + test_pytket_qir_7(QIRProfile.PYTKET) + test_pytket_qir_8(QIRProfile.PYTKET) + test_pytket_qir_9(QIRProfile.PYTKET) + test_pytket_qir_10(QIRProfile.PYTKET) + test_pytket_qir_11(QIRProfile.PYTKET) + test_pytket_qir_12(QIRProfile.PYTKET) + test_pytket_qir_13(QIRProfile.PYTKET) + test_pytket_qir_14(QIRProfile.PYTKET) + test_pytket_qir_15(QIRProfile.PYTKET) + test_pytket_qir_16(QIRProfile.PYTKET) + test_pytket_qir_17(QIRProfile.PYTKET) + test_pytket_qir_18(QIRProfile.PYTKET) + test_pytket_qir_19(QIRProfile.PYTKET) diff --git a/tests/qir/test_pytket_qir-True.ll b/tests/qir/test_pytket_qir-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir-True.ll rename to tests/qir/test_pytket_qir-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..173ace24 --- /dev/null +++ b/tests/qir/test_pytket_qir-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,26 @@ +; ModuleID = 'test_pytket_qir' +source_filename = "test_pytket_qir" + +%Qubit = type opaque +%Result = type opaque + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir-False.ll b/tests/qir/test_pytket_qir-QIRProfile.PYTKET.ll similarity index 81% rename from tests/qir/test_pytket_qir-False.ll rename to tests/qir/test_pytket_qir-QIRProfile.PYTKET.ll index 8cb92ba2..d23fd79d 100644 --- a/tests/qir/test_pytket_qir-False.ll +++ b/tests/qir/test_pytket_qir-QIRProfile.PYTKET.ll @@ -7,31 +7,25 @@ source_filename = "test_pytket_qir" define void @main() #0 { entry: call void @__quantum__qis__h__body(%Qubit* null) - call void @__quantum__rt__tuple_start_record_output() - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_10-True.ll b/tests/qir/test_pytket_qir_10-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_10-True.ll rename to tests/qir/test_pytket_qir_10-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_10-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_10-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..0a4e3581 --- /dev/null +++ b/tests/qir/test_pytket_qir_10-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,27 @@ +; ModuleID = 'test_pytket_qir_10' +source_filename = "test_pytket_qir_10" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_10-False.ll b/tests/qir/test_pytket_qir_10-QIRProfile.PYTKET.ll similarity index 87% rename from tests/qir/test_pytket_qir_10-False.ll rename to tests/qir/test_pytket_qir_10-QIRProfile.PYTKET.ll index ae830521..7b365c7b 100644 --- a/tests/qir/test_pytket_qir_10-False.ll +++ b/tests/qir/test_pytket_qir_10-QIRProfile.PYTKET.ll @@ -15,35 +15,29 @@ entry: call void @set_creg_bit(i1* %1, i64 0, i1 %2) %3 = call i1 @get_creg_bit(i1* %0, i64 1) call void @set_creg_bit(i1* %1, i64 1, i1 %3) - call void @__quantum__rt__tuple_start_record_output() %4 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %4, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %5 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %5, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_11-True.ll b/tests/qir/test_pytket_qir_11-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_11-True.ll rename to tests/qir/test_pytket_qir_11-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_11-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_11-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..7e601c1a --- /dev/null +++ b/tests/qir/test_pytket_qir_11-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,27 @@ +; ModuleID = 'test_pytket_qir_11' +source_filename = "test_pytket_qir_11" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_11-False.ll b/tests/qir/test_pytket_qir_11-QIRProfile.PYTKET.ll similarity index 87% rename from tests/qir/test_pytket_qir_11-False.ll rename to tests/qir/test_pytket_qir_11-QIRProfile.PYTKET.ll index 531e3857..a9779778 100644 --- a/tests/qir/test_pytket_qir_11-False.ll +++ b/tests/qir/test_pytket_qir_11-QIRProfile.PYTKET.ll @@ -15,35 +15,29 @@ entry: call void @set_creg_bit(i1* %1, i64 0, i1 %2) %3 = call i1 @get_creg_bit(i1* %0, i64 1) call void @set_creg_bit(i1* %1, i64 1, i1 %3) - call void @__quantum__rt__tuple_start_record_output() %4 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %4, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %5 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %5, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_12-True.ll b/tests/qir/test_pytket_qir_12-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_12-True.ll rename to tests/qir/test_pytket_qir_12-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_12-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_12-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..8bb6ead9 --- /dev/null +++ b/tests/qir/test_pytket_qir_12-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,25 @@ +; ModuleID = 'test_pytket_qir_12' +source_filename = "test_pytket_qir_12" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_12-False.ll b/tests/qir/test_pytket_qir_12-QIRProfile.PYTKET.ll similarity index 84% rename from tests/qir/test_pytket_qir_12-False.ll rename to tests/qir/test_pytket_qir_12-QIRProfile.PYTKET.ll index 2d8a4286..81437716 100644 --- a/tests/qir/test_pytket_qir_12-False.ll +++ b/tests/qir/test_pytket_qir_12-QIRProfile.PYTKET.ll @@ -12,33 +12,27 @@ entry: %1 = call i64 @get_int_from_creg(i1* %0) %2 = shl i64 %1, 1 call void @set_creg_to_int(i1* %0, i64 %2) - call void @__quantum__rt__tuple_start_record_output() %3 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_13-True.ll b/tests/qir/test_pytket_qir_13-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_13-True.ll rename to tests/qir/test_pytket_qir_13-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_13-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_13-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..a3276000 --- /dev/null +++ b/tests/qir/test_pytket_qir_13-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,27 @@ +; ModuleID = 'test_pytket_qir_13' +source_filename = "test_pytket_qir_13" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_13-False.ll b/tests/qir/test_pytket_qir_13-QIRProfile.PYTKET.ll similarity index 87% rename from tests/qir/test_pytket_qir_13-False.ll rename to tests/qir/test_pytket_qir_13-QIRProfile.PYTKET.ll index 3250d1d3..0d59295e 100644 --- a/tests/qir/test_pytket_qir_13-False.ll +++ b/tests/qir/test_pytket_qir_13-QIRProfile.PYTKET.ll @@ -17,35 +17,29 @@ entry: %4 = call i64 @get_int_from_creg(i1* %0) %5 = lshr i64 %4, 3 call void @set_creg_to_int(i1* %1, i64 %5) - call void @__quantum__rt__tuple_start_record_output() %6 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %6, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %7 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_14-True.ll b/tests/qir/test_pytket_qir_14-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_14-True.ll rename to tests/qir/test_pytket_qir_14-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_14-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_14-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..fd80764c --- /dev/null +++ b/tests/qir/test_pytket_qir_14-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,123 @@ +; ModuleID = 'test_pytket_qir_14' +source_filename = "test_pytket_qir_14" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"d\00" +@3 = internal constant [15 x i8] c"tk_SCRATCH_BIT\00" +@4 = internal constant [20 x i8] c"tk_SCRATCH_BITREG_0\00" +@5 = internal constant [20 x i8] c"tk_SCRATCH_BITREG_1\00" +@6 = internal constant [20 x i8] c"tk_SCRATCH_BITREG_2\00" + +define void @main() #0 { +entry: + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + br label %contb0 + +contb0: ; preds = %condb0, %entry + br i1 false, label %condb1, label %contb1 + +condb1: ; preds = %contb0 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb1 + +contb1: ; preds = %condb1, %contb0 + br i1 true, label %condb2, label %contb2 + +condb2: ; preds = %contb1 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb2 + +contb2: ; preds = %condb2, %contb1 + br i1 false, label %condb3, label %contb3 + +condb3: ; preds = %contb2 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb3 + +contb3: ; preds = %condb3, %contb2 + br i1 false, label %condb4, label %contb4 + +condb4: ; preds = %contb3 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb4 + +contb4: ; preds = %condb4, %contb3 + br i1 false, label %condb5, label %contb5 + +condb5: ; preds = %contb4 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb5 + +contb5: ; preds = %condb5, %contb4 + br i1 false, label %contb6, label %condb6 + +condb6: ; preds = %contb5 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb6 + +contb6: ; preds = %condb6, %contb5 + br i1 false, label %contb7, label %condb7 + +condb7: ; preds = %contb6 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb7 + +contb7: ; preds = %condb7, %contb6 + br i1 false, label %condb8, label %contb8 + +condb8: ; preds = %contb7 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb8 + +contb8: ; preds = %condb8, %contb7 + br i1 false, label %condb9, label %contb9 + +condb9: ; preds = %contb8 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb9 + +contb9: ; preds = %condb9, %contb8 + br i1 false, label %condb10, label %contb10 + +condb10: ; preds = %contb9 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb10 + +contb10: ; preds = %condb10, %contb9 + br i1 false, label %condb11, label %contb11 + +condb11: ; preds = %contb10 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb11 + +contb11: ; preds = %condb11, %contb10 + call void @__quantum__rt__int_record_output(i64 46, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 23, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 2, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @3, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 57, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @4, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 6, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @5, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 63, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @6, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_14-False.ll b/tests/qir/test_pytket_qir_14-QIRProfile.PYTKET.ll similarity index 97% rename from tests/qir/test_pytket_qir_14-False.ll rename to tests/qir/test_pytket_qir_14-QIRProfile.PYTKET.ll index 1c2f4aed..d6598773 100644 --- a/tests/qir/test_pytket_qir_14-False.ll +++ b/tests/qir/test_pytket_qir_14-QIRProfile.PYTKET.ll @@ -222,7 +222,6 @@ condb11: ; preds = %contb10 br label %contb11 contb11: ; preds = %condb11, %contb10 - call void @__quantum__rt__tuple_start_record_output() %74 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %74, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %75 = call i64 @get_int_from_creg(i1* %1) @@ -237,30 +236,25 @@ contb11: ; preds = %condb11, %contb10 call void @__quantum__rt__int_record_output(i64 %79, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @5, i32 0, i32 0)) %80 = call i64 @get_int_from_creg(i1* %6) call void @__quantum__rt__int_record_output(i64 %80, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @6, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } diff --git a/tests/qir/test_pytket_qir_15-True.ll b/tests/qir/test_pytket_qir_15-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_15-True.ll rename to tests/qir/test_pytket_qir_15-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_15-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_15-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..b04dee3f --- /dev/null +++ b/tests/qir/test_pytket_qir_15-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,123 @@ +; ModuleID = 'test_pytket_qir_15' +source_filename = "test_pytket_qir_15" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"d\00" +@3 = internal constant [15 x i8] c"tk_SCRATCH_BIT\00" +@4 = internal constant [20 x i8] c"tk_SCRATCH_BITREG_0\00" +@5 = internal constant [20 x i8] c"tk_SCRATCH_BITREG_1\00" +@6 = internal constant [20 x i8] c"tk_SCRATCH_BITREG_2\00" + +define void @main() #0 { +entry: + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + br label %contb0 + +contb0: ; preds = %condb0, %entry + br i1 false, label %condb1, label %contb1 + +condb1: ; preds = %contb0 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb1 + +contb1: ; preds = %condb1, %contb0 + br i1 true, label %condb2, label %contb2 + +condb2: ; preds = %contb1 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb2 + +contb2: ; preds = %condb2, %contb1 + br i1 false, label %condb3, label %contb3 + +condb3: ; preds = %contb2 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb3 + +contb3: ; preds = %condb3, %contb2 + br i1 false, label %condb4, label %contb4 + +condb4: ; preds = %contb3 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb4 + +contb4: ; preds = %condb4, %contb3 + br i1 false, label %condb5, label %contb5 + +condb5: ; preds = %contb4 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb5 + +contb5: ; preds = %condb5, %contb4 + br i1 false, label %contb6, label %condb6 + +condb6: ; preds = %contb5 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb6 + +contb6: ; preds = %condb6, %contb5 + br i1 false, label %contb7, label %condb7 + +condb7: ; preds = %contb6 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb7 + +contb7: ; preds = %condb7, %contb6 + br i1 false, label %condb8, label %contb8 + +condb8: ; preds = %contb7 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb8 + +contb8: ; preds = %condb8, %contb7 + br i1 false, label %condb9, label %contb9 + +condb9: ; preds = %contb8 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb9 + +contb9: ; preds = %condb9, %contb8 + br i1 false, label %condb10, label %contb10 + +condb10: ; preds = %contb9 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb10 + +contb10: ; preds = %condb10, %contb9 + br i1 false, label %condb11, label %contb11 + +condb11: ; preds = %contb10 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb11 + +contb11: ; preds = %condb11, %contb10 + call void @__quantum__rt__int_record_output(i64 46, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 23, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 2, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @3, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 57, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @4, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 6, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @5, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 63, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @6, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_15-False.ll b/tests/qir/test_pytket_qir_15-QIRProfile.PYTKET.ll similarity index 98% rename from tests/qir/test_pytket_qir_15-False.ll rename to tests/qir/test_pytket_qir_15-QIRProfile.PYTKET.ll index be302b34..d8269738 100644 --- a/tests/qir/test_pytket_qir_15-False.ll +++ b/tests/qir/test_pytket_qir_15-QIRProfile.PYTKET.ll @@ -340,7 +340,6 @@ condb11: ; preds = %contb10 br label %contb11 contb11: ; preds = %condb11, %contb10 - call void @__quantum__rt__tuple_start_record_output() %98 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %98, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %99 = call i64 @get_int_from_creg(i1* %1) @@ -355,30 +354,25 @@ contb11: ; preds = %condb11, %contb10 call void @__quantum__rt__int_record_output(i64 %103, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @5, i32 0, i32 0)) %104 = call i64 @get_int_from_creg(i1* %6) call void @__quantum__rt__int_record_output(i64 %104, i8* getelementptr inbounds ([20 x i8], [20 x i8]* @6, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } diff --git a/tests/qir/test_pytket_qir_16-True.ll b/tests/qir/test_pytket_qir_16-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_16-True.ll rename to tests/qir/test_pytket_qir_16-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_16-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_16-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..0727b09b --- /dev/null +++ b/tests/qir/test_pytket_qir_16-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,45 @@ +; ModuleID = 'test_pytket_qir_16' +source_filename = "test_pytket_qir_16" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + %8 = add i64 %7, 3 + %9 = trunc i64 %8 to i20 + %10 = zext i20 %9 to i64 + call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %10, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_16-False.ll b/tests/qir/test_pytket_qir_16-QIRProfile.PYTKET.ll similarity index 91% rename from tests/qir/test_pytket_qir_16-False.ll rename to tests/qir/test_pytket_qir_16-QIRProfile.PYTKET.ll index fb623e99..39900fd8 100644 --- a/tests/qir/test_pytket_qir_16-False.ll +++ b/tests/qir/test_pytket_qir_16-QIRProfile.PYTKET.ll @@ -29,37 +29,31 @@ entry: %4 = call i64 @get_int_from_creg(i1* %1) %5 = add i64 %3, %4 call void @set_creg_to_int(i1* %2, i64 %5) - call void @__quantum__rt__tuple_start_record_output() %6 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %6, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %7 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) %8 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %8, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_17-True.ll b/tests/qir/test_pytket_qir_17-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_17-True.ll rename to tests/qir/test_pytket_qir_17-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_17-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_17-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..df84527a --- /dev/null +++ b/tests/qir/test_pytket_qir_17-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,27 @@ +; ModuleID = 'test_pytket_qir_17' +source_filename = "test_pytket_qir_17" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 32, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="0" "required_num_results"="0" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_17-False.ll b/tests/qir/test_pytket_qir_17-QIRProfile.PYTKET.ll similarity index 88% rename from tests/qir/test_pytket_qir_17-False.ll rename to tests/qir/test_pytket_qir_17-QIRProfile.PYTKET.ll index 10ca6ee6..f34780bc 100644 --- a/tests/qir/test_pytket_qir_17-False.ll +++ b/tests/qir/test_pytket_qir_17-QIRProfile.PYTKET.ll @@ -19,35 +19,29 @@ entry: call void @set_creg_bit(i1* %0, i64 5, i1 true) call void @set_creg_bit(i1* %0, i64 6, i1 false) call void @set_creg_bit(i1* %0, i64 7, i1 false) - call void @__quantum__rt__tuple_start_record_output() %2 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %2, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %3 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="0" "required_num_results"="0" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_19-True.ll b/tests/qir/test_pytket_qir_19-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_19-True.ll rename to tests/qir/test_pytket_qir_19-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_19-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_19-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..1637ce03 --- /dev/null +++ b/tests/qir/test_pytket_qir_19-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,55 @@ +; ModuleID = 'test_pytket_qir_19' +source_filename = "test_pytket_qir_19" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [3 x i8] c"c1\00" +@1 = internal constant [3 x i8] c"c2\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__cnot__body(%Qubit* null, %Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 1 to %Qubit*), %Result* inttoptr (i64 1 to %Result*)) + %8 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 1 to %Result*)) + %9 = zext i1 %8 to i64 + %10 = mul i64 %9, 1 + %11 = or i64 %10, 0 + %12 = sub i64 1, %9 + %13 = mul i64 %12, 1 + %14 = xor i64 9223372036854775807, %13 + %15 = and i64 %14, %11 + call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %15, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__cnot__body(%Qubit*, %Qubit*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_19-False.ll b/tests/qir/test_pytket_qir_19-QIRProfile.PYTKET.ll similarity index 88% rename from tests/qir/test_pytket_qir_19-False.ll rename to tests/qir/test_pytket_qir_19-QIRProfile.PYTKET.ll index c4606638..ae71a973 100644 --- a/tests/qir/test_pytket_qir_19-False.ll +++ b/tests/qir/test_pytket_qir_19-QIRProfile.PYTKET.ll @@ -15,35 +15,29 @@ entry: call void @__quantum__qis__cnot__body(%Qubit* null, %Qubit* inttoptr (i64 1 to %Qubit*)) call void @mz_to_creg_bit(%Qubit* null, i1* %0, i64 0) call void @mz_to_creg_bit(%Qubit* inttoptr (i64 1 to %Qubit*), i1* %1, i64 0) - call void @__quantum__rt__tuple_start_record_output() %2 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %2, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @0, i32 0, i32 0)) %3 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) declare void @__quantum__qis__cnot__body(%Qubit*, %Qubit*) diff --git a/tests/qir/test_pytket_qir_2-True.ll b/tests/qir/test_pytket_qir_2-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_2-True.ll rename to tests/qir/test_pytket_qir_2-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_2-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_2-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..bd64c477 --- /dev/null +++ b/tests/qir/test_pytket_qir_2-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,26 @@ +; ModuleID = 'test_pytket_qir_2' +source_filename = "test_pytket_qir_2" + +%Qubit = type opaque +%Result = type opaque + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_2-False.ll b/tests/qir/test_pytket_qir_2-QIRProfile.PYTKET.ll similarity index 81% rename from tests/qir/test_pytket_qir_2-False.ll rename to tests/qir/test_pytket_qir_2-QIRProfile.PYTKET.ll index 453a965a..d5e5996d 100644 --- a/tests/qir/test_pytket_qir_2-False.ll +++ b/tests/qir/test_pytket_qir_2-QIRProfile.PYTKET.ll @@ -7,31 +7,25 @@ source_filename = "test_pytket_qir_2" define void @main() #0 { entry: call void @__quantum__qis__h__body(%Qubit* null) - call void @__quantum__rt__tuple_start_record_output() - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_3-True.ll b/tests/qir/test_pytket_qir_3-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_3-True.ll rename to tests/qir/test_pytket_qir_3-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_3-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_3-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..fe1902e1 --- /dev/null +++ b/tests/qir/test_pytket_qir_3-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,31 @@ +; ModuleID = 'test_pytket_qir_3' +source_filename = "test_pytket_qir_3" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_3-False.ll b/tests/qir/test_pytket_qir_3-QIRProfile.PYTKET.ll similarity index 85% rename from tests/qir/test_pytket_qir_3-False.ll rename to tests/qir/test_pytket_qir_3-QIRProfile.PYTKET.ll index c3f41769..c86c2fd7 100644 --- a/tests/qir/test_pytket_qir_3-False.ll +++ b/tests/qir/test_pytket_qir_3-QIRProfile.PYTKET.ll @@ -12,33 +12,27 @@ entry: call void @__quantum__qis__h__body(%Qubit* null) call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 2 to %Qubit*)) - call void @__quantum__rt__tuple_start_record_output() %1 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %1, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_4-True.ll b/tests/qir/test_pytket_qir_4-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_4-True.ll rename to tests/qir/test_pytket_qir_4-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_4-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_4-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..2286f340 --- /dev/null +++ b/tests/qir/test_pytket_qir_4-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,41 @@ +; ModuleID = 'test_pytket_qir_4' +source_filename = "test_pytket_qir_4" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_4-False.ll b/tests/qir/test_pytket_qir_4-QIRProfile.PYTKET.ll similarity index 90% rename from tests/qir/test_pytket_qir_4-False.ll rename to tests/qir/test_pytket_qir_4-QIRProfile.PYTKET.ll index 6c9dc038..bee5d15f 100644 --- a/tests/qir/test_pytket_qir_4-False.ll +++ b/tests/qir/test_pytket_qir_4-QIRProfile.PYTKET.ll @@ -27,37 +27,31 @@ condb0: ; preds = %entry contb0: ; preds = %condb0, %entry call void @__quantum__qis__h__body(%Qubit* null) - call void @__quantum__rt__tuple_start_record_output() %7 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %8 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %8, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) %9 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %9, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_5-True.ll b/tests/qir/test_pytket_qir_5-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_5-True.ll rename to tests/qir/test_pytket_qir_5-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_5-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_5-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..ec4e4ded --- /dev/null +++ b/tests/qir/test_pytket_qir_5-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,43 @@ +; ModuleID = 'test_pytket_qir_5' +source_filename = "test_pytket_qir_5" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"c\00" +@3 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_5-False.ll b/tests/qir/test_pytket_qir_5-QIRProfile.PYTKET.ll similarity index 91% rename from tests/qir/test_pytket_qir_5-False.ll rename to tests/qir/test_pytket_qir_5-QIRProfile.PYTKET.ll index dc487208..86e8d9d0 100644 --- a/tests/qir/test_pytket_qir_5-False.ll +++ b/tests/qir/test_pytket_qir_5-QIRProfile.PYTKET.ll @@ -29,7 +29,6 @@ condb0: ; preds = %entry contb0: ; preds = %condb0, %entry call void @__quantum__qis__h__body(%Qubit* null) - call void @__quantum__rt__tuple_start_record_output() %8 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %8, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %9 = call i64 @get_int_from_creg(i1* %1) @@ -38,30 +37,25 @@ contb0: ; preds = %condb0, %entry call void @__quantum__rt__int_record_output(i64 %10, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) %11 = call i64 @get_int_from_creg(i1* %3) call void @__quantum__rt__int_record_output(i64 %11, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_6-True.ll b/tests/qir/test_pytket_qir_6-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_6-True.ll rename to tests/qir/test_pytket_qir_6-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_6-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_6-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..09b737aa --- /dev/null +++ b/tests/qir/test_pytket_qir_6-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,63 @@ +; ModuleID = 'test_pytket_qir_6' +source_filename = "test_pytket_qir_6" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"c\00" +@3 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__x__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 16 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 16 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + %8 = and i64 16, %7 + %9 = icmp eq i64 16, %8 + br i1 %9, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__z__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +declare void @__quantum__qis__z__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_6-False.ll b/tests/qir/test_pytket_qir_6-QIRProfile.PYTKET.ll similarity index 92% rename from tests/qir/test_pytket_qir_6-False.ll rename to tests/qir/test_pytket_qir_6-QIRProfile.PYTKET.ll index d7f80015..1563decc 100644 --- a/tests/qir/test_pytket_qir_6-False.ll +++ b/tests/qir/test_pytket_qir_6-QIRProfile.PYTKET.ll @@ -32,7 +32,6 @@ condb0: ; preds = %entry contb0: ; preds = %condb0, %entry call void @__quantum__qis__h__body(%Qubit* null) - call void @__quantum__rt__tuple_start_record_output() %8 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %8, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %9 = call i64 @get_int_from_creg(i1* %1) @@ -41,30 +40,25 @@ contb0: ; preds = %condb0, %entry call void @__quantum__rt__int_record_output(i64 %10, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) %11 = call i64 @get_int_from_creg(i1* %3) call void @__quantum__rt__int_record_output(i64 %11, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) declare void @__quantum__qis__h__body(%Qubit*) diff --git a/tests/qir/test_pytket_qir_7-True.ll b/tests/qir/test_pytket_qir_7-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_7-True.ll rename to tests/qir/test_pytket_qir_7-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_7-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_7-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..239eae75 --- /dev/null +++ b/tests/qir/test_pytket_qir_7-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,31 @@ +; ModuleID = 'test_pytket_qir_7' +source_filename = "test_pytket_qir_7" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"c\00" +@3 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 1, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_7-False.ll b/tests/qir/test_pytket_qir_7-QIRProfile.PYTKET.ll similarity index 94% rename from tests/qir/test_pytket_qir_7-False.ll rename to tests/qir/test_pytket_qir_7-QIRProfile.PYTKET.ll index 1eb07a88..93d88cd3 100644 --- a/tests/qir/test_pytket_qir_7-False.ll +++ b/tests/qir/test_pytket_qir_7-QIRProfile.PYTKET.ll @@ -71,7 +71,6 @@ entry: %44 = call i64 @get_int_from_creg(i1* %1) %45 = icmp ule i64 %43, %44 call void @set_creg_bit(i1* %2, i64 0, i1 %45) - call void @__quantum__rt__tuple_start_record_output() %46 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %46, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %47 = call i64 @get_int_from_creg(i1* %1) @@ -80,30 +79,25 @@ entry: call void @__quantum__rt__int_record_output(i64 %48, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) %49 = call i64 @get_int_from_creg(i1* %3) call void @__quantum__rt__int_record_output(i64 %49, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_8-True.ll b/tests/qir/test_pytket_qir_8-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_8-True.ll rename to tests/qir/test_pytket_qir_8-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_8-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_8-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..f40eaccb --- /dev/null +++ b/tests/qir/test_pytket_qir_8-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,25 @@ +; ModuleID = 'test_pytket_qir_8' +source_filename = "test_pytket_qir_8" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 2, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_8-False.ll b/tests/qir/test_pytket_qir_8-QIRProfile.PYTKET.ll similarity index 88% rename from tests/qir/test_pytket_qir_8-False.ll rename to tests/qir/test_pytket_qir_8-QIRProfile.PYTKET.ll index a60ee3d2..58f48270 100644 --- a/tests/qir/test_pytket_qir_8-False.ll +++ b/tests/qir/test_pytket_qir_8-QIRProfile.PYTKET.ll @@ -21,33 +21,27 @@ entry: call void @set_creg_bit(i1* %0, i64 5, i1 false) call void @set_creg_bit(i1* %0, i64 6, i1 false) call void @set_creg_bit(i1* %0, i64 7, i1 false) - call void @__quantum__rt__tuple_start_record_output() %1 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %1, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_9-True.ll b/tests/qir/test_pytket_qir_9-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_9-True.ll rename to tests/qir/test_pytket_qir_9-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_9-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_9-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..b97c1518 --- /dev/null +++ b/tests/qir/test_pytket_qir_9-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,27 @@ +; ModuleID = 'test_pytket_qir_9' +source_filename = "test_pytket_qir_9" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_9-False.ll b/tests/qir/test_pytket_qir_9-QIRProfile.PYTKET.ll similarity index 87% rename from tests/qir/test_pytket_qir_9-False.ll rename to tests/qir/test_pytket_qir_9-QIRProfile.PYTKET.ll index 4a0cf73f..c1958e64 100644 --- a/tests/qir/test_pytket_qir_9-False.ll +++ b/tests/qir/test_pytket_qir_9-QIRProfile.PYTKET.ll @@ -15,35 +15,29 @@ entry: call void @set_creg_bit(i1* %1, i64 0, i1 %2) %3 = call i1 @get_creg_bit(i1* %0, i64 1) call void @set_creg_bit(i1* %1, i64 1, i1 %3) - call void @__quantum__rt__tuple_start_record_output() %4 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %4, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %5 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %5, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_barrier-True.ll b/tests/qir/test_pytket_qir_barrier-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_barrier-True.ll rename to tests/qir/test_pytket_qir_barrier-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_barrier_2-True.ll b/tests/qir/test_pytket_qir_barrier_2-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_barrier_2-True.ll rename to tests/qir/test_pytket_qir_barrier_2-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional-True.ll b/tests/qir/test_pytket_qir_conditional-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional-True.ll rename to tests/qir/test_pytket_qir_conditional-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..ddf10985 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,75 @@ +; ModuleID = 'test_pytket_qir_conditional' +source_filename = "test_pytket_qir_conditional" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"c\00" +@3 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* null) + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + br label %contb0 + +contb0: ; preds = %condb0, %entry + %0 = phi i64 [ 0, %condb0 ], [ 0, %entry ] + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 2 to %Qubit*), %Result* inttoptr (i64 2 to %Result*)) + %1 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 2 to %Result*)) + %2 = zext i1 %1 to i64 + %3 = mul i64 %2, 4 + %4 = or i64 %3, %0 + %5 = sub i64 1, %2 + %6 = mul i64 %5, 4 + %7 = xor i64 9223372036854775807, %6 + %8 = and i64 %7, %4 + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 1 to %Qubit*), %Result* inttoptr (i64 1 to %Result*)) + %9 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 1 to %Result*)) + %10 = zext i1 %9 to i64 + %11 = mul i64 %10, 8 + %12 = or i64 %11, %8 + %13 = sub i64 1, %10 + %14 = mul i64 %13, 8 + %15 = xor i64 9223372036854775807, %14 + %16 = and i64 %15, %12 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %17 = call i1 @__quantum__qis__read_result__body(%Result* null) + %18 = zext i1 %17 to i64 + %19 = mul i64 %18, 16 + %20 = or i64 %19, %16 + %21 = sub i64 1, %18 + %22 = mul i64 %21, 16 + %23 = xor i64 9223372036854775807, %22 + %24 = and i64 %23, %20 + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %24, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional-False.ll b/tests/qir/test_pytket_qir_conditional-QIRProfile.PYTKET.ll similarity index 93% rename from tests/qir/test_pytket_qir_conditional-False.ll rename to tests/qir/test_pytket_qir_conditional-QIRProfile.PYTKET.ll index cb07e4e7..9ff53da5 100644 --- a/tests/qir/test_pytket_qir_conditional-False.ll +++ b/tests/qir/test_pytket_qir_conditional-QIRProfile.PYTKET.ll @@ -41,7 +41,6 @@ contb0: ; preds = %condb0, %entry call void @mz_to_creg_bit(%Qubit* inttoptr (i64 2 to %Qubit*), i1* %3, i64 2) call void @mz_to_creg_bit(%Qubit* inttoptr (i64 1 to %Qubit*), i1* %3, i64 3) call void @mz_to_creg_bit(%Qubit* null, i1* %3, i64 4) - call void @__quantum__rt__tuple_start_record_output() %14 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %14, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %15 = call i64 @get_int_from_creg(i1* %1) @@ -50,30 +49,25 @@ contb0: ; preds = %condb0, %entry call void @__quantum__rt__int_record_output(i64 %16, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) %17 = call i64 @get_int_from_creg(i1* %3) call void @__quantum__rt__int_record_output(i64 %17, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_conditional_10-True.ll b/tests/qir/test_pytket_qir_conditional_10-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_10-True.ll rename to tests/qir/test_pytket_qir_conditional_10-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_10-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_10-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..de7f468c --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_10-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,48 @@ +; ModuleID = 'test_pytket_qir_conditional_10' +source_filename = "test_pytket_qir_conditional_10" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__x__body(%Qubit* null) + call void @__quantum__qis__z__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__y__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 3 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + %0 = phi i64 [ 0, %condb0 ], [ 0, %entry ] + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +declare void @__quantum__qis__z__body(%Qubit*) + +declare void @__quantum__qis__y__body(%Qubit*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="4" "required_num_results"="4" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_10-False.ll b/tests/qir/test_pytket_qir_conditional_10-QIRProfile.PYTKET.ll similarity index 91% rename from tests/qir/test_pytket_qir_conditional_10-False.ll rename to tests/qir/test_pytket_qir_conditional_10-QIRProfile.PYTKET.ll index a84689e4..df3c7bd0 100644 --- a/tests/qir/test_pytket_qir_conditional_10-False.ll +++ b/tests/qir/test_pytket_qir_conditional_10-QIRProfile.PYTKET.ll @@ -27,35 +27,29 @@ condb0: ; preds = %entry br label %contb0 contb0: ; preds = %condb0, %entry - call void @__quantum__rt__tuple_start_record_output() %6 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %6, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %7 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) declare void @__quantum__qis__z__body(%Qubit*) diff --git a/tests/qir/test_pytket_qir_conditional_11-True.ll b/tests/qir/test_pytket_qir_conditional_11-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_11-True.ll rename to tests/qir/test_pytket_qir_conditional_11-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_11-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_11-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..5b87cc46 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_11-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,48 @@ +; ModuleID = 'test_pytket_qir_conditional_11' +source_filename = "test_pytket_qir_conditional_11" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__x__body(%Qubit* null) + call void @__quantum__qis__z__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__y__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 3 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + %0 = phi i64 [ 2, %condb0 ], [ 0, %entry ] + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +declare void @__quantum__qis__z__body(%Qubit*) + +declare void @__quantum__qis__y__body(%Qubit*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="4" "required_num_results"="4" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_11-False.ll b/tests/qir/test_pytket_qir_conditional_11-QIRProfile.PYTKET.ll similarity index 92% rename from tests/qir/test_pytket_qir_conditional_11-False.ll rename to tests/qir/test_pytket_qir_conditional_11-QIRProfile.PYTKET.ll index d7164633..c5bc5c81 100644 --- a/tests/qir/test_pytket_qir_conditional_11-False.ll +++ b/tests/qir/test_pytket_qir_conditional_11-QIRProfile.PYTKET.ll @@ -36,35 +36,29 @@ condb0: ; preds = %entry br label %contb0 contb0: ; preds = %condb0, %entry - call void @__quantum__rt__tuple_start_record_output() %9 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %9, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %10 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %10, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) declare void @__quantum__qis__z__body(%Qubit*) diff --git a/tests/qir/test_pytket_qir_conditional_12-True.ll b/tests/qir/test_pytket_qir_conditional_12-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_12-True.ll rename to tests/qir/test_pytket_qir_conditional_12-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_12-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_12-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..61596ffe --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_12-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,494 @@ +; ModuleID = 'test_pytket_qir_conditional_12' +source_filename = "test_pytket_qir_conditional_12" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [4 x i8] c"syn\00" +@1 = internal constant [17 x i8] c"tk_SCRATCH_BIT_0\00" +@2 = internal constant [17 x i8] c"tk_SCRATCH_BIT_1\00" + +define void @main() #0 { +entry: + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + br i1 false, label %condb1, label %contb1 + +condb1: ; preds = %contb0 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb1 + +contb1: ; preds = %condb1, %contb0 + br i1 false, label %condb2, label %contb2 + +condb2: ; preds = %contb1 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb2 + +contb2: ; preds = %condb2, %contb1 + br i1 false, label %condb3, label %contb3 + +condb3: ; preds = %contb2 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb3 + +contb3: ; preds = %condb3, %contb2 + br i1 false, label %condb4, label %contb4 + +condb4: ; preds = %contb3 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb4 + +contb4: ; preds = %condb4, %contb3 + br i1 false, label %condb5, label %contb5 + +condb5: ; preds = %contb4 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb5 + +contb5: ; preds = %condb5, %contb4 + br i1 false, label %condb6, label %contb6 + +condb6: ; preds = %contb5 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb6 + +contb6: ; preds = %condb6, %contb5 + br i1 false, label %condb7, label %contb7 + +condb7: ; preds = %contb6 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb7 + +contb7: ; preds = %condb7, %contb6 + br i1 false, label %condb8, label %contb8 + +condb8: ; preds = %contb7 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb8 + +contb8: ; preds = %condb8, %contb7 + br i1 false, label %condb9, label %contb9 + +condb9: ; preds = %contb8 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb9 + +contb9: ; preds = %condb9, %contb8 + br i1 false, label %condb10, label %contb10 + +condb10: ; preds = %contb9 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb10 + +contb10: ; preds = %condb10, %contb9 + br i1 false, label %condb11, label %contb11 + +condb11: ; preds = %contb10 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb11 + +contb11: ; preds = %condb11, %contb10 + br i1 false, label %condb12, label %contb12 + +condb12: ; preds = %contb11 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb12 + +contb12: ; preds = %condb12, %contb11 + br i1 false, label %condb13, label %contb13 + +condb13: ; preds = %contb12 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb13 + +contb13: ; preds = %condb13, %contb12 + br i1 false, label %condb14, label %contb14 + +condb14: ; preds = %contb13 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb14 + +contb14: ; preds = %condb14, %contb13 + br i1 false, label %condb15, label %contb15 + +condb15: ; preds = %contb14 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb15 + +contb15: ; preds = %condb15, %contb14 + br i1 false, label %condb16, label %contb16 + +condb16: ; preds = %contb15 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb16 + +contb16: ; preds = %condb16, %contb15 + br i1 false, label %condb17, label %contb17 + +condb17: ; preds = %contb16 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb17 + +contb17: ; preds = %condb17, %contb16 + br i1 false, label %condb18, label %contb18 + +condb18: ; preds = %contb17 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb18 + +contb18: ; preds = %condb18, %contb17 + br i1 false, label %condb19, label %contb19 + +condb19: ; preds = %contb18 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb19 + +contb19: ; preds = %condb19, %contb18 + br i1 false, label %condb20, label %contb20 + +condb20: ; preds = %contb19 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb20 + +contb20: ; preds = %condb20, %contb19 + br i1 false, label %condb21, label %contb21 + +condb21: ; preds = %contb20 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb21 + +contb21: ; preds = %condb21, %contb20 + br i1 false, label %condb22, label %contb22 + +condb22: ; preds = %contb21 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb22 + +contb22: ; preds = %condb22, %contb21 + br i1 false, label %condb23, label %contb23 + +condb23: ; preds = %contb22 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb23 + +contb23: ; preds = %condb23, %contb22 + br i1 false, label %condb24, label %contb24 + +condb24: ; preds = %contb23 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb24 + +contb24: ; preds = %condb24, %contb23 + br i1 false, label %condb25, label %contb25 + +condb25: ; preds = %contb24 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb25 + +contb25: ; preds = %condb25, %contb24 + br i1 false, label %condb26, label %contb26 + +condb26: ; preds = %contb25 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb26 + +contb26: ; preds = %condb26, %contb25 + br i1 false, label %condb27, label %contb27 + +condb27: ; preds = %contb26 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb27 + +contb27: ; preds = %condb27, %contb26 + br i1 false, label %condb28, label %contb28 + +condb28: ; preds = %contb27 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb28 + +contb28: ; preds = %condb28, %contb27 + br i1 false, label %condb29, label %contb29 + +condb29: ; preds = %contb28 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb29 + +contb29: ; preds = %condb29, %contb28 + br i1 false, label %condb30, label %contb30 + +condb30: ; preds = %contb29 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb30 + +contb30: ; preds = %condb30, %contb29 + br i1 false, label %condb31, label %contb31 + +condb31: ; preds = %contb30 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb31 + +contb31: ; preds = %condb31, %contb30 + br i1 false, label %condb32, label %contb32 + +condb32: ; preds = %contb31 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb32 + +contb32: ; preds = %condb32, %contb31 + br i1 false, label %condb33, label %contb33 + +condb33: ; preds = %contb32 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb33 + +contb33: ; preds = %condb33, %contb32 + br i1 false, label %condb34, label %contb34 + +condb34: ; preds = %contb33 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb34 + +contb34: ; preds = %condb34, %contb33 + br i1 false, label %condb35, label %contb35 + +condb35: ; preds = %contb34 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb35 + +contb35: ; preds = %condb35, %contb34 + br i1 false, label %condb36, label %contb36 + +condb36: ; preds = %contb35 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb36 + +contb36: ; preds = %condb36, %contb35 + br i1 false, label %condb37, label %contb37 + +condb37: ; preds = %contb36 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb37 + +contb37: ; preds = %condb37, %contb36 + br i1 false, label %condb38, label %contb38 + +condb38: ; preds = %contb37 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb38 + +contb38: ; preds = %condb38, %contb37 + br i1 false, label %condb39, label %contb39 + +condb39: ; preds = %contb38 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb39 + +contb39: ; preds = %condb39, %contb38 + br i1 false, label %condb40, label %contb40 + +condb40: ; preds = %contb39 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb40 + +contb40: ; preds = %condb40, %contb39 + br i1 false, label %condb41, label %contb41 + +condb41: ; preds = %contb40 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb41 + +contb41: ; preds = %condb41, %contb40 + br i1 false, label %condb42, label %contb42 + +condb42: ; preds = %contb41 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb42 + +contb42: ; preds = %condb42, %contb41 + br i1 false, label %condb43, label %contb43 + +condb43: ; preds = %contb42 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb43 + +contb43: ; preds = %condb43, %contb42 + br i1 false, label %condb44, label %contb44 + +condb44: ; preds = %contb43 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb44 + +contb44: ; preds = %condb44, %contb43 + br i1 false, label %condb45, label %contb45 + +condb45: ; preds = %contb44 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb45 + +contb45: ; preds = %condb45, %contb44 + br i1 false, label %condb46, label %contb46 + +condb46: ; preds = %contb45 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb46 + +contb46: ; preds = %condb46, %contb45 + br i1 false, label %condb47, label %contb47 + +condb47: ; preds = %contb46 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb47 + +contb47: ; preds = %condb47, %contb46 + br i1 false, label %condb48, label %contb48 + +condb48: ; preds = %contb47 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb48 + +contb48: ; preds = %condb48, %contb47 + br i1 false, label %condb49, label %contb49 + +condb49: ; preds = %contb48 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb49 + +contb49: ; preds = %condb49, %contb48 + br i1 false, label %condb50, label %contb50 + +condb50: ; preds = %contb49 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb50 + +contb50: ; preds = %condb50, %contb49 + br i1 false, label %condb51, label %contb51 + +condb51: ; preds = %contb50 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb51 + +contb51: ; preds = %condb51, %contb50 + br i1 false, label %condb52, label %contb52 + +condb52: ; preds = %contb51 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb52 + +contb52: ; preds = %condb52, %contb51 + br i1 false, label %condb53, label %contb53 + +condb53: ; preds = %contb52 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb53 + +contb53: ; preds = %condb53, %contb52 + br i1 false, label %condb54, label %contb54 + +condb54: ; preds = %contb53 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb54 + +contb54: ; preds = %condb54, %contb53 + br i1 false, label %condb55, label %contb55 + +condb55: ; preds = %contb54 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb55 + +contb55: ; preds = %condb55, %contb54 + br i1 false, label %condb56, label %contb56 + +condb56: ; preds = %contb55 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb56 + +contb56: ; preds = %condb56, %contb55 + br i1 false, label %condb57, label %contb57 + +condb57: ; preds = %contb56 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb57 + +contb57: ; preds = %condb57, %contb56 + br i1 false, label %condb58, label %contb58 + +condb58: ; preds = %contb57 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb58 + +contb58: ; preds = %condb58, %contb57 + br i1 false, label %condb59, label %contb59 + +condb59: ; preds = %contb58 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb59 + +contb59: ; preds = %condb59, %contb58 + br i1 false, label %condb60, label %contb60 + +condb60: ; preds = %contb59 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb60 + +contb60: ; preds = %condb60, %contb59 + br i1 false, label %condb61, label %contb61 + +condb61: ; preds = %contb60 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb61 + +contb61: ; preds = %condb61, %contb60 + br i1 false, label %condb62, label %contb62 + +condb62: ; preds = %contb61 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb62 + +contb62: ; preds = %condb62, %contb61 + br i1 false, label %condb63, label %contb63 + +condb63: ; preds = %contb62 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb63 + +contb63: ; preds = %condb63, %contb62 + br i1 false, label %condb64, label %contb64 + +condb64: ; preds = %contb63 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb64 + +contb64: ; preds = %condb64, %contb63 + br i1 false, label %condb65, label %contb65 + +condb65: ; preds = %contb64 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb65 + +contb65: ; preds = %condb65, %contb64 + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([17 x i8], [17 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([17 x i8], [17 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="7" "required_num_results"="7" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_12-False.ll b/tests/qir/test_pytket_qir_conditional_12-QIRProfile.PYTKET.ll similarity index 99% rename from tests/qir/test_pytket_qir_conditional_12-False.ll rename to tests/qir/test_pytket_qir_conditional_12-QIRProfile.PYTKET.ll index 4aad3a39..2169695a 100644 --- a/tests/qir/test_pytket_qir_conditional_12-False.ll +++ b/tests/qir/test_pytket_qir_conditional_12-QIRProfile.PYTKET.ll @@ -739,37 +739,31 @@ condb65: ; preds = %contb64 br label %contb65 contb65: ; preds = %condb65, %contb64 - call void @__quantum__rt__tuple_start_record_output() %201 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %201, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @0, i32 0, i32 0)) %202 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %202, i8* getelementptr inbounds ([17 x i8], [17 x i8]* @1, i32 0, i32 0)) %203 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %203, i8* getelementptr inbounds ([17 x i8], [17 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="7" "required_num_results"="7" } diff --git a/tests/qir/test_pytket_qir_conditional_13-True.ll b/tests/qir/test_pytket_qir_conditional_13-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_13-True.ll rename to tests/qir/test_pytket_qir_conditional_13-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_13-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_13-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..60361ca8 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_13-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,42 @@ +; ModuleID = 'test_pytket_qir_conditional_13' +source_filename = "test_pytket_qir_conditional_13" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [15 x i8] c"tk_SCRATCH_BIT\00" + +define void @main() #0 { +entry: + br i1 true, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + br i1 false, label %condb1, label %contb1 + +condb1: ; preds = %contb0 + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb1 + +contb1: ; preds = %condb1, %contb0 + call void @__quantum__rt__int_record_output(i64 1, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="7" "required_num_results"="7" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_13-False.ll b/tests/qir/test_pytket_qir_conditional_13-QIRProfile.PYTKET.ll similarity index 89% rename from tests/qir/test_pytket_qir_conditional_13-False.ll rename to tests/qir/test_pytket_qir_conditional_13-QIRProfile.PYTKET.ll index 426a8272..6cd25bac 100644 --- a/tests/qir/test_pytket_qir_conditional_13-False.ll +++ b/tests/qir/test_pytket_qir_conditional_13-QIRProfile.PYTKET.ll @@ -27,33 +27,27 @@ condb1: ; preds = %contb0 br label %contb1 contb1: ; preds = %condb1, %contb0 - call void @__quantum__rt__tuple_start_record_output() %3 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="7" "required_num_results"="7" } diff --git a/tests/qir/test_pytket_qir_conditional_14-block-True.ll b/tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_14-block-True.ll rename to tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..630f7e0d --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,38 @@ +; ModuleID = 'test_pytket_qir_conditional_14-block' +source_filename = "test_pytket_qir_conditional_14-block" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + %0 = phi i64 [ 2, %condb0 ], [ 0, %entry ] + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="4" "required_num_results"="4" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_14-block-False.ll b/tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.PYTKET.ll similarity index 91% rename from tests/qir/test_pytket_qir_conditional_14-block-False.ll rename to tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.PYTKET.ll index 15ead2ad..620c65c1 100644 --- a/tests/qir/test_pytket_qir_conditional_14-block-False.ll +++ b/tests/qir/test_pytket_qir_conditional_14-block-QIRProfile.PYTKET.ll @@ -32,35 +32,29 @@ condb0: ; preds = %entry br label %contb0 contb0: ; preds = %condb0, %entry - call void @__quantum__rt__tuple_start_record_output() %9 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %9, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %10 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %10, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="4" "required_num_results"="4" } diff --git a/tests/qir/test_pytket_qir_conditional_15-block-True.ll b/tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_15-block-True.ll rename to tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..035a7805 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,45 @@ +; ModuleID = 'test_pytket_qir_conditional_15-block' +source_filename = "test_pytket_qir_conditional_15-block" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + %8 = add i64 %7, 3 + %9 = trunc i64 %8 to i20 + %10 = zext i20 %9 to i64 + call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %10, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_15-block-False.ll b/tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.PYTKET.ll similarity index 91% rename from tests/qir/test_pytket_qir_conditional_15-block-False.ll rename to tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.PYTKET.ll index a656fe7d..896c7e1e 100644 --- a/tests/qir/test_pytket_qir_conditional_15-block-False.ll +++ b/tests/qir/test_pytket_qir_conditional_15-block-QIRProfile.PYTKET.ll @@ -29,37 +29,31 @@ entry: %4 = call i64 @get_int_from_creg(i1* %1) %5 = add i64 %3, %4 call void @set_creg_to_int(i1* %2, i64 %5) - call void @__quantum__rt__tuple_start_record_output() %6 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %6, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %7 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) %8 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %8, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_conditional_16-block-True.ll b/tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_16-block-True.ll rename to tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..61aefb0f --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,94 @@ +; ModuleID = 'test_pytket_qir_conditional_16-block' +source_filename = "test_pytket_qir_conditional_16-block" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + %8 = and i64 1, %7 + %9 = icmp eq i64 1, %8 + br i1 %9, label %condb0, label %contb0 + +condb0: ; preds = %entry + br label %contb0 + +contb0: ; preds = %condb0, %entry + %10 = phi i64 [ 3, %condb0 ], [ 0, %entry ] + %11 = and i64 1, %7 + %12 = icmp eq i64 1, %11 + br i1 %12, label %condb1, label %contb1 + +condb1: ; preds = %contb0 + %13 = or i64 1, %10 + %14 = and i64 9223372036854775807, %13 + %15 = or i64 2, %14 + %16 = and i64 9223372036854775807, %15 + %17 = or i64 0, %16 + %18 = and i64 9223372036854775803, %17 + %19 = or i64 0, %18 + %20 = and i64 9223372036854775799, %19 + %21 = or i64 0, %20 + %22 = and i64 9223372036854775791, %21 + %23 = or i64 0, %22 + %24 = and i64 9223372036854775775, %23 + %25 = or i64 0, %24 + %26 = and i64 9223372036854775743, %25 + %27 = or i64 0, %26 + %28 = and i64 9223372036854775679, %27 + %29 = or i64 0, %28 + %30 = and i64 9223372036854775551, %29 + %31 = or i64 0, %30 + %32 = and i64 9223372036854775295, %31 + %33 = or i64 0, %32 + %34 = and i64 9223372036854774783, %33 + br label %contb1 + +contb1: ; preds = %condb1, %contb0 + %35 = phi i64 [ %34, %condb1 ], [ %10, %contb0 ] + %36 = and i64 1, %7 + %37 = icmp eq i64 1, %36 + br i1 %37, label %condb2, label %contb2 + +condb2: ; preds = %contb1 + %38 = add i64 %7, %35 + %39 = trunc i64 %38 to i20 + %40 = zext i20 %39 to i64 + br label %contb2 + +contb2: ; preds = %condb2, %contb1 + %41 = phi i64 [ %40, %condb2 ], [ 0, %contb1 ] + call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %35, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %41, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_16-block-False.ll b/tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.PYTKET.ll similarity index 94% rename from tests/qir/test_pytket_qir_conditional_16-block-False.ll rename to tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.PYTKET.ll index 32e2e2c7..66266b51 100644 --- a/tests/qir/test_pytket_qir_conditional_16-block-False.ll +++ b/tests/qir/test_pytket_qir_conditional_16-block-QIRProfile.PYTKET.ll @@ -61,37 +61,31 @@ condb2: ; preds = %contb1 br label %contb2 contb2: ; preds = %condb2, %contb1 - call void @__quantum__rt__tuple_start_record_output() %9 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %9, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %10 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %10, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) %11 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %11, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_conditional_17-block-True.ll b/tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_17-block-True.ll rename to tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..a39f3476 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,652 @@ +; ModuleID = 'test_pytket_qir_conditional_17-block' +source_filename = "test_pytket_qir_conditional_17-block" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + %8 = and i64 1, %7 + %9 = icmp eq i64 1, %8 + br i1 %9, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %10 = call i1 @__quantum__qis__read_result__body(%Result* null) + %11 = zext i1 %10 to i64 + %12 = mul i64 %11, 1 + %13 = or i64 %12, 0 + %14 = sub i64 1, %11 + %15 = mul i64 %14, 1 + %16 = xor i64 9223372036854775807, %15 + %17 = and i64 %16, %13 + br label %contb0 + +contb0: ; preds = %condb0, %entry + %18 = phi i64 [ %17, %condb0 ], [ 0, %entry ] + %19 = and i64 1, %7 + %20 = icmp eq i64 1, %19 + br i1 %20, label %condb1, label %contb1 + +condb1: ; preds = %contb0 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %21 = call i1 @__quantum__qis__read_result__body(%Result* null) + %22 = zext i1 %21 to i64 + %23 = mul i64 %22, 2 + %24 = or i64 %23, %18 + %25 = sub i64 1, %22 + %26 = mul i64 %25, 2 + %27 = xor i64 9223372036854775807, %26 + %28 = and i64 %27, %24 + br label %contb1 + +contb1: ; preds = %condb1, %contb0 + %29 = phi i64 [ %28, %condb1 ], [ %18, %contb0 ] + %30 = and i64 1, %7 + %31 = icmp eq i64 1, %30 + br i1 %31, label %condb2, label %contb2 + +condb2: ; preds = %contb1 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %32 = call i1 @__quantum__qis__read_result__body(%Result* null) + %33 = zext i1 %32 to i64 + %34 = mul i64 %33, 4 + %35 = or i64 %34, %29 + %36 = sub i64 1, %33 + %37 = mul i64 %36, 4 + %38 = xor i64 9223372036854775807, %37 + %39 = and i64 %38, %35 + br label %contb2 + +contb2: ; preds = %condb2, %contb1 + %40 = phi i64 [ %39, %condb2 ], [ %29, %contb1 ] + %41 = and i64 1, %7 + %42 = icmp eq i64 1, %41 + br i1 %42, label %condb3, label %contb3 + +condb3: ; preds = %contb2 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %43 = call i1 @__quantum__qis__read_result__body(%Result* null) + %44 = zext i1 %43 to i64 + %45 = mul i64 %44, 8 + %46 = or i64 %45, %40 + %47 = sub i64 1, %44 + %48 = mul i64 %47, 8 + %49 = xor i64 9223372036854775807, %48 + %50 = and i64 %49, %46 + br label %contb3 + +contb3: ; preds = %condb3, %contb2 + %51 = phi i64 [ %50, %condb3 ], [ %40, %contb2 ] + %52 = and i64 1, %7 + %53 = icmp eq i64 1, %52 + br i1 %53, label %condb4, label %contb4 + +condb4: ; preds = %contb3 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %54 = call i1 @__quantum__qis__read_result__body(%Result* null) + %55 = zext i1 %54 to i64 + %56 = mul i64 %55, 16 + %57 = or i64 %56, %51 + %58 = sub i64 1, %55 + %59 = mul i64 %58, 16 + %60 = xor i64 9223372036854775807, %59 + %61 = and i64 %60, %57 + br label %contb4 + +contb4: ; preds = %condb4, %contb3 + %62 = phi i64 [ %61, %condb4 ], [ %51, %contb3 ] + %63 = and i64 1, %7 + %64 = icmp eq i64 1, %63 + br i1 %64, label %condb5, label %contb5 + +condb5: ; preds = %contb4 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %65 = call i1 @__quantum__qis__read_result__body(%Result* null) + %66 = zext i1 %65 to i64 + %67 = mul i64 %66, 32 + %68 = or i64 %67, %62 + %69 = sub i64 1, %66 + %70 = mul i64 %69, 32 + %71 = xor i64 9223372036854775807, %70 + %72 = and i64 %71, %68 + br label %contb5 + +contb5: ; preds = %condb5, %contb4 + %73 = phi i64 [ %72, %condb5 ], [ %62, %contb4 ] + %74 = and i64 1, %7 + %75 = icmp eq i64 1, %74 + br i1 %75, label %condb6, label %contb6 + +condb6: ; preds = %contb5 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %76 = call i1 @__quantum__qis__read_result__body(%Result* null) + %77 = zext i1 %76 to i64 + %78 = mul i64 %77, 64 + %79 = or i64 %78, %73 + %80 = sub i64 1, %77 + %81 = mul i64 %80, 64 + %82 = xor i64 9223372036854775807, %81 + %83 = and i64 %82, %79 + br label %contb6 + +contb6: ; preds = %condb6, %contb5 + %84 = phi i64 [ %83, %condb6 ], [ %73, %contb5 ] + %85 = and i64 1, %7 + %86 = icmp eq i64 1, %85 + br i1 %86, label %condb7, label %contb7 + +condb7: ; preds = %contb6 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %87 = call i1 @__quantum__qis__read_result__body(%Result* null) + %88 = zext i1 %87 to i64 + %89 = mul i64 %88, 128 + %90 = or i64 %89, %84 + %91 = sub i64 1, %88 + %92 = mul i64 %91, 128 + %93 = xor i64 9223372036854775807, %92 + %94 = and i64 %93, %90 + br label %contb7 + +contb7: ; preds = %condb7, %contb6 + %95 = phi i64 [ %94, %condb7 ], [ %84, %contb6 ] + %96 = and i64 1, %7 + %97 = icmp eq i64 1, %96 + br i1 %97, label %condb8, label %contb8 + +condb8: ; preds = %contb7 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %98 = call i1 @__quantum__qis__read_result__body(%Result* null) + %99 = zext i1 %98 to i64 + %100 = mul i64 %99, 256 + %101 = or i64 %100, %95 + %102 = sub i64 1, %99 + %103 = mul i64 %102, 256 + %104 = xor i64 9223372036854775807, %103 + %105 = and i64 %104, %101 + br label %contb8 + +contb8: ; preds = %condb8, %contb7 + %106 = phi i64 [ %105, %condb8 ], [ %95, %contb7 ] + %107 = and i64 1, %7 + %108 = icmp eq i64 1, %107 + br i1 %108, label %condb9, label %contb9 + +condb9: ; preds = %contb8 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %109 = call i1 @__quantum__qis__read_result__body(%Result* null) + %110 = zext i1 %109 to i64 + %111 = mul i64 %110, 512 + %112 = or i64 %111, %106 + %113 = sub i64 1, %110 + %114 = mul i64 %113, 512 + %115 = xor i64 9223372036854775807, %114 + %116 = and i64 %115, %112 + br label %contb9 + +contb9: ; preds = %condb9, %contb8 + %117 = phi i64 [ %116, %condb9 ], [ %106, %contb8 ] + %118 = and i64 1, %7 + %119 = icmp eq i64 1, %118 + br i1 %119, label %condb10, label %contb10 + +condb10: ; preds = %contb9 + %120 = or i64 1, %117 + %121 = and i64 9223372036854775807, %120 + %122 = or i64 2, %121 + %123 = and i64 9223372036854775807, %122 + %124 = or i64 0, %123 + %125 = and i64 9223372036854775803, %124 + %126 = or i64 0, %125 + %127 = and i64 9223372036854775799, %126 + %128 = or i64 0, %127 + %129 = and i64 9223372036854775791, %128 + %130 = or i64 0, %129 + %131 = and i64 9223372036854775775, %130 + %132 = or i64 0, %131 + %133 = and i64 9223372036854775743, %132 + %134 = or i64 0, %133 + %135 = and i64 9223372036854775679, %134 + %136 = or i64 0, %135 + %137 = and i64 9223372036854775551, %136 + %138 = or i64 0, %137 + %139 = and i64 9223372036854775295, %138 + br label %contb10 + +contb10: ; preds = %condb10, %contb9 + %140 = phi i64 [ %139, %condb10 ], [ %117, %contb9 ] + %141 = and i64 1, %7 + %142 = icmp eq i64 1, %141 + br i1 %142, label %condb11, label %contb11 + +condb11: ; preds = %contb10 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %143 = call i1 @__quantum__qis__read_result__body(%Result* null) + %144 = zext i1 %143 to i64 + %145 = mul i64 %144, 1 + %146 = or i64 %145, 0 + %147 = sub i64 1, %144 + %148 = mul i64 %147, 1 + %149 = xor i64 9223372036854775807, %148 + %150 = and i64 %149, %146 + br label %contb11 + +contb11: ; preds = %condb11, %contb10 + %151 = phi i64 [ %150, %condb11 ], [ 0, %contb10 ] + %152 = and i64 1, %7 + %153 = icmp eq i64 1, %152 + br i1 %153, label %condb12, label %contb12 + +condb12: ; preds = %contb11 + %154 = or i64 1, %140 + %155 = and i64 9223372036854775807, %154 + %156 = or i64 2, %155 + %157 = and i64 9223372036854775807, %156 + %158 = or i64 0, %157 + %159 = and i64 9223372036854775803, %158 + %160 = or i64 0, %159 + %161 = and i64 9223372036854775799, %160 + %162 = or i64 0, %161 + %163 = and i64 9223372036854775791, %162 + %164 = or i64 0, %163 + %165 = and i64 9223372036854775775, %164 + %166 = or i64 0, %165 + %167 = and i64 9223372036854775743, %166 + %168 = or i64 0, %167 + %169 = and i64 9223372036854775679, %168 + %170 = or i64 0, %169 + %171 = and i64 9223372036854775551, %170 + %172 = or i64 0, %171 + %173 = and i64 9223372036854775295, %172 + br label %contb12 + +contb12: ; preds = %condb12, %contb11 + %174 = phi i64 [ %173, %condb12 ], [ %140, %contb11 ] + %175 = and i64 1, %7 + %176 = icmp eq i64 1, %175 + br i1 %176, label %condb13, label %contb13 + +condb13: ; preds = %contb12 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %177 = call i1 @__quantum__qis__read_result__body(%Result* null) + %178 = zext i1 %177 to i64 + %179 = mul i64 %178, 2 + %180 = or i64 %179, %151 + %181 = sub i64 1, %178 + %182 = mul i64 %181, 2 + %183 = xor i64 9223372036854775807, %182 + %184 = and i64 %183, %180 + br label %contb13 + +contb13: ; preds = %condb13, %contb12 + %185 = phi i64 [ %184, %condb13 ], [ %151, %contb12 ] + %186 = and i64 1, %7 + %187 = icmp eq i64 1, %186 + br i1 %187, label %condb14, label %contb14 + +condb14: ; preds = %contb13 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %188 = call i1 @__quantum__qis__read_result__body(%Result* null) + %189 = zext i1 %188 to i64 + %190 = mul i64 %189, 4 + %191 = or i64 %190, %185 + %192 = sub i64 1, %189 + %193 = mul i64 %192, 4 + %194 = xor i64 9223372036854775807, %193 + %195 = and i64 %194, %191 + br label %contb14 + +contb14: ; preds = %condb14, %contb13 + %196 = phi i64 [ %195, %condb14 ], [ %185, %contb13 ] + %197 = and i64 1, %7 + %198 = icmp eq i64 1, %197 + br i1 %198, label %condb15, label %contb15 + +condb15: ; preds = %contb14 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %199 = call i1 @__quantum__qis__read_result__body(%Result* null) + %200 = zext i1 %199 to i64 + %201 = mul i64 %200, 8 + %202 = or i64 %201, %196 + %203 = sub i64 1, %200 + %204 = mul i64 %203, 8 + %205 = xor i64 9223372036854775807, %204 + %206 = and i64 %205, %202 + br label %contb15 + +contb15: ; preds = %condb15, %contb14 + %207 = phi i64 [ %206, %condb15 ], [ %196, %contb14 ] + %208 = and i64 1, %7 + %209 = icmp eq i64 1, %208 + br i1 %209, label %condb16, label %contb16 + +condb16: ; preds = %contb15 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %210 = call i1 @__quantum__qis__read_result__body(%Result* null) + %211 = zext i1 %210 to i64 + %212 = mul i64 %211, 16 + %213 = or i64 %212, %207 + %214 = sub i64 1, %211 + %215 = mul i64 %214, 16 + %216 = xor i64 9223372036854775807, %215 + %217 = and i64 %216, %213 + br label %contb16 + +contb16: ; preds = %condb16, %contb15 + %218 = phi i64 [ %217, %condb16 ], [ %207, %contb15 ] + %219 = and i64 1, %7 + %220 = icmp eq i64 1, %219 + br i1 %220, label %condb17, label %contb17 + +condb17: ; preds = %contb16 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %221 = call i1 @__quantum__qis__read_result__body(%Result* null) + %222 = zext i1 %221 to i64 + %223 = mul i64 %222, 32 + %224 = or i64 %223, %218 + %225 = sub i64 1, %222 + %226 = mul i64 %225, 32 + %227 = xor i64 9223372036854775807, %226 + %228 = and i64 %227, %224 + br label %contb17 + +contb17: ; preds = %condb17, %contb16 + %229 = phi i64 [ %228, %condb17 ], [ %218, %contb16 ] + %230 = and i64 1, %7 + %231 = icmp eq i64 1, %230 + br i1 %231, label %condb18, label %contb18 + +condb18: ; preds = %contb17 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %232 = call i1 @__quantum__qis__read_result__body(%Result* null) + %233 = zext i1 %232 to i64 + %234 = mul i64 %233, 64 + %235 = or i64 %234, %229 + %236 = sub i64 1, %233 + %237 = mul i64 %236, 64 + %238 = xor i64 9223372036854775807, %237 + %239 = and i64 %238, %235 + br label %contb18 + +contb18: ; preds = %condb18, %contb17 + %240 = phi i64 [ %239, %condb18 ], [ %229, %contb17 ] + %241 = and i64 1, %7 + %242 = icmp eq i64 1, %241 + br i1 %242, label %condb19, label %contb19 + +condb19: ; preds = %contb18 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %243 = call i1 @__quantum__qis__read_result__body(%Result* null) + %244 = zext i1 %243 to i64 + %245 = mul i64 %244, 128 + %246 = or i64 %245, %240 + %247 = sub i64 1, %244 + %248 = mul i64 %247, 128 + %249 = xor i64 9223372036854775807, %248 + %250 = and i64 %249, %246 + br label %contb19 + +contb19: ; preds = %condb19, %contb18 + %251 = phi i64 [ %250, %condb19 ], [ %240, %contb18 ] + %252 = and i64 1, %7 + %253 = icmp eq i64 1, %252 + br i1 %253, label %condb20, label %contb20 + +condb20: ; preds = %contb19 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %254 = call i1 @__quantum__qis__read_result__body(%Result* null) + %255 = zext i1 %254 to i64 + %256 = mul i64 %255, 256 + %257 = or i64 %256, %251 + %258 = sub i64 1, %255 + %259 = mul i64 %258, 256 + %260 = xor i64 9223372036854775807, %259 + %261 = and i64 %260, %257 + br label %contb20 + +contb20: ; preds = %condb20, %contb19 + %262 = phi i64 [ %261, %condb20 ], [ %251, %contb19 ] + %263 = and i64 1, %7 + %264 = icmp eq i64 1, %263 + br i1 %264, label %condb21, label %contb21 + +condb21: ; preds = %contb20 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %265 = call i1 @__quantum__qis__read_result__body(%Result* null) + %266 = zext i1 %265 to i64 + %267 = mul i64 %266, 512 + %268 = or i64 %267, %262 + %269 = sub i64 1, %266 + %270 = mul i64 %269, 512 + %271 = xor i64 9223372036854775807, %270 + %272 = and i64 %271, %268 + br label %contb21 + +contb21: ; preds = %condb21, %contb20 + %273 = phi i64 [ %272, %condb21 ], [ %262, %contb20 ] + %274 = and i64 1, %7 + %275 = icmp eq i64 1, %274 + br i1 %275, label %condb22, label %contb22 + +condb22: ; preds = %contb21 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %276 = call i1 @__quantum__qis__read_result__body(%Result* null) + %277 = zext i1 %276 to i64 + %278 = mul i64 %277, 1024 + %279 = or i64 %278, %273 + %280 = sub i64 1, %277 + %281 = mul i64 %280, 1024 + %282 = xor i64 9223372036854775807, %281 + %283 = and i64 %282, %279 + br label %contb22 + +contb22: ; preds = %condb22, %contb21 + %284 = phi i64 [ %283, %condb22 ], [ %273, %contb21 ] + %285 = and i64 1, %7 + %286 = icmp eq i64 1, %285 + br i1 %286, label %condb23, label %contb23 + +condb23: ; preds = %contb22 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %287 = call i1 @__quantum__qis__read_result__body(%Result* null) + %288 = zext i1 %287 to i64 + %289 = mul i64 %288, 2048 + %290 = or i64 %289, %284 + %291 = sub i64 1, %288 + %292 = mul i64 %291, 2048 + %293 = xor i64 9223372036854775807, %292 + %294 = and i64 %293, %290 + br label %contb23 + +contb23: ; preds = %condb23, %contb22 + %295 = phi i64 [ %294, %condb23 ], [ %284, %contb22 ] + %296 = and i64 1, %7 + %297 = icmp eq i64 1, %296 + br i1 %297, label %condb24, label %contb24 + +condb24: ; preds = %contb23 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %298 = call i1 @__quantum__qis__read_result__body(%Result* null) + %299 = zext i1 %298 to i64 + %300 = mul i64 %299, 4096 + %301 = or i64 %300, %295 + %302 = sub i64 1, %299 + %303 = mul i64 %302, 4096 + %304 = xor i64 9223372036854775807, %303 + %305 = and i64 %304, %301 + br label %contb24 + +contb24: ; preds = %condb24, %contb23 + %306 = phi i64 [ %305, %condb24 ], [ %295, %contb23 ] + %307 = and i64 1, %7 + %308 = icmp eq i64 1, %307 + br i1 %308, label %condb25, label %contb25 + +condb25: ; preds = %contb24 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %309 = call i1 @__quantum__qis__read_result__body(%Result* null) + %310 = zext i1 %309 to i64 + %311 = mul i64 %310, 8192 + %312 = or i64 %311, %306 + %313 = sub i64 1, %310 + %314 = mul i64 %313, 8192 + %315 = xor i64 9223372036854775807, %314 + %316 = and i64 %315, %312 + br label %contb25 + +contb25: ; preds = %condb25, %contb24 + %317 = phi i64 [ %316, %condb25 ], [ %306, %contb24 ] + %318 = and i64 1, %7 + %319 = icmp eq i64 1, %318 + br i1 %319, label %condb26, label %contb26 + +condb26: ; preds = %contb25 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %320 = call i1 @__quantum__qis__read_result__body(%Result* null) + %321 = zext i1 %320 to i64 + %322 = mul i64 %321, 16384 + %323 = or i64 %322, %317 + %324 = sub i64 1, %321 + %325 = mul i64 %324, 16384 + %326 = xor i64 9223372036854775807, %325 + %327 = and i64 %326, %323 + br label %contb26 + +contb26: ; preds = %condb26, %contb25 + %328 = phi i64 [ %327, %condb26 ], [ %317, %contb25 ] + %329 = and i64 1, %7 + %330 = icmp eq i64 1, %329 + br i1 %330, label %condb27, label %contb27 + +condb27: ; preds = %contb26 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %331 = call i1 @__quantum__qis__read_result__body(%Result* null) + %332 = zext i1 %331 to i64 + %333 = mul i64 %332, 32768 + %334 = or i64 %333, %328 + %335 = sub i64 1, %332 + %336 = mul i64 %335, 32768 + %337 = xor i64 9223372036854775807, %336 + %338 = and i64 %337, %334 + br label %contb27 + +contb27: ; preds = %condb27, %contb26 + %339 = phi i64 [ %338, %condb27 ], [ %328, %contb26 ] + %340 = and i64 1, %7 + %341 = icmp eq i64 1, %340 + br i1 %341, label %condb28, label %contb28 + +condb28: ; preds = %contb27 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %342 = call i1 @__quantum__qis__read_result__body(%Result* null) + %343 = zext i1 %342 to i64 + %344 = mul i64 %343, 65536 + %345 = or i64 %344, %339 + %346 = sub i64 1, %343 + %347 = mul i64 %346, 65536 + %348 = xor i64 9223372036854775807, %347 + %349 = and i64 %348, %345 + br label %contb28 + +contb28: ; preds = %condb28, %contb27 + %350 = phi i64 [ %349, %condb28 ], [ %339, %contb27 ] + %351 = and i64 1, %7 + %352 = icmp eq i64 1, %351 + br i1 %352, label %condb29, label %contb29 + +condb29: ; preds = %contb28 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %353 = call i1 @__quantum__qis__read_result__body(%Result* null) + %354 = zext i1 %353 to i64 + %355 = mul i64 %354, 131072 + %356 = or i64 %355, %350 + %357 = sub i64 1, %354 + %358 = mul i64 %357, 131072 + %359 = xor i64 9223372036854775807, %358 + %360 = and i64 %359, %356 + br label %contb29 + +contb29: ; preds = %condb29, %contb28 + %361 = phi i64 [ %360, %condb29 ], [ %350, %contb28 ] + %362 = and i64 1, %7 + %363 = icmp eq i64 1, %362 + br i1 %363, label %condb30, label %contb30 + +condb30: ; preds = %contb29 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %364 = call i1 @__quantum__qis__read_result__body(%Result* null) + %365 = zext i1 %364 to i64 + %366 = mul i64 %365, 262144 + %367 = or i64 %366, %361 + %368 = sub i64 1, %365 + %369 = mul i64 %368, 262144 + %370 = xor i64 9223372036854775807, %369 + %371 = and i64 %370, %367 + br label %contb30 + +contb30: ; preds = %condb30, %contb29 + %372 = phi i64 [ %371, %condb30 ], [ %361, %contb29 ] + %373 = and i64 1, %7 + %374 = icmp eq i64 1, %373 + br i1 %374, label %condb31, label %contb31 + +condb31: ; preds = %contb30 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %375 = call i1 @__quantum__qis__read_result__body(%Result* null) + %376 = zext i1 %375 to i64 + %377 = mul i64 %376, 524288 + %378 = or i64 %377, %372 + %379 = sub i64 1, %376 + %380 = mul i64 %379, 524288 + %381 = xor i64 9223372036854775807, %380 + %382 = and i64 %381, %378 + br label %contb31 + +contb31: ; preds = %condb31, %contb30 + %383 = phi i64 [ %382, %condb31 ], [ %372, %contb30 ] + %384 = and i64 1, %7 + %385 = icmp eq i64 1, %384 + br i1 %385, label %condb32, label %contb32 + +condb32: ; preds = %contb31 + %386 = add i64 %7, %174 + %387 = trunc i64 %386 to i20 + %388 = zext i20 %387 to i64 + br label %contb32 + +contb32: ; preds = %condb32, %contb31 + %389 = phi i64 [ %388, %condb32 ], [ %383, %contb31 ] + call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %174, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %389, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_17-block-False.ll b/tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.PYTKET.ll similarity index 98% rename from tests/qir/test_pytket_qir_conditional_17-block-False.ll rename to tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.PYTKET.ll index 131a4fe6..393fab36 100644 --- a/tests/qir/test_pytket_qir_conditional_17-block-False.ll +++ b/tests/qir/test_pytket_qir_conditional_17-block-QIRProfile.PYTKET.ll @@ -299,37 +299,31 @@ condb32: ; preds = %contb31 br label %contb32 contb32: ; preds = %condb32, %contb31 - call void @__quantum__rt__tuple_start_record_output() %39 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %39, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %40 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %40, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) %41 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %41, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_conditional_18-True.ll b/tests/qir/test_pytket_qir_conditional_18-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_18-True.ll rename to tests/qir/test_pytket_qir_conditional_18-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_18-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_18-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..10907a69 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_18-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,37 @@ +; ModuleID = 'test_pytket_qir_conditional_18' +source_filename = "test_pytket_qir_conditional_18" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" +@1 = internal constant [15 x i8] c"tk_SCRATCH_BIT\00" + +define void @main() #0 { +entry: + br i1 true, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 1, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_18-False.ll b/tests/qir/test_pytket_qir_conditional_18-QIRProfile.PYTKET.ll similarity index 89% rename from tests/qir/test_pytket_qir_conditional_18-False.ll rename to tests/qir/test_pytket_qir_conditional_18-QIRProfile.PYTKET.ll index 229c7e9b..2a5665a1 100644 --- a/tests/qir/test_pytket_qir_conditional_18-False.ll +++ b/tests/qir/test_pytket_qir_conditional_18-QIRProfile.PYTKET.ll @@ -22,35 +22,29 @@ condb0: ; preds = %entry br label %contb0 contb0: ; preds = %condb0, %entry - call void @__quantum__rt__tuple_start_record_output() %5 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %5, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %6 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %6, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } diff --git a/tests/qir/test_pytket_qir_conditional_19-True.ll b/tests/qir/test_pytket_qir_conditional_19-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_19-True.ll rename to tests/qir/test_pytket_qir_conditional_19-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_19-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_19-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..a69f57dd --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_19-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,51 @@ +; ModuleID = 'test_pytket_qir_conditional_19' +source_filename = "test_pytket_qir_conditional_19" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + %8 = and i64 1, %7 + %9 = icmp eq i64 1, %8 + %10 = sub i1 true, %9 + %11 = zext i1 %10 to i64 + %12 = mul i64 %11, 2 + %13 = or i64 %12, %7 + %14 = sub i64 1, %11 + %15 = mul i64 %14, 2 + %16 = xor i64 9223372036854775807, %15 + %17 = and i64 %16, %13 + call void @__quantum__rt__int_record_output(i64 %17, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_19-False.ll b/tests/qir/test_pytket_qir_conditional_19-QIRProfile.PYTKET.ll similarity index 86% rename from tests/qir/test_pytket_qir_conditional_19-False.ll rename to tests/qir/test_pytket_qir_conditional_19-QIRProfile.PYTKET.ll index 5ee90850..190b8244 100644 --- a/tests/qir/test_pytket_qir_conditional_19-False.ll +++ b/tests/qir/test_pytket_qir_conditional_19-QIRProfile.PYTKET.ll @@ -14,33 +14,27 @@ entry: %1 = call i1 @get_creg_bit(i1* %0, i64 0) %2 = sub i1 true, %1 call void @set_creg_bit(i1* %0, i64 1, i1 %2) - call void @__quantum__rt__tuple_start_record_output() %3 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } diff --git a/tests/qir/test_pytket_qir_conditional_2-True.ll b/tests/qir/test_pytket_qir_conditional_2-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_2-True.ll rename to tests/qir/test_pytket_qir_conditional_2-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_2-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_2-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..77a63288 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_2-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,75 @@ +; ModuleID = 'test_pytket_qir_conditional_2' +source_filename = "test_pytket_qir_conditional_2" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"c\00" +@3 = internal constant [2 x i8] c"d\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* null) + br i1 false, label %contb0, label %condb0 + +condb0: ; preds = %entry + br label %contb0 + +contb0: ; preds = %condb0, %entry + %0 = phi i64 [ 0, %condb0 ], [ 0, %entry ] + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 2 to %Qubit*), %Result* inttoptr (i64 2 to %Result*)) + %1 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 2 to %Result*)) + %2 = zext i1 %1 to i64 + %3 = mul i64 %2, 4 + %4 = or i64 %3, %0 + %5 = sub i64 1, %2 + %6 = mul i64 %5, 4 + %7 = xor i64 9223372036854775807, %6 + %8 = and i64 %7, %4 + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 1 to %Qubit*), %Result* inttoptr (i64 1 to %Result*)) + %9 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 1 to %Result*)) + %10 = zext i1 %9 to i64 + %11 = mul i64 %10, 8 + %12 = or i64 %11, %8 + %13 = sub i64 1, %10 + %14 = mul i64 %13, 8 + %15 = xor i64 9223372036854775807, %14 + %16 = and i64 %15, %12 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %17 = call i1 @__quantum__qis__read_result__body(%Result* null) + %18 = zext i1 %17 to i64 + %19 = mul i64 %18, 16 + %20 = or i64 %19, %16 + %21 = sub i64 1, %18 + %22 = mul i64 %21, 16 + %23 = xor i64 9223372036854775807, %22 + %24 = and i64 %23, %20 + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %24, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_2-False.ll b/tests/qir/test_pytket_qir_conditional_2-QIRProfile.PYTKET.ll similarity index 93% rename from tests/qir/test_pytket_qir_conditional_2-False.ll rename to tests/qir/test_pytket_qir_conditional_2-QIRProfile.PYTKET.ll index ee3179ea..b08252d8 100644 --- a/tests/qir/test_pytket_qir_conditional_2-False.ll +++ b/tests/qir/test_pytket_qir_conditional_2-QIRProfile.PYTKET.ll @@ -41,7 +41,6 @@ contb0: ; preds = %condb0, %entry call void @mz_to_creg_bit(%Qubit* inttoptr (i64 2 to %Qubit*), i1* %3, i64 2) call void @mz_to_creg_bit(%Qubit* inttoptr (i64 1 to %Qubit*), i1* %3, i64 3) call void @mz_to_creg_bit(%Qubit* null, i1* %3, i64 4) - call void @__quantum__rt__tuple_start_record_output() %14 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %14, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %15 = call i64 @get_int_from_creg(i1* %1) @@ -50,30 +49,25 @@ contb0: ; preds = %condb0, %entry call void @__quantum__rt__int_record_output(i64 %16, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) %17 = call i64 @get_int_from_creg(i1* %3) call void @__quantum__rt__int_record_output(i64 %17, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_conditional_20-True.ll b/tests/qir/test_pytket_qir_conditional_20-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_20-True.ll rename to tests/qir/test_pytket_qir_conditional_20-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_20-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_20-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..96ec9dac --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_20-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,25 @@ +; ModuleID = 'test_pytket_qir_conditional_20' +source_filename = "test_pytket_qir_conditional_20" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" + +define void @main() #0 { +entry: + call void @__quantum__rt__int_record_output(i64 12582912, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_20-False.ll b/tests/qir/test_pytket_qir_conditional_20-QIRProfile.PYTKET.ll similarity index 92% rename from tests/qir/test_pytket_qir_conditional_20-False.ll rename to tests/qir/test_pytket_qir_conditional_20-QIRProfile.PYTKET.ll index 849fbee2..50551dd8 100644 --- a/tests/qir/test_pytket_qir_conditional_20-False.ll +++ b/tests/qir/test_pytket_qir_conditional_20-QIRProfile.PYTKET.ll @@ -41,33 +41,27 @@ entry: call void @set_creg_bit(i1* %0, i64 29, i1 false) call void @set_creg_bit(i1* %0, i64 30, i1 false) call void @set_creg_bit(i1* %0, i64 31, i1 false) - call void @__quantum__rt__tuple_start_record_output() %1 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %1, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/tests/qir/test_pytket_qir_conditional_3-True.ll b/tests/qir/test_pytket_qir_conditional_3-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_3-True.ll rename to tests/qir/test_pytket_qir_conditional_3-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_3-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_3-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..8d99c083 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_3-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,46 @@ +; ModuleID = 'test_pytket_qir_conditional_3' +source_filename = "test_pytket_qir_conditional_3" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"a\00" +@1 = internal constant [2 x i8] c"b\00" +@2 = internal constant [2 x i8] c"c\00" +@3 = internal constant [2 x i8] c"d\00" +@4 = internal constant [2 x i8] c"e\00" +@5 = internal constant [15 x i8] c"tk_SCRATCH_BIT\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @3, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @4, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @5, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_3-False.ll b/tests/qir/test_pytket_qir_conditional_3-QIRProfile.PYTKET.ll similarity index 94% rename from tests/qir/test_pytket_qir_conditional_3-False.ll rename to tests/qir/test_pytket_qir_conditional_3-QIRProfile.PYTKET.ll index cc2380ba..3961a8a3 100644 --- a/tests/qir/test_pytket_qir_conditional_3-False.ll +++ b/tests/qir/test_pytket_qir_conditional_3-QIRProfile.PYTKET.ll @@ -52,7 +52,6 @@ contb0: ; preds = %condb0, %entry %26 = call i64 @get_int_from_creg(i1* %2) %27 = mul i64 %25, %26 call void @set_creg_to_int(i1* %4, i64 %27) - call void @__quantum__rt__tuple_start_record_output() %28 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %28, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %29 = call i64 @get_int_from_creg(i1* %1) @@ -65,30 +64,25 @@ contb0: ; preds = %condb0, %entry call void @__quantum__rt__int_record_output(i64 %32, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @4, i32 0, i32 0)) %33 = call i64 @get_int_from_creg(i1* %5) call void @__quantum__rt__int_record_output(i64 %33, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @5, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } diff --git a/tests/qir/test_pytket_qir_conditional_4-True.ll b/tests/qir/test_pytket_qir_conditional_4-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_4-True.ll rename to tests/qir/test_pytket_qir_conditional_4-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_4-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_4-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..b06b8095 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_4-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,59 @@ +; ModuleID = 'test_pytket_qir_conditional_4' +source_filename = "test_pytket_qir_conditional_4" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 1 to %Qubit*), %Result* inttoptr (i64 1 to %Result*)) + %8 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 1 to %Result*)) + %9 = zext i1 %8 to i64 + %10 = mul i64 %9, 2 + %11 = or i64 %10, %7 + %12 = sub i64 1, %9 + %13 = mul i64 %12, 2 + %14 = xor i64 9223372036854775807, %13 + %15 = and i64 %14, %11 + %16 = icmp eq i64 3, %15 + br i1 %16, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__rt__int_record_output(i64 %15, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_4-False.ll b/tests/qir/test_pytket_qir_conditional_4-QIRProfile.PYTKET.ll similarity index 88% rename from tests/qir/test_pytket_qir_conditional_4-False.ll rename to tests/qir/test_pytket_qir_conditional_4-QIRProfile.PYTKET.ll index 246f9525..99e0de74 100644 --- a/tests/qir/test_pytket_qir_conditional_4-False.ll +++ b/tests/qir/test_pytket_qir_conditional_4-QIRProfile.PYTKET.ll @@ -22,33 +22,27 @@ condb0: ; preds = %entry br label %contb0 contb0: ; preds = %condb0, %entry - call void @__quantum__rt__tuple_start_record_output() %3 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } diff --git a/tests/qir/test_pytket_qir_conditional_5-True.ll b/tests/qir/test_pytket_qir_conditional_5-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_5-True.ll rename to tests/qir/test_pytket_qir_conditional_5-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_5-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_5-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..d0093895 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_5-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,59 @@ +; ModuleID = 'test_pytket_qir_conditional_5' +source_filename = "test_pytket_qir_conditional_5" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %0 = call i1 @__quantum__qis__read_result__body(%Result* null) + %1 = zext i1 %0 to i64 + %2 = mul i64 %1, 1 + %3 = or i64 %2, 0 + %4 = sub i64 1, %1 + %5 = mul i64 %4, 1 + %6 = xor i64 9223372036854775807, %5 + %7 = and i64 %6, %3 + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 1 to %Qubit*), %Result* inttoptr (i64 1 to %Result*)) + %8 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 1 to %Result*)) + %9 = zext i1 %8 to i64 + %10 = mul i64 %9, 2 + %11 = or i64 %10, %7 + %12 = sub i64 1, %9 + %13 = mul i64 %12, 2 + %14 = xor i64 9223372036854775807, %13 + %15 = and i64 %14, %11 + %16 = icmp eq i64 3, %15 + br i1 %16, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__h__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__rt__int_record_output(i64 %15, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } +attributes #1 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_5-False.ll b/tests/qir/test_pytket_qir_conditional_5-QIRProfile.PYTKET.ll similarity index 88% rename from tests/qir/test_pytket_qir_conditional_5-False.ll rename to tests/qir/test_pytket_qir_conditional_5-QIRProfile.PYTKET.ll index 57bd2505..5eceed04 100644 --- a/tests/qir/test_pytket_qir_conditional_5-False.ll +++ b/tests/qir/test_pytket_qir_conditional_5-QIRProfile.PYTKET.ll @@ -22,33 +22,27 @@ condb0: ; preds = %entry br label %contb0 contb0: ; preds = %condb0, %entry - call void @__quantum__rt__tuple_start_record_output() %3 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } diff --git a/tests/qir/test_pytket_qir_conditional_6-True.ll b/tests/qir/test_pytket_qir_conditional_6-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_6-True.ll rename to tests/qir/test_pytket_qir_conditional_6-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_6-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_6-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..da598c59 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_6-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,39 @@ +; ModuleID = 'test_pytket_qir_conditional_6' +source_filename = "test_pytket_qir_conditional_6" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__phasedx__body(double 0x3FD41B2F769CF0E0, double 0x3FE41B2F769CF0E0, %Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +declare void @__quantum__qis__phasedx__body(double, double, %Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="2" "required_num_results"="2" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_6-False.ll b/tests/qir/test_pytket_qir_conditional_6-QIRProfile.PYTKET.ll similarity index 88% rename from tests/qir/test_pytket_qir_conditional_6-False.ll rename to tests/qir/test_pytket_qir_conditional_6-QIRProfile.PYTKET.ll index 66465f5e..b518604b 100644 --- a/tests/qir/test_pytket_qir_conditional_6-False.ll +++ b/tests/qir/test_pytket_qir_conditional_6-QIRProfile.PYTKET.ll @@ -20,33 +20,27 @@ condb0: ; preds = %entry br label %contb0 contb0: ; preds = %condb0, %entry - call void @__quantum__rt__tuple_start_record_output() %3 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) declare void @__quantum__qis__phasedx__body(double, double, %Qubit*) diff --git a/tests/qir/test_pytket_qir_conditional_7-True.ll b/tests/qir/test_pytket_qir_conditional_7-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_7-True.ll rename to tests/qir/test_pytket_qir_conditional_7-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_7-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_7-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..0515e76b --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_7-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,72 @@ +; ModuleID = 'test_pytket_qir_conditional_7' +source_filename = "test_pytket_qir_conditional_7" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [4 x i8] c"syn\00" +@1 = internal constant [15 x i8] c"tk_SCRATCH_BIT\00" + +define void @main() #0 { +entry: + br i1 false, label %condb0, label %contb0 + +condb0: ; preds = %entry + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb0 + +contb0: ; preds = %condb0, %entry + br i1 false, label %condb1, label %contb1 + +condb1: ; preds = %contb0 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb1 + +contb1: ; preds = %condb1, %contb0 + br i1 false, label %condb2, label %contb2 + +condb2: ; preds = %contb1 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb2 + +contb2: ; preds = %condb2, %contb1 + br i1 false, label %condb3, label %contb3 + +condb3: ; preds = %contb2 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb3 + +contb3: ; preds = %condb3, %contb2 + br i1 false, label %condb4, label %contb4 + +condb4: ; preds = %contb3 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb4 + +contb4: ; preds = %condb4, %contb3 + br i1 false, label %condb5, label %contb5 + +condb5: ; preds = %contb4 + call void @__quantum__qis__x__body(%Qubit* null) + br label %contb5 + +contb5: ; preds = %condb5, %contb4 + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @1, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="7" "required_num_results"="7" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_7-False.ll b/tests/qir/test_pytket_qir_conditional_7-QIRProfile.PYTKET.ll similarity index 94% rename from tests/qir/test_pytket_qir_conditional_7-False.ll rename to tests/qir/test_pytket_qir_conditional_7-QIRProfile.PYTKET.ll index 05a64302..45615b2d 100644 --- a/tests/qir/test_pytket_qir_conditional_7-False.ll +++ b/tests/qir/test_pytket_qir_conditional_7-QIRProfile.PYTKET.ll @@ -77,35 +77,29 @@ condb5: ; preds = %contb4 br label %contb5 contb5: ; preds = %condb5, %contb4 - call void @__quantum__rt__tuple_start_record_output() %20 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %20, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @0, i32 0, i32 0)) %21 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %21, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="7" "required_num_results"="7" } diff --git a/tests/qir/test_pytket_qir_conditional_8-True.ll b/tests/qir/test_pytket_qir_conditional_8-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_8-True.ll rename to tests/qir/test_pytket_qir_conditional_8-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_8-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_8-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..9f1ddeb6 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_8-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,29 @@ +; ModuleID = 'test_pytket_qir_conditional_8' +source_filename = "test_pytket_qir_conditional_8" + +%Qubit = type opaque +%Result = type opaque + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 3 to %Qubit*)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="4" "required_num_results"="4" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_8-False.ll b/tests/qir/test_pytket_qir_conditional_8-QIRProfile.PYTKET.ll similarity index 84% rename from tests/qir/test_pytket_qir_conditional_8-False.ll rename to tests/qir/test_pytket_qir_conditional_8-QIRProfile.PYTKET.ll index 277d1dd8..f91194d1 100644 --- a/tests/qir/test_pytket_qir_conditional_8-False.ll +++ b/tests/qir/test_pytket_qir_conditional_8-QIRProfile.PYTKET.ll @@ -10,31 +10,25 @@ entry: call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 1 to %Qubit*)) call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 2 to %Qubit*)) call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 3 to %Qubit*)) - call void @__quantum__rt__tuple_start_record_output() - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="4" "required_num_results"="4" } diff --git a/tests/qir/test_pytket_qir_conditional_9-True.ll b/tests/qir/test_pytket_qir_conditional_9-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_conditional_9-True.ll rename to tests/qir/test_pytket_qir_conditional_9-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_conditional_9-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_conditional_9-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..a99a1155 --- /dev/null +++ b/tests/qir/test_pytket_qir_conditional_9-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,35 @@ +; ModuleID = 'test_pytket_qir_conditional_9' +source_filename = "test_pytket_qir_conditional_9" + +%Qubit = type opaque +%Result = type opaque + +define void @main() #0 { +entry: + call void @__quantum__qis__x__body(%Qubit* null) + call void @__quantum__qis__y__body(%Qubit* inttoptr (i64 1 to %Qubit*)) + call void @__quantum__qis__z__body(%Qubit* inttoptr (i64 2 to %Qubit*)) + call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 3 to %Qubit*)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @__quantum__qis__x__body(%Qubit*) + +declare void @__quantum__qis__y__body(%Qubit*) + +declare void @__quantum__qis__z__body(%Qubit*) + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="4" "required_num_results"="4" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_conditional_9-False.ll b/tests/qir/test_pytket_qir_conditional_9-QIRProfile.PYTKET.ll similarity index 85% rename from tests/qir/test_pytket_qir_conditional_9-False.ll rename to tests/qir/test_pytket_qir_conditional_9-QIRProfile.PYTKET.ll index 1559fb03..9abd0748 100644 --- a/tests/qir/test_pytket_qir_conditional_9-False.ll +++ b/tests/qir/test_pytket_qir_conditional_9-QIRProfile.PYTKET.ll @@ -10,31 +10,25 @@ entry: call void @__quantum__qis__y__body(%Qubit* inttoptr (i64 1 to %Qubit*)) call void @__quantum__qis__z__body(%Qubit* inttoptr (i64 2 to %Qubit*)) call void @__quantum__qis__h__body(%Qubit* inttoptr (i64 3 to %Qubit*)) - call void @__quantum__rt__tuple_start_record_output() - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__x__body(%Qubit*) declare void @__quantum__qis__y__body(%Qubit*) diff --git a/tests/qir/test_pytket_qir_module-True.ll b/tests/qir/test_pytket_qir_module-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_module-True.ll rename to tests/qir/test_pytket_qir_module-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_qasm-True.ll b/tests/qir/test_pytket_qir_qasm-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_qasm-True.ll rename to tests/qir/test_pytket_qir_qasm-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_quantum-True.ll b/tests/qir/test_pytket_qir_quantum-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_quantum-True.ll rename to tests/qir/test_pytket_qir_quantum-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_quantum_2-True.ll b/tests/qir/test_pytket_qir_quantum_2-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_quantum_2-True.ll rename to tests/qir/test_pytket_qir_quantum_2-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_quantum_3-True.ll b/tests/qir/test_pytket_qir_quantum_3-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_quantum_3-True.ll rename to tests/qir/test_pytket_qir_quantum_3-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_quantum_4-True.ll b/tests/qir/test_pytket_qir_quantum_4-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_quantum_4-True.ll rename to tests/qir/test_pytket_qir_quantum_4-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_quantum_5-True.ll b/tests/qir/test_pytket_qir_quantum_5-QIRProfile.ADAPTIVE.ll similarity index 100% rename from tests/qir/test_pytket_qir_quantum_5-True.ll rename to tests/qir/test_pytket_qir_quantum_5-QIRProfile.ADAPTIVE.ll diff --git a/tests/qir/test_pytket_qir_rangepredicate.ll b/tests/qir/test_pytket_qir_rangepredicate.ll index c14518e2..30e718d5 100644 --- a/tests/qir/test_pytket_qir_rangepredicate.ll +++ b/tests/qir/test_pytket_qir_rangepredicate.ll @@ -86,35 +86,29 @@ condb5: ; preds = %contb4 br label %contb5 contb5: ; preds = %condb5, %contb4 - call void @__quantum__rt__tuple_start_record_output() %29 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %29, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %30 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %30, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @1, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="3" "required_num_results"="3" } diff --git a/tests/qir/test_pytket_qir_wasm-True.ll b/tests/qir/test_pytket_qir_wasm-QIRProfile.ADAPTIVE.ll similarity index 89% rename from tests/qir/test_pytket_qir_wasm-True.ll rename to tests/qir/test_pytket_qir_wasm-QIRProfile.ADAPTIVE.ll index 64ab5443..78c308e8 100644 --- a/tests/qir/test_pytket_qir_wasm-True.ll +++ b/tests/qir/test_pytket_qir_wasm-QIRProfile.ADAPTIVE.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm-True' -source_filename = "test_pytket_qir_wasm-True" +; ModuleID = 'test_pytket_qir_wasm-QIRProfile.ADAPTIVE' +source_filename = "test_pytket_qir_wasm-QIRProfile.ADAPTIVE" %Qubit = type opaque %Result = type opaque diff --git a/tests/qir/test_pytket_qir_wasm-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_wasm-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..d36a7c98 --- /dev/null +++ b/tests/qir/test_pytket_qir_wasm-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,44 @@ +; ModuleID = 'test_pytket_qir_wasm-QIRProfile.ADAPTIVE_CREGSIZE' +source_filename = "test_pytket_qir_wasm-QIRProfile.ADAPTIVE_CREGSIZE" + +%Qubit = type opaque +%Result = type opaque + +define void @main() #0 { +entry: + call void @__quantum__qis__h__body(%Qubit* null) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i32, i8*) + +declare void @init() #1 + +declare i32 @add_one(i32) #1 + +declare i32 @multi(i32, i32) #1 + +declare i32 @add_two(i32) #1 + +declare i32 @add_eleven(i32) #1 + +declare void @no_return(i32) #1 + +declare i32 @no_parameters() #1 + +declare i32 @new_function() #1 + +declare void @__quantum__qis__h__body(%Qubit*) + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } + +attributes #1 = { "wasm" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_wasm-False.ll b/tests/qir/test_pytket_qir_wasm-QIRProfile.PYTKET.ll similarity index 79% rename from tests/qir/test_pytket_qir_wasm-False.ll rename to tests/qir/test_pytket_qir_wasm-QIRProfile.PYTKET.ll index 439cfefd..204d8e16 100644 --- a/tests/qir/test_pytket_qir_wasm-False.ll +++ b/tests/qir/test_pytket_qir_wasm-QIRProfile.PYTKET.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm-False' -source_filename = "test_pytket_qir_wasm-False" +; ModuleID = 'test_pytket_qir_wasm-QIRProfile.PYTKET' +source_filename = "test_pytket_qir_wasm-QIRProfile.PYTKET" %Qubit = type opaque %Result = type opaque @@ -7,31 +7,13 @@ source_filename = "test_pytket_qir_wasm-False" define void @main() #0 { entry: call void @__quantum__qis__h__body(%Qubit* null) - call void @__quantum__rt__tuple_start_record_output() - call void @__quantum__rt__tuple_end_record_output() ret void } -declare i1 @get_creg_bit(i1*, i32) - -declare void @set_creg_bit(i1*, i32, i1) - -declare void @set_creg_to_int(i1*, i32) - declare i1 @__quantum__qis__read_result__body(%Result*) -declare i1* @create_creg(i32) - -declare i32 @get_int_from_creg(i1*) - -declare void @mz_to_creg_bit(%Qubit*, i1*, i32) - declare void @__quantum__rt__int_record_output(i32, i8*) -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @init() #1 declare i32 @add_one(i32) #1 @@ -48,6 +30,18 @@ declare i32 @no_parameters() #1 declare i32 @new_function() #1 +declare i1 @get_creg_bit(i1*, i32) + +declare void @set_creg_bit(i1*, i32, i1) + +declare void @set_creg_to_int(i1*, i32) + +declare i1* @create_creg(i32) + +declare i32 @get_int_from_creg(i1*) + +declare void @mz_to_creg_bit(%Qubit*, i1*, i32) + declare void @__quantum__qis__h__body(%Qubit*) attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="1" "required_num_results"="1" } diff --git a/tests/qir/test_pytket_qir_wasm_2-True.ll b/tests/qir/test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE.ll similarity index 93% rename from tests/qir/test_pytket_qir_wasm_2-True.ll rename to tests/qir/test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE.ll index 82eaa09e..4d99870f 100644 --- a/tests/qir/test_pytket_qir_wasm_2-True.ll +++ b/tests/qir/test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm_2-True' -source_filename = "test_pytket_qir_wasm_2-True" +; ModuleID = 'test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE' +source_filename = "test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE" %Result = type opaque diff --git a/tests/qir/test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..e37f4c78 --- /dev/null +++ b/tests/qir/test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,60 @@ +; ModuleID = 'test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE_CREGSIZE' +source_filename = "test_pytket_qir_wasm_2-QIRProfile.ADAPTIVE_CREGSIZE" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" +@1 = internal constant [3 x i8] c"c0\00" +@2 = internal constant [3 x i8] c"c1\00" +@3 = internal constant [3 x i8] c"c2\00" + +define void @main() #0 { +entry: + %0 = call i32 @multi(i32 0, i32 0) + %1 = trunc i32 %0 to i5 + %2 = zext i5 %1 to i32 + %3 = call i32 @add_one(i32 %2) + %4 = trunc i32 %3 to i5 + %5 = zext i5 %4 to i32 + call void @no_return(i32 %5) + call void @init() + %6 = call i32 @no_parameters() + %7 = trunc i32 %6 to i5 + %8 = zext i5 %7 to i32 + call void @__quantum__rt__int_record_output(i32 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i32 0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i32 0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @2, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i32 %8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @3, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i32, i8*) + +declare void @init() #1 + +declare i32 @add_one(i32) #1 + +declare i32 @multi(i32, i32) #1 + +declare i32 @add_two(i32) #1 + +declare i32 @add_eleven(i32) #1 + +declare void @no_return(i32) #1 + +declare i32 @no_parameters() #1 + +declare i32 @new_function() #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="6" "required_num_results"="6" } + +attributes #1 = { "wasm" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_wasm_2-False.ll b/tests/qir/test_pytket_qir_wasm_2-QIRProfile.PYTKET.ll similarity index 88% rename from tests/qir/test_pytket_qir_wasm_2-False.ll rename to tests/qir/test_pytket_qir_wasm_2-QIRProfile.PYTKET.ll index 02f8b390..bba75e51 100644 --- a/tests/qir/test_pytket_qir_wasm_2-False.ll +++ b/tests/qir/test_pytket_qir_wasm_2-QIRProfile.PYTKET.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm_2-False' -source_filename = "test_pytket_qir_wasm_2-False" +; ModuleID = 'test_pytket_qir_wasm_2-QIRProfile.PYTKET' +source_filename = "test_pytket_qir_wasm_2-QIRProfile.PYTKET" %Result = type opaque %Qubit = type opaque @@ -27,7 +27,6 @@ entry: call void @init() %10 = call i32 @no_parameters() call void @set_creg_to_int(i1* %3, i32 %10) - call void @__quantum__rt__tuple_start_record_output() %11 = call i32 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i32 %11, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %12 = call i32 @get_int_from_creg(i1* %1) @@ -36,30 +35,13 @@ entry: call void @__quantum__rt__int_record_output(i32 %13, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @2, i32 0, i32 0)) %14 = call i32 @get_int_from_creg(i1* %3) call void @__quantum__rt__int_record_output(i32 %14, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @3, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } -declare i1 @get_creg_bit(i1*, i32) - -declare void @set_creg_bit(i1*, i32, i1) - -declare void @set_creg_to_int(i1*, i32) - declare i1 @__quantum__qis__read_result__body(%Result*) -declare i1* @create_creg(i32) - -declare i32 @get_int_from_creg(i1*) - -declare void @mz_to_creg_bit(%Qubit*, i1*, i32) - declare void @__quantum__rt__int_record_output(i32, i8*) -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - declare void @init() #1 declare i32 @add_one(i32) #1 @@ -76,6 +58,18 @@ declare i32 @no_parameters() #1 declare i32 @new_function() #1 +declare i1 @get_creg_bit(i1*, i32) + +declare void @set_creg_bit(i1*, i32, i1) + +declare void @set_creg_to_int(i1*, i32) + +declare i1* @create_creg(i32) + +declare i32 @get_int_from_creg(i1*) + +declare void @mz_to_creg_bit(%Qubit*, i1*, i32) + attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="6" "required_num_results"="6" } attributes #1 = { "wasm" } diff --git a/tests/qir/test_pytket_qir_wasm_3-True.ll b/tests/qir/test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE.ll similarity index 90% rename from tests/qir/test_pytket_qir_wasm_3-True.ll rename to tests/qir/test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE.ll index 4c29855a..228f6fe3 100644 --- a/tests/qir/test_pytket_qir_wasm_3-True.ll +++ b/tests/qir/test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm_3-True' -source_filename = "test_pytket_qir_wasm_3-True" +; ModuleID = 'test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE' +source_filename = "test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE" %Result = type opaque diff --git a/tests/qir/test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..2c9973d0 --- /dev/null +++ b/tests/qir/test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,41 @@ +; ModuleID = 'test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE_CREGSIZE' +source_filename = "test_pytket_qir_wasm_3-QIRProfile.ADAPTIVE_CREGSIZE" + +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" +@1 = internal constant [3 x i8] c"c0\00" +@2 = internal constant [3 x i8] c"c1\00" + +define void @main() #0 { +entry: + %0 = call i64 @add_something(i64 0) + %1 = trunc i64 %0 to i4 + %2 = zext i4 %1 to i64 + %3 = call i64 @add_something(i64 %2) + %4 = trunc i64 %3 to i4 + %5 = zext i4 %4 to i64 + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %5, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @init() #1 + +declare i64 @add_something(i64) #1 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="6" "required_num_results"="6" } + +attributes #1 = { "wasm" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_wasm_3-False.ll b/tests/qir/test_pytket_qir_wasm_3-QIRProfile.PYTKET.ll similarity index 85% rename from tests/qir/test_pytket_qir_wasm_3-False.ll rename to tests/qir/test_pytket_qir_wasm_3-QIRProfile.PYTKET.ll index 67702f5f..7fdd6258 100644 --- a/tests/qir/test_pytket_qir_wasm_3-False.ll +++ b/tests/qir/test_pytket_qir_wasm_3-QIRProfile.PYTKET.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm_3-False' -source_filename = "test_pytket_qir_wasm_3-False" +; ModuleID = 'test_pytket_qir_wasm_3-QIRProfile.PYTKET' +source_filename = "test_pytket_qir_wasm_3-QIRProfile.PYTKET" %Result = type opaque %Qubit = type opaque @@ -19,41 +19,35 @@ entry: %5 = call i64 @get_int_from_creg(i1* %2) %6 = call i64 @add_something(i64 %5) call void @set_creg_to_int(i1* %2, i64 %6) - call void @__quantum__rt__tuple_start_record_output() %7 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %8 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @1, i32 0, i32 0)) %9 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %9, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @init() #1 + +declare i64 @add_something(i64) #1 + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - -declare void @init() #1 - -declare i64 @add_something(i64) #1 - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="6" "required_num_results"="6" } attributes #1 = { "wasm" } diff --git a/tests/qir/test_pytket_qir_wasm_4-True.ll b/tests/qir/test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE.ll similarity index 95% rename from tests/qir/test_pytket_qir_wasm_4-True.ll rename to tests/qir/test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE.ll index 1de97eae..b4c9beac 100644 --- a/tests/qir/test_pytket_qir_wasm_4-True.ll +++ b/tests/qir/test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm_4-True' -source_filename = "test_pytket_qir_wasm_4-True" +; ModuleID = 'test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE' +source_filename = "test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE" %Qubit = type opaque %Result = type opaque diff --git a/tests/qir/test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE_CREGSIZE.ll b/tests/qir/test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE_CREGSIZE.ll new file mode 100644 index 00000000..6aec58b3 --- /dev/null +++ b/tests/qir/test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE_CREGSIZE.ll @@ -0,0 +1,71 @@ +; ModuleID = 'test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE_CREGSIZE' +source_filename = "test_pytket_qir_wasm_4-QIRProfile.ADAPTIVE_CREGSIZE" + +%Qubit = type opaque +%Result = type opaque + +@0 = internal constant [2 x i8] c"c\00" +@1 = internal constant [3 x i8] c"c0\00" +@2 = internal constant [3 x i8] c"c1\00" + +define void @main() #0 { +entry: + %0 = call i64 @add_something(i64 0) + %1 = trunc i64 %0 to i4 + %2 = zext i4 %1 to i64 + call void @__quantum__qis__mz__body(%Qubit* null, %Result* null) + %3 = call i1 @__quantum__qis__read_result__body(%Result* null) + %4 = zext i1 %3 to i64 + %5 = mul i64 %4, 1 + %6 = or i64 %5, 0 + %7 = sub i64 1, %4 + %8 = mul i64 %7, 1 + %9 = xor i64 9223372036854775807, %8 + %10 = and i64 %9, %6 + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 1 to %Qubit*), %Result* inttoptr (i64 1 to %Result*)) + %11 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 1 to %Result*)) + %12 = zext i1 %11 to i64 + %13 = mul i64 %12, 2 + %14 = or i64 %13, %10 + %15 = sub i64 1, %12 + %16 = mul i64 %15, 2 + %17 = xor i64 9223372036854775807, %16 + %18 = and i64 %17, %14 + call void @__quantum__qis__mz__body(%Qubit* inttoptr (i64 2 to %Qubit*), %Result* inttoptr (i64 2 to %Result*)) + %19 = call i1 @__quantum__qis__read_result__body(%Result* inttoptr (i64 2 to %Result*)) + %20 = zext i1 %19 to i64 + %21 = mul i64 %20, 4 + %22 = or i64 %21, %18 + %23 = sub i64 1, %20 + %24 = mul i64 %23, 4 + %25 = xor i64 9223372036854775807, %24 + %26 = and i64 %25, %22 + %27 = call i64 @add_something(i64 %2) + %28 = trunc i64 %27 to i4 + %29 = zext i4 %28 to i64 + call void @__quantum__rt__int_record_output(i64 %26, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @1, i32 0, i32 0)) + call void @__quantum__rt__int_record_output(i64 %29, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @2, i32 0, i32 0)) + ret void +} + +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @init() #1 + +declare i64 @add_something(i64) #1 + +declare void @__quantum__qis__mz__body(%Qubit*, %Result* writeonly) #2 + +attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="6" "required_num_results"="6" } +attributes #1 = { "wasm" } +attributes #2 = { "irreversible" } + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"qir_major_version", i32 1} +!1 = !{i32 7, !"qir_minor_version", i32 0} +!2 = !{i32 1, !"dynamic_qubit_management", i1 false} +!3 = !{i32 1, !"dynamic_result_management", i1 false} diff --git a/tests/qir/test_pytket_qir_wasm_4-False.ll b/tests/qir/test_pytket_qir_wasm_4-QIRProfile.PYTKET.ll similarity index 86% rename from tests/qir/test_pytket_qir_wasm_4-False.ll rename to tests/qir/test_pytket_qir_wasm_4-QIRProfile.PYTKET.ll index d10bfc2b..eb30394f 100644 --- a/tests/qir/test_pytket_qir_wasm_4-False.ll +++ b/tests/qir/test_pytket_qir_wasm_4-QIRProfile.PYTKET.ll @@ -1,5 +1,5 @@ -; ModuleID = 'test_pytket_qir_wasm_4-False' -source_filename = "test_pytket_qir_wasm_4-False" +; ModuleID = 'test_pytket_qir_wasm_4-QIRProfile.PYTKET' +source_filename = "test_pytket_qir_wasm_4-QIRProfile.PYTKET" %Qubit = type opaque %Result = type opaque @@ -22,41 +22,35 @@ entry: %5 = call i64 @get_int_from_creg(i1* %2) %6 = call i64 @add_something(i64 %5) call void @set_creg_to_int(i1* %2, i64 %6) - call void @__quantum__rt__tuple_start_record_output() %7 = call i64 @get_int_from_creg(i1* %0) call void @__quantum__rt__int_record_output(i64 %7, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i32 0, i32 0)) %8 = call i64 @get_int_from_creg(i1* %1) call void @__quantum__rt__int_record_output(i64 %8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @1, i32 0, i32 0)) %9 = call i64 @get_int_from_creg(i1* %2) call void @__quantum__rt__int_record_output(i64 %9, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @2, i32 0, i32 0)) - call void @__quantum__rt__tuple_end_record_output() ret void } +declare i1 @__quantum__qis__read_result__body(%Result*) + +declare void @__quantum__rt__int_record_output(i64, i8*) + +declare void @init() #1 + +declare i64 @add_something(i64) #1 + declare i1 @get_creg_bit(i1*, i64) declare void @set_creg_bit(i1*, i64, i1) declare void @set_creg_to_int(i1*, i64) -declare i1 @__quantum__qis__read_result__body(%Result*) - declare i1* @create_creg(i64) declare i64 @get_int_from_creg(i1*) declare void @mz_to_creg_bit(%Qubit*, i1*, i64) -declare void @__quantum__rt__int_record_output(i64, i8*) - -declare void @__quantum__rt__tuple_start_record_output() - -declare void @__quantum__rt__tuple_end_record_output() - -declare void @init() #1 - -declare i64 @add_something(i64) #1 - attributes #0 = { "entry_point" "output_labeling_schema" "qir_profiles"="custom" "required_num_qubits"="6" "required_num_results"="6" } attributes #1 = { "wasm" } diff --git a/tests/utilities.py b/tests/utilities.py index c683e772..3c41ae25 100644 --- a/tests/utilities.py +++ b/tests/utilities.py @@ -14,7 +14,7 @@ from pytket.circuit import Circuit -from pytket.qir.conversion.api import QIRFormat, pytket_to_qir +from pytket.qir.conversion.api import QIRFormat, QIRProfile, pytket_to_qir def check_qir_result(given_qir: str, filename: str, writefile: bool = False) -> None: @@ -43,7 +43,10 @@ def check_qir_result(given_qir: str, filename: str, writefile: bool = False) -> def run_qir_gen_and_check( - circ: Circuit, filename: str, writefile: bool = False, profile: bool = True + circ: Circuit, + filename: str, + writefile: bool = False, + profile: QIRProfile = QIRProfile.ADAPTIVE, ) -> None: """this function can be used to compare the generated qir from a circuit to the qir in a file can be used to write the file as well, if the file is written diff --git a/tests/wasm_test.py b/tests/wasm_test.py index 088d272f..be89c668 100644 --- a/tests/wasm_test.py +++ b/tests/wasm_test.py @@ -17,17 +17,18 @@ from pytket import wasm from pytket.circuit import Bit, Circuit, Qubit -from pytket.qir.conversion.api import QIRFormat, pytket_to_qir +from pytket.qir.conversion.api import QIRFormat, QIRProfile, pytket_to_qir @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_wasm(profile: bool) -> None: +def test_pytket_qir_wasm(profile: QIRProfile) -> None: w = wasm.WasmFileHandler("testfile.wasm") circ = Circuit(1) circ.H(0) @@ -47,11 +48,12 @@ def test_pytket_qir_wasm(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_wasm_2(profile: bool) -> None: +def test_pytket_qir_wasm_2(profile: QIRProfile) -> None: w = wasm.WasmFileHandler("testfile.wasm") c = Circuit(6, 6) c0 = c.add_c_register("c0", 3) @@ -77,11 +79,12 @@ def test_pytket_qir_wasm_2(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_wasm_3(profile: bool) -> None: +def test_pytket_qir_wasm_3(profile: QIRProfile) -> None: w = wasm.WasmFileHandler("testfile.wasm", int_size=64) c = Circuit(6, 6) c0 = c.add_c_register("c0", 3) @@ -103,11 +106,12 @@ def test_pytket_qir_wasm_3(profile: bool) -> None: @pytest.mark.parametrize( "profile", [ - True, - False, + QIRProfile.ADAPTIVE, + QIRProfile.PYTKET, + QIRProfile.ADAPTIVE_CREGSIZE, ], ) -def test_pytket_qir_wasm_4(profile: bool) -> None: +def test_pytket_qir_wasm_4(profile: QIRProfile) -> None: w = wasm.WasmFileHandler("testfile.wasm", int_size=64) c = Circuit(6, 6) c.Measure(Qubit(0), Bit(0)) @@ -130,4 +134,7 @@ def test_pytket_qir_wasm_4(profile: bool) -> None: if __name__ == "__main__": - test_pytket_qir_wasm(True) + test_pytket_qir_wasm(QIRProfile.PYTKET) + test_pytket_qir_wasm_2(QIRProfile.PYTKET) + test_pytket_qir_wasm_3(QIRProfile.PYTKET) + test_pytket_qir_wasm_4(QIRProfile.PYTKET)