From 96cfabc4c505af5199ada36e71c31b59457cb5fc Mon Sep 17 00:00:00 2001 From: Derek Bruening Date: Fri, 22 Oct 2010 02:54:38 +0000 Subject: [PATCH] issue 34: REG_* enum conflict with sys/ucontext.h * renamed to DR_REG_ and DR_SEG_* in all client-exposed headers * added set of compatibility defines if DR_REG_ENUM_COMPATIBILITY is set, which it is for the core to avoid changing the rest of the core * added client var DynamoRIO_REG_COMPATIBILITY for requesting compatibility * if client requests 2.0.0 or earlier, automatically use old constants * added error message if compat is requested and ucontext.h included before DR * added genapi.pl check for exposing non-DR_ constants which is the danger of a half-replace like this * turned on REG_ compatibility for suite/ tests SVN-Revision: 469 --- CMakeLists.txt | 2 +- api/docs/release.dox | 7 +- api/samples/countcalls.c | 8 +- api/samples/memtrace.c | 10 +- api/samples/stats.c | 2 +- api/samples/stl_test.cpp | 5 + api/samples/strace.c | 2 +- core/lib/genapi.pl | 19 +- core/x86/decode.h | 6 +- core/x86/instr.h | 467 ++++++++++++----- core/x86/instr_create.h | 746 +++++++++++++++------------ core/x86/instrument.h | 10 +- make/DynamoRIOConfig.cmake.in | 9 + make/DynamoRIOConfigVersion.cmake.in | 26 +- suite/tests/CMakeLists.txt | 4 + 15 files changed, 838 insertions(+), 485 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index be73da6c5ce..6ff2c2ee962 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -261,7 +261,7 @@ set(CMAKE_BUILD_TYPE "" CACHE INTERNAL # resources when packaging # N.B.: once VERSION_NUMBER crosses 3.x we'll need to update the # symlink loop in core/CMakeLists.txt -set(VERSION_NUMBER_DEFAULT "2.0.0") +set(VERSION_NUMBER_DEFAULT "2.1.0") # do not store the default VERSION_NUMBER in the cache to prevent a stale one # from preventing future version updates in a pre-existing build dir set(VERSION_NUMBER "" CACHE STRING "Version number: leave empty for default") diff --git a/api/docs/release.dox b/api/docs/release.dox index c75f9a4ff22..d01949859b4 100644 --- a/api/docs/release.dox +++ b/api/docs/release.dox @@ -112,7 +112,7 @@ are not backward compatible: see below for details. The changes between version 2.1.0 and 2.0.0 are: - Added Windows 7 support - - Added DR_TRY_EXCEPT() (Issue 52) + - Added DR_TRY_EXCEPT() (Issue 51) - Added dr_client_thread_set_suspendable() - Added dr_get_random_value(), dr_set_random_seed(), and dr_get_random_seed() - Added dr_file_exists() and dr_directory_exists() for Linux @@ -126,6 +126,11 @@ The changes between version 2.1.0 and 2.0.0 are: - Added drsym_enumerate_symbols() to the \p drsyms Extension - Added limited support for printing to the cmd window (Issue 261) via the \p drsyms Extension: drsym_write_to_console() and drsym_using_console() + - Renamed the REG_ constants to DR_REG_ to avoid conflicts with system + headers (Issue 34). \Clients should set(DynamoRIO_REG_COMPATIBILITY ON) + prior to configure_DynamoRIO_client() to use the old constants and avoid + any source changes; this will happen automatically if the \client + targets version 2.0 or earlier. Binary compatibility is unaffected. - Deprecated dr_request_synchronized_exit() and replaced it with dr_set_process_exit_behavior(). Now a full thread synch is performed at exit time in release build if a process exit event or thread exit diff --git a/api/samples/countcalls.c b/api/samples/countcalls.c index 06148c4c8e9..0da1f4b7696 100644 --- a/api/samples/countcalls.c +++ b/api/samples/countcalls.c @@ -176,11 +176,11 @@ insert_counter_update(void *drcontext, instrlist_t *bb, instr_t *where, int offs /* We spill xbx to use a scratch register (we could do a liveness * analysis to try and find a dead register to use). Note that xax * is currently holding the saved eflags. */ - dr_save_reg(drcontext, bb, where, REG_XBX, SPILL_SLOT_2); - dr_insert_read_tls_field(drcontext, bb, where, REG_XBX); + dr_save_reg(drcontext, bb, where, DR_REG_XBX, SPILL_SLOT_2); + dr_insert_read_tls_field(drcontext, bb, where, DR_REG_XBX); instrlist_meta_preinsert(bb, where, - INSTR_CREATE_inc(drcontext, OPND_CREATE_MEM32(REG_XBX, offset))); - dr_restore_reg(drcontext, bb, where, REG_XBX, SPILL_SLOT_2); + INSTR_CREATE_inc(drcontext, OPND_CREATE_MEM32(DR_REG_XBX, offset))); + dr_restore_reg(drcontext, bb, where, DR_REG_XBX, SPILL_SLOT_2); } /* restore flags */ diff --git a/api/samples/memtrace.c b/api/samples/memtrace.c index eed11492535..fbfb3f78a7f 100644 --- a/api/samples/memtrace.c +++ b/api/samples/memtrace.c @@ -308,7 +308,7 @@ code_cache_init(void) ilist = instrlist_create(drcontext); /* The lean procecure simply performs a clean call, and then jump back */ /* jump back to the DR's code cache */ - where = INSTR_CREATE_jmp_ind(drcontext, opnd_create_reg(REG_XCX)); + where = INSTR_CREATE_jmp_ind(drcontext, opnd_create_reg(DR_REG_XCX)); instrlist_meta_append(ilist, where); /* clean call */ dr_insert_clean_call(drcontext, ilist, where, (void *)clean_call, false, 0); @@ -344,8 +344,8 @@ instrument_mem(void *drcontext, instrlist_t *ilist, instr_t *where, { instr_t *instr, *call, *restore; opnd_t ref, opnd1, opnd2; - reg_id_t reg1 = REG_XBX; /* We can optimize it by picking dead reg */ - reg_id_t reg2 = REG_XCX; /* reg2 must be ECX or RCX for jecxz */ + reg_id_t reg1 = DR_REG_XBX; /* We can optimize it by picking dead reg */ + reg_id_t reg2 = DR_REG_XCX; /* reg2 must be ECX or RCX for jecxz */ per_thread_t *data; data = dr_get_tls_field(drcontext); @@ -409,7 +409,7 @@ instrument_mem(void *drcontext, instrlist_t *ilist, instr_t *where, /* Increment reg value by pointer size using lea instr */ opnd1 = opnd_create_reg(reg2); - opnd2 = opnd_create_base_disp(reg2, REG_NULL, 0, + opnd2 = opnd_create_base_disp(reg2, DR_REG_NULL, 0, sizeof(mem_ref_t), OPSZ_lea); instr = INSTR_CREATE_lea(drcontext, opnd1, opnd2); @@ -453,7 +453,7 @@ instrument_mem(void *drcontext, instrlist_t *ilist, instr_t *where, * clean call invocation. This is to reduce the code cache size. */ instrlist_meta_preinsert(ilist, where, call); - /* mov restore REG_XCX */ + /* mov restore DR_REG_XCX */ opnd1 = opnd_create_reg(reg2); /* this is the return address for jumping back from lean procedure */ opnd2 = opnd_create_instr(restore); diff --git a/api/samples/stats.c b/api/samples/stats.c index 46caee52c58..6cbc10f1d80 100644 --- a/api/samples/stats.c +++ b/api/samples/stats.c @@ -591,7 +591,7 @@ insert_inc(void *drcontext, instrlist_t *bb, instr_t *where, immed = OPND_CREATE_INT8(incby); else /* unlikely but possible */ immed = OPND_CREATE_INT32(incby); - inc = INSTR_CREATE_add(drcontext, OPND_CREATE_MEM32(REG_NULL, (int)addr), immed); + inc = INSTR_CREATE_add(drcontext, OPND_CREATE_MEM32(DR_REG_NULL, (int)addr), immed); /* make it thread-safe (only works if it doesn't straddle a cache line) */ instr_set_prefix_flag(inc, PREFIX_LOCK); DR_ASSERT((((ptr_uint_t)addr) & 0x3) == 0); /* 4-aligned => single cache line */ diff --git a/api/samples/stl_test.cpp b/api/samples/stl_test.cpp index 13f0089c186..f8dad8c1b6f 100644 --- a/api/samples/stl_test.cpp +++ b/api/samples/stl_test.cpp @@ -42,6 +42,11 @@ #include #include +#ifdef LINUX +/* included as a test of i#34 */ +# include +#endif + using namespace std; diff --git a/api/samples/strace.c b/api/samples/strace.c index 2c68abe8783..4956d079eca 100644 --- a/api/samples/strace.c +++ b/api/samples/strace.c @@ -284,7 +284,7 @@ decode_syscall_num(byte *entry) } /* Note that we'll failed if somebody has hooked the wrapper */ if (opc == OP_mov_imm && opnd_is_reg(instr_get_dst(&instr, 0)) && - opnd_get_reg(instr_get_dst(&instr, 0)) == REG_EAX) { + opnd_get_reg(instr_get_dst(&instr, 0)) == DR_REG_EAX) { DR_ASSERT(opnd_is_immed_int(instr_get_src(&instr, 0))); num = (int) opnd_get_immed_int(instr_get_src(&instr, 0)); break; diff --git a/core/lib/genapi.pl b/core/lib/genapi.pl index 75bc9c70569..9894eb10ba5 100755 --- a/core/lib/genapi.pl +++ b/core/lib/genapi.pl @@ -248,6 +248,19 @@ ($) if ($_ =~ /\r$/) { chop; }; $l = $_; + if ($output_routine || $output_directly || $output_verbatim) { + # Enforce the rename to DR_REG_ and DR_SEG_ + if (($l =~ /[^_]REG_/ || $l =~ /[^_]SEG_/) && + # We have certain exceptions + ($l !~ /^# define [RS]EG_/ && + $l !~ /DR_REG_ENUM_COMPATIBILITY/ && + $l !~ /conflict/ && + $l !~ /compatibility/ && + $l !~ /weird errors/)) { + die "Error: update to DR_{REG,SEG} constants:\n$l\n"; + } + } + if ($l =~ /^DR_API/) { $output_routine = 1; $did_output_something = 1; @@ -450,10 +463,10 @@ ($) # remove pointers into decode tables $l =~ s/(OP_[a-zA-Z0-9_]*,) *\/\*[^\*]*\*\/(.*)/\1\2/; } - # PR 227381: auto-insert doxygen comments for REG_ enum lines without any + # PR 227381: auto-insert doxygen comments for DR_REG_ enum lines w/o any if ($file =~ "/instr.h" && - $l =~ /^ *[RS]EG_/ && $l !~ /\/\*\*: i#34). + * Clients should set(DynamoRIO_REG_COMPATIBILITY ON) prior to + * configure_DynamoRIO_client() to set this define. + */ +#ifdef DR_REG_ENUM_COMPATIBILITY +# define REG_NULL DR_REG_NULL +# define REG_RAX DR_REG_RAX +# define REG_RCX DR_REG_RCX +# define REG_RDX DR_REG_RDX +# define REG_RBX DR_REG_RBX +# define REG_RSP DR_REG_RSP +# define REG_RBP DR_REG_RBP +# define REG_RSI DR_REG_RSI +# define REG_RDI DR_REG_RDI +# define REG_R8 DR_REG_R8 +# define REG_R9 DR_REG_R9 +# define REG_R10 DR_REG_R10 +# define REG_R11 DR_REG_R11 +# define REG_R12 DR_REG_R12 +# define REG_R13 DR_REG_R13 +# define REG_R14 DR_REG_R14 +# define REG_R15 DR_REG_R15 +# define REG_EAX DR_REG_EAX +# define REG_ECX DR_REG_ECX +# define REG_EDX DR_REG_EDX +# define REG_EBX DR_REG_EBX +# define REG_ESP DR_REG_ESP +# define REG_EBP DR_REG_EBP +# define REG_ESI DR_REG_ESI +# define REG_EDI DR_REG_EDI +# define REG_R8D DR_REG_R8D +# define REG_R9D DR_REG_R9D +# define REG_R10D DR_REG_R10D +# define REG_R11D DR_REG_R11D +# define REG_R12D DR_REG_R12D +# define REG_R13D DR_REG_R13D +# define REG_R14D DR_REG_R14D +# define REG_R15D DR_REG_R15D +# define REG_AX DR_REG_AX +# define REG_CX DR_REG_CX +# define REG_DX DR_REG_DX +# define REG_BX DR_REG_BX +# define REG_SP DR_REG_SP +# define REG_BP DR_REG_BP +# define REG_SI DR_REG_SI +# define REG_DI DR_REG_DI +# define REG_R8W DR_REG_R8W +# define REG_R9W DR_REG_R9W +# define REG_R10W DR_REG_R10W +# define REG_R11W DR_REG_R11W +# define REG_R12W DR_REG_R12W +# define REG_R13W DR_REG_R13W +# define REG_R14W DR_REG_R14W +# define REG_R15W DR_REG_R15W +# define REG_AL DR_REG_AL +# define REG_CL DR_REG_CL +# define REG_DL DR_REG_DL +# define REG_BL DR_REG_BL +# define REG_AH DR_REG_AH +# define REG_CH DR_REG_CH +# define REG_DH DR_REG_DH +# define REG_BH DR_REG_BH +# define REG_R8L DR_REG_R8L +# define REG_R9L DR_REG_R9L +# define REG_R10L DR_REG_R10L +# define REG_R11L DR_REG_R11L +# define REG_R12L DR_REG_R12L +# define REG_R13L DR_REG_R13L +# define REG_R14L DR_REG_R14L +# define REG_R15L DR_REG_R15L +# define REG_SPL DR_REG_SPL +# define REG_BPL DR_REG_BPL +# define REG_SIL DR_REG_SIL +# define REG_DIL DR_REG_DIL +# define REG_MM0 DR_REG_MM0 +# define REG_MM1 DR_REG_MM1 +# define REG_MM2 DR_REG_MM2 +# define REG_MM3 DR_REG_MM3 +# define REG_MM4 DR_REG_MM4 +# define REG_MM5 DR_REG_MM5 +# define REG_MM6 DR_REG_MM6 +# define REG_MM7 DR_REG_MM7 +# define REG_XMM0 DR_REG_XMM0 +# define REG_XMM1 DR_REG_XMM1 +# define REG_XMM2 DR_REG_XMM2 +# define REG_XMM3 DR_REG_XMM3 +# define REG_XMM4 DR_REG_XMM4 +# define REG_XMM5 DR_REG_XMM5 +# define REG_XMM6 DR_REG_XMM6 +# define REG_XMM7 DR_REG_XMM7 +# define REG_XMM8 DR_REG_XMM8 +# define REG_XMM9 DR_REG_XMM9 +# define REG_XMM10 DR_REG_XMM10 +# define REG_XMM11 DR_REG_XMM11 +# define REG_XMM12 DR_REG_XMM12 +# define REG_XMM13 DR_REG_XMM13 +# define REG_XMM14 DR_REG_XMM14 +# define REG_XMM15 DR_REG_XMM15 +# define REG_ST0 DR_REG_ST0 +# define REG_ST1 DR_REG_ST1 +# define REG_ST2 DR_REG_ST2 +# define REG_ST3 DR_REG_ST3 +# define REG_ST4 DR_REG_ST4 +# define REG_ST5 DR_REG_ST5 +# define REG_ST6 DR_REG_ST6 +# define REG_ST7 DR_REG_ST7 +# define SEG_ES DR_SEG_ES +# define SEG_CS DR_SEG_CS +# define SEG_SS DR_SEG_SS +# define SEG_DS DR_SEG_DS +# define SEG_FS DR_SEG_FS +# define SEG_GS DR_SEG_GS +# define REG_DR0 DR_REG_DR0 +# define REG_DR1 DR_REG_DR1 +# define REG_DR2 DR_REG_DR2 +# define REG_DR3 DR_REG_DR3 +# define REG_DR4 DR_REG_DR4 +# define REG_DR5 DR_REG_DR5 +# define REG_DR6 DR_REG_DR6 +# define REG_DR7 DR_REG_DR7 +# define REG_DR8 DR_REG_DR8 +# define REG_DR9 DR_REG_DR9 +# define REG_DR10 DR_REG_DR10 +# define REG_DR11 DR_REG_DR11 +# define REG_DR12 DR_REG_DR12 +# define REG_DR13 DR_REG_DR13 +# define REG_DR14 DR_REG_DR14 +# define REG_DR15 DR_REG_DR15 +# define REG_CR0 DR_REG_CR0 +# define REG_CR1 DR_REG_CR1 +# define REG_CR2 DR_REG_CR2 +# define REG_CR3 DR_REG_CR3 +# define REG_CR4 DR_REG_CR4 +# define REG_CR5 DR_REG_CR5 +# define REG_CR6 DR_REG_CR6 +# define REG_CR7 DR_REG_CR7 +# define REG_CR8 DR_REG_CR8 +# define REG_CR9 DR_REG_CR9 +# define REG_CR10 DR_REG_CR10 +# define REG_CR11 DR_REG_CR11 +# define REG_CR12 DR_REG_CR12 +# define REG_CR13 DR_REG_CR13 +# define REG_CR14 DR_REG_CR14 +# define REG_CR15 DR_REG_CR15 +# define REG_INVALID DR_REG_INVALID +# define REG_XAX DR_REG_XAX +# define REG_XCX DR_REG_XCX +# define REG_XDX DR_REG_XDX +# define REG_XBX DR_REG_XBX +# define REG_XSP DR_REG_XSP +# define REG_XBP DR_REG_XBP +# define REG_XSI DR_REG_XSI +# define REG_XDI DR_REG_XDI +# define REG_START_64 DR_REG_START_64 +# define REG_STOP_64 DR_REG_STOP_64 +# define REG_START_32 DR_REG_START_32 +# define REG_STOP_32 DR_REG_STOP_32 +# define REG_START_16 DR_REG_START_16 +# define REG_STOP_16 DR_REG_STOP_16 +# define REG_START_8 DR_REG_START_8 +# define REG_STOP_8 DR_REG_STOP_8 +# define REG_START_8HL DR_REG_START_8HL +# define REG_STOP_8HL DR_REG_STOP_8HL +# define REG_START_x86_8 DR_REG_START_x86_8 +# define REG_STOP_x86_8 DR_REG_STOP_x86_8 +# define REG_START_x64_8 DR_REG_START_x64_8 +# define REG_STOP_x64_8 DR_REG_STOP_x64_8 +# define REG_START_MMX DR_REG_START_MMX +# define REG_STOP_MMX DR_REG_STOP_MMX +# define REG_START_XMM DR_REG_START_XMM +# define REG_STOP_XMM DR_REG_STOP_XMM +# define REG_START_FLOAT DR_REG_START_FLOAT +# define REG_STOP_FLOAT DR_REG_STOP_FLOAT +# define REG_START_SEGMENT DR_REG_START_SEGMENT +# define REG_STOP_SEGMENT DR_REG_STOP_SEGMENT +# define REG_START_DR DR_REG_START_DR +# define REG_STOP_DR DR_REG_STOP_DR +# define REG_START_CR DR_REG_START_CR +# define REG_STOP_CR DR_REG_STOP_CR +# define REG_LAST_VALID_ENUM DR_REG_LAST_VALID_ENUM +# define REG_LAST_ENUM DR_REG_LAST_ENUM +#endif /* DR_REG_ENUM_COMPATIBILITY */ +/* DR_API EXPORT END */ + #define REG_SPECIFIER_BITS 8 #define SCALE_SPECIFIER_BITS 4 @@ -226,7 +441,7 @@ struct _opnd_t { */ app_pc pc; /* PC_kind and FAR_PC_kind */ /* For FAR_PC_kind and FAR_INSTR_kind, we use pc/instr, and keep the - * segment selector (which is NOT a SEG_constant) in far_pc_seg_selector + * segment selector (which is NOT a DR_SEG_ constant) in far_pc_seg_selector * above, to save space. */ instr_t *instr; /* INSTR_kind and FAR_INSTR_kind */ @@ -265,7 +480,7 @@ enum { PC_kind, INSTR_kind, REG_kind, - BASE_DISP_kind, /* optional SEG_ reg + base reg + scaled index reg + disp */ + BASE_DISP_kind, /* optional DR_SEG_ reg + base reg + scaled index reg + disp */ FAR_PC_kind, /* a segment is specified as a selector value */ FAR_INSTR_kind, /* a segment is specified as a selector value */ #ifdef X64 @@ -283,7 +498,7 @@ opnd_t opnd_create_null(void); DR_API -/** Returns a register operand (\p r must be a REG_ constant). */ +/** Returns a register operand (\p r must be a DR_REG_ constant). */ opnd_t opnd_create_reg(reg_id_t r); @@ -308,7 +523,7 @@ opnd_create_pc(app_pc pc); DR_API /** * Returns a far program address operand with value \p seg_selector:pc. - * \p seg_selector is a segment selector, not a SEG_ constant. + * \p seg_selector is a segment selector, not a DR_SEG_ constant. */ opnd_t opnd_create_far_pc(ushort seg_selector, app_pc pc); @@ -321,7 +536,7 @@ opnd_create_instr(instr_t *instr); DR_API /** * Returns a far instr_t pointer address with value \p seg_selector:instr. - * \p seg_selector is a segment selector, not a SEG_ constant. + * \p seg_selector is a segment selector, not a DR_SEG_ constant. */ opnd_t opnd_create_far_instr(ushort seg_selector, instr_t *instr); @@ -335,7 +550,7 @@ DR_API * - base_reg + index_reg*scale + disp * * The operand has data size data_size (must be a OPSZ_ constant). - * Both \p base_reg and \p index_reg must be REG_ constants. + * Both \p base_reg and \p index_reg must be DR_REG_ constants. * \p scale must be either 1, 2, 4, or 8. */ opnd_t @@ -351,7 +566,7 @@ DR_API * - base_reg + index_reg*scale + disp * * The operand has data size \p data_size (must be a OPSZ_ constant). - * Both \p base_reg and \p index_reg must be REG_ constants. + * Both \p base_reg and \p index_reg must be DR_REG_ constants. * \p scale must be either 1, 2, 4, or 8. * Gives control over encoding optimizations: * -# If \p encode_zero_disp, a zero value for disp will not be omitted; @@ -378,8 +593,8 @@ DR_API * - seg : base_reg + index_reg*scale + disp * * The operand has data size \p data_size (must be a OPSZ_ constant). - * \p seg must be a SEG_ constant. - * Both \p base_reg and \p index_reg must be REG_ constants. + * \p seg must be a DR_SEG_ constant. + * Both \p base_reg and \p index_reg must be DR_REG_ constants. * \p scale must be either 1, 2, 4, or 8. */ opnd_t @@ -395,8 +610,8 @@ DR_API * - seg : base_reg + index_reg*scale + disp * * The operand has data size \p data_size (must be a OPSZ_ constant). - * \p seg must be a SEG_ constant. - * Both \p base_reg and \p index_reg must be REG_ constants. + * \p seg must be a DR_SEG_ constant. + * Both \p base_reg and \p index_reg must be DR_REG_ constants. * scale must be either 1, 2, 4, or 8. * Gives control over encoding optimizations: * -# If \p encode_zero_disp, a zero value for disp will not be omitted; @@ -421,7 +636,7 @@ DR_API * * If \p addr <= 2^32 (which is always true in 32-bit mode), this routine * is equivalent to - * opnd_create_base_disp(REG_NULL, REG_NULL, 0, (int)addr, data_size). + * opnd_create_base_disp(DR_REG_NULL, DR_REG_NULL, 0, (int)addr, data_size). * * Otherwise, this routine creates a separate operand type with an * absolute 64-bit memory address. Note that such an operand can only be @@ -438,7 +653,7 @@ DR_API * * If \p addr <= 2^32 (which is always true in 32-bit mode), this routine * is equivalent to - * opnd_create_far_base_disp(seg, REG_NULL, REG_NULL, 0, (int)addr, data_size). + * opnd_create_far_base_disp(seg, DR_REG_NULL, DR_REG_NULL, 0, (int)addr, data_size). * * Otherwise, this routine creates a separate operand type with an * absolute 64-bit memory address. Note that such an operand can only be @@ -675,7 +890,7 @@ DR_API * Return the data size of \p opnd as a OPSZ_ constant. * Assumes \p opnd is a register, immediate integer, or memory reference. * If \p opnd is a register returns the result of opnd_reg_get_size() - * called on the REG_ constant. + * called on the DR_REG_ constant. * Returns OPSZ_NA if \p opnd does not have a valid size. */ opnd_size_t @@ -692,7 +907,7 @@ opnd_set_size(opnd_t *opnd, opnd_size_t newsize); DR_API /** * Assumes \p opnd is a register operand. - * Returns the register it refers to (a REG_ constant). + * Returns the register it refers to (a DR_REG_ constant). */ reg_id_t opnd_get_reg(opnd_t opnd); @@ -715,7 +930,7 @@ opnd_get_pc(opnd_t opnd); DR_API /** * Assumes \p opnd is a far program address. - * Returns \p opnd's segment, a segment selector (not a SEG_ constant). + * Returns \p opnd's segment, a segment selector (not a DR_SEG_ constant). */ ushort opnd_get_segment_selector(opnd_t opnd); @@ -728,7 +943,7 @@ opnd_get_instr(opnd_t opnd); DR_API /** * Assumes \p opnd is a (near or far) base+disp memory reference. Returns the base - * register (a REG_ constant). + * register (a DR_REG_ constant). */ reg_id_t opnd_get_base(opnd_t opnd); @@ -768,7 +983,7 @@ opnd_is_disp_short_addr(opnd_t opnd); DR_API /** * Assumes \p opnd is a (near or far) base+disp memory reference. - * Returns the index register (a REG_ constant). + * Returns the index register (a DR_REG_ constant). */ reg_id_t opnd_get_index(opnd_t opnd); @@ -781,7 +996,7 @@ opnd_get_scale(opnd_t opnd); DR_API /** * Assumes \p opnd is a (near or far) memory reference of any type. - * Returns \p opnd's segment (a SEG_ constant), or REG_NULL if it is a near + * Returns \p opnd's segment (a DR_SEG_ constant), or DR_REG_NULL if it is a near * memory reference. */ reg_id_t @@ -823,7 +1038,7 @@ reg_check_reg_fixer(void); DR_API /** - * Assumes that \p reg is a REG_ 32-bit register constant. + * Assumes that \p reg is a DR_REG_ 32-bit register constant. * Returns the string name for \p reg. */ const char * @@ -831,7 +1046,7 @@ get_register_name(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ 32-bit register constant. + * Assumes that \p reg is a DR_REG_ 32-bit register constant. * Returns the 16-bit version of \p reg. */ reg_id_t @@ -839,11 +1054,11 @@ reg_32_to_16(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ 32-bit register constant. + * Assumes that \p reg is a DR_REG_ 32-bit register constant. * Returns the 8-bit version of \p reg (the least significant byte: - * REG_AL instead of REG_AH if passed REG_EAX, e.g.). For 32-bit DR - * builds, returns REG_NULL if passed REG_ESP, REG_EBP, REG_ESI, or - * REG_EDI. + * DR_REG_AL instead of DR_REG_AH if passed DR_REG_EAX, e.g.). For 32-bit DR + * builds, returns DR_REG_NULL if passed DR_REG_ESP, DR_REG_EBP, DR_REG_ESI, or + * DR_REG_EDI. */ reg_id_t reg_32_to_8(reg_id_t reg); @@ -853,7 +1068,7 @@ reg_32_to_8(reg_id_t reg); /* DR_API EXPORT END */ DR_API /** - * Assumes that \p reg is a REG_ 32-bit register constant. + * Assumes that \p reg is a DR_REG_ 32-bit register constant. * Returns the 64-bit version of \p reg. * * \note For 64-bit DR builds only. @@ -863,7 +1078,7 @@ reg_32_to_64(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ 64-bit register constant. + * Assumes that \p reg is a DR_REG_ 64-bit register constant. * Returns the 32-bit version of \p reg. * * \note For 64-bit DR builds only. @@ -886,7 +1101,7 @@ reg_is_extended(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ 32-bit register constant. + * Assumes that \p reg is a DR_REG_ 32-bit register constant. * If \p sz == OPSZ_2, returns the 16-bit version of \p reg. * For 64-bit versions of this library, if \p sz == OPSZ_8, returns * the 64-bit version of \p reg. @@ -896,7 +1111,7 @@ reg_32_to_opsz(reg_id_t reg, opnd_size_t sz); DR_API /** - * Assumes that \p reg is a REG_ register constant. + * Assumes that \p reg is a DR_REG_ register constant. * If reg is used as part of the calling convention, returns which * parameter ordinal it matches (0-based); otherwise, returns -1. */ @@ -905,7 +1120,7 @@ reg_parameter_num(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff it refers to a General Purpose Register, * i.e., rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, or a subset. */ @@ -914,8 +1129,8 @@ reg_is_gpr(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. - * Returns true iff it refers to a segment (i.e., it's really a SEG_ + * Assumes that \p reg is a DR_REG_ constant. + * Returns true iff it refers to a segment (i.e., it's really a DR_SEG_ * constant). */ bool @@ -923,7 +1138,7 @@ reg_is_segment(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff it refers to an xmm (128-bit SSE/SSE2) register. */ bool @@ -931,7 +1146,7 @@ reg_is_xmm(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff it refers to an mmx (64-bit) register. */ bool @@ -939,7 +1154,7 @@ reg_is_mmx(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff it refers to a floating-point register. */ bool @@ -947,7 +1162,7 @@ reg_is_fp(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff it refers to a 32-bit general-purpose register. */ bool @@ -963,7 +1178,7 @@ opnd_is_reg_32bit(opnd_t opnd); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff it refers to a 64-bit general-purpose register. */ bool @@ -979,7 +1194,7 @@ opnd_is_reg_64bit(opnd_t opnd); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff it refers to a pointer-sized general-purpose register. */ bool @@ -987,7 +1202,7 @@ reg_is_pointer_sized(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ 32-bit register constant. + * Assumes that \p reg is a DR_REG_ 32-bit register constant. * Returns the pointer-sized version of \p reg. */ reg_id_t @@ -1010,16 +1225,16 @@ opnd_get_reg_mcontext_offs(reg_id_t reg); DR_API /** - * Assumes that \p r1 and \p r2 are both REG_ constants. + * Assumes that \p r1 and \p r2 are both DR_REG_ constants. * Returns true iff \p r1's register overlaps \p r2's register - * (e.g., if \p r1 == REG_AX and \p r2 == REG_EAX). + * (e.g., if \p r1 == DR_REG_AX and \p r2 == DR_REG_EAX). */ bool reg_overlap(reg_id_t r1, reg_id_t r2); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns \p reg's representation as 3 bits in a modrm byte * (the 3 bits are the lower-order bits in the return value). */ @@ -1028,18 +1243,18 @@ reg_get_bits(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns the OPSZ_ constant corresponding to the register size. - * Returns OPSZ_NA if reg is not a REG_ constant. + * Returns OPSZ_NA if reg is not a DR_REG_ constant. */ opnd_size_t reg_get_size(reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff \p opnd refers to reg directly or refers to a register - * that overlaps \p reg (e.g., REG_AX overlaps REG_EAX). + * that overlaps \p reg (e.g., DR_REG_AX overlaps DR_REG_EAX). */ bool opnd_uses_reg(opnd_t opnd, reg_id_t reg); @@ -1065,7 +1280,7 @@ opnd_set_disp_ex(opnd_t *opnd, int disp, bool encode_zero_disp, bool force_full_ DR_API /** - * Assumes that both \p old_reg and \p new_reg are REG_ constants. + * Assumes that both \p old_reg and \p new_reg are DR_REG_ constants. * Replaces all occurrences of \p old_reg in \p *opnd with \p new_reg. */ bool @@ -1106,8 +1321,8 @@ opnd_defines_use(opnd_t def, opnd_t use); DR_API /** - * Assumes \p size is a OPSZ_ or a REG_ constant. - * If \p size is a REG_ constant, first calls reg_get_size(\p size) + * Assumes \p size is a OPSZ_ or a DR_REG_ constant. + * If \p size is a DR_REG_ constant, first calls reg_get_size(\p size) * to get a OPSZ_ constant. * Returns the number of bytes the OPSZ_ constant represents. */ @@ -1906,7 +2121,7 @@ DR_API /** * Shrinks all registers not used as addresses, and all immed integer and * address sizes, to 16 bits. - * Does not shrink REG_ESI or REG_EDI used in string instructions. + * Does not shrink DR_REG_ESI or DR_REG_EDI used in string instructions. */ void instr_shrink_to_16_bits(instr_t *instr); @@ -1929,7 +2144,7 @@ instr_shrink_to_32_bits(instr_t *instr); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff at least one of \p instr's operands references a * register that overlaps \p reg. */ @@ -1946,7 +2161,7 @@ instr_uses_fp_reg(instr_t *instr); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff at least one of \p instr's source operands references \p reg. * * \note Use instr_reads_from_reg() to also consider addressing @@ -1957,7 +2172,7 @@ instr_reg_in_src(instr_t *instr, reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff at least one of \p instr's destination operands references \p reg. */ bool @@ -1965,7 +2180,7 @@ instr_reg_in_dst(instr_t *instr, reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff at least one of \p instr's destination operands is * a register operand for a register that overlaps \p reg. */ @@ -1974,7 +2189,7 @@ instr_writes_to_reg(instr_t *instr, reg_id_t reg); DR_API /** - * Assumes that reg is a REG_ constant. + * Assumes that reg is a DR_REG_ constant. * Returns true iff at least one of instr's operands reads * from a register that overlaps reg (checks both source operands * and addressing registers used in destination operands). @@ -1984,7 +2199,7 @@ instr_reads_from_reg(instr_t *instr, reg_id_t reg); DR_API /** - * Assumes that \p reg is a REG_ constant. + * Assumes that \p reg is a DR_REG_ constant. * Returns true iff at least one of \p instr's destination operands is * the same register (not enough to just overlap) as \p reg. */ diff --git a/core/x86/instr_create.h b/core/x86/instr_create.h index db0d1d04de1..9e7125f3111 100644 --- a/core/x86/instr_create.h +++ b/core/x86/instr_create.h @@ -68,16 +68,16 @@ /* operand convenience routines for common cases */ /** Create a base+disp 8-byte operand. */ #define OPND_CREATE_MEM64(base_reg, disp) \ - opnd_create_base_disp(base_reg, REG_NULL, 0, disp, OPSZ_8) + opnd_create_base_disp(base_reg, DR_REG_NULL, 0, disp, OPSZ_8) /** Create a base+disp 4-byte operand. */ #define OPND_CREATE_MEM32(base_reg, disp) \ - opnd_create_base_disp(base_reg, REG_NULL, 0, disp, OPSZ_4) + opnd_create_base_disp(base_reg, DR_REG_NULL, 0, disp, OPSZ_4) /** Create a base+disp 2-byte operand. */ #define OPND_CREATE_MEM16(base_reg, disp) \ - opnd_create_base_disp(base_reg, REG_NULL, 0, disp, OPSZ_2) + opnd_create_base_disp(base_reg, DR_REG_NULL, 0, disp, OPSZ_2) /** Create a base+disp 1-byte operand. */ #define OPND_CREATE_MEM8(base_reg, disp) \ - opnd_create_base_disp(base_reg, REG_NULL, 0, disp, OPSZ_1) + opnd_create_base_disp(base_reg, DR_REG_NULL, 0, disp, OPSZ_1) #ifdef X64 /** Create a base+disp pointer-sized operand. */ # define OPND_CREATE_MEMPTR OPND_CREATE_MEM64 @@ -444,9 +444,9 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_fxam(dc) \ - instr_create_0dst_1src((dc), OP_fxam, opnd_create_reg(REG_ST0)) + instr_create_0dst_1src((dc), OP_fxam, opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_sahf(dc) \ - instr_create_0dst_1src((dc), OP_sahf, opnd_create_reg(REG_AH)) + instr_create_0dst_1src((dc), OP_sahf, opnd_create_reg(DR_REG_AH)) /* @} */ /* end doxygen group */ /* no destination, 2 explicit sources */ @@ -504,7 +504,7 @@ * a pc (opnd_create_pc()) or an instr_t (opnd_create_instr()). */ #define INSTR_CREATE_jecxz(dc, t) \ - instr_create_0dst_2src((dc), OP_jecxz, (t), opnd_create_reg(REG_XCX)) + instr_create_0dst_2src((dc), OP_jecxz, (t), opnd_create_reg(DR_REG_XCX)) /** * Creates an instr_t for an OP_jecxz instruction that uses cx instead of ecx * (there is no separate OP_jcxz). @@ -513,7 +513,7 @@ * a pc (opnd_create_pc()) or an instr_t (opnd_create_instr()). */ #define INSTR_CREATE_jcxz(dc, t) \ - instr_create_0dst_2src((dc), OP_jecxz, (t), opnd_create_reg(REG_CX)) + instr_create_0dst_2src((dc), OP_jecxz, (t), opnd_create_reg(DR_REG_CX)) /* no destination, 2 sources */ /** @name No destination, 2 sources */ @@ -524,9 +524,11 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_out_1(dc) \ - instr_create_0dst_2src((dc), OP_out, opnd_create_reg(REG_AL), opnd_create_reg(REG_DX)) + instr_create_0dst_2src((dc), OP_out, opnd_create_reg(DR_REG_AL), \ + opnd_create_reg(DR_REG_DX)) #define INSTR_CREATE_out_4(dc) \ - instr_create_0dst_2src((dc), OP_out, opnd_create_reg(REG_EAX), opnd_create_reg(REG_DX)) + instr_create_0dst_2src((dc), OP_out, opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_DX)) /* @} */ /* end doxygen group */ /** @name No destination, explicit immed source */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -538,9 +540,9 @@ * immediate integer (opnd_create_immed_int()). */ #define INSTR_CREATE_out_1_imm(dc, i) \ - instr_create_0dst_2src((dc), OP_out, (i), opnd_create_reg(REG_AL)) + instr_create_0dst_2src((dc), OP_out, (i), opnd_create_reg(DR_REG_AL)) #define INSTR_CREATE_out_4_imm(dc, i) \ - instr_create_0dst_2src((dc), OP_out, (i), opnd_create_reg(REG_EAX)) + instr_create_0dst_2src((dc), OP_out, (i), opnd_create_reg(DR_REG_EAX)) /* @} */ /* end doxygen group */ /** @name No destination, 2 implicit sources */ @@ -552,15 +554,15 @@ */ /* no destination, 2 implicit sources */ #define INSTR_CREATE_mwait(dc) \ - instr_create_0dst_2src((dc), OP_mwait, opnd_create_reg(REG_EAX), \ - opnd_create_reg(REG_ECX)) + instr_create_0dst_2src((dc), OP_mwait, opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_ECX)) /* no destination, 3 implicit sources */ #define INSTR_CREATE_wrmsr(dc) \ - instr_create_0dst_3src((dc), OP_wrmsr, opnd_create_reg(REG_EDX), \ - opnd_create_reg(REG_EAX), opnd_create_reg(REG_ECX)) + instr_create_0dst_3src((dc), OP_wrmsr, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_monitor(dc) \ - instr_create_0dst_3src((dc), OP_monitor, opnd_create_reg(REG_EAX), \ - opnd_create_reg(REG_ECX), opnd_create_reg(REG_EDX)) + instr_create_0dst_3src((dc), OP_monitor, opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_ECX), opnd_create_reg(DR_REG_EDX)) /* @} */ /* end doxygen group */ /* floating-point */ @@ -574,12 +576,12 @@ * be one of the following: * -# A floating point register (opnd_create_reg()). * -# A memory reference (opnd_create_base_disp() or opnd_create_far_base_disp()). - * The other (implicit) source operand is #REG_ST0. + * The other (implicit) source operand is #DR_REG_ST0. */ #define INSTR_CREATE_fcom(dc, s) \ - instr_create_0dst_2src((dc), OP_fcom, (s), opnd_create_reg(REG_ST0)) + instr_create_0dst_2src((dc), OP_fcom, (s), opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fcomp(dc, s) \ - instr_create_0dst_2src((dc), OP_fcomp, (s), opnd_create_reg(REG_ST0)) + instr_create_0dst_2src((dc), OP_fcomp, (s), opnd_create_reg(DR_REG_ST0)) /* @} */ /* end doxygen group */ /** @name Floating-point with fp register source */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -589,20 +591,20 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. * \param f The opnd_t explicit source operand for the instruction, which must * be a floating point register (opnd_create_reg()). - * The other (implicit) source operand is #REG_ST0. + * The other (implicit) source operand is #DR_REG_ST0. */ #define INSTR_CREATE_fcomi(dc, f) \ - instr_create_0dst_2src((dc), OP_fcomi, opnd_create_reg(REG_ST0), (f)) + instr_create_0dst_2src((dc), OP_fcomi, opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fcomip(dc, f) \ - instr_create_0dst_2src((dc), OP_fcomip, opnd_create_reg(REG_ST0), (f)) + instr_create_0dst_2src((dc), OP_fcomip, opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fucomi(dc, f) \ - instr_create_0dst_2src((dc), OP_fucomi, opnd_create_reg(REG_ST0), (f)) + instr_create_0dst_2src((dc), OP_fucomi, opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fucomip(dc, f) \ - instr_create_0dst_2src((dc), OP_fucomip, opnd_create_reg(REG_ST0), (f)) + instr_create_0dst_2src((dc), OP_fucomip, opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fucom(dc, f) \ - instr_create_0dst_2src((dc), OP_fucom, opnd_create_reg(REG_ST0), (f)) + instr_create_0dst_2src((dc), OP_fucom, opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fucomp(dc, f) \ - instr_create_0dst_2src((dc), OP_fucomp, opnd_create_reg(REG_ST0), (f)) + instr_create_0dst_2src((dc), OP_fucomp, opnd_create_reg(DR_REG_ST0), (f)) /* @} */ /* end doxygen group */ /** @name Floating-point with no explicit sources */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -612,9 +614,11 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_fucompp(dc) \ - instr_create_0dst_2src((dc), OP_fucompp, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1)) + instr_create_0dst_2src((dc), OP_fucompp, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1)) #define INSTR_CREATE_fcompp(dc) \ - instr_create_0dst_2src((dc), OP_fcompp, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1)) + instr_create_0dst_2src((dc), OP_fcompp, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1)) /* @} */ /* end doxygen group */ /* 1 destination, no sources */ @@ -732,15 +736,15 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_lahf(dc) \ - instr_create_1dst_0src((dc), OP_lahf, opnd_create_reg(REG_AH)) + instr_create_1dst_0src((dc), OP_lahf, opnd_create_reg(DR_REG_AH)) #define INSTR_CREATE_sysenter(dc) \ - instr_create_1dst_0src((dc), OP_sysenter, opnd_create_reg(REG_XSP)) + instr_create_1dst_0src((dc), OP_sysenter, opnd_create_reg(DR_REG_XSP)) #define INSTR_CREATE_sysexit(dc) \ - instr_create_1dst_0src((dc), OP_sysexit, opnd_create_reg(REG_XSP)) + instr_create_1dst_0src((dc), OP_sysexit, opnd_create_reg(DR_REG_XSP)) #define INSTR_CREATE_syscall(dc) \ - instr_create_1dst_0src((dc), OP_syscall, opnd_create_reg(REG_XCX)) + instr_create_1dst_0src((dc), OP_syscall, opnd_create_reg(DR_REG_XCX)) #define INSTR_CREATE_salc(dc) \ - instr_create_1dst_0src((dc), OP_salc, opnd_create_reg(REG_AL)) + instr_create_1dst_0src((dc), OP_salc, opnd_create_reg(DR_REG_AL)) /* @} */ /* end doxygen group */ /* 1 destination, 1 source */ @@ -976,20 +980,26 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_cdq(dc) \ - instr_create_1dst_1src((dc), OP_cdq, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX)) + instr_create_1dst_1src((dc), OP_cdq, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX)) #define INSTR_CREATE_daa(dc) \ - instr_create_1dst_1src((dc), OP_daa, opnd_create_reg(REG_AL), opnd_create_reg(REG_AL)) + instr_create_1dst_1src((dc), OP_daa, opnd_create_reg(DR_REG_AL), \ + opnd_create_reg(DR_REG_AL)) #define INSTR_CREATE_das(dc) \ - instr_create_1dst_1src((dc), OP_das, opnd_create_reg(REG_AL), opnd_create_reg(REG_AL)) + instr_create_1dst_1src((dc), OP_das, opnd_create_reg(DR_REG_AL), \ + opnd_create_reg(DR_REG_AL)) #define INSTR_CREATE_aaa(dc) \ - instr_create_1dst_1src((dc), OP_aaa, opnd_create_reg(REG_AX), opnd_create_reg(REG_AX)) + instr_create_1dst_1src((dc), OP_aaa, opnd_create_reg(DR_REG_AX), \ + opnd_create_reg(DR_REG_AX)) #define INSTR_CREATE_aas(dc) \ - instr_create_1dst_1src((dc), OP_aas, opnd_create_reg(REG_AX), opnd_create_reg(REG_AX)) + instr_create_1dst_1src((dc), OP_aas, opnd_create_reg(DR_REG_AX), \ + opnd_create_reg(DR_REG_AX)) #define INSTR_CREATE_cwde(dc) \ - instr_create_1dst_1src((dc), OP_cwde, opnd_create_reg(REG_EAX), opnd_create_reg(REG_AX)) + instr_create_1dst_1src((dc), OP_cwde, opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_AX)) #define INSTR_CREATE_xlat(dc) \ - instr_create_1dst_1src((dc), OP_xlat, opnd_create_reg(REG_AL), \ - opnd_create_far_base_disp(SEG_DS, REG_XBX, REG_AL, 1, 0, OPSZ_xlat)) + instr_create_1dst_1src((dc), OP_xlat, opnd_create_reg(DR_REG_AL), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XBX, DR_REG_AL, 1, 0, OPSZ_xlat)) /* @} */ /* end doxygen group */ /** @name In with no explicit sources */ @@ -1000,9 +1010,11 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_in_1(dc) \ - instr_create_1dst_1src((dc), OP_in, opnd_create_reg(REG_AL), opnd_create_reg(REG_DX)) + instr_create_1dst_1src((dc), OP_in, opnd_create_reg(DR_REG_AL), \ + opnd_create_reg(DR_REG_DX)) #define INSTR_CREATE_in_4(dc) \ - instr_create_1dst_1src((dc), OP_in, opnd_create_reg(REG_EAX), opnd_create_reg(REG_DX)) + instr_create_1dst_1src((dc), OP_in, opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_DX)) /* @} */ /* end doxygen group */ /** @name In with explicit source */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -1014,9 +1026,9 @@ * immediate integer (opnd_create_immed_int()). */ #define INSTR_CREATE_in_1_imm(dc, i) \ - instr_create_1dst_1src((dc), OP_in, opnd_create_reg(REG_AL), (i)) + instr_create_1dst_1src((dc), OP_in, opnd_create_reg(DR_REG_AL), (i)) #define INSTR_CREATE_in_4_imm(dc, i) \ - instr_create_1dst_1src((dc), OP_in, opnd_create_reg(REG_EAX), (i)) + instr_create_1dst_1src((dc), OP_in, opnd_create_reg(DR_REG_EAX), (i)) /* @} */ /* end doxygen group */ /* floating-point */ @@ -1030,7 +1042,7 @@ * be a floating point register (opnd_create_reg()). */ #define INSTR_CREATE_fcmovcc(dc, op, f) \ - instr_create_1dst_1src((dc), (op), opnd_create_reg(REG_ST0), (f)) + instr_create_1dst_1src((dc), (op), opnd_create_reg(DR_REG_ST0), (f)) /** @name Floating point with destination that is memory or fp register */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ /** @@ -1043,9 +1055,9 @@ * -# A memory reference (opnd_create_base_disp() or opnd_create_far_base_disp()). */ #define INSTR_CREATE_fst(dc, d) \ - instr_create_1dst_1src((dc), OP_fst, (d), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fst, (d), opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fstp(dc, d) \ - instr_create_1dst_1src((dc), OP_fstp, (d), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fstp, (d), opnd_create_reg(DR_REG_ST0)) /* @} */ /* end doxygen group */ /** * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the @@ -1057,7 +1069,7 @@ * -# A memory reference (opnd_create_base_disp() or opnd_create_far_base_disp()). */ #define INSTR_CREATE_fld(dc, s) \ - instr_create_1dst_1src((dc), OP_fld, opnd_create_reg(REG_ST0), (s)) + instr_create_1dst_1src((dc), OP_fld, opnd_create_reg(DR_REG_ST0), (s)) /** @name Floating-point with memory destination and implicit source */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ /** @@ -1068,13 +1080,13 @@ * a memory reference (opnd_create_base_disp() or opnd_create_far_base_disp()). */ #define INSTR_CREATE_fist(dc, m) \ - instr_create_1dst_1src((dc), OP_fist, (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fist, (m), opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fistp(dc, m) \ - instr_create_1dst_1src((dc), OP_fistp, (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fistp, (m), opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fisttp(dc, m) \ - instr_create_1dst_1src((dc), OP_fisttp, (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fisttp, (m), opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fbstp(dc, m) \ - instr_create_1dst_1src((dc), OP_fbstp, (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fbstp, (m), opnd_create_reg(DR_REG_ST0)) /* @} */ /* end doxygen group */ /** @name Floating-point with memory source */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -1086,9 +1098,9 @@ * a memory reference (opnd_create_base_disp() or opnd_create_far_base_disp()). */ #define INSTR_CREATE_fild(dc, m) \ - instr_create_1dst_1src((dc), OP_fild, opnd_create_reg(REG_ST0), (m)) + instr_create_1dst_1src((dc), OP_fild, opnd_create_reg(DR_REG_ST0), (m)) #define INSTR_CREATE_fbld(dc, m) \ - instr_create_1dst_1src((dc), OP_fbld, opnd_create_reg(REG_ST0), (m)) + instr_create_1dst_1src((dc), OP_fbld, opnd_create_reg(DR_REG_ST0), (m)) /* @} */ /* end doxygen group */ /** @name Floating-point implicit destination and implicit source */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -1098,66 +1110,85 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_fchs(dc) \ - instr_create_1dst_1src((dc), OP_fchs, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fchs, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fabs(dc) \ - instr_create_1dst_1src((dc), OP_fabs, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fabs, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_ftst(dc) \ - instr_create_1dst_1src((dc), OP_ftst, opnd_create_reg(REG_ST0), opnd_create_immed_float(0.0f)) + instr_create_1dst_1src((dc), OP_ftst, opnd_create_reg(DR_REG_ST0), \ + opnd_create_immed_float(0.0f)) #define INSTR_CREATE_fld1(dc) \ - instr_create_1dst_1src((dc), OP_fld1, opnd_create_reg(REG_ST0), opnd_create_immed_float(1.0f)) + instr_create_1dst_1src((dc), OP_fld1, opnd_create_reg(DR_REG_ST0), \ + opnd_create_immed_float(1.0f)) /* FIXME: do we really want these constants here? Should they be floats or doubles? */ #define INSTR_CREATE_fldl2t(dc) \ - instr_create_1dst_1src((dc), OP_fldl2t, opnd_create_reg(REG_ST0), \ + instr_create_1dst_1src((dc), OP_fldl2t, opnd_create_reg(DR_REG_ST0), \ opnd_create_immed_float((float)M_LN10/(float)M_LN2)) #define INSTR_CREATE_fldl2e(dc) \ - instr_create_1dst_1src((dc), OP_fldl2e, opnd_create_reg(REG_ST0), \ + instr_create_1dst_1src((dc), OP_fldl2e, opnd_create_reg(DR_REG_ST0), \ opnd_create_immed_float(1.0f/(float)M_LN2)) #define INSTR_CREATE_fldpi(dc) \ - instr_create_1dst_1src((dc), OP_fldpi, opnd_create_reg(REG_ST0), \ + instr_create_1dst_1src((dc), OP_fldpi, opnd_create_reg(DR_REG_ST0), \ opnd_create_immed_float((float)M_PI)) #define INSTR_CREATE_fldlg2(dc) \ - instr_create_1dst_1src((dc), OP_fldlg2, opnd_create_reg(REG_ST0), \ + instr_create_1dst_1src((dc), OP_fldlg2, opnd_create_reg(DR_REG_ST0), \ opnd_create_immed_float((float)M_LN2/(float)M_LN10)) #define INSTR_CREATE_fldln2(dc) \ - instr_create_1dst_1src((dc), OP_fldln2, opnd_create_reg(REG_ST0), \ + instr_create_1dst_1src((dc), OP_fldln2, opnd_create_reg(DR_REG_ST0), \ opnd_create_immed_float((float)M_LN2)) #define INSTR_CREATE_fldz(dc) \ - instr_create_1dst_1src((dc), OP_fldz, opnd_create_reg(REG_ST0), opnd_create_immed_float(0.0f)) + instr_create_1dst_1src((dc), OP_fldz, opnd_create_reg(DR_REG_ST0), \ + opnd_create_immed_float(0.0f)) #define INSTR_CREATE_f2xm1(dc) \ - instr_create_1dst_1src((dc), OP_f2xm1, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_f2xm1, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fptan(dc) \ - instr_create_1dst_1src((dc), OP_fptan, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fptan, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fxtract(dc) \ - instr_create_1dst_1src((dc), OP_fxtract, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fxtract, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fsqrt(dc) \ - instr_create_1dst_1src((dc), OP_fsqrt, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fsqrt, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fsincos(dc) \ - instr_create_1dst_1src((dc), OP_fsincos, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fsincos, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_frndint(dc) \ - instr_create_1dst_1src((dc), OP_frndint, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_frndint, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fsin(dc) \ - instr_create_1dst_1src((dc), OP_fsin, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fsin, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fcos(dc) \ - instr_create_1dst_1src((dc), OP_fcos, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST0)) + instr_create_1dst_1src((dc), OP_fcos, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fscale(dc) \ - instr_create_1dst_2src((dc), OP_fscale, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1), \ - opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_fscale, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fyl2x(dc) \ - instr_create_2dst_2src((dc), OP_fyl2x, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1), \ - opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1)) + instr_create_2dst_2src((dc), OP_fyl2x, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1), \ + opnd_create_reg(DR_REG_ST0), opnd_create_reg(DR_REG_ST1)) #define INSTR_CREATE_fyl2xp1(dc) \ - instr_create_2dst_2src((dc), OP_fyl2xp1, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1), \ - opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1)) + instr_create_2dst_2src((dc), OP_fyl2xp1, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1), \ + opnd_create_reg(DR_REG_ST0), opnd_create_reg(DR_REG_ST1)) #define INSTR_CREATE_fpatan(dc) \ - instr_create_2dst_2src((dc), OP_fpatan, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1), \ - opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1)) + instr_create_2dst_2src((dc), OP_fpatan, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1), \ + opnd_create_reg(DR_REG_ST0), opnd_create_reg(DR_REG_ST1)) #define INSTR_CREATE_fprem(dc) \ - instr_create_2dst_2src((dc), OP_fprem, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1), \ - opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1)) + instr_create_2dst_2src((dc), OP_fprem, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1), \ + opnd_create_reg(DR_REG_ST0), opnd_create_reg(DR_REG_ST1)) #define INSTR_CREATE_fprem1(dc) \ - instr_create_2dst_2src((dc), OP_fprem1, opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1), \ - opnd_create_reg(REG_ST0), opnd_create_reg(REG_ST1)) + instr_create_2dst_2src((dc), OP_fprem1, opnd_create_reg(DR_REG_ST0), \ + opnd_create_reg(DR_REG_ST1), \ + opnd_create_reg(DR_REG_ST0), opnd_create_reg(DR_REG_ST1)) /* @} */ /* end doxygen group */ /* 1 destination, 2 sources */ @@ -1520,11 +1551,11 @@ instr_create_1dst_2src((dc), OP_pabsd, (d), (s), (d)) /* SSE4 */ #define INSTR_CREATE_pblendvb(dc, d, s) \ - instr_create_1dst_2src((dc), OP_pblendvb, (d), (s), opnd_create_reg(REG_XMM0)) + instr_create_1dst_2src((dc), OP_pblendvb, (d), (s), opnd_create_reg(DR_REG_XMM0)) #define INSTR_CREATE_blendvps(dc, d, s) \ - instr_create_1dst_2src((dc), OP_blendvps, (d), (s), opnd_create_reg(REG_XMM0)) + instr_create_1dst_2src((dc), OP_blendvps, (d), (s), opnd_create_reg(DR_REG_XMM0)) #define INSTR_CREATE_blendvpd(dc, d, s) \ - instr_create_1dst_2src((dc), OP_blendvpd, (d), (s), opnd_create_reg(REG_XMM0)) + instr_create_1dst_2src((dc), OP_blendvpd, (d), (s), opnd_create_reg(DR_REG_XMM0)) #define INSTR_CREATE_crc32(dc, d, s) \ instr_create_1dst_2src((dc), OP_crc32, (d), (s), (d)) #define INSTR_CREATE_packusdw(dc, d, s) \ @@ -1618,25 +1649,31 @@ * \param s The opnd_t explicit source operand for the instruction. */ #define INSTR_CREATE_imul_1(dc, s) \ - instr_create_1dst_2src((dc), OP_imul, opnd_create_reg(REG_AX), (s), opnd_create_reg(REG_AL)) + instr_create_1dst_2src((dc), OP_imul, opnd_create_reg(DR_REG_AX), (s), \ + opnd_create_reg(DR_REG_AL)) #define INSTR_CREATE_imul_4(dc, s) \ - instr_create_2dst_2src((dc), OP_imul, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX), \ - (s), opnd_create_reg(REG_EAX)) + instr_create_2dst_2src((dc), OP_imul, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX), (s), opnd_create_reg(DR_REG_EAX)) #define INSTR_CREATE_mul_1(dc, s) \ - instr_create_1dst_2src((dc), OP_mul, opnd_create_reg(REG_AX), (s), opnd_create_reg(REG_AL)) + instr_create_1dst_2src((dc), OP_mul, opnd_create_reg(DR_REG_AX), (s), \ + opnd_create_reg(DR_REG_AL)) #define INSTR_CREATE_mul_4(dc, s) \ - instr_create_2dst_2src((dc), OP_mul, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX), \ - (s), opnd_create_reg(REG_EAX)) + instr_create_2dst_2src((dc), OP_mul, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX), (s), opnd_create_reg(DR_REG_EAX)) #define INSTR_CREATE_div_1(dc, s) \ - instr_create_2dst_2src((dc), OP_div, opnd_create_reg(REG_AH), opnd_create_reg(REG_AL), (s), opnd_create_reg(REG_AX)) + instr_create_2dst_2src((dc), OP_div, opnd_create_reg(DR_REG_AH), \ + opnd_create_reg(DR_REG_AL), (s), opnd_create_reg(DR_REG_AX)) #define INSTR_CREATE_div_4(dc, s) \ - instr_create_2dst_3src((dc), OP_div, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX), \ - (s), opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX)) + instr_create_2dst_3src((dc), OP_div, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX), \ + (s), opnd_create_reg(DR_REG_EDX), opnd_create_reg(DR_REG_EAX)) #define INSTR_CREATE_idiv_1(dc, s) \ - instr_create_2dst_2src((dc), OP_idiv, opnd_create_reg(REG_AH), opnd_create_reg(REG_AL), (s), opnd_create_reg(REG_AX)) + instr_create_2dst_2src((dc), OP_idiv, opnd_create_reg(DR_REG_AH), \ + opnd_create_reg(DR_REG_AL), (s), opnd_create_reg(DR_REG_AX)) #define INSTR_CREATE_idiv_4(dc, s) \ - instr_create_2dst_3src((dc), OP_idiv, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX), \ - (s), opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX)) + instr_create_2dst_3src((dc), OP_idiv, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX), \ + (s), opnd_create_reg(DR_REG_EDX), opnd_create_reg(DR_REG_EAX)) /* @} */ /* end doxygen group */ /** @name 1 destination, 1 explicit source that is cl, an immediate, or a constant */ @@ -1648,7 +1685,7 @@ * \param d The opnd_t explicit destination operand for the instruction. * \param ri The opnd_t explicit source operand for the instruction, which must * be one of the following: - * -# The register cl (#opnd_create_reg(#REG_CL)); + * -# The register cl (#opnd_create_reg(#DR_REG_CL)); * -# An immediate integer (opnd_create_immed_int()) of size #OPSZ_1; * -# An immediate integer with value 1 and size #OPSZ_0 * (#opnd_create_immed_int(1, #OPSZ_0)), which will become an implicit operand @@ -1681,11 +1718,11 @@ */ #define INSTR_CREATE_maskmovq(dc, s1, s2) \ instr_create_1dst_2src((dc), OP_maskmovq, \ - opnd_create_far_base_disp(SEG_DS, REG_XDI, REG_NULL, 0, 0, OPSZ_maskmovq), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_maskmovq), \ (s1), (s2)) #define INSTR_CREATE_maskmovdqu(dc, s1, s2) \ instr_create_1dst_2src((dc), OP_maskmovdqu, \ - opnd_create_far_base_disp(SEG_DS, REG_XDI, REG_NULL, 0, 0, OPSZ_maskmovdqu), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_maskmovdqu), \ (s1), (s2)) /* @} */ /* end doxygen group */ @@ -1702,7 +1739,7 @@ * instruction, which must be one of the following: * -# A floating point register (opnd_create_reg()). * -# A memory reference (opnd_create_base_disp() or opnd_create_far_base_disp()), - * in which case the destination \p f must be #REG_ST0. + * in which case the destination \p f must be #DR_REG_ST0. */ #define INSTR_CREATE_fadd(dc, f, s) \ instr_create_1dst_2src((dc), OP_fadd, (f), (s), (f)) @@ -1728,17 +1765,17 @@ * must be a floating point register (opnd_create_reg()). */ #define INSTR_CREATE_faddp(dc, f) \ - instr_create_1dst_2src((dc), OP_faddp, (f), opnd_create_reg(REG_ST0), (f)) + instr_create_1dst_2src((dc), OP_faddp, (f), opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fmulp(dc, f) \ - instr_create_1dst_2src((dc), OP_fmulp, (f), opnd_create_reg(REG_ST0), (f)) + instr_create_1dst_2src((dc), OP_fmulp, (f), opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fdivp(dc, f) \ - instr_create_1dst_2src((dc), OP_fdivp, (f), opnd_create_reg(REG_ST0), (f)) + instr_create_1dst_2src((dc), OP_fdivp, (f), opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fdivrp(dc, f) \ - instr_create_1dst_2src((dc), OP_fdivrp, (f), opnd_create_reg(REG_ST0), (f)) + instr_create_1dst_2src((dc), OP_fdivrp, (f), opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fsubp(dc, f) \ - instr_create_1dst_2src((dc), OP_fsubp, (f), opnd_create_reg(REG_ST0), (f)) + instr_create_1dst_2src((dc), OP_fsubp, (f), opnd_create_reg(DR_REG_ST0), (f)) #define INSTR_CREATE_fsubrp(dc, f) \ - instr_create_1dst_2src((dc), OP_fsubrp, (f), opnd_create_reg(REG_ST0), (f)) + instr_create_1dst_2src((dc), OP_fsubrp, (f), opnd_create_reg(DR_REG_ST0), (f)) /* @} */ /* end doxygen group */ /** @name Floating-point with implicit destination and explicit memory source */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -1750,21 +1787,29 @@ * a memory reference (opnd_create_base_disp() or opnd_create_far_base_disp()). */ #define INSTR_CREATE_fiadd(dc, m) \ - instr_create_1dst_2src((dc), OP_fiadd, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_fiadd, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fimul(dc, m) \ - instr_create_1dst_2src((dc), OP_fimul, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_fimul, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fidiv(dc, m) \ - instr_create_1dst_2src((dc), OP_fidiv, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_fidiv, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fidivr(dc, m) \ - instr_create_1dst_2src((dc), OP_fidivr, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_fidivr, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fisub(dc, m) \ - instr_create_1dst_2src((dc), OP_fisub, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_fisub, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_fisubr(dc, m) \ - instr_create_1dst_2src((dc), OP_fisubr, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_fisubr, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_ficom(dc, m) \ - instr_create_1dst_2src((dc), OP_ficom, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_ficom, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) #define INSTR_CREATE_ficomp(dc, m) \ - instr_create_1dst_2src((dc), OP_ficomp, opnd_create_reg(REG_ST0), (m), opnd_create_reg(REG_ST0)) + instr_create_1dst_2src((dc), OP_ficomp, opnd_create_reg(DR_REG_ST0), (m), \ + opnd_create_reg(DR_REG_ST0)) /* @} */ /* end doxygen group */ /** @@ -1829,9 +1874,11 @@ * must be an immediate integer (opnd_create_immed_int()). */ #define INSTR_CREATE_aam(dc, i) \ - instr_create_1dst_2src((dc), OP_aam, opnd_create_reg(REG_AX), (i), opnd_create_reg(REG_AX)) + instr_create_1dst_2src((dc), OP_aam, opnd_create_reg(DR_REG_AX), (i), \ + opnd_create_reg(DR_REG_AX)) #define INSTR_CREATE_aad(dc, i) \ - instr_create_1dst_2src((dc), OP_aad, opnd_create_reg(REG_AX), (i), opnd_create_reg(REG_AX)) + instr_create_1dst_2src((dc), OP_aad, opnd_create_reg(DR_REG_AX), (i), \ + opnd_create_reg(DR_REG_AX)) /* @} */ /* end doxygen group */ /** @name Loop instructions */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -1843,11 +1890,14 @@ * a pc (opnd_create_pc()) or an instr_t (opnd_create_instr()). */ #define INSTR_CREATE_loopne(dc, t) \ - instr_create_1dst_2src((dc), OP_loopne, opnd_create_reg(REG_XCX), (t), opnd_create_reg(REG_XCX)) + instr_create_1dst_2src((dc), OP_loopne, opnd_create_reg(DR_REG_XCX), (t), \ + opnd_create_reg(DR_REG_XCX)) #define INSTR_CREATE_loope(dc, t) \ - instr_create_1dst_2src((dc), OP_loope, opnd_create_reg(REG_XCX), (t), opnd_create_reg(REG_XCX)) + instr_create_1dst_2src((dc), OP_loope, opnd_create_reg(DR_REG_XCX), (t), \ + opnd_create_reg(DR_REG_XCX)) #define INSTR_CREATE_loop(dc, t) \ - instr_create_1dst_2src((dc), OP_loop, opnd_create_reg(REG_XCX), (t), opnd_create_reg(REG_XCX)) + instr_create_1dst_2src((dc), OP_loop, opnd_create_reg(DR_REG_XCX), (t), \ + opnd_create_reg(DR_REG_XCX)) /* @} */ /* end doxygen group */ /* 1 implicit destination, 2 implicit sources */ @@ -1859,27 +1909,27 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_popf(dc) \ - instr_create_1dst_2src((dc), OP_popf, opnd_create_reg(REG_XSP), \ - opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK)) + instr_create_1dst_2src((dc), OP_popf, opnd_create_reg(DR_REG_XSP), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK)) #define INSTR_CREATE_ret(dc) \ - instr_create_1dst_2src((dc), OP_ret, opnd_create_reg(REG_XSP), \ - opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_ret)) + instr_create_1dst_2src((dc), OP_ret, opnd_create_reg(DR_REG_XSP), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_ret)) /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ /* FIXME - using OPSZ_STACK to get 64-bit size (32-bit is default for x64) */ #define INSTR_CREATE_ret_far(dc) \ - instr_create_1dst_2src((dc), OP_ret_far, opnd_create_reg(REG_XSP), \ - opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK)) + instr_create_1dst_2src((dc), OP_ret_far, opnd_create_reg(DR_REG_XSP), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK)) /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ /* FIXME - must use OPSZ_STACK (OPSZ_REXVARSTACK is ambiguous => iretd in 64-bit mode) */ #define INSTR_CREATE_iret(dc) \ - instr_create_1dst_2src((dc), OP_iret, opnd_create_reg(REG_XSP), \ - opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK)) + instr_create_1dst_2src((dc), OP_iret, opnd_create_reg(DR_REG_XSP), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK)) /* @} */ /* end doxygen group */ /* 1 destination, 3 sources: 1 implicit */ @@ -1893,7 +1943,7 @@ * \param s The opnd_t explicit source operand for the instruction. * \param ri The opnd_t explicit source operand for the instruction, which must * be one of the following: - * -# The register cl (#opnd_create_reg(#REG_CL)); + * -# The register cl (#opnd_create_reg(#DR_REG_CL)); * -# An immediate integer (opnd_create_immed_int()) of size #OPSZ_1; */ #define INSTR_CREATE_shld(dc, d, s, ri) \ @@ -1947,9 +1997,9 @@ * must be an immediate integer (opnd_create_immed_int()). */ #define INSTR_CREATE_pcmpistrm(dc, s1, s2, i) \ - instr_create_1dst_3src((dc), OP_pcmpistrm, opnd_create_reg(REG_XMM0), (s1), (s2), (i)) + instr_create_1dst_3src((dc), OP_pcmpistrm, opnd_create_reg(DR_REG_XMM0), (s1), (s2), (i)) #define INSTR_CREATE_pcmpistri(dc, s1, s2, i) \ - instr_create_1dst_3src((dc), OP_pcmpistri, opnd_create_reg(REG_ECX), (s1), (s2), (i)) + instr_create_1dst_3src((dc), OP_pcmpistri, opnd_create_reg(DR_REG_ECX), (s1), (s2), (i)) /* @} */ /* end doxygen group */ /* 1 implicit destination, 3 sources: 2 implicit */ @@ -1965,16 +2015,16 @@ * must be an immediate integer (opnd_create_immed_int()). */ #define INSTR_CREATE_ret_imm(dc, i) \ - instr_create_1dst_3src((dc), OP_ret, opnd_create_reg(REG_XSP), (i), \ - opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_ret)) + instr_create_1dst_3src((dc), OP_ret, opnd_create_reg(DR_REG_XSP), (i), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_ret)) /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ /* FIXME - using OPSZ_STACK to get 64-bit size (32-bit is default for x64) */ #define INSTR_CREATE_ret_far_imm(dc, i) \ - instr_create_1dst_3src((dc), OP_ret_far, opnd_create_reg(REG_XSP), (i), \ - opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK)) + instr_create_1dst_3src((dc), OP_ret_far, opnd_create_reg(DR_REG_XSP), (i), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK)) /* @} */ /* end doxygen group */ /* 1 implicit destination, 5 sources: 2 implicit */ @@ -1990,11 +2040,11 @@ * must be an immediate integer (opnd_create_immed_int()). */ #define INSTR_CREATE_pcmpestrm(dc, s1, s2, i) \ - instr_create_1dst_5src((dc), OP_pcmpestrm, opnd_create_reg(REG_XMM0), \ - (s1), (s2), (i), opnd_create_reg(REG_EAX), opnd_create_reg(REG_EDX)) + instr_create_1dst_5src((dc), OP_pcmpestrm, opnd_create_reg(DR_REG_XMM0), \ + (s1), (s2), (i), opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_EDX)) #define INSTR_CREATE_pcmpestri(dc, s1, s2, i) \ - instr_create_1dst_5src((dc), OP_pcmpestri, opnd_create_reg(REG_ECX), \ - (s1), (s2), (i), opnd_create_reg(REG_EAX), opnd_create_reg(REG_EDX)) + instr_create_1dst_5src((dc), OP_pcmpestri, opnd_create_reg(DR_REG_ECX), \ + (s1), (s2), (i), opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_EDX)) /* @} */ /* end doxygen group */ /* 2 implicit destinations, no sources */ @@ -2004,7 +2054,8 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_rdtsc(dc) \ - instr_create_2dst_0src((dc), OP_rdtsc, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX)) + instr_create_2dst_0src((dc), OP_rdtsc, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX)) /* 2 destinations: 1 implicit, 1 source */ /** @name 2 destinations: 1 implicit, 1 source */ @@ -2017,15 +2068,15 @@ * \param s The opnd_t explicit source operand for the instruction. */ #define INSTR_CREATE_lds(dc, d, s) \ - instr_create_2dst_1src((dc), OP_lds, (d), opnd_create_reg(SEG_DS), (s)) + instr_create_2dst_1src((dc), OP_lds, (d), opnd_create_reg(DR_SEG_DS), (s)) #define INSTR_CREATE_lss(dc, d, s) \ - instr_create_2dst_1src((dc), OP_lss, (d), opnd_create_reg(SEG_SS), (s)) + instr_create_2dst_1src((dc), OP_lss, (d), opnd_create_reg(DR_SEG_SS), (s)) #define INSTR_CREATE_les(dc, d, s) \ - instr_create_2dst_1src((dc), OP_les, (d), opnd_create_reg(SEG_ES), (s)) + instr_create_2dst_1src((dc), OP_les, (d), opnd_create_reg(DR_SEG_ES), (s)) #define INSTR_CREATE_lfs(dc, d, s) \ - instr_create_2dst_1src((dc), OP_lfs, (d), opnd_create_reg(SEG_FS), (s)) + instr_create_2dst_1src((dc), OP_lfs, (d), opnd_create_reg(DR_SEG_FS), (s)) #define INSTR_CREATE_lgs(dc, d, s) \ - instr_create_2dst_1src((dc), OP_lgs, (d), opnd_create_reg(SEG_GS), (s)) + instr_create_2dst_1src((dc), OP_lgs, (d), opnd_create_reg(DR_SEG_GS), (s)) /* @} */ /* end doxygen group */ /* 2 implicit destinations, 1 implicit source */ @@ -2037,33 +2088,33 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_pushf(dc) \ - instr_create_2dst_1src((dc), OP_pushf, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - opnd_create_reg(REG_XSP)) + instr_create_2dst_1src((dc), OP_pushf, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + opnd_create_reg(DR_REG_XSP)) /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ #define INSTR_CREATE_int3(dc) \ - instr_create_2dst_1src((dc), OP_int3, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - opnd_create_reg(REG_XSP)) + instr_create_2dst_1src((dc), OP_int3, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + opnd_create_reg(DR_REG_XSP)) /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ #define INSTR_CREATE_into(dc) \ - instr_create_2dst_1src((dc), OP_into, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - opnd_create_reg(REG_XSP)) + instr_create_2dst_1src((dc), OP_into, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + opnd_create_reg(DR_REG_XSP)) /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ #define INSTR_CREATE_int1(dc) \ - instr_create_2dst_1src((dc), OP_int1, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - opnd_create_reg(REG_XSP)) + instr_create_2dst_1src((dc), OP_int1, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + opnd_create_reg(DR_REG_XSP)) #define INSTR_CREATE_rdmsr(dc) \ - instr_create_2dst_1src((dc), OP_rdmsr, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX), \ - opnd_create_reg(REG_ECX)) + instr_create_2dst_1src((dc), OP_rdmsr, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rdpmc(dc) \ - instr_create_2dst_1src((dc), OP_rdpmc, opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX), \ - opnd_create_reg(REG_ECX)) + instr_create_2dst_1src((dc), OP_rdpmc, opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_ECX)) /* @} */ /* end doxygen group */ /* 2 destinations: 1 implicit, 2 sources */ @@ -2074,9 +2125,9 @@ * \param d The opnd_t explicit destination operand for the instruction. */ #define INSTR_CREATE_pop(dc, d) \ - instr_create_2dst_2src((dc), OP_pop, (d), opnd_create_reg(REG_XSP), \ - opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_VARSTACK)) + instr_create_2dst_2src((dc), OP_pop, (d), opnd_create_reg(DR_REG_XSP), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_VARSTACK)) /* 2 destinations: 1 implicit, 2 sources: 1 implicit */ /** @name 2 destinations: 1 implicit, 2 sources: 1 implicit */ @@ -2106,156 +2157,195 @@ */ #define INSTR_CREATE_ins_1(dc) \ instr_create_2dst_2src((dc), OP_ins, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_DX), opnd_create_reg(REG_XDI)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_ins_4(dc) \ instr_create_2dst_2src((dc), OP_ins, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_DX), opnd_create_reg(REG_XDI)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_stos_1(dc) \ instr_create_2dst_2src((dc), OP_stos, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_AL), opnd_create_reg(REG_XDI)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_AL), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_stos_4(dc) \ instr_create_2dst_2src((dc), OP_stos, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_XAX), opnd_create_reg(REG_XDI)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_XAX), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_lods_1(dc) \ - instr_create_2dst_2src((dc), OP_lods, opnd_create_reg(REG_AL), opnd_create_reg(REG_XSI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI)) + instr_create_2dst_2src((dc), OP_lods, opnd_create_reg(DR_REG_AL), \ + opnd_create_reg(DR_REG_XSI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI)) #define INSTR_CREATE_lods_4(dc) \ - instr_create_2dst_2src((dc), OP_lods, opnd_create_reg(REG_XAX), opnd_create_reg(REG_XSI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI)) + instr_create_2dst_2src((dc), OP_lods, opnd_create_reg(DR_REG_XAX), \ + opnd_create_reg(DR_REG_XSI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI)) #define INSTR_CREATE_movs_1(dc) \ instr_create_3dst_3src((dc), OP_movs, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_movs_4(dc) \ instr_create_3dst_3src((dc), OP_movs, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_rep_ins_1(dc) \ instr_create_3dst_3src((dc), OP_rep_ins, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_reg(REG_DX), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX), \ + opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_ins_4(dc) \ instr_create_3dst_3src((dc), OP_rep_ins, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_reg(REG_DX), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX), \ + opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_stos_1(dc) \ instr_create_3dst_3src((dc), OP_rep_stos, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_reg(REG_AL), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX), \ + opnd_create_reg(DR_REG_AL), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_stos_4(dc) \ instr_create_3dst_3src((dc), OP_rep_stos, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_reg(REG_EAX), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX), \ + opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_lods_1(dc) \ - instr_create_3dst_3src((dc), OP_rep_lods, opnd_create_reg(REG_AL), opnd_create_reg(REG_XSI), \ - opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_ECX)) + instr_create_3dst_3src((dc), OP_rep_lods, opnd_create_reg(DR_REG_AL), \ + opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_lods_4(dc) \ - instr_create_3dst_3src((dc), OP_rep_lods, opnd_create_reg(REG_EAX), opnd_create_reg(REG_XSI), \ - opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_ECX)) + instr_create_3dst_3src((dc), OP_rep_lods, opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_movs_1(dc) \ instr_create_4dst_4src((dc), OP_rep_movs, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_movs_4(dc) \ instr_create_4dst_4src((dc), OP_rep_movs, \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_outs_1(dc) \ - instr_create_1dst_3src((dc), OP_outs, opnd_create_reg(REG_XSI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_DX), opnd_create_reg(REG_XSI)) + instr_create_1dst_3src((dc), OP_outs, opnd_create_reg(DR_REG_XSI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XSI)) #define INSTR_CREATE_outs_4(dc) \ - instr_create_1dst_3src((dc), OP_outs, opnd_create_reg(REG_XSI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_DX), opnd_create_reg(REG_XSI)) + instr_create_1dst_3src((dc), OP_outs, opnd_create_reg(DR_REG_XSI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XSI)) #define INSTR_CREATE_cmps_1(dc) \ - instr_create_2dst_4src((dc), OP_cmps, opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI)) + instr_create_2dst_4src((dc), OP_cmps, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_XDI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_cmps_4(dc) \ - instr_create_2dst_4src((dc), OP_cmps, opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI)) + instr_create_2dst_4src((dc), OP_cmps, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_XDI), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_scas_1(dc) \ - instr_create_1dst_3src((dc), OP_scas, opnd_create_reg(REG_XDI), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_AL), opnd_create_reg(REG_XDI)) + instr_create_1dst_3src((dc), OP_scas, opnd_create_reg(DR_REG_XDI), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_AL), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_scas_4(dc) \ - instr_create_1dst_3src((dc), OP_scas, opnd_create_reg(REG_XDI), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_EAX), opnd_create_reg(REG_XDI)) + instr_create_1dst_3src((dc), OP_scas, opnd_create_reg(DR_REG_XDI), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_XDI)) #define INSTR_CREATE_rep_outs_1(dc) \ - instr_create_2dst_4src((dc), OP_rep_outs, opnd_create_reg(REG_XSI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_DX), opnd_create_reg(REG_XSI), opnd_create_reg(REG_ECX)) + instr_create_2dst_4src((dc), OP_rep_outs, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_outs_4(dc) \ - instr_create_2dst_4src((dc), OP_rep_outs, opnd_create_reg(REG_XSI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_DX), opnd_create_reg(REG_XSI), opnd_create_reg(REG_ECX)) + instr_create_2dst_4src((dc), OP_rep_outs, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_DX), opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_cmps_1(dc) \ - instr_create_3dst_5src((dc), OP_rep_cmps, opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_3dst_5src((dc), OP_rep_cmps, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_cmps_4(dc) \ - instr_create_3dst_5src((dc), OP_rep_cmps, opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_3dst_5src((dc), OP_rep_cmps, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_repne_cmps_1(dc) \ - instr_create_3dst_5src((dc), OP_repne_cmps, opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_3dst_5src((dc), OP_repne_cmps, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_repne_cmps_4(dc) \ - instr_create_3dst_5src((dc), OP_repne_cmps, opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), \ - opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_DS, REG_XSI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_XSI), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_3dst_5src((dc), OP_repne_cmps, opnd_create_reg(DR_REG_XSI), \ + opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_DS, DR_REG_XSI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_XSI), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_scas_1(dc) \ - instr_create_2dst_4src((dc), OP_rep_scas, opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_AL), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_2dst_4src((dc), OP_rep_scas, opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_AL), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_rep_scas_4(dc) \ - instr_create_2dst_4src((dc), OP_rep_scas, opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_EAX), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_2dst_4src((dc), OP_rep_scas, opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_repne_scas_1(dc) \ - instr_create_2dst_4src((dc), OP_repne_scas, opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_1), \ - opnd_create_reg(REG_AL), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_2dst_4src((dc), OP_repne_scas, opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, OPSZ_1), \ + opnd_create_reg(DR_REG_AL), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) #define INSTR_CREATE_repne_scas_4(dc) \ - instr_create_2dst_4src((dc), OP_repne_scas, opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX), \ - opnd_create_far_base_disp(SEG_ES, REG_XDI, REG_NULL, 0, 0, OPSZ_4_rex8_short2), \ - opnd_create_reg(REG_EAX), opnd_create_reg(REG_XDI), opnd_create_reg(REG_ECX)) + instr_create_2dst_4src((dc), OP_repne_scas, opnd_create_reg(DR_REG_XDI), \ + opnd_create_reg(DR_REG_ECX), \ + opnd_create_far_base_disp(DR_SEG_ES, DR_REG_XDI, DR_REG_NULL, 0, 0, \ + OPSZ_4_rex8_short2), \ + opnd_create_reg(DR_REG_EAX), opnd_create_reg(DR_REG_XDI), opnd_create_reg(DR_REG_ECX)) /* @} */ /* end doxygen group */ /* floating point */ @@ -2267,8 +2357,8 @@ * be a floating point register (opnd_create_reg()). */ #define INSTR_CREATE_fxch(dc, f) \ - instr_create_2dst_2src((dc), OP_fxch, opnd_create_reg(REG_ST0), (f), \ - opnd_create_reg(REG_ST0), (f)) + instr_create_2dst_2src((dc), OP_fxch, opnd_create_reg(DR_REG_ST0), (f), \ + opnd_create_reg(DR_REG_ST0), (f)) /* 2 destinations, 2 sources: 1 implicit */ /** @@ -2279,9 +2369,9 @@ * a pc (opnd_create_pc()) or an instr_t (opnd_create_instr()). */ #define INSTR_CREATE_call(dc, t) \ - instr_create_2dst_2src((dc), OP_call, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - (t), opnd_create_reg(REG_XSP)) + instr_create_2dst_2src((dc), OP_call, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + (t), opnd_create_reg(DR_REG_XSP)) /** * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and * the given explicit operands, automatically supplying any implicit operands. @@ -2290,9 +2380,9 @@ * a memory reference created with opnd_create_base_disp(). */ #define INSTR_CREATE_call_ind(dc, t) \ - instr_create_2dst_2src((dc), OP_call_ind, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - (t), opnd_create_reg(REG_XSP)) + instr_create_2dst_2src((dc), OP_call_ind, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + (t), opnd_create_reg(DR_REG_XSP)) /** * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and * the given explicit operands, automatically supplying any implicit operands. @@ -2303,9 +2393,9 @@ /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ #define INSTR_CREATE_call_far(dc, t) \ - instr_create_2dst_2src((dc), OP_call_far, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - (t), opnd_create_reg(REG_XSP)) + instr_create_2dst_2src((dc), OP_call_far, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + (t), opnd_create_reg(DR_REG_XSP)) /** * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and * the given explicit operands, automatically supplying any implicit operands. @@ -2317,9 +2407,9 @@ /* WARNING: actually performs multiple stack operations (not reflected in size) */ /* FIXME - unlike iret/ret_far, OPSZ_4 is typical desired size => OPSZ_REXVARSTACK */ #define INSTR_CREATE_call_far_ind(dc, t) \ - instr_create_2dst_2src((dc), OP_call_far_ind, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_REXVARSTACK), \ - (t), opnd_create_reg(REG_XSP)) + instr_create_2dst_2src((dc), OP_call_far_ind, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_REXVARSTACK), \ + (t), opnd_create_reg(DR_REG_XSP)) /** * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and * the given explicit operands, automatically supplying any implicit operands. @@ -2327,9 +2417,9 @@ * \param s The opnd_t explicit source operand for the instruction. */ #define INSTR_CREATE_push(dc, s) \ - instr_create_2dst_2src((dc), OP_push, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_VARSTACK), \ - (s), opnd_create_reg(REG_XSP)) + instr_create_2dst_2src((dc), OP_push, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_VARSTACK), \ + (s), opnd_create_reg(DR_REG_XSP)) /** * This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx and the * given explicit operands, automatically supplying any implicit operands. @@ -2338,9 +2428,9 @@ * must be an immediate integer (opnd_create_immed_int()). */ #define INSTR_CREATE_push_imm(dc, i) \ - instr_create_2dst_2src((dc), OP_push_imm, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_VARSTACK), \ - (i), opnd_create_reg(REG_XSP)) + instr_create_2dst_2src((dc), OP_push_imm, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_VARSTACK), \ + (i), opnd_create_reg(DR_REG_XSP)) /* 2 implicit destinations, 2 sources: 1 implicit */ /** @@ -2353,9 +2443,9 @@ /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ #define INSTR_CREATE_int(dc, i) \ - instr_create_2dst_2src((dc), OP_int, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - (i), opnd_create_reg(REG_XSP)) + instr_create_2dst_2src((dc), OP_int, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + (i), opnd_create_reg(DR_REG_XSP)) /* 2 destinations: 1 implicit, 3 sources: 1 implicit */ /** @name 2 destinations: 1 implicit, 3 sources: 1 implicit */ @@ -2370,18 +2460,19 @@ * \param s The opnd_t explicit source operand for the instruction. */ #define INSTR_CREATE_cmpxchg_1(dc, d, s) \ - instr_create_2dst_3src((dc), OP_cmpxchg, (d), opnd_create_reg(REG_AL), (s), (d), \ - opnd_create_reg(REG_AL)) + instr_create_2dst_3src((dc), OP_cmpxchg, (d), opnd_create_reg(DR_REG_AL), (s), (d), \ + opnd_create_reg(DR_REG_AL)) #define INSTR_CREATE_cmpxchg_4(dc, d, s) \ - instr_create_2dst_3src((dc), OP_cmpxchg, (d), opnd_create_reg(REG_EAX), (s), (d), \ - opnd_create_reg(REG_EAX)) + instr_create_2dst_3src((dc), OP_cmpxchg, (d), opnd_create_reg(DR_REG_EAX), (s), (d), \ + opnd_create_reg(DR_REG_EAX)) /* @} */ /* end doxygen group */ /* 2 implicit destinations, 3 implicit sources */ #define INSTR_CREATE_leave(dc) \ - instr_create_2dst_3src((dc), OP_leave, opnd_create_reg(REG_XSP), \ - opnd_create_reg(REG_XBP), opnd_create_reg(REG_XBP), opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XBP, REG_NULL, 0, 0, OPSZ_STACK)) + instr_create_2dst_3src((dc), OP_leave, opnd_create_reg(DR_REG_XSP), \ + opnd_create_reg(DR_REG_XBP), opnd_create_reg(DR_REG_XBP), \ + opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XBP, DR_REG_NULL, 0, 0, OPSZ_STACK)) /** @name No destination, many implicit sources */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -2397,8 +2488,9 @@ /* 3 implicit destinations, 1 source */ #define INSTR_CREATE_cpuid(dc) \ - instr_create_4dst_1src((dc), OP_cpuid, opnd_create_reg(REG_EAX), \ - opnd_create_reg(REG_EBX), opnd_create_reg(REG_ECX), opnd_create_reg(REG_EDX), opnd_create_reg(REG_EAX)) + instr_create_4dst_1src((dc), OP_cpuid, opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_EBX), opnd_create_reg(DR_REG_ECX), \ + opnd_create_reg(DR_REG_EDX), opnd_create_reg(DR_REG_EAX)) /* @} */ /* end doxygen group */ /* 3 destinations: 2 implicit, 5 implicit sources */ @@ -2409,9 +2501,10 @@ * \param d The opnd_t explicit destination operand for the instruction. */ #define INSTR_CREATE_cmpxchg8b(dc, d) \ - instr_create_3dst_5src((dc), OP_cmpxchg8b, (d), opnd_create_reg(REG_EAX), \ - opnd_create_reg(REG_EDX), (d), opnd_create_reg(REG_EAX), opnd_create_reg(REG_EDX), \ - opnd_create_reg(REG_ECX), opnd_create_reg(REG_EBX)) + instr_create_3dst_5src((dc), OP_cmpxchg8b, (d), opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_EDX), (d), opnd_create_reg(DR_REG_EAX), \ + opnd_create_reg(DR_REG_EDX), \ + opnd_create_reg(DR_REG_ECX), opnd_create_reg(DR_REG_EBX)) /* 3 implicit destinations, 4 sources: 2 implicit */ /** @@ -2426,10 +2519,10 @@ /* FIXME - size is wrong, xref PR 214976/10541 */ /* WARNING: actually performs multiple stack operations (not reflected in size) */ #define INSTR_CREATE_enter(dc, i16, i8) \ - instr_create_3dst_4src((dc), OP_enter, opnd_create_reg(REG_XSP), \ - opnd_create_base_disp(REG_XSP, REG_NULL, 0, 0, OPSZ_STACK), \ - opnd_create_reg(REG_XBP), \ - (i16), (i8), opnd_create_reg(REG_XSP), opnd_create_reg(REG_XBP)) + instr_create_3dst_4src((dc), OP_enter, opnd_create_reg(DR_REG_XSP), \ + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, 0, OPSZ_STACK), \ + opnd_create_reg(DR_REG_XBP), \ + (i16), (i8), opnd_create_reg(DR_REG_XSP), opnd_create_reg(DR_REG_XBP)) /* 8 implicit destinations, 2 implicit sources */ /** @@ -2455,8 +2548,8 @@ * \param dc The void * dcontext used to allocate memory for the instr_t. */ #define INSTR_CREATE_nop1byte(dc) INSTR_CREATE_nop(dc) -#define INSTR_CREATE_nop2byte(dc) INSTR_CREATE_nop2byte_reg(dc, REG_XDI) -#define INSTR_CREATE_nop3byte(dc) INSTR_CREATE_nop3byte_reg(dc, REG_XDI) +#define INSTR_CREATE_nop2byte(dc) INSTR_CREATE_nop2byte_reg(dc, DR_REG_XDI) +#define INSTR_CREATE_nop3byte(dc) INSTR_CREATE_nop3byte_reg(dc, DR_REG_XDI) /* @} */ /* end doxygen group */ /** @name 2-byte reg nops */ /* @{ */ /* doxygen start group; w/ DISTRIBUTE_GROUP_DOC=YES, one comment suffices. */ @@ -2491,11 +2584,12 @@ INSTR_CREATE_nop2byte_reg(dcontext_t *dcontext, reg_id_t reg) * displacement and put in rex.w */ # define INSTR_CREATE_nop3byte_reg(dc, reg) \ - INSTR_CREATE_lea(dc, opnd_create_reg(reg), OPND_CREATE_MEM_lea(reg, REG_NULL, 0, 0)) + INSTR_CREATE_lea(dc, opnd_create_reg(reg), \ + OPND_CREATE_MEM_lea(reg, DR_REG_NULL, 0, 0)) #else # define INSTR_CREATE_nop3byte_reg(dc, reg) \ INSTR_CREATE_lea(dc, opnd_create_reg(reg), \ - opnd_create_base_disp_ex(reg, REG_NULL, 0, 0, OPSZ_lea, \ + opnd_create_base_disp_ex(reg, DR_REG_NULL, 0, 0, OPSZ_lea, \ true/*encode 0*/, false, false)) #endif /* @} */ /* end doxygen group */ diff --git a/core/x86/instrument.h b/core/x86/instrument.h index e580bc1cbd1..4d6e499ca86 100644 --- a/core/x86/instrument.h +++ b/core/x86/instrument.h @@ -3033,8 +3033,8 @@ DR_API * \note For 64-bit mode, variable-sized argument operands may not work * properly. * - * \note Arguments that reference sub-register portions of REG_XSP are - * not supported (full REG_XSP is supported). + * \note Arguments that reference sub-register portions of DR_REG_XSP are + * not supported (full DR_REG_XSP is supported). */ void dr_insert_clean_call(void *drcontext, instrlist_t *ilist, instr_t *where, @@ -3085,7 +3085,7 @@ DR_API * \note For 64-bit mode, variable-sized argument operands may not work * properly. * - * \note Arguments that reference REG_XSP are not supported in 64-bit mode. + * \note Arguments that reference DR_REG_XSP are not supported in 64-bit mode. */ void dr_insert_call(void *drcontext, instrlist_t *ilist, instr_t *where, @@ -3102,9 +3102,9 @@ DR_API * instrumentation routine should call proc_save_fpstate() to save and * then proc_restore_fpstate() to restore (or use dr_insert_clean_call()). * - * \note The preparation modifies the REG_XSP and REG_XAX registers + * \note The preparation modifies the DR_REG_XSP and DR_REG_XAX registers * (after saving them). Use dr_insert_clean_call() instead if an - * argument to the subsequent call that references REG_XAX is + * argument to the subsequent call that references DR_REG_XAX is * desired. * * \note The stack used to save the state is limited to diff --git a/make/DynamoRIOConfig.cmake.in b/make/DynamoRIOConfig.cmake.in index 0526f48b644..2a4dc4b8e51 100644 --- a/make/DynamoRIOConfig.cmake.in +++ b/make/DynamoRIOConfig.cmake.in @@ -109,6 +109,11 @@ # # set(DynamoRIO_VISATT ON) # +# To request the old REG_ enum symbols (which were changed to DR_REG_ to +# avoid conflicts with system headers) set this variable: +# +# set(DynamoRIO_REG_COMPATIBILITY ON) +# ########################################################################### if (UNIX) @@ -370,6 +375,10 @@ function (configure_DynamoRIO_common target is_client x64_var defs_var link_var) endif (is_client) endif (UNIX) + if (DynamoRIO_REG_COMPATIBILITY) + set(tgt_cflags "${tgt_cflags} -DDR_REG_ENUM_COMPATIBILITY") + endif (DynamoRIO_REG_COMPATIBILITY) + # DynamoRIOTarget.cmake added the "dynamorio" imported target target_link_libraries(${target} dynamorio) diff --git a/make/DynamoRIOConfigVersion.cmake.in b/make/DynamoRIOConfigVersion.cmake.in index 79656dcb60e..970ed07cedb 100644 --- a/make/DynamoRIOConfigVersion.cmake.in +++ b/make/DynamoRIOConfigVersion.cmake.in @@ -32,23 +32,31 @@ set(PACKAGE_VERSION @VERSION_NUMBER@) -if("${PACKAGE_FIND_VERSION_MAJOR}" EQUAL 0) +if ("${PACKAGE_FIND_VERSION_MAJOR}" EQUAL 0) # No version specified: assume compatible set(PACKAGE_VERSION_COMPATIBLE 1) -elseif("${PACKAGE_FIND_VERSION_MAJOR}" LESS @VERSION_NUMBER_MAJOR@) +elseif ("${PACKAGE_FIND_VERSION_MAJOR}" LESS @VERSION_NUMBER_MAJOR@) # Asking for lesser major version == backward compatible set(PACKAGE_VERSION_COMPATIBLE 1) -elseif("${PACKAGE_FIND_VERSION_MAJOR}" EQUAL @VERSION_NUMBER_MAJOR@) +elseif ("${PACKAGE_FIND_VERSION_MAJOR}" EQUAL @VERSION_NUMBER_MAJOR@) # Asking for lesser version == backward compatible - if("${PACKAGE_FIND_VERSION_MINOR}" EQUAL @VERSION_NUMBER_MINOR@) + if ("${PACKAGE_FIND_VERSION_MINOR}" EQUAL @VERSION_NUMBER_MINOR@) set(PACKAGE_VERSION_EXACT 1) - elseif("${PACKAGE_FIND_VERSION_MINOR}" LESS @VERSION_NUMBER_MINOR@) + elseif ("${PACKAGE_FIND_VERSION_MINOR}" LESS @VERSION_NUMBER_MINOR@) set(PACKAGE_VERSION_COMPATIBLE 1) - else() + else () # We are relatively forward compatible except features we added # but better err on the side of caution set(PACKAGE_VERSION_UNSUITABLE 1) - endif() -else() + endif () +else () set(PACKAGE_VERSION_UNSUITABLE 1) -endif() +endif () + +# Compatibility with particular versions +if (NOT "${PACKAGE_FIND_VERSION_MAJOR}" EQUAL 0) + if ("${PACKAGE_FIND_VERSION_MAJOR}.${PACKAGE_FIND_VERSION_MINOR}" STRLESS "2.1") + # Automatically use the older constants if client targets older version + set(DynamoRIO_REG_COMPATIBILITY ON PARENT_SCOPE) + endif () +endif () diff --git a/suite/tests/CMakeLists.txt b/suite/tests/CMakeLists.txt index 4b9a252d09f..3a6439d5d51 100644 --- a/suite/tests/CMakeLists.txt +++ b/suite/tests/CMakeLists.txt @@ -535,6 +535,8 @@ function(tobuild_ci test source client_ops dr_ops exe_ops) endif (NOT "${source}" MATCHES "\\.runall$") add_library(${test}.dll SHARED ${client_source}) + # to avoid changing all the REG_ constants we ask for compatibility + set(DynamoRIO_REG_COMPATIBILITY ON) configure_DynamoRIO_client(${test}.dll) add_dependencies(${test}.dll api_headers) get_target_property(client_path ${test}.dll LOCATION) @@ -554,6 +556,8 @@ function(tobuild_api test source dr_ops exe_ops) get_target_property(pre_lflags ${test} LINK_FLAGS) # disable the default rpath for standalone apps set(DynamoRIO_RPATH OFF) + # to avoid changing all the REG_ constants we ask for compatibility + set(DynamoRIO_REG_COMPATIBILITY ON) configure_DynamoRIO_standalone(${test}) # we don't set -DUSE_DYNAMO on the target to avoid setting # it for tools.c and thus adding dependencies on api headers