From e74114f638b35c401b1a2b271737646f1147a61f Mon Sep 17 00:00:00 2001 From: Edmund Grimley Evans Date: Tue, 28 Jun 2016 09:28:19 +0100 Subject: [PATCH] i#1569 AArch64: Replace "AARCH64 || ARM" with AARCHXX in many places. Review-URL: https://codereview.appspot.com/302060043 --- core/arch/arch.c | 18 ++++++++--------- core/arch/arch.h | 6 +++--- core/arch/arch_exports.h | 16 +++++++-------- core/arch/asm_defines.asm | 8 ++++---- core/arch/decode.h | 2 +- core/arch/emit_utils_shared.c | 10 +++++----- core/arch/instr.h | 4 ++-- core/arch/instr_inline.h | 6 +++--- core/arch/instr_shared.c | 6 +++--- core/arch/interp.c | 6 +++--- core/arch/mangle_shared.c | 2 +- core/arch/opnd.h | 8 ++++---- core/arch/opnd_shared.c | 10 +++++----- core/lib/globals_shared.h | 2 +- core/lib/instrument.c | 2 +- core/lib/mcxtx.h | 2 +- core/optionsx.h | 2 +- core/os_shared.h | 2 +- core/unix/injector.c | 2 +- core/unix/loader_linux.c | 10 +++++----- core/unix/native_elf.c | 2 +- core/unix/os.c | 12 +++++------ core/unix/os_exports.h | 10 +++++----- core/unix/os_private.h | 2 +- core/unix/signal.c | 20 +++++++++---------- core/unix/signal_private.h | 2 +- core/unix/tls.h | 6 +++--- core/unix/tls_linux_aarchxx.c | 2 +- ext/drreg/drreg.c | 2 +- ext/drutil/drutil.c | 6 +++--- ext/drwrap/drwrap.c | 6 +++--- ext/drx/drx.c | 10 +++++----- .../tests/security-common/ret_noncall_trace.c | 2 +- suite/tests/tools.h | 2 +- 34 files changed, 104 insertions(+), 104 deletions(-) diff --git a/core/arch/arch.c b/core/arch/arch.c index a2d99be7686..7015551899b 100644 --- a/core/arch/arch.c +++ b/core/arch/arch.c @@ -427,7 +427,7 @@ shared_gencode_emit(generated_code_t *gencode _IF_X86_64(bool x86_mode)) gencode->do_syscall = pc; pc = emit_do_syscall(GLOBAL_DCONTEXT, gencode, pc, gencode->fcache_return, true/*shared*/, 0, &gencode->do_syscall_offs); -# if defined(ARM) || defined(AARCH64) +# ifdef AARCHXX /* ARM has no thread-private gencode, so our clone syscall is shared */ gencode->do_clone_syscall = pc; pc = emit_do_clone_syscall(GLOBAL_DCONTEXT, gencode, pc, gencode->fcache_return, @@ -569,7 +569,7 @@ shared_gencode_init(IF_X86_64_ELSE(gencode_mode_t gencode_mode, void)) protect_generated_code(gencode, READONLY); } -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* Called during a reset when all threads are suspended */ void arch_reset_stolen_reg(void) @@ -680,7 +680,7 @@ arch_init(void) ASSERT(syscall_method != SYSCALL_METHOD_UNINITIALIZED); #endif -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX dr_reg_stolen = DR_REG_R0 + DYNAMO_OPTION(steal_reg); ASSERT(dr_reg_stolen >= DR_REG_STOLEN_MIN && dr_reg_stolen <= DR_REG_STOLEN_MAX) #endif @@ -1120,7 +1120,7 @@ arch_thread_init(dcontext_t *dcontext) return; #endif -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* Store addresses we access via TLS from exit stubs and gencode. */ get_local_state_extended()->spill_space.fcache_return = PC_AS_JMP_TGT(isa_mode, fcache_return_shared_routine()); @@ -2893,7 +2893,7 @@ hook_vsyscall(dcontext_t *dcontext) instr_free(dcontext, &instr); return res; # undef CHECK -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* No vsyscall support needed for our ARM targets */ ASSERT_NOT_REACHED(); return false; @@ -2926,7 +2926,7 @@ unhook_vsyscall(void) ASSERT(res); } return true; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) ASSERT_NOT_IMPLEMENTED(get_syscall_method() != SYSCALL_METHOD_SYSENTER); return false; #endif /* X86/ARM */ @@ -2948,7 +2948,7 @@ check_syscall_method(dcontext_t *dcontext, instr_t *instr) else if (instr_get_opcode(instr) == OP_call_ind) new_method = SYSCALL_METHOD_WOW64; # endif -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) if (instr_get_opcode(instr) == OP_svc) new_method = SYSCALL_METHOD_SVC; #endif /* X86/ARM */ @@ -3318,7 +3318,7 @@ dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml) , context->r8, context->r9, context->r10, context->r11, context->r12, context->r13, context->r14, context->r15 # endif /* X64 */ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) context->r0, context->r1, context->r2, context->r3, context->r4, context->r5, context->r6, context->r7, context->r8, context->r9, context->r10, context->r11, @@ -3380,7 +3380,7 @@ dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml) context->xflags, context->pc); } -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX reg_t get_stolen_reg_val(priv_mcontext_t *mc) { diff --git a/core/arch/arch.h b/core/arch/arch.h index 3ebc90c66b4..931c8ecd7fb 100644 --- a/core/arch/arch.h +++ b/core/arch/arch.h @@ -114,7 +114,7 @@ mixed_mode_enabled(void) # define SCRATCH_REG3_OFFS XDX_OFFSET # define SCRATCH_REG4_OFFS XSI_OFFSET # define SCRATCH_REG5_OFFS XDI_OFFSET -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define R0_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, r0))) # define R1_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, r1))) # define R2_OFFSET ((MC_OFFS) + (offsetof(priv_mcontext_t, r2))) @@ -491,7 +491,7 @@ instr_t * mangle_rel_addr(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, instr_t *next_instr); #endif -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* mangle instructions that use pc or dr_reg_stolen */ instr_t * mangle_special_registers(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, @@ -1317,7 +1317,7 @@ add_patch_entry_internal(patch_list_t *patch, instr_t *instr, ushort patch_flags cache_pc get_direct_exit_target(dcontext_t *dcontext, uint flags); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX size_t get_fcache_return_tls_offs(dcontext_t *dcontext, uint flags); diff --git a/core/arch/arch_exports.h b/core/arch/arch_exports.h index fa188355f92..4402e0e74c4 100644 --- a/core/arch/arch_exports.h +++ b/core/arch/arch_exports.h @@ -125,7 +125,7 @@ typedef struct _table_stat_state_t { #endif } table_stat_state_t; -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX typedef struct _ibl_entry_pc_t { byte *ibl; byte *unlinked; @@ -140,13 +140,13 @@ typedef struct _spill_state_t { /* Four registers are used in the indirect branch lookup routines */ #ifdef X86 reg_t xax, xbx, xcx, xdx; /* general-purpose registers */ -#elif defined (ARM) || defined(AARCH64) +#elif defined(AARCHXX) reg_t r0, r1, r2, r3; reg_t reg_stolen; /* slot for the stolen register */ #endif /* FIXME: move this below the tables to fit more on cache line */ dcontext_t *dcontext; -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* We store addresses here so we can load pointer-sized addresses into * registers with a single instruction in our exit stubs and gencode. */ @@ -184,7 +184,7 @@ typedef struct _local_state_extended_t { # define SCRATCH_REG1 DR_REG_XBX # define SCRATCH_REG2 DR_REG_XCX # define SCRATCH_REG3 DR_REG_XDX -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define TLS_REG0_SLOT ((ushort)offsetof(spill_state_t, r0)) # define TLS_REG1_SLOT ((ushort)offsetof(spill_state_t, r1)) # define TLS_REG2_SLOT ((ushort)offsetof(spill_state_t, r2)) @@ -198,7 +198,7 @@ typedef struct _local_state_extended_t { #define IBL_TARGET_REG SCRATCH_REG2 #define IBL_TARGET_SLOT TLS_REG2_SLOT #define TLS_DCONTEXT_SLOT ((ushort)offsetof(spill_state_t, dcontext)) -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX # define TLS_FCACHE_RETURN_SLOT ((ushort)offsetof(spill_state_t, fcache_return)) #endif @@ -959,7 +959,7 @@ void arch_thread_exit(dcontext_t *dcontext _IF_WINDOWS(bool detach_stacked_callb void arch_thread_profile_exit(dcontext_t *dcontext); void arch_profile_exit(void); #endif -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX void arch_reset_stolen_reg(void); void arch_mcontext_reset_stolen_reg(dcontext_t *dcontext, priv_mcontext_t *mc); #endif @@ -977,7 +977,7 @@ priv_mcontext_t *dr_mcontext_as_priv_mcontext(dr_mcontext_t *mc); priv_mcontext_t *get_priv_mcontext_from_dstack(dcontext_t *dcontext); void dr_mcontext_init(dr_mcontext_t *mc); void dump_mcontext(priv_mcontext_t *context, file_t f, bool dump_xml); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX reg_t get_stolen_reg_val(priv_mcontext_t *context); void set_stolen_reg_val(priv_mcontext_t *mc, reg_t newval); #endif @@ -1462,7 +1462,7 @@ decode_init(void); # define MAX_PAD_SIZE 3 /****************************************************************************/ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # ifdef X64 # define FRAG_IS_THUMB(flags) false diff --git a/core/arch/asm_defines.asm b/core/arch/asm_defines.asm index bfe74221011..1040f0a7783 100644 --- a/core/arch/asm_defines.asm +++ b/core/arch/asm_defines.asm @@ -65,7 +65,7 @@ # error ARM is only 32-bit; AARCH64 is 64-bit #endif -#if (defined(ARM) || defined(AARCH64)) && defined(WINDOWS) +#if defined(AARCHXX) && defined(WINDOWS) # error ARM/AArch64 on Windows is not supported #endif @@ -106,7 +106,7 @@ # else # define SYMREF(sym) [sym] # endif -# elif defined(ARM) || defined(AARCH64) +# elif defined(AARCHXX) # define BYTE /* nothing */ # define WORD /* nothing */ # define DWORD /* nothing */ @@ -307,7 +307,7 @@ ASSUME fs:_DATA @N@\ # define PTRSZ DWORD #endif -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* ARM AArch64 calling convention: * SP: stack pointer * x30(LR): link register @@ -680,7 +680,7 @@ ASSUME fs:_DATA @N@\ # define RETURN ret # define INC(reg) inc reg # define DEC(reg) dec reg -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define REG_SCRATCH0 REG_R0 # define REG_SCRATCH1 REG_R1 # define REG_SCRATCH2 REG_R2 diff --git a/core/arch/decode.h b/core/arch/decode.h index 0513ce5c7ce..c10effe0529 100644 --- a/core/arch/decode.h +++ b/core/arch/decode.h @@ -434,7 +434,7 @@ bool is_isa_mode_legal(dr_isa_mode_t mode); * Later, if needed, we can introduce a new field in dcontext_t (xref i#862). */ # define X64_CACHE_MODE_DC(dc) (X64_MODE_DC(dc) IF_X64(|| DYNAMO_OPTION(x86_to_x64))) -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define X64_MODE_DC(dc) IF_X64_ELSE(true, false) # define X64_CACHE_MODE_DC(dc) IF_X64_ELSE(true, false) #endif diff --git a/core/arch/emit_utils_shared.c b/core/arch/emit_utils_shared.c index 8af42e4e4c4..4808ba82767 100644 --- a/core/arch/emit_utils_shared.c +++ b/core/arch/emit_utils_shared.c @@ -792,7 +792,7 @@ coarse_indirect_stub_jmp_target(cache_pc stub) ASSERT(*prefix_tgt == JMP_OPCODE); tgt = (cache_pc) PC_RELATIVE_TARGET(prefix_tgt+1); return tgt; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */ ASSERT_NOT_IMPLEMENTED(false); return NULL; @@ -3366,7 +3366,7 @@ instr_t * create_syscall_instr(dcontext_t *dcontext) { int method = get_syscall_method(); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX if (method == SYSCALL_METHOD_SVC || method == SYSCALL_METHOD_UNINITIALIZED) { return INSTR_CREATE_svc(dcontext, opnd_create_immed_int((char)0x0, OPSZ_1)); } @@ -4581,7 +4581,7 @@ emit_do_syscall_common(dcontext_t *dcontext, generated_code_t *code, *syscall_offs += AARCH64_INSTR_SIZE; #endif -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* We have to save r0 in case the syscall is interrupted. We can't * easily do this from dispatch b/c fcache_enter clobbers some TLS slots. */ @@ -5145,7 +5145,7 @@ special_ibl_xfer_is_thread_private(void) #endif } -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX size_t get_ibl_entry_tls_offs(dcontext_t *dcontext, cache_pc ibl_entry) { @@ -5351,7 +5351,7 @@ byte * emit_clean_call_save(dcontext_t *dcontext, byte *pc, generated_code_t *code) { instrlist_t ilist; -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* FIXME i#1551, i#1569: * NYI on ARM/AArch64 (no assert here, it's in get_clean_call_save()) */ diff --git a/core/arch/instr.h b/core/arch/instr.h index 491cd36a47c..9963d2948e3 100644 --- a/core/arch/instr.h +++ b/core/arch/instr.h @@ -257,7 +257,7 @@ typedef enum _dr_pred_type_t { * unconditionally written, unlike regular destination operands. */ DR_PRED_COMPLEX, -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) DR_PRED_EQ, /**< ARM condition: 0000 Equal (Z == 1) */ DR_PRED_NE, /**< ARM condition: 0001 Not equal (Z == 0) */ DR_PRED_CS, /**< ARM condition: 0010 Carry set (C == 1) */ @@ -2838,7 +2838,7 @@ enum { EFLAGS_ARITH = EFLAGS_CF|EFLAGS_PF|EFLAGS_AF|EFLAGS_ZF|EFLAGS_SF|EFLAGS_OF, }; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define EFLAGS_READ_N 0x00000001 /**< Reads N (negative flag). */ # define EFLAGS_READ_Z 0x00000002 /**< Reads Z (zero flag). */ # define EFLAGS_READ_C 0x00000004 /**< Reads C (carry flag). */ diff --git a/core/arch/instr_inline.h b/core/arch/instr_inline.h index e522603a2cd..57663334daf 100644 --- a/core/arch/instr_inline.h +++ b/core/arch/instr_inline.h @@ -154,7 +154,7 @@ opnd_is_far_rel_addr(opnd_t opnd) return IF_X86_ELSE(opnd.kind == REL_ADDR_kind && opnd.aux.segment != DR_REG_NULL, false); } -# elif defined(ARM) || defined(AARCH64) +# elif defined(AARCHXX) # ifdef ARM # define OPND_IS_REL_ADDR(op) \ ((op).kind == REL_ADDR_kind || \ @@ -258,7 +258,7 @@ opnd_create_pc(app_pc pc) opnd_is_immed_int(opnd), \ "opnd_get_flags called on non-reg non-base-disp non-immed-int opnd") \ 0) -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define OPND_GET_FLAGS(opnd) \ (CLIENT_ASSERT_(opnd_is_reg(opnd) || opnd_is_base_disp(opnd) || \ opnd_is_immed_int(opnd), \ @@ -293,7 +293,7 @@ opnd_create_pc(app_pc pc) opnd_is_rel_addr(opnd)), \ "opnd_get_segment called on invalid opnd type") \ (opnd).aux.segment) -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define OPND_GET_SEGMENT(opnd) DR_REG_NULL #endif #define opnd_get_segment OPND_GET_SEGMENT diff --git a/core/arch/instr_shared.c b/core/arch/instr_shared.c index a250e042f1d..c4b8a088012 100644 --- a/core/arch/instr_shared.c +++ b/core/arch/instr_shared.c @@ -3129,7 +3129,7 @@ instr_raw_is_tls_spill(byte *pc, reg_id_t reg, ushort offs) /* 0x1e for ebx, 0x0e for ecx, 0x06 for eax */ *(pc+2) == MODRM_BYTE(0/*mod*/, reg_get_bits(reg), 6/*rm*/) && *((uint*)(pc+4)) == os_tls_offset(offs)); -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */ ASSERT_NOT_IMPLEMENTED(false); return false; @@ -3168,7 +3168,7 @@ instr_check_tls_spill_restore(instr_t *instr, bool *spill, reg_id_t *reg, int *o opnd_is_far_base_disp(memop) && opnd_get_segment(memop) == SEG_TLS && opnd_is_abs_base_disp(memop) -#elif defined (ARM) || defined(AARCH64) +#elif defined(AARCHXX) opnd_is_base_disp(memop) && opnd_get_base(memop) == dr_reg_stolen && opnd_get_index(memop) == DR_REG_NULL @@ -3223,7 +3223,7 @@ instr_is_tls_xcx_spill(instr_t *instr) REG_ECX, MANGLE_XCX_SPILL_SLOT); } else return instr_is_tls_spill(instr, REG_ECX, MANGLE_XCX_SPILL_SLOT); -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */ ASSERT_NOT_IMPLEMENTED(false); return false; diff --git a/core/arch/interp.c b/core/arch/interp.c index 834218d1162..ffe3d8347f3 100644 --- a/core/arch/interp.c +++ b/core/arch/interp.c @@ -2515,7 +2515,7 @@ bb_process_IAT_convertible_indjmp(dcontext_t *dcontext, build_bb_t *bb, bb->exit_target = target; *elide_continue = false; /* matching, but should stop bb */ return true; /* matching */ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */ ASSERT_NOT_IMPLEMENTED(false); return false; @@ -2626,7 +2626,7 @@ bb_process_IAT_convertible_indcall(dcontext_t *dcontext, build_bb_t *bb, */ *elide_continue = false; /* matching, but should stop bb */ return true; /* converted indirect to direct */ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */ ASSERT_NOT_IMPLEMENTED(false); return false; @@ -5724,7 +5724,7 @@ instr_is_trace_cmp(dcontext_t *dcontext, instr_t *inst) instr_get_opcode(inst) == OP_jmp # endif ; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */ ASSERT_NOT_IMPLEMENTED(DYNAMO_OPTION(disable_traces)); return false; diff --git a/core/arch/mangle_shared.c b/core/arch/mangle_shared.c index 56dae816a70..0a9c7137867 100644 --- a/core/arch/mangle_shared.c +++ b/core/arch/mangle_shared.c @@ -822,7 +822,7 @@ mangle(dcontext_t *dcontext, instrlist_t *ilist, uint *flags INOUT, } #endif /* X64 || ARM */ -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX if (!instr_is_meta(instr) && instr_reads_thread_register(instr)) { next_instr = mangle_reads_thread_register(dcontext, ilist, instr, next_instr); diff --git a/core/arch/opnd.h b/core/arch/opnd.h index 5ad56650738..dd13d5c42b0 100644 --- a/core/arch/opnd.h +++ b/core/arch/opnd.h @@ -180,7 +180,7 @@ enum { DR_REG_YMM12,DR_REG_YMM13,DR_REG_YMM14,DR_REG_YMM15, /****************************************************************************/ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) DR_REG_INVALID, /**< Sentinel value indicating an invalid register. */ # ifdef AARCH64 @@ -470,7 +470,7 @@ extern const reg_id_t dr_reg_fixer[]; #ifdef X86 # define REG_START_SPILL DR_REG_XAX # define REG_STOP_SPILL DR_REG_XDI -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* We only normally use r0-r3 but we support more in translation code */ # define REG_START_SPILL DR_REG_R0 # define REG_STOP_SPILL DR_REG_R10 /* r10 might be used in syscall mangling */ @@ -2254,7 +2254,7 @@ enum { REGPARM_END_ALIGN = sizeof(XSP_SZ), # endif # endif /* 64/32 */ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) REGPARM_0 = DR_REG_R0, REGPARM_1 = DR_REG_R1, REGPARM_2 = DR_REG_R2, @@ -2278,7 +2278,7 @@ extern const reg_id_t regparms[]; /* arch-specific */ uint opnd_immed_float_arch(uint opcode); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX # define DR_REG_STOLEN_MIN DR_REG_R8 /* no syscall regs */ # define DR_REG_STOLEN_MAX IF_X64_ELSE(DR_REG_X29, DR_REG_R12) /* DR's stolen register for TLS access */ diff --git a/core/arch/opnd_shared.c b/core/arch/opnd_shared.c index fdd77e83dae..a08415bfd64 100644 --- a/core/arch/opnd_shared.c +++ b/core/arch/opnd_shared.c @@ -968,7 +968,7 @@ const reg_id_t regparms[] = { REGPARM_4, REGPARM_5, # endif # endif -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) REGPARM_0, REGPARM_1, REGPARM_2, REGPARM_3, # ifdef X64 REGPARM_4, REGPARM_5, REGPARM_6, REGPARM_7, @@ -1053,7 +1053,7 @@ opnd_replace_reg(opnd_t *opnd, reg_id_t old_reg, reg_id_t new_reg) reg_id_t b = (old_reg == ob) ? new_reg : ob; reg_id_t i = (old_reg == oi) ? new_reg : oi; int d = opnd_get_disp(*opnd); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX uint amount; dr_shift_type_t shift = opnd_get_index_shift(*opnd, &amount); dr_opnd_flags_t flags = opnd_get_flags(*opnd); @@ -1853,7 +1853,7 @@ reg_32_to_16(reg_id_t reg) CLIENT_ASSERT(reg >= REG_START_32 && reg <= REG_STOP_32, "reg_32_to_16: passed non-32-bit reg"); return (reg - REG_START_32) + REG_START_16; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) CLIENT_ASSERT(false, "reg_32_to_16 not supported on ARM"); return REG_NULL; #endif @@ -1875,7 +1875,7 @@ reg_32_to_8(reg_id_t reg) # endif } return r8; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) CLIENT_ASSERT(false, "reg_32_to_8 not supported on ARM"); return REG_NULL; #endif @@ -2056,7 +2056,7 @@ reg_get_size(reg_id_t reg) /* i#176 add reg size handling for floating point registers */ if (reg >= REG_START_FLOAT && reg <= REG_STOP_FLOAT) return OPSZ_10; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) if (reg >= DR_REG_Q0 && reg <= DR_REG_Q31) return OPSZ_16; if (reg >= DR_REG_D0 && reg <= DR_REG_D31) diff --git a/core/lib/globals_shared.h b/core/lib/globals_shared.h index 52805f6e1a3..7b7e1f6f56c 100644 --- a/core/lib/globals_shared.h +++ b/core/lib/globals_shared.h @@ -1783,7 +1783,7 @@ typedef union _dr_ymm_t { reg_t reg[IF_X64_ELSE(4,8)]; /**< Representation as 4 or 8 registers. */ } dr_ymm_t; -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /** * 128-bit ARM SIMD Vn register. * In AArch64, align to 16 bytes for better performance. diff --git a/core/lib/instrument.c b/core/lib/instrument.c index b062585fb75..3f540cd5ef0 100644 --- a/core/lib/instrument.c +++ b/core/lib/instrument.c @@ -5320,7 +5320,7 @@ static const reg_id_t SPILL_SLOT_MC_REG[NUM_SPILL_SLOTS - NUM_TLS_SPILL_SLOTS] = REG_R15, REG_R14, REG_R13, REG_R12, REG_R11, REG_R10, REG_R9, REG_R8, # endif REG_XDI, REG_XSI, REG_XBP, REG_XDX, REG_XCX, REG_XBX -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) DR_REG_R6, DR_REG_R5, DR_REG_R4, DR_REG_R3, DR_REG_R2, DR_REG_R1 #endif /* X86/ARM */ }; diff --git a/core/lib/mcxtx.h b/core/lib/mcxtx.h index 09faa237291..a9cce197ad4 100644 --- a/core/lib/mcxtx.h +++ b/core/lib/mcxtx.h @@ -39,7 +39,7 @@ */ /* START INCLUDE */ -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX # ifdef AVOID_API_EXPORT /* FIXME: have special comment syntax instead of bogus ifdef to * get genapi to strip out internal-only comments? */ diff --git a/core/optionsx.h b/core/optionsx.h index 7393f66f0df..dc96592fea9 100644 --- a/core/optionsx.h +++ b/core/optionsx.h @@ -570,7 +570,7 @@ "Optimize ibl code with extra 64-bit registers in x86_to_x64 mode.") #endif -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* we only allow register between r8 and r12(A32)/r29(A64) to be used */ OPTION_DEFAULT_INTERNAL(uint, steal_reg, IF_X64_ELSE(28/*r28*/, 10/*r10*/), "the register stolen/used by DynamoRIO") diff --git a/core/os_shared.h b/core/os_shared.h index 27f6f330ce8..be34a4e3947 100644 --- a/core/os_shared.h +++ b/core/os_shared.h @@ -1017,7 +1017,7 @@ enum { JMP_ABS_MEM_IND64_MODRM = 0x25, # endif }; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) enum { /* FIXME i#1551, i#1569: this is for A32 for now to get things compiling */ JMP_REL32_OPCODE = 0xec000000, diff --git a/core/unix/injector.c b/core/unix/injector.c index f78f5d3be44..fec0b250add 100644 --- a/core/unix/injector.c +++ b/core/unix/injector.c @@ -1465,7 +1465,7 @@ inject_ptrace(dr_inject_info_t *info, const char *library_path) strncpy(args.home_dir, getenv("HOME"), BUFFER_SIZE_ELEMENTS(args.home_dir)); NULL_TERMINATE_BUFFER(args.home_dir); -#if defined(X86) || defined(ARM) || defined(AARCH64) +#if defined(X86) || defined(AARCHXX) regs.REG_SP_FIELD -= REDZONE_SIZE; /* Need to preserve x64 red zone. */ regs.REG_SP_FIELD -= sizeof(args); /* Allocate space for args. */ regs.REG_SP_FIELD = ALIGN_BACKWARD(regs.REG_SP_FIELD, REGPARM_END_ALIGN); diff --git a/core/unix/loader_linux.c b/core/unix/loader_linux.c index 664f0d2ca22..73a6019515c 100644 --- a/core/unix/loader_linux.c +++ b/core/unix/loader_linux.c @@ -162,7 +162,7 @@ typedef struct _tcb_head_t { #ifdef X86 # define TLS_PRE_TCB_SIZE 0 -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1569: This may be wrong for AArch64! */ /* Data structure to match libc pthread. * GDB reads some slot in TLS, which is pid/tid of pthread, so we must make sure @@ -187,7 +187,7 @@ typedef struct _dr_pthread_t { * (i#46), we need to copy this data from before the thread pointer. */ # define APP_LIBC_TLS_SIZE 0x400 -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: investigate the difference between ARM and X86 on TLS. * On ARM, it seems that TLS variables are not put before the thread pointer * as they are on X86. @@ -254,7 +254,7 @@ privload_tls_init(void *app_tp) __FUNCTION__, app_tp); dr_tp = heap_mmap(max_client_tls_size); ASSERT(APP_LIBC_TLS_SIZE + TLS_PRE_TCB_SIZE + tcb_size <= max_client_tls_size); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* GDB reads some pthread members (e.g., pid, tid), so we must make sure * the size and member locations match to avoid gdb crash. */ @@ -284,7 +284,7 @@ privload_tls_init(void *app_tp) LOG(GLOBAL, LOG_LOADER, 2, "%s: read failed, tcb was 0x%lx bytes " "instead of 0x%lx\n", __FUNCTION__, tls_bytes_read - APP_LIBC_TLS_SIZE, tcb_size); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX } else { dr_pthread_t *dp = (dr_pthread_t *)(dr_tp - APP_LIBC_TLS_SIZE - TLS_PRE_TCB_SIZE); @@ -303,7 +303,7 @@ privload_tls_init(void *app_tp) dr_tcb->self = dr_tcb; /* i#555: replace app's vsyscall with DR's int0x80 syscall */ dr_tcb->sysinfo = (ptr_uint_t)client_int_syscall; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) dr_tcb->dtv = NULL; dr_tcb->private = NULL; #endif diff --git a/core/unix/native_elf.c b/core/unix/native_elf.c index 16eccf1de8c..c2f1ead2557 100644 --- a/core/unix/native_elf.c +++ b/core/unix/native_elf.c @@ -150,7 +150,7 @@ find_dl_fixup(dcontext_t *dcontext, app_pc resolver) } instr_free(dcontext, &instr); return fixup; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551, i#1569: NYI on ARM/AArch64 */ ASSERT_NOT_IMPLEMENTED(false); return NULL; diff --git a/core/unix/os.c b/core/unix/os.c index 55a8b7f001c..025d2aec788 100644 --- a/core/unix/os.c +++ b/core/unix/os.c @@ -1327,7 +1327,7 @@ os_timeout(int time_in_milliseconds) asm("movzw"IF_X64_ELSE("q","l")" %0, %%"ASM_XAX : : "m"((offs)) : ASM_XAX); \ asm("mov %"ASM_SEG":(%%"ASM_XAX"), %%"ASM_XAX : : : ASM_XAX); \ asm("mov %%"ASM_XAX", %0" : "=m"((var)) : : ASM_XAX); -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define WRITE_TLS_SLOT_IMM(imm, var) \ __asm__ __volatile__( \ READ_TP_TO_R3 \ @@ -1389,7 +1389,7 @@ is_thread_tls_initialized(void) } # endif return false; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) byte **dr_tls_base_addr; if (tls_global_type == TLS_TYPE_NONE) return false; @@ -1466,7 +1466,7 @@ get_os_tls_from_dc(dcontext_t *dcontext) return (os_local_state_t *)(local_state - offsetof(os_local_state_t, state)); } -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX bool os_set_app_tls_base(dcontext_t *dcontext, reg_id_t reg, void *base) { @@ -1575,7 +1575,7 @@ get_segment_base(uint seg) # else return (byte *) POINTER_MAX; #endif /* HAVE_TLS */ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* XXX i#1551: should we rename/refactor to avoid "segment"? */ return (byte *) read_thread_register(seg); #endif @@ -2172,7 +2172,7 @@ os_should_swap_state(void) /* -private_loader currently implies -mangle_app_seg, but let's be safe. */ return (INTERNAL_OPTION(mangle_app_seg) && IF_CLIENT_INTERFACE_ELSE(INTERNAL_OPTION(private_loader), false)); -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1582: this should return true, but there is a lot of complexity * getting os_switch_seg_to_context() to do the right then when called * at main thread init, secondary thread init, early and late injection, @@ -4717,7 +4717,7 @@ const reg_id_t syscall_regparms[MAX_SYSCALL_ARGS] = { DR_REG_EDI, DR_REG_EBP # endif /* 64/32-bit */ -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) DR_REG_R0, DR_REG_R1, DR_REG_R2, diff --git a/core/unix/os_exports.h b/core/unix/os_exports.h index 41aa3a3a1bf..2aad8bad36e 100644 --- a/core/unix/os_exports.h +++ b/core/unix/os_exports.h @@ -83,7 +83,7 @@ # define LIB_SEG_TLS SEG_GS /* libc+loader tls */ # define LIB_ASM_SEG "%gs" # endif -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* The SEG_TLS is not preserved by all kernels (older 32-bit, or all 64-bit), so we * end up having to steal the app library TPID register for priv lib use. * When in DR state, we steal a field inside the priv lib TLS to store the DR base. @@ -104,7 +104,7 @@ #define DR_REG_SYSNUM IF_X86_ELSE(REG_EAX/* not XAX */, DR_REG_R7) -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX # ifdef ANDROID /* We have our own slot at the end of our instance of Android's pthread_internal_t */ # ifdef AARCH64 @@ -212,7 +212,7 @@ bool disable_env(const char *name); # define DECLARE_DATA_SECTION(name, wx) \ asm(".section "name", \"a"wx"\", @progbits"); \ asm(".align 0x1000"); -# elif defined(ARM) || defined(AARCH64) +# elif defined(AARCHXX) # define DECLARE_DATA_SECTION(name, wx) \ asm(".section "name", \"a"wx"\""); \ asm(".align 12"); /* 2^12 */ @@ -236,7 +236,7 @@ bool disable_env(const char *name); asm(".section .data"); \ asm(".align 0x1000"); \ asm(".text"); -# elif defined(ARM) || defined(AARCH64) +# elif defined(AARCHXX) # define END_DATA_SECTION_DECLARATIONS() \ asm(".section .data"); \ asm(".align 12"); \ @@ -364,7 +364,7 @@ get_clone_record_app_xsp(void *record); byte * get_clone_record_dstack(void *record); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX reg_t get_clone_record_stolen_value(void *record); diff --git a/core/unix/os_private.h b/core/unix/os_private.h index 592a06cac08..c5bc9053fd6 100644 --- a/core/unix/os_private.h +++ b/core/unix/os_private.h @@ -183,7 +183,7 @@ void os_thread_take_over(priv_mcontext_t *mc); void *os_get_priv_tls_base(dcontext_t *dcontext, reg_id_t seg); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX bool os_set_app_tls_base(dcontext_t *dcontext, reg_id_t reg, void *base); #endif diff --git a/core/unix/signal.c b/core/unix/signal.c index 381b5e54e87..2b3227886e9 100644 --- a/core/unix/signal.c +++ b/core/unix/signal.c @@ -208,7 +208,7 @@ typedef struct _clone_record_t { thread_sig_info_t info; thread_sig_info_t *parent_info; void *pcprofile_info; -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* To ensure we have the right value as of the point of the clone, we * store it here (we'll have races if we try to get it during new thread * init). @@ -561,7 +561,7 @@ create_clone_record(dcontext_t *dcontext, reg_t *app_thread_xsp) record->info = *((thread_sig_info_t *)dcontext->signal_field); record->parent_info = (thread_sig_info_t *) dcontext->signal_field; record->pcprofile_info = dcontext->pcprofile_field; -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX record->app_stolen_value = get_stolen_reg_val(get_mcontext(dcontext)); # ifndef AARCH64 record->isa_mode = dr_get_isa_mode(dcontext); @@ -672,7 +672,7 @@ get_clone_record_dstack(void *record) return ((clone_record_t *) record)->dstack; } -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX reg_t get_clone_record_stolen_value(void *record) { @@ -2072,7 +2072,7 @@ mcontext_to_ucontext(kernel_ucontext_t *uc, priv_mcontext_t *mc) mcontext_to_sigcontext(&sc_full, mc); } -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX static void set_sigcxt_stolen_reg(sigcontext_t *sc, reg_t val) { @@ -2812,7 +2812,7 @@ transfer_from_sig_handler_to_fcache_return(dcontext_t *dcontext, sigcontext_t *s * still go to the private fcache_return for simplicity. */ sc->SC_XIP = (ptr_uint_t) fcache_return_routine(dcontext); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* We do not have to set dr_reg_stolen in dcontext's mcontext here * because dcontext's mcontext is stale and we used the mcontext * created from recreate_app_state_internal with the original sigcontext. @@ -3260,7 +3260,7 @@ adjust_syscall_for_restart(dcontext_t *dcontext, thread_sig_info_t *info, int si } #ifdef X86 sc->SC_SYSNUM_REG = sysnum; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* We just need to restore the app's arg to the syscall into r0, which * the kernel clobbered with -EINTR. We stored r0 into TLS. */ @@ -4532,7 +4532,7 @@ execute_handler_from_cache(dcontext_t *dcontext, int sig, sigframe_rt_t *our_fra sc->SC_XDI = sig; sc->SC_XSI = (reg_t) &((sigframe_rt_t *)xsp)->info; sc->SC_XDX = (reg_t) &((sigframe_rt_t *)xsp)->uc; -#elif defined(AARCH64) || defined(ARM) +#elif defined(AARCHXX) sc->SC_R0 = sig; if (IS_RT_FOR_APP(info, sig)) { sc->SC_R1 = (reg_t) &((sigframe_rt_t *)xsp)->info; @@ -4745,7 +4745,7 @@ execute_handler_from_dispatch(dcontext_t *dcontext, int sig) mcontext->xdi = sig; mcontext->xsi = (reg_t) &((sigframe_rt_t *)xsp)->info; mcontext->xdx = (reg_t) &((sigframe_rt_t *)xsp)->uc; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) mcontext->r0 = sig; if (IS_RT_FOR_APP(info, sig)) { mcontext->r1 = (reg_t) &((sigframe_rt_t *)xsp)->info; @@ -5310,7 +5310,7 @@ handle_sigreturn(dcontext_t *dcontext, void *ucxt_param, int style) * look like whatever would happen to the app... */ ASSERT((app_pc)sc->SC_XIP != next_pc); -# if defined(ARM) || defined(AARCH64) +# ifdef AARCHXX set_stolen_reg_val(get_mcontext(dcontext), get_sigcxt_stolen_reg(sc)); set_sigcxt_stolen_reg(sc, (reg_t) *get_dr_tls_base_addr()); # ifdef AARCH64 @@ -6098,7 +6098,7 @@ handle_suspend_signal(dcontext_t *dcontext, kernel_ucontext_t *ucxt) asm("movl $1,(%"ASM_XAX")"); asm("jmp dynamorio_futex_wake_and_exit"); # endif -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) asm("ldr "ASM_R0", %0" : : "m"(term)); asm("mov "ASM_R1", #1"); asm("str "ASM_R1",["ASM_R0"]"); diff --git a/core/unix/signal_private.h b/core/unix/signal_private.h index c506fad5c1b..0f08f3d229d 100644 --- a/core/unix/signal_private.h +++ b/core/unix/signal_private.h @@ -243,7 +243,7 @@ typedef struct rt_sigframe { char retcode[RETCODE_SIZE]; # endif /* In 2.6.28+, fpstate/xstate goes here */ -# elif defined(ARM) || defined(AARCH64) +# elif defined(AARCHXX) siginfo_t info; kernel_ucontext_t uc; char retcode[RETCODE_SIZE]; diff --git a/core/unix/tls.h b/core/unix/tls.h index 3e99187356f..0c46b48654a 100644 --- a/core/unix/tls.h +++ b/core/unix/tls.h @@ -106,7 +106,7 @@ typedef struct _our_modify_ldt_t { ASSERT(sizeof(val) == sizeof(reg_t)); \ asm volatile("mov %0,%%"ASM_XAX"; mov %%"ASM_XAX", %"LIB_ASM_SEG";" \ : : "m" ((val)) : ASM_XAX); -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) # define WRITE_DR_SEG(val) ASSERT_NOT_REACHED() # define WRITE_LIB_SEG(val) ASSERT_NOT_REACHED() # define TLS_SLOT_VAL_EXITED ((byte *)PTR_UINT_MINUS_1) @@ -131,7 +131,7 @@ read_thread_register(reg_id_t reg) * is_segment_register_initialized(). */ sel &= 0xffff; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) ptr_uint_t sel; if (reg == DR_REG_TPIDRURO) { IF_X64_ELSE({ @@ -243,7 +243,7 @@ tls_thread_init(os_local_state_t *os_tls, byte *segment); void tls_thread_free(tls_type_t tls_type, int index); -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX byte ** get_dr_tls_base_addr(void); #endif diff --git a/core/unix/tls_linux_aarchxx.c b/core/unix/tls_linux_aarchxx.c index 7835fcd8c2a..2b8a10bc433 100644 --- a/core/unix/tls_linux_aarchxx.c +++ b/core/unix/tls_linux_aarchxx.c @@ -45,7 +45,7 @@ # error Linux-only #endif -#if !(defined(ARM) || defined(AARCH64)) +#ifndef AARCHXX # error ARM/AArch64-only #endif diff --git a/ext/drreg/drreg.c b/ext/drreg/drreg.c index 4c125eb45bb..2e3cc4a9bbd 100644 --- a/ext/drreg/drreg.c +++ b/ext/drreg/drreg.c @@ -1212,7 +1212,7 @@ drreg_event_restore_state(void *drcontext, bool restore_memory, if (spilled_to_aflags < MAX_SPILLS) { reg_t val = get_spilled_value(drcontext, spilled_to_aflags); reg_t newval = info->mcontext->xflags; -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX newval &= ~(EFLAGS_ARITH); newval |= val; #elif defined(X86) diff --git a/ext/drutil/drutil.c b/ext/drutil/drutil.c index 01632de5b61..27ac2f11ade 100644 --- a/ext/drutil/drutil.c +++ b/ext/drutil/drutil.c @@ -95,7 +95,7 @@ drutil_exit(void) static bool drutil_insert_get_mem_addr_x86(void *drcontext, instrlist_t *bb, instr_t *where, opnd_t memref, reg_id_t dst, reg_id_t scratch); -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) static bool drutil_insert_get_mem_addr_arm(void *drcontext, instrlist_t *bb, instr_t *where, opnd_t memref, reg_id_t dst, reg_id_t scratch); @@ -119,7 +119,7 @@ drutil_insert_get_mem_addr(void *drcontext, instrlist_t *bb, instr_t *where, { #ifdef X86 return drutil_insert_get_mem_addr_x86(drcontext, bb, where, memref, dst, scratch); -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) return drutil_insert_get_mem_addr_arm(drcontext, bb, where, memref, dst, scratch); #endif } @@ -221,7 +221,7 @@ drutil_insert_get_mem_addr_x86(void *drcontext, instrlist_t *bb, instr_t *where, } return true; } -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) static bool instr_has_opnd(instr_t *instr, opnd_t opnd) { diff --git a/ext/drwrap/drwrap.c b/ext/drwrap/drwrap.c index fd51d80d9f8..81479904976 100644 --- a/ext/drwrap/drwrap.c +++ b/ext/drwrap/drwrap.c @@ -559,7 +559,7 @@ drwrap_get_mcontext_internal(drwrap_context_t *wrapcxt, dr_mcontext_flags_t flag * trap flag or other flags so instead of zeroing we copy cur flags * (xref i#806). */ -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX wrapcxt->mc->xflags = 0; /*0 is fine for ARM */ #else # ifdef WINDOWS @@ -625,7 +625,7 @@ drwrap_arg_addr(drwrap_context_t *wrapcxt, int arg) drwrap_get_mcontext_internal(wrapcxt, DR_MC_INTEGER); /* already have xsp */ switch (wrapcxt->callconv) { -#if defined(ARM) || defined(AARCH64) /* registers are platform-exclusive */ +#if defined(AARCHXX) /* registers are platform-exclusive */ case DRWRAP_CALLCONV_ARM: switch (arg) { case 0: return &wrapcxt->mc->r0; @@ -1270,7 +1270,7 @@ drwrap_replace_native_push_retaddr(void *drcontext, instrlist_t *bb, app_pc pc, ptr_int_t pushval, opnd_size_t stacksz _IF_X86_64(bool x86)) { -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX instr_t *mov1, *mov2; instrlist_insert_mov_immed_ptrsz(drcontext, pushval, opnd_create_reg(DR_REG_LR), bb, NULL, &mov1, &mov2); diff --git a/ext/drx/drx.c b/ext/drx/drx.c index d157c617189..c268ad6cbec 100644 --- a/ext/drx/drx.c +++ b/ext/drx/drx.c @@ -179,7 +179,7 @@ drx_aflags_are_dead(instr_t *where) * INSTRUMENTATION */ -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX /* XXX i#1603: add liveness analysis and pick dead regs */ # define SCRATCH_REG0 DR_REG_R0 # define SCRATCH_REG1 DR_REG_R1 @@ -236,7 +236,7 @@ drx_save_arith_flags(void *drcontext, instrlist_t *ilist, instr_t *where, instr = INSTR_CREATE_setcc(drcontext, OP_seto, opnd_create_reg(DR_REG_AL)); MINSERT(ilist, where, instr); } -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) ASSERT(reg >= DR_REG_START_GPR && reg <= DR_REG_STOP_GPR, "reg must be a GPR"); if (save_reg) { ASSERT(slot >= SPILL_SLOT_1 && slot <= SPILL_SLOT_MAX, @@ -295,7 +295,7 @@ drx_restore_arith_flags(void *drcontext, instrlist_t *ilist, instr_t *where, dr_restore_reg(drcontext, ilist, where, DR_REG_XAX, slot); } } -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) ASSERT(reg >= DR_REG_START_GPR && reg <= DR_REG_STOP_GPR, "reg must be a GPR"); instr = INSTR_CREATE_mrs(drcontext, opnd_create_reg(reg), opnd_create_reg(DR_REG_CPSR)); @@ -390,7 +390,7 @@ drx_insert_counter_update(void *drcontext, instrlist_t *ilist, instr_t *where, bool use_drreg = false; #ifdef X86 bool save_aflags = true; -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) bool save_regs = true; reg_id_t reg1, reg2; #endif @@ -477,7 +477,7 @@ drx_insert_counter_update(void *drcontext, instrlist_t *ilist, instr_t *where, slot, DR_REG_NULL); } } -#elif defined(ARM) || defined(AARCH64) +#elif defined(AARCHXX) /* FIXME i#1551: implement 64-bit counter support */ ASSERT(!is_64, "DRX_COUNTER_64BIT is not implemented"); diff --git a/suite/tests/security-common/ret_noncall_trace.c b/suite/tests/security-common/ret_noncall_trace.c index ca7a705e606..1c12776c42c 100644 --- a/suite/tests/security-common/ret_noncall_trace.c +++ b/suite/tests/security-common/ret_noncall_trace.c @@ -52,7 +52,7 @@ #define INNER_LOOP_COUNT 4 #define MAX_SUM (NUM_TIMES * (NUM_TIMES + 1) / 2 * INNER_LOOP_COUNT) -#if defined(ARM) || defined(AARCH64) +#ifdef AARCHXX # define OFFSET 8 #elif defined(X86) # define OFFSET 6 diff --git a/suite/tests/tools.h b/suite/tests/tools.h index fdad37ffbc7..38145651e2e 100644 --- a/suite/tests/tools.h +++ b/suite/tests/tools.h @@ -211,7 +211,7 @@ intercept_signal(int sig, handler_3_t handler, bool sigstack); # else # define NOP_NOP_CALL(tgt) asm("nop\n nop\n call " #tgt) # endif -# elif defined(ARM) || defined(AARCH64) +# elif defined(AARCHXX) /* Make sure to mark LR/X30 as clobbered to avoid functions like * client-interface/call-retarget.c:main() being interpreted as a leaf * function that does not need the link register preserved.