diff --git a/core/arch/aarch64/codec.c b/core/arch/aarch64/codec.c
index bf3b05318f5..84c9a27ce3b 100644
--- a/core/arch/aarch64/codec.c
+++ b/core/arch/aarch64/codec.c
@@ -1966,6 +1966,26 @@ encode_opnd_s10(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
     return encode_opnd_vector_reg(10, 2, opnd, enc_out);
 }
 
+/* isz: Vector element width for SIMD instructions. */
+
+static inline bool
+decode_opnd_isz(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
+{
+    uint bits = enc >> 22 & 3;
+    *opnd = opnd_create_immed_int(bits, OPSZ_2b);
+    return true;
+}
+
+static inline bool
+encode_opnd_isz(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
+{
+    ptr_int_t val = opnd_get_immed_int(opnd);
+    if ( val < 0 || val > 3)
+        return false;
+    *enc_out = val << 22;
+    return true;
+}
+
 /* shift3: shift type for ADD/SUB: LSL, LSR or ASR */
 
 static inline bool
diff --git a/core/arch/aarch64/codec.txt b/core/arch/aarch64/codec.txt
index f697e6d3e36..af184d2bbda 100644
--- a/core/arch/aarch64/codec.txt
+++ b/core/arch/aarch64/codec.txt
@@ -131,6 +131,7 @@
 ---------?x---------x-----------  vindex_SD  # Index for vector with single or double
                                              # elements, depending on bit 22 (sz)
 ?--------xx---------------------  imm16sh    # shift for MOVK/... (immediate); checks 31
+--------xx----------------------  isz        # element size of a vector register (8<<isz)
 --------xx----------------------  shift3     # shift type for add/sub (shifted register)
 --------xx----------------------  shift4     # shift type for logical (shifted register)
 ??---?--xxxxxxxxxxxxxxxxxxx-----  memlit     # load literal, gets size from 31:30 and 26
@@ -957,6 +958,10 @@ x101101011000000000101xxxxxxxxxx  cls     wx0 : wx5
 1101101011000000000011xxxxxxxxxx  rev     x0 : x5
 
 # Data Processing - Scalar Floating-Point and Advanced SIMD
+
+# ADD
+0x001110xx1xxxxx100001xxxxxxxxxx     add dq0 : dq5 dq16 isz
+
 # FMOV (general) GPR to FP reg
 0001111011100111000000xxxxxxxxxx     fmov h0 : w5 # Armv8.2
 0001111000100111000000xxxxxxxxxx     fmov s0 : w5
diff --git a/core/arch/aarch64/instr_create.h b/core/arch/aarch64/instr_create.h
index 9ce53310012..4192ce81228 100644
--- a/core/arch/aarch64/instr_create.h
+++ b/core/arch/aarch64/instr_create.h
@@ -41,6 +41,30 @@
 /* DR_API EXPORT TOFILE dr_ir_macros_aarch64.h */
 /* DR_API EXPORT BEGIN */
 
+/**
+ * Used in an additional immediate source operand to a vector operation, denotes
+ * 8 bit vector element width. See \ref sec_IR_AArch64.
+ */
+#define ISZ_BYTE 0
+
+/**
+ * Used in an additional immediate source operand to a vector operation, denotes
+ * 16 bit vector element width. See \ref sec_IR_AArch64.
+ */
+#define ISZ_HALF 1
+
+/**
+ * Used in an additional immediate source operand to a vector operation, denotes
+ * 32 bit vector element width. See \ref sec_IR_AArch64.
+ */
+#define ISZ_SINGLE 2
+
+/**
+ * Used in an additional immediate source operand to a vector operation, denotes
+ * 64 bit vector element width. See \ref sec_IR_AArch64.
+ */
+#define ISZ_DOUBLE 3
+
 /**
  * Used in an additional immediate source operand to a vector operation, denotes
  * half-precision floating point vector elements. See \ref sec_IR_AArch64.
diff --git a/suite/tests/api/dis-a64.txt b/suite/tests/api/dis-a64.txt
index a9ce274a60d..5ad82f32b2a 100644
--- a/suite/tests/api/dis-a64.txt
+++ b/suite/tests/api/dis-a64.txt
@@ -1561,6 +1561,16 @@ fd3fffff : str    d31, [sp,#32760]        : str    %d31 -> +0x7ff8(%sp)[8byte]
 fd481041 : ldr    d1, [x2,#4128]          : ldr    +0x1020(%x2)[8byte] -> %d1
 fd7fffff : ldr    d31, [sp,#32760]        : ldr    +0x7ff8(%sp)[8byte] -> %d31
 
+
+# ADD (vector)
+4e2c856a : add v10.16b, v11.16b, v12.16b : add    %q11 %q12 $0x00 -> %q10
+0e2584a5 : add v5.8b, v5.8b, v5.8b       : add    %d5 %d5 $0x00 -> %d5
+4e7f87c3 : add v3.8h, v30.8h, v31.8h     : add    %q30 %q31 $0x01 -> %q3
+0e7f87c3 : add v3.4h, v30.4h, v31.4h     : add    %d30 %d31 $0x01 -> %d3
+4ebd8633 : add v19.4s, v17.4s, v29.4s    : add    %q17 %q29 $0x02 -> %q19
+0ebd8633 : add v19.2s, v17.2s, v29.2s    : add    %d17 %d29 $0x02 -> %d19
+4ee9852d : add v13.2d, v9.2d, v9.2d      : add    %q9 %q9 $0x03 -> %q13
+
 # FMOV (general) GPR to FP reg
 1ee70220 : fmov  h0, w17 : fmov   %w17 -> %h0
 1e27012a : fmov  s10, w9 : fmov   %w9 -> %s10