diff --git a/core/ir/aarch64/codec.c b/core/ir/aarch64/codec.c index 180d6354aa0..14e48f46196 100644 --- a/core/ir/aarch64/codec.c +++ b/core/ir/aarch64/codec.c @@ -5055,25 +5055,6 @@ encode_opnds_tbz(byte *pc, instr_t *instr, uint enc, decode_info_t *di) return ENCFAIL; } -/* Function(s) used by new codec. */ - -/* Halfword and short element size. This is the same as encode_opnd_hs_sz() - * except that the shift of the size value to place it in the correct part of - * the encoding is not done here. That placement is instruction specific and so - * is done by each instruction's enc_*() function. In general the positioning - * of operand encodings in instruction encodings should be done by each - * instruction's encoding function, rather than an operand's encoding function. - */ -static inline bool -get_el_hs_sz(OUT uint *elsz_out, opnd_t opnd) -{ - ptr_int_t val = opnd_get_immed_int(opnd); - if (val < 1 || val > 2) - return false; - *elsz_out = val; - return true; -} - /******************************************************************************/ /* Include automatically generated decoder and encoder files. Decode and encode @@ -5086,13 +5067,11 @@ get_el_hs_sz(OUT uint *elsz_out, opnd_t opnd) #include "opnd_encode_funcs.h" #include "decode_gen_sve.h" #include "decode_gen_v82.h" -#include "decode_v81.h" -#include "decode_gen_v81.h" /* Redirects decoding to decode_v81.h */ +#include "decode_gen_v81.h" #include "decode_gen_v80.h" #include "encode_gen_sve.h" #include "encode_gen_v82.h" -#include "encode_v81.h" -#include "encode_gen_v81.h" /* Redirects encoding to encode_v81.h */ +#include "encode_gen_v81.h" #include "encode_gen_v80.h" /******************************************************************************/ diff --git a/core/ir/aarch64/codec.h b/core/ir/aarch64/codec.h index e44210464e5..119830a2480 100644 --- a/core/ir/aarch64/codec.h +++ b/core/ir/aarch64/codec.h @@ -51,32 +51,8 @@ decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr); uint encode_common(byte *pc, instr_t *i, decode_info_t *di); -/* Types and macros used by new codec. */ - -/* Bit extraction macro used extensively by automatically generated decoder and - * encoder functions. - */ #define BITS(_enc, bitmax, bitmin) \ ((((uint32)(_enc)) >> (bitmin)) & \ (uint32)((1ULL << ((bitmax) - (bitmin) + 1)) - 1ULL)) -/* Decoding is based on a key/value mapping (decode_map) where the key - * (enc_bits) is a unique set of up to 32 bits representing an instruction - * which is decoded by a function (decode_fn). - */ -typedef bool(decode_func_ptr)(dcontext_t *dcontext, uint enc, instr_t *instr); - -typedef struct dmap { - uint32 enc_bits; - decode_func_ptr *decode_fn; -} decode_map; - -/* Encoding function call-and-check macro used extensively by automatically - * generated encoder switch/case clauses. - */ -#define ENCODE_IF_MATCH(ENCODE_FUNCTION) \ - enc = ENCODE_FUNCTION(instr); \ - if (enc != ENCFAIL) \ - return enc; - #endif /* CODEC_H */ diff --git a/core/ir/aarch64/codec.py b/core/ir/aarch64/codec.py index 823fbee750b..c4f274bb47c 100755 --- a/core/ir/aarch64/codec.py +++ b/core/ir/aarch64/codec.py @@ -121,10 +121,6 @@ def generate_opndset_decoders(opndsettab, opndtab): FALLTHROUGH.values()] c += ['\n'] for name in sorted(opndsettab): - # Ignore dummy codec_*.txt entries. This suppresses generation of this - # decoder function for instructions handled by the new decoder. - if name == 'gen_00000000_00000000': - return '\n' opnd_set = opndsettab[name] (dsts, srcs) = (opnd_set.dsts, opnd_set.srcs) c += ['/* %s <- %s */' % (opnd_set.dsts, opnd_set.srcs)] @@ -259,17 +255,10 @@ def indent_append(text): c = ['static bool', 'decoder_' + curr_isa + '(uint enc, dcontext_t *dc, byte *pc, instr_t *instr)', '{'] - if curr_isa != 'v81': - gen(c, patterns, 1) - for opcode in FALLTHROUGH.values(): - c += [' %s' % opcode.decode_clause] - c += [' %s' % opcode.decode_function] - else: - # This calls a decode function for v8.1 instructions which uses a new - # method of decoding. - c += [' return decode_v81(enc, dc, pc, instr);'] - c.append('}') - return '\n'.join(c) + '\n' + gen(c, patterns, 1) + for opcode in FALLTHROUGH.values(): + c += [' %s' % opcode.decode_clause] + c += [' %s' % opcode.decode_function] # Call the next version of the decoder if defined. if next_isa != '': c.append(' return decoder_' + next_isa + '(enc, dc, pc, instr);') @@ -308,10 +297,6 @@ def make_enc(n, reordered, f, opndtab): def generate_opndset_encoders(opndsettab, opndtab): c = [] for name in sorted(opndsettab): - # Ignore dummy codec_*.txt entries. This suppresses generation of this - # encoder function for instructions handled by the new encoder. - if name == 'gen_00000000_00000000': - return '\n' os = opndsettab[name] (fixed, dsts, srcs, enc_order) = (os.fixed, os.dsts, os.srcs, os.enc_order) c += ['/* %s <- %s */' % (os.dsts, os.srcs)] @@ -360,17 +345,10 @@ def generate_encoder(patterns, opndsettab, opndtab, curr_isa, next_isa): case[mn].append(p) c += ['static uint', 'encoder_' + curr_isa + '(byte *pc, instr_t *instr, decode_info_t *di)', - '{'] - # This calls an encode function for v8.1 instructions which uses a new - # method of encoding. - if curr_isa == 'v81': - c += [' return encode_v81(pc, instr, di);'] - c.append('}') - return '\n'.join(c) + '\n' - else: - c += [' uint enc;', - ' (void)enc;', - ' switch (instr->opcode) {'] + '{', + ' uint enc;', + ' (void)enc;', + ' switch (instr->opcode) {'] def reorder_key(t): b, m, mn, f = t diff --git a/core/ir/aarch64/codec_v80.txt b/core/ir/aarch64/codec_v80.txt index b0353835904..85991f55f42 100644 --- a/core/ir/aarch64/codec_v80.txt +++ b/core/ir/aarch64/codec_v80.txt @@ -161,30 +161,6 @@ x1101010xx1xxxxxxxxxxxxxxxxxxxxx w 30 bics wx0 : wx5 wx16 1101011000011111000000xxxxx00000 n 35 br : x5 11010100001xxxxxxxxxxxxxxxx00000 n 36 brk : imm16 0x101110011xxxxx000111xxxxxxxxxx n 37 bsl dq0 : dq5 dq16 -10001000101xxxxx011111xxxxxxxxxx n 38 cas w16 mem0 : w16 w0 mem0 -11001000101xxxxx011111xxxxxxxxxx n 38 cas x16 mem0 : x16 x0 mem0 -10001000111xxxxx011111xxxxxxxxxx n 39 casa w16 mem0 : w16 w0 mem0 -11001000111xxxxx011111xxxxxxxxxx n 39 casa x16 mem0 : x16 x0 mem0 -00001000111xxxxx011111xxxxxxxxxx n 40 casab w16 mem0 : w16 w0 mem0 -01001000111xxxxx011111xxxxxxxxxx n 41 casah w16 mem0 : w16 w0 mem0 -10001000111xxxxx111111xxxxxxxxxx n 42 casal w16 mem0 : w16 w0 mem0 -11001000111xxxxx111111xxxxxxxxxx n 42 casal x16 mem0 : x16 x0 mem0 -00001000111xxxxx111111xxxxxxxxxx n 43 casalb w16 mem0 : w16 w0 mem0 -01001000111xxxxx111111xxxxxxxxxx n 44 casalh w16 mem0 : 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-00001000001xxxxx111111xxxxxxxxxx n 53 caspl w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p -01001000001xxxxx111111xxxxxxxxxx n 53 caspl x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p x0110101xxxxxxxxxxxxxxxxxxxxxxxx n 54 cbnz cbz x0110100xxxxxxxxxxxxxxxxxxxxxxxx n 55 cbz cbz x0111010010xxxxxxxxx00xxxxx0xxxx w 56 ccmn ccm @@ -548,22 +524,6 @@ x001111001011001xxxxxxxxxxxxxxxx n 126 fcvtzu wx0 : d5 scale 0x001101111xxxxx101001xxxxxxxxxx n 179 ld4 q0 q0p1 q0p2 q0p3 x5sp : memvs index3 x5sp x16immvs d_const_sz 0x001101011000001110xxxxxxxxxxxx n 180 ld4r dq0 dq0p1 dq0p2 dq0p3 : memvr vmsz 0x001101111xxxxx1110xxxxxxxxxxxx n 180 ld4r dq0 dq0p1 dq0p2 dq0p3 x5sp : memvr x5sp x16immvr vmsz -10111000001xxxxx000000xxxxxxxxxx n 181 ldadd w0 mem0 : w16 mem0 -11111000001xxxxx000000xxxxxxxxxx n 181 ldadd x0 mem0 : x16 mem0 -10111000101xxxxx000000xxxxxxxxxx n 182 ldadda w0 mem0 : w16 mem0 -11111000101xxxxx000000xxxxxxxxxx n 182 ldadda x0 mem0 : x16 mem0 -00111000101xxxxx000000xxxxxxxxxx n 183 ldaddab w0 mem0 : w16 mem0 -01111000101xxxxx000000xxxxxxxxxx n 184 ldaddah w0 mem0 : w16 mem0 -10111000111xxxxx000000xxxxxxxxxx n 185 ldaddal w0 mem0 : w16 mem0 -11111000111xxxxx000000xxxxxxxxxx n 185 ldaddal x0 mem0 : x16 mem0 -00111000111xxxxx000000xxxxxxxxxx n 186 ldaddalb w0 mem0 : w16 mem0 -01111000111xxxxx000000xxxxxxxxxx n 187 ldaddalh w0 mem0 : w16 mem0 -00111000001xxxxx000000xxxxxxxxxx n 188 ldaddb w0 mem0 : w16 mem0 -01111000001xxxxx000000xxxxxxxxxx n 189 ldaddh w0 mem0 : w16 mem0 -10111000011xxxxx000000xxxxxxxxxx n 190 ldaddl w0 mem0 : w16 mem0 -11111000011xxxxx000000xxxxxxxxxx n 190 ldaddl x0 mem0 : x16 mem0 -00111000011xxxxx000000xxxxxxxxxx n 191 ldaddlb w0 mem0 : w16 mem0 -01111000011xxxxx000000xxxxxxxxxx n 192 ldaddlh w0 mem0 : w16 mem0 1000100011011111111111xxxxxxxxxx n 193 ldar w0 : mem0 1100100011011111111111xxxxxxxxxx n 193 ldar x0 : mem0 0000100011011111111111xxxxxxxxxx n 194 ldarb w0 : mem0 @@ -574,38 +534,6 @@ x001111001011001xxxxxxxxxxxxxxxx n 126 fcvtzu wx0 : d5 scale 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220 ldeorh w0 mem0 : w16 mem0 -10111000011xxxxx001000xxxxxxxxxx n 221 ldeorl w0 mem0 : w16 mem0 -11111000011xxxxx001000xxxxxxxxxx n 221 ldeorl x0 mem0 : x16 mem0 -00111000011xxxxx001000xxxxxxxxxx n 222 ldeorlb w0 mem0 : w16 mem0 -01111000011xxxxx001000xxxxxxxxxx n 223 ldeorlh w0 mem0 : w16 mem0 0010100001xxxxxxxxxxxxxxxxxxxxxx n 224 ldnp w0 w10 : mem7 0010110001xxxxxxxxxxxxxxxxxxxxxx n 224 ldnp s0 s10 : mem7 0110110001xxxxxxxxxxxxxxxxxxxxxx n 224 ldnp d0 d10 : mem7 @@ -691,54 +619,6 @@ x001111001011001xxxxxxxxxxxxxxxx n 126 fcvtzu wx0 : d5 scale 10111000100xxxxxxxxx11xxxxxxxxxx n 232 ldrsw x0 x5sp : mem9 x5sp mem9off 10111000101xxxxxxxxx10xxxxxxxxxx n 232 ldrsw x0 : memreg 1011100110xxxxxxxxxxxxxxxxxxxxxx n 232 ldrsw x0 : mem12 -10111000001xxxxx001100xxxxxxxxxx n 233 ldset w0 mem0 : w16 mem0 -11111000001xxxxx001100xxxxxxxxxx n 233 ldset x0 mem0 : x16 mem0 -10111000101xxxxx001100xxxxxxxxxx n 234 ldseta w0 mem0 : w16 mem0 -11111000101xxxxx001100xxxxxxxxxx n 234 ldseta x0 mem0 : x16 mem0 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269 ldtr w0 : mem9 11111000010xxxxxxxxx10xxxxxxxxxx n 269 ldtr x0 : mem9 00111000010xxxxxxxxx10xxxxxxxxxx n 270 ldtrb w0 : mem9 @@ -748,38 +628,6 @@ x001111001011001xxxxxxxxxxxxxxxx n 126 fcvtzu wx0 : d5 scale 01111000100xxxxxxxxx10xxxxxxxxxx n 273 ldtrsh x0 : mem9 01111000110xxxxxxxxx10xxxxxxxxxx n 273 ldtrsh w0 : mem9 10111000100xxxxxxxxx10xxxxxxxxxx n 274 ldtrsw x0 : mem9 -10111000001xxxxx011000xxxxxxxxxx n 275 ldumax w0 mem0 : w16 mem0 -11111000001xxxxx011000xxxxxxxxxx n 275 ldumax x0 mem0 : x16 mem0 -10111000101xxxxx011000xxxxxxxxxx n 276 ldumaxa w0 mem0 : w16 mem0 -11111000101xxxxx011000xxxxxxxxxx n 276 ldumaxa x0 mem0 : x16 mem0 -00111000101xxxxx011000xxxxxxxxxx n 277 ldumaxab w0 mem0 : w16 mem0 -01111000101xxxxx011000xxxxxxxxxx n 278 ldumaxah w0 mem0 : w16 mem0 -10111000111xxxxx011000xxxxxxxxxx n 279 ldumaxal w0 mem0 : w16 mem0 -11111000111xxxxx011000xxxxxxxxxx n 279 ldumaxal x0 mem0 : x16 mem0 -00111000111xxxxx011000xxxxxxxxxx n 280 ldumaxalb w0 mem0 : w16 mem0 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1101010100001xxxxxxxxxxxxxxxxxxx n 488 sys x0 : op1 crn imm4 op2 1101010100101xxxxxxxxxxxxxxxxxxx n 489 sysl x0 : op1 crn imm4 op2 0x001110000xxxxx0xx000xxxxxxxxxx n 490 tbl dq0 : dq5 dq16 len diff --git a/core/ir/aarch64/codec_v81.txt b/core/ir/aarch64/codec_v81.txt index bca56305ba4..3664061f8c1 100644 --- a/core/ir/aarch64/codec_v81.txt +++ b/core/ir/aarch64/codec_v81.txt @@ -28,11 +28,184 @@ # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH # DAMAGE. -# The new codec will no longer use the instruction specification format of -# codec_v80.txt and opnd_defs.txt to generate the decoder and encoder. This -# file is a temporary placeholder using dummy definitions to enable codec.py to -# ignore instructions handled by the new generator while it is in development. +# See header comments in codec_v80.txt and opnd_defs.txt to understand how +# instructions are defined for the purposes of decode and encode code +# generation. # Instruction definitions: -00000000000000000000000000000000 n 412 sqrdmlah : +10001000101xxxxx011111xxxxxxxxxx n 38 cas w16 mem0 : w16 w0 mem0 +11001000101xxxxx011111xxxxxxxxxx n 38 cas x16 mem0 : x16 x0 mem0 +10001000111xxxxx011111xxxxxxxxxx n 39 casa w16 mem0 : w16 w0 mem0 +11001000111xxxxx011111xxxxxxxxxx n 39 casa x16 mem0 : x16 x0 mem0 +00001000111xxxxx011111xxxxxxxxxx n 40 casab w16 mem0 : w16 w0 mem0 +01001000111xxxxx011111xxxxxxxxxx n 41 casah w16 mem0 : w16 w0 mem0 +10001000111xxxxx111111xxxxxxxxxx n 42 casal w16 mem0 : w16 w0 mem0 +11001000111xxxxx111111xxxxxxxxxx n 42 casal x16 mem0 : x16 x0 mem0 +00001000111xxxxx111111xxxxxxxxxx n 43 casalb w16 mem0 : w16 w0 mem0 +01001000111xxxxx111111xxxxxxxxxx n 44 casalh w16 mem0 : w16 w0 mem0 +00001000101xxxxx011111xxxxxxxxxx n 45 casb w16 mem0 : w16 w0 mem0 +01001000101xxxxx011111xxxxxxxxxx n 46 cash w16 mem0 : w16 w0 mem0 +10001000101xxxxx111111xxxxxxxxxx n 47 casl w16 mem0 : w16 w0 mem0 +11001000101xxxxx111111xxxxxxxxxx n 47 casl x16 mem0 : x16 x0 mem0 +00001000101xxxxx111111xxxxxxxxxx n 48 caslb w16 mem0 : w16 w0 mem0 +01001000101xxxxx111111xxxxxxxxxx n 49 caslh w16 mem0 : w16 w0 mem0 +00001000001xxxxx011111xxxxxxxxxx n 50 casp w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p +01001000001xxxxx011111xxxxxxxxxx n 50 casp x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p +00001000011xxxxx011111xxxxxxxxxx n 51 caspa w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p +01001000011xxxxx011111xxxxxxxxxx n 51 caspa x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p +00001000011xxxxx111111xxxxxxxxxx n 52 caspal w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p +01001000011xxxxx111111xxxxxxxxxx n 52 caspal x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p +00001000001xxxxx111111xxxxxxxxxx n 53 caspl w16p0 w16p1 mem0p : w16p0 w16p1 w0p0 w0p1 mem0p +01001000001xxxxx111111xxxxxxxxxx n 53 caspl x16p0 x16p1 mem0p : x16p0 x16p1 x0p0 x0p1 mem0p +10111000001xxxxx000000xxxxxxxxxx n 181 ldadd w0 mem0 : w16 mem0 +11111000001xxxxx000000xxxxxxxxxx n 181 ldadd x0 mem0 : x16 mem0 +10111000101xxxxx000000xxxxxxxxxx n 182 ldadda w0 mem0 : w16 mem0 +11111000101xxxxx000000xxxxxxxxxx n 182 ldadda x0 mem0 : x16 mem0 +00111000101xxxxx000000xxxxxxxxxx n 183 ldaddab w0 mem0 : w16 mem0 +01111000101xxxxx000000xxxxxxxxxx n 184 ldaddah w0 mem0 : w16 mem0 +10111000111xxxxx000000xxxxxxxxxx n 185 ldaddal w0 mem0 : w16 mem0 +11111000111xxxxx000000xxxxxxxxxx n 185 ldaddal x0 mem0 : x16 mem0 +00111000111xxxxx000000xxxxxxxxxx n 186 ldaddalb w0 mem0 : w16 mem0 +01111000111xxxxx000000xxxxxxxxxx n 187 ldaddalh w0 mem0 : w16 mem0 +00111000001xxxxx000000xxxxxxxxxx n 188 ldaddb w0 mem0 : w16 mem0 +01111000001xxxxx000000xxxxxxxxxx n 189 ldaddh w0 mem0 : w16 mem0 +10111000011xxxxx000000xxxxxxxxxx n 190 ldaddl w0 mem0 : w16 mem0 +11111000011xxxxx000000xxxxxxxxxx n 190 ldaddl x0 mem0 : x16 mem0 +00111000011xxxxx000000xxxxxxxxxx n 191 ldaddlb w0 mem0 : w16 mem0 +01111000011xxxxx000000xxxxxxxxxx n 192 ldaddlh w0 mem0 : w16 mem0 +10111000001xxxxx000100xxxxxxxxxx n 200 ldclr w0 mem0 : w16 mem0 +11111000001xxxxx000100xxxxxxxxxx n 200 ldclr x0 mem0 : x16 mem0 +10111000101xxxxx000100xxxxxxxxxx n 201 ldclra w0 mem0 : w16 mem0 +11111000101xxxxx000100xxxxxxxxxx n 201 ldclra x0 mem0 : x16 mem0 +00111000101xxxxx000100xxxxxxxxxx n 202 ldclrab w0 mem0 : w16 mem0 +01111000101xxxxx000100xxxxxxxxxx n 203 ldclrah w0 mem0 : w16 mem0 +10111000111xxxxx000100xxxxxxxxxx n 204 ldclral w0 mem0 : w16 mem0 +11111000111xxxxx000100xxxxxxxxxx n 204 ldclral x0 mem0 : x16 mem0 +00111000111xxxxx000100xxxxxxxxxx n 205 ldclralb w0 mem0 : w16 mem0 +01111000111xxxxx000100xxxxxxxxxx n 206 ldclralh w0 mem0 : w16 mem0 +00111000001xxxxx000100xxxxxxxxxx n 207 ldclrb w0 mem0 : w16 mem0 +01111000001xxxxx000100xxxxxxxxxx n 208 ldclrh w0 mem0 : w16 mem0 +10111000011xxxxx000100xxxxxxxxxx n 209 ldclrl w0 mem0 : w16 mem0 +11111000011xxxxx000100xxxxxxxxxx n 209 ldclrl x0 mem0 : x16 mem0 +00111000011xxxxx000100xxxxxxxxxx n 210 ldclrlb w0 mem0 : w16 mem0 +01111000011xxxxx000100xxxxxxxxxx n 211 ldclrlh w0 mem0 : w16 mem0 +10111000001xxxxx001000xxxxxxxxxx n 212 ldeor w0 mem0 : w16 mem0 +11111000001xxxxx001000xxxxxxxxxx n 212 ldeor x0 mem0 : x16 mem0 +10111000101xxxxx001000xxxxxxxxxx n 213 ldeora w0 mem0 : w16 mem0 +11111000101xxxxx001000xxxxxxxxxx n 213 ldeora x0 mem0 : x16 mem0 +00111000101xxxxx001000xxxxxxxxxx n 214 ldeorab w0 mem0 : w16 mem0 +01111000101xxxxx001000xxxxxxxxxx n 215 ldeorah w0 mem0 : w16 mem0 +10111000111xxxxx001000xxxxxxxxxx n 216 ldeoral w0 mem0 : w16 mem0 +11111000111xxxxx001000xxxxxxxxxx n 216 ldeoral x0 mem0 : x16 mem0 +00111000111xxxxx001000xxxxxxxxxx n 217 ldeoralb w0 mem0 : w16 mem0 +01111000111xxxxx001000xxxxxxxxxx n 218 ldeoralh w0 mem0 : w16 mem0 +00111000001xxxxx001000xxxxxxxxxx n 219 ldeorb w0 mem0 : w16 mem0 +01111000001xxxxx001000xxxxxxxxxx n 220 ldeorh w0 mem0 : w16 mem0 +10111000011xxxxx001000xxxxxxxxxx n 221 ldeorl w0 mem0 : w16 mem0 +11111000011xxxxx001000xxxxxxxxxx n 221 ldeorl x0 mem0 : x16 mem0 +00111000011xxxxx001000xxxxxxxxxx n 222 ldeorlb w0 mem0 : w16 mem0 +01111000011xxxxx001000xxxxxxxxxx n 223 ldeorlh w0 mem0 : w16 mem0 +10111000001xxxxx001100xxxxxxxxxx n 233 ldset w0 mem0 : w16 mem0 +11111000001xxxxx001100xxxxxxxxxx n 233 ldset x0 mem0 : x16 mem0 +10111000101xxxxx001100xxxxxxxxxx n 234 ldseta w0 mem0 : w16 mem0 +11111000101xxxxx001100xxxxxxxxxx n 234 ldseta x0 mem0 : x16 mem0 +00111000101xxxxx001100xxxxxxxxxx n 235 ldsetab w0 mem0 : w16 mem0 +01111000101xxxxx001100xxxxxxxxxx n 236 ldsetah w0 mem0 : w16 mem0 +10111000111xxxxx001100xxxxxxxxxx n 237 ldsetal w0 mem0 : w16 mem0 +11111000111xxxxx001100xxxxxxxxxx n 237 ldsetal x0 mem0 : x16 mem0 +00111000111xxxxx001100xxxxxxxxxx n 238 ldsetalb w0 mem0 : w16 mem0 +01111000111xxxxx001100xxxxxxxxxx n 239 ldsetalh w0 mem0 : w16 mem0 +00111000001xxxxx001100xxxxxxxxxx n 240 ldsetb w0 mem0 : w16 mem0 +01111000001xxxxx001100xxxxxxxxxx n 241 ldseth w0 mem0 : w16 mem0 +10111000011xxxxx001100xxxxxxxxxx n 242 ldsetl w0 mem0 : w16 mem0 +11111000011xxxxx001100xxxxxxxxxx n 242 ldsetl x0 mem0 : x16 mem0 +00111000011xxxxx001100xxxxxxxxxx n 243 ldsetlb w0 mem0 : w16 mem0 +01111000011xxxxx001100xxxxxxxxxx n 244 ldsetlh w0 mem0 : w16 mem0 +10111000001xxxxx010000xxxxxxxxxx n 245 ldsmax w0 mem0 : w16 mem0 +11111000001xxxxx010000xxxxxxxxxx n 245 ldsmax x0 mem0 : x16 mem0 +10111000101xxxxx010000xxxxxxxxxx n 246 ldsmaxa w0 mem0 : w16 mem0 +11111000101xxxxx010000xxxxxxxxxx n 246 ldsmaxa x0 mem0 : x16 mem0 +00111000101xxxxx010000xxxxxxxxxx n 247 ldsmaxab w0 mem0 : w16 mem0 +01111000101xxxxx010000xxxxxxxxxx n 248 ldsmaxah w0 mem0 : w16 mem0 +10111000111xxxxx010000xxxxxxxxxx n 249 ldsmaxal w0 mem0 : w16 mem0 +11111000111xxxxx010000xxxxxxxxxx n 249 ldsmaxal x0 mem0 : x16 mem0 +00111000111xxxxx010000xxxxxxxxxx n 250 ldsmaxalb w0 mem0 : w16 mem0 +01111000111xxxxx010000xxxxxxxxxx n 251 ldsmaxalh w0 mem0 : w16 mem0 +00111000001xxxxx010000xxxxxxxxxx n 252 ldsmaxb w0 mem0 : w16 mem0 +01111000001xxxxx010000xxxxxxxxxx n 253 ldsmaxh w0 mem0 : w16 mem0 +10111000011xxxxx010000xxxxxxxxxx n 254 ldsmaxl w0 mem0 : w16 mem0 +11111000011xxxxx010000xxxxxxxxxx n 254 ldsmaxl x0 mem0 : x16 mem0 +00111000011xxxxx010000xxxxxxxxxx n 255 ldsmaxlb w0 mem0 : w16 mem0 +01111000011xxxxx010000xxxxxxxxxx n 256 ldsmaxlh w0 mem0 : w16 mem0 +10111000001xxxxx010100xxxxxxxxxx n 257 ldsmin w0 mem0 : w16 mem0 +11111000001xxxxx010100xxxxxxxxxx n 257 ldsmin x0 mem0 : x16 mem0 +10111000101xxxxx010100xxxxxxxxxx n 258 ldsmina w0 mem0 : w16 mem0 +11111000101xxxxx010100xxxxxxxxxx n 258 ldsmina x0 mem0 : x16 mem0 +00111000101xxxxx010100xxxxxxxxxx n 259 ldsminab w0 mem0 : w16 mem0 +01111000101xxxxx010100xxxxxxxxxx n 260 ldsminah w0 mem0 : w16 mem0 +10111000111xxxxx010100xxxxxxxxxx n 261 ldsminal w0 mem0 : w16 mem0 +11111000111xxxxx010100xxxxxxxxxx n 261 ldsminal x0 mem0 : x16 mem0 +00111000111xxxxx010100xxxxxxxxxx n 262 ldsminalb w0 mem0 : w16 mem0 +01111000111xxxxx010100xxxxxxxxxx n 263 ldsminalh w0 mem0 : w16 mem0 +00111000001xxxxx010100xxxxxxxxxx n 264 ldsminb w0 mem0 : w16 mem0 +01111000001xxxxx010100xxxxxxxxxx n 265 ldsminh w0 mem0 : w16 mem0 +10111000011xxxxx010100xxxxxxxxxx n 266 ldsminl w0 mem0 : w16 mem0 +11111000011xxxxx010100xxxxxxxxxx n 266 ldsminl x0 mem0 : x16 mem0 +00111000011xxxxx010100xxxxxxxxxx n 267 ldsminlb w0 mem0 : w16 mem0 +01111000011xxxxx010100xxxxxxxxxx n 268 ldsminlh w0 mem0 : w16 mem0 +10111000001xxxxx011000xxxxxxxxxx n 275 ldumax w0 mem0 : w16 mem0 +11111000001xxxxx011000xxxxxxxxxx n 275 ldumax x0 mem0 : x16 mem0 +10111000101xxxxx011000xxxxxxxxxx n 276 ldumaxa w0 mem0 : w16 mem0 +11111000101xxxxx011000xxxxxxxxxx n 276 ldumaxa x0 mem0 : x16 mem0 +00111000101xxxxx011000xxxxxxxxxx n 277 ldumaxab w0 mem0 : w16 mem0 +01111000101xxxxx011000xxxxxxxxxx n 278 ldumaxah w0 mem0 : w16 mem0 +10111000111xxxxx011000xxxxxxxxxx n 279 ldumaxal w0 mem0 : w16 mem0 +11111000111xxxxx011000xxxxxxxxxx n 279 ldumaxal x0 mem0 : x16 mem0 +00111000111xxxxx011000xxxxxxxxxx n 280 ldumaxalb w0 mem0 : w16 mem0 +01111000111xxxxx011000xxxxxxxxxx n 281 ldumaxalh w0 mem0 : w16 mem0 +00111000001xxxxx011000xxxxxxxxxx n 282 ldumaxb w0 mem0 : w16 mem0 +01111000001xxxxx011000xxxxxxxxxx n 283 ldumaxh w0 mem0 : w16 mem0 +10111000011xxxxx011000xxxxxxxxxx n 284 ldumaxl w0 mem0 : w16 mem0 +11111000011xxxxx011000xxxxxxxxxx n 284 ldumaxl x0 mem0 : x16 mem0 +00111000011xxxxx011000xxxxxxxxxx n 285 ldumaxlb w0 mem0 : w16 mem0 +01111000011xxxxx011000xxxxxxxxxx n 286 ldumaxlh w0 mem0 : w16 mem0 +10111000001xxxxx011100xxxxxxxxxx n 287 ldumin w0 mem0 : w16 mem0 +11111000001xxxxx011100xxxxxxxxxx n 287 ldumin x0 mem0 : x16 mem0 +10111000101xxxxx011100xxxxxxxxxx n 288 ldumina w0 mem0 : w16 mem0 +11111000101xxxxx011100xxxxxxxxxx n 288 ldumina x0 mem0 : x16 mem0 +00111000101xxxxx011100xxxxxxxxxx n 289 lduminab w0 mem0 : w16 mem0 +01111000101xxxxx011100xxxxxxxxxx n 290 lduminah w0 mem0 : w16 mem0 +10111000111xxxxx011100xxxxxxxxxx n 291 lduminal w0 mem0 : w16 mem0 +11111000111xxxxx011100xxxxxxxxxx n 291 lduminal x0 mem0 : x16 mem0 +00111000111xxxxx011100xxxxxxxxxx n 292 lduminalb w0 mem0 : w16 mem0 +01111000111xxxxx011100xxxxxxxxxx n 293 lduminalh w0 mem0 : w16 mem0 +00111000001xxxxx011100xxxxxxxxxx n 294 lduminb w0 mem0 : w16 mem0 +01111000001xxxxx011100xxxxxxxxxx n 295 lduminh w0 mem0 : w16 mem0 +10111000011xxxxx011100xxxxxxxxxx n 296 lduminl w0 mem0 : w16 mem0 +11111000011xxxxx011100xxxxxxxxxx n 296 lduminl x0 mem0 : x16 mem0 +00111000011xxxxx011100xxxxxxxxxx n 297 lduminlb w0 mem0 : w16 mem0 +01111000011xxxxx011100xxxxxxxxxx n 298 lduminlh w0 mem0 : w16 mem0 +0x1011111xxxxxxx1101x0xxxxxxxxxx n 412 sqrdmlah dq0 : dq0 dq5 dq16 vindex_SD sd_sz +0x10111101xxxxxx1101x0xxxxxxxxxx n 412 sqrdmlah dq0 : dq0 dq5 dq16_h_sz vindex_H h_sz +0111111101xxxxxx1101x0xxxxxxxxxx n 412 sqrdmlah h0 : h0 h5 dq16_h_sz vindex_H h_sz +0111111110xxxxxx1101x0xxxxxxxxxx n 412 sqrdmlah s0 : s0 s5 dq16 vindex_SD sd_sz +0x101110xx0xxxxx100001xxxxxxxxxx n 412 sqrdmlah dq0 : dq0 dq5 dq16 hs_sz +01111110010xxxxx100001xxxxxxxxxx n 412 sqrdmlah h0 : h0 h5 h16 +01111110100xxxxx100001xxxxxxxxxx n 412 sqrdmlah s0 : s0 s5 s16 +10111000001xxxxx100000xxxxxxxxxx n 476 swp w0 mem0 : w16 mem0 +11111000001xxxxx100000xxxxxxxxxx n 476 swp x0 mem0 : x16 mem0 +10111000101xxxxx100000xxxxxxxxxx n 477 swpa w0 mem0 : w16 mem0 +11111000101xxxxx100000xxxxxxxxxx n 477 swpa x0 mem0 : x16 mem0 +00111000101xxxxx100000xxxxxxxxxx n 478 swpab w0 mem0 : w16 mem0 +01111000101xxxxx100000xxxxxxxxxx n 479 swpah w0 mem0 : w16 mem0 +10111000111xxxxx100000xxxxxxxxxx n 480 swpal w0 mem0 : w16 mem0 +11111000111xxxxx100000xxxxxxxxxx n 480 swpal x0 mem0 : x16 mem0 +00111000111xxxxx100000xxxxxxxxxx n 481 swpalb w0 mem0 : w16 mem0 +01111000111xxxxx100000xxxxxxxxxx n 482 swpalh w0 mem0 : w16 mem0 +00111000001xxxxx100000xxxxxxxxxx n 483 swpb w0 mem0 : w16 mem0 +01111000001xxxxx100000xxxxxxxxxx n 484 swph w0 mem0 : w16 mem0 +10111000011xxxxx100000xxxxxxxxxx n 485 swpl w0 mem0 : w16 mem0 +11111000011xxxxx100000xxxxxxxxxx n 485 swpl x0 mem0 : x16 mem0 +00111000011xxxxx100000xxxxxxxxxx n 486 swplb w0 mem0 : w16 mem0 +01111000011xxxxx100000xxxxxxxxxx n 487 swplh w0 mem0 : w16 mem0 diff --git a/core/ir/aarch64/decode_v81.h b/core/ir/aarch64/decode_v81.h deleted file mode 100644 index 51ca9756104..00000000000 --- a/core/ir/aarch64/decode_v81.h +++ /dev/null @@ -1,435 +0,0 @@ -/* ********************************************************** - * Copyright (c) 2016-2022 ARM Limited. All rights reserved. - * **********************************************************/ - -/* - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of ARM Limited nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL ARM LIMITED OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -/* File created by codec_gen.py on 07-04-22 from MRS version v8.1. */ - -/* This file is an example of the code which will be generated from a machine - * readable specification (MRS) for all AArch64 instruction from v8.1 onwards. - * - * The comments in this file bind instruction specification data in the MRS to - * decoder functionality to help describe the mapping between the two for - * auto-generation purposes. - * - * The format of the code is intended to be human readable and will include - * auto-generated comments extracted from the MRS. The prefix 'MRSC:' is used - * to distinguish these examples from manual comments in this file. - */ - -/* Each instruction's decode and encode function name is built from literal and - * type data from the MRS. As an example: - * dec_ Decode function, (enc_ for encode function, see encode_v81.h). - * SQRDMLAH Instruction name. - * VVV Operands signature: - * R General purpose register. - * I Immediate. - * V Vector register (size specification follows). - * 16 Vector size and type, e.g. 16 bit scalar (halfword). For vector - * elements, x, e.g. 4x16. - */ -/* MRSC: SQRDMLAH , , */ -static bool -dec_SQRDMLAH_VVV_16(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - /* Sanity check to ensure correct key/value entry has been generated in - * decode_map. - */ - ASSERT(BITS(enc, 15, 10) == 0b100001 && BITS(enc, 31, 21) == 0b01111110010); - - /* Decode operands based on type and size data, and bit positions extracted - * from MRS. - */ - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_HALF, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_HALF, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_HALF, BITS(enc, 20, 16)); - - /* Instruction name and operand type data from MRS. */ - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 2); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - - return true; -} - -/* MRSC: SQRDMLAH , , */ -static bool -dec_SQRDMLAH_VVV_32(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 15, 10) == 0b100001 && BITS(enc, 31, 21) == 0b01111110100); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_SINGLE, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_SINGLE, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_SINGLE, BITS(enc, 20, 16)); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 2); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - - return true; -} - -/* MRSC: SQRDMLAH ., ., . */ -static bool -dec_SQRDMLAH_VVV_4x16(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 15, 10) == 0b100001 && BITS(enc, 31, 21) == 0b00101110010); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 20, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_HALF, OPSZ_2b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 3); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, elsz); - - return true; -} - -/* MRSC: SQRDMLAH ., ., . */ -static bool -dec_SQRDMLAH_VVV_8x16(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 15, 10) == 0b100001 && BITS(enc, 31, 21) == 0b01101110010); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 20, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_HALF, OPSZ_2b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 3); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, elsz); - - return true; -} - -/* MRSC: SQRDMLAH ., ., . */ -static bool -dec_SQRDMLAH_VVV_2x32(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 15, 10) == 0b100001 && BITS(enc, 31, 21) == 0b00101110100); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 20, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_SINGLE, OPSZ_2b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 3); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, elsz); - - return true; -} - -/* MRSC: SQRDMLAH ., ., . */ -static bool -dec_SQRDMLAH_VVV_4x32(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 15, 10) == 0b100001 && BITS(enc, 31, 21) == 0b01101110100); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 20, 16)); - opnd_t elsz = opnd_create_immed_int(VECTOR_ELEM_WIDTH_SINGLE, OPSZ_2b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 3); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, elsz); - - return true; -} - -/* Translation from a 32 bit encoding to the decode function is based on a - * collection of decode_map structures which use key/value mappings. The key is - * a unique set of up to 32 fixed (non-operand) bits. The value is a pointer to - * the decode function. - * - * The name of each decode_map struct is created from the bit positions of the - * fixed (non-operand) bits extracted from the MRS. The keys are encodings for - * these bit positions extracted from the MRS. The function pointer name is - * created from the MRS as described by dec_SQRDMLAH_VVV_16() above. - */ -/* MRSC: SQRDMLAH , , */ -/* MRSC: SQRDMLAH ., ., . */ -const static decode_map decode_map__31_21__15_10[] = { - { 0b01111110010100001, dec_SQRDMLAH_VVV_16 }, - { 0b01111110100100001, dec_SQRDMLAH_VVV_32 }, - { 0b00101110010100001, dec_SQRDMLAH_VVV_4x16 }, - { 0b01101110010100001, dec_SQRDMLAH_VVV_8x16 }, - { 0b00101110100100001, dec_SQRDMLAH_VVV_2x32 }, - { 0b01101110100100001, dec_SQRDMLAH_VVV_4x32 } -}; - -/* MRSC: SQRDMLAH , , .[] */ -static bool -dec_SQRDMLAH_VVVI_16(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 10, 10) == 0b0 && BITS(enc, 15, 12) == 0b1101 && - BITS(enc, 31, 22) == 0b0111111101); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_HALF, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_HALF, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 19, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_HALF, OPSZ_1); - uint hlm = (BITS(enc, 11, 11) << 2) | BITS(enc, 21, 20); - opnd_t idx = opnd_create_immed_uint(hlm, OPSZ_3b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 4); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, idx); - instr_set_src(instr, 3, elsz); - - return true; -} - -/* MRSC: SQRDMLAH , , .[] */ -static bool -dec_SQRDMLAH_VVVI_32(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 10, 10) == 0b0 && BITS(enc, 15, 12) == 0b1101 && - BITS(enc, 31, 22) == 0b0111111110); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_SINGLE, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_SINGLE, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(4, BITS(enc, 19, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_SINGLE, OPSZ_1); - uint hl = (BITS(enc, 11, 11) << 1) | BITS(enc, 21, 21); - opnd_t idx = opnd_create_immed_uint(hl, OPSZ_3b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 4); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, idx); - instr_set_src(instr, 3, elsz); - - return true; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static bool -dec_SQRDMLAH_VVVI_4x16_1x16(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 10, 10) == 0b0 && BITS(enc, 15, 12) == 0b1101 && - BITS(enc, 31, 22) == 0b0010111101); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 19, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_HALF, OPSZ_1); - uint hlm = (BITS(enc, 11, 11) << 2) | BITS(enc, 21, 20); - opnd_t idx = opnd_create_immed_uint(hlm, OPSZ_3b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 4); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, idx); - instr_set_src(instr, 3, elsz); - - return true; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static bool -dec_SQRDMLAH_VVVI_8x16_1x16(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 10, 10) == 0b0 && BITS(enc, 15, 12) == 0b1101 && - BITS(enc, 31, 22) == 0b0110111101); - - opnd_t Vd = decode_vreg(4, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(4, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(4, BITS(enc, 19, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_HALF, OPSZ_1); - uint hlm = (BITS(enc, 11, 11) << 2) | BITS(enc, 21, 20); - opnd_t idx = opnd_create_immed_uint(hlm, OPSZ_3b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 4); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, idx); - instr_set_src(instr, 3, elsz); - - return true; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static bool -dec_SQRDMLAH_VVVI_2x32_1x32(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 10, 10) == 0b0 && BITS(enc, 15, 12) == 0b1101 && - BITS(enc, 31, 22) == 0b0010111110); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_DOUBLE, BITS(enc, 20, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_SINGLE, OPSZ_1); - uint hl = (BITS(enc, 11, 11) << 1) | BITS(enc, 21, 21); - opnd_t idx = opnd_create_immed_uint(hl, OPSZ_3b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 4); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, idx); - instr_set_src(instr, 3, elsz); - - return true; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static bool -dec_SQRDMLAH_VVVI_4x32_1x32(dcontext_t *dcontext, uint enc, instr_t *instr) -{ - ASSERT(BITS(enc, 10, 10) == 0b0 && BITS(enc, 15, 12) == 0b1101 && - BITS(enc, 31, 22) == 0b0110111110); - - opnd_t Vd = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 4, 0)); - opnd_t Vn = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 9, 5)); - opnd_t Vm = decode_vreg(VECTOR_ELEM_WIDTH_QUAD, BITS(enc, 20, 16)); - opnd_t elsz = opnd_create_immed_uint(VECTOR_ELEM_WIDTH_SINGLE, OPSZ_1); - uint hl = (BITS(enc, 11, 11) << 1) | BITS(enc, 21, 21); - opnd_t idx = opnd_create_immed_uint(hl, OPSZ_3b); - - instr_set_opcode(instr, OP_sqrdmlah); - instr_set_num_opnds(dcontext, instr, 1, 4); - - instr_set_dst(instr, 0, Vd); - instr_set_src(instr, 0, Vn); - instr_set_src(instr, 1, Vm); - instr_set_src(instr, 2, idx); - instr_set_src(instr, 3, elsz); - - return true; -} - -/* MRSC: SQRDMLAH , , .[] */ -/* MRSC: SQRDMLAH ., ., .[] */ -const static decode_map decode_map__31_22__15_12__10[] = { - { 0b011111110111010, dec_SQRDMLAH_VVVI_16 }, - { 0b011111111011010, dec_SQRDMLAH_VVVI_32 }, - { 0b001011110111010, dec_SQRDMLAH_VVVI_4x16_1x16 }, - { 0b011011110111010, dec_SQRDMLAH_VVVI_8x16_1x16 }, - { 0b001011111011010, dec_SQRDMLAH_VVVI_2x32_1x32 }, - { 0b011011111011010, dec_SQRDMLAH_VVVI_4x32_1x32 } -}; - -static bool -decode_v81(uint enc, dcontext_t *dc, byte *pc, instr_t *instr) -{ - int map_size; - - /* The decoder for each version of the architecture is a set of loops over - * the decode_map structs defined for supported instructions. When a fixed - * (non-operand) bit match is found from the 32 bit input encoding, a - * decode function is called, constructing an instr_t object. - * - * This example is the lowest level (leaf) of the decode tree. The fully - * generated decoder will start at the top level (root) working its way - * down to the leaves by decoding successive fixed opcode fields of the - * encoding spec: a chain of decode_map objects with pointers to lower - * level decode loops and instruction decode functions. - */ - { - /* Extract bit values from input encoding for instructions with fixed - * (non-operand) bits specified in MRS at: - * 31 21 15 10 - * | | | | - * 01111110sz0Vm---100001Vn---Vd--- - * Note: the size field (22,23) is a fixed property of the instruction - * variant, not an operand. - */ - /* MRSC: SQRDMLAH , , */ - /* MRSC: SQRDMLAH ., ., . */ - uint bits_15_10 = BITS(enc, 15, 10); - uint bits_31_21 = BITS(enc, 31, 21); - uint bits_15_10_len = (15 - 10) + 1; - uint bitmap = (bits_31_21 << bits_15_10_len) | bits_15_10; - map_size = sizeof(decode_map__31_21__15_10) / sizeof(decode_map); - for (int m = 0; m < map_size; m++) { - if (decode_map__31_21__15_10[m].enc_bits == bitmap) - return decode_map__31_21__15_10[m].decode_fn(dc, enc, instr); - } - } - { - /* MRSC: SQRDMLAH , , .[] */ - /* MRSC: SQRDMLAH ., ., .[] */ - uint bit_10 = BITS(enc, 10, 10); - uint bits_15_12 = BITS(enc, 15, 12); - uint bits_31_22 = BITS(enc, 31, 22); - uint bit_10_len = 1; - uint bits_15_12_len = (15 - 12) + 1; - uint bitmap = (bits_31_22 << (bit_10_len + bits_15_12_len)) | - (bits_15_12 << bit_10_len) | bit_10; - map_size = sizeof(decode_map__31_22__15_12__10) / sizeof(decode_map); - for (int m = 0; m < map_size; m++) { - if (decode_map__31_22__15_12__10[m].enc_bits == bitmap) - return decode_map__31_22__15_12__10[m].decode_fn(dc, enc, instr); - } - } - return decoder_v82(enc, dc, pc, instr); -} diff --git a/core/ir/aarch64/encode_v81.h b/core/ir/aarch64/encode_v81.h deleted file mode 100644 index cfe781bcf94..00000000000 --- a/core/ir/aarch64/encode_v81.h +++ /dev/null @@ -1,429 +0,0 @@ -/* ********************************************************** - * Copyright (c) 2016-2022 ARM Limited. All rights reserved. - * **********************************************************/ - -/* - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of ARM Limited nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL ARM LIMITED OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -/* File created by codec_gen.py on 07-04-22 from MRS version v8.1. */ - -/* This file is an example of the code which will be generated from a machine - * readable specification (MRS) for all AArch64 instruction from v8.1 onwards. - * - * The comments in this file bind instruction specification data in the MRS to - * encoder functionality to help describe the mapping between the two for - * auto-generation purposes. - * - * The format of the code is intended to be human readable and will include - * auto-generated comments extracted from the MRS. The prefix 'MRSC:' is used - * to distinguish these examples from manual comments in this file. - */ - -/* Each instruction's decode and encode function name is built from literal and - * type data from the MRS. As an example: - * enc_ Encode function, (dec_ for decode function, see decode_v81.h). - * SQRDMLAH Instruction name. - * VVV Operands signature: - * R General purpose register. - * I Immediate. - * V Vector register (size specification follows). - * 16 Vector size and type, e.g. 16 bit scalar (halfword). For vector - * elements, x, e.g. 4x16. - */ -/* MRSC: SQRDMLAH , , */ -static uint -enc_SQRDMLAH_VVV_16(instr_t *instr) -{ - /* Fixed (non-operand) bits extracted from the MRS uniquely identifying - * this instruction. - */ - uint32 enc = 0x7e408400; - - /* Sanity check based on name of instruction extracted from MRS. */ - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - /* Encode operands based on number, type and size data, and bit positions - * extracted from MRS. - */ - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 2) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0; - opnd_size_t half = OPSZ_2; - if (!encode_vreg(&half, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&half, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&half, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - - return enc |= (Vm << 16) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH , , */ -static uint -enc_SQRDMLAH_VVV_32(instr_t *instr) -{ - uint32 enc = 0x7e808400; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 2) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0; - opnd_size_t single = OPSZ_4; - if (!encode_vreg(&single, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&single, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&single, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - - return enc |= (Vm << 16) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., . */ -static uint -enc_SQRDMLAH_VVV_4x16(instr_t *instr) -{ - uint32 enc = 0x2e408400; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 3) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0; - opnd_size_t double_ = OPSZ_8; - if (!encode_vreg(&double_, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!get_el_hs_sz(&elsz, instr_get_src(instr, 2))) - return ENCFAIL; - if (elsz != VECTOR_ELEM_WIDTH_HALF) - return ENCFAIL; - - return enc |= (elsz << 22) | (Vm << 16) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., . */ -static uint -enc_SQRDMLAH_VVV_8x16(instr_t *instr) -{ - uint32 enc = 0x6e408400; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 3) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0; - opnd_size_t quad = OPSZ_16; - if (!encode_vreg(&quad, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!get_el_hs_sz(&elsz, instr_get_src(instr, 2))) - return ENCFAIL; - if (elsz != VECTOR_ELEM_WIDTH_HALF) - return ENCFAIL; - - return enc |= (elsz << 22) | (Vm << 16) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., . */ -static uint -enc_SQRDMLAH_VVV_2x32(instr_t *instr) -{ - uint32 enc = 0x2e808400; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 3) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0; - opnd_size_t double_ = OPSZ_8; - if (!encode_vreg(&double_, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!get_el_hs_sz(&elsz, instr_get_src(instr, 2))) - return ENCFAIL; - if (elsz != VECTOR_ELEM_WIDTH_SINGLE) - return ENCFAIL; - - return enc |= (elsz << 22) | (Vm << 16) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., . */ -static uint -enc_SQRDMLAH_VVV_4x32(instr_t *instr) -{ - uint32 enc = 0x6e808400; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 3) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0; - opnd_size_t quad = OPSZ_16; - if (!encode_vreg(&quad, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!get_el_hs_sz(&elsz, instr_get_src(instr, 2))) - return ENCFAIL; - if (elsz != VECTOR_ELEM_WIDTH_SINGLE) - return ENCFAIL; - - return enc |= (elsz << 22) | (Vm << 16) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH , , .[] */ -static uint -enc_SQRDMLAH_VVVI_16(instr_t *instr) -{ - uint32 enc = 0x7f40d000; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 4) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0, idx = 0; - opnd_size_t half = OPSZ_2, quad = OPSZ_16; - if (!encode_vreg(&half, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&half, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!encode_opnd_vindex_H(0, 0, 0, instr_get_src(instr, 2), &idx)) - return ENCFAIL; - if (!encode_opnd_h_sz(0, 0, 0, instr_get_src(instr, 3), &elsz)) - return ENCFAIL; - - return enc |= - (elsz << 22) | (idx & 0x300000) | (Vm << 16) | (idx & 0x800) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH , , .[] */ -static uint -enc_SQRDMLAH_VVVI_32(instr_t *instr) -{ - uint32 enc = 0x7f80d000; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 4) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0, idx = 0; - opnd_size_t single = OPSZ_4, quad = OPSZ_16; - if (!encode_vreg(&single, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&single, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!encode_opnd_vindex_SD(0, 0, 0, instr_get_src(instr, 2), &idx)) - return ENCFAIL; - if (!encode_opnd_sd_sz(0, 0, 0, instr_get_src(instr, 3), &elsz)) - return ENCFAIL; - - return enc |= - (elsz << 22) | (idx & 0x200000) | (Vm << 16) | (idx & 0x800) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static uint -enc_SQRDMLAH_VVVI_4x16_1x16(instr_t *instr) -{ - uint32 enc = 0x2f40d000; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 4) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0, idx = 0; - opnd_size_t double_ = OPSZ_8; - if (!encode_vreg(&double_, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!encode_opnd_vindex_H(0, 0, 0, instr_get_src(instr, 2), &idx)) - return ENCFAIL; - if (!encode_opnd_h_sz(0, 0, 0, instr_get_src(instr, 3), &elsz)) - return ENCFAIL; - - return enc |= - (elsz << 22) | (idx & 0x300000) | (Vm << 16) | (idx & 0x800) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static uint -enc_SQRDMLAH_VVVI_8x16_1x16(instr_t *instr) -{ - uint32 enc = 0x6f40d000; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 4) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0, idx = 0; - opnd_size_t quad = OPSZ_16; - if (!encode_vreg(&quad, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!encode_opnd_vindex_H(0, 0, 0, instr_get_src(instr, 2), &idx)) - return ENCFAIL; - if (!encode_opnd_h_sz(0, 0, 0, instr_get_src(instr, 3), &elsz)) - return ENCFAIL; - - return enc |= - (elsz << 22) | (idx & 0x300000) | (Vm << 16) | (idx & 0x800) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static uint -enc_SQRDMLAH_VVVI_2x32_1x32(instr_t *instr) -{ - uint32 enc = 0x2f80d000; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 4) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0, idx = 0; - opnd_size_t double_ = OPSZ_8; - if (!encode_vreg(&double_, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&double_, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!encode_opnd_vindex_SD(0, 0, 0, instr_get_src(instr, 2), &idx)) - return ENCFAIL; - if (!encode_opnd_sd_sz(0, 0, 0, instr_get_src(instr, 3), &elsz)) - return ENCFAIL; - - return enc |= - (elsz << 22) | (idx & 0x200000) | (Vm << 16) | (idx & 0x800) | (Vn << 5) | Vd; -} - -/* MRSC: SQRDMLAH ., ., .[] */ -static uint -enc_SQRDMLAH_VVVI_4x32_1x32(instr_t *instr) -{ - uint32 enc = 0x6f80d000; - - if (instr_get_opcode(instr) != OP_sqrdmlah) - return ENCFAIL; - - if (instr_num_dsts(instr) != 1 || instr_num_srcs(instr) != 4) - return ENCFAIL; - - uint Vd = 0, Vn = 0, Vm = 0, elsz = 0, idx = 0; - opnd_size_t quad = OPSZ_16; - if (!encode_vreg(&quad, &Vd, instr_get_dst(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vn, instr_get_src(instr, 0))) - return ENCFAIL; - if (!encode_vreg(&quad, &Vm, instr_get_src(instr, 1))) - return ENCFAIL; - if (!encode_opnd_vindex_SD(0, 0, 0, instr_get_src(instr, 2), &idx)) - return ENCFAIL; - if (!encode_opnd_sd_sz(0, 0, 0, instr_get_src(instr, 3), &elsz)) - return ENCFAIL; - - return enc |= - (elsz << 22) | (idx & 0x200000) | (Vm << 16) | (idx & 0x800) | (Vn << 5) | Vd; -} - -static uint -encode_v81(byte *pc, instr_t *instr, decode_info_t *di) -{ - /* The encoder for each version of the architecture is a switch statement - * which selects encoder function(s) for each instruction and its variants - * based on the instruction name extracted from the MRS. - */ - uint enc; - (void)enc; - switch (instr->opcode) { - case OP_sqrdmlah: - /* MRSC: SQRDMLAH , , */ - ENCODE_IF_MATCH(enc_SQRDMLAH_VVV_16); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVV_32); - /* MRSC: SQRDMLAH ., ., . */ - ENCODE_IF_MATCH(enc_SQRDMLAH_VVV_4x16); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVV_8x16); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVV_2x32); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVV_4x32); - /* MRSC: SQRDMLAH , , .[] */ - ENCODE_IF_MATCH(enc_SQRDMLAH_VVVI_16); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVVI_32); - /* MRSC: SQRDMLAH ., ., .[] */ - ENCODE_IF_MATCH(enc_SQRDMLAH_VVVI_4x16_1x16); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVVI_8x16_1x16); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVVI_2x32_1x32); - ENCODE_IF_MATCH(enc_SQRDMLAH_VVVI_4x32_1x32); - break; - } - return encoder_v82(pc, instr, di); -} diff --git a/suite/tests/api/dis-a64.txt b/suite/tests/api/dis-a64.txt index 185eb0624ed..913333044cd 100644 --- a/suite/tests/api/dis-a64.txt +++ b/suite/tests/api/dis-a64.txt @@ -6981,100 +6981,100 @@ d41fffe3 : smc #0xffff : smc $0xffff 4fbddb9e : sqrdmulh v30.4s, v28.4s, v29.s[3] : sqrdmulh %q28 %q29 $0x03 $0x02 -> %q30 # SQRDMLAH , , -7e428420 : sqrdmlah h0, h1, h2 : sqrdmlah %h1 %h2 -> %h0 -7e448465 : sqrdmlah h5, h3, h4 : sqrdmlah %h3 %h4 -> %h5 -7e49850a : sqrdmlah h10, h8, h9 : sqrdmlah %h8 %h9 -> %h10 -7e4e85af : sqrdmlah h15, h13, h14 : sqrdmlah %h13 %h14 -> %h15 -7e538654 : sqrdmlah h20, h18, h19 : sqrdmlah %h18 %h19 -> %h20 -7e5886f9 : sqrdmlah h25, h23, h24 : sqrdmlah %h23 %h24 -> %h25 -7e5d879e : sqrdmlah h30, h28, h29 : sqrdmlah %h28 %h29 -> %h30 -7e828420 : sqrdmlah s0, s1, s2 : sqrdmlah %s1 %s2 -> %s0 -7e848465 : sqrdmlah s5, s3, s4 : sqrdmlah %s3 %s4 -> %s5 -7e89850a : sqrdmlah s10, s8, s9 : sqrdmlah %s8 %s9 -> %s10 -7e8e85af : sqrdmlah s15, s13, s14 : sqrdmlah %s13 %s14 -> %s15 -7e938654 : sqrdmlah s20, s18, s19 : sqrdmlah %s18 %s19 -> %s20 -7e9886f9 : sqrdmlah s25, s23, s24 : sqrdmlah %s23 %s24 -> %s25 -7e9d879e : sqrdmlah s30, s28, s29 : sqrdmlah %s28 %s29 -> %s30 +7e428420 : sqrdmlah h0, h1, h2 : sqrdmlah %h0 %h1 %h2 -> %h0 +7e448465 : sqrdmlah h5, h3, h4 : sqrdmlah %h5 %h3 %h4 -> %h5 +7e49850a : sqrdmlah h10, h8, h9 : sqrdmlah %h10 %h8 %h9 -> %h10 +7e4e85af : sqrdmlah h15, h13, h14 : sqrdmlah %h15 %h13 %h14 -> %h15 +7e538654 : sqrdmlah h20, h18, h19 : sqrdmlah %h20 %h18 %h19 -> %h20 +7e5886f9 : sqrdmlah h25, h23, h24 : sqrdmlah %h25 %h23 %h24 -> %h25 +7e5d879e : sqrdmlah h30, h28, h29 : sqrdmlah %h30 %h28 %h29 -> %h30 +7e828420 : sqrdmlah s0, s1, s2 : sqrdmlah %s0 %s1 %s2 -> %s0 +7e848465 : sqrdmlah s5, s3, s4 : sqrdmlah %s5 %s3 %s4 -> %s5 +7e89850a : sqrdmlah s10, s8, s9 : sqrdmlah %s10 %s8 %s9 -> %s10 +7e8e85af : sqrdmlah s15, s13, s14 : sqrdmlah %s15 %s13 %s14 -> %s15 +7e938654 : sqrdmlah s20, s18, s19 : sqrdmlah %s20 %s18 %s19 -> %s20 +7e9886f9 : sqrdmlah s25, s23, s24 : sqrdmlah %s25 %s23 %s24 -> %s25 +7e9d879e : sqrdmlah s30, s28, s29 : sqrdmlah %s30 %s28 %s29 -> %s30 # SQRDMLAH ., ., . -2e428420 : sqrdmlah v0.4h, v1.4h, v2.4h : sqrdmlah %d1 %d2 $0x01 -> %d0 -2e448465 : sqrdmlah v5.4h, v3.4h, v4.4h : sqrdmlah %d3 %d4 $0x01 -> %d5 -2e49850a : sqrdmlah v10.4h, v8.4h, v9.4h : sqrdmlah %d8 %d9 $0x01 -> %d10 -2e4e85af : sqrdmlah v15.4h, v13.4h, v14.4h : sqrdmlah %d13 %d14 $0x01 -> %d15 -2e538654 : sqrdmlah v20.4h, v18.4h, v19.4h : sqrdmlah %d18 %d19 $0x01 -> %d20 -2e5886f9 : sqrdmlah v25.4h, v23.4h, v24.4h : sqrdmlah %d23 %d24 $0x01 -> %d25 -2e5d879e : sqrdmlah v30.4h, v28.4h, v29.4h : sqrdmlah %d28 %d29 $0x01 -> %d30 -6e428420 : sqrdmlah v0.8h, v1.8h, v2.8h : sqrdmlah %q1 %q2 $0x01 -> %q0 -6e448465 : sqrdmlah v5.8h, v3.8h, v4.8h : sqrdmlah %q3 %q4 $0x01 -> %q5 -6e49850a : sqrdmlah v10.8h, v8.8h, v9.8h : sqrdmlah %q8 %q9 $0x01 -> %q10 -6e4e85af : sqrdmlah v15.8h, v13.8h, v14.8h : sqrdmlah %q13 %q14 $0x01 -> %q15 -6e538654 : sqrdmlah v20.8h, v18.8h, v19.8h : sqrdmlah %q18 %q19 $0x01 -> %q20 -6e5886f9 : sqrdmlah v25.8h, v23.8h, v24.8h : sqrdmlah %q23 %q24 $0x01 -> %q25 -6e5d879e : sqrdmlah v30.8h, v28.8h, v29.8h : sqrdmlah %q28 %q29 $0x01 -> %q30 -2e828420 : sqrdmlah v0.2s, v1.2s, v2.2s : sqrdmlah %d1 %d2 $0x02 -> %d0 -2e848465 : sqrdmlah v5.2s, v3.2s, v4.2s : sqrdmlah %d3 %d4 $0x02 -> %d5 -2e89850a : sqrdmlah v10.2s, v8.2s, v9.2s : sqrdmlah %d8 %d9 $0x02 -> %d10 -2e8e85af : sqrdmlah v15.2s, v13.2s, v14.2s : sqrdmlah %d13 %d14 $0x02 -> %d15 -2e938654 : sqrdmlah v20.2s, v18.2s, v19.2s : sqrdmlah %d18 %d19 $0x02 -> %d20 -2e9886f9 : sqrdmlah v25.2s, v23.2s, v24.2s : sqrdmlah %d23 %d24 $0x02 -> %d25 -2e9d879e : sqrdmlah v30.2s, v28.2s, v29.2s : sqrdmlah %d28 %d29 $0x02 -> %d30 -6e828420 : sqrdmlah v0.4s, v1.4s, v2.4s : sqrdmlah %q1 %q2 $0x02 -> %q0 -6e848465 : sqrdmlah v5.4s, v3.4s, v4.4s : sqrdmlah %q3 %q4 $0x02 -> %q5 -6e89850a : sqrdmlah v10.4s, v8.4s, v9.4s : sqrdmlah %q8 %q9 $0x02 -> %q10 -6e8e85af : sqrdmlah v15.4s, v13.4s, v14.4s : sqrdmlah %q13 %q14 $0x02 -> %q15 -6e938654 : sqrdmlah v20.4s, v18.4s, v19.4s : sqrdmlah %q18 %q19 $0x02 -> %q20 -6e9886f9 : sqrdmlah v25.4s, v23.4s, v24.4s : sqrdmlah %q23 %q24 $0x02 -> %q25 -6e9d879e : sqrdmlah v30.4s, v28.4s, v29.4s : sqrdmlah %q28 %q29 $0x02 -> %q30 +2e428420 : sqrdmlah v0.4h, v1.4h, v2.4h : sqrdmlah %d0 %d1 %d2 $0x01 -> %d0 +2e448465 : sqrdmlah v5.4h, v3.4h, v4.4h : sqrdmlah %d5 %d3 %d4 $0x01 -> %d5 +2e49850a : sqrdmlah v10.4h, v8.4h, v9.4h : sqrdmlah %d10 %d8 %d9 $0x01 -> %d10 +2e4e85af : sqrdmlah v15.4h, v13.4h, v14.4h : sqrdmlah %d15 %d13 %d14 $0x01 -> %d15 +2e538654 : sqrdmlah v20.4h, v18.4h, v19.4h : sqrdmlah %d20 %d18 %d19 $0x01 -> %d20 +2e5886f9 : sqrdmlah v25.4h, v23.4h, v24.4h : sqrdmlah %d25 %d23 %d24 $0x01 -> %d25 +2e5d879e : sqrdmlah v30.4h, v28.4h, v29.4h : sqrdmlah %d30 %d28 %d29 $0x01 -> %d30 +6e428420 : sqrdmlah v0.8h, v1.8h, v2.8h : sqrdmlah %q0 %q1 %q2 $0x01 -> %q0 +6e448465 : sqrdmlah v5.8h, v3.8h, v4.8h : sqrdmlah %q5 %q3 %q4 $0x01 -> %q5 +6e49850a : sqrdmlah v10.8h, v8.8h, v9.8h : sqrdmlah %q10 %q8 %q9 $0x01 -> %q10 +6e4e85af : sqrdmlah v15.8h, v13.8h, v14.8h : sqrdmlah %q15 %q13 %q14 $0x01 -> %q15 +6e538654 : sqrdmlah v20.8h, v18.8h, v19.8h : sqrdmlah %q20 %q18 %q19 $0x01 -> %q20 +6e5886f9 : sqrdmlah v25.8h, v23.8h, v24.8h : sqrdmlah %q25 %q23 %q24 $0x01 -> %q25 +6e5d879e : sqrdmlah v30.8h, v28.8h, v29.8h : sqrdmlah %q30 %q28 %q29 $0x01 -> %q30 +2e828420 : sqrdmlah v0.2s, v1.2s, v2.2s : sqrdmlah %d0 %d1 %d2 $0x02 -> %d0 +2e848465 : sqrdmlah v5.2s, v3.2s, v4.2s : sqrdmlah %d5 %d3 %d4 $0x02 -> %d5 +2e89850a : sqrdmlah v10.2s, v8.2s, v9.2s : sqrdmlah %d10 %d8 %d9 $0x02 -> %d10 +2e8e85af : sqrdmlah v15.2s, v13.2s, v14.2s : sqrdmlah %d15 %d13 %d14 $0x02 -> %d15 +2e938654 : sqrdmlah v20.2s, v18.2s, v19.2s : sqrdmlah %d20 %d18 %d19 $0x02 -> %d20 +2e9886f9 : sqrdmlah v25.2s, v23.2s, v24.2s : sqrdmlah %d25 %d23 %d24 $0x02 -> %d25 +2e9d879e : sqrdmlah v30.2s, v28.2s, v29.2s : sqrdmlah %d30 %d28 %d29 $0x02 -> %d30 +6e828420 : sqrdmlah v0.4s, v1.4s, v2.4s : sqrdmlah %q0 %q1 %q2 $0x02 -> %q0 +6e848465 : sqrdmlah v5.4s, v3.4s, v4.4s : sqrdmlah %q5 %q3 %q4 $0x02 -> %q5 +6e89850a : sqrdmlah v10.4s, v8.4s, v9.4s : sqrdmlah %q10 %q8 %q9 $0x02 -> %q10 +6e8e85af : sqrdmlah v15.4s, v13.4s, v14.4s : sqrdmlah %q15 %q13 %q14 $0x02 -> %q15 +6e938654 : sqrdmlah v20.4s, v18.4s, v19.4s : sqrdmlah %q20 %q18 %q19 $0x02 -> %q20 +6e9886f9 : sqrdmlah v25.4s, v23.4s, v24.4s : sqrdmlah %q25 %q23 %q24 $0x02 -> %q25 +6e9d879e : sqrdmlah v30.4s, v28.4s, v29.4s : sqrdmlah %q30 %q28 %q29 $0x02 -> %q30 # SQRDMLAH , , .[] -7f42d020 : sqrdmlah h0, h1, v2.h[0] : sqrdmlah %h1 %q2 $0x00 $0x01 -> %h0 -7f52d020 : sqrdmlah h0, h1, v2.h[1] : sqrdmlah %h1 %q2 $0x01 $0x01 -> %h0 -7f62d020 : sqrdmlah h0, h1, v2.h[2] : sqrdmlah %h1 %q2 $0x02 $0x01 -> %h0 -7f72d020 : sqrdmlah h0, h1, v2.h[3] : sqrdmlah %h1 %q2 $0x03 $0x01 -> %h0 -7f42d820 : sqrdmlah h0, h1, v2.h[4] : sqrdmlah %h1 %q2 $0x04 $0x01 -> %h0 -7f52d820 : sqrdmlah h0, h1, v2.h[5] : sqrdmlah %h1 %q2 $0x05 $0x01 -> %h0 -7f62d820 : sqrdmlah h0, h1, v2.h[6] : sqrdmlah %h1 %q2 $0x06 $0x01 -> %h0 -7f72d820 : sqrdmlah h0, h1, v2.h[7] : sqrdmlah %h1 %q2 $0x07 $0x01 -> %h0 -7f82d020 : sqrdmlah s0, s1, v2.s[0] : sqrdmlah %s1 %q2 $0x00 $0x02 -> %s0 -7fa2d020 : sqrdmlah s0, s1, v2.s[1] : sqrdmlah %s1 %q2 $0x01 $0x02 -> %s0 -7f82d820 : sqrdmlah s0, s1, v2.s[2] : sqrdmlah %s1 %q2 $0x02 $0x02 -> %s0 -7fa2d820 : sqrdmlah s0, s1, v2.s[3] : sqrdmlah %s1 %q2 $0x03 $0x02 -> %s0 +7f42d020 : sqrdmlah h0, h1, v2.h[0] : sqrdmlah %h0 %h1 %q2 $0x00 $0x01 -> %h0 +7f52d020 : sqrdmlah h0, h1, v2.h[1] : sqrdmlah %h0 %h1 %q2 $0x01 $0x01 -> %h0 +7f62d020 : sqrdmlah h0, h1, v2.h[2] : sqrdmlah %h0 %h1 %q2 $0x02 $0x01 -> %h0 +7f72d020 : sqrdmlah h0, h1, v2.h[3] : sqrdmlah %h0 %h1 %q2 $0x03 $0x01 -> %h0 +7f42d820 : sqrdmlah h0, h1, v2.h[4] : sqrdmlah %h0 %h1 %q2 $0x04 $0x01 -> %h0 +7f52d820 : sqrdmlah h0, h1, v2.h[5] : sqrdmlah %h0 %h1 %q2 $0x05 $0x01 -> %h0 +7f62d820 : sqrdmlah h0, h1, v2.h[6] : sqrdmlah %h0 %h1 %q2 $0x06 $0x01 -> %h0 +7f72d820 : sqrdmlah h0, h1, v2.h[7] : sqrdmlah %h0 %h1 %q2 $0x07 $0x01 -> %h0 +7f82d020 : sqrdmlah s0, s1, v2.s[0] : sqrdmlah %s0 %s1 %q2 $0x00 $0x02 -> %s0 +7fa2d020 : sqrdmlah s0, s1, v2.s[1] : sqrdmlah %s0 %s1 %q2 $0x01 $0x02 -> %s0 +7f82d820 : sqrdmlah s0, s1, v2.s[2] : sqrdmlah %s0 %s1 %q2 $0x02 $0x02 -> %s0 +7fa2d820 : sqrdmlah s0, s1, v2.s[3] : sqrdmlah %s0 %s1 %q2 $0x03 $0x02 -> %s0 # SQRDMLAH ., ., .[] -2f42d020 : sqrdmlah v0.4h, v1.4h, v2.h[0] : sqrdmlah %d1 %d2 $0x00 $0x01 -> %d0 -2f52d020 : sqrdmlah v0.4h, v1.4h, v2.h[1] : sqrdmlah %d1 %d2 $0x01 $0x01 -> %d0 -2f62d020 : sqrdmlah v0.4h, v1.4h, v2.h[2] : sqrdmlah %d1 %d2 $0x02 $0x01 -> %d0 -2f72d020 : sqrdmlah v0.4h, v1.4h, v2.h[3] : sqrdmlah %d1 %d2 $0x03 $0x01 -> %d0 -2f42d820 : sqrdmlah v0.4h, v1.4h, v2.h[4] : sqrdmlah %d1 %d2 $0x04 $0x01 -> %d0 -2f52d820 : sqrdmlah v0.4h, v1.4h, v2.h[5] : sqrdmlah %d1 %d2 $0x05 $0x01 -> %d0 -2f62d820 : sqrdmlah v0.4h, v1.4h, v2.h[6] : sqrdmlah %d1 %d2 $0x06 $0x01 -> %d0 -2f72d820 : sqrdmlah v0.4h, v1.4h, v2.h[7] : sqrdmlah %d1 %d2 $0x07 $0x01 -> %d0 -2f79d90a : sqrdmlah v10.4h, v8.4h, v9.h[7] : sqrdmlah %d8 %d9 $0x07 $0x01 -> %d10 -2f7ed9af : sqrdmlah v15.4h, v13.4h, v14.h[7] : sqrdmlah %d13 %d14 $0x07 $0x01 -> %d15 -6f42d020 : sqrdmlah v0.8h, v1.8h, v2.h[0] : sqrdmlah %q1 %q2 $0x00 $0x01 -> %q0 -6f52d020 : sqrdmlah v0.8h, v1.8h, v2.h[1] : sqrdmlah %q1 %q2 $0x01 $0x01 -> %q0 -6f62d020 : sqrdmlah v0.8h, v1.8h, v2.h[2] : sqrdmlah %q1 %q2 $0x02 $0x01 -> %q0 -6f72d020 : sqrdmlah v0.8h, v1.8h, v2.h[3] : sqrdmlah %q1 %q2 $0x03 $0x01 -> %q0 -6f42d820 : sqrdmlah v0.8h, v1.8h, v2.h[4] : sqrdmlah %q1 %q2 $0x04 $0x01 -> %q0 -6f52d820 : sqrdmlah v0.8h, v1.8h, v2.h[5] : sqrdmlah %q1 %q2 $0x05 $0x01 -> %q0 -6f62d820 : sqrdmlah v0.8h, v1.8h, v2.h[6] : sqrdmlah %q1 %q2 $0x06 $0x01 -> %q0 -6f72d820 : sqrdmlah v0.8h, v1.8h, v2.h[7] : sqrdmlah %q1 %q2 $0x07 $0x01 -> %q0 -6f79d90a : sqrdmlah v10.8h, v8.8h, v9.h[7] : sqrdmlah %q8 %q9 $0x07 $0x01 -> %q10 -6f7ed9af : sqrdmlah v15.8h, v13.8h, v14.h[7] : sqrdmlah %q13 %q14 $0x07 $0x01 -> %q15 -2f82d020 : sqrdmlah v0.2s, v1.2s, v2.s[0] : sqrdmlah %d1 %d2 $0x00 $0x02 -> %d0 -2fa2d020 : sqrdmlah v0.2s, v1.2s, v2.s[1] : sqrdmlah %d1 %d2 $0x01 $0x02 -> %d0 -2f82d820 : sqrdmlah v0.2s, v1.2s, v2.s[2] : sqrdmlah %d1 %d2 $0x02 $0x02 -> %d0 -2fa2d820 : sqrdmlah v0.2s, v1.2s, v2.s[3] : sqrdmlah %d1 %d2 $0x03 $0x02 -> %d0 -2fa9d90a : sqrdmlah v10.2s, v8.2s, v9.s[3] : sqrdmlah %d8 %d9 $0x03 $0x02 -> %d10 -2fb3da54 : sqrdmlah v20.2s, v18.2s, v19.s[3] : sqrdmlah %d18 %d19 $0x03 $0x02 -> %d20 -2fbddb9e : sqrdmlah v30.2s, v28.2s, v29.s[3] : sqrdmlah %d28 %d29 $0x03 $0x02 -> %d30 -6f82d020 : sqrdmlah v0.4s, v1.4s, v2.s[0] : sqrdmlah %q1 %q2 $0x00 $0x02 -> %q0 -6fa2d020 : sqrdmlah v0.4s, v1.4s, v2.s[1] : sqrdmlah %q1 %q2 $0x01 $0x02 -> %q0 -6f82d820 : sqrdmlah v0.4s, v1.4s, v2.s[2] : sqrdmlah %q1 %q2 $0x02 $0x02 -> %q0 -6fa2d820 : sqrdmlah v0.4s, v1.4s, v2.s[3] : sqrdmlah %q1 %q2 $0x03 $0x02 -> %q0 -6fa9d90a : sqrdmlah v10.4s, v8.4s, v9.s[3] : sqrdmlah %q8 %q9 $0x03 $0x02 -> %q10 -6fb3da54 : sqrdmlah v20.4s, v18.4s, v19.s[3] : sqrdmlah %q18 %q19 $0x03 $0x02 -> %q20 -6fbddb9e : sqrdmlah v30.4s, v28.4s, v29.s[3] : sqrdmlah %q28 %q29 $0x03 $0x02 -> %q30 +2f42d020 : sqrdmlah v0.4h, v1.4h, v2.h[0] : sqrdmlah %d0 %d1 %d2 $0x00 $0x01 -> %d0 +2f52d020 : sqrdmlah v0.4h, v1.4h, v2.h[1] : sqrdmlah %d0 %d1 %d2 $0x01 $0x01 -> %d0 +2f62d020 : sqrdmlah v0.4h, v1.4h, v2.h[2] : sqrdmlah %d0 %d1 %d2 $0x02 $0x01 -> %d0 +2f72d020 : sqrdmlah v0.4h, v1.4h, v2.h[3] : sqrdmlah %d0 %d1 %d2 $0x03 $0x01 -> %d0 +2f42d820 : sqrdmlah v0.4h, v1.4h, v2.h[4] : sqrdmlah %d0 %d1 %d2 $0x04 $0x01 -> %d0 +2f52d820 : sqrdmlah v0.4h, v1.4h, v2.h[5] : sqrdmlah %d0 %d1 %d2 $0x05 $0x01 -> %d0 +2f62d820 : sqrdmlah v0.4h, v1.4h, v2.h[6] : sqrdmlah %d0 %d1 %d2 $0x06 $0x01 -> %d0 +2f72d820 : sqrdmlah v0.4h, v1.4h, v2.h[7] : sqrdmlah %d0 %d1 %d2 $0x07 $0x01 -> %d0 +2f79d90a : sqrdmlah v10.4h, v8.4h, v9.h[7] : sqrdmlah %d10 %d8 %d9 $0x07 $0x01 -> %d10 +2f7ed9af : sqrdmlah v15.4h, v13.4h, v14.h[7] : sqrdmlah %d15 %d13 %d14 $0x07 $0x01 -> %d15 +6f42d020 : sqrdmlah v0.8h, v1.8h, v2.h[0] : sqrdmlah %q0 %q1 %q2 $0x00 $0x01 -> %q0 +6f52d020 : sqrdmlah v0.8h, v1.8h, v2.h[1] : sqrdmlah %q0 %q1 %q2 $0x01 $0x01 -> %q0 +6f62d020 : sqrdmlah v0.8h, v1.8h, v2.h[2] : sqrdmlah %q0 %q1 %q2 $0x02 $0x01 -> %q0 +6f72d020 : sqrdmlah v0.8h, v1.8h, v2.h[3] : sqrdmlah %q0 %q1 %q2 $0x03 $0x01 -> %q0 +6f42d820 : sqrdmlah v0.8h, v1.8h, v2.h[4] : sqrdmlah %q0 %q1 %q2 $0x04 $0x01 -> %q0 +6f52d820 : sqrdmlah v0.8h, v1.8h, v2.h[5] : sqrdmlah %q0 %q1 %q2 $0x05 $0x01 -> %q0 +6f62d820 : sqrdmlah v0.8h, v1.8h, v2.h[6] : sqrdmlah %q0 %q1 %q2 $0x06 $0x01 -> %q0 +6f72d820 : sqrdmlah v0.8h, v1.8h, v2.h[7] : sqrdmlah %q0 %q1 %q2 $0x07 $0x01 -> %q0 +6f79d90a : sqrdmlah v10.8h, v8.8h, v9.h[7] : sqrdmlah %q10 %q8 %q9 $0x07 $0x01 -> %q10 +6f7ed9af : sqrdmlah v15.8h, v13.8h, v14.h[7] : sqrdmlah %q15 %q13 %q14 $0x07 $0x01 -> %q15 +2f82d020 : sqrdmlah v0.2s, v1.2s, v2.s[0] : sqrdmlah %d0 %d1 %d2 $0x00 $0x02 -> %d0 +2fa2d020 : sqrdmlah v0.2s, v1.2s, v2.s[1] : sqrdmlah %d0 %d1 %d2 $0x01 $0x02 -> %d0 +2f82d820 : sqrdmlah v0.2s, v1.2s, v2.s[2] : sqrdmlah %d0 %d1 %d2 $0x02 $0x02 -> %d0 +2fa2d820 : sqrdmlah v0.2s, v1.2s, v2.s[3] : sqrdmlah %d0 %d1 %d2 $0x03 $0x02 -> %d0 +2fa9d90a : sqrdmlah v10.2s, v8.2s, v9.s[3] : sqrdmlah %d10 %d8 %d9 $0x03 $0x02 -> %d10 +2fb3da54 : sqrdmlah v20.2s, v18.2s, v19.s[3] : sqrdmlah %d20 %d18 %d19 $0x03 $0x02 -> %d20 +2fbddb9e : sqrdmlah v30.2s, v28.2s, v29.s[3] : sqrdmlah %d30 %d28 %d29 $0x03 $0x02 -> %d30 +6f82d020 : sqrdmlah v0.4s, v1.4s, v2.s[0] : sqrdmlah %q0 %q1 %q2 $0x00 $0x02 -> %q0 +6fa2d020 : sqrdmlah v0.4s, v1.4s, v2.s[1] : sqrdmlah %q0 %q1 %q2 $0x01 $0x02 -> %q0 +6f82d820 : sqrdmlah v0.4s, v1.4s, v2.s[2] : sqrdmlah %q0 %q1 %q2 $0x02 $0x02 -> %q0 +6fa2d820 : sqrdmlah v0.4s, v1.4s, v2.s[3] : sqrdmlah %q0 %q1 %q2 $0x03 $0x02 -> %q0 +6fa9d90a : sqrdmlah v10.4s, v8.4s, v9.s[3] : sqrdmlah %q10 %q8 %q9 $0x03 $0x02 -> %q10 +6fb3da54 : sqrdmlah v20.4s, v18.4s, v19.s[3] : sqrdmlah %q20 %q18 %q19 $0x03 $0x02 -> %q20 +6fbddb9e : sqrdmlah v30.4s, v28.4s, v29.s[3] : sqrdmlah %q30 %q28 %q29 $0x03 $0x02 -> %q30 # SQNEG , 7e207820 : sqneg b0, b1 : sqneg %b1 -> %b0