[pull] master from chipsalliance:master #2
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(cherry picked from commit a8663bc)
This makes it a bit easier to use the StoreGen circuit. StoreGen shouldn't error if the `typ` argument is narrower than `maxSize` would normally permit. (cherry picked from commit 9a416a1)
(cherry picked from commit ec106af)
(cherry picked from commit 1d69e6d)
Suppress SourceShrinker require if no shrinking is to be done (copy #3485)
Make StoreGen support narrow typ field (copy #3479)
Fix Makefrag for mill cross-compile (backport #3489)
Connect all s1_data fields in SimpleHellaIF (backport #3497)
(cherry picked from commit d477572)
* Remove vsim/emulator flows, add simple make verilog flowx * Remove unnecessary dependencies from Makefile' (cherry picked from commit 4a1715e)
Remove SCIE interface (backport #3499)
Remove vsim/emulator flows, add simple make verilog flow (backport #3494)
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