From 72ef4bc650017c86b7be8b8b6fd95a624714787e Mon Sep 17 00:00:00 2001 From: GitHub Action test Date: Thu, 2 Nov 2023 12:11:32 +0000 Subject: [PATCH] Automatic English texts updated --- locale/translation.js | 50 +++++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 30 deletions(-) diff --git a/locale/translation.js b/locale/translation.js index 543a5be..eeab727 100644 --- a/locale/translation.js +++ b/locale/translation.js @@ -145,17 +145,8 @@ gettext('01-Sys-DFF-initial-pulse'); gettext('01-Sys-DFF-initial-pulse'); gettext('01-Sys-DFF-initial-pulse'); gettext('01-Sys-DFF-initial-pulse'); -gettext('System - D Flip-flop. Capture data every system clock cycle'); -gettext('RS-FF-set. RS Flip-flop with priority set'); -gettext('D Flip-flop (verilog implementation)'); -gettext('SReg-right-x4: 4 bits Shift register (to the right)'); -gettext('Reg: 1-Bit register'); -gettext('2-to-1 Multplexer (1-bit channels). Fippled version'); -gettext('Bus4-Join-all: Join all the wires into a 4-bits Bus'); -gettext('DFF-02: Two D flip-flops in paralell'); gettext('4bits constant value: 0'); gettext('Generic: 4-bits generic constant (0-15)'); -gettext('# D Flip-Flop \n\nIt stores the input data that arrives at cycle n \nIts output is shown in the cycle n+1'); gettext('Alhambra-II'); gettext('Nandland-go-board'); gettext('ULX3S-12F'); @@ -185,8 +176,6 @@ gettext('03-Sys-DFF-rst'); gettext('03-Sys-DFF-rst'); gettext('03-Sys-DFF-rst'); gettext('03-Sys-DFF-rst'); -gettext('DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is set to it initial value'); -gettext('Reset input: Active high \nWhen rst = 1, the DFF is set to its initial value'); gettext('Alhambra-II'); gettext('Nandland-go-board'); gettext('ULX3S-12F'); @@ -211,6 +200,7 @@ gettext('Adder-8bits: Adder of two operands of 8 bits'); gettext('Bus8-Split-half: Split the 8-bits bus into two buses of the same size'); gettext('Adder-4bits: Adder of two operands of 4 bits'); gettext('Bus4-Split-all: Split the 4-bits bus into its wires'); +gettext('Bus4-Join-all: Join all the wires into a 4-bits Bus'); gettext('Bus8-Join-half: Join the two same halves into an 8-bits Bus'); gettext('AdderC-4bits: Adder of two operands of 4 bits and Carry in'); gettext('AdderC-8bits: Adder of two operands of 8 bits and Carry in'); @@ -254,18 +244,6 @@ gettext('Button-tic: Configurable button that emits a tic when it is pressed. EC gettext('Configurable button (pull-up on/off. Not on/off). ECP5 FPGA family'); gettext('04-DFF-button-LED'); gettext('04-DFF-button-LED'); -gettext('DFF: D flip-flop with load input'); -gettext('Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input'); -gettext('1bit register (implemented in verilog)'); -gettext('DFF-rst-x16: 16 D flip-flops in paralell with reset'); -gettext('DFF-rst-x04: Three D flip-flops in paralell with reset'); -gettext('DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0'); -gettext('Bus16-Split-quarter: Split the 16-bits bus into four buses of the same size'); -gettext('Bus16-Join-quarter: Join the four same buses into an 16-bits Bus'); -gettext('Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input'); -gettext('Sync 1-bit input with the system clock domain'); -gettext('Initial value'); -gettext('Reset input: Active high \nWhen rst = 1, the DFF is reset to 0'); gettext('Alhambra-II'); gettext('Nandland-go-board'); gettext('ULX3S-12F'); @@ -277,8 +255,6 @@ gettext('05-DFF-rst-buttons-LED'); gettext('05-DFF-rst-buttons-LED'); gettext('05-DFF-rst-buttons-LED'); gettext('05-DFF-rst-buttons-LED'); -gettext('D Flip-Flop with load and reset'); -gettext('Syste DFF'); gettext('Alhambra-II'); gettext('Nandland-go-board'); gettext('ULX3S-12F'); @@ -317,7 +293,6 @@ gettext('07-Sys-TFF-rst-Test'); gettext('07-Sys-TFF-rst-Test'); gettext('07-Sys-TFF-rst-Test'); gettext('07-Sys-TFF-rst-Test'); -gettext('System TFF with reset: It toogles its output on every system cycle'); gettext('Alhambra-II'); gettext('Nandland-go-board'); gettext('ULX3S-12F'); @@ -330,7 +305,6 @@ gettext('08-TFF-button-LED'); gettext('08-TFF-button-LED'); gettext('08-TFF-button-LED'); gettext('08-TFF-button-LED'); -gettext('System TFF with toggle input: It toogles on every system cycle if the input is active'); gettext('Alhambra-II'); gettext('Nandland-go-board'); gettext('ULX3S-12F'); @@ -343,7 +317,6 @@ gettext('09-TFF-rst-buttons-LED'); gettext('09-TFF-rst-buttons-LED'); gettext('09-TFF-rst-buttons-LED'); gettext('09-TFF-rst-buttons-LED'); -gettext('System TFF with toggle input and reset: It toogles on every system cycle if the input is active'); gettext('Alhambra-II'); gettext('Nandland-go-board'); gettext('ULX3S-12F'); @@ -355,7 +328,6 @@ gettext('10-RS-FF-set-priority-Manual-testing'); gettext('10-RS-FF-set-priority-Manual-testing'); gettext('10-RS-FF-set-priority-Manual-testing'); gettext('10-RS-FF-set-priority-Manual-testing'); -gettext('Priority on set'); gettext('Alhambra-II'); gettext('Nandlang-go-board'); gettext('ULX3S-12F'); @@ -367,7 +339,6 @@ gettext('11-RS-FF-reset-priority-Manual-testing'); gettext('11-RS-FF-reset-priority-Manual-testing'); gettext('11-RS-FF-reset-priority-Manual-testing'); gettext('11-RS-FF-reset-priority-Manual-testing'); -gettext('RS-FF-reset. RS Flip-flop with priority reset'); gettext('DFFs'); gettext('RS-FFs'); gettext('TFFs'); @@ -380,14 +351,33 @@ gettext('Sys-DFF-rst'); gettext('Alhambra-II'); gettext('Alhambra-II'); gettext('Manual-testing'); +gettext('Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input'); +gettext('D Flip-flop (verilog implementation)'); +gettext('1bit register (implemented in verilog)'); +gettext('DFF-rst-x16: 16 D flip-flops in paralell with reset'); +gettext('DFF-rst-x04: Three D flip-flops in paralell with reset'); +gettext('DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0'); +gettext('Bus16-Split-quarter: Split the 16-bits bus into four buses of the same size'); +gettext('Bus16-Join-quarter: Join the four same buses into an 16-bits Bus'); +gettext('Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input'); +gettext('Sync 1-bit input with the system clock domain'); gettext('## DFF-rst: Manual testing\n'); +gettext('# D Flip-Flop \n\nIt stores the input data that arrives at cycle n \nIts output is shown in the cycle n+1'); +gettext('Initial value'); +gettext('Reset input: Active high \nWhen rst = 1, the DFF is reset to 0'); gettext('01-manual-testing'); gettext('## DFF: Manual testing\n'); gettext('Alhambra-II'); gettext('Alhambra-II'); gettext('Alhambra-II'); gettext('01-manual-testing'); +gettext('RS-FF-set. RS Flip-flop with priority set'); +gettext('SReg-right-x4: 4 bits Shift register (to the right)'); +gettext('Reg: 1-Bit register'); +gettext('2-to-1 Multplexer (1-bit channels). Fippled version'); +gettext('DFF-02: Two D flip-flops in paralell'); gettext('start: Start signal: It goes from 1 to 0 when the system clock starts. 1 cycle pulse witch'); +gettext('System - D Flip-flop. Capture data every system clock cycle'); gettext('## Sys-DFF-ld-rst: Manual testing\n\nThe expected ouput of this circuit is 1,0,1,1. It is shown \non the LEDs'); gettext('Initial value: 1'); gettext('Initial value: 0');