diff --git a/llvm/README.txt b/llvm/README.txt index b9b71a3b6daff1..1598d75b02c11f 100644 --- a/llvm/README.txt +++ b/llvm/README.txt @@ -15,3 +15,6 @@ documentation setup. If you are writing a package for LLVM, see docs/Packaging.rst for our suggestions. + +Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +Notified per clause 4(b) of the license. diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake index 2bbf81ec8e7636..471f6bf8961693 100644 --- a/llvm/cmake/modules/AddLLVM.cmake +++ b/llvm/cmake/modules/AddLLVM.cmake @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. include(GNUInstallDirs) include(LLVMDistributionSupport) include(LLVMProcessSources) diff --git a/llvm/cmake/modules/GetErrcMessages.cmake b/llvm/cmake/modules/GetErrcMessages.cmake index 2d9848ef5a8dd2..2b57d48217f8c4 100644 --- a/llvm/cmake/modules/GetErrcMessages.cmake +++ b/llvm/cmake/modules/GetErrcMessages.cmake @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # This function returns the messages of various POSIX error codes as they are returned by std::error_code. # The purpose of this function is to supply those error messages to llvm-lit using the errc_messages config. # Currently supplied and needed error codes: ENOENT, EISDIR, EINVAL and EACCES. diff --git a/llvm/cmake/modules/HandleLLVMOptions.cmake b/llvm/cmake/modules/HandleLLVMOptions.cmake index e0fde49d963bdf..5d00b2925d76ab 100644 --- a/llvm/cmake/modules/HandleLLVMOptions.cmake +++ b/llvm/cmake/modules/HandleLLVMOptions.cmake @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # This CMake module is responsible for interpreting the user defined LLVM_ # options and executing the appropriate CMake commands to realize the users' # selections. diff --git a/llvm/include/llvm/Config/llvm-config.h.cmake b/llvm/include/llvm/Config/llvm-config.h.cmake index fdfe86880a91af..f0246a52bf7598 100644 --- a/llvm/include/llvm/Config/llvm-config.h.cmake +++ b/llvm/include/llvm/Config/llvm-config.h.cmake @@ -4,6 +4,8 @@ /* Exceptions. */ /* See https://llvm.org/LICENSE.txt for license information. */ /* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception */ +/* Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. */ +/* Notified per clause 4(b) of the license. */ /* */ /*===----------------------------------------------------------------------===*/ diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index ee7dec4452000b..8b3cd4d7c6efec 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Analysis/DemandedBits.cpp b/llvm/lib/Analysis/DemandedBits.cpp index 66ebfde9f0dccc..e9e00fcf534d63 100644 --- a/llvm/lib/Analysis/DemandedBits.cpp +++ b/llvm/lib/Analysis/DemandedBits.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 52a1d576adc28a..b3aa8154070b08 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // /// \file //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td index fdc9e4ecf59c5f..63f62bf6a8d34b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp b/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp index aaf35f4f3796a8..2312431a50127d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUConditionalDiscard.cpp @@ -4,6 +4,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // @@ -68,19 +70,25 @@ using namespace llvm; using namespace llvm::AMDGPU; +namespace llvm { +namespace cl { + // Enable conditional discard transformations -static cl::opt EnableConditionalDiscardTransformations( +opt EnableConditionalDiscardTransformations( "amdgpu-conditional-discard-transformations", - cl::desc("Enable conditional discard transformations"), - cl::init(false), - cl::Hidden); + desc("Enable conditional discard transformations"), + init(false), + Hidden); // Enable conditional discard to demote transformations -static cl::opt EnableTransformDiscardToDemote( +opt EnableTransformDiscardToDemote( "amdgpu-transform-discard-to-demote", - cl::desc("Enable transformation of optimized discards to demotes"), - cl::init(false), - cl::Hidden); + desc("Enable transformation of optimized discards to demotes"), + init(false), + Hidden); + +} // namespace cl +} // namespace llvm namespace { @@ -225,12 +233,12 @@ bool AMDGPUConditionalDiscard::runOnFunction(Function &F) { if (skipFunction(F)) return false; - if (!(EnableConditionalDiscardTransformations || + if (!(cl::EnableConditionalDiscardTransformations || F.hasFnAttribute("amdgpu-conditional-discard-transformations"))) return false; bool ConvertToDemote = - (EnableTransformDiscardToDemote || + (cl::EnableTransformDiscardToDemote || F.hasFnAttribute("amdgpu-transform-discard-to-demote")); LI = &getAnalysis().getLoopInfo(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 7e08abe0495c38..a463f9ac310d8e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 9ae3b32b5369d9..35f9223a962423 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp index 54f75b46af3e17..84ca97312e74fb 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td index 0b9fccec463da0..d6bdddfb50895b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index fe47a0cb530899..2737eafd107a6b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// /// \file diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp index b4e8fea0925b3a..a4710b7b546e04 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp index 811f6104eeda2b..36cd5c6ec611ce 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h index 8ce9fdc77e186c..adbe02ea8c093b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegPressAnalysis.h @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 6997a9e5a2b9be..07f10724580b41 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// /// \file diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index def13dad166943..4c6c19c90c262a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index 0daec68d1dbf84..474fe404f6b223 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index be17cb4d2ee769..daa6e3debd943c 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. add_llvm_component_group(AMDGPU) set(LLVM_TARGET_DEFINITIONS AMDGPU.td) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 7d96f686aeab71..ad468a19adbeb7 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp index 8209668ecd4693..1bd4214167e9db 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaterfall.cpp @@ -4,6 +4,8 @@ // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index a2baf622f5e77d..82e66dcfa50522 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // This file was originally auto-generated from a GPU register header file and diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index ca3c12cec1c2ba..6d7e09ac49d8ca 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp index 6ad54acdf71dbb..1fb2678285b9d8 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 0f51e3bf06296d..14512e80dc1d49 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp index da6fa2279841de..3636520d0f6360 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Transforms/Scalar/ADCE.cpp b/llvm/lib/Transforms/Scalar/ADCE.cpp index c6f7f281c127ab..049279cc73b8ca 100644 --- a/llvm/lib/Transforms/Scalar/ADCE.cpp +++ b/llvm/lib/Transforms/Scalar/ADCE.cpp @@ -3,6 +3,8 @@ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +// Notified per clause 4(b) of the license. // //===----------------------------------------------------------------------===// // diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll index 286acb6b330908..cbfe08a86dfb70 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.waterfall.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX10,VI %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX10,GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir index 5b79c1ca255ac9..160b8aca5c64a4 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-removed-undef-copy.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s # # This is another example of a test giving "Couldn't join subrange!" diff --git a/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll b/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll index c677b48e69f0e2..1ee03b23f6d9e7 100644 --- a/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll +++ b/llvm/test/CodeGen/AMDGPU/discard-optimization-fn-attr.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc --march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,KILL,DEMOTE %s ; Check that the branch is removed by the discard opt. diff --git a/llvm/test/CodeGen/AMDGPU/discard-optimization.ll b/llvm/test/CodeGen/AMDGPU/discard-optimization.ll index e4f332ff967b1b..aa34de486f6c96 100644 --- a/llvm/test/CodeGen/AMDGPU/discard-optimization.ll +++ b/llvm/test/CodeGen/AMDGPU/discard-optimization.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -amdgpu-conditional-discard-transformations=1 --march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,KILL %s ; RUN: llc -amdgpu-conditional-discard-transformations=1 -amdgpu-transform-discard-to-demote --march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,DEMOTE %s ; RUN: llc -amdgpu-conditional-discard-transformations=1 --march=amdgcn -mcpu=gfx900 -stop-after=amdgpu-conditional-discard < %s | FileCheck -check-prefix=GCN-IR %s diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll index 5d684a52ef028e..8bc24b52b97873 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; When EXPENSIVE_CHECKS are enabled, the machine verifier appears between each ; pass. Ignore it with 'grep -v'. ; fixme: the following line is added to cleanup bots, will be removed in weeks. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll index 386dc99eadc3bb..f1ae25c8d4a1a1 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SI ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SI ;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=GFX10 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll index 83d8748600eda8..5565919e99dbdc 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waterfall.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX10,VI %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX10,GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll index 0dea0c55c18d58..007fb675385081 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs -enable-misched=false < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX906 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -enable-misched=false < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX900 %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-misched=false < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir index 28b3a0eb532a21..809b84943d394f 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-bogus-subrange-comparison.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -mtriple=amdgcn--amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir index 9a810d5056fc64..7917c436f02d48 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-followcopychain-different-subreg-diffs.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -mtriple=amdgcn--amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll b/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll index b5285509675d36..fcbb60a38dfd74 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll +++ b/llvm/test/CodeGen/AMDGPU/regcoal-removepartial-redundancy-not-jointly-dominated.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; ; This test was causing a "Use not jointly dominated by defs" when diff --git a/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir b/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir index 4ac41c0f17a703..d2e712f1826b5e 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalescer-assert-from-incorrect-subrange-extension.mir @@ -1,3 +1,5 @@ +# Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +# Notified per clause 4(b) of the license. # RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # diff --git a/llvm/test/CodeGen/AMDGPU/smrd.ll b/llvm/test/CodeGen/AMDGPU/smrd.ll index aa92803936f204..83355b41bf0d58 100644 --- a/llvm/test/CodeGen/AMDGPU/smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/smrd.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck --check-prefixes=SI,GCN,SICIVI,SICI,SIVIGFX9_10 %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck --check-prefixes=CI,GCN,SICIVI,SICI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck --check-prefixes=VI,GCN,SICIVI,VIGFX9_10,SIVIGFX9_10 %s diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll index 742ac65bc7e6c7..54010571cb0d10 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefixes=CHECK,GFX6 %s ; RUN: llc -sgpr-regalloc=basic -vgpr-regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mattr=-xnack -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=CHECK,GFX9-FLATSCR,FLATSCR %s diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index 062f73a4e6e103..680060d549a5d1 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll index d70753caccd0db..f765b17c50d713 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -mtriple=hexagon -S -hexagon-vc -instcombine < %s | FileCheck %s diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll index ee7d07dc3abe37..777cd9ce48573f 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -instcombine -mtriple=amdgcn-amd-amdhsa %s | FileCheck %s diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/waterfall.ll b/llvm/test/Transforms/InstCombine/AMDGPU/waterfall.ll index 30ec674b59896c..26573d9d13d8c1 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/waterfall.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/waterfall.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -instcombine -mtriple=amdgcn-amd-amdhsa %s | FileCheck %s diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll index b68bb2b3b614f8..2db656ce735e5a 100644 --- a/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll index e2acdac8e07d74..0e10f6db55f5c3 100644 --- a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll +++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll index b6553bcd1abf70..7f1c494d8764d9 100644 --- a/llvm/test/Transforms/InstCombine/icmp-add.ll +++ b/llvm/test/Transforms/InstCombine/icmp-add.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s diff --git a/llvm/test/Transforms/InstCombine/inttoptr_followed_by_bitcast.ll b/llvm/test/Transforms/InstCombine/inttoptr_followed_by_bitcast.ll index 427eb72b7dbe15..7374aac142361b 100644 --- a/llvm/test/Transforms/InstCombine/inttoptr_followed_by_bitcast.ll +++ b/llvm/test/Transforms/InstCombine/inttoptr_followed_by_bitcast.ll @@ -1,3 +1,5 @@ +; Modifications Copyright (c) 2020 Advanced Micro Devices, Inc. All rights reserved. +; Notified per clause 4(b) of the license. ; RUN: opt < %s -instcombine -S | FileCheck %s define i32 @inttoptr_followed_by_bitcast(i32 %i0, i32 %i1, float %i2) { diff --git a/llvm/utils/emacs/README b/llvm/utils/emacs/README deleted file mode 100644 index d0f2bfbbb3e58d..00000000000000 --- a/llvm/utils/emacs/README +++ /dev/null @@ -1,27 +0,0 @@ --*- llvm/utils/emacs/README -*- - -These are syntax highlighting files for the Emacs and XEmacs editors. Included -are: - -* llvm-mode.el - - Syntax highlighting mode for LLVM assembly files. To use, add this code to - your ~/.emacs : - - (setq load-path - (cons (expand-file-name "path-to-llvm/utils/emacs") load-path)) - (require 'llvm-mode) - -* tablegen-mode.el - - Syntax highlighting mode for TableGen description files. To use, add this code - to your ~/.emacs: - - (setq load-path - (cons (expand-file-name "path-to-llvm/utils/emacs") load-path)) - (require 'tablegen-mode) - - -Note: If you notice missing or incorrect syntax highlighting, please contact -; if you wish to provide a patch to improve the -functionality, it will be most appreciated. Thank you. diff --git a/llvm/utils/emacs/emacs.el b/llvm/utils/emacs/emacs.el deleted file mode 100644 index 3a2b47cee1db13..00000000000000 --- a/llvm/utils/emacs/emacs.el +++ /dev/null @@ -1,32 +0,0 @@ -;; LLVM coding style guidelines in emacs -;; Maintainer: LLVM Team, http://llvm.org/ - -(defun llvm-lineup-statement (langelem) - (let ((in-assign (c-lineup-assignments langelem))) - (if (not in-assign) - '++ - (aset in-assign 0 - (+ (aref in-assign 0) - (* 2 c-basic-offset))) - in-assign))) - -;; Add a cc-mode style for editing LLVM C and C++ code -(c-add-style "llvm.org" - '("gnu" - (fill-column . 80) - (c++-indent-level . 2) - (c-basic-offset . 2) - (indent-tabs-mode . nil) - (c-offsets-alist . ((arglist-intro . ++) - (innamespace . 0) - (member-init-intro . ++) - (statement-cont . llvm-lineup-statement))))) - -;; Files with "llvm" in their names will automatically be set to the -;; llvm.org coding style. -(add-hook 'c-mode-common-hook - (function - (lambda nil - (if (string-match "llvm" buffer-file-name) - (progn - (c-set-style "llvm.org")))))) diff --git a/llvm/utils/emacs/llvm-mode.el b/llvm/utils/emacs/llvm-mode.el deleted file mode 100644 index 1fb811b1d3c9a9..00000000000000 --- a/llvm/utils/emacs/llvm-mode.el +++ /dev/null @@ -1,112 +0,0 @@ -;;; llvm-mode.el --- Major mode for the LLVM assembler language. - -;; Maintainer: The LLVM team, http://llvm.org/ -;; Version: 1.0 - -;;; Commentary: - -;; Major mode for editing LLVM IR files. - -;;; Code: - -(defvar llvm-mode-syntax-table - (let ((table (make-syntax-table))) - (modify-syntax-entry ?% "_" table) - (modify-syntax-entry ?. "_" table) - (modify-syntax-entry ?\; "< " table) - (modify-syntax-entry ?\n "> " table) - table) - "Syntax table used while in LLVM mode.") - -(defvar llvm-font-lock-keywords - (list - ;; Attributes - `(,(regexp-opt - '("alwaysinline" "argmemonly" "allocsize" "builtin" "cold" "convergent" "dereferenceable" "dereferenceable_or_null" "hot" "inaccessiblememonly" - "inaccessiblemem_or_argmemonly" "inalloca" "inlinehint" "jumptable" "minsize" "mustprogress" "naked" "nobuiltin" "nonnull" - "nocallback" "nocf_check" "noduplicate" "nofree" "noimplicitfloat" "noinline" "nomerge" "nonlazybind" "noprofile" "noredzone" "noreturn" - "norecurse" "nosync" "noundef" "nounwind" "nosanitize_coverage" "null_pointer_is_valid" "optforfuzzing" "optnone" "optsize" "preallocated" "readnone" "readonly" "returned" "returns_twice" - "shadowcallstack" "speculatable" "speculative_load_hardening" "ssp" "sspreq" "sspstrong" "safestack" "sanitize_address" "sanitize_hwaddress" "sanitize_memtag" - "sanitize_thread" "sanitize_memory" "strictfp" "swifterror" "uwtable" "vscale_range" "willreturn" "writeonly" "immarg") 'symbols) . font-lock-constant-face) - ;; Variables - '("%[-a-zA-Z$._][-a-zA-Z$._0-9]*" . font-lock-variable-name-face) - ;; Labels - '("[-a-zA-Z$._0-9]+:" . font-lock-variable-name-face) - ;; Unnamed variable slots - '("%[-]?[0-9]+" . font-lock-variable-name-face) - ;; Types - `(,(regexp-opt - '("void" "i1" "i8" "i16" "i32" "i64" "i128" "half" "bfloat" "float" "double" "fp128" "x86_fp80" "ppc_fp128" "x86_mmx" "x86_amx" - "type" "label" "opaque" "token") 'symbols) . font-lock-type-face) - ;; Integer literals - '("\\b[-]?[0-9]+\\b" . font-lock-preprocessor-face) - ;; Floating point constants - '("\\b[-+]?[0-9]+.[0-9]*\\([eE][-+]?[0-9]+\\)?\\b" . font-lock-preprocessor-face) - ;; Hex constants - '("\\b0x[0-9A-Fa-f]+\\b" . font-lock-preprocessor-face) - ;; Keywords - `(,(regexp-opt - '(;; Toplevel entities - "declare" "define" "module" "target" "source_filename" "global" "constant" "const" "alias" "ifunc" "comdat" - "attributes" "uselistorder" "uselistorder_bb" - ;; Linkage types - "private" "internal" "weak" "weak_odr" "linkonce" "linkonce_odr" "available_externally" "appending" "common" "extern_weak" "external" - "uninitialized" "implementation" "..." - ;; Values - "true" "false" "null" "undef" "zeroinitializer" "none" "c" "asm" "blockaddress" "poison" - - ;; Calling conventions - "ccc" "fastcc" "coldcc" "webkit_jscc" "anyregcc" "preserve_mostcc" "preserve_allcc" - "cxx_fast_tlscc" "swiftcc" "tailcc" "swifttailcc" "cfguard_checkcc" - ;; Visibility styles - "default" "hidden" "protected" - ;; DLL storages - "dllimport" "dllexport" - ;; Thread local - "thread_local" "localdynamic" "initialexec" "localexec" - ;; Runtime preemption specifiers - "dso_preemptable" "dso_local" "dso_local_equivalent" - - "gc" "atomic" "no_cfi" "volatile" "personality" "prologue" "section") 'symbols) . font-lock-keyword-face) - ;; Arithmetic and Logical Operators - `(,(regexp-opt '("add" "sub" "mul" "sdiv" "udiv" "urem" "srem" "and" "or" "xor" - "setne" "seteq" "setlt" "setgt" "setle" "setge") 'symbols) . font-lock-keyword-face) - ;; Floating-point operators - `(,(regexp-opt '("fadd" "fsub" "fneg" "fmul" "fdiv" "frem") 'symbols) . font-lock-keyword-face) - ;; Special instructions - `(,(regexp-opt '("phi" "tail" "call" "select" "to" "shl" "lshr" "ashr" "fcmp" "icmp" "va_arg" "landingpad" "freeze") 'symbols) . font-lock-keyword-face) - ;; Control instructions - `(,(regexp-opt '("ret" "br" "switch" "invoke" "resume" "unwind" "unreachable" "indirectbr" "callbr") 'symbols) . font-lock-keyword-face) - ;; Memory operators - `(,(regexp-opt '("malloc" "alloca" "free" "load" "store" "getelementptr" "fence" "cmpxchg" "atomicrmw") 'symbols) . font-lock-keyword-face) - ;; Casts - `(,(regexp-opt '("bitcast" "inttoptr" "ptrtoint" "trunc" "zext" "sext" "fptrunc" "fpext" "fptoui" "fptosi" "uitofp" "sitofp" "addrspacecast") 'symbols) . font-lock-keyword-face) - ;; Vector ops - `(,(regexp-opt '("extractelement" "insertelement" "shufflevector") 'symbols) . font-lock-keyword-face) - ;; Aggregate ops - `(,(regexp-opt '("extractvalue" "insertvalue") 'symbols) . font-lock-keyword-face) - ;; Metadata types - `(,(regexp-opt '("distinct") 'symbols) . font-lock-keyword-face) - ;; Atomic memory ordering constraints - `(,(regexp-opt '("unordered" "monotonic" "acquire" "release" "acq_rel" "seq_cst") 'symbols) . font-lock-keyword-face) - ;; Fast-math flags - `(,(regexp-opt '("nnan" "ninf" "nsz" "arcp" "contract" "afn" "reassoc" "fast") 'symbols) . font-lock-keyword-face) - ;; Use-list order directives - `(,(regexp-opt '("uselistorder" "uselistorder_bb") 'symbols) . font-lock-keyword-face)) - "Syntax highlighting for LLVM.") - -;;;###autoload -(define-derived-mode llvm-mode prog-mode "LLVM" - "Major mode for editing LLVM source files. -\\{llvm-mode-map} - Runs `llvm-mode-hook' on startup." - (setq font-lock-defaults `(llvm-font-lock-keywords)) - (setq-local comment-start ";")) - -;; Associate .ll files with llvm-mode -;;;###autoload -(add-to-list 'auto-mode-alist (cons "\\.ll\\'" 'llvm-mode)) - -(provide 'llvm-mode) - -;;; llvm-mode.el ends here diff --git a/llvm/utils/emacs/tablegen-mode.el b/llvm/utils/emacs/tablegen-mode.el deleted file mode 100644 index 572823fa56e132..00000000000000 --- a/llvm/utils/emacs/tablegen-mode.el +++ /dev/null @@ -1,129 +0,0 @@ -;;; tablegen-mode.el --- Major mode for TableGen description files (part of LLVM project) - -;; Maintainer: The LLVM team, http://llvm.org/ - -;;; Commentary: -;; A major mode for TableGen description files in LLVM. - -(require 'comint) -(require 'custom) -(require 'ansi-color) - -;; Create mode-specific tables. -;;; Code: - -(defvar td-decorators-face 'td-decorators-face - "Face method decorators.") -(make-face 'td-decorators-face) - -(defvar tablegen-font-lock-keywords - (let ((kw (regexp-opt '("class" "defm" "def" "field" "include" "in" - "let" "multiclass" "foreach" "if" "then" "else" - "defvar" "defset") - 'words)) - (type-kw (regexp-opt '("bit" "bits" "code" "dag" "int" "list" "string") - 'words)) - ) - (list - ;; Comments -;; '("\/\/" . font-lock-comment-face) - ;; Strings - '("\"[^\"]+\"" . font-lock-string-face) - ;; Hex constants - '("\\<0x[0-9A-Fa-f]+\\>" . font-lock-preprocessor-face) - ;; Binary constants - '("\\<0b[01]+\\>" . font-lock-preprocessor-face) - ;; Integer literals - '("\\<[-]?[0-9]+\\>" . font-lock-preprocessor-face) - ;; Floating point constants - '("\\<[-+]?[0-9]+\.[0-9]*\([eE][-+]?[0-9]+\)?\\>" . font-lock-preprocessor-face) - - '("^[ \t]*\\(@.+\\)" 1 'td-decorators-face) - ;; Keywords - kw - ;; Type keywords - type-kw - )) - "Additional expressions to highlight in TableGen mode.") -(put 'tablegen-mode 'font-lock-defaults '(tablegen-font-lock-keywords)) - -;; ---------------------- Syntax table --------------------------- - -(defvar tablegen-mode-syntax-table nil - "Syntax table used in `tablegen-mode' buffers.") -(when (not tablegen-mode-syntax-table) - (setq tablegen-mode-syntax-table (make-syntax-table)) - ;; whitespace (` ') - (modify-syntax-entry ?\ " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\t " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\r " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\n " " tablegen-mode-syntax-table) - (modify-syntax-entry ?\f " " tablegen-mode-syntax-table) - ;; word constituents (`w') - (modify-syntax-entry ?\% "w" tablegen-mode-syntax-table) - (modify-syntax-entry ?\_ "w" tablegen-mode-syntax-table) - ;; comments - (modify-syntax-entry ?/ ". 124b" tablegen-mode-syntax-table) - (modify-syntax-entry ?* ". 23" tablegen-mode-syntax-table) - (modify-syntax-entry ?\n "> b" tablegen-mode-syntax-table) - ;; open paren (`(') - (modify-syntax-entry ?\( "(" tablegen-mode-syntax-table) - (modify-syntax-entry ?\[ "(" tablegen-mode-syntax-table) - (modify-syntax-entry ?\{ "(" tablegen-mode-syntax-table) - (modify-syntax-entry ?\< "(" tablegen-mode-syntax-table) - ;; close paren (`)') - (modify-syntax-entry ?\) ")" tablegen-mode-syntax-table) - (modify-syntax-entry ?\] ")" tablegen-mode-syntax-table) - (modify-syntax-entry ?\} ")" tablegen-mode-syntax-table) - (modify-syntax-entry ?\> ")" tablegen-mode-syntax-table) - ;; string quote ('"') - (modify-syntax-entry ?\" "\"" tablegen-mode-syntax-table) - ) - -;; --------------------- Abbrev table ----------------------------- - -(defvar tablegen-mode-abbrev-table nil - "Abbrev table used while in TableGen mode.") -(define-abbrev-table 'tablegen-mode-abbrev-table ()) - -(defvar tablegen-mode-hook nil) -(defvar tablegen-mode-map nil) ; Create a mode-specific keymap. - -(if (not tablegen-mode-map) - () ; Do not change the keymap if it is already set up. - (setq tablegen-mode-map (make-sparse-keymap)) - (define-key tablegen-mode-map "\t" 'tab-to-tab-stop) - (define-key tablegen-mode-map "\es" 'center-line) - (define-key tablegen-mode-map "\eS" 'center-paragraph)) - -;;;###autoload -(defun tablegen-mode () - "Major mode for editing TableGen description files. -\\{tablegen-mode-map} - Runs `tablegen-mode-hook' on startup." - (interactive) - (kill-all-local-variables) - (use-local-map tablegen-mode-map) ; Provides the local keymap. - (make-local-variable 'font-lock-defaults) - (setq major-mode 'tablegen-mode ; This is how describe-mode - ; finds the doc string to print. - mode-name "TableGen" ; This name goes into the modeline. - local-abbrev-table tablegen-mode-abbrev-table - font-lock-defaults `(tablegen-font-lock-keywords) - require-final-newline t - ) - - (set-syntax-table tablegen-mode-syntax-table) - (make-local-variable 'comment-start) - (setq comment-start "//") - (setq indent-tabs-mode nil) - (run-hooks 'tablegen-mode-hook)) ; Finally, this permits the user to - ; customize the mode with a hook. - -;; Associate .td files with tablegen-mode -;;;###autoload -(add-to-list 'auto-mode-alist (cons (purecopy "\\.td\\'") 'tablegen-mode)) - -(provide 'tablegen-mode) - -;;; tablegen-mode.el ends here