diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index ad45947382..8239a9df37 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -39,7 +39,7 @@ jobs: run: make tools-install - name: Build saftlib - run: make saftlib -j$(nproc) + run: make saftlib - name: Install saftlib run: sudo make saftlib-install diff --git a/.gitignore b/.gitignore index 778bd2bc90..8a29bd3605 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,13 @@ gcc-4.5.3-lm32.tar.xz lm32-elf-gcc.tar.xz +lm32-gcc-4.5.3.tar.xz +lm32-gcc.tar.xz +riscv_gcc.tar.xz +riscv_gcc.tgz toolchain/ +lm32-toolchain/ +riscv-toolchain/ +lm32-gcc-4.5.3/ bin/ lib/ tags @@ -37,7 +44,3 @@ greybox_tmp buildid.c ram.ld .hdlmake -lm32-gcc-4.5.3.tar.xz -lm32-toolchain -lm32-gcc.tar.xz -lm32-gcc-4.5.3/ diff --git a/Makefile b/Makefile index 0b016e00a3..16f4744faf 100644 --- a/Makefile +++ b/Makefile @@ -24,6 +24,11 @@ export TLU ECA=$(PWD)/ip_cores/wr-cores/modules/wr_eca export ECA PATH:=$(PWD)/lm32-toolchain/bin:$(PATH) +export PATH +CROSS_COMPILE_RISCV:="$(PWD)/riscv-toolchain/bin/riscv32-elf-" +export CROSS_COMPILE_RISCV +EB_TOOLS_WRPC_SW=no +export EB_TOOLS_WRPC_SW # This is mainly used to sort QSF files. After sorting it adds and deletes a "GIT marker" which will mark the file as changed. # Additionally all empty lines will be removed. @@ -86,7 +91,7 @@ define ldconfig_note @echo "***************************************************************************" endef -all: hdlmake_install etherbone tools sdbfs lm32-toolchain firmware +all: hdlmake_install etherbone tools sdbfs lm32-toolchain riscv-toolchain firmware gateware: all pexarria5 exploder5 vetar2a vetar2a-ee-butis scu2 scu3 pmc microtca pexp @@ -202,21 +207,32 @@ lm32-toolchain: lm32-toolchain-download lm32-toolchain-clean:: rm -rf lm32-toolchain +riscv-toolchain-download: + test -f riscv_gcc.tgz || wget https://ohwr.org/project/wrpc-sw/wikis/uploads/9f9224d2249848ed3e854636de9c08dc/riscv-11.2-small.tgz -O riscv_gcc.tgz + +riscv-toolchain: riscv-toolchain-download + test -d riscv-toolchain || tar zxvf riscv_gcc.tgz -o + test -d riscv-11.2-small && mv riscv-11.2-small riscv-toolchain || true + lm32-cluster-testbench-run:: lm32-toolchain hdlmake_install make -C testbench/lm32_cluster/test run lm32-cluster-testbench-clean:: lm32-toolchain hdlmake_install make -C testbench/lm32_cluster/test clean +riscv-toolchain-clean:: + rm -rf riscv_gcc.tgz || true + rm -rf riscv-toolchain || true + wrpc-sw-config:: test -s ip_cores/wrpc-sw/.config || \ $(MAKE) -C ip_cores/wrpc-sw/ gsi_defconfig -firmware: sdbfs etherbone lm32-toolchain wrpc-sw-config +firmware: sdbfs etherbone lm32-toolchain riscv-toolchain wrpc-sw-config ifeq ($(UNAME), x86_64) $(MAKE) -C ip_cores/wrpc-sw SDBFS=$(PWD)/ip_cores/fpga-config-space/sdbfs/userspace all else - @echo "Info: Skipping WRPC-SW build (LM32 toolchain does not support your architecture)..." + @echo "Skipping WRPC-SW build (LM32/RISCV toolchain does not support your architecture)..." endif firmware-clean: @@ -224,6 +240,12 @@ ifeq ($(UNAME), x86_64) $(MAKE) -C ip_cores/wrpc-sw SDBFS=$(PWD)/ip_cores/fpga-config-space/sdbfs/userspace clean endif +# Debug print +debug: + echo $$PATH + echo $$EXTRA_FLAGS + echo $$CROSS_COMPILE_RISCV + # ################################################################################################# # Arria 2 devices # ################################################################################################# @@ -472,6 +494,18 @@ bg: lm32-toolchain bg-clean:: $(MAKE) -C modules/burst_generator clean +lm32-example: + $(MAKE) -C modules/lm32-example + +lm32-example-clean: + $(MAKE) -C modules/lm32-example clean + +lm32-simple-access: + $(MAKE) -C modules/lm32-example TARGET=simpleAccess + +lm32-simple-access-clean: + $(MAKE) -C modules/lm32-example clean TARGET=simpleAccess + # ################################################################################################# # Legacy and unmaintained devices # ################################################################################################# @@ -495,10 +529,10 @@ exploder-clean:: $(MAKE) -C syn/gsi_exploder/wr_core_demo clean pexarria10_soc:: firmware - $(MAKE) -C syn/gsi_pexarria10_soc/control PATH=$(PWD)/lm-32toolchain/bin:$(PATH) all + $(MAKE) -C syn/gsi_pexarria10_soc/control PATH=$(PWD)/lm32-toolchain/bin:$(PATH) all pexarria10_soc-clean:: - $(MAKE) -C syn/gsi_pexarria10_soc/control PATH=$(PWD)/lm-32toolchain/bin:$(PATH) clean + $(MAKE) -C syn/gsi_pexarria10_soc/control PATH=$(PWD)/lm32-toolchain/bin:$(PATH) clean # We need to run ./fix-git.sh and ./install-hdlmake.sh: make them a prerequisite for Makefile Makefile: prereq-rule diff --git a/fix-git.sh b/fix-git.sh index 252070e1b3..5ad944c273 100755 --- a/fix-git.sh +++ b/fix-git.sh @@ -19,7 +19,7 @@ if false; then # use explicit names instead else - for d in ip_cores/wrpc-sw ip_cores/fpga-config-space; do + for d in ip_cores/wrpc-sw ip_cores/wr-cores ip_cores/fpga-config-space; do (cd $d && do_submod) done fi diff --git a/ip_cores/fpga-config-space b/ip_cores/fpga-config-space index 4f853dbb01..b2dcb185b2 160000 --- a/ip_cores/fpga-config-space +++ b/ip_cores/fpga-config-space @@ -1 +1 @@ -Subproject commit 4f853dbb016a3244c257933ce5e0a1b882543b57 +Subproject commit b2dcb185b2c1b1cddbfb9b69d3f76612da9e8fd5 diff --git a/ip_cores/general-cores b/ip_cores/general-cores index 78020ea30d..a637d457d0 160000 --- a/ip_cores/general-cores +++ b/ip_cores/general-cores @@ -1 +1 @@ -Subproject commit 78020ea30da71290401a1549968243ed19ceac21 +Subproject commit a637d457d06cea8022ec55bab3cc94cd7daa5808 diff --git a/ip_cores/wr-cores b/ip_cores/wr-cores index 48f04c0663..abaca820d1 160000 --- a/ip_cores/wr-cores +++ b/ip_cores/wr-cores @@ -1 +1 @@ -Subproject commit 48f04c06637e9da4b70db7bf62aab5e04517dd89 +Subproject commit abaca820d1ecdae3ccd7e0107379295ab98fb7e9 diff --git a/ip_cores/wrpc-sw b/ip_cores/wrpc-sw index aef35918d8..f7851eb84e 160000 --- a/ip_cores/wrpc-sw +++ b/ip_cores/wrpc-sw @@ -1 +1 @@ -Subproject commit aef35918d88cb978e5d43ae9ae6cea5802d8665d +Subproject commit f7851eb84e3f3162ef808271f900e1b091c46e27 diff --git a/modules/common-libs/fw/common-fwlib.c b/modules/common-libs/fw/common-fwlib.c index fdac557b41..33f9474b78 100644 --- a/modules/common-libs/fw/common-fwlib.c +++ b/modules/common-libs/fw/common-fwlib.c @@ -311,9 +311,9 @@ b2bt_t fwlib_tfns2tps(float t_ns) float fwlib_tps2tfns(b2bt_t t_ps) -{ +{ float tmp1, tmp2; - + tmp1 = (float)(t_ps.ns); tmp2 = (float)(t_ps.ps) / 1000.0; diff --git a/modules/lm32-example/miniExample.c b/modules/lm32-example/miniExample.c index c37c7a5e01..c6f9e1c883 100644 --- a/modules/lm32-example/miniExample.c +++ b/modules/lm32-example/miniExample.c @@ -6,7 +6,7 @@ * version : 05-Jun-2020 * * very basic example program for lm32 softcore on GSI timing receivers - * + * * ------------------------------------------------------------------------------------------- * License Agreement for this software: * @@ -27,7 +27,7 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library. If not, see . * @@ -41,14 +41,14 @@ #include #include -// includes specific for bel_projects +// includes specific for bel_projects #include "pp-printf.h" #include "mini_sdb.h" #include "aux.h" #include "dbg.h" #include "uart.h" -// shared memory map for communication via Wishbone +// shared memory map for communication via Wishbone #include "miniExample_shared_mmap.h" // stuff required for environment @@ -59,22 +59,25 @@ uint64_t SHARED dummy = 0; void init(){ discoverPeriphery(); // mini-sdb: get info on important Wishbone infrastructure - uart_init_hw(); // init UART, required for printf... - cpuId = getCpuIdx(); // get ID of THIS CPU + uart_init_hw(); // init UART, required for printf... + cpuId = getCpuIdx(); // get ID of THIS CPU } // init -void main(void) { +int main(void) { int j; - + init(); - + // wait 1 second and print initial message to UART // pro tip: try 'eb-console' to view printed messages for (j = 0; j < (31000000); ++j) { asm("nop"); } // 31.25 x 'asm("nop")' operations take 1 us; handmade sleep + pp_printf("Hello World!\n"); while (1) { pp_printf("boring...\n"); uwait(1000000); // alternative to handmade sleep using the wb_timer for lm32 } // while + + return 0; } // main diff --git a/modules/lm32-example/simpleAccess.c b/modules/lm32-example/simpleAccess.c new file mode 100644 index 0000000000..92a0810126 --- /dev/null +++ b/modules/lm32-example/simpleAccess.c @@ -0,0 +1,47 @@ +// Build and test +// make lm32-simple-access-clean && make lm32-simple-access && lm32-elf-objdump -D modules/lm32-example/simpleAccess.elf > dis && eb-fwload -v dev/ttyUSB0 u 0x0 modules/lm32-example/simpleAccess.bin + +#include +#include +#include +#include +#include "mini_sdb.h" +#include "pp-printf.h" +#include "uart.h" + +#define LVDS_OE_ON_OFFSET (0x300>>2) +#define LVDS_OE_OFF_OFFSET (0x308>>2) +#define ALL_BITS 0xffffffff +#define LOOP_CNT 1000000 + +void loop(void); + +void loop(void) +{ + volatile uint32_t cnt = 0; + for (cnt = 0; cnt < LOOP_CNT; ++cnt) { asm("nop"); } +} + +int main(void) +{ + volatile uint32_t *pGPIO_on = NULL; + volatile uint32_t *pGPIO_off = NULL; + + discoverPeriphery(); + uart_init_hw(); + + pGPIO_on = pIOC+LVDS_OE_ON_OFFSET; + pGPIO_off = pIOC+LVDS_OE_OFF_OFFSET; + + pp_printf("GPIO Base: 0x%x 0x%x 0x%x\n", pIOC, pGPIO_on, pGPIO_off); + + while(1) + { + *pGPIO_on = ALL_BITS; + loop(); + *pGPIO_off = ALL_BITS; + loop(); + } + + return 0; +} diff --git a/modules/lm32-include/mini_sdb.c b/modules/lm32-include/mini_sdb.c index abdb93585b..57289c4617 100644 --- a/modules/lm32-include/mini_sdb.c +++ b/modules/lm32-include/mini_sdb.c @@ -1,7 +1,7 @@ #include #include "mini_sdb.h" #include "dbg.h" -#include "hw/memlayout.h" +#include "memlayout.h" #include "sdb_add.h" sdb_location *find_sdb_deep(sdb_record_t *parent_sdb, sdb_location *found_sdb, uint32_t base, uint32_t msi_base, uint32_t msi_last, uint32_t *idx, uint32_t qty, uint32_t venId, uint32_t devId) @@ -11,28 +11,28 @@ sdb_location *find_sdb_deep(sdb_record_t *parent_sdb, sdb_location *found_sdb, u uint32_t i; uint32_t msi_cnt = 0; uint32_t msi_adr = 0; - - + + record = parent_sdb; records = record->interconnect.sdb_records; //discover MSI address before moving on to possible next Crossbar for (i = 0; i < records; ++i, ++record) { - + if(record->empty.record_type == SDB_MSI) { if (record->msi.msi_flags & OWN_MSI) { - //mprintf("adr: 0x%08x, i : %u type %u own: 0x%08x msi_addr %08x \n", base, i, record->empty.record_type, record->msi.msi_flags, record->msi.sdb_component.addr_first.low); + //mprintf("adr: 0x%08x, i : %u type %u own: 0x%08x msi_addr %08x \n", base, i, record->empty.record_type, record->msi.msi_flags, record->msi.sdb_component.addr_first.low); if((msi_base == NO_MSI) || (record->msi.sdb_component.product.vendor_id.low == 0 && record->msi.sdb_component.product.device_id == 0)) msi_base = NO_MSI; else msi_adr = record->msi.sdb_component.addr_first.low; msi_cnt++; - } + } } } if( msi_cnt > 1) { //This is an error, the CB layout is messed up DBPRINT1("Found more than 1 MSI at 0x%08x par 0x%08x\n", (unsigned int)base, (unsigned int)(unsigned char*)parent_sdb); - *idx = 0; + *idx = 0; return found_sdb; } @@ -47,14 +47,14 @@ sdb_location *find_sdb_deep(sdb_record_t *parent_sdb, sdb_location *found_sdb, u found_sdb[(*idx)].sdb = record; found_sdb[(*idx)].adr = base; found_sdb[(*idx)].msi_first = msi_base + msi_adr; - found_sdb[(*idx)].msi_last = msi_base + msi_adr + msi_last; + found_sdb[(*idx)].msi_last = msi_base + msi_adr + msi_last; (*idx)++; - } + } find_sdb_deep((sdb_record_t *)(base+record->bridge.sdb_child.low), found_sdb, base+record->bridge.sdb_component.addr_first.low, msi_base+msi_adr, msi_last, idx, qty, venId, devId ); } - - + + if (record->empty.record_type == SDB_DEVICE) { if (record->device.sdb_component.product.vendor_id.low == venId && @@ -63,7 +63,7 @@ sdb_location *find_sdb_deep(sdb_record_t *parent_sdb, sdb_location *found_sdb, u found_sdb[(*idx)].sdb = record; found_sdb[(*idx)].adr = base; found_sdb[(*idx)].msi_first = msi_base + msi_adr; - found_sdb[(*idx)].msi_last = msi_base + msi_adr + msi_last; + found_sdb[(*idx)].msi_last = msi_base + msi_adr + msi_last; (*idx)++; } } @@ -76,15 +76,15 @@ sdb_location *find_sdb_deep(sdb_record_t *parent_sdb, sdb_location *found_sdb, u found_sdb[(*idx)].sdb = record; found_sdb[(*idx)].adr = base; found_sdb[(*idx)].msi_first = msi_base + msi_adr; - found_sdb[(*idx)].msi_last = msi_base + msi_adr + msi_last; + found_sdb[(*idx)].msi_last = msi_base + msi_adr + msi_last; (*idx)++; } - } + } if(*idx >= qty) { return found_sdb; } } - + return found_sdb; } @@ -94,16 +94,16 @@ uint32_t getMsiUpperRange() { uint32_t records = record->interconnect.sdb_records; uint32_t i; uint32_t msi_adr = 0; - - //get upper range of MSI target - for (i = 0; i < records; ++i, ++record) { + + //get upper range of MSI target + for (i = 0; i < records; ++i, ++record) { if(record->empty.record_type == SDB_MSI) { if (record->msi.msi_flags == OWN_MSI) { msi_adr = record->msi.sdb_component.addr_last.low; - break; - } + break; + } } - } + } return msi_adr; } @@ -116,12 +116,12 @@ uint32_t getMsiUpperRange() { // convenience wrappers sdb_location* find_device_multi(sdb_location *found_sdb, uint32_t *idx, uint32_t qty, uint32_t venId, uint32_t devId) { - uint32_t root = sdb_add(); + uint32_t root = sdb_add(); sdb_record_t *pRoot = (sdb_record_t *)((uint32_t)(root)); return find_sdb_deep(pRoot, found_sdb, 0, 0, getMsiUpperRange(), idx, qty, venId, devId); - + } uint32_t* find_device_adr(uint32_t venId, uint32_t devId) @@ -129,10 +129,10 @@ uint32_t* find_device_adr(uint32_t venId, uint32_t devId) sdb_location found_sdb; uint32_t idx = 0; uint32_t* adr = (uint32_t*)ERROR_NOT_FOUND; - + find_device_multi(&found_sdb, &idx, 1, venId, devId); if(idx > 0) adr = (uint32_t*)getSdbAdr(&found_sdb); - + return adr; } @@ -158,19 +158,19 @@ uint32_t getSdbAdr(sdb_location *loc) { if (loc->sdb->empty.record_type == SDB_DEVICE ) return loc->adr + loc->sdb->device.sdb_component.addr_first.low; else if (loc->sdb->empty.record_type == SDB_BRIDGE ) return loc->adr + loc->sdb->bridge.sdb_component.addr_first.low; - else return ERROR_NOT_FOUND; + else return ERROR_NOT_FOUND; } uint32_t getMsiAdr(sdb_location *loc) { return loc->msi_first; - + } uint32_t getMsiAdrLast(sdb_location *loc) { return loc->msi_last; - + } uint32_t getSdbAdrLast(sdb_location *loc) @@ -203,13 +203,13 @@ void discoverPeriphery(void) uint32_t idx = 0; uint32_t idx_w1 = 0; pCpuMsiBox = NULL; - pMyMsi = NULL; + pMyMsi = NULL; + + //pUart = find_device_adr(CERN, WR_UART); + pUart = (uint32_t*)0x80040500; + //BASE_UART = (char *)pUart; //make WR happy ... + - pUart = find_device_adr(CERN, WR_UART); - //pUart = (uint32_t*)0x84060500; - BASE_UART = (char *)pUart; //make WR happy ... - - pCpuId = find_device_adr(GSI, CPU_INFO_ROM); pCpuAtomic = find_device_adr(GSI, CPU_ATOM_ACC); pCpuSysTime = find_device_adr(GSI, CPU_SYSTEM_TIME); @@ -218,18 +218,18 @@ void discoverPeriphery(void) idx = 0; - find_device_multi(&found_sdb[0], &idx, 1, GSI, MSI_MSG_BOX); + find_device_multi(&found_sdb[0], &idx, 1, GSI, MSI_MSG_BOX); if(idx) { - pCpuMsiBox = (uint32_t*)getSdbAdr(&found_sdb[0]); - pMyMsi = (uint32_t*)getMsiAdr(&found_sdb[0]); - } + pCpuMsiBox = (uint32_t*)getSdbAdr(&found_sdb[0]); + pMyMsi = (uint32_t*)getMsiAdr(&found_sdb[0]); + } pCluCB = find_device_adr(GSI, LM32_CB_CLUSTER); pCluInfo = find_device_adr(GSI, CLU_INFO_ROM); - pFpqCtrl = find_device_adr(GSI, FTM_PRIOQ_CTRL); - pFpqData = find_device_adr(GSI, FTM_PRIOQ_DATA); - - - pOledDisplay = find_device_adr(GSI, OLED_DISPLAY); + pFpqCtrl = find_device_adr(GSI, FTM_PRIOQ_CTRL); + pFpqData = find_device_adr(GSI, FTM_PRIOQ_DATA); + + + pOledDisplay = find_device_adr(GSI, OLED_DISPLAY); idx = 0; find_device_multi(&found_sdb[0], &idx, 20, GSI, ETHERBONE_MASTER); pEbm = (uint32_t*)getSdbAdr(&found_sdb[0]); @@ -238,18 +238,19 @@ void discoverPeriphery(void) pEca = find_device_adr(GSI, ECA_EVENT); pTlu = find_device_adr(GSI, TLU); - + pCfiPFlash = find_device_adr(GSI, WR_CFIPFlash); - + pDDR3_if1 = find_device_adr(GSI, WB_DDR3_if1); pDDR3_if2 = find_device_adr(GSI, WB_DDR3_if2); - + + pIOC = find_device_adr(GSI, IO_CONTROL); + // Get the second onewire/w1 record (0=white rabbit w1 unit, 1=user w1 unit) find_device_multi(&found_sdb_w1[0], &idx_w1, 2, CERN, WR_1Wire); pOneWire = (uint32_t*)getSdbAdr(&found_sdb_w1[1]); - BASE_SYSCON = (char *)find_device_adr(CERN, WR_SYS_CON); //probably the same reason as BASE_UART is of type char* + //BASE_SYSCON = (char *)find_device_adr(CERN, WR_SYS_CON); //probably the same reason as BASE_UART is of type char* pPps = (uint32_t *)find_device_adr(CERN, WR_PPS_GEN); } - diff --git a/modules/lm32-include/mini_sdb.h b/modules/lm32-include/mini_sdb.h index 0ca707ca8b..377370632a 100644 --- a/modules/lm32-include/mini_sdb.h +++ b/modules/lm32-include/mini_sdb.h @@ -63,7 +63,7 @@ #define ECA_EVENT 0x8752bf45 #define ECA_CTRL 0x8752bf44 -#define TLU 0x10051981 +#define TLU 0x10051981 #define WR_UART 0xe2d13d04 #define WR_PPS_GEN 0xde0d8ced #define SCU_BUS_MASTER 0x9602eb6f @@ -79,19 +79,19 @@ #define WR_CFIPFlash 0x12122121 #define WB_DDR3_if1 0x20150828 #define WB_DDR3_if2 0x20160525 -#define WR_SYS_CON 0xff07fc47 +#define WR_SYS_CON 0xff07fc47 #define WB_REMOTE_UPDATE 0x38956271 #define WB_ASMI 0x48526423 #define WB_SCU_REG 0xe2d13d04 - +#define IO_CONTROL 0x10c05791 //periphery device pointers -volatile uint32_t* pTlu; +volatile uint32_t* pTlu; volatile uint32_t* pEbm; volatile uint32_t* pEbCfg; volatile uint32_t* pEbmLast; -volatile uint32_t* pOledDisplay; +volatile uint32_t* pOledDisplay; volatile uint32_t* pFpqCtrl; volatile uint32_t* pFpqData; volatile uint32_t* pEca; @@ -114,6 +114,8 @@ volatile uint32_t* pCfiPFlash; volatile uint32_t* pDDR3_if1; volatile uint32_t* pDDR3_if2; +volatile uint32_t* pIOC; + typedef struct pair64 { uint32_t high; diff --git a/modules/lm32-include/wrpc-import/board.c b/modules/lm32-include/wrpc-import/board.c new file mode 100644 index 0000000000..6a31188631 --- /dev/null +++ b/modules/lm32-include/wrpc-import/board.c @@ -0,0 +1,126 @@ +#include "board.h" +#include "wrc-debug.h" +#include "dev/bb_spi.h" +#include "dev/bb_i2c.h" +#include "dev/w1.h" +#include "dev/spi_flash.h" +#include "dev/i2c_eeprom.h" +#include "dev/syscon.h" +#include "dev/endpoint.h" +#include "storage.h" + +static struct i2c_bus i2c_wrc_eeprom; +static struct i2c_eeprom_device wrc_eeprom_dev; + +int wrc_board_early_init() +{ + int memtype; + uint32_t sdbfs_entry; + uint32_t sector_size; + + if (HAS_W1_EEPROM + && storage_w1eeprom_create(&wrc_storage_dev, &wrpc_w1_bus) == 0) { + /* Found. */ + } + else if (EEPROM_STORAGE) { + /* EEPROM support */ + bb_i2c_create(&i2c_wrc_eeprom, + &pin_sysc_fmc_scl, + &pin_sysc_fmc_sda); + bb_i2c_init(&i2c_wrc_eeprom); + + i2c_eeprom_create(&wrc_eeprom_dev, &i2c_wrc_eeprom, FMC_EEPROM_ADR, 2); + storage_i2ceeprom_create( &wrc_storage_dev, &wrc_eeprom_dev ); + } else { + /* Flash support */ + /* + * declare GPIO pins and configure their directions for bit-banging SPI + * limit SPI speed to 10MHz by setting bit_delay = CPU_CLOCK / 10^6 + */ + bb_spi_create( &spi_wrc_flash, + &pin_sysc_spi_ncs, + &pin_sysc_spi_mosi, + &pin_sysc_spi_miso, + &pin_sysc_spi_sclk, CPU_CLOCK / 10000000 ); + + spi_wrc_flash.rd_falling_edge = 1; + + /* + * Read from gateware info about used memory. Currently only base + * address and sector size for memtype flash is supported. + */ + get_storage_info(&memtype, &sdbfs_entry, §or_size); + + /* + * Initialize SPI flash and read its ID + */ + spi_flash_create( &wrc_flash_dev, &spi_wrc_flash, sector_size, sdbfs_entry); + + /* + * Initialize storage subsystem with newly created SPI Flash + */ + storage_spiflash_create( &wrc_storage_dev, &wrc_flash_dev ); + } + + /* + * Mount SDBFS filesystem from storage. + */ + storage_mount( &wrc_storage_dev ); + + return 0; +} + +static int board_get_persistent_mac(uint8_t *mac) +{ + int i; + struct w1_dev *d; + + /* Try from SDB */ + if (storage_get_persistent_mac(0, mac) == 0) + return 0; + + /* Get from one-wire (derived from unique id) */ + if (HAS_W1) { + for (i = 0; i < W1_MAX_DEVICES; i++) { + d = wrpc_w1_bus.devs + i; + if (d->rom) { + mac[0] = 0x22; + mac[1] = 0x33; + mac[2] = 0xff & (d->rom >> 32); + mac[3] = 0xff & (d->rom >> 24); + mac[4] = 0xff & (d->rom >> 16); + mac[5] = 0xff & (d->rom >> 8); + return 0; + } + } + } + + /* Not found */ + return -1; +} + +int wrc_board_init() +{ + uint8_t mac_addr[6]; + /* + * Try reading MAC addr stored in flash + */ + if (board_get_persistent_mac(mac_addr) < 0) { + board_dbg("Failed to get MAC address from the flash. Using fallback address.\n"); + mac_addr[0] = 0x22; + mac_addr[1] = 0x33; + mac_addr[2] = 0x44; + mac_addr[3] = 0x55; + mac_addr[4] = 0x66; + mac_addr[5] = 0x77; + } + ep_set_mac_addr(&wrc_endpoint_dev, mac_addr); + ep_pfilter_init_default(&wrc_endpoint_dev); + + return 0; +} + +int wrc_board_create_tasks() +{ + return 0; +} diff --git a/modules/lm32-include/wrpc-import/board.h b/modules/lm32-include/wrpc-import/board.h new file mode 100644 index 0000000000..9118882454 --- /dev/null +++ b/modules/lm32-include/wrpc-import/board.h @@ -0,0 +1,92 @@ +/* + * This work is part of the White Rabbit project + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#ifndef CONFIG_TARGET_GSI_DEVICE +//#include +#endif + +#ifndef __BOARD_WRC_H +#define __BOARD_WRC_H +/* + * This is meant to be automatically included by the Makefile, + * when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch) + */ + +#ifdef CONFIG_ARCH_RISCV +#define DEV_BASE 0x100000 +#elif defined CONFIG_ARCH_LM32 +#define DEV_BASE 0x80040000 +//#warning Test +#else +//#error (Wrong Arch!) +#endif + +/* Fixed base addresses */ +#define BASE_MINIC (DEV_BASE + 0x000) +#define BASE_EP (DEV_BASE + 0x100) +#define BASE_SOFTPLL (DEV_BASE + 0x200) +#define BASE_PPS_GEN (DEV_BASE + 0x300) +#define BASE_SYSCON (DEV_BASE + 0x400) +#define BASE_UART (DEV_BASE + 0x500) +#define BASE_ONEWIRE (DEV_BASE + 0x600) +#define BASE_WDIAGS_PRIV (DEV_BASE + 0x900) +#define BASE_ETHERBONE_CFG (DEV_BASE + 0x8000) + +/* Board-specific parameters */ +#define TICS_PER_SECOND 1000 + +/* WR Core system/CPU clock frequency in Hz */ +#define CPU_CLOCK 62500000ULL + +/* WR Reference clock period (picoseconds) and frequency (Hz) */ +#ifdef CONFIG_TARGET_GENERIC_PHY_16BIT +# define NS_PER_CLOCK 16 +# define REF_CLOCK_PERIOD_PS 16000 +# define REF_CLOCK_FREQ_HZ 62500000 +#else +# define NS_PER_CLOCK 8 +# define REF_CLOCK_PERIOD_PS 8000 +# define REF_CLOCK_FREQ_HZ 125000000 +#endif + +/* Maximum number of simultaneously created sockets */ +#define NET_MAX_SOCKETS 12 + +/* Socket buffer size, determines the max. RX packet size */ +#define NET_MAX_SKBUF_SIZE 512 + +/* Number of auxillary clock channels - usually equal to the number of FMCs */ +#define NUM_AUX_CLOCKS 1 + +/* spll parameter that are board-specific */ +#ifdef CONFIG_TARGET_GENERIC_PHY_16BIT +# define BOARD_DIVIDE_DMTD_CLOCKS 0 +#else +# define BOARD_DIVIDE_DMTD_CLOCKS 1 +#endif +#define BOARD_MAX_CHAN_REF 1 +#define BOARD_MAX_CHAN_AUX 2 +#define BOARD_MAX_PTRACKERS 1 + +#undef CONFIG_DISALLOW_LONG_DIVISION + +#define BOARD_USE_EVENTS 0 + +#define BOARD_MAX_CONSOLE_DEVICES (1 + HAS_NETCONSOLE + HAS_PUTS_SYSLOG) + +#define CONSOLE_UART_BAUDRATE 115200 + +#define FMC_EEPROM_ADR 0x50 + +#define SDBFS_REC 5 + +#define EEPROM_STORAGE 0 + +#if 0 +void sdb_find_devices(void); +void sdb_print_devices(void); +#endif + +#endif /* __BOARD_WRC_H */ diff --git a/modules/lm32-include/wrpc-import/dev/w1-eeprom.c b/modules/lm32-include/wrpc-import/dev/w1-eeprom.c new file mode 100644 index 0000000000..b612d2e0b5 --- /dev/null +++ b/modules/lm32-include/wrpc-import/dev/w1-eeprom.c @@ -0,0 +1,180 @@ +/* + * Eeprom support (family 0x43) + * Cesar Prados, Alessandro Rubini, 2013. GNU GPL2 or later + */ +#include "dev/w1.h" +#include "syscon.h" /* for usleep */ + +#define LSB_ADDR(X) ((X) & 0xFF) +#define MSB_ADDR(X) (((X) & 0xFF00)>>8) + +static int w1_write_page(struct w1_dev *dev, int offset, const uint8_t *buffer, + int blen) +{ + int i, j, es; + + /* First, write scratchpad */ + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDR_W_SPAD); + w1_write_byte(dev->bus, LSB_ADDR(offset)); + w1_write_byte(dev->bus, MSB_ADDR(offset)); + for(i = 0; i < blen; i++) + w1_write_byte(dev->bus, buffer[i]); + + /* Then, read it back, and remember the return E/S */ + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDR_R_SPAD); + if (w1_read_byte(dev->bus) != LSB_ADDR(offset)) + return -1; + if (w1_read_byte(dev->bus) != MSB_ADDR(offset)) + return -2; + es = w1_read_byte(dev->bus); + for(i = 0; i < blen; i++) { + j = w1_read_byte(dev->bus); + if (j != buffer[i]) + return -3; + } + + /* Finally, "copy scratchpad" to actually write */ + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDR_C_SPAD); + w1_write_byte(dev->bus, LSB_ADDR(offset)); + w1_write_byte(dev->bus, MSB_ADDR(offset)); + w1_write_byte(dev->bus, es); + usleep(10000); /* 10ms, in theory */ + + /* Don't read back, as nothing useful is there (I get 0xf9, why?) */ + return blen; +} + +static int w1_erase_page(struct w1_dev *dev, int offset, int blen) +{ + int i, j, es; + + /* First, write scratchpad */ + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDR_W_SPAD); + w1_write_byte(dev->bus, LSB_ADDR(offset)); + w1_write_byte(dev->bus, MSB_ADDR(offset)); + for(i = 0; i < blen; i++) + w1_write_byte(dev->bus, 0xFF); + + /* Then, read it back, and remember the return E/S */ + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDR_R_SPAD); + if (w1_read_byte(dev->bus) != LSB_ADDR(offset)) + return -1; + if (w1_read_byte(dev->bus) != MSB_ADDR(offset)) + return -2; + es = w1_read_byte(dev->bus); + for(i = 0; i < blen; i++) { + j = w1_read_byte(dev->bus); + if (j != 0xFF) + return -3; + } + + /* Finally, "copy scratchpad" to actually write */ + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDR_C_SPAD); + w1_write_byte(dev->bus, LSB_ADDR(offset)); + w1_write_byte(dev->bus, MSB_ADDR(offset)); + w1_write_byte(dev->bus, es); + usleep(10000); /* 10ms, in theory */ + + /* Don't read back, as nothing useful is there (I get 0xf9, why?) */ + return blen; +} + +int w1_write_eeprom(struct w1_dev *dev, int offset, const uint8_t *buffer, + int blen) +{ + int i, page, endpage; + int ret = 0; + + /* Split the write into several page-local writes */ + page = offset / 32; + endpage = (offset + blen - 1) / 32; + + /* Traling part of first page */ + if (offset % 32) { + if (endpage != page) + i = 32 - (offset % 32); + else + i = blen; + ret += w1_write_page(dev, offset, buffer, i); + if (ret < 0) + return ret; + buffer += i; + offset += i; + blen -= i; + } + + /* Whole pages and leading part of last page */ + while (blen > 0 ) { + i = blen; + if (blen > 32) + i = 32; + i = w1_write_page(dev, offset, buffer, i); + if (i < 0) + return i; + ret += i; + buffer += 32; + offset += 32; + blen -= 32; + } + return ret; +} + +int w1_read_eeprom(struct w1_dev *dev, int offset, uint8_t *buffer, int blen) +{ + int i; + + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDR_R_MEMORY); + + w1_write_byte(dev->bus, LSB_ADDR(offset)); + w1_write_byte(dev->bus, MSB_ADDR(offset)); + + /* There is no page-size limit in reading, just go on at will */ + for(i = 0; i < blen; i++) + buffer[i] = w1_read_byte(dev->bus); + + return blen; +} + +int w1_erase_eeprom(struct w1_dev *dev, int offset, int blen) +{ + int i, page, endpage; + int ret = 0; + + /* Split the write into several page-local writes */ + page = offset / 32; + endpage = (offset + blen - 1) / 32; + + /* Traling part of first page */ + if (offset % 32) { + if (endpage != page) + i = 32 - (offset % 32); + else + i = blen; + ret += w1_erase_page(dev, offset, i); + if (ret < 0) + return ret; + offset += i; + blen -= i; + } + + /* Whole pages and leading part of last page */ + while (blen > 0 ) { + i = blen; + if (blen > 32) + i = 32; + i = w1_erase_page(dev, offset, i); + if (i < 0) + return i; + ret += i; + offset += 32; + blen -= 32; + } + return ret; +} diff --git a/modules/lm32-include/wrpc-import/dev/w1-hw.c b/modules/lm32-include/wrpc-import/dev/w1-hw.c new file mode 100644 index 0000000000..34ac6c725c --- /dev/null +++ b/modules/lm32-include/wrpc-import/dev/w1-hw.c @@ -0,0 +1,76 @@ +/* + * This work is part of the White Rabbit project + * + * Copyright (C) 2013 CERN (www.cern.ch) + * Author: Alessandro Rubini + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#include +#include +#include +#include +//#include "memlayout.h" + +static inline uint32_t __wait_cycle(void *base) +{ + uint32_t reg; + + while ((reg = IORD_SOCKIT_OWM_CTL(base)) & SOCKIT_OWM_CTL_CYC_MSK) + ; + return reg; +} + +static int w1_reset(struct w1_bus *bus) +{ + int portnum = bus->detail; + uint32_t reg; + + IOWR_SOCKIT_OWM_CTL(BASE_ONEWIRE, (portnum << SOCKIT_OWM_CTL_SEL_OFST) + | (SOCKIT_OWM_CTL_CYC_MSK) + | (SOCKIT_OWM_CTL_RST_MSK)); + reg = __wait_cycle(BASE_ONEWIRE); + /* return presence-detect pulse (1 if true) */ + return (reg & SOCKIT_OWM_CTL_DAT_MSK) ? 0 : 1; +} + +static int w1_read_bit(struct w1_bus *bus) +{ + int portnum = bus->detail; + uint32_t reg; + + IOWR_SOCKIT_OWM_CTL(BASE_ONEWIRE, (portnum << SOCKIT_OWM_CTL_SEL_OFST) + | (SOCKIT_OWM_CTL_CYC_MSK) + | (SOCKIT_OWM_CTL_DAT_MSK)); + reg = __wait_cycle(BASE_ONEWIRE); + return (reg & SOCKIT_OWM_CTL_DAT_MSK) ? 1 : 0; +} + +static void w1_write_bit(struct w1_bus *bus, int bit) +{ + int portnum = bus->detail; + + IOWR_SOCKIT_OWM_CTL(BASE_ONEWIRE, (portnum << SOCKIT_OWM_CTL_SEL_OFST) + | (SOCKIT_OWM_CTL_CYC_MSK) + | (bit ? SOCKIT_OWM_CTL_DAT_MSK : 0)); + __wait_cycle(BASE_ONEWIRE); +} + +struct w1_ops wrpc_w1_ops = { + .reset = w1_reset, + .read_bit = w1_read_bit, + .write_bit = w1_write_bit, +}; + +struct w1_bus wrpc_w1_bus; + +/* Init from sockitowm code */ +#define CLK_DIV_NOR (CPU_CLOCK / 200000 - 1) /* normal mode */ +#define CLK_DIV_OVD (CPU_CLOCK / 1000000 - 1) /* overdrive mode (not used) */ +void wrpc_w1_init(void) +{ + IOWR_SOCKIT_OWM_CDR(BASE_ONEWIRE, + ((CLK_DIV_NOR & SOCKIT_OWM_CDR_N_MSK) | + ((CLK_DIV_OVD << SOCKIT_OWM_CDR_O_OFST) & + SOCKIT_OWM_CDR_O_MSK))); +} diff --git a/modules/lm32-include/wrpc-import/dev/w1-temp.c b/modules/lm32-include/wrpc-import/dev/w1-temp.c new file mode 100644 index 0000000000..763330df94 --- /dev/null +++ b/modules/lm32-include/wrpc-import/dev/w1-temp.c @@ -0,0 +1,78 @@ +/* + * Temperature input for DS18S20 (family 0x10) + * Alessandro Rubini, 2013 GNU GPL2 or later + */ +#include +#include + +int32_t w1_read_temp(struct w1_dev *dev, unsigned long flags) +{ + static uint8_t scratchpad[8]; + int class = w1_class(dev); + int32_t res; + int16_t cval; + int i; + + /* The caller is expected to have checked the class. but still... */ + switch(class) { + case 0x10: case 0x28: case 0x42: + break; /* Supported, at least for temperature input */ + default: + return 1<<31; /* very negative */ + } + + /* If so asked, jump over start-conversion and only collect result */ + if (flags & W1_FLAG_COLLECT) + goto collect; + + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDT_CONVERT); + + /* If so asked, don't wait for the conversion to be over */ + if (flags & W1_FLAG_NOWAIT) + return 0; + + while(wrpc_w1_ops.read_bit(dev->bus) == 0) + ; +collect: + w1_match_rom(dev); + w1_write_byte(dev->bus, W1_CMDT_R_SPAD); + for (i = 0; i < sizeof(scratchpad); i++) + scratchpad[i] = w1_read_byte(dev->bus); + + res = 0; + cval = scratchpad[1] << 8 | scratchpad[0]; + + switch(class) { + case 0x10: + /* 18S20: two bytes plus "count remain" value */ + res = (int32_t)cval << 15; /* 1 decimal points */ + res -= 0x4000; /* - 0.25 degrees */ + res |= scratchpad[6] << 12; /* 1/16th of degree each */ + break; + + case 0x28: + case 0x42: + /* 18B20 and DS28EA00: only the two bytes */ + res = (int32_t)cval << 12; /* 4 decimal points */ + break; + } + return res; +} + +int32_t w1_read_temp_bus(struct w1_bus *bus, unsigned long flags) +{ + int i, class; + + for (i = 0; i < W1_MAX_DEVICES; i++) { + class = w1_class(bus->devs + i); + switch(class) { + case 0x10: case 0x28: case 0x42: + return w1_read_temp(bus->devs + i, flags); + default: + break; + } + } + /* not found */ + return 1 << 31; +} diff --git a/modules/lm32-include/wrpc-import/dev/w1.c b/modules/lm32-include/wrpc-import/dev/w1.c new file mode 100644 index 0000000000..0948ba24c8 --- /dev/null +++ b/modules/lm32-include/wrpc-import/dev/w1.c @@ -0,0 +1,145 @@ +/* + * Onewire generic interface + * Alessandro Rubini, 2013 GNU GPL2 or later + */ +#include +#include +#include + +static const struct w1_ops *ops = &wrpc_w1_ops; /* local shorter name */ + +void w1_write_byte(struct w1_bus *bus, int byte) +{ + int i; + + for (i = 1; i < 0x100; i <<= 1) + ops->write_bit(bus, byte & i ? 1 : 0); +} + +int w1_read_byte(struct w1_bus *bus) +{ + int i, res = 0; + + for (i = 1; i < 0x100; i <<= 1) + res |= ops->read_bit(bus) ? i : 0; + usleep(100); /* inter-byte, for my eyes only */ + return res; + +} + +/* scan_bus requires this di-bit helper */ +enum __bits {B_0, B_1, B_BOTH}; + +/* return what we get, select it if unambiguous or the one passed */ +static enum __bits __get_dibit(struct w1_bus *bus, int select) +{ + int a, b; + + a = ops->read_bit(bus); + b = ops->read_bit(bus); + if (a != b) { + ops->write_bit(bus, a); + return a ? B_1 : B_0; + } + ops->write_bit(bus, select); + return B_BOTH; +} + +/* + * This identifies one. Returns 0 if not found, -1 on error. The current mask + * is used to return the conflicts we found: on each conflict, we follow + * what's already in our id->rom, but remember it for later scans. + */ +static int __w1_scan_one(struct w1_bus *bus, uint64_t *rom, uint64_t *cmask) +{ + uint64_t mask; + int select; + enum __bits b; + + if (ops->reset(bus) != 1) + return -1; + w1_write_byte(bus, 0xf0); /* search rom */ + + /* + * Send all bits we have (initially, zero). + * On a conflict, follow what we have in rom and possibly mark it. + */ + *cmask = 0; + for (mask = 1; mask; mask <<= 1) { + select = *rom & mask; + b = __get_dibit(bus, select); + + switch(b) { + case B_1: + *rom |= mask; + case B_0: + break; + case B_BOTH: + /* if we follow 1, it's resolved, else mark it */ + if (!select) + *cmask |= mask; + break; + } + } + return 0; +} + +int w1_scan_bus(struct w1_bus *bus) +{ + uint64_t mask; + uint64_t cmask; /* current */ + struct w1_dev *d; + int i; + + memset(bus->devs, 0, sizeof(bus->devs)); + + if (!ops->reset) + return 0; /* no devices */ + for (i = 0, cmask = 0; i < W1_MAX_DEVICES; i++) { + d = bus->devs + i; + d->bus = bus; + + if (i) { /* Not first: scan conflicts and resolve last */ + d->rom = bus->devs[i-1].rom; + for (mask = (1ULL<<63); mask; mask >>= 1) { + /* + * Warning: lm32 compiter treats as signed! + * + * Even if mask is uint64_t, the shift in the + * for loop above is signed, so fix it. + * I prefer not to change the loop, as the + * code is in use elsewhere and I prefer to + * keep differences to a minimum + */ + if (mask & (1ULL<<62)) + mask = (1ULL<<62); + + if (cmask & mask) + break; + d->rom &= ~mask; + } + if (!mask) { + /* no conflicts to solve: done */ + return i; + } + d->rom |= mask; /* we'll reply 1 next loop */ + cmask &= ~mask; + } + if (__w1_scan_one(bus, &d->rom, &cmask)) { + /* error on this one */ + return i; + } + } + return i; +} + +void w1_match_rom(struct w1_dev *dev) +{ + int i; + + ops->reset(dev->bus); + w1_write_byte(dev->bus, W1_CMD_MATCH_ROM); /* match rom */ + for (i = 0; i < 64; i+=8) { + w1_write_byte(dev->bus, (int)(dev->rom >> i) ); + } +} diff --git a/modules/lm32-include/wrpc-import/dev/w1.h b/modules/lm32-include/wrpc-import/dev/w1.h new file mode 100644 index 0000000000..33328a4cf7 --- /dev/null +++ b/modules/lm32-include/wrpc-import/dev/w1.h @@ -0,0 +1,89 @@ +/* + * Onewire generic interface + * Alessandro Rubini, 2013 GNU GPL2 or later + */ +#ifndef __BATHOS_W1_H__ +#define __BATHOS_W1_H__ + +#include + +#define W1_MAX_DEVICES 8 /* we have no alloc */ + +struct w1_dev { + struct w1_bus *bus; + uint64_t rom; +}; + +static inline int w1_class(struct w1_dev *dev) +{ + return dev->rom & 0xff; +} + + +struct w1_bus { + unsigned long detail; /* gpio bit or whatever (driver-specific) */ + struct w1_dev devs[W1_MAX_DEVICES]; +}; + +/* + * The low-level driver is based on this set of operations. We expect to + * only have one set of such operations in each build. (i.e., no bus-specific + * operations, to keep the thing simple and small). + */ +struct w1_ops { + int (*reset)(struct w1_bus *bus); /* returns 1 on "present" */ + int (*read_bit)(struct w1_bus *bus); + void (*write_bit)(struct w1_bus *bus, int bit); +}; + +/* Library functions */ +extern int w1_scan_bus(struct w1_bus *bus); +extern void w1_write_byte(struct w1_bus *bus, int byte); +extern int w1_read_byte(struct w1_bus *bus); +extern void w1_match_rom(struct w1_dev *dev); + +#define W1_CMD_SEARCH_ROM 0xf0 +#define W1_CMD_READ_ROM 0x33 +#define W1_CMD_MATCH_ROM 0x55 +#define W1_CMD_SKIP_ROM 0xcc +#define W1_CMD_ASEARCH 0xec + +/* commands for specific families */ +#define W1_CMDT_CONVERT 0x44 +#define W1_CMDT_W_SPAD 0x4e +#define W1_CMDT_R_SPAD 0xbe +#define W1_CMDT_CP_SPAD 0x48 +#define W1_CMDT_RECALL 0xb8 +#define W1_CMDT_R_PS 0xb4 +/* EEPROM DS28EC20 */ +#define W1_CMDR_W_SPAD 0x0f +#define W1_CMDR_R_SPAD 0xaa +#define W1_CMDR_C_SPAD 0x55 +#define W1_CMDR_R_MEMORY 0xf0 +#define W1_CMDR_EXT_R_MEMORY 0xa5 + +/* Temperature conversion takes time: by default wait, but allow flags */ +#define W1_FLAG_NOWAIT 0x01 /* start conversion only*/ +#define W1_FLAG_COLLECT 0x02 /* don't start, just get output */ + +/* These functions are dev-specific */ +extern int32_t w1_read_temp(struct w1_dev *dev, unsigned long flags); +extern int w1_read_eeprom(struct w1_dev *dev, + int offset, uint8_t *buffer, int blen); +extern int w1_write_eeprom(struct w1_dev *dev, + int offset, const uint8_t *buffer, int blen); +extern int w1_erase_eeprom(struct w1_dev *dev, int offset, int blen); + +/* These are generic, using the first suitable device in the bus */ +extern int32_t w1_read_temp_bus(struct w1_bus *bus, unsigned long flags); +extern int w1_read_eeprom_bus(struct w1_bus *bus, + int offset, uint8_t *buffer, int blen); +extern int w1_write_eeprom_bus(struct w1_bus *bus, + int offset, const uint8_t *buffer, int blen); +extern int w1_erase_eeprom_bus(struct w1_bus *bus, int offset, int blen); + +extern struct w1_ops wrpc_w1_ops; +extern struct w1_bus wrpc_w1_bus; +extern void wrpc_w1_init(void); + +#endif /* __BATHOS_W1_H__ */ diff --git a/modules/lm32-include/wrpc-import/div64.c b/modules/lm32-include/wrpc-import/div64.c new file mode 100644 index 0000000000..d175bc4a04 --- /dev/null +++ b/modules/lm32-include/wrpc-import/div64.c @@ -0,0 +1,53 @@ +/* This file in ppsi is a subset of lib/div64.c in Linux source code */ + +/* + * Copyright (C) 2003 Bernardo Innocenti + * + * Based on former do_div() implementation from asm-parisc/div64.h: + * Copyright (C) 1999 Hewlett-Packard Co + * Copyright (C) 1999 David Mosberger-Tang + * + * + * Generic C version of 64bit/32bit division and modulo, with + * 64bit result and 32bit remainder. + * + * The fast case for (n>>32 == 0) is handled inline by do_div(). + * + * Code generated for this function might be very inefficient + * for some CPUs. __div64_32() can be overridden by linking arch-specific + * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S. + */ +#include + +uint32_t __div64_32(uint64_t *n, uint32_t base) +{ + uint64_t rem = *n; + uint64_t b = base; + uint64_t res, d = 1; + uint32_t high = rem >> 32; + + /* Reduce the thing a bit first */ + res = 0; + if (high >= base) { + high /= base; + res = (uint64_t) high << 32; + rem -= (uint64_t) (high*base) << 32; + } + + while ((int64_t)b > 0 && b < rem) { + b = b+b; + d = d+d; + } + + do { + if (rem >= b) { + rem -= b; + res += d; + } + b >>= 1; + d >>= 1; + } while (d); + + *n = res; + return rem; +} diff --git a/modules/lm32-include/wrpc-import/hw/etherbone.h b/modules/lm32-include/wrpc-import/hw/etherbone.h new file mode 100644 index 0000000000..3e26b932bc --- /dev/null +++ b/modules/lm32-include/wrpc-import/hw/etherbone.h @@ -0,0 +1,12 @@ +/* + * This work is part of the White Rabbit project + * + * Released according to the GNU GPL, version 2 or any later version. + */ + +#ifndef __ETHERBONE_H__ +#define __ETHERBONE_H__ + +void eb_setIP(unsigned char *IP); + +#endif diff --git a/modules/lm32-include/wrpc-import/hw/rawmem.h b/modules/lm32-include/wrpc-import/hw/rawmem.h new file mode 100644 index 0000000000..d1039b7d85 --- /dev/null +++ b/modules/lm32-include/wrpc-import/hw/rawmem.h @@ -0,0 +1,16 @@ +#ifndef __HW_RAWMEM_H +#define __HW_RAWMEM_H + +#include + +static inline void writel(uint32_t data, void *where) +{ + * (volatile uint32_t *)where = data; +} + +static inline uint32_t readl(void *where) +{ + return * (volatile uint32_t *)where; +} + +#endif \ No newline at end of file diff --git a/modules/lm32-include/wrpc-import/hw/sockit_owm_regs.h b/modules/lm32-include/wrpc-import/hw/sockit_owm_regs.h new file mode 100644 index 0000000000..244728bf19 --- /dev/null +++ b/modules/lm32-include/wrpc-import/hw/sockit_owm_regs.h @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////////////// +// // +// Minimalistic 1-wire (onewire) master with Avalon MM bus interface // +// // +// Copyright (C) 2010 Iztok Jeras // +// // +////////////////////////////////////////////////////////////////////////////// +// // +// This program is free software: you can redistribute it and/or modify // +// it under the terms of the GNU Lesser General Public License // +// as published by the Free Software Foundation, either // +// version 3 of the License, or (at your option) any later version. // +// // +// This program is distributed in the hope that it will be useful, // +// but WITHOUT ANY WARRANTY; without even the implied warranty of // +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // +// GNU General Public License for more details. // +// // +// You should have received a copy of the GNU General Public License // +// along with this program. If not, see . // +// // +////////////////////////////////////////////////////////////////////////////// + + +#ifndef __SOCKIT_OWM_REGS_H__ +#define __SOCKIT_OWM_REGS_H__ + + + +////////////////////////////////////////////////////////////////////////////// +// control status register // +////////////////////////////////////////////////////////////////////////////// + +#define SOCKIT_OWM_CTL_REG 0 +#define IOADDR_SOCKIT_OWM_CTL(base) IO_CALC_ADDRESS_NATIVE(base, SOCKIT_OWM_CTL_REG) +#define IORD_SOCKIT_OWM_CTL(base) (*(( volatile int*)base + SOCKIT_OWM_CTL_REG)) +#define IOWR_SOCKIT_OWM_CTL(base, data) (*(( volatile int*)base + SOCKIT_OWM_CTL_REG)) = data + +#define SOCKIT_OWM_CTL_DAT_MSK (0x00000001) // data bit +#define SOCKIT_OWM_CTL_DAT_OFST (0) +#define SOCKIT_OWM_CTL_RST_MSK (0x00000002) // reset +#define SOCKIT_OWM_CTL_RST_OFST (1) +#define SOCKIT_OWM_CTL_OVD_MSK (0x00000004) // overdrive +#define SOCKIT_OWM_CTL_OVD_OFST (2) +#define SOCKIT_OWM_CTL_CYC_MSK (0x00000008) // cycle +#define SOCKIT_OWM_CTL_CYC_OFST (3) +#define SOCKIT_OWM_CTL_PWR_MSK (0x00000010) // power (strong pull-up), if there is a single 1-wire line +#define SOCKIT_OWM_CTL_PWR_OFST (5) +#define SOCKIT_OWM_CTL_RSV_MSK (0x00000020) // reserved +#define SOCKIT_OWM_CTL_RSV_OFST (5) +#define SOCKIT_OWM_CTL_IRQ_MSK (0x00000040) // irq status +#define SOCKIT_OWM_CTL_IRQ_OFST (6) +#define SOCKIT_OWM_CTL_IEN_MSK (0x00000080) // irq enable +#define SOCKIT_OWM_CTL_IEN_OFST (7) + +#define SOCKIT_OWM_CTL_SEL_MSK (0x00000f00) // port select number +#define SOCKIT_OWM_CTL_SEL_OFST (8) + +#define SOCKIT_OWM_CTL_POWER_MSK (0xffff0000) // power (strong pull-up), if there is more than one 1-wire line +#define SOCKIT_OWM_CTL_POWER_OFST (16) + +// two common commands +#define SOCKIT_OWM_CTL_DLY_MSK ( SOCKIT_OWM_CTL_RST_MSK | SOCKIT_OWM_CTL_DAT_MSK) +#define SOCKIT_OWM_CTL_IDL_MSK (SOCKIT_OWM_CTL_OVD_MSK | SOCKIT_OWM_CTL_RST_MSK | SOCKIT_OWM_CTL_DAT_MSK) + +////////////////////////////////////////////////////////////////////////////// +// clock divider ratio register // +////////////////////////////////////////////////////////////////////////////// + +#define SOCKIT_OWM_CDR_REG 1 +#define IOADDR_SOCKIT_OWM_CDR(base) IO_CALC_ADDRESS_NATIVE(base, SOCKIT_OWM_CDR_REG) +#define IORD_SOCKIT_OWM_CDR(base) (*(( volatile int*)base + SOCKIT_OWM_CDR_REG)) +#define IOWR_SOCKIT_OWM_CDR(base, data) (*(( volatile int*)base + SOCKIT_OWM_CDR_REG)) = data + +#define SOCKIT_OWM_CDR_N_MSK (0x0000ffff) // normal mode +#define SOCKIT_OWM_CDR_N_OFST (0) +#define SOCKIT_OWM_CDR_O_MSK (0xffff0000) // overdrive mode +#define SOCKIT_OWM_CDR_O_OFST (16) + + +#endif /* __SOCKIT_OWM_REGS_H__ */ + diff --git a/modules/lm32-include/wrpc-import/hw/wb_uart.h b/modules/lm32-include/wrpc-import/hw/wb_uart.h new file mode 100644 index 0000000000..4d65c07e99 --- /dev/null +++ b/modules/lm32-include/wrpc-import/hw/wb_uart.h @@ -0,0 +1,137 @@ +/* + Register definitions for slave core: Simple Wishbone UART + + * File : wb_uart.h + * Author : auto-generated by wbgen2 from simple_uart_wb.wb + * Created : Tue Aug 25 17:17:50 2020 + * Standard : ANSI C + + THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb + DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! + +*/ + +#ifndef __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB +#define __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB + +#ifdef __KERNEL__ +#include +#else +#include +#endif + +#if defined( __GNUC__) +#define PACKED __attribute__ ((packed)) +#else +#error "Unsupported compiler?" +#endif + +#ifndef __WBGEN2_MACROS_DEFINED__ +#define __WBGEN2_MACROS_DEFINED__ +#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset)) +#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset)) +#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1)) +#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1< +#else +#include +#endif + +#if defined( __GNUC__) +#define PACKED __attribute__ ((packed)) +#else +#error "Unsupported compiler?" +#endif + +#ifndef __WBGEN2_MACROS_DEFINED__ +#define __WBGEN2_MACROS_DEFINED__ +#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset)) +#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset)) +#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1)) +#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1< + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#include +#include +//#include + +static int usleep_lpj; /* loops per jiffy */ + + +static inline void __delay(int count) +{ + while (count-- > 0) + asm(""); +} + + +static int verify_lpj(int lpj) +{ + unsigned long j; + + /* wait for the beginning of a tick */ + j = timer_get_tics() + 1; + while (timer_get_tics() < j) + ; + + __delay(lpj); + + /* did it expire? */ + j = timer_get_tics() - j; + if (0) + pp_printf("check %i: %li\n", lpj, j); + return j; +} + +void usleep_init(void) +{ + int lpj = 1024, test_lpj; + int step = 1024; + + /* Increase until we get over it */ + while (verify_lpj(lpj) == 0) { + lpj += step; + step *= 2; + } + /* Ok, now we are over; half again and restart */ + lpj /= 2; step /= 4; + + /* So, *this* jpj is lower, and with two steps we are higher */ + while (step) { + test_lpj = lpj + step; + if (verify_lpj(test_lpj) == 0) + lpj = test_lpj; + step /= 2; + } + usleep_lpj = lpj; + //main_dbg("calibrating usleep(): loops per jiffy = %i\n", lpj); +} + +/* lpj is around 20800 on the spec: the above calculation overflows at 200ms */ +int usleep(unsigned usec) +{ + /* Sleep 10ms each time, so we support 20x faster cards */ + const int step = 10 * 1000; + const int usec_per_jiffy = 1000 * 1000 / TICS_PER_SECOND; + const int count_per_step = usleep_lpj * step / usec_per_jiffy; + + while (usec > step) { + __delay(count_per_step); + usec -= step; + } + __delay(usec * usleep_lpj / usec_per_jiffy); + return 0; +} diff --git a/modules/lm32-include/wrpc-import/memlayout.h b/modules/lm32-include/wrpc-import/memlayout.h new file mode 100644 index 0000000000..883ba7b7b3 --- /dev/null +++ b/modules/lm32-include/wrpc-import/memlayout.h @@ -0,0 +1,25 @@ +/* + * This work is part of the White Rabbit project + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#ifndef __REGS_H +#define __REGS_H + +//#define SDB_ADDRESS 0x30000 + +unsigned char *BASE_MINIC; +unsigned char *BASE_EP; +unsigned char *BASE_SOFTPLL; +unsigned char *BASE_PPS_GEN; +unsigned char *BASE_SYSCON; +unsigned char *BASE_UART; +unsigned char *BASE_ONEWIRE; +unsigned char *BASE_ETHERBONE_CFG; + +#define FMC_EEPROM_ADR 0x50 + +void sdb_find_devices(void); +void sdb_print_devices(void); + +#endif diff --git a/modules/lm32-include/wrpc-import/pp-printf.h b/modules/lm32-include/wrpc-import/pp-printf.h new file mode 100644 index 0000000000..30f715909f --- /dev/null +++ b/modules/lm32-include/wrpc-import/pp-printf.h @@ -0,0 +1,17 @@ +#include + +extern int pp_printf(const char *fmt, ...) + __attribute__((format(printf,1,2))); + +extern int pp_sprintf(char *s, const char *fmt, ...) + __attribute__((format(printf,2,3))); + +extern int pp_vprintf(const char *fmt, va_list args); + +extern int pp_vsprintf(char *buf, const char *, va_list) + __attribute__ ((format (printf, 2, 0))); + +/* This is what we rely on for output */ +extern int puts(const char *s); + + diff --git a/modules/lm32-include/wrpc-import/printf.c b/modules/lm32-include/wrpc-import/printf.c new file mode 100644 index 0000000000..ec5b96e976 --- /dev/null +++ b/modules/lm32-include/wrpc-import/printf.c @@ -0,0 +1,43 @@ +/* + * Basic printf based on vprintf based on vsprintf + * + * Alessandro Rubini for CERN, 2011 -- public domain + * (please note that the vsprintf is not public domain but GPL) + */ +#include +#include + +static char print_buf[CONFIG_PRINT_BUFSIZE]; + +int pp_vprintf(const char *fmt, va_list args) +{ + int ret; + + ret = pp_vsprintf(print_buf, fmt, args); + puts(print_buf); + return ret; +} + +int pp_sprintf(char *s, const char *fmt, ...) +{ + va_list args; + int ret; + + va_start(args, fmt); + ret = pp_vsprintf(s, fmt, args); + va_end(args); + return ret; +} + + +int pp_printf(const char *fmt, ...) +{ + va_list args; + int ret; + + va_start(args, fmt); + ret = pp_vprintf(fmt, args); + va_end(args); + + return ret; +} diff --git a/modules/lm32-include/wrpc-import/syscon.h b/modules/lm32-include/wrpc-import/syscon.h new file mode 100644 index 0000000000..09f7e1a690 --- /dev/null +++ b/modules/lm32-include/wrpc-import/syscon.h @@ -0,0 +1,105 @@ +/* + * This work is part of the White Rabbit project + * + * Copyright (C) 2012 - 2015 CERN (www.cern.ch) + * Author: Grzegorz Daniluk + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#ifndef __SYSCON_H +#define __SYSCON_H + +#include +#include +#include "board.h" + +uint32_t timer_get_tics(void); +void timer_delay(uint32_t tics); + +/* The following ones come from the kernel, but simplified */ +#ifndef time_after +#define time_after(a,b) \ + ((long)(b) - (long)(a) < 0) +#define time_before(a,b) time_after(b,a) +#define time_after_eq(a,b) \ + ((long)(a) - (long)(b) >= 0) +#define time_before_eq(a,b) time_after_eq(b,a) +#endif + +/* This can be used for up to 2^32 / TICS_PER_SECONDS == 42 seconds in wrs */ +static inline void timer_delay_ms(int ms) +{ + timer_delay(ms * TICS_PER_SECOND / 1000); +} + +/* usleep.c */ +//extern void usleep_init(void); +//#ifndef unix +//extern int usleep(unsigned usec); +//#endif + + +#ifdef CONFIG_WR_NODE + +#undef PACKED /* if we already included a regs file, we'd get a warning */ +#include + +struct SYSCON_WB { + uint32_t RSTR; /*Syscon Reset Register */ + uint32_t GPSR; /*GPIO Set/Readback Register */ + uint32_t GPCR; /*GPIO Clear Register */ + uint32_t HWFR; /*Hardware Feature Register */ + uint32_t HWIR; /*Hardware Info Register */ + uint32_t SDBFS; /*Flash SDBFS Info Register */ + uint32_t TCR; /*Timer Control Register */ + uint32_t TVR; /*Timer Counter Value Register */ + uint32_t DIAG_INFO; + uint32_t DIAG_NW; + uint32_t DIAG_CR; + uint32_t DIAG_DAT; +}; + +/* GPIO pins */ + +extern const struct gpio_pin pin_sysc_led_link; +extern const struct gpio_pin pin_sysc_led_stat; +extern const struct gpio_pin pin_sysc_btn1; +extern const struct gpio_pin pin_sysc_btn2; +extern const struct gpio_pin pin_sysc_sfp_det; +extern const struct gpio_pin pin_sysc_spi_sclk; +extern const struct gpio_pin pin_sysc_spi_ncs; +extern const struct gpio_pin pin_sysc_spi_mosi; +extern const struct gpio_pin pin_sysc_spi_miso; +extern const struct gpio_pin pin_sysc_fmc_scl; +extern const struct gpio_pin pin_sysc_fmc_sda; +extern const struct gpio_pin pin_sysc_sfp_scl; +extern const struct gpio_pin pin_sysc_sfp_sda; +extern const struct gpio_pin pin_sysc_net_rst; + +extern const struct i2c_bus dev_i2c_fmc; +extern const struct i2c_bus dev_i2c_sfp; +extern struct spi_flash_device wrc_flash_dev; + +#define FMC_I2C_DELAY 15 +#define SFP_I2C_DELAY 300 + +void timer_init(uint32_t enable); + +extern struct spi_bus spi_wrc_flash; +extern struct spi_flash_device wrc_flash_dev; + +#define HW_NAME_LENGTH 5 /* 4 letters + '\0' */ +void get_hw_name(char *str); +void get_storage_info(int *memtype, uint32_t *sdbfs_baddr, uint32_t *blocksize); +int sysc_get_memsize(void); + +#define DIAG_RW_BANK 0 +#define DIAG_RO_BANK 1 +void diag_read_info(uint32_t *id, uint32_t *ver, uint32_t *nrw, uint32_t *nro); +int diag_read_word(uint32_t adr, int bank, uint32_t *val); +int diag_write_word(uint32_t adr, uint32_t val); + +void net_rst(void); + +#endif /* CONFIG_WR_NODE */ +#endif diff --git a/modules/lm32-include/wrpc-import/timer.c b/modules/lm32-include/wrpc-import/timer.c new file mode 100644 index 0000000000..d11126083d --- /dev/null +++ b/modules/lm32-include/wrpc-import/timer.c @@ -0,0 +1,23 @@ +/* + * This work is part of the White Rabbit project + * + * Copyright (C) 2011 CERN (www.cern.ch) + * Author: Grzegorz Daniluk + * + * Released according to the GNU GPL, version 2 or any later version. + */ + + +#include "board.h" +#include "hw/wrc_syscon_regs.h" +#include "hw/rawmem.h" + +void timer_init(int enable) +{ + writel( SYSC_TCR_ENABLE, (void*) BASE_SYSCON + SYSC_REG_TCR ); +} + +uint32_t timer_get_tics() +{ + return readl( (void*) BASE_SYSCON + SYSC_REG_TVR ); +} diff --git a/modules/lm32-include/wrpc-import/uart.c b/modules/lm32-include/wrpc-import/uart.c new file mode 100644 index 0000000000..b457a7abfb --- /dev/null +++ b/modules/lm32-include/wrpc-import/uart.c @@ -0,0 +1,83 @@ +/* + * DSI Shield + * + * Copyright (C) 2013-2014 twl + * + * This program is free software: you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation, either version 3 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* uart.c - simple UART driver */ + +#include + +#include "uart.h" +#include "board.h" +#include "mini_sdb.h" + +#include + +PACKED struct UART_WB { + /* [0x0]: REG Status Register */ + uint32_t SR; + /* [0x4]: REG Baudrate control register */ + uint32_t BCR; + /* [0x8]: REG Transmit data regsiter */ + uint32_t TDR; + /* [0xc]: REG Receive data regsiter */ + uint32_t RDR; +}; + +#define CALC_BAUD(baudrate) \ + ( ((( (unsigned int)baudrate << 12)) + \ + (BASE_CLOCK >> 8)) / (BASE_CLOCK >> 7) ) + +volatile struct UART_WB *uart; + +void uart_init_hw() +{ + uart = (volatile struct UART_WB *)pUart; +#if 0 + // WRPC will do this + uart->BCR = CALC_BAUD((CPU_CLOCK/10)); +#endif + +} + +void uart_write_byte(int b) +{ + if (b == '\n') + uart_write_byte('\r'); + while (uart->SR & UART_SR_TX_BUSY) + ; + uart->TDR = b; +} + +int uart_poll() +{ + return uart->SR & UART_SR_RX_RDY; +} + +int uart_read_byte() +{ + if (!uart_poll()) + return -1; + + return uart->RDR & 0xff; +} +int puts(const char *s) +{ + char c; + while(c=*s++) + uart_write_byte(c); +} diff --git a/modules/lm32-include/wrpc-import/uart.h b/modules/lm32-include/wrpc-import/uart.h new file mode 100644 index 0000000000..ece8f15af4 --- /dev/null +++ b/modules/lm32-include/wrpc-import/uart.h @@ -0,0 +1,35 @@ +/* + * DSI Shield + * + * Copyright (C) 2013-2014 twl + * + * This program is free software: you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation, either version 3 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + + +#ifndef __UART_H +#define __UART_H + +void uart_init_sw(void); +void uart_init_hw(void); +void uart_write_byte(int b); +int uart_write_string(const char *s); +int puts(const char *s); +int uart_read_byte(void); + +/* uart-sw is used by ppsi (but may be wrapped to normal uart) */ +int uart_sw_write_string(const char *s); + + +#endif diff --git a/modules/lm32-include/wrpc-import/util.h b/modules/lm32-include/wrpc-import/util.h new file mode 100644 index 0000000000..ce7e7554f4 --- /dev/null +++ b/modules/lm32-include/wrpc-import/util.h @@ -0,0 +1,105 @@ +/* + * This work is part of the White Rabbit project + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#ifndef __UTIL_H +#define __UTIL_H + +#include + +/* Color codes for cprintf()/pcprintf() */ +#define C_DIM 0x80 + +#define C_RED 1 +#define C_GREEN 2 +#define C_BLUE 4 +#define C_MAGENTA 5 +#define C_CYAN 6 +#define C_GREY 7 +/* Default foreground color, White or Black depends on User's terminal */ +#define C_WHITE 9 + +/* Return TAI date/time in human-readable form. Non-reentrant. */ +char *format_time(uint64_t sec, int format); +#define TIME_FORMAT_LEGACY 0 +#define TIME_FORMAT_SYSLOG 1 +#define TIME_FORMAT_SORTED 2 + +typedef struct +{ + uint32_t start_tics; + uint32_t timeout; +} timeout_t; + +/* Color printf() variant. Does not restore color */ +void cprintf(int color, const char *fmt, ...); + +/* Color printf() variant, sets curspor position to (row, col) too. + * Does not restore color */ +void pcprintf(int row, int col, int color, const char *fmt, ...); + +/* Printf, sets curspor position to (row, col) */ +void pprintf(int row, int col, const char *fmt, ...); + +void __debug_printf(const char *fmt, ...); + +/* Clears the terminal screen */ +void term_clear(void); + +/* Clears the terminal screen from cursor to the end */ +void term_clear_to_end(void); + +int tmo_init(timeout_t *tmo, uint32_t milliseconds); +int tmo_restart(timeout_t *tmo); +int tmo_expired(timeout_t *tmo); + +int atoi(const char *s); + +const char *fromhex(const char *hex, int *v); +const char *fromhex64(const char *hex, int64_t *v); +const char *fromdec(const char *dec, int *v); + +char *format_mac(char *s, const unsigned char *mac); +char *format_hex8(char *s, const unsigned char *mac); + +void decode_mac(const char *str, unsigned char *mac); +void decode_port(const char *str, int *port); + +/* div64.c, lifted from the linux kernel through pp_printf or ppsi */ +extern uint32_t __div64_32(uint64_t *n, uint32_t base); + +static inline int within_range(int x, int minval, int maxval, int wrap) +{ + int rv; + + //printf("min %d max %d x %d ", minval, maxval, x); + + while (maxval >= wrap) + maxval -= wrap; + + while (maxval < 0) + maxval += wrap; + + while (minval >= wrap) + minval -= wrap; + + while (minval < 0) + minval += wrap; + + while (x < 0) + x += wrap; + + while (x >= wrap) + x -= wrap; + + if (maxval > minval) + rv = (x >= minval && x <= maxval) ? 1 : 0; + else + rv = (x >= minval || x <= maxval) ? 1 : 0; + + return rv; +} + + +#endif diff --git a/modules/lm32-include/wrpc-import/vsprintf-full.c b/modules/lm32-include/wrpc-import/vsprintf-full.c new file mode 100644 index 0000000000..3d61b19f2d --- /dev/null +++ b/modules/lm32-include/wrpc-import/vsprintf-full.c @@ -0,0 +1,417 @@ +/* + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + * GNU GPL version 2 + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +/* Retrieved from u-boot on 2010-02, changed some stuff (ARub) */ +#include +#include +#include + +/* BEGIN OF HACKS */ +#include +#include "util.h" + +#define CONFIG_PRINTF_64BIT +/* -- but if we typedef we get redefined type when hosted */ +#define u8 uint8_t +#define size_t unsigned long +#define ptrdiff_t unsigned long + +#define noinline __attribute__((noinline)) + +/* + * We now have optional 64-bit support. It depends on __div64_32. + * The suggested implementaion is the one by Bernardo Innocenti, found + * in asm-generic in the kernel -- ARub + */ +#ifdef CONFIG_PRINTF_64BIT + +#define NUMBER_TYPE uint64_t +#define SIGNED_NUMBER_TYPE int64_t + +/* The unnecessary pointer compare is there + * to check for type safety (n must be 64bit) + */ +#define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ + if (((n) >> 32) == 0) { \ + __rem = (uint32_t)(n) % __base; \ + (n) = (uint32_t)(n) / __base; \ + } else \ + __rem = __div64_32(&(n), __base); \ + __rem; \ + }) + +#else /* 32 bits (or native 64 bits): a reduced version of above */ + +#define NUMBER_TYPE unsigned long +#define SIGNED_NUMBER_TYPE signed long + +#define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + (void)(((typeof((n)) *)0) == ((unsigned long *)0)); \ + __rem = (n) % __base; \ + (n) = (n) / __base; \ + __rem; \ + }) + +#endif /* CONFIG_PRINTF_64BIT */ + +/* END OF HACKS */ + +const char hex_asc[] = "0123456789abcdef"; +#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] +#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] + +static inline char *pack_hex_byte(char *buf, u8 byte) +{ + *buf++ = hex_asc_hi(byte); + *buf++ = hex_asc_lo(byte); + return buf; +} + + +/* we use this so that we can do without the ctype library */ +#define is_digit(c) ((c) >= '0' && (c) <= '9') + +static int skip_atoi(const char **s) +{ + int i=0; + + while (is_digit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} + +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SMALL 32 /* Must be 32 == 0x20 */ +#define SPECIAL 64 /* 0x */ + +static char *number(char *buf, NUMBER_TYPE num, int base, int size, int precision, int type) +{ + /* we are called with base 8, 10 or 16, only, thus don't need "G..." */ + static const char digits[16] = "0123456789ABCDEF"; /* "GHIJKLMNOPQRSTUVWXYZ"; */ + + char tmp[66]; + char sign; + char locase; + int need_pfx = ((type & SPECIAL) && base != 10); + int i; + + /* locase = 0 or 0x20. ORing digits or letters with 'locase' + * produces same digits or (maybe lowercased) letters */ + locase = (type & SMALL); + if (type & LEFT) + type &= ~ZEROPAD; + sign = 0; + if (type & SIGN) { + if ((SIGNED_NUMBER_TYPE) num < 0) { + sign = '-'; + num = - (SIGNED_NUMBER_TYPE) num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (need_pfx) { + size--; + if (base == 16) + size--; + } + + /* generate full string in tmp[], in reverse order */ + i = 0; + if (num == 0) + tmp[i++] = '0'; + /* Generic code, for any base: */ + else do { + tmp[i++] = (digits[do_div(num,base)] | locase); + } while (num != 0); + + /* printing 100 using %2d gives "100", not "00" */ + if (i > precision) + precision = i; + /* leading space padding */ + size -= precision; + if (!(type & (ZEROPAD+LEFT))) + while(--size >= 0) + *buf++ = ' '; + /* sign */ + if (sign) + *buf++ = sign; + /* "0x" / "0" prefix */ + if (need_pfx) { + *buf++ = '0'; + if (base == 16) + *buf++ = ('X' | locase); + } + /* zero or space padding */ + if (!(type & LEFT)) { + char c = (type & ZEROPAD) ? '0' : ' '; + while (--size >= 0) + *buf++ = c; + } + /* hmm even more zero padding? */ + while (i <= --precision) + *buf++ = '0'; + /* actual digits of result */ + while (--i >= 0) + *buf++ = tmp[i]; + /* trailing space padding */ + while (--size >= 0) + *buf++ = ' '; + return buf; +} + +static char *string(char *buf, char *s, int field_width, int precision, int flags) +{ + int len, i; + + if (s == 0) + s = ""; + + len = strnlen(s, precision); + + if (!(flags & LEFT)) + while (len < field_width--) + *buf++ = ' '; + for (i = 0; i < len; ++i) + *buf++ = *s++; + while (len < field_width--) + *buf++ = ' '; + return buf; +} + + +#if 0 +/* + * Show a '%p' thing. A kernel extension is that the '%p' is followed + * by an extra set of alphanumeric characters that are extended format + * specifiers. + * + * -- Such extension is removed in pp_printf + */ +static char *pointer(const char *fmt, char *buf, void *ptr, int field_width, int precision, int flags) +{ + unsigned long plong; + + if (!ptr) + return string(buf, "(null)", field_width, precision, flags); + + flags |= SMALL; + if (field_width == -1) { + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + } + plong = (intptr_t)ptr; + return number(buf, plong, 16, field_width, precision, flags); +} +#endif + +/** + * vsprintf - Format a string and place it in a buffer + * @buf: The buffer to place the result into + * @fmt: The format string to use + * @args: Arguments for the format string + * + * This function follows C99 vsprintf, but has some extensions: + * %pS output the name of a text symbol + * %pF output the name of a function pointer + * %pR output the address range in a struct resource + * + * The function returns the number of characters written + * into @buf. + * + * Call this function if you are already dealing with a va_list. + * You probably want sprintf() instead. + */ +int pp_vsprintf(char *buf, const char *fmt, va_list args) +{ + NUMBER_TYPE num; + int base; + char *str; + + int flags; /* flags to number() */ + + int field_width; /* width of output field */ + int precision; /* min. # of digits for integers; max + number of chars for from string */ + int qualifier; /* 'h', 'l', or 'L' for integer fields */ + /* 'z' support added 23/7/1999 S.H. */ + /* 'z' changed to 'Z' --davidm 1/25/99 */ + /* 't' added for ptrdiff_t */ + + str = buf; + + for (; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + /* process flags */ + flags = 0; + repeat: + ++fmt; /* this also skips first '%' */ + switch (*fmt) { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } + + /* get field width */ + field_width = -1; + if (is_digit(*fmt)) + field_width = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) { + field_width = -field_width; + flags |= LEFT; + } + } + + /* get the precision */ + precision = -1; + if (*fmt == '.') { + ++fmt; + if (is_digit(*fmt)) + precision = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) + precision = 0; + } + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || + *fmt == 'Z' || *fmt == 'z' || *fmt == 't') { + qualifier = *fmt; + ++fmt; + if (qualifier == 'l' && *fmt == 'l') { + qualifier = 'L'; + ++fmt; + } + } + + /* default base */ + base = 10; + + switch (*fmt) { + case 'c': + if (!(flags & LEFT)) + while (--field_width > 0) + *str++ = ' '; + *str++ = (unsigned char) va_arg(args, int); + while (--field_width > 0) + *str++ = ' '; + continue; + + case 's': + str = string(str, va_arg(args, char *), field_width, precision, flags); + continue; + +#if 0 + case 'p': + str = pointer(fmt+1, str, + va_arg(args, void *), + field_width, precision, flags); + continue; +#endif + + case 'n': + if (qualifier == 'l') { + long * ip = va_arg(args, long *); + *ip = (str - buf); + } else { + int * ip = va_arg(args, int *); + *ip = (str - buf); + } + continue; + + case '%': + *str++ = '%'; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'p': + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + case 'x': + flags |= SMALL; + case 'X': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + *str++ = '%'; + if (*fmt) + *str++ = *fmt; + else + --fmt; + continue; + } +#ifdef CONFIG_PRINTF_64BIT + if (qualifier == 'L') + num = va_arg(args, unsigned long long); + else +#endif + if (qualifier == 'l') { + num = va_arg(args, unsigned long); + if (flags & SIGN) + num = (signed long) num; + } else if (qualifier == 'Z' || qualifier == 'z') { + num = va_arg(args, size_t); + } else if (qualifier == 't') { + num = va_arg(args, ptrdiff_t); + } else if (qualifier == 'h') { + num = (unsigned short) va_arg(args, int); + if (flags & SIGN) + num = (signed short) num; + } else { + num = va_arg(args, unsigned int); + if (flags & SIGN) + num = (signed int) num; + } + str = number(str, num, base, field_width, precision, flags); + } + *str = '\0'; + return str-buf; +} diff --git a/modules/lm32-include/wrpc-import/vsprintf-mini.c b/modules/lm32-include/wrpc-import/vsprintf-mini.c new file mode 100644 index 0000000000..d68c848845 --- /dev/null +++ b/modules/lm32-include/wrpc-import/vsprintf-mini.c @@ -0,0 +1,69 @@ +#include +/* + * minimal vsprintf: only %s and hex values + * Alessandro Rubini 2010, based on code in u-boot (from older Linux) + * GNU GPL version 2. + */ +int pp_vsprintf(char *buf, const char *fmt, va_list args) +{ + int i, j; + static char hex[] = "0123456789abcdef"; + char *s; + char *str = buf; + + for (; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + repeat: + fmt++; /* Skip '%' initially, other stuff later */ + + /* Skip the complete format string */ + switch(*fmt) { + case '\0': + goto ret; + case '*': + /* should be precision, just eat it */ + i = va_arg(args, int); + /* fall through: discard unknown stuff */ + default: + goto repeat; + + /* Special cases for conversions */ + + case 'c': /* char: supported */ + *str++ = (unsigned char) va_arg(args, int); + break; + case 's': /* string: supported */ + s = va_arg(args, char *); + while (*s) + *str++ = *s++; + break; + case 'n': /* number-thus-far: not supported */ + break; + case '%': /* supported */ + *str++ = '%'; + break; + + /* all integer (and pointer) are printed as <%08x> */ + case 'o': + case 'x': + case 'X': + case 'd': + case 'i': + case 'u': + case 'p': + i = va_arg(args, int); + *str++ = '<'; + for (j = 28; j >= 0; j -= 4) + *str++ = hex[(i>>j)&0xf]; + *str++ = '>'; + break; + } + } + ret: + *str = '\0'; + return str - buf; +} diff --git a/modules/lm32-include/wrpc-import/vsprintf-none.c b/modules/lm32-include/wrpc-import/vsprintf-none.c new file mode 100644 index 0000000000..7404135415 --- /dev/null +++ b/modules/lm32-include/wrpc-import/vsprintf-none.c @@ -0,0 +1,14 @@ +#include +#include +/* + * empty vsprintf: only the format string. Public domain + */ +int pp_vsprintf(char *buf, const char *fmt, va_list args) +{ + char *str = buf; + + for (; *fmt ; ++fmt) + *str++ = *fmt; + *str++ = '\0'; + return str - buf; +} diff --git a/modules/lm32-include/wrpc-import/vsprintf-xint.c b/modules/lm32-include/wrpc-import/vsprintf-xint.c new file mode 100644 index 0000000000..45e5d6cc4c --- /dev/null +++ b/modules/lm32-include/wrpc-import/vsprintf-xint.c @@ -0,0 +1,116 @@ +/* + * vsprintf-xint: a possible free-software replacement for mprintf + * + * public domain + */ +#include +#include + +static const char hex[] = "0123456789abcdef"; + +static int number(char *out, unsigned value, int base, int lead, int wid) +{ + char tmp[16]; + int i = 16, ret, negative = 0; + + if (wid == 0) + wid = 1; + + /* No error checking at all: it is as ugly as possible */ + if ((signed)value < 0 && base == 10) { + negative = 1; + value = -value; + } + while (value && i) { + tmp[--i] = hex[value % base]; + value /= base; + } + if (i == 16) + tmp[--i] = '0'; + if (negative && lead == ' ') { + tmp[--i] = '-'; + negative = 0; + } + while (i > 16 - wid + negative) + tmp[--i] = lead; + if (negative) + tmp[--i] = '-'; + ret = 16 - i; + while (i < 16) + *(out++) = tmp[i++]; + return ret; +} + +int pp_vsprintf(char *buf, const char *fmt, va_list args) +{ + char *s, *str = buf; + int base, lead, wid; + + for (; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + base = 10; + lead = ' '; + wid = 0; + repeat: + fmt++; /* Skip '%' initially, other stuff later */ + switch(*fmt) { + case '\0': + goto ret; + case '*': + /* should be precision, just eat it */ + base = va_arg(args, int); + /* fall through: discard unknown stuff */ + case '0': + if (wid == 0) { + lead = '0'; + goto repeat; + } /* else go to default */ + default: + if (*fmt >= '0' && *fmt <= '9') { + /* decimal shift left */ + wid *= 10; + wid += *fmt - '0'; + } + goto repeat; + + /* Special cases for conversions */ + + case 'c': /* char: supported */ + *str++ = (unsigned char) va_arg(args, int); + break; + case 's': /* string: supported */ + s = va_arg(args, char *); + while (*s) + *str++ = *s++; + break; + case 'n': /* number-thus-far: not supported */ + break; + case '%': /* supported */ + *str++ = '%'; + break; + + /* integers are more or less printed */ + case 'p': + case 'x': + case 'X': + base = 16; + case 'o': + if (base == 10) /* yet unchaged */ + base = 8; + case 'd': + case 'i': + case 'u': + str += number(str, va_arg(args, int), base, lead, wid); + break; + } + } + ret: + *str = '\0'; + return str - buf; + + +} diff --git a/modules/lm32-include/wrpc-import/wrc.h b/modules/lm32-include/wrpc-import/wrc.h new file mode 100644 index 0000000000..aa13032649 --- /dev/null +++ b/modules/lm32-include/wrpc-import/wrc.h @@ -0,0 +1,104 @@ +/* + * This work is part of the White Rabbit project + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#ifndef __WRC_H__ +#define __WRC_H__ + +/* + * This header includes all generic prototypes that were missing + * in earlier implementations. For example, the monitor is only + * one function and doesn't deserve an header of its own. + * Also, this brings in very common and needed headers + */ +#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include + +#define sprintf pp_sprintf + +#ifndef min +#define min(a, b) \ + ({ __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a < _b ? _a : _b; }) +#endif + +/* Don't use abs from the library */ +#define abs(x) ((x >= 0) ? x : -x) + +#undef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +/* Allow "if" at C language level, to avoid ifdef */ +#ifdef CONFIG_TARGET_WR_SWITCH +# define is_wr_switch 1 +# define is_wr_node 0 +#else +# define is_wr_switch 0 +# define is_wr_node 1 +#endif + +#ifdef CONFIG_WR_NODE_SIM +# define IS_WR_NODE_SIM 1 +#else +# define IS_WR_NODE_SIM 0 +#endif + +#ifdef CONFIG_IP +#define HAS_IP 1 +#else +#define HAS_IP 0 +#endif + +#ifdef CONFIG_ABSCAL +#define HAS_ABSCAL 1 +#else +#define HAS_ABSCAL 0 +#endif + +#ifdef CONFIG_ETHERBONE +#define HAS_EB 1 +#else +#define HAS_EB 0 +#endif + +#ifdef CONFIG_VLAN +#define HAS_VLANS 1 +#else +#define HAS_VLANS 0 +#endif + + +#ifdef CONFIG_CMD_LL +#define HAS_LL 1 +#else +#define HAS_LL 0 +#endif + +int wrc_mon_gui(void); +void redraw_gui(void); +int wrc_log_stats(void); +void shell_init(void); + +/* Default width (in 8ns/16ns units) of the pulses on the PPS output */ +#define PPS_WIDTH (10 * 1000 * 1000 / NS_PER_CLOCK) /* 10ms */ + +/* Init functions and defaults for the wrs build */ +int ad9516_init(int scb_ver, int ljd_present); +int ljd_ad9516_init(void); +void rts_init(void); +int rtipc_init(void); +void rts_update(void); +void rtipc_action(void); + +int wrc_is_timing_up(void); + + +#endif /* __WRC_H__ */ diff --git a/modules/lm32_stub/stubs.c b/modules/lm32_stub/stubs.c index ea07e295c0..f83f746e96 100644 --- a/modules/lm32_stub/stubs.c +++ b/modules/lm32_stub/stubs.c @@ -1,4 +1,4 @@ -void __attribute__((weak)) main(void) { +int __attribute__((weak)) main(void) { } void __attribute__((weak)) _irq_entry(void) { diff --git a/modules/monster/monster.vhd b/modules/monster/monster.vhd index 4df9a0b2e7..5b31b3a8fc 100644 --- a/modules/monster/monster.vhd +++ b/modules/monster/monster.vhd @@ -113,7 +113,6 @@ entity monster is g_a10_en_phy_reconf : boolean; g_en_butis : boolean; g_lm32_cores : natural; - g_lm32_MSIs : natural; g_lm32_ramsizes : natural; g_lm32_init_files : string; g_lm32_profiles : string; @@ -515,8 +514,9 @@ architecture rtl of monster is constant c_use_tlu : boolean := (g_lm32_are_ftm and g_en_tlu) or (not(g_lm32_are_ftm) and g_en_tlu); -- We have to specify the values for WRC as they provide no function for this - constant c_wrcore_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000"); - constant c_wrcore_aux_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0004ffff", x"00040000"); + -- Why is there an additional 0xc00 offset? Check wr_core.vhd and look for this constant: c_secbar_sdb_address : t_wishbone_address := x"00000c00"; + constant c_wrcore_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030c00"); + constant c_wrcore_aux_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0004ffff", x"00040c00"); constant c_ftm_slaves : t_sdb_bridge := f_cluster_bridge(c_dev_bridge_msi, g_lm32_cores, g_lm32_ramsizes, g_lm32_are_ftm, g_delay_diagnostics); constant c_dev_layout_req_slaves : t_sdb_record_array(c_dev_slaves-1 downto 0) := diff --git a/modules/monster/monster_pkg.vhd b/modules/monster/monster_pkg.vhd index 5cbc2e8fcd..e093a10174 100644 --- a/modules/monster/monster_pkg.vhd +++ b/modules/monster/monster_pkg.vhd @@ -94,7 +94,7 @@ package monster_pkg is g_lvds_out : natural := 0; g_fixed : natural := 0; g_lvds_invert : boolean := false; - g_en_tlu : boolean := true; + g_en_tlu : boolean := false; g_en_pcie : boolean := false; g_en_vme : boolean := false; g_en_usb : boolean := false; @@ -119,7 +119,6 @@ package monster_pkg is g_a10_en_phy_reconf : boolean := false; g_en_butis : boolean := true; g_lm32_cores : natural := 1; - g_lm32_MSIs : natural := 1; g_lm32_ramsizes : natural := 131072/4; -- in 32b words g_lm32_init_files : string; -- multiple init files must be seperated by a semicolon ';' g_lm32_profiles : string; -- multiple profiles must be seperated by a semicolon ';' diff --git a/modules/remote_update/.gitignore b/modules/remote_update/.gitignore index da391eff99..e035683ebd 100644 --- a/modules/remote_update/.gitignore +++ b/modules/remote_update/.gitignore @@ -1,4 +1,4 @@ asmi10/ asmi5/ asmi_arriaII/ - +asmi5/asmi5.sopcinfo diff --git a/modules/remote_update/asmi5/asmi5.sopcinfo b/modules/remote_update/asmi5/asmi5.sopcinfo deleted file mode 100644 index f1dbed8ed7..0000000000 --- a/modules/remote_update/asmi5/asmi5.sopcinfo +++ /dev/null @@ -1,1638 +0,0 @@ - - - - - - - java.lang.Integer - 1596715069 - false - true - false - true - GENERATION_ID - - - java.lang.String - - false - true - false - true - UNIQUE_ID - - - java.lang.String - ARRIAV - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 5AGXMA3D4F27I3 - false - true - false - true - DEVICE - - - java.lang.String - 3_H4 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.Long - -1 - false - true - false - true - CLOCK_RATE - clkin - - - java.lang.Integer - -1 - false - true - false - true - CLOCK_DOMAIN - clkin - - - java.lang.Integer - -1 - false - true - false - true - RESET_DOMAIN - clkin - - - java.lang.String - Arria V - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - java.lang.String - ARRIAV - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - ARRIAV - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - ALL - false - true - false - true - - - java.lang.String - EPCQ256 - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - QUAD - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - int - 256 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_UNUSED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_UNUSED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_UNUSED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - java.lang.String - PORT_USED - true - true - false - true - - - int - 0 - false - true - false - true - - - java.lang.String - ON - true - true - false - true - - - java.lang.String - ON - true - true - false - true - - - java.lang.String - FALSE - false - true - false - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clkin - Input - 1 - clk - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - fast_read - Input - 1 - fast_read - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - rden - Input - 1 - rden - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - addr - Input - 32 - addr - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - read_status - Input - 1 - read_status - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - write - Input - 1 - write - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - datain - Input - 8 - datain - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - shift_bytes - Input - 1 - shift_bytes - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - sector_erase - Input - 1 - sector_erase - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - bulk_erase - Input - 1 - bulk_erase - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - wren - Input - 1 - wren - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - read_rdid - Input - 1 - read_rdid - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - en4b_addr - Input - 1 - en4b_addr - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - ex4b_addr - Input - 1 - ex4b_addr - - - - - - java.lang.String - clkin - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - read_dummyclk - Input - 1 - read_dummyclk - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - dataout - Output - 8 - dataout - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - busy - Output - 1 - busy - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - data_valid - Output - 1 - data_valid - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - status_out - Output - 8 - status_out - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - illegal_write - Output - 1 - illegal_write - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - illegal_erase - Output - 1 - illegal_erase - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - read_address - Output - 32 - read_address - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - rdid_out - Output - 8 - rdid_out - - - - - 1 - altera_asmi_parallel - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ASMI Parallel Intel FPGA IP - 18.1 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 22 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - 18.1 625 - - diff --git a/res/rocky-9/README.md b/res/rocky-9/README.md index a5d9fb0921..27f5d02f86 100644 --- a/res/rocky-9/README.md +++ b/res/rocky-9/README.md @@ -12,6 +12,7 @@ A: You need to generate soft links and add paths to your environment variables. ./generate_soft_links.sh export PATH=$PATH:$(pwd) export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$(pwd) +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$(pwd)/../../ip_cores/etherbone-core/api/.libs # make saftlib export PKG_CONFIG_PATH=$PKG_CONFIG_PATH:$(pwd)/../../ip_cores/etherbone-core/api/ # make saftlib export CPATH=$CPATH:$(pwd)/../../ip_cores/etherbone-core/api/ # make saflib diff --git a/syn/build.mk b/syn/build.mk index 7917c7638a..a1eabedc7b 100644 --- a/syn/build.mk +++ b/syn/build.mk @@ -10,21 +10,34 @@ CC = $(CROSS_COMPILE)gcc SHELL = /bin/sh OBJCOPY = $(CROSS_COMPILE)objcopy GENRAMMIF ?= $(TOP)/ip_cores/wrpc-sw/tools/genrammif + INCPATH := $(TOP)/modules/lm32-include EBPATH := $(TOP)/ip_cores/etherbone-core/hdl/eb_master_core W1 := $(TOP)/ip_cores/wrpc-sw +WR_DEV := $(WR_INC)/dev +WR_BOARD := $(W1)/boards/generic/board.h +WR_LIB := $(W1)/lib +WR_INC := $(W1)/include +WR_IMPORT := $(INCPATH)/wrpc-import +WR_HW_IMPORT := $(INCPATH)/wrpc-import/hw +WR_LIB_IMPORT := $(INCPATH)/wrpc-import/lib +WR_DEV_IMPORT := $(INCPATH)/wrpc-import/dev + USRCPUCLK ?= 62500 -CFLAGS += -mmultiply-enabled -mbarrel-shift-enabled -Os -DUSRCPUCLK=$(USRCPUCLK) -I$(INCPATH) -I$(W1)/include \ - -I$(W1)/sdb-lib -I$(W1)/pp_printf -I$(EBPATH) -std=gnu99 -DCONFIG_WR_NODE -DCONFIG_PRINT_BUFSIZE=128 -DCONFIG_PRINTF_64BIT -DSDBFS_BIG_ENDIAN -CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections +CFLAGS += -mmultiply-enabled -mbarrel-shift-enabled -Os \ + -I$(INCPATH) -I$(EBPATH) -I$(WR_IMPORT) -I$(WR_HW_IMPORT) -I$(WR_DEV_IMPORT) \ + -DUSRCPUCLK=$(USRCPUCLK) -DCONFIG_TARGET_GSI_DEVICE -DCONFIG_ARCH_LM32 -DCONFIG_WR_NODE -DCONFIG_PRINT_BUFSIZE=128 \ + -DTICS_PER_SECOND=1000 -DUART_BAUDRATE=115200 -DBASE_CLOCK=100000000 -DSDB_BASED_ADDRESSES -DUSRCPUCLK=125000 \ + -DCONFIG_TARGET_GSI_DEVICE -DSDBFS_BIG_ENDIAN + +CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections -std=gnu99 -pedantic STUBD ?= $(TOP)/modules/lm32_stub STUBS ?= $(STUBD)/stubs.c $(STUBD)/crt0.S -INCLUDES += $(INCPATH)/dbg.c $(INCPATH)/aux.c $(INCPATH)/irq.c $(INCPATH)/mini_sdb.c \ - $(W1)/dev/uart.c $(W1)/lib/usleep.c $(W1)/dev/devicelist.c $(W1)/dev/syscon.c $(W1)/pp_printf/printf.c \ - $(W1)/sdb-lib/glue.c $(W1)/pp_printf/vsprintf-full.c $(W1)/pp_printf/div64.c $(INCPATH)/sdb_add.c \ - $(INCPATH)/assert.c $(INCPATH)/stack-check.c +INCLUDES += $(WR_IMPORT)/uart.c $(WR_IMPORT)/timer.c $(WR_IMPORT)/vsprintf-full.c $(WR_IMPORT)/div64.c $(WR_IMPORT)/printf.c \ + $(INCPATH)/dbg.c $(INCPATH)/aux.c $(INCPATH)/irq.c $(INCPATH)/mini_sdb.c $(INCPATH)/sdb_add.c $(INCPATH)/assert.c \ + $(INCPATH)/stack-check.c $(WR_LIB_IMPORT)/usleep.c $(WR_DEV_IMPORT)/w1-hw.c $(WR_DEV_IMPORT)/w1.c $(WR_DEV_IMPORT)/w1-temp.c LDFLAGS ?= -nostdlib -T ram.ld -lgcc -lc ifndef RAM_SIZE @@ -40,7 +53,6 @@ endif include $(INCPATH)/build_lm32.mk - all: $(TARGET).mif $(TARGET)_stub.mif $(TARGET).sof $(TARGET).jic $(TARGET).rpd $(TARGET)_shared_mmap.h: $(INCPATH)/shared_mmap.h.S diff --git a/syn/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.qsf b/syn/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.qsf index 4bbd75780b..8b4f9c2bca 100644 --- a/syn/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.qsf +++ b/syn/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.qsf @@ -146,7 +146,7 @@ set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS ON set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name SDC_FILE ../../../top/common/arria5.sdc -set_global_assignment -name SEED 65 +set_global_assignment -name SEED 100 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 @@ -237,6 +237,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -295,6 +315,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -312,6 +334,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -319,6 +342,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -327,9 +352,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -342,6 +369,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -351,6 +380,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -380,6 +413,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -392,6 +427,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -432,6 +468,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -442,20 +480,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -533,6 +576,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -540,6 +597,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -550,9 +611,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -562,13 +627,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work diff --git a/syn/gsi_microtca/control/microtca_control.qsf b/syn/gsi_microtca/control/microtca_control.qsf index 8498e41e0e..73ab9ab46e 100644 --- a/syn/gsi_microtca/control/microtca_control.qsf +++ b/syn/gsi_microtca/control/microtca_control.qsf @@ -144,7 +144,7 @@ set_global_assignment -name QSYS_FILE ../../../modules/temp_sens/temp_sens.qsys set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES ON set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name SDC_FILE ../../../top/common/arria5.sdc -set_global_assignment -name SEED 213 +set_global_assignment -name SEED 54 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 @@ -234,6 +234,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -292,6 +312,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -309,6 +331,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -316,6 +339,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -324,9 +349,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -339,6 +366,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -348,6 +377,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -377,6 +410,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -389,6 +424,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -429,6 +465,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -439,20 +477,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -530,6 +573,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -537,6 +594,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -547,9 +608,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -559,13 +624,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work diff --git a/syn/gsi_pexarria10/ftm10/Makefile b/syn/gsi_pexarria10/ftm10/Makefile index 6315c2251a..65eb462a4c 100644 --- a/syn/gsi_pexarria10/ftm10/Makefile +++ b/syn/gsi_pexarria10/ftm10/Makefile @@ -2,7 +2,7 @@ TARGET = ftm10 DEVICE = 10AX066H2F FLASH = EPCQL256 SPI_LANES = ASx4 -RAM_SIZE = 458752 +RAM_SIZE = 393216 SKIP_JIC = yes include ../../build.mk diff --git a/syn/gsi_pexarria10/ftm10/ftm10.qsf b/syn/gsi_pexarria10/ftm10/ftm10.qsf index bd470fa65b..3a48fd0627 100644 --- a/syn/gsi_pexarria10/ftm10/ftm10.qsf +++ b/syn/gsi_pexarria10/ftm10/ftm10.qsf @@ -67,7 +67,7 @@ set_global_assignment -name QSYS_FILE ../../../modules/remote_update/asmi10/asmi set_global_assignment -name QSYS_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset.qsys set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name SDC_FILE ../../../top/common/arria10.sdc -set_global_assignment -name SEED 108 +set_global_assignment -name SEED 118 set_global_assignment -name SMART_RECOMPILE OFF set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 @@ -156,6 +156,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -214,6 +234,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -224,6 +246,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work @@ -231,6 +254,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -238,6 +263,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -246,9 +273,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -261,6 +290,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -270,6 +301,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -299,6 +334,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -311,6 +348,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -351,6 +389,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -361,20 +401,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -452,6 +497,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -459,6 +518,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -469,9 +532,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -481,13 +548,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria10_phy/wr_arria10_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work diff --git a/syn/gsi_pexarria5/control/pci_control.qsf b/syn/gsi_pexarria5/control/pci_control.qsf index 8db6d7a348..afa73328f4 100644 --- a/syn/gsi_pexarria5/control/pci_control.qsf +++ b/syn/gsi_pexarria5/control/pci_control.qsf @@ -138,7 +138,7 @@ set_global_assignment -name QSYS_FILE ../../../modules/remote_update/asmi5/asmi5 set_global_assignment -name QSYS_FILE ../../../modules/temp_sens/temp_sens.qsys set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name SDC_FILE ../../../top/common/arria5.sdc -set_global_assignment -name SEED 171 +set_global_assignment -name SEED 16 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 @@ -227,6 +227,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -285,6 +305,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -295,6 +317,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work @@ -302,6 +325,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -309,6 +334,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -317,9 +344,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -332,6 +361,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -341,6 +372,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -370,6 +405,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -382,6 +419,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -422,6 +460,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -432,20 +472,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -523,6 +568,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -530,6 +589,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -540,9 +603,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -552,13 +619,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work diff --git a/syn/gsi_pexarria5/ftm/ftm.qsf b/syn/gsi_pexarria5/ftm/ftm.qsf index a3677ceabd..ea885a01e6 100644 --- a/syn/gsi_pexarria5/ftm/ftm.qsf +++ b/syn/gsi_pexarria5/ftm/ftm.qsf @@ -137,7 +137,7 @@ set_global_assignment -name QSYS_FILE ../../../modules/temp_sens/temp_sens.qsys set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name SDC_FILE ../../../top/common/arria5.sdc -set_global_assignment -name SEED 83 +set_global_assignment -name SEED 119 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 @@ -227,6 +227,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -285,6 +305,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -295,6 +317,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work @@ -302,6 +325,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -309,6 +334,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -317,9 +344,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -332,6 +361,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -341,6 +372,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -370,6 +405,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -382,6 +419,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -422,6 +460,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -432,20 +472,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -523,6 +568,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -530,6 +589,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -540,9 +603,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -552,13 +619,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work diff --git a/syn/gsi_pexp/control/pexp_control.qsf b/syn/gsi_pexp/control/pexp_control.qsf index d9814762b3..ca80043c5f 100644 --- a/syn/gsi_pexp/control/pexp_control.qsf +++ b/syn/gsi_pexp/control/pexp_control.qsf @@ -140,7 +140,7 @@ set_global_assignment -name QIP_FILE ../../../modules/pll/arria5/sys_pll5.qip set_global_assignment -name QSYS_FILE ../../../modules/temp_sens/temp_sens.qsys set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES ON set_global_assignment -name SDC_FILE ../../../top/common/arria5.sdc -set_global_assignment -name SEED 191 +set_global_assignment -name SEED 222 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 @@ -229,6 +229,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -287,6 +307,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -304,6 +326,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -311,6 +334,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -319,9 +344,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -334,6 +361,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -343,6 +372,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -372,6 +405,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -384,6 +419,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -424,6 +460,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -434,20 +472,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -525,6 +568,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -532,6 +589,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -542,9 +603,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -554,13 +619,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work diff --git a/syn/gsi_pmc/control/pci_pmc.qsf b/syn/gsi_pmc/control/pci_pmc.qsf index 4a636c38b0..cf40df4921 100644 --- a/syn/gsi_pmc/control/pci_pmc.qsf +++ b/syn/gsi_pmc/control/pci_pmc.qsf @@ -140,7 +140,7 @@ set_global_assignment -name QIP_FILE ../../../modules/pll/arria5/sys_pll5.qip set_global_assignment -name QSYS_FILE ../../../modules/temp_sens/temp_sens.qsys set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES ON set_global_assignment -name SDC_FILE ../../../top/common/arria5.sdc -set_global_assignment -name SEED 138 +set_global_assignment -name SEED 6 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 @@ -229,6 +229,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -287,6 +307,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -304,6 +326,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -311,6 +334,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -319,9 +344,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -334,6 +361,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -343,6 +372,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -372,6 +405,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -384,6 +419,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -424,6 +460,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -434,20 +472,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -525,6 +568,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -532,6 +589,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -542,9 +603,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -554,13 +619,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work diff --git a/syn/gsi_scu/control2/Makefile b/syn/gsi_scu/control2/Makefile index a8d8fc43a0..48b861fe4c 100644 --- a/syn/gsi_scu/control2/Makefile +++ b/syn/gsi_scu/control2/Makefile @@ -12,11 +12,8 @@ include ../../build.mk CFLAGS += -O2 $(TARGET).elf: $(PATHSCU)/main.c $(INCPATH)/display.c $(PATHSCU)/cb.c \ - $(PATHSCU)/scu_bus.c $(PATHSCU)/scu_mil.c $(PATHSCU)/fg.c \ - $(PATHSCU)/dow_crc.c $(PATHSCU)/history.c \ - $(W1)/dev/w1.c $(W1)/dev/w1-temp.c $(W1)/dev/w1-hw.c + $(PATHSCU)/scu_bus.c $(PATHSCU)/scu_mil.c $(PATHSCU)/fg.c \ + $(PATHSCU)/dow_crc.c $(PATHSCU)/history.c \ clean:: rm -f $(PATHSCU)/main.o $(W1)/dev/*.o - - diff --git a/syn/gsi_scu/control2/scu_control.qsf b/syn/gsi_scu/control2/scu_control.qsf index a6807bcede..4f5d9b9e55 100644 --- a/syn/gsi_scu/control2/scu_control.qsf +++ b/syn/gsi_scu/control2/scu_control.qsf @@ -98,7 +98,7 @@ set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/sys_pll.qip set_global_assignment -name QSYS_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII.qsys set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name SDC_FILE ../../../top/gsi_scu/control2/scu_control.sdc -set_global_assignment -name SEED 120 +set_global_assignment -name SEED 117 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128 @@ -127,6 +127,57 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/module set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pclk_align.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pclk_pll.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_phasefifo.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_100_250.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_125_250.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_phy0.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_phy2.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_trans.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp_dcram.v" +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v" set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work @@ -186,6 +237,26 @@ set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/ver set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work @@ -243,6 +314,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -253,6 +326,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work @@ -260,6 +334,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -267,6 +343,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -275,9 +353,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -290,6 +370,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -299,6 +381,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -328,6 +414,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -340,6 +428,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -380,6 +469,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -390,20 +481,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -481,6 +577,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -488,6 +598,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -498,9 +612,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -510,13 +628,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work @@ -532,6 +652,9 @@ set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/led_n.vhd - set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/lemo_io.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_125_to_12p5.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_20_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/slave_clk_switch.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/tmr_scu_bus.vhd -library work @@ -583,6 +706,8 @@ set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_qu set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/ring_buffer.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg.vhd -library work diff --git a/syn/gsi_scu/control3/Makefile b/syn/gsi_scu/control3/Makefile index c15d0cb0ab..31837a6fa0 100644 --- a/syn/gsi_scu/control3/Makefile +++ b/syn/gsi_scu/control3/Makefile @@ -14,11 +14,8 @@ CFLAGS += -O2 doc: doxygen Doxyfile $(TARGET).elf: $(PATHSCU)/main.c $(INCPATH)/display.c $(PATHSCU)/cb.c \ - $(PATHSCU)/scu_bus.c $(PATHSCU)/scu_mil.c $(PATHSCU)/fg.c \ - $(PATHSCU)/dow_crc.c $(PATHSCU)/history.c \ - $(W1)/dev/w1.c $(W1)/dev/w1-temp.c $(W1)/dev/w1-hw.c + $(PATHSCU)/scu_bus.c $(PATHSCU)/scu_mil.c $(PATHSCU)/fg.c \ + $(PATHSCU)/dow_crc.c $(PATHSCU)/history.c clean:: rm -f $(PATHSCU)/main.o $(W1)/dev/*.o - - diff --git a/syn/gsi_scu/control3/scu_control.qsf b/syn/gsi_scu/control3/scu_control.qsf index 811677ea4b..95fe788eda 100644 --- a/syn/gsi_scu/control3/scu_control.qsf +++ b/syn/gsi_scu/control3/scu_control.qsf @@ -1,4 +1,4 @@ -set_global_assignment -name AHDL_FILE ../../../modules/modulbus/i2c.tdf + set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF set_global_assignment -name AUTO_MERGE_PLLS OFF set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF @@ -79,25 +79,8 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH 100 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:scu_control.tcl" set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:00:25 FEBRUARY 13, 2012" -set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx/dual_region.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx/global_region.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx_networks.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx/single_region.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie_hip.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie_reconf.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/arria2_phy.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/arria2_phy_reconf.qip" -set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.qip" -set_global_assignment -name QIP_FILE ../../../modules/ddr3/arria2/arria2_ddr3.qip -set_global_assignment -name QIP_FILE ../../../modules/ddr3/arria2/scu_ddr3.qip -set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/arria2_pll.qip -set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/dmtd_pll.qip -set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/ref_pll.qip -set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/sys_pll.qip -set_global_assignment -name QSYS_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII.qsys set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SDC_FILE ../../../top/gsi_scu/control3/scu_control.sdc +set_global_assignment -name SEED 22 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128 @@ -108,630 +91,7 @@ set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL ON set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON -set_global_assignment -name TOP_LEVEL_ENTITY scu_control set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work -set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work -set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work -set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work -set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work -set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v -library work -set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work -set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work -set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work -set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Access_Decode.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer_pack.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_pack.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" 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-library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" 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VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work -set_global_assignment -name VHDL_FILE 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"../../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/ad7606.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_modul_bus.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_scu_bus.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/aux_functions_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Debounce.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/div_n.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/IO_4x8.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/led_n.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/lemo_io.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_125_to_12p5.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_20_to_12p5.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/slave_clk_switch.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/tmr_scu_bus.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Zeitbasis.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/BuTis_T0_generator.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/crc8_data8.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampDecoder.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampEncoder.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/cfi_flash_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/xwb_cfi_wrapper.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Bus_io.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Debounce_Skal.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Independent_Clk.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/chopper/K12_K23_Logik_Leds.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kanal.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kicker_Leds.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/daq/crc5x16.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_chan_reg_logic.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/daq/daq.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/daq/Zeitbasis_daq.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/diob/hw_interlock.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/diob/quench_detection.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/diob/spill_abort.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/flash_loader/flash_loader_v01.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32_cluster.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ftm/time_clk_cross.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pathfinder.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_top.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_writer.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/heap/xwb_heap.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/led_blink.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/i8042_kbc.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_peripheral.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/postcode.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_ibuf.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_obuf.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_rx.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_tx.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria10_lvds_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_ibuf.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_obuf.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_rx.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_tx.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2_lvds_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5_lvds_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/lvds/eca_lvds_channel.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/hw6408_vhdl.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_bipol_dec.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_dec_edge_timed.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_Enc_Vhdl.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_en_decoder.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_hw_or_soft_ip.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/PLL_SIO.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/PU_Reset.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/mil/SysClock.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Epcs_spi.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/f_divider.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/global_reg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/I2C_Cntrl.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/K_EPCS_IF.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/led.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Loader_MB.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modul2spi.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_loader.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_v5.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Rd_mb_ld.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/rdram.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_iodir.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/monster/monster.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/char_render.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/display_console.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/Display_RAM_Ini_v01.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_display_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/spi_master.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/wb_console.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_butis.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_phase.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_reset.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/pll/pll_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/power_test/pwm.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/power_test/row_array.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/power_test/row.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/arbiter.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min3.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min9_64.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/queue_unit.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/psram/psram_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/psram/psram.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_asmi.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_remote_update.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/reverse_lpb/reverse_lpb.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/housekeeping.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_to_wb.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_irq_scu_bus.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_scu_bus.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/temp_sens/hdl/wb_temp_sense_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_loop.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_rcfg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/trans_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/trans_pll/trans_pll.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_clock_div.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_counter.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_edge_detect.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_fifo.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_filter.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_sync.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_mv_filter.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_16750.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_baudgen.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_interrupt.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_receiver.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria5_reset.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria_reset.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/event_processing.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/mil_pll.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer.vhd -library work -set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/control3/ramsize_pkg.vhd -library work -set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/control3/scu_control.vhd -library work set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R 100 -to DDR3_CLK @@ -1569,3 +929,710 @@ set_location_assignment PIN_Y9 -to EIO[1] set_location_assignment PLL_2 -to "monster:main|sys_pll:\\sys_a2:sys_inst|altpll:altpll_component|sys_pll_altpll:auto_generated|pll1" set_location_assignment PLL_3 -to "monster:main|dmtd_pll:\\dmtd_a2:dmtd_inst|altpll:altpll_component|dmtd_pll_altpll:auto_generated|pll1" set_location_assignment PLL_4 -to "monster:main|ref_pll:\\ref_a2:ref_inst|altpll:altpll_component|ref_pll_altpll:auto_generated|pll1" + +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Bus_io.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_asmi_slave.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/ad7606.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/global_reg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_remote_update.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/IO_4x8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/temp_sens/hdl/wb_temp_sense_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/i8042_kbc.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/f_divider.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/led_blink.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_clock_div.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/lemo_io.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/altasmi.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_modul_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/housekeeping.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/led_n.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_dec_edge_timed.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_tx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/PU_Reset.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/xwb_heap.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/eca_lvds_channel.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Loader_MB.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_tx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/BuTis_T0_generator.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria5_reset.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_hw_or_soft_ip.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/psram/psram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_to_wb.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_top.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/reverse_lpb/reverse_lpb.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/event_processing.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampEncoder.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/ring_buffer.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/hw_interlock.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/row_array.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Rd_mb_ld.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/flash_loader/flash_loader_v01.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampDecoder.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/tmr_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_phase.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/rdram.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/mil_pll.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/PLL_SIO.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_125_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/control3/ramsize_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_butis.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_writer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/aux_functions_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Epcs_spi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/spi_master.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_loader.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_en_decoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_irq_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_ibuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/quench_detection.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/cfi_flash_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_display_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_16750.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_rx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/slave_clk_switch.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_edge_detect.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria10_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/display_console.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/time_clk_cross.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_ibuf.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/wb_console.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/char_render.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_receiver.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/pwm.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_obuf.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Debounce.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/led.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_chan_reg_logic.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_loop.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/psram/psram_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/xwb_cfi_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Zeitbasis.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32_cluster.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_remapper/xwb_remapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/K_EPCS_IF.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_obuf.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_baudgen.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modul2spi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_Enc_Vhdl.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/spill_abort.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/row.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/SysClock.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/hw6408_vhdl.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_20_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_filter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/arbiter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Debounce_Skal.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/I2C_Cntrl.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/Zeitbasis_daq.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/crc8_data8.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_interrupt.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/trans_pll/trans_pll.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/crc5x16.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pathfinder.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/trans_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_v5.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_sync.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/Display_RAM_Ini_v01.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min9_64.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/postcode.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/K12_K23_Logik_Leds.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_rx.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_fifo.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_peripheral.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_reset.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/pll_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Independent_Clk.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kanal.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_asmi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_rcfg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Access_Decode.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/queue_unit.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_mv_filter.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_iodir.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/div_n.vhd -library work +set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/control3/scu_control.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kicker_Leds.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_pkg.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min3.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_bipol_dec.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_counter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work +set_global_assignment -name SDC_FILE ../../../top/gsi_scu/control3/scu_control.sdc +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie.qip" +set_global_assignment -name QIP_FILE ../../../modules/ddr3/arria2/arria2_ddr3.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/arria2_pll.qip +set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx_networks.qip" +set_global_assignment -name AHDL_FILE ../../../modules/modulbus/i2c.tdf +set_global_assignment -name TOP_LEVEL_ENTITY scu_control \ No newline at end of file diff --git a/syn/gsi_scu/ftm4dp/ftm4dp.qsf b/syn/gsi_scu/ftm4dp/ftm4dp.qsf index e5aabb95b4..fb874c37cd 100644 --- a/syn/gsi_scu/ftm4dp/ftm4dp.qsf +++ b/syn/gsi_scu/ftm4dp/ftm4dp.qsf @@ -72,7 +72,7 @@ set_global_assignment -name QSYS_FILE ../../../modules/remote_update/asmi10/asmi set_global_assignment -name QSYS_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset.qsys set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name SDC_FILE ../../../top/common/arria10.sdc -set_global_assignment -name SEED 0 +set_global_assignment -name SEED 13 set_global_assignment -name SMART_RECOMPILE OFF set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQ256 diff --git a/syn/gsi_vetar2a/ee_butis/vetar2a.qsf b/syn/gsi_vetar2a/ee_butis/vetar2a.qsf index 171fac0f29..c057767024 100644 --- a/syn/gsi_vetar2a/ee_butis/vetar2a.qsf +++ b/syn/gsi_vetar2a/ee_butis/vetar2a.qsf @@ -52,96 +52,120 @@ set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/dmtd_pll.qip set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/ref_pll.qip set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/sys_pll.qip set_global_assignment -name SDC_FILE ../../../top/gsi_vetar2a/ee_butis/vetar2a_ee_butis.sdc -set_global_assignment -name SEED 113 +set_global_assignment -name SEED 25 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128 set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL" set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work -set_global_assignment -name SYSTEMVERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work -set_global_assignment -name SYSTEMVERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work -set_global_assignment -name SYSTEMVERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work -set_global_assignment -name SYSTEMVERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v -library work set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name TOP_LEVEL_ENTITY vetar2a_ee_butis set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work @@ -191,6 +215,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legac set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work @@ -208,6 +234,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work @@ -215,6 +242,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work @@ -223,9 +252,11 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/c set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work @@ -238,6 +269,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work @@ -247,6 +280,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/g set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work @@ -276,6 +313,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work @@ -288,6 +327,7 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work @@ -328,6 +368,8 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/ set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work @@ -338,20 +380,25 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work @@ -429,6 +476,20 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_min set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work @@ -436,6 +497,10 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si5 set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work @@ -446,9 +511,13 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sof set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work @@ -458,13 +527,15 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_str set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work @@ -480,6 +551,9 @@ set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/led_n.vhd - set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/lemo_io.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_125_to_12p5.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_20_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/slave_clk_switch.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/tmr_scu_bus.vhd -library work @@ -518,6 +592,10 @@ set_global_assignment -name VHDL_FILE ../../../modules/diob/spill_abort.vhd -lib set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/flash_loader/flash_loader_v01.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32_cluster.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32.vhd -library work @@ -527,6 +605,8 @@ set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_qu set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/ring_buffer.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg.vhd -library work @@ -540,6 +620,7 @@ set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pkg.vhd -librar set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_top.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_writer.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/heap/xwb_heap.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/led_blink.vhd -library work @@ -617,7 +698,10 @@ set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio.vhd -library set_global_assignment -name VHDL_FILE ../../../modules/prioq2/queue_unit.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/psram/psram_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/psram/psram.vhd -library work -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/altasmi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_asmi.vhd -library work @@ -627,6 +711,7 @@ set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/housekeeping.vhd set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_to_wb.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_irq_scu_bus.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_scu_bus.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work @@ -656,6 +741,8 @@ set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_receiver.vhd -l set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria5_reset.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria_reset.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work @@ -666,6 +753,8 @@ set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu_pkg set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer.vhd -library work set_global_assignment -name VHDL_FILE ../../../top/gsi_vetar2a/ee_butis/ramsize_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../../top/gsi_vetar2a/ee_butis/vetar2a_ee_butis.vhd -library work set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 diff --git a/syn/gsi_vetar2a/wr_core_demo/vetar2a.qsf b/syn/gsi_vetar2a/wr_core_demo/vetar2a.qsf index d7aea3b67e..4b3304a126 100644 --- a/syn/gsi_vetar2a/wr_core_demo/vetar2a.qsf +++ b/syn/gsi_vetar2a/wr_core_demo/vetar2a.qsf @@ -1,8 +1,8 @@ -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_20MHZ +set_global_assignment -name AHDL_FILE ../../../modules/modulbus/i2c.tdf set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name DEVICE EP2AGX125EF29C5 +set_global_assignment -name DEVICE ep2agx125ef29c5 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name ECO_OPTIMIZE_TIMING ON set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" @@ -17,7 +17,7 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 set_global_assignment -name FAMILY "Arria II GX" set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" set_global_assignment -name LL_AUTO_SIZE OFF -section_id flash set_global_assignment -name LL_AUTO_SIZE OFF -section_id "wr_arria2:tx" set_global_assignment -name LL_CORE_ONLY OFF -section_id flash @@ -64,12 +64,22 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:vetar2a_top.tcl" set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:00:25 FEBRUARY 13, 2012" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx/dual_region.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx/global_region.qip" set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx_networks.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/networks/arria2gx/single_region.qip" set_global_assignment -name QIP_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/arria2_pcie.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/arria2_phy.qip" +set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/arria2_phy_reconf.qip" set_global_assignment -name QIP_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.qip" -set_global_assignment -name QIP_FILE ../../../modules/nau8811/src/hdl/altera_pll/audio_pll_ref.qip +set_global_assignment -name QIP_FILE ../../../modules/ddr3/arria2/arria2_ddr3.qip set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/arria2_pll.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/dmtd_pll.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/ref_pll.qip +set_global_assignment -name QIP_FILE ../../../modules/pll/arria2/sys_pll.qip +set_global_assignment -name QSYS_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII.qsys set_global_assignment -name SDC_FILE ../../../top/gsi_vetar2a/wr_core_demo/vetar2a_top.sdc +set_global_assignment -name SEED 206 set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128 @@ -80,496 +90,700 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name TOP_LEVEL_ENTITY vetar2a_top set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Access_Decode.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer_pack.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_pack.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" 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"../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/gc_escape_detector.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/gc_escape_inserter.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/altera_pkg.vhd" -set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/ad7606.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_modul_bus.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_scu_bus.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/aux_functions_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Debounce.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/div_n.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/IO_4x8.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/led_n.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/lemo_io.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_125_to_12p5.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_20_to_12p5.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/slave_clk_switch.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/sys_clk_or_local_clk.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/tmr_scu_bus.vhd -set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Zeitbasis.vhd -set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id.vhd -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/BuTis_T0_generator.vhd -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/crc8_data8.vhd -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampDecoder.vhd -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampEncoder.vhd -set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/cfi_flash_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/xwb_cfi_wrapper.vhd -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Bus_io.vhd -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Debounce_Skal.vhd -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Independent_Clk.vhd -set_global_assignment -name VHDL_FILE ../../../modules/chopper/K12_K23_Logik_Leds.vhd -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kanal.vhd -set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kicker_Leds.vhd -set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714.vhd -set_global_assignment -name VHDL_FILE ../../../modules/flash_loader/flash_loader_v01.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32_cluster.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ftm/time_clk_cross.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wb_fg_quad.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wbmstr_core.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pathfinder.vhd -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_top.vhd -set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_writer.vhd -set_global_assignment -name VHDL_FILE ../../../modules/heap/xwb_heap.vhd -set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control.vhd -set_global_assignment -name VHDL_FILE ../../../modules/led_blink.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/i8042_kbc.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_peripheral.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/postcode.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_ibuf.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_obuf.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_rx.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_tx.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_ibuf.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_obuf.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_rx.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_tx.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2_lvds_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5_lvds_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/lvds/eca_lvds_channel.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/hw6408_vhdl.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_bipol_dec.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_dec_edge_timed.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_Enc_Vhdl.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_en_decoder.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_hw_or_soft_ip.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/PLL_SIO.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/PU_Reset.vhd -set_global_assignment -name VHDL_FILE ../../../modules/mil/SysClock.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Epcs_spi.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/f_divider.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/global_reg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/I2C_Cntrl.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/K_EPCS_IF.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/led.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Loader_MB.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modul2spi.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_loader.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_v5.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Rd_mb_ld.vhd -set_global_assignment -name VHDL_FILE ../../../modules/modulbus/rdram.vhd -set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_iodir.vhd -set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/monster/monster.vhd -set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/generic_iis_master_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/generic_iis_master.vhd -set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/wb_nau8811_audio_driver.vhd -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/char_render.vhd -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/display_console.vhd -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/Display_RAM_Ini_v01.vhd -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_display_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/spi_master.vhd -set_global_assignment -name VHDL_FILE ../../../modules/oled_display/wb_console.vhd -set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_butis.vhd -set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_phase.vhd -set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_reset.vhd -set_global_assignment -name VHDL_FILE ../../../modules/pll/pll_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test.vhd -set_global_assignment -name VHDL_FILE ../../../modules/power_test/pwm.vhd -set_global_assignment -name VHDL_FILE ../../../modules/power_test/row_array.vhd -set_global_assignment -name VHDL_FILE ../../../modules/power_test/row.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/arbiter.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min3.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min9_64.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio.vhd -set_global_assignment -name VHDL_FILE ../../../modules/prioq2/queue_unit.vhd -set_global_assignment -name VHDL_FILE ../../../modules/psram/psram_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/psram/psram.vhd -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/altasmi.vhd -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update.vhd -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_asmi.vhd -set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_remote_update.vhd -set_global_assignment -name VHDL_FILE ../../../modules/reverse_lpb/reverse_lpb.vhd -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/housekeeping.vhd -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave.vhd -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_irq_scu_bus.vhd -set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_scu_bus.vhd -set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_loop.vhd -set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_rcfg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/trans_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/trans_pll/trans_pll.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_clock_div.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_counter.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_edge_detect.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_fifo.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_filter.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_sync.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_mv_filter.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_16750.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_baudgen.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_interrupt.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_receiver.vhd -set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd -set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria5_reset.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria_reset.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/event_processing.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/mil_pll.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg.vhd -set_global_assignment -name VHDL_FILE ../../../top/gsi_vetar2a/wr_core_demo/ramsize_pkg.vhd -set_global_assignment -name VHDL_FILE ../../../top/gsi_vetar2a/wr_core_demo/vetar2a_top.vhd +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/bus_commands.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_async_reset_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_bridge32.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cbe_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_cyc_addr_dec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_conf_space.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_cur_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_sync.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_delayed_write_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_frame_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_in_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_io_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_irdy_out_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ad_load_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_mas_ch_state_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm_if.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_master32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_out_reg.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_par_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_parity_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pcir_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pci_tpram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_pciw_pcir_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_perr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_ram_16x40d.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_rst_int.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_serr_en_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_spoci_ctrl.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_synchronizer_flop.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_sync_module.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_clk_en.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_devs_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_interface.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_sm.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_stop_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target32_trdy_crit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_target_unit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_user_constants.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_addr_mux.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_decoder.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_master.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbr_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave_unit.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_slave.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wb_tpram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_fifo_control.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/pci_wbw_wbr_fifos.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/pci-core/src/hdl/verilog/timescale.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_cpu.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_csr.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_decode.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_divide.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_ecc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_exec.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_fetch.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_iram.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_multiply.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_regfile.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_shifter.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_timer.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_writeback.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_crc.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_descramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr_scramble.v" -library work +set_global_assignment -name VERILOG_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/prbs/lfsr.v" -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl_engine.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/cfi_flash/cfi_ctrl.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_gdoqleq.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_altera_asmi_parallel_181_svbigkq.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/submodules/asmi5_asmi_parallel_0.v -library work +set_global_assignment -name VERILOG_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/submodules/asmi_arriaII_asmi_parallel_0.v -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/ebm_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Access_Decode.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Am_Match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_bus.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CRAM.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_CSR_Space.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CR_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_CSR_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Funct_Match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Init.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_IRQ_Controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_SharedComps.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_swapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_master_eb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/VME_Wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xVME64xCore_Top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/fpga-config-space/legacy-vme64x-core/hdl/xvme64x_pack.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/axi4_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_comparator.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_negedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_posedge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/cheby/cheby_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/secded_32b_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/radtol/voter_vec_status.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb16_to_wb32/wb16_to_wb32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/wb_indirect_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_indirect/xwb_indirect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad2.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/wb_skidpad.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register_link.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_register/xwb_register.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_remapper/xwb_remapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pci_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/pci-core/src/hdl/wb_pmc_host_bridge.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/urv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/ip_cores/urv-core/rtl/xurv_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_dpram.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/cute_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_bw_throttling.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_constants_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptor_manager.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_descriptors_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_elastic_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_rx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_tx_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/nic_wishbone_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/wr_nic_wrapper.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_nic/xwr_nic.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/wr_txtsu_wb.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/modules/wr_txtsu/xwr_txtsu.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_altera_pkg.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd" -library work +set_global_assignment -name VHDL_FILE "../../../ip_cores/wr-cores/platform/altera/xwrc_platform_altera.vhd" -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/ad7606.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_modul_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ad7606/adc_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/aux_functions_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Debounce.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/div_n.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/IO_4x8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/led_n.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/lemo_io.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_125_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/local_20_to_12p5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_16_4.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_256_8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/prio_encoder/prio_encoder_64_6.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/slave_clk_switch.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/sys_clk_or_local_clk.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/tmr_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/aux_functions/Zeitbasis.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/beam_dump/beam_dump.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/build_id/build_id.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/BuTis_T0_generator.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/crc8_data8.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampDecoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/TimestampEncoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/butis_t0/wr_serialtimestamp_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/cfi_flash_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cfi_flash/xwb_cfi_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Bus_io.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Debounce_Skal.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Independent_Clk.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/K12_K23_Logik_Leds.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kanal.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/chopper/Kicker_Leds.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/cpri_phy_reconf/cpri_phy_reconf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dac714/dac714.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/crc5x16.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_chan_reg_logic.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/daq.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/daq/Zeitbasis_daq.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ddr3/ddr3_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/hw_interlock.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/quench_detection.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/diob/spill_abort.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/dm_diag/dm_diag.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/eca_tap/eca_tap.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/flash_loader/flash_loader_v01.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32_cluster.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_lm32.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/ftm_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ftm/time_clk_cross.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_datapath.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_ifa.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/fg_quad_statistics.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/ring_buffer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/fg_quad/wbmstr_core.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/scu_slave_fg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen_regs.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/wb_serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/function_generators/serdes_clk_gen/xwb_serdes_clk_gen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pathfinder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_top.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/heap_writer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/heap/xwb_heap.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/i2c_wrapper/src/hdl/wb_i2c_wrapper_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/io_control/src/hdl/io_control.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/led_blink.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/i8042_kbc.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_peripheral.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/postcode.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_ibuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_obuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_rx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds_tx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/altera_lvds.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria10_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_ibuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_obuf.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_rx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2/arria2_lvds_tx.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria2_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/arria5_lvds_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/lvds/eca_lvds_channel.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mbox/mbox.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/hw6408_vhdl.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_bipol_dec.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_dec_edge_timed.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_Enc_Vhdl.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_en_decoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/mil_hw_or_soft_ip.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/Mil_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/PLL_SIO.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/PU_Reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/mil/SysClock.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Epcs_spi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/f_divider.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/global_reg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/I2C_Cntrl.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/K_EPCS_IF.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/led.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Loader_MB.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modul2spi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_loader.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/modulbus_v5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/Rd_mb_ld.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/modulbus/rdram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_iodir.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/monster/monster.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/nau8811/src/hdl/wb_nau8811_audio_driver_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/char_render.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/display_console.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/Display_RAM_Ini_v01.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/oled_display_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/spi_master.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/oled_display/wb_console.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_butis.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_phase.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/altera_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/pll/pll_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/power_test.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/pwm.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/row_array.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/power_test/row.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/arbiter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min3.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/min9_64.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_auto.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/prio.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/prioq2/queue_unit.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/psram/psram_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/psram/psram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/altera_asmi_parallel_181/synth/asmi10_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi10/asmi10/synth/asmi10.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi5/asmi5/synthesis/asmi5.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/asmi_arriaII/asmi_arriaII/synthesis/asmi_arriaII.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/remote_update.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_asmi.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/remote_update/wb_remote_update.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/reverse_lpb/reverse_lpb.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/housekeeping.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_bus_slave.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/scu_to_wb.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_irq_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/scu_bus/wb_scu_bus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/simple_tag_decoder/simple_tag_decoder.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_fifo.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/generic_serial_master.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/ssd1325/src/hdl/wb_ssd1325_serial_driver.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/temp_sens/hdl/wb_temp_sense_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_loop.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/transceiver_prbs/trans_rcfg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/trans_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/trans_pll/trans_pll.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_clock_div.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_counter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_edge_detect.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_fifo.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_filter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_input_sync.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/slib_mv_filter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_16750.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_baudgen.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_interrupt.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_receiver.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/watchdog/watchdog.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/altera_remote_update_181/synth/arria10_reset_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria10_reset/arria10_reset/synth/arria10_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria5_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/arria_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_arria_reset/wb_arria_reset.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/event_processing.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/mil_pll.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_mil_scu/wb_mil_scu.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_scu_reg/wb_scu_reg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../modules/wb_timer/wb_timer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../top/gsi_vetar2a/wr_core_demo/ramsize_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../top/gsi_vetar2a/wr_core_demo/vetar2a_top.vhd -library work set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF set_instance_assignment -name FAST_INPUT_REGISTER ON -to emptyn_i diff --git a/tools/1w/eb-w1-write.c b/tools/1w/eb-w1-write.c new file mode 100644 index 0000000000..159593733f --- /dev/null +++ b/tools/1w/eb-w1-write.c @@ -0,0 +1,153 @@ +/* + * This work is part of the White Rabbit project + * + * Copyright (C) 2013 CERN (www.cern.ch) + * Author: Wesley W. Terpstra + * Author: Alessandro Rubini + * Author: Tomasz Wlostowski + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define W1_VENDOR 0xce42 /* CERN */ +#define W1_DEVICE 0x779c5443 /* WR-Periph-1Wire */ + +char *prgname; +int verbose; + +eb_address_t BASE_ONEWIRE; +eb_device_t device; +extern struct w1_bus wrpc_w1_bus; + + +static int write_w1(int w1base, int w1len) +{ + struct w1_dev *d; + uint8_t buf[w1len]; + int i; + + wrpc_w1_init(); + w1_scan_bus(&wrpc_w1_bus); + + if (verbose) { /* code borrowed from dev/w1.c -- "w1" shell command */ + for (i = 0; i < W1_MAX_DEVICES; i++) { + d = wrpc_w1_bus.devs + i; + if (d->rom) + fprintf(stderr, "device %i: %08x%08x\n", i, + (int)(d->rom >> 32), (int)d->rom); + } + } + + if (verbose) { + fprintf(stderr, "Writing device offset %i (0x%x), len %i\n", + w1base, w1base, w1len); + } + + if (isatty(fileno(stdin))) + fprintf(stderr, "Reading from stdin, please type the data\n"); + i = fread(buf, 1, w1len, stdin); + if (i != w1len) { + fprintf(stderr, "%s: read error (%i, expeted %i)\n", prgname, + i, w1len); + return 1; + } + i = w1_write_eeprom_bus(&wrpc_w1_bus, w1base, buf, w1len); + if (i != w1len) { + fprintf(stderr, "Tried to write %i bytes, retval %i\n", + w1len, i); + return 1; + } + return 0; +} + +/* + * What follows is mostly generic, should be librarized in a way + */ + + +static int help(void) +{ + fprintf(stderr, "%s: Use: \"%s [-v] [-i ] \n", + prgname, prgname); + return 1; +} + +static void die(const char *reason, eb_status_t status) +{ + fprintf(stderr, "%s: %s: %s\n", prgname, reason, eb_status(status)); + exit(1); +} + +int main(int argc, char **argv) +{ + int c, i; + eb_status_t status; + eb_socket_t socket; + struct sdb_device sdb[10];; + char *tail; + + prgname = argv[0]; + i = -1; + + while ((c = getopt(argc, argv, "i:v")) != -1) { + switch(c) { + case 'i': + i = strtol(optarg, &tail, 0); + if (*tail != 0) { + fprintf(stderr, "Specify a proper number, not '%s'!\n", optarg); + exit(1); + } + break; + case 'v': + verbose++; + break; + default: + exit(help()); + } + } + if (optind != argc - 3) + exit(help()); + + if ((status = eb_socket_open(EB_ABI_CODE, 0, EB_DATAX|EB_ADDRX, &socket)) != EB_OK) + die("eb_socket_open", status); + + if ((status = eb_device_open(socket, argv[optind], EB_DATAX|EB_ADDRX, 3, &device)) != EB_OK) + die(argv[optind], status); + + /* Find the W1 device */ + c = sizeof(sdb) / sizeof(struct sdb_device); + if ((status = eb_sdb_find_by_identity(device, W1_VENDOR, W1_DEVICE, &sdb[0], &c)) != EB_OK) + die("eb_sdb_find_by_identity", status); + + if (i == -1) { + if (c > 1) { + fprintf(stderr, "Found %d 1wire controllers on that device; pick one with -i #\n", c); + exit(1); + } else { + i = 0; + } + } + if (i >= c) { + fprintf(stderr, "Could not find 1wire controller #%d on that device (%d total)\n", i, c); + exit(1); + } + + BASE_ONEWIRE = sdb[i].sdb_component.addr_first; + + return write_w1(atoi(argv[optind + 1]), atoi(argv[optind + 2])); +} diff --git a/tools/1w/eb-w1.c b/tools/1w/eb-w1.c new file mode 100644 index 0000000000..298800742d --- /dev/null +++ b/tools/1w/eb-w1.c @@ -0,0 +1,86 @@ +/* + * This work is part of the White Rabbit project + * + * Copyright (C) 2013 CERN (www.cern.ch) + * Author: Wesley W. Terpstra + * Alessandro Rubini + * + * Released according to the GNU GPL, version 2 or any later version. + */ +#include +#include +#include +#include + +extern eb_address_t BASE_ONEWIRE; +extern eb_device_t device; + +static inline uint32_t __wait_cycle(eb_device_t device) +{ + eb_data_t data; + + do { + eb_device_read(device, BASE_ONEWIRE, EB_DATA32|EB_BIG_ENDIAN, &data, 0, 0); + } while (data & SOCKIT_OWM_CTL_CYC_MSK); + + return data; +} + +static int w1_reset(struct w1_bus *bus) +{ + int portnum = bus->detail; + uint32_t reg; + + eb_data_t data = (portnum << SOCKIT_OWM_CTL_SEL_OFST) + | (SOCKIT_OWM_CTL_CYC_MSK) + | (SOCKIT_OWM_CTL_RST_MSK); + eb_device_write(device, BASE_ONEWIRE, EB_DATA32|EB_BIG_ENDIAN, data, 0, 0); + reg = __wait_cycle(device); + + /* return presence-detect pulse (1 if true) */ + return (reg & SOCKIT_OWM_CTL_DAT_MSK) ? 0 : 1; +} + +static int w1_read_bit(struct w1_bus *bus) +{ + int portnum = bus->detail; + uint32_t reg; + + eb_data_t data = (portnum << SOCKIT_OWM_CTL_SEL_OFST) + | (SOCKIT_OWM_CTL_CYC_MSK) + | (SOCKIT_OWM_CTL_DAT_MSK); + eb_device_write(device, BASE_ONEWIRE, EB_DATA32|EB_BIG_ENDIAN, data, 0, 0); + reg = __wait_cycle(device); + + return (reg & SOCKIT_OWM_CTL_DAT_MSK) ? 1 : 0; +} + +static void w1_write_bit(struct w1_bus *bus, int bit) +{ + int portnum = bus->detail; + + eb_data_t data = (portnum << SOCKIT_OWM_CTL_SEL_OFST) + | (SOCKIT_OWM_CTL_CYC_MSK) + | (bit ? SOCKIT_OWM_CTL_DAT_MSK : 0); + eb_device_write(device, BASE_ONEWIRE, EB_DATA32|EB_BIG_ENDIAN, data, 0, 0); + __wait_cycle(device); +} + +#define WB_CLOCK 62500000 +#define CLK_DIV_NOR (WB_CLOCK / 200000 - 1) /* normal mode */ +#define CLK_DIV_OVD (WB_CLOCK / 1000000 - 1) /* overdrive mode (not used) */ +void wrpc_w1_init(void) +{ + eb_data_t data = ((CLK_DIV_NOR & SOCKIT_OWM_CDR_N_MSK) | + ((CLK_DIV_OVD << SOCKIT_OWM_CDR_O_OFST) & + SOCKIT_OWM_CDR_O_MSK)); + eb_device_write(device, BASE_ONEWIRE+4, EB_DATA32|EB_BIG_ENDIAN, data, 0, 0); +} + +struct w1_ops wrpc_w1_ops = { + .reset = w1_reset, + .read_bit = w1_read_bit, + .write_bit = w1_write_bit, +}; + +struct w1_bus wrpc_w1_bus; diff --git a/tools/1w/sockit_owm_regs.h b/tools/1w/sockit_owm_regs.h new file mode 100644 index 0000000000..244728bf19 --- /dev/null +++ b/tools/1w/sockit_owm_regs.h @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////////////// +// // +// Minimalistic 1-wire (onewire) master with Avalon MM bus interface // +// // +// Copyright (C) 2010 Iztok Jeras // +// // +////////////////////////////////////////////////////////////////////////////// +// // +// This program is free software: you can redistribute it and/or modify // +// it under the terms of the GNU Lesser General Public License // +// as published by the Free Software Foundation, either // +// version 3 of the License, or (at your option) any later version. // +// // +// This program is distributed in the hope that it will be useful, // +// but WITHOUT ANY WARRANTY; without even the implied warranty of // +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // +// GNU General Public License for more details. // +// // +// You should have received a copy of the GNU General Public License // +// along with this program. If not, see . // +// // +////////////////////////////////////////////////////////////////////////////// + + +#ifndef __SOCKIT_OWM_REGS_H__ +#define __SOCKIT_OWM_REGS_H__ + + + +////////////////////////////////////////////////////////////////////////////// +// control status register // +////////////////////////////////////////////////////////////////////////////// + +#define SOCKIT_OWM_CTL_REG 0 +#define IOADDR_SOCKIT_OWM_CTL(base) IO_CALC_ADDRESS_NATIVE(base, SOCKIT_OWM_CTL_REG) +#define IORD_SOCKIT_OWM_CTL(base) (*(( volatile int*)base + SOCKIT_OWM_CTL_REG)) +#define IOWR_SOCKIT_OWM_CTL(base, data) (*(( volatile int*)base + SOCKIT_OWM_CTL_REG)) = data + +#define SOCKIT_OWM_CTL_DAT_MSK (0x00000001) // data bit +#define SOCKIT_OWM_CTL_DAT_OFST (0) +#define SOCKIT_OWM_CTL_RST_MSK (0x00000002) // reset +#define SOCKIT_OWM_CTL_RST_OFST (1) +#define SOCKIT_OWM_CTL_OVD_MSK (0x00000004) // overdrive +#define SOCKIT_OWM_CTL_OVD_OFST (2) +#define SOCKIT_OWM_CTL_CYC_MSK (0x00000008) // cycle +#define SOCKIT_OWM_CTL_CYC_OFST (3) +#define SOCKIT_OWM_CTL_PWR_MSK (0x00000010) // power (strong pull-up), if there is a single 1-wire line +#define SOCKIT_OWM_CTL_PWR_OFST (5) +#define SOCKIT_OWM_CTL_RSV_MSK (0x00000020) // reserved +#define SOCKIT_OWM_CTL_RSV_OFST (5) +#define SOCKIT_OWM_CTL_IRQ_MSK (0x00000040) // irq status +#define SOCKIT_OWM_CTL_IRQ_OFST (6) +#define SOCKIT_OWM_CTL_IEN_MSK (0x00000080) // irq enable +#define SOCKIT_OWM_CTL_IEN_OFST (7) + +#define SOCKIT_OWM_CTL_SEL_MSK (0x00000f00) // port select number +#define SOCKIT_OWM_CTL_SEL_OFST (8) + +#define SOCKIT_OWM_CTL_POWER_MSK (0xffff0000) // power (strong pull-up), if there is more than one 1-wire line +#define SOCKIT_OWM_CTL_POWER_OFST (16) + +// two common commands +#define SOCKIT_OWM_CTL_DLY_MSK ( SOCKIT_OWM_CTL_RST_MSK | SOCKIT_OWM_CTL_DAT_MSK) +#define SOCKIT_OWM_CTL_IDL_MSK (SOCKIT_OWM_CTL_OVD_MSK | SOCKIT_OWM_CTL_RST_MSK | SOCKIT_OWM_CTL_DAT_MSK) + +////////////////////////////////////////////////////////////////////////////// +// clock divider ratio register // +////////////////////////////////////////////////////////////////////////////// + +#define SOCKIT_OWM_CDR_REG 1 +#define IOADDR_SOCKIT_OWM_CDR(base) IO_CALC_ADDRESS_NATIVE(base, SOCKIT_OWM_CDR_REG) +#define IORD_SOCKIT_OWM_CDR(base) (*(( volatile int*)base + SOCKIT_OWM_CDR_REG)) +#define IOWR_SOCKIT_OWM_CDR(base, data) (*(( volatile int*)base + SOCKIT_OWM_CDR_REG)) = data + +#define SOCKIT_OWM_CDR_N_MSK (0x0000ffff) // normal mode +#define SOCKIT_OWM_CDR_N_OFST (0) +#define SOCKIT_OWM_CDR_O_MSK (0xffff0000) // overdrive mode +#define SOCKIT_OWM_CDR_O_OFST (16) + + +#endif /* __SOCKIT_OWM_REGS_H__ */ + diff --git a/tools/1w/w1.h b/tools/1w/w1.h new file mode 100644 index 0000000000..389fb1153f --- /dev/null +++ b/tools/1w/w1.h @@ -0,0 +1,102 @@ +/* + * Onewire generic interface + * Alessandro Rubini, 2013 GNU GPL2 or later + */ +#ifndef __BATHOS_W1_H__ +#define __BATHOS_W1_H__ + +#include + +#ifdef CONFIG_W1 +#define HAS_W1 1 +#else +#define HAS_W1 0 +#endif + +#ifdef CONFIG_W1_EEPROM +#define HAS_W1_EEPROM 1 +#else +#define HAS_W1_EEPROM 0 +#endif + +#define W1_MAX_DEVICES 8 /* we have no alloc */ +#define ONEWIRE_PORT 0 + +struct w1_dev { + struct w1_bus *bus; + uint64_t rom; +}; + +static inline int w1_class(struct w1_dev *dev) +{ + return dev->rom & 0xff; +} + + +struct w1_bus { + unsigned long detail; /* gpio bit or whatever (driver-specific) */ + struct w1_dev devs[W1_MAX_DEVICES]; +}; + +/* + * The low-level driver is based on this set of operations. We expect to + * only have one set of such operations in each build. (i.e., no bus-specific + * operations, to keep the thing simple and small). + */ +struct w1_ops { + int (*reset)(struct w1_bus *bus); /* returns 1 on "present" */ + int (*read_bit)(struct w1_bus *bus); + void (*write_bit)(struct w1_bus *bus, int bit); +}; + +/* Library functions */ +extern int w1_scan_bus(struct w1_bus *bus); +extern void w1_write_byte(struct w1_bus *bus, int byte); +extern int w1_read_byte(struct w1_bus *bus); +extern void w1_match_rom(struct w1_dev *dev); + +#define W1_CMD_SEARCH_ROM 0xf0 +#define W1_CMD_READ_ROM 0x33 +#define W1_CMD_MATCH_ROM 0x55 +#define W1_CMD_SKIP_ROM 0xcc +#define W1_CMD_ASEARCH 0xec + +/* commands for specific families */ +#define W1_CMDT_CONVERT 0x44 +#define W1_CMDT_W_SPAD 0x4e +#define W1_CMDT_R_SPAD 0xbe +#define W1_CMDT_CP_SPAD 0x48 +#define W1_CMDT_RECALL 0xb8 +#define W1_CMDT_R_PS 0xb4 +/* EEPROM DS28EC20 */ +#define W1_CMDR_W_SPAD 0x0f +#define W1_CMDR_R_SPAD 0xaa +#define W1_CMDR_C_SPAD 0x55 +#define W1_CMDR_R_MEMORY 0xf0 +#define W1_CMDR_EXT_R_MEMORY 0xa5 + +/* Temperature conversion takes time: by default wait, but allow flags */ +#define W1_FLAG_NOWAIT 0x01 /* start conversion only*/ +#define W1_FLAG_COLLECT 0x02 /* don't start, just get output */ + +/* These functions are dev-specific */ +extern int32_t w1_read_temp(struct w1_dev *dev, unsigned long flags); +extern int w1_read_eeprom(struct w1_dev *dev, + int offset, uint8_t *buffer, int blen); +extern int w1_write_eeprom(struct w1_dev *dev, + int offset, const uint8_t *buffer, int blen); +extern int w1_erase_eeprom(struct w1_dev *dev, int offset, int blen); + +/* These are generic, using the first suitable device in the bus */ +extern int32_t w1_read_temp_bus(struct w1_bus *bus, unsigned long flags); +extern int w1_read_eeprom_bus(struct w1_bus *bus, + int offset, uint8_t *buffer, int blen); +extern int w1_write_eeprom_bus(struct w1_bus *bus, + int offset, const uint8_t *buffer, int blen); +extern int w1_erase_eeprom_bus(struct w1_bus *bus, int offset, int blen); + +extern const struct w1_ops wrpc_w1_ops; +extern struct w1_bus wrpc_w1_bus; +extern void wrpc_w1_init(void); + +#endif /* __BATHOS_W1_H__ */ diff --git a/tools/Makefile b/tools/Makefile index aa02090394..77577b0cbd 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -4,6 +4,7 @@ EB ?= ../ip_cores/etherbone-core/api ECA ?= ../ip_cores/wr-cores/modules/wr_eca TLU ?= ../ip_cores/wr-cores/modules/wr_tlu WRPC ?= ../ip_cores/wrpc-sw +WRPC_IMPORT ?= ../modules/lm32-include/wrpc-import WBDIR ?= . TARGETS := eb-flash eb-info eb-console eb-config-nv eb-time eb-sflash eb-iflash eb-reset eb-daq-dump eb-fwload eb-i2c-master eb-asmi eb-fg-statistic EXTRA_I := eb-flash-secure @@ -60,7 +61,7 @@ io-test: io-test.cpp g++ $(CFLAGS) -I $(ECA) -I $(TLU) -o io-test io-test.cpp -L $(ECA) -L $(TLU) $(LIBS) -leca -ltlu eb-reset: eb-reset.c - $(CC) $(CFLAGS) -I$(WBDIR) -I$(WRPC)/include -I$(WRPC)/pp_printf $(WBDIR)/wb_api.c $(WRPC)/dev/w1.c $(WRPC)/dev/w1-temp.c $(WRPC)/dev/w1-eeprom.c $(WRPC)/tools/eb-w1.c -o eb-reset eb-reset.c $(LIBS) + $(CC) $(CFLAGS) -I$(WBDIR) -I$(WRPC_IMPORT) -I$(WRPC_IMPORT)/dev -I$(WBDIR)/1w $(WRPC_IMPORT)/dev/w1.c $(WRPC_IMPORT)/dev/w1-temp.c $(WBDIR)/wb_api.c $(WBDIR)/1w/eb-w1.c -o eb-reset eb-reset.c $(LIBS) eb-asmi: eb-asmi.c $(CC) $(CFLAGS) -I$(WBDIR) -o eb-asmi eb-asmi.c crc8.c crc32.c $(LIBS) diff --git a/tools/monitoring/Makefile b/tools/monitoring/Makefile index ea8c2fe58c..19be84fce4 100644 --- a/tools/monitoring/Makefile +++ b/tools/monitoring/Makefile @@ -6,11 +6,12 @@ PREFIX ?= /usr/local STAGING ?= EB ?= ../../ip_cores/etherbone-core/api WRPC ?= ../../ip_cores/wrpc-sw +WRPC_IMPORT ?= ../../modules/lm32-include/wrpc-import TARGETS := eb-mon eb-massmon USE_RPATH ?= yes EXTRA_FLAGS ?= -CFLAGS ?= $(EXTRA_FLAGS) -Wall -O2 -I $(EB) -I $(WRPC)/include -I $(WRPC)/pp_printf +CFLAGS ?= $(EXTRA_FLAGS) -Wall -O2 -I $(EB) -I$(WRPC_IMPORT)/dev -I$(WRPC_IMPORT) ifeq ($(USE_RPATH),yes) LIBS ?= -L $(EB)/.libs -Wl,-rpath,$(PREFIX)/lib -letherbone -lm else @@ -25,10 +26,10 @@ WBFLAG += -I$(WBDIR) all: $(TARGETS) eb-mon: eb-mon.c - $(CC) $(CFLAGS) $(WBFLAG) $(WBDIR)/wb_api.c $(WRPC)/dev/w1.c $(WRPC)/dev/w1-temp.c $(WRPC)/dev/w1-eeprom.c $(WRPC)/tools/eb-w1.c -o eb-mon eb-mon.c $(LIBS) + $(CC) $(CFLAGS) $(WBFLAG) $(WBDIR)/wb_api.c $(WRPC_IMPORT)/dev/w1.c $(WRPC_IMPORT)/dev/w1-temp.c $(WRPC_IMPORT)/dev/w1-eeprom.c $(WRPC)/tools/eb-w1.c -o eb-mon eb-mon.c $(LIBS) eb-massmon: eb-massmon.c - $(CC) $(CFLAGS) $(WBFLAG) $(WBDIR)/wb_api.c $(WRPC)/dev/w1.c $(WRPC)/dev/w1-temp.c $(WRPC)/dev/w1-eeprom.c $(WRPC)/tools/eb-w1.c -o eb-massmon eb-massmon.c $(LIBS) + $(CC) $(CFLAGS) $(WBFLAG) $(WBDIR)/wb_api.c $(WRPC_IMPORT)/dev/w1.c $(WRPC_IMPORT)/dev/w1-temp.c $(WRPC_IMPORT)/dev/w1-eeprom.c $(WRPC)/tools/eb-w1.c -o eb-massmon eb-massmon.c $(LIBS) clean: rm -f *.o eb-mon eb-massmon diff --git a/top/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.vhd b/top/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.vhd index 730daa0148..a5a748e4a2 100644 --- a/top/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.vhd +++ b/top/gsi_exploder5/exploder5_csco_tr/exploder5_csco_tr.vhd @@ -293,7 +293,7 @@ begin g_delay_diagnostics => true, g_en_timer => true, g_en_eca_tap => true, - g_en_asmi => false, + g_en_asmi => true, g_io_table => io_mapping_table, g_lm32_cores => c_cores, g_lm32_ramsizes => c_lm32_ramsizes/4, diff --git a/top/gsi_microtca/control/microtca_control.vhd b/top/gsi_microtca/control/microtca_control.vhd index c5279612c5..06dcfd5e0f 100644 --- a/top/gsi_microtca/control/microtca_control.vhd +++ b/top/gsi_microtca/control/microtca_control.vhd @@ -398,12 +398,12 @@ begin g_delay_diagnostics => true, g_en_timer => true, g_en_eca_tap => true, + g_en_asmi => true, g_io_table => io_mapping_table, g_lm32_cores => c_cores, g_lm32_ramsizes => c_lm32_ramsizes/4, g_lm32_init_files => f_string_list_repeat(c_initf_name, c_cores), - g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores), - g_en_asmi => false + g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores) ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i, diff --git a/top/gsi_pexarria10/ftm10/ftm10.vhd b/top/gsi_pexarria10/ftm10/ftm10.vhd index daf3c81b00..eb0900569b 100644 --- a/top/gsi_pexarria10/ftm10/ftm10.vhd +++ b/top/gsi_pexarria10/ftm10/ftm10.vhd @@ -252,7 +252,6 @@ begin g_en_eca => false, g_delay_diagnostics => true, g_lm32_are_ftm => true, - g_lm32_MSIs => 1, g_lm32_cores => c_cores, g_lm32_ramsizes => c_lm32_ramsizes/4, g_lm32_init_files => f_string_list_repeat(c_initf_name, c_cores), diff --git a/top/gsi_pexarria10/ftm10/ramsize_pkg.vhd b/top/gsi_pexarria10/ftm10/ramsize_pkg.vhd index 9a188d83da..137d5360d5 100644 --- a/top/gsi_pexarria10/ftm10/ramsize_pkg.vhd +++ b/top/gsi_pexarria10/ftm10/ramsize_pkg.vhd @@ -4,5 +4,5 @@ use ieee.numeric_std.all; library work; package ramsize_pkg is - constant c_lm32_ramsizes : natural := 458752; + constant c_lm32_ramsizes : natural := 393216; end ramsize_pkg; diff --git a/top/gsi_pexarria5/control/pci_control.vhd b/top/gsi_pexarria5/control/pci_control.vhd index debfbf8313..82ab6c51c7 100644 --- a/top/gsi_pexarria5/control/pci_control.vhd +++ b/top/gsi_pexarria5/control/pci_control.vhd @@ -273,12 +273,12 @@ begin g_delay_diagnostics => true, g_en_timer => true, g_en_eca_tap => true, + g_en_asmi => true, g_io_table => io_mapping_table, g_lm32_cores => c_cores, g_lm32_ramsizes => c_lm32_ramsizes/4, g_lm32_init_files => f_string_list_repeat(c_initf_name, c_cores), - g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores), - g_en_asmi => false + g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores) ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i, diff --git a/top/gsi_pexarria5/ftm/ftm.vhd b/top/gsi_pexarria5/ftm/ftm.vhd index 44a9bb862e..fedba62e98 100644 --- a/top/gsi_pexarria5/ftm/ftm.vhd +++ b/top/gsi_pexarria5/ftm/ftm.vhd @@ -270,15 +270,15 @@ begin g_en_pcie => true, g_en_usb => true, g_en_lcd => false, + g_delay_diagnostics => true, + g_en_eca => false, + g_en_asmi => true, g_io_table => io_mapping_table, g_lm32_are_ftm => true, g_lm32_cores => c_cores, g_lm32_ramsizes => c_lm32_ramsizes/4, - g_lm32_MSIs => 1, - g_delay_diagnostics => true, g_lm32_init_files => f_string_list_repeat(c_initf_name, c_cores), - g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores), - g_en_eca => false + g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores) ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i, diff --git a/top/gsi_pexarria5/ftm/ramsize_pkg.vhd b/top/gsi_pexarria5/ftm/ramsize_pkg.vhd index e3ac4d048d..abdef1927f 100644 --- a/top/gsi_pexarria5/ftm/ramsize_pkg.vhd +++ b/top/gsi_pexarria5/ftm/ramsize_pkg.vhd @@ -4,5 +4,5 @@ use ieee.numeric_std.all; library work; package ramsize_pkg is - constant c_lm32_ramsizes : natural := 65536; + constant c_lm32_ramsizes : natural := 131072 ; end ramsize_pkg; diff --git a/top/gsi_pexp/control/pexp_control.vhd b/top/gsi_pexp/control/pexp_control.vhd index 1348bd1c19..522ea06dc3 100644 --- a/top/gsi_pexp/control/pexp_control.vhd +++ b/top/gsi_pexp/control/pexp_control.vhd @@ -287,7 +287,7 @@ begin g_delay_diagnostics => true, g_en_timer => true, g_en_eca_tap => true, - g_en_asmi => false, + g_en_asmi => true, g_io_table => io_mapping_table, g_lm32_cores => c_cores, g_lm32_ramsizes => c_lm32_ramsizes/4, diff --git a/top/gsi_pmc/control/pci_pmc.vhd b/top/gsi_pmc/control/pci_pmc.vhd index e82a1f4ab6..58bed28d0a 100644 --- a/top/gsi_pmc/control/pci_pmc.vhd +++ b/top/gsi_pmc/control/pci_pmc.vhd @@ -299,12 +299,12 @@ begin g_delay_diagnostics => true, g_en_timer => true, g_en_eca_tap => true, + g_en_asmi => true, g_io_table => io_mapping_table, g_lm32_cores => c_cores, g_lm32_ramsizes => c_lm32_ramsizes/4, g_lm32_init_files => f_string_list_repeat(c_initf_name, c_cores), - g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores), - g_en_asmi => false + g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores) ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i, diff --git a/top/gsi_scu/control2/ramsize_pkg.vhd b/top/gsi_scu/control2/ramsize_pkg.vhd index e3ac4d048d..19d71e50c2 100644 --- a/top/gsi_scu/control2/ramsize_pkg.vhd +++ b/top/gsi_scu/control2/ramsize_pkg.vhd @@ -4,5 +4,5 @@ use ieee.numeric_std.all; library work; package ramsize_pkg is - constant c_lm32_ramsizes : natural := 65536; + constant c_lm32_ramsizes : natural := 147456; end ramsize_pkg; diff --git a/top/gsi_scu/control2/scu_control.vhd b/top/gsi_scu/control2/scu_control.vhd index 7b93efc5ab..7d3a84f008 100644 --- a/top/gsi_scu/control2/scu_control.vhd +++ b/top/gsi_scu/control2/scu_control.vhd @@ -312,7 +312,7 @@ begin g_en_wd_tmr => true, g_en_eca_tap => true, g_en_timer => true, - g_en_asmi => false + g_en_asmi => true ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i, diff --git a/top/gsi_scu/control3/ramsize_pkg.vhd b/top/gsi_scu/control3/ramsize_pkg.vhd index 6c237cd97a..19d71e50c2 100644 --- a/top/gsi_scu/control3/ramsize_pkg.vhd +++ b/top/gsi_scu/control3/ramsize_pkg.vhd @@ -4,5 +4,5 @@ use ieee.numeric_std.all; library work; package ramsize_pkg is - constant c_lm32_ramsizes : natural := 98304; + constant c_lm32_ramsizes : natural := 147456; end ramsize_pkg; diff --git a/top/gsi_scu/control3/scu_control.vhd b/top/gsi_scu/control3/scu_control.vhd index d097e85033..a0d675c4d9 100644 --- a/top/gsi_scu/control3/scu_control.vhd +++ b/top/gsi_scu/control3/scu_control.vhd @@ -323,7 +323,7 @@ begin g_en_wd_tmr => true, g_en_eca_tap => true, g_en_timer => true, - g_en_asmi => false + g_en_asmi => true ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i, diff --git a/top/gsi_scu/ftm4/ftm4.vhd b/top/gsi_scu/ftm4/ftm4.vhd index 1791dd2bad..b131661a32 100644 --- a/top/gsi_scu/ftm4/ftm4.vhd +++ b/top/gsi_scu/ftm4/ftm4.vhd @@ -229,7 +229,6 @@ begin g_en_psram => true, g_io_table => io_mapping_table, g_lm32_are_ftm => true, - g_lm32_MSIs => 1, g_en_tempsens => false, g_a10_use_sys_fpll => false, g_a10_use_ref_fpll => false, diff --git a/top/gsi_scu/ftm4dp/ftm4dp.vhd b/top/gsi_scu/ftm4dp/ftm4dp.vhd index 2912d128c0..aaa881ed9d 100644 --- a/top/gsi_scu/ftm4dp/ftm4dp.vhd +++ b/top/gsi_scu/ftm4dp/ftm4dp.vhd @@ -237,7 +237,6 @@ begin g_en_psram => true, g_io_table => io_mapping_table, g_lm32_are_ftm => true, - g_lm32_MSIs => 1, g_en_tempsens => false, g_a10_use_sys_fpll => false, g_a10_use_ref_fpll => false, diff --git a/top/gsi_scu/main.c b/top/gsi_scu/main.c index 84775f9146..981b86cb83 100644 --- a/top/gsi_scu/main.c +++ b/top/gsi_scu/main.c @@ -6,7 +6,6 @@ #include #include "syscon.h" -#include "hw/memlayout.h" #include "mprintf.h" #include "display.h" #include "irq.h" @@ -24,6 +23,7 @@ #include "../../ip_cores/saftlib/src/eca_flags.h" #include "history.h" #include "scu_control_shared_mmap.h" +//#include "memlayout.h" #define MSI_SLAVE 0 #define MSI_WB_FG 2 @@ -645,14 +645,14 @@ void disable_channel(unsigned int channel) { /** @brief updates the temperatur information in the shared section */ void updateTemp() { - BASE_ONEWIRE = (unsigned char *)wr_1wire_base; + pOneWire = (uint32_t*)wr_1wire_base; wrpc_w1_init(); ReadTempDevices(0, &board_id, &board_temp); - BASE_ONEWIRE = (unsigned char *)user_1wire_base; + pOneWire = (uint32_t*)user_1wire_base; wrpc_w1_init(); ReadTempDevices(0, &ext_id, &ext_temp); ReadTempDevices(1, &backplane_id, &backplane_temp); - BASE_ONEWIRE = (unsigned char *)wr_1wire_base; // important for PTP deamon + pOneWire = (uint32_t*)wr_1wire_base; // important for PTP deamon wrpc_w1_init(); } diff --git a/top/gsi_vetar2a/ee_butis/vetar2a_ee_butis.vhd b/top/gsi_vetar2a/ee_butis/vetar2a_ee_butis.vhd index d987fefea8..573e21bd92 100644 --- a/top/gsi_vetar2a/ee_butis/vetar2a_ee_butis.vhd +++ b/top/gsi_vetar2a/ee_butis/vetar2a_ee_butis.vhd @@ -343,7 +343,7 @@ begin g_lm32_ramsizes => c_lm32_ramsizes/4, g_lm32_init_files => f_string_list_repeat(c_initf_name, c_cores), g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores), - g_en_asmi => false + g_en_asmi => true ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i, diff --git a/top/gsi_vetar2a/wr_core_demo/vetar2a_top.vhd b/top/gsi_vetar2a/wr_core_demo/vetar2a_top.vhd index 826148b8d6..3dfb817fca 100644 --- a/top/gsi_vetar2a/wr_core_demo/vetar2a_top.vhd +++ b/top/gsi_vetar2a/wr_core_demo/vetar2a_top.vhd @@ -344,7 +344,7 @@ begin g_lm32_ramsizes => c_lm32_ramsizes/4, g_lm32_init_files => f_string_list_repeat(c_initf_name, c_cores), g_lm32_profiles => f_string_list_repeat(c_profile_name, c_cores), - g_en_asmi => false + g_en_asmi => true ) port map( core_clk_20m_vcxo_i => clk_20m_vcxo_i,