From 27dd3bb04d01188f4d372b5b4393735ad0857c19 Mon Sep 17 00:00:00 2001 From: Antonietta Russo Date: Wed, 31 Jul 2024 13:47:18 +0200 Subject: [PATCH 1/2] BLM: added the control through event cycles, the readout of all the counters status and extended the counters width. --- top/blm_aco/BLM_counter_pool_el.vhd | 6 +- top/blm_aco/BLM_out_el_m_v1.0.vhd | 42 +-- top/blm_aco/Beam_Loss_check_v2.vhd | 397 ++++++++++++++++++++++++++ top/blm_aco/Manifest.py | 6 +- top/blm_aco/blm_aco_v1.0.vhd | 416 +++++++++++++++++++--------- top/blm_aco/event_ctrl_el.vhd | 170 ++++++++++++ top/blm_aco/p_connector.vhd | 13 +- top/blm_aco/scu_diob_pkg.vhd | 26 +- top/blm_aco/thr_load_el.vhd | 0 top/blm_aco/up_down_counter.vhd | 6 +- 10 files changed, 885 insertions(+), 197 deletions(-) create mode 100644 top/blm_aco/Beam_Loss_check_v2.vhd create mode 100644 top/blm_aco/event_ctrl_el.vhd create mode 100644 top/blm_aco/thr_load_el.vhd diff --git a/top/blm_aco/BLM_counter_pool_el.vhd b/top/blm_aco/BLM_counter_pool_el.vhd index a71255be52..bd5678ec8e 100644 --- a/top/blm_aco/BLM_counter_pool_el.vhd +++ b/top/blm_aco/BLM_counter_pool_el.vhd @@ -5,7 +5,7 @@ use work.scu_diob_pkg.all; entity BLM_counter_pool_el is generic ( - WIDTH : integer := 30 -- Counter width + WIDTH : integer := 32 -- Counter width ); port ( @@ -45,7 +45,7 @@ signal cnt_up, cnt_down: std_logic; component up_down_counter is generic ( - WIDTH : integer := 30 -- Counter width + WIDTH : integer := 32 -- Counter width ); port ( @@ -122,7 +122,7 @@ end process; Counter_module: up_down_counter generic map ( - WIDTH => 30 --WIDTH -- Counter width + WIDTH => 32 --WIDTH -- Counter width ) port map diff --git a/top/blm_aco/BLM_out_el_m_v1.0.vhd b/top/blm_aco/BLM_out_el_m_v1.0.vhd index 05a9523660..670270500a 100644 --- a/top/blm_aco/BLM_out_el_m_v1.0.vhd +++ b/top/blm_aco/BLM_out_el_m_v1.0.vhd @@ -24,7 +24,7 @@ port ( gate_in : in std_logic_vector(11 downto 0); -- to be sent to the status registers gate_error : in std_logic_vector(11 downto 0); -- to be sent to the status registers gate_out : in std_logic_vector (11 downto 0); --gate error - counter_reg: in t_BLM_counter_Array; + -- counter_reg: in t_BLM_counter_Array; gate_state: in std_logic_vector(47 downto 0); led_id_state : in std_logic_vector(3 downto 0); BLM_Output : out std_logic_vector(5 downto 0); @@ -131,41 +131,7 @@ begin end process; ----------------------------------------------------------------------------------------- -out_counter_buffer_proc: process (clk, nRST) -begin - if not nRST='1' then - for i in 0 to 127 loop - up_down_counter_val(i) <= (others =>'0'); - end loop; - - out_cnt_wr <='0'; - - elsif (clk'EVENT AND clk= '1') then - - out_cnt_wr<= BLM_out_sel_reg(126)(15); - - - - if out_cnt_wr='1' then - - for i in 0 to 127 loop - up_down_counter_val(i) <= counter_reg(i); - - end loop; - end if; - - end if; -end process; - - status_reg_counter_value_process: process (up_down_counter_val, BLM_out_sel_reg(121)) - begin - - read_counters <= to_integer(unsigned(BLM_out_sel_Reg(126)(6 downto 0))); - cnt_readback <= up_down_counter_val(read_counters); - - - end process; +------------------------------------------------------------------------------------ -------------------------------------------------------------------------------------------------- ----- BLM_STATUS_REGISTERS -------------------------------------------------------------------------------------------------- @@ -181,8 +147,8 @@ end process; BLM_status_reg(18) <= wd_output(31 downto 16); BLM_status_reg(19) <= wd_output(47 downto 32); BLM_status_reg(20) <= "0000000000" & wd_output(53 downto 48); - BLM_status_reg(21) <= cnt_readback(15 downto 0); - BLM_status_reg(22) <= cnt_readback(29) & cnt_readback(29) & cnt_readback(29 downto 16); + BLM_status_reg(21) <=(others =>'0'); + BLM_status_reg(22) <=(others =>'0'); BLM_status_reg(23) <= "0000" & gate_input; BLM_status_reg(24) <= "0000" & gate_output; BLM_status_reg(25) <= "0000000000" & BLM_out_signal; diff --git a/top/blm_aco/Beam_Loss_check_v2.vhd b/top/blm_aco/Beam_Loss_check_v2.vhd new file mode 100644 index 0000000000..fb9b263e12 --- /dev/null +++ b/top/blm_aco/Beam_Loss_check_v2.vhd @@ -0,0 +1,397 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; +use IEEE.std_logic_misc.all; +use work.scu_diob_pkg.all; + +entity Beam_Loss_check is + generic ( + + WIDTH : integer := 30 -- Counter width + +); +port ( + clk_sys : in std_logic; -- Clock + rstn_sys : in std_logic; -- Reset + + -- IN BLM + BLM_data_in : in std_logic_vector(53 downto 0); + BLM_gate_in : in std_logic_vector(11 downto 0); + BLM_tst_ck_sig : in std_logic_vector (10 downto 0); + IOBP_LED_nr : in std_logic_vector(3 downto 0); + --IN registers + pos_threshold : in t_BLM_th_Array; --t_BLM_th_Array is array (0 to 127) of std_logic_vector(31 downto 0); + neg_threshold : in t_BLM_th_Array ; + BLM_wdog_hold_time_Reg : in std_logic_vector(15 downto 0); + BLM_wd_reset : in std_logic_vector(53 downto 0); + BLM_gate_hold_time_Reg : in t_BLM_gate_hold_Time_Array; + BLM_ctrl_Reg : in std_logic_vector(15 downto 0); + -- bit 11-0 Direct Gate-usage, one bit for each gate signal input (BLM_gate_in), + -- bit 14 reset from gate + -- bit 15 free + + BLM_gate_seq_prep_ck_sel_Reg : in std_logic_vector(15 downto 0);-- bit 15 free + -- bit 12counter RESET, + -- bit 11-0f or gate_prepare signals + -- + BLM_gate_recover_Reg : in std_logic_vector(15 downto 0); -- bit 15_12 free + -- bit 11-0 for gate_prepare signals + BLM_in_sel_Reg : in t_BLM_reg_Array; --128 x (4 bit for gate ena & 6 bit for up signal ena & 6 for down signal ena) + BLM_out_sel_reg : in t_BLM_out_sel_reg_Array; --- 122 x 16 bits = Reg120-0: "0000" and 6 x (54 watchdog errors + 12 gate errors + 256 counters overflows outputs) + + + ev_thr_load: in std_logic; + virt_acc: in std_logic_vector(11 downto 0); + ev_prepare_reg : in std_logic_vector(11 downto 0); + ev_recover_reg: in std_logic_vector(11 downto 0); + ev_counter_reset: in std_logic; + + + + -- + 4 more registers for 6 x 12 input gate (= 72 bits) to be send to the outputs. + --=> 126 registers + -- REg127 (ex Reg121): counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used + -- OUT register + -- BLM_status_Reg : out t_IO_Reg_0_to_25_Array ; + BLM_status_Reg : out t_IO_Reg_0_to_29_Array ; + counter_readout_reg: out t_BLM_th_Array ; + -- OUT BLM + BLM_Out : out std_logic_vector(5 downto 0) +); + +end Beam_Loss_check; + +architecture rtl of Beam_Loss_check is + + signal BLM_test_signal : std_logic_vector(9 downto 0); --Test signals + ground --to reference Test_In_Mtx + + signal gate_clock : std_logic_vector (11 downto 0); + signal g_clock: std_logic_vector(11 downto 0); + signal VALUE_IN: std_logic_vector(63 downto 0); + + signal out_wd: std_logic_vector(53 downto 0); + signal out_1wd: std_logic_vector(53 downto 0); + + signal INT_out: std_logic_vector(53 downto 0); + signal gate_error: std_logic_vector(11 downto 0); + signal Gate_In_Mtx: std_logic_vector (11 downto 0):= (OTHERS => '0'); -- gate outputs from the gate timing sequence control + signal UP_OVERFLOW: std_logic_vector(127 downto 0); + signal DOWN_OVERFLOW: std_logic_vector(127 downto 0); + signal gate_sel: integer range 0 to 127; + signal cnt_enable: std_logic_vector(127 downto 0); + signal BLM_Output_mtx: t_BLM_out_Array; + signal gate_output: std_logic_vector (11 downto 0); + signal wd_reset: std_logic_vector(53 downto 0); + signal BLM_gate_recover: std_logic_vector(11 downto 0); + signal BLM_gate_seq_clk_sel: std_logic_vector(2 downto 0); + signal BLM_gate_prepare : std_logic_vector(11 downto 0); + signal counter_value: t_BLM_counter_Array; +signal gate_test_value: std_logic_vector(11 downto 0); +signal gate_sm_error: std_logic_vector(11 downto 0); +signal gate_sm_output: std_logic_vector(11 downto 0); +signal gate_recover: std_logic_vector(11 downto 0); +signal gate_prepare: std_logic_vector(11 downto 0); +signal gate_hold_time: t_BLM_gate_hold_Time_Array; +signal gate_state: std_logic_vector(47 downto 0); +signal gate_sm_state :t_gate_state_nr; + +signal UP_OVERFLOW_OUT: std_logic_vector(127 downto 0):=(others => '0'); +signal DOWN_OVERFLOW_OUT: std_logic_vector(127 downto 0):=(others => '0'); +signal direct_gate: std_logic_vector(11 downto 0); +signal LED_ID_state: std_logic_vector(3 downto 0); +signal pos_th, neg_th: t_BLM_th_Array; +signal ev_pos_neg_thr: std_logic_vector(63 downto 0):=(others => '0'); +signal cnt_nr : integer range 0 to 127; + component BLM_watchdog is + + port( + clk_i : in std_logic; -- chip-internal pulsed clk signal + rst_i : in std_logic; -- reset signal + wd_reset: in std_logic; -- watchdog reset signal + hold: in std_logic_vector(15 downto 0); + in_watchdog : in std_logic; -- input signal + -- ena_i : in std_logic; -- enable '1' for input connected to the counter + INTL_out: out std_logic -- interlock output for signal that doesn't change for a given time + + ); +end component BLM_watchdog; + +component BLM_gate_timing_seq is + + generic ( + + + n : integer range 0 TO 12 := 12 + ); + port( + clk_i : in std_logic; + rstn_i : in std_logic; -- reset signal + gate_in : in std_logic_vector(n-1 downto 0); -- input signal + direct_gate : in std_logic_vector(n-1 downto 0); + BLM_gate_recover: in std_logic_vector(11 downto 0); + BLM_gate_prepare : in std_logic_vector(11 downto 0); + hold_time : in t_BLM_gate_hold_Time_Array; + gate_error : out std_logic_vector(n-1 downto 0); -- gate doesn't start within the given timeout + state_nr: out t_gate_state_nr; + gate_out: out std_logic_vector(n-1 downto 0) -- out gate signal + ); + end component BLM_gate_timing_seq; + + component BLM_ena_in_mux is + port ( + CLK : in std_logic; -- Clock + nRST : in std_logic; -- Reset + mux_sel : in t_BLM_reg_Array; + in_mux : in std_logic_vector(11 downto 0); + cnt_enable : out std_logic_vector(127 downto 0) + ); + end component BLM_ena_in_mux; + + + component BLM_counter_pool_el is + + generic ( + WIDTH : integer := 32 -- Counter width + + ); + port ( + CLK : in std_logic; -- Clock + nRST : in std_logic; -- Reset + gate_reset_ena : in std_logic; + RESET : in std_logic; -- global counter reset + ENABLE : in std_logic; -- Enable count operation (gate signals) + pos_threshold : in std_logic_vector(31 downto 0); + neg_threshold : in std_logic_vector(31 downto 0); + in_counter : in std_logic_vector(63 downto 0); + BLM_cnt_Reg : in std_logic_vector(15 downto 0); -- bit 5-0 = up_in_counter select, bit 11-6 = down_in_counter select, 15..13 in_ena + cnt : out std_logic_vector (WIDTH-1 downto 0); -- Counter register + + UP_OVERFLOW : out std_logic; -- UP_Counter overflow for the input signals + DOWN_OVERFLOW : out std_logic -- DOWN_Counter overflow for the input signals + + ); + end component BLM_counter_pool_el; + + + component BLM_out_el is + + port ( + CLK : in std_logic; -- Clock + nRST : in std_logic; -- Reset + BLM_out_sel_reg : in t_BLM_out_sel_reg_Array; -- 122 x 16 bits = Reg120-0: "0000" and 6 x (54 watchdog errors + 12 gate errors + 256 counters overflows outputs) + -- Reg121: counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used + UP_OVERFLOW : in std_logic_vector(127 downto 0); + DOWN_OVERFLOW : in std_logic_vector(127 downto 0); + + wd_out : in std_logic_vector(53 downto 0); + gate_in : in std_logic_vector(11 downto 0); -- to be sent to the status registers + gate_error : in std_logic_vector (11 downto 0); + gate_out : in std_logic_vector (11 downto 0); + -- counter_reg: in t_BLM_counter_Array; + + gate_state: in std_logic_vector(47 downto 0); + led_id_state : in std_logic_vector(3 downto 0); + BLM_Output : out std_logic_vector(5 downto 0); + -- BLM_status_Reg : out t_IO_Reg_0_to_25_Array + BLM_status_Reg : out t_IO_Reg_0_to_29_Array + ); + + end component BLM_out_el; + + + -- component thr_RAM is + -- port( + -- clock : in std_logic; + -- wren : in std_logic; + -- rden : in std_logic; + -- raddr : in std_logic_vector(10 downto 0); + -- waddr : in std_logic_vector(10 downto 0); + -- data_in : in std_logic_vector(63 downto 0); + -- data_out : out std_logic_vector(63 downto 0) + -- ); + -- end component thr_RAM; + + +---###################################################################################### + +begin + +VALUE_IN <= BLM_test_signal & BLM_data_in; +BLM_gate_recover <= ev_recover_reg or BLM_gate_recover_Reg(11 downto 0); + BLM_gate_prepare <= ev_prepare_reg or BLM_gate_seq_prep_ck_sel_Reg(11 downto 0); + + +--direct_gate <= BLM_ctrl_Reg(11 downto 0); +direct_gate <= BLM_ctrl_Reg(5 downto 0) & BLM_ctrl_Reg(11 downto 6); +g_clock <= gate_clock; + +BLM_test_signal <= BLM_tst_ck_sig(9) & -- 25 MHz + BLM_tst_ck_sig(8) & -- 24.9 MHz + BLM_tst_ck_sig(7) & -- 10 MHz + BLM_tst_ck_sig(2) & -- 9.9 MHz + BLM_tst_ck_sig(6) & -- 1 MHz + BLM_tst_ck_sig(1) & -- 0.99 MHz + BLM_tst_ck_sig(5) & -- 100 kHz + BLM_tst_ck_sig(0) & -- 99 kHz + BLM_tst_ck_sig(4) & -- 10 kHz + '0'; -- GND + +-- for direct Gate operations: if the corresponding BLM_ctrl_Reg (bit +2)='0' then BLM_gate_in signals +-- are used as input signal to the multiplexer (BLM_ena_in_mux) which gives the counter enables. + + +LED_ID_state <= IOBP_LED_nr; + +direct_gate_operation: process(BLM_ctrl_Reg, BLM_gate_in, gate_output) + +begin + + for i in 0 to 5 loop + + if BLM_ctrl_Reg(i) = '1' then --when '0', gate signals are directly sent to the 12 to 126 multiplexer for the counter enables assignments + gate_In_Mtx(i)<= BLM_gate_in(i+6); + else + gate_IN_Mtx(i) <= gate_output(i+6); + end if; + end loop; + for i in 6 to 11 loop + + if BLM_ctrl_Reg(i) = '1' then --when '0', gate signals are directly sent to the 12 to 128 multiplexer for the counter enables assignments + gate_In_Mtx(i)<= BLM_gate_in(i-6); + else + gate_IN_Mtx(i) <= gate_output(i-6); + end if; + end loop; +end process direct_gate_operation; + + + gate_board: BLM_gate_timing_seq + + generic map ( + n => 12 + ) + port map( + clk_i => clk_sys, -- + rstn_i => rstn_sys, -- reset signal + gate_in => BLM_gate_in, -- gate input signals + direct_gate => direct_gate, + BLM_gate_recover => BLM_gate_recover(5 downto 0)&BLM_gate_recover(11 downto 6), + BLM_gate_prepare => BLM_gate_prepare(5 downto 0)&BLM_gate_prepare(11 downto 6), + hold_time => gate_hold_time, + + gate_error => gate_sm_error, -- gate error + state_nr => gate_sm_state, + gate_out => gate_sm_output --gate_output + ); + + gate_error <= gate_sm_error; + gate_output <= gate_sm_output; + + gate_state <= '0'& gate_sm_state(5) & '0'& gate_sm_state(4)& '0'& gate_sm_state(3)&'0'& gate_sm_state(2) & '0'& gate_sm_state(1)&'0'& gate_sm_state(0)& + '0'& gate_sm_state(11) & '0'& gate_sm_state(10)& '0'& gate_sm_state(9)&'0'& gate_sm_state(8) & '0'& gate_sm_state(7)&'0'& gate_sm_state(6); + + + gate_hold_time_proc: process(BLM_gate_hold_time_Reg) + + begin + for i in 0 to 5 loop + gate_hold_time(i) <= BLM_gate_hold_time_Reg(i+6); + end loop; + for i in 6 to 11 loop + gate_hold_time(i) <= BLM_gate_hold_time_Reg(i-6); + end loop; + + end process gate_hold_time_proc; + + wd_elem_gen: for i in 0 to 53 generate + + input_Watchdog: BLM_watchdog + + port map( + clk_i => clk_sys, + rst_i => rstn_sys, -- reset signal + wd_reset=> BLM_wd_reset(i), -- watchdog reset signal + hold => BLM_wdog_hold_time_Reg, + in_watchdog => BLM_data_in(i), + -- ena_i => '1', -- enable for input connected to the counter + INTL_out => out_1wd(i)); + --INTL_out => out_wd(i)); + end generate wd_elem_gen; + + + + +---- counter ena mux ------------------------------------------------------------------------------ +BLM_counter_ena_block: BLM_ena_in_mux + port map( + CLK => clk_sys, + nRST => rstn_sys, + mux_sel => BLM_in_sel_Reg, + in_mux => gate_In_Mtx, + cnt_enable => cnt_enable + ); + + + ---- counter pool ------------------------------------------------------------------------------ + +BLM_counter_pool: for i in 0 to 127 generate + +BLM_counter_pool_elem: BLM_counter_pool_el +generic map ( + WIDTH => 32) +port map ( + CLK => clk_sys, + nRST => rstn_sys, + gate_reset_ena => BLM_ctrl_reg(14) and cnt_enable(i), + RESET => BLM_gate_seq_prep_ck_sel_Reg(12) or ev_counter_reset, + ENABLE => cnt_enable(i), + pos_threshold => pos_threshold(i), + neg_threshold => neg_threshold(i), + in_counter => VALUE_IN, + + BLM_cnt_Reg => BLM_in_sel_Reg(i), + cnt => counter_value(i), + + UP_OVERFLOW => UP_OVERFLOW(i), + DOWN_OVERFLOW => DOWN_OVERFLOW(i) + ); + end generate BLM_counter_pool; +----------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------- + + +BLM_out_section: BLM_out_el + + port map( + CLK => clk_sys, + nRST => rstn_sys, -- Reset + -- +++ + BLM_out_sel_reg => BLM_out_sel_reg, + -- + UP_OVERFLOW =>UP_OVERFLOW, + -- UP_OVERFLOW => neg_threshold(0) & pos_threshold(0)&UP_OVERFLOW(63 downto 0), + --UP_OVERFLOW => UP_OVERFLOW(127 downto 80)& gate_state & "0000"& BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6)& "0000"& gate_output(5 downto 0) & gate_output(11 downto 6), -- UP_OVERFLOW & gate_in & gate_out , -- ONLY FOR TESTS + --DOWN_OVERFLOW => DOWN_OVERFLOW_OUT, + DOWN_OVERFLOW => DOWN_OVERFLOW, + wd_out => out_1wd, --out_wd, --out_1wd, + gate_in => BLM_gate_in(5 downto 0) & BLM_gate_in(11 downto 6),--BLM_gate_in, + gate_error => gate_error(5 downto 0) & gate_error(11 downto 6), + gate_out => gate_output(5 downto 0) & gate_output(11 downto 6), + gate_state => gate_state, + led_id_state => LED_ID_state, + BLM_Output => BLM_out, + -- counter_reg => counter_value, + BLM_status_Reg => BLM_status_Reg + ); + + + counters_readout_proc: process (counter_value) + begin + for i in 0 to 127 loop + counter_readout_reg(i) <= counter_value(i); + end loop; + end process counters_readout_proc; + + + end architecture; + diff --git a/top/blm_aco/Manifest.py b/top/blm_aco/Manifest.py index bd8ead7018..530dc4f154 100644 --- a/top/blm_aco/Manifest.py +++ b/top/blm_aco/Manifest.py @@ -23,7 +23,8 @@ "BLM_watchdog_v1.0.vhd", "BLM_gate_timing_seq_v1.2.vhd", "up_down_counter.vhd", - "Beam_Loss_check_v1.2.vhd", + # working, but without ev_ctrl "Beam_Loss_check_v1.2.vhd", + "Beam_Loss_check_v2.vhd", "front_board_id_v0.vhd", "BLM_counter_pool_el.vhd", "BLM_out_el_m_v1.0.vhd", @@ -35,7 +36,8 @@ "BLM_ena_in_mux.vhd", "blm_24_9_9_9pll.vhd", "deglitcher.v", - "BLM_cnt_pulse_former.vhd" + "BLM_cnt_pulse_former.vhd", + "event_ctrl_el.vhd" ] modules = { diff --git a/top/blm_aco/blm_aco_v1.0.vhd b/top/blm_aco/blm_aco_v1.0.vhd index a0e11dde9d..3df6a4b378 100644 --- a/top/blm_aco/blm_aco_v1.0.vhd +++ b/top/blm_aco/blm_aco_v1.0.vhd @@ -10,7 +10,7 @@ use work.aux_functions_pkg.all; use work.scu_diob_pkg.all; use work.pll_pkg.all; use work.monster_pkg.all; -use work.daq_pkg.all; + -- Base_addr : DIOB-Config-Register1 (all bits can be read and written) @@ -156,12 +156,16 @@ architecture blm_aco_arch_for_Beam_Loss_Mon of blm_aco is CONSTANT c_IOBP_Masken_Base_Addr: Integer := 16#0630#; -- IO-Backplane Maske-Register CONSTANT c_IOBP_ID_Base_Addr: Integer := 16#0638#; -- IO-Backplane Modul-ID-Register CONSTANT c_Status_READBACK_Base_Addr: Integer := 16#0670#; -- IO-Backplane Output Readback Register: 24 x 16 bit registers --> +18h - CONSTANT c_DIOB_DAQ_Base_Addr: Integer := 16#2000#; -- DAQ Base Address - CONSTANT c_BLM_thres_Base_Addr: Integer := 16#0700#; -- BLM threshold for the counter pool: 512 16 bit registers--> + 200h + -- CONSTANT c_DIOB_DAQ_Base_Addr: Integer := 16#2000#; -- DAQ Base Address + CONSTANT c_BLM_thres_Base_Addr: Integer := 16#0700#; -- BLM thresholds for the counter pool: 512 16 bit registers--> + 200h CONSTANT c_BLM_in_sel_Base_Addr: Integer := 16#1000#; --BLM input mux select registers : 128 16 bit registers -->80h CONSTANT c_BLM_out_sel_Base_Addr: Integer := 16#1100#; --BLM output mux select registers : 130 16 bit registers -->82h - CONSTANT c_BLM_ctrl_Base_Addr: Integer := 16#1200#; --BLM control registers: 15 x 16 bit registers - + CONSTANT c_BLM_ctrl_Base_Addr: Integer := 16#1200#; --BLM control registers: 15 x 16 bit registers --7Fh + CONSTANT c_BLM_event_readout_Base_Addr: Integer := 16#1280#; --BLM event readout registers: 8 x 16 bit registers + CONSTANT c_BLM_event_ctrl_Base_Addr: Integer := 16#1288#; --BLM event control registers: 8 x 16 bit registers + CONSTANT c_BLM_counter_readout_Base_Addr: Integer := 16#1290#; --BLM counters readout registers: 256 x 16 bit registers + -- CONSTANT c_BLM_mem_thres_Base_Addr: Integer := 16#1390#; --BLM thresholds from local RAM : 512 x 16 bit registers + -- +============================================================================================================================+ -- | CONSTANT | @@ -402,38 +406,7 @@ port ); end component gate_deglitcher; - COMPONENT daq - generic ( - Base_addr: unsigned(15 downto 0); - CLK_sys_in_Hz: integer := 125_000_000; - ch_num: integer := 16 - ); - - port ( - Adr_from_SCUB_LA: in std_logic_vector(15 downto 0); - Data_from_SCUB_LA: in std_logic_vector(15 downto 0); - Ext_Adr_Val: in std_logic; - Ext_Rd_active: in std_logic; - Ext_Wr_active: in std_logic; - clk_i: in std_logic; - nReset: in std_logic; - - diob_extension_id: in std_logic_vector(15 downto 0); - - user_rd_active: out std_logic; - Rd_Port: out std_logic_vector(15 downto 0); - Dtack: out std_logic; - daq_srq: out std_logic; - HiRes_srq: out std_logic; - Timing_Pattern_LA: in std_logic_vector(31 downto 0); - Timing_Pattern_RCV: in std_logic; - - --daq input channels - daq_dat_i: in t_daq_dat (1 to ch_num); - daq_ext_trig: in t_daq_ctl (1 to ch_num) - ); - END COMPONENT daq; - + component Beam_Loss_check is generic ( @@ -468,8 +441,19 @@ port ( -- REg127 ex Reg121: counter outputs buffering enable (bit 15) and buffered output select (bit 7-0). Bits 14-8 not used -- OUT register -- BLM_status_Reg : out t_IO_Reg_0_to_25_Array ; + + + + ev_prepare_reg : in std_logic_vector(11 downto 0); + ev_recover_reg: in std_logic_vector(11 downto 0); + ev_counter_reset: in std_logic; + ev_thr_load: in std_logic; + virt_acc: in std_logic_vector(11 downto 0); + + BLM_status_Reg : out t_IO_Reg_0_to_29_Array ; + counter_readout_reg: out t_BLM_th_Array ; -- OUT BLM BLM_Out : out std_logic_vector(5 downto 0) ); @@ -620,11 +604,9 @@ port ( s_nLED_User3_i : out std_logic; --IOBP_Output_Readback : out t_IO_Reg_0_to_7_Array; --IOBP_Output_Readback : out std_logic_vector(15 downto 0); - Deb_Sync66 : out std_logic_vector(65 downto 0); - daq_dat : out t_daq_dat; - daq_diob_ID : out std_logic_vector(15 downto 0) - + Deb_Sync66 : out std_logic_vector(65 downto 0) + ); end component p_connector; @@ -674,6 +656,28 @@ component aw_io_reg end component aw_io_reg; +component event_ctrl_el is + + port( + clk : in std_logic; -- chip-internal pulsed clk signal + nRST : in std_logic; -- general reset signal + nEvent_Str : in std_logic; -- low active SCU_Bus runs timing cycle + A_Address: in std_logic_vector(15 downto 0); -- SCU-Adress Bus + A_Data: in std_logic_vector(15 downto 0); -- SCU-Data Bus (inout) + BLM_event_key_Reg : in std_logic_vector(15 downto 0); --mask in_data + BLM_event_ctrl_Reg : in std_logic_vector(15 downto 0); --config signals reg + + prepare_out: out std_logic_vector(11 downto 0); + recover_out: out std_logic_vector(11 downto 0); + reset_ctr_out: out std_logic; + load_thr_out: out std_logic; + reg_curr_data_set_by_ev: out std_logic_vector(11 downto 0); + BLM_event_readout_Reg : out t_IO_Reg_0_to_2_Array-- virt acc readed address + value + + + ); + end component event_ctrl_el; + -- +============================================================================================================================+ -- | signal | -- +============================================================================================================================+ @@ -991,19 +995,7 @@ signal BLM_gate_in : std_logic_vector(11 downto 0); signal BLM_Out : std_logic_vector(5 downto 0); signal BLM_deglitcher_data: std_logic_vector(65 downto 0); signal BLM_deg_gate_in: std_logic_vector(11 downto 0); ------------------DAQ-Signale--------------------------------------------------------------------------------------------------- - -constant daq_ch_num: integer := 16; -signal daq_diob_ID: std_logic_vector(15 downto 0):=x"00FF"; --hard-coded ID Value for DAQ Diob implementation of which bits 3-0 are used -signal daq_user_rd_active: std_logic; -signal daq_data_to_SCUB: std_logic_vector(15 downto 0);-- Data to SCU Bus Macro -signal daq_Dtack: std_logic; -- Dtack to SCU Bus Macro -signal daq_srq: std_logic; -- consolidated irq lines from n daq channels for "channel fifo full" -signal daq_HiRes_srq: std_logic; -- consolidated irq lines from n HiRes channels for "HiRes Daq finished" ---daq input channels signals -signal daq_dat: t_daq_dat (1 to daq_ch_num) := (others => dummy_daq_dat_in); -signal daq_ext_trig: t_daq_ctl (1 to daq_ch_num) := (others => dummy_daq_ctl_in); -------------------------------------------------------------------------------------------------------------------------------------- --for thresholds @@ -1049,10 +1041,40 @@ signal BLM_out_sel_res_Dtack : std_logic; signal IOBP_LED_sm_nr: std_logic_vector(3 downto 0); --- +---------------------------------------------------------- + -- for event and virtual accelerator +signal BLM_event_readout_Reg :t_IO_Reg_0_to_2_Array; +signal BLM_virt_acc_rd_Reg: std_logic_vector(15 downto 0); +signal BLM_event_v_acc_readout_rd_active: std_logic; +signal BLM_event_v_acc_readout_Dtack: std_logic; +signal BLM_event_v_acc_readout_data_to_SCUB: std_logic_vector(15 downto 0); + + +signal BLM_event_key_Reg:std_logic_vector(15 downto 0); +signal BLM_event_ctrl_Reg: std_logic_vector(15 downto 0); +signal BLM_mem_cmd_Reg: std_logic_vector(15 downto 0); +signal BLM_new_dataset_Reg: std_logic_vector(15 downto 0); + +signal BLM_event_v_acc_ctrl_rd_active: std_logic; +signal BLM_event_v_acc_ctrl_Dtack: std_logic; +signal BLM_event_v_acc_ctrl_data_to_SCUB: std_logic_vector(15 downto 0); +signal ev_cmd_prepare : std_logic_vector(11 downto 0); +signal ev_cmd_recover: std_logic_vector(11 downto 0); + +signal ev_cmd_reset_ctr: std_logic; +signal ev_cmd_load_thr: std_logic; +signal loaded_data_set: std_logic_vector(11 downto 0); +signal counter_readout_Reg: t_BLM_th_Array ; +signal counter_readout_active: std_logic_vector(31 downto 0); +signal counter_readout_Dtack: std_logic_vector(31 downto 0); +signal counter_readout_data_to_SCUB: t_IO_Reg_0_to_31_Array; +signal counter_readout_res_Dtack: std_logic; + constant ZERO_th: std_logic_vector(BLM_th_Dtack'range) := (others => '0'); constant ZERO_in_sel: std_logic_vector(BLM_in_sel_Dtack'range) := (others => '0'); constant ZERO_status_sel: std_logic_vector(IOBP_in_Dtack'range) := (others => '0'); constant ZERO_out_sel: std_logic_vector(BLM_out_sel_Dtack'range) := (others => '0'); +constant ZERO_cnt_readout_sel: std_logic_vector(counter_readout_Dtack'range) := (others => '0'); -- ############################################################################################################################### -- ############################################################################################################################### -- ##### ##### @@ -1679,7 +1701,7 @@ BLM_ctrl_Reg_1st_block: io_reg ); end generate BLM_out_sel_registers; - + BLM_o_sel_Reg_120_126: io_reg generic map( @@ -1702,7 +1724,7 @@ BLM_ctrl_Reg_1st_block: io_reg Reg_IO4 => BLM_out_sel_Reg(123), Reg_IO5 => BLM_out_sel_Reg(124), Reg_IO6 => BLM_out_sel_Reg(125), - Reg_IO7 => BLM_out_sel_Reg(126), + Reg_IO7 => open, Reg_IO8 => open, -- Reg_rd_active => BLM_out_sel_rd_active(15), @@ -1710,38 +1732,153 @@ BLM_ctrl_Reg_1st_block: io_reg Data_to_SCUB => BLM_out_sel_data_to_SCUB(15)); + -------------------------------------------------------------------- +BLM_event_v_acc_readout_Reg: in_reg +generic map( + Base_addr => c_BLM_event_readout_Base_Addr + ) +port map ( + Adr_from_SCUB_LA => ADR_from_SCUB_LA, + Data_from_SCUB_LA => Data_from_SCUB_LA, + Ext_Adr_Val => Ext_Adr_Val, + Ext_Rd_active => Ext_Rd_active, + Ext_Rd_fin => Ext_Rd_fin, + Ext_Wr_active => Ext_Wr_active, + Ext_Wr_fin => SCU_Ext_Wr_fin, + clk => clk_sys, + nReset => rstn_sys, +-- + Reg_In1 => BLM_event_readout_Reg(0), + Reg_In2 => BLM_event_readout_Reg(1), + Reg_In3 => BLM_event_readout_Reg(2), + Reg_In4 => BLM_virt_acc_rd_Reg, + Reg_In5 => (others =>'0'), + Reg_In6 => (others =>'0'), + Reg_In7 => (others =>'0'), + Reg_In8 => (others =>'0'), +-- + Reg_rd_active => BLM_event_v_acc_readout_rd_active, + Dtack_to_SCUB => BLM_event_v_acc_readout_Dtack, + Data_to_SCUB => BLM_event_v_acc_readout_data_to_SCUB + ); + + +BLM_event_v_acc_control_Reg: io_reg +generic map( + Base_addr => c_BLM_event_ctrl_Base_Addr +) +port map ( + Adr_from_SCUB_LA => ADR_from_SCUB_LA, + Data_from_SCUB_LA => Data_from_SCUB_LA, + Ext_Adr_Val => Ext_Adr_Val, + Ext_Rd_active => Ext_Rd_active, + Ext_Rd_fin => Ext_Rd_fin, + Ext_Wr_active => Ext_Wr_active, + Ext_Wr_fin => SCU_Ext_Wr_fin, + clk => clk_sys, + nReset => rstn_sys, + + Reg_IO1 => BLM_event_key_Reg, + Reg_IO2 => BLM_event_ctrl_Reg, + Reg_IO3 => BLM_mem_cmd_Reg, + Reg_IO4 => BLM_new_dataset_Reg, + Reg_IO5 => open, + Reg_IO6 => open, + Reg_IO7 => open, + Reg_IO8 => open, + + Reg_rd_active => BLM_event_v_acc_ctrl_rd_active, + Dtack_to_SCUB => BLM_event_v_acc_ctrl_Dtack, + Data_to_SCUB => BLM_event_v_acc_ctrl_data_to_SCUB + ); + + + counters_readout_registers: for i in 0 to 31 generate + + counter_readout_Reg_module: in_reg + generic map( + Base_addr => c_BLM_counter_readout_Base_Addr + 8*i + ) + port map ( + Adr_from_SCUB_LA => ADR_from_SCUB_LA, + Data_from_SCUB_LA => Data_from_SCUB_LA, + Ext_Adr_Val => Ext_Adr_Val, + Ext_Rd_active => Ext_Rd_active, + Ext_Rd_fin => Ext_Rd_fin, + Ext_Wr_active => Ext_Wr_active, + Ext_Wr_fin => SCU_Ext_Wr_fin, + clk => clk_sys, + nReset => rstn_sys, - DAQ_modul: daq - GENERIC MAP( - Base_addr => to_unsigned(c_DIOB_DAQ_Base_Addr, 16), - CLK_sys_in_Hz => 125000000, - ch_num => daq_ch_num - ) - - PORT MAP ( - - Adr_from_SCUB_LA => ADR_from_SCUB_LA, - Data_from_SCUB_LA => Data_from_SCUB_LA, - Ext_Adr_Val => Ext_Adr_Val, - Ext_Rd_active => Ext_Rd_active, - Ext_Wr_active => Ext_Wr_active, - clk_i => clk_sys, - nReset => rstn_sys, - - diob_extension_id => daq_diob_ID, - user_rd_active => daq_user_rd_active, - Rd_Port => daq_data_to_SCUB, - Dtack => daq_Dtack, - daq_srq => daq_srq, - HiRes_srq => daq_HiRes_srq, - Timing_Pattern_LA => Timing_Pattern_LA, - Timing_Pattern_RCV => Timing_Pattern_RCV, - - --daq input channels - daq_dat_i => daq_dat, - daq_ext_trig => daq_ext_trig + Reg_In1 => counter_readout_Reg(4*i)(15 downto 0), + Reg_In2 => counter_readout_Reg(4*i)(31 downto 16), + Reg_In3 => counter_readout_Reg(4*i+1)(15 downto 0), + Reg_In4 => counter_readout_Reg(4*i+1)(31 downto 16), + Reg_In5 => counter_readout_Reg(4*i+2)(15 downto 0), + Reg_In6 => counter_readout_Reg(4*i+2)(31 downto 16), + Reg_In7 => counter_readout_Reg(4*i+3)(15 downto 0), + Reg_In8 => counter_readout_Reg(4*i+3)(31 downto 16), + -- + Reg_rd_active => counter_readout_active (i), + Dtack_to_SCUB => counter_readout_Dtack(i), + Data_to_SCUB => counter_readout_data_to_SCUB(i) + ); + end generate counters_readout_registers; + + -- RAM_threshold_registers: for i in 0 to 63 generate + + -- BLM_RAM_thr_Reg: io_reg + -- generic map( + -- Base_addr => c_BLM_mem_thres_Base_Addr + 8*i + -- ) + -- port map ( + -- Adr_from_SCUB_LA => ADR_from_SCUB_LA, + -- Data_from_SCUB_LA => Data_from_SCUB_LA, + -- Ext_Adr_Val => Ext_Adr_Val, + -- Ext_Rd_active => Ext_Rd_active, + -- Ext_Rd_fin => Ext_Rd_fin, + -- Ext_Wr_active => Ext_Wr_active, + -- Ext_Wr_fin => SCU_Ext_Wr_fin, + -- clk => clk_sys, + -- nReset => rstn_sys, + + -- Reg_IO1 => mem_pos_thres_Reg(2*i)(15 downto 0), + -- Reg_IO2 => mem_pos_thres_Reg(2*i)(31 downto 16), + -- Reg_IO3 => mem_neg_thres_Reg(2*i)(15 downto 0), + -- Reg_IO4 => mem_neg_thres_Reg(2*i)(31 downto 16), + -- Reg_IO5 => mem_pos_thres_Reg(2*i+1)(15 downto 0), + -- Reg_IO6 => mem_pos_thres_Reg(2*i+1)(31 downto 16), + -- Reg_IO7 => mem_neg_thres_Reg(2*i+1)(15 downto 0), + -- Reg_IO8 => mem_neg_thres_Reg(2*i+1)(31 downto 16), + -- + -- Reg_rd_active => BLM_mem th_active (i), + -- Dtack_to_SCUB => BLM_mem_th_Dtack(i), + -- Data_to_SCUB => BLM__memth_data_to_SCUB(i) + -- ); + -- end generate threshold_registers; + + + Event_Timestamping_module: event_ctrl_el + + port map( + clk => clk_sys, + nRST => rstn_sys, + nEvent_Str => A_nEvent_Str, + A_Address=> A_A, + A_Data => A_D, + BLM_event_key_Reg => BLM_event_key_Reg, + prepare_out => ev_cmd_prepare, + recover_out => ev_cmd_recover, + reset_ctr_out => ev_cmd_reset_ctr, + load_thr_out => ev_cmd_load_thr, + reg_curr_data_set_by_ev => loaded_data_set, + BLM_event_ctrl_Reg => BLM_event_ctrl_Reg, + + + BLM_event_readout_Reg => BLM_event_readout_Reg ); - + + testport_mux: process (A_SEL, AW_Config1, AW_Input_Reg, AW_Output_Reg, LA_Tag_Ctrl1, LA_AW_Port1, LA_Conf_Sts1, Timing_Pattern_RCV, Timing_Pattern_LA, test_port_in_0, test_clocks, uart_txd_out, @@ -1905,11 +2042,7 @@ port map ( nSCUB_Reset_in => A_nReset, -- in, SCU_Bus-Signal: '0' => 'nSCUB_Reset_in' is active Data_to_SCUB => Data_to_SCUB, -- in, connect read sources from external user functions Dtack_to_SCUB => Dtack_to_SCUB, -- in, connect Dtack from from external user functions - intr_in => '0'& '0' & tmr_irq & daq_srq -- bit 15..12 - & daq_HiRes_srq & '0' & '0' &'0' -- bit 11..8 - - & x"0" -- bit 7..4 - & '0' & '0' & clk_switch_intr, -- bit 3..1 + intr_in =>"00" & tmr_irq & "00000000000"& clk_switch_intr, User_Ready => '1', CID_GROUP => 26, -- important: => "FG900500_SCU_Diob1" extension_cid_system => extension_cid_system, -- in, extension card: cid_system @@ -1996,28 +2129,30 @@ port map ( Data_to_SCUB => tmr_data_to_SCUB, Dtack_to_SCUB => tmr_dtack); -rd_port_mux: process ( clk_switch_rd_active, clk_switch_rd_data, - wb_scu_rd_active, wb_scu_data_to_SCUB, - Tag_Ctrl1_rd_active, Tag_Ctrl1_data_to_SCUB, - Conf_Sts1_rd_active, Conf_Sts1_data_to_SCUB, - tmr_rd_active, tmr_data_to_SCUB, - AW_Port1_rd_active, AW_Port1_data_to_SCUB, - IOBP_msk_rd_active, IOBP_msk_data_to_SCUB, - IOBP_id_rd_active, IOBP_id_data_to_SCUB, - IOBP_in_rd_active, IOBP_in_data_to_SCUB, - daq_user_rd_active, daq_data_to_SCUB, - BLM_ctrl_rd_active, BLM_ctrl_data_to_SCUB, - BLM_th_active, BLM_th_data_to_SCUB, - BLM_in_sel_rd_active, BLM_in_sel_data_to_SCUB +rd_port_mux: process ( clk_switch_rd_active, clk_switch_rd_data, + wb_scu_rd_active, wb_scu_data_to_SCUB, + Tag_Ctrl1_rd_active, Tag_Ctrl1_data_to_SCUB, + Conf_Sts1_rd_active, Conf_Sts1_data_to_SCUB, + tmr_rd_active, tmr_data_to_SCUB, + AW_Port1_rd_active, AW_Port1_data_to_SCUB, + IOBP_msk_rd_active, IOBP_msk_data_to_SCUB, + IOBP_id_rd_active, IOBP_id_data_to_SCUB, + IOBP_in_rd_active, IOBP_in_data_to_SCUB, + BLM_ctrl_rd_active, BLM_ctrl_data_to_SCUB, + BLM_th_active, BLM_th_data_to_SCUB, + BLM_in_sel_rd_active, BLM_in_sel_data_to_SCUB, + BLM_event_v_acc_readout_rd_active, BLM_event_v_acc_readout_data_to_SCUB, + BLM_event_v_acc_ctrl_rd_active, BLM_event_v_acc_ctrl_data_to_SCUB, + counter_readout_active, counter_readout_data_to_SCUB ) - variable sel: unsigned(11 downto 0); + variable sel: unsigned(12 downto 0); variable sel_th: unsigned(63 downto 0); variable sel_in_sel: unsigned(15 downto 0); variable sel_st: unsigned(3 downto 0); variable sel_out_sel: unsigned(15 downto 0); - + variable sel_cnt_readout_sel: unsigned(31 downto 0); begin @@ -2025,25 +2160,28 @@ rd_port_mux: process ( clk_switch_rd_active, clk_switch_rd_data, sel_th:= unsigned (BLM_th_active); sel_st:= unsigned(IOBP_in_rd_active); sel_out_sel := unsigned(BLM_out_sel_rd_active); + sel_cnt_readout_sel := unsigned(counter_readout_active); - sel:= BLM_ctrl_rd_active(1)& BLM_ctrl_rd_active(1)&BLM_ctrl_rd_active(0) & daq_user_rd_active & + sel:= BLM_event_v_acc_readout_rd_active & BLM_event_v_acc_ctrl_rd_active& + BLM_ctrl_rd_active(2) & BLM_ctrl_rd_active(1)&BLM_ctrl_rd_active(0) & AW_Port1_rd_active & tmr_rd_active & wb_scu_rd_active & clk_switch_rd_active & Conf_Sts1_rd_active & Tag_Ctrl1_rd_active & IOBP_msk_rd_active & IOBP_id_rd_active ; -if to_integer(sel(11 downto 0))>0 then - case sel(11 downto 0) IS - when "100000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(2); - when "010000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(1); - when "001000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(0); - when "000100000000" => Data_to_SCUB <= daq_data_to_SCUB; - when "000010000000" => Data_to_SCUB <= AW_Port1_data_to_SCUB; - when "000001000000" => Data_to_SCUB <= tmr_data_to_SCUB; - when "000000100000" => Data_to_SCUB <= wb_scu_data_to_SCUB; - when "000000010000" => Data_to_SCUB <= clk_switch_rd_data; - when "000000001000" => Data_to_SCUB <= Conf_Sts1_data_to_SCUB; - when "000000000100" => Data_to_SCUB <= Tag_Ctrl1_data_to_SCUB; - when "000000000010" => Data_to_SCUB <= IOBP_msk_data_to_SCUB; - when "000000000001" => Data_to_SCUB <= IOBP_id_data_to_SCUB; +if to_integer(sel(12 downto 0))>0 then + case sel(12 downto 0) IS + when "1000000000000" => Data_to_SCUB <= BLM_event_v_acc_readout_data_to_SCUB; + when "0100000000000" => Data_to_SCUB <= BLM_event_v_acc_ctrl_data_to_SCUB; + when "0010000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(2); + when "0001000000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(1); + when "0000100000000" => Data_to_SCUB <= BLM_ctrl_data_to_SCUB(0); + when "0000010000000" => Data_to_SCUB <= AW_Port1_data_to_SCUB; + when "0000001000000" => Data_to_SCUB <= tmr_data_to_SCUB; + when "0000000100000" => Data_to_SCUB <= wb_scu_data_to_SCUB; + when "0000000010000" => Data_to_SCUB <= clk_switch_rd_data; + when "0000000001000" => Data_to_SCUB <= Conf_Sts1_data_to_SCUB; + when "0000000000100" => Data_to_SCUB <= Tag_Ctrl1_data_to_SCUB; + when "0000000000010" => Data_to_SCUB <= IOBP_msk_data_to_SCUB; + when "0000000000001" => Data_to_SCUB <= IOBP_id_data_to_SCUB; when others => Data_to_SCUB <= (others => '0'); end case; @@ -2075,7 +2213,14 @@ else Data_to_SCUB <= BLM_out_sel_data_to_SCUB(i); end if; end loop; - + else + if to_integer(sel_cnt_readout_sel) > 0 then + for i in 0 to 31 loop + if sel_cnt_readout_sel(i) = '1' then + Data_to_SCUB <= counter_readout_data_to_SCUB(i); + end if; + end loop; + else Data_to_SCUB <= (others =>'0'); end if; @@ -2083,7 +2228,7 @@ else end if; end if; end if; - +end if; end process rd_port_mux; ------------------------------------------------------ @@ -2119,12 +2264,18 @@ end if; if (IOBP_in_Dtack =ZERO_status_sel) then IOBP_in_res_Dtack <='0'; else IOBP_in_res_Dtack <='1'; end if; + + +if (counter_readout_Dtack =ZERO_cnt_readout_sel) then counter_readout_res_Dtack <='0'; +else counter_readout_res_Dtack <='1'; +end if; -------------- Dtack_to_SCUB ----------------------------- Dtack_to_SCUB <= ( tmr_dtack or AW_Port1_Dtack or wb_scu_dtack or clk_switch_dtack or Conf_Sts1_Dtack or Tag_Ctrl1_Dtack or - IOBP_msk_Dtack or IOBP_id_Dtack or IOBP_in_res_Dtack or daq_Dtack or - BLM_ctrl_Dtack(2) or BLM_ctrl_Dtack(1) or BLM_ctrl_Dtack(0) or BLM_th_res_Dtack or BLM_in_sel_res_Dtack or BLM_out_sel_res_Dtack); + IOBP_msk_Dtack or IOBP_id_Dtack or IOBP_in_res_Dtack or + BLM_ctrl_Dtack(2) or BLM_ctrl_Dtack(1) or BLM_ctrl_Dtack(0) or BLM_th_res_Dtack or BLM_in_sel_res_Dtack or BLM_out_sel_res_Dtack or + BLM_event_v_acc_readout_Dtack or BLM_event_v_acc_ctrl_Dtack or counter_readout_res_Dtack); A_nDtack <= NOT(SCUB_Dtack); A_nSRQ <= NOT(SCUB_SRQ); @@ -2255,8 +2406,21 @@ BLM_Module : Beam_Loss_check BLM_in_sel_Reg => BLM_in_sel_Reg, BLM_out_sel_reg => BLM_out_sel_Reg, +-- event_ctrl_sig + + +ev_counter_reset=> ev_cmd_reset_ctr, +ev_thr_load => ev_cmd_load_thr, +virt_acc => loaded_data_set, +ev_prepare_reg =>ev_cmd_prepare, +ev_recover_reg =>ev_cmd_recover, + + + + -- OUT register BLM_status_Reg => BLM_status_Reg, +counter_readout_reg => counter_readout_Reg, -- OUT BLM BLM_Out => BLM_out ); @@ -2470,9 +2634,7 @@ AW_B12s1_connection: p_connector s_nLED_User2_i => s_nLED_User2_i, s_nLED_User3_i => s_nLED_User3_i, --IOBP_Output_Readback => BLM_Status_Reg(0), - Deb_Sync66 => Deg_Sync66, - daq_dat => daq_dat, - daq_diob_ID => daq_diob_ID + Deb_Sync66 => Deg_Sync66 ); diff --git a/top/blm_aco/event_ctrl_el.vhd b/top/blm_aco/event_ctrl_el.vhd new file mode 100644 index 0000000000..648cf52fc0 --- /dev/null +++ b/top/blm_aco/event_ctrl_el.vhd @@ -0,0 +1,170 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.scu_diob_pkg.all; +use IEEE.std_logic_misc.all; + +entity event_ctrl_el is + +port( + clk : in std_logic; -- chip-internal pulsed clk signal + nRST : in std_logic; -- general reset signal + nEvent_Str : in std_logic; -- low active SCU_Bus runs timing cycle + A_Address: in std_logic_vector(15 downto 0); -- SCU-Adress Bus + A_Data: in std_logic_vector(15 downto 0); -- SCU-Data Bus (inout) + BLM_event_key_Reg : in std_logic_vector(15 downto 0); --mask in_data + BLM_event_ctrl_Reg : in std_logic_vector(15 downto 0); --config signals reg + + prepare_out: out std_logic_vector(11 downto 0); + recover_out: out std_logic_vector(11 downto 0); + reset_ctr_out: out std_logic; + load_thr_out: out std_logic; + reg_curr_data_set_by_ev: out std_logic_vector(11 downto 0); + BLM_event_readout_Reg : out t_IO_Reg_0_to_2_Array -- virt acc readed address + value + +); +end event_ctrl_el; + +architecture rtl of event_ctrl_el is +signal sync_str : std_logic; + + + + +type event_state_type is (idle, check_state, select_state, wait_state); +signal event_state: event_state_type; + + +signal prepare_sig: std_logic_vector(11 downto 0); +signal recover_sig: std_logic_vector(11 downto 0); +signal reset_ctr_sig: std_logic; +signal load_thr_sig: std_logic; +signal reg_curr_data_set_sig : std_logic_vector(11 downto 0); +signal data_value : std_logic_vector(15 downto 0); +signal data_value_del : std_logic_vector(15 downto 0); +signal latched_value : std_logic_vector(31 downto 0); +signal data_address : std_logic_vector(15 downto 0); +signal data_address_del : std_logic_vector(15 downto 0); +signal compare: std_logic; + + +signal sync_str_del: std_logic; +signal compare_vector: std_logic_vector(15 downto 0); +signal tag_code: std_logic_vector(15 downto 0); + +signal event_enable: std_logic; + + + +begin + + +event_sync_proc: process (clk, nRST) + begin + if not nRST='1' then + sync_str <='0'; + elsif (clk'EVENT AND clk= '1') then + sync_str_del <= not (nEvent_Str); + sync_str <= sync_str_del; + end if; +end process; + +events_processing: process(clk, nRST) +begin + if not nRST='1' then + + latched_value <= (others =>'0'); + tag_code <= (others =>'0'); + event_state <= idle; + prepare_sig <=(others =>'0'); + recover_sig <= (others =>'0'); + reset_ctr_sig <= '0'; + load_thr_sig <= '0'; + reg_curr_data_set_sig <= (others => '0'); + + event_enable <= '0'; + + elsif (clk'EVENT AND clk= '1') then + + data_address_del <= A_Address; + data_value_del <= A_Data; + data_address <= data_address_del; + data_value <= data_value_del; + event_enable <= BLM_event_ctrl_Reg(0); + case (event_state) is + when idle => + --for i in 31 to 16 loop + -- compare_vector(i) <= latched_value(i) XNOR BLM_event_key_Reg(i); + --end loop; + -- compare <= and_reduce (compare_vector); + if BLM_event_key_Reg = data_address then + compare <= '1'; + else + compare <= '0'; + end if; + -- if sync_str ='1' then + + if (sync_str = '1' and event_enable ='1') then + latched_value <= data_address & data_value; + event_state <= check_state; + end if; + + when check_state => + if compare = '1' then + event_state <= select_state; + tag_code <= latched_value(15 downto 0); + else + event_state <= wait_state; + end if; + + + when select_state => + + + case tag_code (15 downto 12) is + when "0001" => load_thr_sig <= '1'; + reg_curr_data_set_sig <= tag_code(11 downto 0); + + when "0010" => prepare_sig <= tag_code(11 downto 0); + + when "0011" => recover_sig <= tag_code(11 downto 0); + + when "0100" => reset_ctr_sig <= '1'; + + + when others => NULL; + + end case; + event_state <= wait_state; + + when wait_state => + prepare_sig <=(others =>'0'); + recover_sig <= (others =>'0'); + reset_ctr_sig <= '0'; + load_thr_sig <= '0'; + -- if sync_str ='0' then + if sync_str ='0' then + event_state <= idle; + + end if; + + + when others => null; + end case; + end if; +end process; + +BLM_event_readout_Reg(0) <= latched_value(15 downto 0); +BLM_event_readout_Reg(1) <= latched_value(31 downto 16); +BLM_event_readout_Reg (2) <= tag_code; +prepare_out <= prepare_sig; +recover_out<= recover_sig; +reset_ctr_out <= reset_ctr_sig; +load_thr_out<= load_thr_sig; +reg_curr_data_set_by_ev <= reg_curr_data_set_sig; + + + + + +end architecture rtl; \ No newline at end of file diff --git a/top/blm_aco/p_connector.vhd b/top/blm_aco/p_connector.vhd index ec9f8da8b4..b5c32db517 100644 --- a/top/blm_aco/p_connector.vhd +++ b/top/blm_aco/p_connector.vhd @@ -2,7 +2,6 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; use work.scu_diob_pkg.all; -use work.daq_pkg.all; entity p_connector is @@ -96,10 +95,7 @@ port( s_nLED_User3_i : out std_logic; --IOBP_Output_Readback : out t_IO_Reg_0_to_7_Array; --IOBP_Output_Readback : out std_logic_vector(15 downto 0); - Deb_Sync66 : out std_logic_vector(65 downto 0); - daq_dat : out t_daq_dat; - daq_diob_ID : out std_logic_vector(15 downto 0) - + Deb_Sync66 : out std_logic_vector(65 downto 0) ); end p_connector; @@ -449,13 +445,6 @@ Syn66(65 DOWNTO 60) <= not IOBP_Input( 11); Deb_Sync66 <= Deb66_out; -- Debounce und Synchronisation --END IF; ---------------------------------------------------------------------------------------------------------- - --################################ daq_channels assignments ################################## - - daq_dat(1)(5 downto 0) <= AW_Output_Reg(6)(11 downto 6); - daq_dat(1)(15 downto 6) <= (others => '0'); - daq_diob_ID(15 downto 0)<= "0000000000010011" ; --"00000000"& c_AW_INLB12S1.ID; ---############################################################################################################ else diff --git a/top/blm_aco/scu_diob_pkg.vhd b/top/blm_aco/scu_diob_pkg.vhd index 6e05e9a1d3..984a5273a5 100644 --- a/top/blm_aco/scu_diob_pkg.vhd +++ b/top/blm_aco/scu_diob_pkg.vhd @@ -2,8 +2,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library work; -use work.gencores_pkg.all; +--library work; +--use work.gencores_pkg.all; package scu_diob_pkg is @@ -26,17 +26,19 @@ package scu_diob_pkg is --TYPE t_BLM_wd_mux_sel_array is array (0 to 5) of std_logic_vector(5 downto 0); TYPE t_BLM_mux_reg_Array is array (0 to 5) of std_logic_vector(15 downto 0); --TYPE t_BLM_out_reg_Array is array (0 to 191) of std_logic_vector(15 downto 0); - TYPE t_BLM_out_sel_reg_Array is array (0 to 126) of std_logic_vector(15 downto 0); + TYPE t_BLM_out_sel_reg_Array is array (0 to 125) of std_logic_vector(15 downto 0); -- TYPE t_BLM_reg_Array is array (natural range <>) of std_logic_vector(15 downto 0); -TYPE t_IO_Reg_0_to_25_Array is array(0 to 25) of std_logic_vector(15 downto 0); + TYPE t_IO_Reg_0_to_25_Array is array(0 to 25) of std_logic_vector(15 downto 0); TYPE t_IO_Reg_0_to_27_Array is array (0 to 27) of std_logic_vector(15 downto 0); - TYPE t_BLM_gate_hold_Time_Array is array (0 to 11) of std_logic_vector(15 downto 0); + TYPE t_BLM_gate_hold_Time_Array is array (0 to 11) of std_logic_vector(15 downto 0); TYPE t_IO_Reg_0_to_15_Array is array (0 to 15) of std_logic_vector(15 downto 0); - TYPE t_IO_Reg_0_to_3_Array is array (0 to 3) of std_logic_vector(15 downto 0); - TYPE t_IO_Reg_0_to_8_Array is array (0 to 8) of std_logic_vector(15 downto 0); - TYPE t_IO_Reg_0_to_32_Array is array (0 to 32) of std_logic_vector(15 downto 0); - TYPE t_BLM_in_sel_Array is array (0 to 15) of std_logic_vector(15 downto 0); - TYPE t_BLM_counter_Array is array (0 to 127) of std_logic_vector(29 downto 0); - TYPE t_gate_state_nr is array (0 to 11) of std_logic_vector(2 downto 0); - TYPE t_IO_Reg_0_to_29_Array is array(0 to 29) of std_logic_vector(15 downto 0); + TYPE t_IO_Reg_0_to_3_Array is array (0 to 3) of std_logic_vector(15 downto 0); + TYPE t_IO_Reg_0_to_8_Array is array (0 to 8) of std_logic_vector(15 downto 0); + TYPE t_IO_Reg_0_to_32_Array is array (0 to 32) of std_logic_vector(15 downto 0); + TYPE t_BLM_in_sel_Array is array (0 to 15) of std_logic_vector(15 downto 0); + TYPE t_BLM_counter_Array is array (0 to 127) of std_logic_vector(31 downto 0); + TYPE t_gate_state_nr is array (0 to 11) of std_logic_vector(2 downto 0); + TYPE t_IO_Reg_0_to_29_Array is array(0 to 29) of std_logic_vector(15 downto 0); + TYPE t_IO_Reg_0_to_1_Array is array (0 to 1) of std_logic_vector(15 downto 0); + TYPE t_IO_Reg_0_to_31_Array is array (0 to 31) of std_logic_vector(15 downto 0); end scu_diob_pkg; diff --git a/top/blm_aco/thr_load_el.vhd b/top/blm_aco/thr_load_el.vhd new file mode 100644 index 0000000000..e69de29bb2 diff --git a/top/blm_aco/up_down_counter.vhd b/top/blm_aco/up_down_counter.vhd index 24a9241e2e..83cc155196 100644 --- a/top/blm_aco/up_down_counter.vhd +++ b/top/blm_aco/up_down_counter.vhd @@ -6,7 +6,7 @@ USE IEEE.numeric_std.all; entity up_down_counter is generic ( --c : integer :=1; -- Counter_input width - WIDTH : integer := 30 -- Counter width + WIDTH : integer := 32 -- Counter width ); @@ -96,11 +96,11 @@ begin elsif ( ENABLE = '1') then ---------------------------- - if up_input ='1' then + if (up_input ='1') and (down_input ='0') then int_count <= int_count +1; - elsif down_input ='1' then + elsif (down_input ='1') and (up_input ='0') then int_count <= int_count -1; From 48d36b5ec16991571d9221afabf6a1fdbc426b01 Mon Sep 17 00:00:00 2001 From: Antonietta Russo Date: Wed, 31 Jul 2024 13:56:32 +0200 Subject: [PATCH 2/2] BLM qsf file --- syn/blm_aco/blm_aco.qsf | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/syn/blm_aco/blm_aco.qsf b/syn/blm_aco/blm_aco.qsf index e5c9ad5053..35ca63d8bc 100644 --- a/syn/blm_aco/blm_aco.qsf +++ b/syn/blm_aco/blm_aco.qsf @@ -234,6 +234,9 @@ + + + @@ -740,9 +743,13 @@ set_global_assignment -name VHDL_FILE ../../modules/daq/daq.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/daq/Zeitbasis_daq.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE ../../modules/diob/del_quench_detection.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/diob/hw_interlock.vhd -library work +set_global_assignment -name VHDL_FILE ../../modules/diob/QuD_masken_reg.vhd -library work +set_global_assignment -name VHDL_FILE ../../modules/diob/qud_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/diob/quench_detection.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/diob/spill_abort.vhd -library work +set_global_assignment -name VHDL_FILE ../../modules/diob/TM_quench_detection.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto.vhd -library work set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag.vhd -library work @@ -918,7 +925,7 @@ set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_ctrl.vhd -libra set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_n.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_timeout.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/aw_io_reg.vhd -library work -set_global_assignment -name VHDL_FILE ../../top/blm_aco/Beam_Loss_check_v1.2.vhd -library work +set_global_assignment -name VHDL_FILE ../../top/blm_aco/Beam_Loss_check_v2.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_24_9_9_9pll.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_aco_v1.0.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_cnt_pulse_former.vhd -library work @@ -932,6 +939,7 @@ set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_watchdog_v1.0.vhd -l set_global_assignment -name VHDL_FILE ../../top/blm_aco/config_status.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_debounce.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_sync.vhd -library work +set_global_assignment -name VHDL_FILE ../../top/blm_aco/event_ctrl_el.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/fg901040.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/flanke.vhd -library work set_global_assignment -name VHDL_FILE ../../top/blm_aco/front_board_id_v0.vhd -library work