WIP

Grarak · Nov 20, 2024 · 9f8c0c1 · 9f8c0c1
1 parent dacdb66
commit 9f8c0c1
Show file tree

Hide file tree

Showing 2 changed files with 43 additions and 41 deletions.
diff --git a/src/core/memory/mem.rs b/src/core/memory/mem.rs
@@ -65,6 +65,31 @@ impl Memory {
         }
     }
 
+    pub fn get_shm_offset<const CPU: CpuType, const TCM: bool, const WRITE: bool>(&self, addr: u32) -> usize {
+        let mmu = {
+            let mmu = get_mem_mmu!(self, CPU);
+            if CPU == ARM9 && TCM {
+                if WRITE {
+                    mmu.get_mmu_write_tcm()
+                } else {
+                    mmu.get_mmu_read_tcm()
+                }
+            } else if WRITE {
+                mmu.get_mmu_write()
+            } else {
+                mmu.get_mmu_read()
+            }
+        };
+
+        let shm_offset = unsafe { *mmu.get_unchecked((addr as usize) >> MMU_PAGE_SHIFT) };
+        if shm_offset != 0 {
+            let offset = (addr as usize) & (MMU_PAGE_SIZE - 1);
+            shm_offset + offset
+        } else {
+            0
+        }
+    }
+
     pub fn read<const CPU: CpuType, T: Convert>(&mut self, addr: u32, emu: &mut Emu) -> T {
         self.read_with_options::<CPU, true, T>(addr, emu)
     }
@@ -78,19 +103,9 @@ impl Memory {
         let aligned_addr = addr & !(size_of::<T>() as u32 - 1);
         let aligned_addr = aligned_addr & 0x0FFFFFFF;
 
-        let mmu = {
-            let mmu = get_mem_mmu!(self, CPU);
-            if CPU == ARM9 && TCM {
-                mmu.get_mmu_read_tcm()
-            } else {
-                mmu.get_mmu_read()
-            }
-        };
-
-        let shm_offset = unsafe { *mmu.get_unchecked((aligned_addr as usize) >> MMU_PAGE_SHIFT) };
+        let shm_offset = self.get_shm_offset::<CPU, TCM, false>(aligned_addr);
         if shm_offset != 0 {
-            let offset = aligned_addr & (MMU_PAGE_SIZE as u32 - 1);
-            return utils::read_from_mem(&self.shm, shm_offset as u32 + offset);
+            return utils::read_from_mem(&self.shm, shm_offset as u32);
         }
 
         let addr_base = aligned_addr & 0x0F000000;
@@ -180,19 +195,9 @@ impl Memory {
         let aligned_addr = addr & !(size_of::<T>() as u32 - 1);
         let aligned_addr = aligned_addr & 0x0FFFFFFF;
 
-        let mmu = {
-            let mmu = get_mem_mmu!(self, CPU);
-            if CPU == ARM9 && TCM {
-                mmu.get_mmu_write_tcm()
-            } else {
-                mmu.get_mmu_write()
-            }
-        };
-
-        let shm_offset = unsafe { *mmu.get_unchecked((aligned_addr as usize) >> MMU_PAGE_SHIFT) };
+        let shm_offset = self.get_shm_offset::<CPU, TCM, true>(aligned_addr);
         if shm_offset != 0 {
-            let offset = aligned_addr & (MMU_PAGE_SIZE as u32 - 1);
-            utils::write_to_mem(&mut self.shm, shm_offset as u32 + offset, value);
+            utils::write_to_mem(&mut self.shm, shm_offset as u32, value);
             return;
         }
 

diff --git a/src/jit/inst_mem_handler.rs b/src/jit/inst_mem_handler.rs
@@ -111,24 +111,21 @@ mod handler {
         } else {
             ThreadRegs::get_reg_mut
         };
-
-        for i in Reg::R0 as u8..Reg::CPSR as u8 {
-            let reg = Reg::from(i);
-            if unlikely(rlist.is_reserved(reg)) {
-                if PRE {
-                    addr += 4;
-                }
-                if WRITE {
-                    let value = *get_reg_fun(get_regs_mut!(emu, CPU), reg);
-                    emu.mem_write::<CPU, _>(addr, value);
-                } else {
-                    let value = emu.mem_read::<CPU, _>(addr);
-                    *get_reg_fun(get_regs_mut!(emu, CPU), reg) = value;
-                }
-                if !PRE {
-                    addr += 4;
-                }
+
+        for reg in rlist {
+            if PRE {
+                addr += 4;
+            }
+            if WRITE {
+                let value = *get_reg_fun(get_regs_mut!(emu, CPU), reg);
+                emu.mem_write::<CPU, _>(addr, value);
+            } else {
+                let value = emu.mem_read::<CPU, _>(addr);
+                *get_reg_fun(get_regs_mut!(emu, CPU), reg) = value;
             }
+            if !PRE {
+                addr += 4;
+            }   
         }
 
         if WRITE_BACK && (WRITE || (CPU == CpuType::ARM9 && unlikely((rlist.0 & !((1 << (op0 as u8 + 1)) - 1)) != 0 || (rlist.0 == (1 << op0 as u8))))) {