cpldfit: version P.40xd Xilinx Inc. Fitter Report Design Name: gz_ppm Date: 1-30-2015, 9:22AM Device Used: XC9572XL-10-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 66 /72 ( 92%) 239 /360 ( 66%) 116/216 ( 54%) 46 /72 ( 64%) 15 /34 ( 44%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 32/54 66/90 7/ 9 FB2 18/18* 28/54 73/90 4/ 9 FB3 17/18 24/54 49/90 0/ 9 FB4 13/18 32/54 51/90 4/ 6 ----- ----- ----- ----- 66/72 116/216 239/360 15/33 * - Resource is exhausted ** Global Control Resources ** Signal 'ppm_clk_i' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 3 3 | I/O : 14 28 Output : 11 11 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 15 15 ** Power Data ** There are 66 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'gz_ppm.ise'. ************************* Summary of Mapped Logic ************************ ** 11 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State pwms_o<0> 1 7 FB1_5 2~ I/O O STD FAST pwms_o<1> 1 7 FB1_6 3~ I/O O STD FAST pwms_o<2> 1 7 FB1_8 4~ I/O O STD FAST pwms_o<3> 1 7 FB1_15 8~ I/O O STD FAST pwms_o<4> 1 7 FB1_17 9~ I/O O STD FAST pwms_o<5> 1 7 FB2_2 35~ I/O O STD FAST pwms_o<6> 1 7 FB2_5 36~ I/O O STD FAST pwms_o<7> 1 7 FB2_6 37~ I/O O STD FAST ppm_irq_o 3 3 FB2_8 38~ I/O O STD FAST RESET sync_o 5 8 FB4_2 25~ I/O O STD FAST RESET miso_o 17 21 FB4_17 34 I/O O STD FAST ** 55 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State sync_cmp_eq0000/sync_cmp_eq0000_D2 1 16 FB1_1 STD pulse_width<8> 4 8 FB1_2 STD RESET pulse_width<5> 4 7 FB1_3 STD RESET pulse_width<3> 4 8 FB1_4 STD RESET pulse_width<11> 4 8 FB1_7 STD RESET output_register<5> 5 12 FB1_9 STD RESET output_register<3> 5 13 FB1_10 STD RESET output_register<1> 5 10 FB1_11 STD RESET output_register<0> 5 9 FB1_12 STD RESET output_register<6> 6 10 FB1_13 STD RESET output_register<4> 6 10 FB1_14 STD RESET output_register<2> 6 11 FB1_16 STD RESET Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 6 11 FB1_18 STD reset 11 17 FB2_1 STD RESET channel_counter<2> 6 8 FB2_3 STD RESET channel_counter<3> 6 8 FB2_4 STD RESET output_register<10> 6 11 FB2_7 STD RESET output_register<7> 6 11 FB2_9 STD RESET output_register<9> 6 10 FB2_10 STD RESET channel_counter<1> 5 7 FB2_11 STD RESET output_register<11> 5 13 FB2_12 STD RESET output_register<8> 5 13 FB2_13 STD RESET channel_counter<0> 3 6 FB2_14 STD RESET irq_assert 2 6 FB2_15 STD RESET output_register<12> 2 6 FB2_16 STD RESET output_register<13> 2 6 FB2_17 STD RESET output_register<14> 2 6 FB2_18 STD RESET ppm_irq_o_OBUF/ppm_irq_o_OBUF_RSTF 1 2 FB3_2 STD Q1 1 1 FB3_3 STD RESET Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 1 5 FB3_4 STD Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 1 5 FB3_5 STD Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 1 4 FB3_6 STD Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 1 5 FB3_7 STD BUF_irq_deassert 1 3 FB3_8 STD Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 2 6 FB3_9 STD BUF_ppm 2 5 FB3_10 STD pulse_width<1> 4 5 FB3_11 STD RESET pulse_width<0> 4 4 FB3_12 STD RESET pulse_width<9> 5 5 FB3_13 STD RESET pulse_width<7> 5 6 FB3_14 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State pulse_width<6> 5 5 FB3_15 STD RESET pulse_width<4> 5 5 FB3_16 STD RESET pulse_width<2> 5 6 FB3_17 STD RESET pulse_width<10> 5 6 FB3_18 STD RESET pulse_width<13> 5 5 FB4_1 STD RESET ppm 1 1 FB4_6 STD RESET irq_deassert 1 1 FB4_7 STD RESET Q0 1 1 FB4_8 STD RESET Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 1 3 FB4_9 STD bit_cnt<0> 2 2 FB4_10 STD SET bit_cnt<3> 3 5 FB4_11 STD SET bit_cnt<2> 3 4 FB4_12 STD SET bit_cnt<1> 3 3 FB4_13 STD SET pulse_width<12> 4 6 FB4_14 STD RESET pulse_width<14> 5 6 FB4_15 STD RESET ** 4 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use ppm_i FB1_2 1~ I/O I ppm_clk_i FB1_9 5 GCK/I/O GCK sclk_i FB4_11 28 I/O I sel_i FB4_15 33 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use sync_cmp_eq0000/sync_cmp_eq0000_D2 1 0 /\1 3 FB1_1 (b) (b) pulse_width<8> 4 0 0 1 FB1_2 1 I/O I pulse_width<5> 4 0 0 1 FB1_3 (b) (b) pulse_width<3> 4 0 0 1 FB1_4 (b) (b) pwms_o<0> 1 0 0 4 FB1_5 2~ I/O O pwms_o<1> 1 0 0 4 FB1_6 3~ I/O O pulse_width<11> 4 0 0 1 FB1_7 (b) (b) pwms_o<2> 1 0 0 4 FB1_8 4~ I/O O output_register<5> 5 0 0 0 FB1_9 5 GCK/I/O GCK output_register<3> 5 0 0 0 FB1_10 (b) (b) output_register<1> 5 0 0 0 FB1_11 6 GCK/I/O (b) output_register<0> 5 0 0 0 FB1_12 (b) (b) output_register<6> 6 1<- 0 0 FB1_13 (b) (b) output_register<4> 6 2<- /\1 0 FB1_14 7 GCK/I/O (b) pwms_o<3> 1 0 /\2 2 FB1_15 8~ I/O O output_register<2> 6 1<- 0 0 FB1_16 (b) (b) pwms_o<4> 1 0 /\1 3 FB1_17 9~ I/O O Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 6 1<- 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: BUF_irq_deassert 12: channel_counter<2> 23: pulse_width<3> 2: BUF_ppm 13: channel_counter<3> 24: pulse_width<4> 3: Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 14: ppm_i 25: pulse_width<5> 4: Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 15: pulse_width<0> 26: pulse_width<6> 5: Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 16: pulse_width<10> 27: pulse_width<7> 6: Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 17: pulse_width<11> 28: pulse_width<8> 7: Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 18: pulse_width<12> 29: pulse_width<9> 8: Q0 19: pulse_width<13> 30: reset 9: Q1 20: pulse_width<14> 31: sync_cmp_eq0000/sync_cmp_eq0000_D2 10: channel_counter<0> 21: pulse_width<1> 32: sync_o 11: channel_counter<1> 22: pulse_width<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs sync_cmp_eq0000/sync_cmp_eq0000_D2 X.............XXXXXXXXXXXXXXX........... 16 pulse_width<8> XX.XX....................XXX..X......... 8 pulse_width<5> XXXX...................XX.....X......... 7 pulse_width<3> XXX...........X.....XXX.......X......... 8 pwms_o<0> .........XXXXX...............X.X........ 7 pwms_o<1> .........XXXXX...............X.X........ 7 pulse_width<11> XX..XX.........XX...........X.X......... 8 pwms_o<2> .........XXXXX...............X.X........ 7 output_register<5> XXXX...XX...XX.........XX....XX......... 12 output_register<3> XXX....XX...XXX.....XXX......XX......... 13 output_register<1> XX.....XX...XXX.....X........XX......... 10 output_register<0> XX.....XX...XXX..............XX......... 9 output_register<6> XX.X...XX...XX...........X...XX......... 10 output_register<4> XXX....XX...XX.........X.....XX......... 10 pwms_o<3> .........XXXXX...............X.X........ 7 output_register<2> XX.....XX...XXX.....XX.......XX......... 11 pwms_o<4> .........XXXXX...............X.X........ 7 Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 X..X.XX........XXX.......XXXX........... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use reset 11 6<- 0 0 FB2_1 (b) (b) pwms_o<5> 1 0 /\4 0 FB2_2 35~ I/O O channel_counter<2> 6 1<- 0 0 FB2_3 (b) (b) channel_counter<3> 6 2<- /\1 0 FB2_4 (b) (b) pwms_o<6> 1 0 /\2 2 FB2_5 36~ I/O O pwms_o<7> 1 0 \/1 3 FB2_6 37~ I/O O output_register<10> 6 1<- 0 0 FB2_7 (b) (b) ppm_irq_o 3 0 \/2 0 FB2_8 38~ I/O O output_register<7> 6 2<- \/1 0 FB2_9 39 GSR/I/O (b) output_register<9> 6 1<- 0 0 FB2_10 (b) (b) channel_counter<1> 5 0 0 0 FB2_11 40 GTS/I/O (b) output_register<11> 5 0 0 0 FB2_12 (b) (b) output_register<8> 5 0 0 0 FB2_13 (b) (b) channel_counter<0> 3 0 0 2 FB2_14 42 GTS/I/O (b) irq_assert 2 0 0 3 FB2_15 43 I/O (b) output_register<12> 2 0 0 3 FB2_16 (b) (b) output_register<13> 2 0 0 3 FB2_17 44 I/O (b) output_register<14> 2 0 \/2 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: BUF_irq_deassert 11: channel_counter<1> 20: pulse_width<13> 2: BUF_ppm 12: channel_counter<2> 21: pulse_width<14> 3: Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 13: channel_counter<3> 22: pulse_width<6> 4: Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 14: irq_assert 23: pulse_width<7> 5: Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 15: ppm_i 24: pulse_width<8> 6: Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 16: ppm_irq_o_OBUF/ppm_irq_o_OBUF_RSTF 25: pulse_width<9> 7: Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 17: pulse_width<10> 26: reset 8: Q0 18: pulse_width<11> 27: sync_cmp_eq0000/sync_cmp_eq0000_D2 9: Q1 19: pulse_width<12> 28: sync_o 10: channel_counter<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs reset XXX.XXX.........XXXXXXXXXXX............. 17 pwms_o<5> .........XXXX.X..........X.X............ 7 channel_counter<2> .......XXXXXX.X..........X.............. 8 channel_counter<3> .......XXXXXX.X..........X.............. 8 pwms_o<6> .........XXXX.X..........X.X............ 7 pwms_o<7> .........XXXX.X..........X.X............ 7 output_register<10> XX.X...XX...X.X.X.......XXX............. 11 ppm_irq_o .............X.X...........X............ 3 output_register<7> XXX....XX...X.X......XX..XX............. 11 output_register<9> XX.X...XX...X.X.........XXX............. 10 channel_counter<1> .......XXXX.X.X..........X.............. 7 output_register<11> XX.XX..XX...X.X.XX......XXX............. 13 output_register<8> XXXX...XX...X.X......XXX.XX............. 13 channel_counter<0> .......XXX..X.X..........X.............. 6 irq_assert .......XX...XXX..........X.............. 6 output_register<12> .......XXX..X.X..........X.............. 6 output_register<13> .......XX.X.X.X..........X.............. 6 output_register<14> .......XX..XX.X..........X.............. 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 24/30 Number of signals used by logic mapping into function block: 24 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) ppm_irq_o_OBUF/ppm_irq_o_OBUF_RSTF 1 0 0 4 FB3_2 11 I/O (b) Q1 1 0 0 4 FB3_3 (b) (b) Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 1 0 0 4 FB3_4 (b) (b) Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 1 0 0 4 FB3_5 12 I/O (b) Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 1 0 0 4 FB3_6 (b) (b) Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 1 0 0 4 FB3_7 (b) (b) BUF_irq_deassert 1 0 0 4 FB3_8 13 I/O (b) Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 2 0 0 3 FB3_9 14 I/O (b) BUF_ppm 2 0 0 3 FB3_10 (b) (b) pulse_width<1> 4 0 0 1 FB3_11 18 I/O (b) pulse_width<0> 4 0 0 1 FB3_12 (b) (b) pulse_width<9> 5 0 0 0 FB3_13 (b) (b) pulse_width<7> 5 0 0 0 FB3_14 19 I/O (b) pulse_width<6> 5 0 0 0 FB3_15 20 I/O (b) pulse_width<4> 5 0 0 0 FB3_16 24 I/O (b) pulse_width<2> 5 0 0 0 FB3_17 22 I/O (b) pulse_width<10> 5 0 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: BUF_irq_deassert 9: ppm 17: pulse_width<4> 2: BUF_ppm 10: ppm_i 18: pulse_width<5> 3: Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 11: pulse_width<0> 19: pulse_width<6> 4: Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 12: pulse_width<10> 20: pulse_width<7> 5: Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 13: pulse_width<11> 21: pulse_width<8> 6: Q0 14: pulse_width<1> 22: pulse_width<9> 7: Q1 15: pulse_width<2> 23: sel_i 8: irq_deassert 16: pulse_width<3> 24: sync_cmp_eq0000/sync_cmp_eq0000_D2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ppm_irq_o_OBUF/ppm_irq_o_OBUF_RSTF .......X..............X................. 2 Q1 .....X.................................. 1 Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 X...X......XX........X.................. 5 Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 X..X..............XXX................... 5 Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 X.X.............XX...................... 4 Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 X.........X..XXX........................ 5 BUF_irq_deassert .....XX..X.............................. 3 Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 X.X............XXXX..................... 6 BUF_ppm X....XX.XX.............................. 5 pulse_width<1> XX........X..X.........X................ 5 pulse_width<0> XX........X............X................ 4 pulse_width<9> XX..X................X.X................ 5 pulse_width<7> XX.X..............XX...X................ 6 pulse_width<6> XX.X..............X....X................ 5 pulse_width<4> XXX.............X......X................ 5 pulse_width<2> XX........X..XX........X................ 6 pulse_width<10> XX..X......X.........X.X................ 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use pulse_width<13> 5 0 0 0 FB4_1 (b) (b) sync_o 5 0 0 0 FB4_2 25~ I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 26 I/O ppm 1 0 0 4 FB4_6 (b) (b) irq_deassert 1 0 0 4 FB4_7 (b) (b) Q0 1 0 0 4 FB4_8 27 I/O (b) Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 1 0 0 4 FB4_9 (b) (b) bit_cnt<0> 2 0 0 3 FB4_10 (b) (b) bit_cnt<3> 3 0 0 2 FB4_11 28 I/O I bit_cnt<2> 3 0 0 2 FB4_12 (b) (b) bit_cnt<1> 3 0 \/1 1 FB4_13 (b) (b) pulse_width<12> 4 1<- \/2 0 FB4_14 (b) (b) pulse_width<14> 5 2<- \/2 0 FB4_15 33 I/O I (unused) 0 0 \/5 0 FB4_16 (b) (b) miso_o 17 12<- 0 0 FB4_17 34 I/O O (unused) 0 0 /\5 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: BUF_irq_deassert 12: output_register<11> 23: output_register<8> 2: BUF_ppm 13: output_register<12> 24: output_register<9> 3: Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 14: output_register<13> 25: ppm_i 4: Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 15: output_register<14> 26: pulse_width<12> 5: Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 16: output_register<1> 27: pulse_width<13> 6: bit_cnt<0> 17: output_register<2> 28: pulse_width<14> 7: bit_cnt<1> 18: output_register<3> 29: sclk_i 8: bit_cnt<2> 19: output_register<4> 30: sel_i 9: bit_cnt<3> 20: output_register<5> 31: sync_cmp_eq0000/sync_cmp_eq0000_D2 10: output_register<0> 21: output_register<6> 32: sync_o 11: output_register<10> 22: output_register<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs pulse_width<13> XX.X......................X...X......... 5 sync_o XX.XX.....................XX..XX........ 8 ppm .X...................................... 1 irq_deassert X....................................... 1 Q0 ........................X............... 1 Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 X.X......................X.............. 3 bit_cnt<0> ............................XX.......... 2 bit_cnt<3> .....XXX....................XX.......... 5 bit_cnt<2> .....XX.....................XX.......... 4 bit_cnt<1> .....X......................XX.......... 3 pulse_width<12> XXXX.....................X....X......... 6 pulse_width<14> XX.X......................XX..X......... 6 miso_o .....XXXXXXXXXXXXXXXXXXXX....X.......... 21 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** BUF_irq_deassert <= (ppm_i AND Q0 AND NOT Q1); BUF_ppm <= ((NOT ppm AND NOT BUF_irq_deassert) OR (NOT ppm_i AND NOT Q0 AND Q1 AND NOT BUF_irq_deassert)); Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 <= (pulse_width(0) AND pulse_width(1) AND pulse_width(2) AND pulse_width(3) AND NOT BUF_irq_deassert); Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 <= (pulse_width(4) AND pulse_width(5) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2); Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 <= (pulse_width(6) AND pulse_width(7) AND pulse_width(8) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2); Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 <= (pulse_width(10) AND pulse_width(11) AND pulse_width(9) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2); Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 <= (pulse_width(12) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2); Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 <= ((pulse_width(3) AND NOT pulse_width(4) AND pulse_width(5) AND pulse_width(6) AND NOT BUF_irq_deassert) OR (pulse_width(4) AND pulse_width(5) AND pulse_width(6) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2)); Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 <= ((pulse_width(12) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2) OR (NOT pulse_width(12) AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2) OR ( NOT Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 AND Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2) OR (BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2) OR (NOT pulse_width(10) AND NOT pulse_width(11) AND NOT pulse_width(6) AND NOT pulse_width(7) AND NOT pulse_width(8) AND NOT pulse_width(9) AND NOT Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2) OR (NOT pulse_width(10) AND NOT pulse_width(11) AND NOT pulse_width(7) AND NOT pulse_width(8) AND NOT pulse_width(9) AND NOT Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2)); FDCPE_Q0: FDCPE port map (Q0,ppm_i,ppm_clk_i,'0','0'); FDCPE_Q1: FDCPE port map (Q1,Q0,ppm_clk_i,'0','0'); FTCPE_bit_cnt0: FTCPE port map (bit_cnt(0),'1',NOT sclk_i,'0',sel_i); FTCPE_bit_cnt1: FTCPE port map (bit_cnt(1),bit_cnt(0),NOT sclk_i,'0',sel_i); FTCPE_bit_cnt2: FTCPE port map (bit_cnt(2),bit_cnt_T(2),NOT sclk_i,'0',sel_i); bit_cnt_T(2) <= (NOT bit_cnt(1) AND NOT bit_cnt(0)); FTCPE_bit_cnt3: FTCPE port map (bit_cnt(3),bit_cnt_T(3),NOT sclk_i,'0',sel_i); bit_cnt_T(3) <= (NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FTCPE_channel_counter0: FTCPE port map (channel_counter(0),channel_counter_T(0),ppm_clk_i,'0','0',channel_counter_CE(0)); channel_counter_T(0) <= ((NOT ppm_i AND NOT channel_counter(0) AND channel_counter(3) AND NOT Q0 AND Q1) OR (NOT ppm_i AND NOT channel_counter(0) AND reset AND NOT Q0 AND Q1)); channel_counter_CE(0) <= (NOT ppm_i AND NOT Q0 AND Q1); FDCPE_channel_counter1: FDCPE port map (channel_counter(1),channel_counter_D(1),ppm_clk_i,'0','0',channel_counter_CE(1)); channel_counter_D(1) <= ((channel_counter(0) AND channel_counter(1)) OR (NOT channel_counter(0) AND NOT channel_counter(1)) OR (NOT ppm_i AND channel_counter(3) AND NOT Q0 AND Q1) OR (NOT ppm_i AND reset AND NOT Q0 AND Q1)); channel_counter_CE(1) <= (NOT ppm_i AND NOT Q0 AND Q1); FDCPE_channel_counter2: FDCPE port map (channel_counter(2),channel_counter_D(2),ppm_clk_i,'0','0',channel_counter_CE(2)); channel_counter_D(2) <= ((NOT ppm_i AND reset AND NOT Q0 AND Q1) OR (NOT channel_counter(0) AND NOT channel_counter(2)) OR (NOT channel_counter(1) AND NOT channel_counter(2)) OR (channel_counter(0) AND channel_counter(1) AND channel_counter(2)) OR (NOT ppm_i AND channel_counter(3) AND NOT Q0 AND Q1)); channel_counter_CE(2) <= (NOT ppm_i AND NOT Q0 AND Q1); FTCPE_channel_counter3: FTCPE port map (channel_counter(3),channel_counter_T(3),ppm_clk_i,'0','0',channel_counter_CE(3)); channel_counter_T(3) <= ((channel_counter(0) AND channel_counter(1) AND channel_counter(2) AND NOT reset) OR (channel_counter(0) AND channel_counter(1) AND channel_counter(2) AND NOT Q1) OR (ppm_i AND channel_counter(0) AND channel_counter(1) AND channel_counter(2)) OR (NOT ppm_i AND channel_counter(3) AND NOT Q0 AND Q1) OR (channel_counter(0) AND channel_counter(1) AND channel_counter(2) AND Q0)); channel_counter_CE(3) <= (NOT ppm_i AND NOT Q0 AND Q1); FDCPE_irq_assert: FDCPE port map (irq_assert,irq_assert_D,ppm_clk_i,'0','0'); irq_assert_D <= ((NOT ppm_i AND irq_assert AND NOT Q0 AND Q1) OR (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1)); FDCPE_irq_deassert: FDCPE port map (irq_deassert,BUF_irq_deassert,ppm_clk_i,'0','0'); miso_o_I <= ((pulse_width(14).EXP) OR (ppm_i AND bit_cnt(3) AND bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)) OR (bit_cnt(3) AND NOT bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0) AND output_register(11)) OR (NOT bit_cnt(3) AND bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0) AND output_register(7)) OR (NOT bit_cnt(3) AND NOT bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0) AND output_register(3)) OR (NOT bit_cnt(3) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0) AND output_register(1)) OR (bit_cnt(3) AND bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0) AND output_register(13)) OR (bit_cnt(3) AND NOT bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0) AND output_register(10)) OR (bit_cnt(3) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0) AND output_register(9)) OR (NOT bit_cnt(3) AND bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0) AND output_register(6)) OR (NOT bit_cnt(3) AND bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0) AND output_register(5)) OR (bit_cnt(3) AND bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0) AND output_register(12)) OR (bit_cnt(3) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0) AND output_register(8)) OR (NOT bit_cnt(3) AND bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0) AND output_register(4)) OR (NOT bit_cnt(3) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0) AND output_register(0))); miso_o <= miso_o_I when miso_o_OE = '1' else 'Z'; miso_o_OE <= NOT sel_i; FDCPE_output_register0: FDCPE port map (output_register(0),output_register_D(0),ppm_clk_i,'0','0',output_register_CE(0)); output_register_D(0) <= ((NOT pulse_width(0) AND BUF_ppm) OR (BUF_irq_deassert AND BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(0) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm)); output_register_CE(0) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register1: FDCPE port map (output_register(1),output_register_D(1),ppm_clk_i,'0','0',output_register_CE(1)); output_register_D(1) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(0) AND NOT pulse_width(1) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (NOT pulse_width(0) AND pulse_width(1) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(1) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); output_register_CE(1) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register2: FDCPE port map (output_register(2),output_register_D(2),ppm_clk_i,'0','0',output_register_CE(2)); output_register_D(2) <= ((pulse_width(0) AND pulse_width(1) AND NOT pulse_width(2) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(0) AND pulse_width(2) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (NOT pulse_width(1) AND pulse_width(2) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(2) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); output_register_CE(2) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register3: FDCPE port map (output_register(3),output_register_D(3),ppm_clk_i,'0','0',output_register_CE(3)); output_register_D(3) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(3) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm) OR (pulse_width(3) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(0) AND pulse_width(1) AND pulse_width(2) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm)); output_register_CE(3) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register4: FDCPE port map (output_register(4),output_register_D(4),ppm_clk_i,'0','0',output_register_CE(4)); output_register_D(4) <= ((pulse_width(4) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm) OR (pulse_width(4) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(4) AND Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm)); output_register_CE(4) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register5: FDCPE port map (output_register(5),output_register_D(5),ppm_clk_i,'0','0',output_register_CE(5)); output_register_D(5) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(5) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (pulse_width(5) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(4) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm)); output_register_CE(5) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register6: FDCPE port map (output_register(6),output_register_D(6),ppm_clk_i,'0','0',output_register_CE(6)); output_register_D(6) <= ((pulse_width(6) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(6) AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (pulse_width(6) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm)); output_register_CE(6) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register7: FDCPE port map (output_register(7),output_register_D(7),ppm_clk_i,'0','0',output_register_CE(7)); output_register_D(7) <= ((NOT pulse_width(6) AND pulse_width(7) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(6) AND NOT pulse_width(7) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(7) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (pulse_width(7) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); output_register_CE(7) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register8: FDCPE port map (output_register(8),output_register_D(8),ppm_clk_i,'0','0',output_register_CE(8)); output_register_D(8) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(8) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (pulse_width(8) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(6) AND pulse_width(7) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm)); output_register_CE(8) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register9: FDCPE port map (output_register(9),output_register_D(9),ppm_clk_i,'0','0',output_register_CE(9)); output_register_D(9) <= ((pulse_width(9) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(9) AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (pulse_width(9) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm)); output_register_CE(9) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register10: FDCPE port map (output_register(10),output_register_D(10),ppm_clk_i,'0','0',output_register_CE(10)); output_register_D(10) <= ((NOT pulse_width(10) AND pulse_width(9) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(10) AND NOT pulse_width(9) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(10) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (pulse_width(10) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); output_register_CE(10) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register11: FDCPE port map (output_register(11),output_register_D(11),ppm_clk_i,'0','0',output_register_CE(11)); output_register_D(11) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(11) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND NOT BUF_ppm) OR (pulse_width(11) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(10) AND pulse_width(9) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm)); output_register_CE(11) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register12: FDCPE port map (output_register(12),channel_counter(0),ppm_clk_i,'0','0',output_register_CE(12)); output_register_CE(12) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register13: FDCPE port map (output_register(13),channel_counter(1),ppm_clk_i,'0','0',output_register_CE(13)); output_register_CE(13) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_output_register14: FDCPE port map (output_register(14),channel_counter(2),ppm_clk_i,'0','0',output_register_CE(14)); output_register_CE(14) <= (NOT ppm_i AND NOT channel_counter(3) AND NOT reset AND NOT Q0 AND Q1); FDCPE_ppm: FDCPE port map (ppm,BUF_ppm,ppm_clk_i,'0','0'); FDCPE_ppm_irq_o: FDCPE port map (ppm_irq_o,sync_o,irq_assert,NOT ppm_irq_o_OBUF/ppm_irq_o_OBUF_RSTF,'0'); ppm_irq_o_OBUF/ppm_irq_o_OBUF_RSTF <= (sel_i AND NOT irq_deassert); FDCPE_pulse_width0: FDCPE port map (pulse_width(0),pulse_width_D(0),ppm_clk_i,'0','0'); pulse_width_D(0) <= ((NOT pulse_width(0) AND NOT BUF_ppm) OR (BUF_irq_deassert AND NOT BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(0) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); FDCPE_pulse_width1: FDCPE port map (pulse_width(1),pulse_width_D(1),ppm_clk_i,'0','0'); pulse_width_D(1) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(0) AND NOT pulse_width(1) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (NOT pulse_width(0) AND pulse_width(1) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(1) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); FDCPE_pulse_width2: FDCPE port map (pulse_width(2),pulse_width_D(2),ppm_clk_i,'0','0'); pulse_width_D(2) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(0) AND pulse_width(2) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (NOT pulse_width(1) AND pulse_width(2) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(2) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(0) AND pulse_width(1) AND NOT pulse_width(2) AND NOT BUF_irq_deassert AND NOT BUF_ppm)); FDCPE_pulse_width3: FDCPE port map (pulse_width(3),pulse_width_D(3),ppm_clk_i,'0','0'); pulse_width_D(3) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(3) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm) OR (pulse_width(3) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(0) AND pulse_width(1) AND pulse_width(2) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm)); FDCPE_pulse_width4: FDCPE port map (pulse_width(4),pulse_width_D(4),ppm_clk_i,'0','0'); pulse_width_D(4) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(4) AND Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm) OR (pulse_width(4) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT BUF_ppm) OR (pulse_width(4) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); FDCPE_pulse_width5: FDCPE port map (pulse_width(5),pulse_width_D(5),ppm_clk_i,'0','0'); pulse_width_D(5) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(5) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (pulse_width(5) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(4) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0002/Madd_pulse_width_add0000__and0002_D2 AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm)); FDCPE_pulse_width6: FDCPE port map (pulse_width(6),pulse_width_D(6),ppm_clk_i,'0','0'); pulse_width_D(6) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(6) AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (pulse_width(6) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (pulse_width(6) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); FDCPE_pulse_width7: FDCPE port map (pulse_width(7),pulse_width_D(7),ppm_clk_i,'0','0'); pulse_width_D(7) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(6) AND pulse_width(7) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(7) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm) OR (pulse_width(7) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(6) AND NOT pulse_width(7) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT BUF_ppm)); FDCPE_pulse_width8: FDCPE port map (pulse_width(8),pulse_width_D(8),ppm_clk_i,'0','0'); pulse_width_D(8) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(8) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (pulse_width(8) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(6) AND pulse_width(7) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm)); FDCPE_pulse_width9: FDCPE port map (pulse_width(9),pulse_width_D(9),ppm_clk_i,'0','0'); pulse_width_D(9) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(9) AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (pulse_width(9) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (pulse_width(9) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); FDCPE_pulse_width10: FDCPE port map (pulse_width(10),pulse_width_D(10),ppm_clk_i,'0','0'); pulse_width_D(10) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(10) AND NOT pulse_width(9) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(10) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm) OR (pulse_width(10) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (NOT pulse_width(10) AND pulse_width(9) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm)); FDCPE_pulse_width11: FDCPE port map (pulse_width(11),pulse_width_D(11),ppm_clk_i,'0','0'); pulse_width_D(11) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(11) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND NOT BUF_ppm) OR (pulse_width(11) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm) OR (pulse_width(10) AND pulse_width(9) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND Madd_pulse_width_add0000__and0007/Madd_pulse_width_add0000__and0007_D2 AND NOT BUF_ppm)); FDCPE_pulse_width12: FDCPE port map (pulse_width(12),pulse_width_D(12),ppm_clk_i,'0','0'); pulse_width_D(12) <= ((pulse_width(12) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR ( Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT BUF_ppm) OR (pulse_width(12) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); FDCPE_pulse_width13: FDCPE port map (pulse_width(13),pulse_width_D(13),ppm_clk_i,'0','0'); pulse_width_D(13) <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(13) AND Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT BUF_ppm) OR (pulse_width(13) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT BUF_ppm) OR (pulse_width(13) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); FDCPE_pulse_width14: FDCPE port map (pulse_width(14),pulse_width_D(14),ppm_clk_i,'0','0'); pulse_width_D(14) <= ((NOT pulse_width(13) AND pulse_width(14) AND NOT BUF_irq_deassert AND NOT BUF_ppm) OR (pulse_width(13) AND NOT pulse_width(14) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT BUF_ppm) OR (sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(14) AND NOT BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT BUF_ppm) OR (pulse_width(14) AND NOT BUF_irq_deassert AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND BUF_ppm)); pwms_o(0) <= (ppm_i AND sync_o AND NOT channel_counter(0) AND NOT channel_counter(3) AND NOT channel_counter(1) AND NOT channel_counter(2) AND NOT reset); pwms_o(1) <= (ppm_i AND sync_o AND channel_counter(0) AND NOT channel_counter(3) AND NOT channel_counter(1) AND NOT channel_counter(2) AND NOT reset); pwms_o(2) <= (ppm_i AND sync_o AND NOT channel_counter(0) AND NOT channel_counter(3) AND channel_counter(1) AND NOT channel_counter(2) AND NOT reset); pwms_o(3) <= (ppm_i AND sync_o AND channel_counter(0) AND NOT channel_counter(3) AND channel_counter(1) AND NOT channel_counter(2) AND NOT reset); pwms_o(4) <= (ppm_i AND sync_o AND NOT channel_counter(0) AND NOT channel_counter(3) AND NOT channel_counter(1) AND channel_counter(2) AND NOT reset); pwms_o(5) <= (ppm_i AND sync_o AND channel_counter(0) AND NOT channel_counter(3) AND NOT channel_counter(1) AND channel_counter(2) AND NOT reset); pwms_o(6) <= (ppm_i AND sync_o AND NOT channel_counter(0) AND NOT channel_counter(3) AND channel_counter(1) AND channel_counter(2) AND NOT reset); pwms_o(7) <= (ppm_i AND sync_o AND channel_counter(0) AND NOT channel_counter(3) AND channel_counter(1) AND channel_counter(2) AND NOT reset); FDCPE_reset: FDCPE port map (reset,reset_D,ppm_clk_i,'0','0'); reset_D <= ((NOT pulse_width(13) AND NOT pulse_width(14) AND pulse_width(6) AND pulse_width(7) AND pulse_width(8) AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(10) AND NOT pulse_width(11) AND NOT pulse_width(13) AND NOT pulse_width(14) AND NOT pulse_width(6) AND NOT pulse_width(7) AND NOT pulse_width(8) AND NOT pulse_width(9) AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(10) AND NOT pulse_width(11) AND NOT pulse_width(13) AND NOT pulse_width(14) AND NOT pulse_width(7) AND NOT pulse_width(8) AND NOT pulse_width(9) AND NOT Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 AND NOT Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(10) AND NOT pulse_width(11) AND NOT pulse_width(13) AND NOT pulse_width(14) AND NOT pulse_width(7) AND NOT pulse_width(8) AND NOT pulse_width(9) AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT pulse_width(12) AND NOT pulse_width(13) AND NOT pulse_width(14) AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (pulse_width(13) AND pulse_width(14) AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (NOT reset AND sync_cmp_eq0000/sync_cmp_eq0000_D2) OR (NOT reset AND BUF_ppm) OR (BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0010/Madd_pulse_width_add0000__and0010_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR ( NOT Mcompar_sync_cmp_le0000_N0/Mcompar_sync_cmp_le0000_N0_D2 AND BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm) OR (BUF_irq_deassert AND Madd_pulse_width_add0000__and0004/Madd_pulse_width_add0000__and0004_D2 AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2 AND NOT sync_cmp_eq0000/sync_cmp_eq0000_D2 AND NOT BUF_ppm)); sync_cmp_eq0000/sync_cmp_eq0000_D2 <= (pulse_width(0) AND pulse_width(10) AND pulse_width(11) AND pulse_width(12) AND pulse_width(13) AND pulse_width(14) AND pulse_width(1) AND pulse_width(2) AND pulse_width(3) AND pulse_width(4) AND pulse_width(5) AND pulse_width(6) AND pulse_width(7) AND pulse_width(8) AND pulse_width(9) AND NOT BUF_irq_deassert); FDCPE_sync_o: FDCPE port map (sync_o,sync_o_D,ppm_clk_i,'0','0'); sync_o_D <= ((sync_cmp_eq0000/sync_cmp_eq0000_D2) OR (NOT sync_o AND BUF_ppm) OR (NOT sync_o AND Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 AND BUF_irq_deassert AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2) OR (NOT sync_o AND NOT pulse_width(13) AND NOT pulse_width(14) AND Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 AND NOT Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2) OR (NOT sync_o AND pulse_width(13) AND pulse_width(14) AND Mcompar_sync_cmp_le0000_N1/Mcompar_sync_cmp_le0000_N1_D2 AND NOT BUF_irq_deassert AND Madd_pulse_width_add0000__and0011/Madd_pulse_width_add0000__and0011_D2)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-10-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-10-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 ppm_i 23 GND 2 pwms_o<0> 24 KPR 3 pwms_o<1> 25 sync_o 4 pwms_o<2> 26 KPR 5 ppm_clk_i 27 KPR 6 KPR 28 sclk_i 7 KPR 29 PROHIBITED 8 pwms_o<3> 30 TDO 9 pwms_o<4> 31 GND 10 GND 32 VCC 11 KPR 33 sel_i 12 KPR 34 miso_o 13 KPR 35 pwms_o<5> 14 KPR 36 pwms_o<6> 15 TDI 37 pwms_o<7> 16 TMS 38 ppm_irq_o 17 TCK 39 KPR 18 KPR 40 KPR 19 KPR 41 VCC 20 KPR 42 KPR 21 VCC 43 KPR 22 KPR 44 KPR Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-PC44 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 90