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vivado.jou
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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Mon May 27 07:26:12 2024
# Process ID: 3304
# Current directory: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent27020 D:\SUSTech\02Sophomore\DigitalDesign\CS214-Project-CPU-debug\CS214-Project-CPU.xpr
# Log file: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/vivado.log
# Journal file: D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.xpr
update_compile_order -fileset sources_1
set_property -dict [list CONFIG.CLKOUT3_USED {true} CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {10.000} CONFIG.MMCM_DIVCLK_DIVIDE {10} CONFIG.MMCM_CLKOUT2_DIVIDE {60} CONFIG.NUM_OUT_CLKS {3} CONFIG.CLKOUT3_JITTER {884.240} CONFIG.CLKOUT3_PHASE_ERROR {871.302}] [get_ips clk_wiz]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
catch { config_ip_cache -export [get_ips -all clk_wiz] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -no_script -sync -force -quiet
reset_run clk_wiz_synth_1
launch_runs -jobs 12 clk_wiz_synth_1
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
set_property ip_repo_paths {{D:/SUSTech/02Sophomore/03 Spring Semester/CS214 ¼ÆËã»ú×é³ÉÔÀí£¨H£©/Labs/Lab 12/SEU_CSE_507_user_uart_bmpg_1.3}} [current_project]
update_ip_catalog
create_ip -name uart_bmpg -vendor SEU_CSE_507 -library user -version 1.3 -module_name uart_bmpg_0 -dir d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip
generate_target {instantiation_template} [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci]
generate_target all [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci]
catch { config_ip_cache -export [get_ips -all uart_bmpg_0] }
export_ip_user_files -of_objects [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci]
launch_runs -jobs 12 uart_bmpg_0_synth_1
export_simulation -of_objects [get_files d:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/uart_bmpg_0/uart_bmpg_0.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
set_property -dict [list CONFIG.Enable_A {Always_Enabled}] [get_ips instr_mem]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/instr_mem_1/instr_mem.xci]
catch { config_ip_cache -export [get_ips -all instr_mem] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/instr_mem_1/instr_mem.xci] -no_script -sync -force -quiet
reset_run instr_mem_synth_1
launch_runs -jobs 12 instr_mem_synth_1
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/instr_mem_1/instr_mem.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
set_property -dict [list CONFIG.Enable_A {Always_Enabled}] [get_ips dmem_uram]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/dmem_uram_1/dmem_uram.xci]
catch { config_ip_cache -export [get_ips -all dmem_uram] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/dmem_uram_1/dmem_uram.xci] -no_script -sync -force -quiet
reset_run dmem_uram_synth_1
launch_runs -jobs 12 dmem_uram_synth_1
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/dmem_uram_1/dmem_uram.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
set_property -dict [list CONFIG.RESET_TYPE {ACTIVE_HIGH} CONFIG.RESET_PORT {reset}] [get_ips clk_wiz]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
catch { config_ip_cache -export [get_ips -all clk_wiz] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -no_script -sync -force -quiet
reset_run clk_wiz_synth_1
launch_runs -jobs 12 clk_wiz_synth_1
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
set_property -dict [list CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.RESET_PORT {resetn}] [get_ips clk_wiz]
generate_target all [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
catch { config_ip_cache -export [get_ips -all clk_wiz] }
catch { [ delete_ip_run [get_ips -all clk_wiz] ] }
export_ip_user_files -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci]
export_simulation -of_objects [get_files D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.srcs/sources_1/ip/clk_wiz/clk_wiz.xci] -directory D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/sim_scripts -ip_user_files_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files -ipstatic_source_dir D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/modelsim} {questa=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/questa} {riviera=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/riviera} {activehdl=D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 12
wait_on_run impl_1
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA}
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {D:/SUSTech/02Sophomore/DigitalDesign/CS214-Project-CPU-debug/CS214-Project-CPU.runs/impl_1/cpu_top.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA}
close_hw