From 3a776241c84e32a551cdc1e53862e973a3dfb88e Mon Sep 17 00:00:00 2001 From: Matt Devereau Date: Mon, 27 Nov 2023 16:12:00 +0000 Subject: [PATCH] Update patch to include changes introduced in https://github.com/ARM-software/acle/pull/278 --- clang/include/clang/Basic/arm_sme.td | 4 +- .../acle_sme2_luti2_lane_zt_x2.c | 88 +++++++++++++++---- .../acle_sme2_luti4_lane_zt_x2.c | 88 +++++++++++++++---- .../aarch64-sme2-intrinsics/acle_sme2_imm.cpp | 28 +++++- .../Target/AArch64/AArch64ISelDAGToDAG.cpp | 3 +- .../AArch64/sme2-intrinsics-luti2-lane-x2.ll | 32 ++++++- .../AArch64/sme2-intrinsics-luti4-lane-x2.ll | 30 +++++++ 7 files changed, 235 insertions(+), 38 deletions(-) diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 9efb2391c89d1..98ddbd68ba574 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -342,6 +342,6 @@ let TargetGuard = "sme2" in { // lookup table expand two contiguous registers // let TargetGuard = "sme2" in { - def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt[_{d}]_x2", "2.dmdm", "cUcsUsiUi", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; - def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt[_{d}]_x2", "2.dmdm", "cUcsUsiUi", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; + def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.dmdm", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; + def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.dmdm", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; } diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c index 51adc31c6968e..dcfe7b24f291a 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c @@ -4,20 +4,10 @@ // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 -#endif - - // CHECK-LABEL: @test_svluti2_lane_zt_u8( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 0) @@ -37,7 +27,7 @@ // CPP-CHECK-NEXT: ret [[TMP4]] // svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_u8,_x2,)(0, zn, 0); + return svluti2_lane_zt_u8_x2(0, zn, 0); } @@ -60,7 +50,7 @@ svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_z // CPP-CHECK-NEXT: ret [[TMP4]] // svint8x2_t test_svluti2_lane_zt_s8(svint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_s8,_x2,)(0, zn, 0); + return svluti2_lane_zt_s8_x2(0, zn, 0); } // CHECK-LABEL: @test_svluti2_lane_zt_u16( @@ -82,7 +72,7 @@ svint8x2_t test_svluti2_lane_zt_s8(svint8_t zn) __arm_streaming __arm_shared_za // CPP-CHECK-NEXT: ret [[TMP4]] // svuint16x2_t test_svluti2_lane_zt_u16(svuint16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_u16,_x2,)(0, zn, 7); + return svluti2_lane_zt_u16_x2(0, zn, 7); } @@ -105,7 +95,51 @@ svuint16x2_t test_svluti2_lane_zt_u16(svuint16_t zn) __arm_streaming __arm_share // CPP-CHECK-NEXT: ret [[TMP4]] // svint16x2_t test_svluti2_lane_zt_s16(svint16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_s16,_x2,)(0, zn, 7); + return svluti2_lane_zt_s16_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f16u13__SVFloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat16x2_t test_svluti2_lane_zt_f16(svfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f16_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_bf16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z25test_svluti2_lane_zt_bf16u14__SVBfloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svbfloat16x2_t test_svluti2_lane_zt_bf16(svbfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_bf16_x2(0, zn, 7); } // CHECK-LABEL: @test_svluti2_lane_zt_u32( @@ -127,7 +161,7 @@ svint16x2_t test_svluti2_lane_zt_s16(svint16_t zn) __arm_streaming __arm_shared_ // CPP-CHECK-NEXT: ret [[TMP4]] // svuint32x2_t test_svluti2_lane_zt_u32(svuint32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_u32,_x2,)(0, zn, 7); + return svluti2_lane_zt_u32_x2(0, zn, 7); } // CHECK-LABEL: @test_svluti2_lane_zt_s32( @@ -149,5 +183,27 @@ svuint32x2_t test_svluti2_lane_zt_u32(svuint32_t zn) __arm_streaming __arm_share // CPP-CHECK-NEXT: ret [[TMP4]] // svint32x2_t test_svluti2_lane_zt_s32(svint32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_s32,_x2,)(0, zn, 7); + return svluti2_lane_zt_s32_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f32u13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat32x2_t test_svluti2_lane_zt_f32(svfloat32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f32_x2(0, zn, 7); } diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c index 51adc31c6968e..dcfe7b24f291a 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c @@ -4,20 +4,10 @@ // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 -#endif - - // CHECK-LABEL: @test_svluti2_lane_zt_u8( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 0) @@ -37,7 +27,7 @@ // CPP-CHECK-NEXT: ret [[TMP4]] // svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_u8,_x2,)(0, zn, 0); + return svluti2_lane_zt_u8_x2(0, zn, 0); } @@ -60,7 +50,7 @@ svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_z // CPP-CHECK-NEXT: ret [[TMP4]] // svint8x2_t test_svluti2_lane_zt_s8(svint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_s8,_x2,)(0, zn, 0); + return svluti2_lane_zt_s8_x2(0, zn, 0); } // CHECK-LABEL: @test_svluti2_lane_zt_u16( @@ -82,7 +72,7 @@ svint8x2_t test_svluti2_lane_zt_s8(svint8_t zn) __arm_streaming __arm_shared_za // CPP-CHECK-NEXT: ret [[TMP4]] // svuint16x2_t test_svluti2_lane_zt_u16(svuint16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_u16,_x2,)(0, zn, 7); + return svluti2_lane_zt_u16_x2(0, zn, 7); } @@ -105,7 +95,51 @@ svuint16x2_t test_svluti2_lane_zt_u16(svuint16_t zn) __arm_streaming __arm_share // CPP-CHECK-NEXT: ret [[TMP4]] // svint16x2_t test_svluti2_lane_zt_s16(svint16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_s16,_x2,)(0, zn, 7); + return svluti2_lane_zt_s16_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f16u13__SVFloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat16x2_t test_svluti2_lane_zt_f16(svfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f16_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_bf16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z25test_svluti2_lane_zt_bf16u14__SVBfloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svbfloat16x2_t test_svluti2_lane_zt_bf16(svbfloat16_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_bf16_x2(0, zn, 7); } // CHECK-LABEL: @test_svluti2_lane_zt_u32( @@ -127,7 +161,7 @@ svint16x2_t test_svluti2_lane_zt_s16(svint16_t zn) __arm_streaming __arm_shared_ // CPP-CHECK-NEXT: ret [[TMP4]] // svuint32x2_t test_svluti2_lane_zt_u32(svuint32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_u32,_x2,)(0, zn, 7); + return svluti2_lane_zt_u32_x2(0, zn, 7); } // CHECK-LABEL: @test_svluti2_lane_zt_s32( @@ -149,5 +183,27 @@ svuint32x2_t test_svluti2_lane_zt_u32(svuint32_t zn) __arm_streaming __arm_share // CPP-CHECK-NEXT: ret [[TMP4]] // svint32x2_t test_svluti2_lane_zt_s32(svint32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { - return SVE_ACLE_FUNC(svluti2_lane_zt,_s32,_x2,)(0, zn, 7); + return svluti2_lane_zt_s32_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f32u13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat32x2_t test_svluti2_lane_zt_f32(svfloat32_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f32_x2(0, zn, 7); } diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp index b4f9c5c9261ae..a82943f17c05f 100644 --- a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp @@ -78,7 +78,7 @@ void test_svluti4_lane_zt_x4(svuint8_t zn) __arm_streaming __arm_shared_za __arm svluti4_lane_zt_f32_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} } -void test_svluti2_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32) __arm_streaming __arm_shared_za __arm_preserves_za { +void test_svluti2_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za { // Test Reg Offset svluti2_lane_zt_u8_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} // Test index value range @@ -91,9 +91,21 @@ void test_svluti2_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u svluti2_lane_zt_u32_x2(1, zn_u32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} // Test index value range svluti2_lane_zt_u32_x2(0, zn_u32, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_f16_x2(1, zn_f16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f16_x2(0, zn_f16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_bf16_x2(1, zn_bf16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_bf16_x2(0, zn_bf16, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_f32_x2(1, zn_f32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f32_x2(0, zn_f32, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} } -void test_svluti4_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32) __arm_streaming __arm_shared_za __arm_preserves_za { +void test_svluti4_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u32, svfloat16_t zn_f16, svbfloat16_t zn_bf16, svfloat32_t zn_f32) __arm_streaming __arm_shared_za __arm_preserves_za { // Test Reg Offset svluti4_lane_zt_u8_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} // Test index value range @@ -106,4 +118,16 @@ void test_svluti4_lane_zt_x2(svuint8_t zn_u8, svuint16_t zn_u16, svuint32_t zn_u svluti4_lane_zt_u32_x2(1, zn_u32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} // Test index value range svluti4_lane_zt_u32_x2(0, zn_u32, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_f16_x2(1, zn_f16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f16_x2(0, zn_f16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_bf16_x2(1, zn_bf16, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_bf16_x2(0, zn_bf16, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_f32_x2(1, zn_f32, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f32_x2(0, zn_f32, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} } diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 4417b0cc73333..b1388774e1c0b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1674,7 +1674,8 @@ static unsigned SelectOpcodeFromVT(EVT VT, ArrayRef Opcodes) { return 0; break; case SelectTypeKind::FP: - if (EltVT != MVT::f16 && EltVT != MVT::f32 && EltVT != MVT::f64) + if (EltVT != MVT::bf16 && EltVT != MVT::f16 && EltVT != MVT::f32 && + EltVT != MVT::f64) return 0; break; } diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll index df658539ba8bf..163349f1a67eb 100644 --- a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll @@ -27,9 +27,39 @@ define {, } @luti2_i32( %x ; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7] ; CHECK-NEXT: ret %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %x, i32 7) - ret {, }%res + ret {, } %res +} + +define {, } @luti2_f16( %x) { +; CHECK-LABEL: luti2_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, %x, i32 7) + ret {, } %res +} + +define {, } @luti2_bf16( %x) { +; CHECK-LABEL: luti2_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, %x, i32 7) + ret {, } %res +} + +define {, } @luti2_f32( %x) { +; CHECK-LABEL: luti2_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, %x, i32 7) + ret {, } %res } declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32, , i32) declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32, , i32) declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32, , i32) diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll index 4aba45025a445..c3209f5025b76 100644 --- a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll @@ -30,6 +30,36 @@ define {, } @luti4_i32( %x ret {, } %res } +define {, } @luti4_f16( %x) { +; CHECK-LABEL: luti4_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, %x, i32 3) + ret {, } %res +} + +define {, } @luti4_bf16( %x) { +; CHECK-LABEL: luti4_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, %x, i32 3) + ret {, } %res +} + +define {, } @luti4_i32( %x) { +; CHECK-LABEL: luti4_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.s, z1.s }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, %x, i32 3) + ret {, } %res +} + declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32, , i32) declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32, , i32) declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32, , i32)