MultiCycleProccessorTest_stx_beh.prj

verilog isim_temp "SignExtend.v"
verilog isim_temp "ShiftRegisterEnable.v"
verilog isim_temp "ShiftRegister.v"
verilog isim_temp "Shifter2.v"
verilog isim_temp "Shifte2New.v"
verilog isim_temp "RegFile.v"
verilog isim_temp "Mux4Fivebit.v"
verilog isim_temp "Mux4.v"
verilog isim_temp "Mux2.v"
verilog isim_temp "Memory.v"
verilog isim_temp "ALU.v"
verilog isim_temp "DataPath.v"
verilog isim_temp "Controller.v"
verilog isim_temp "MultiCycleProccessor.v"
verilog isim_temp "MultiCycleProccessorTest.v"
verilog isim_temp "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"