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RegFile.syr
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RegFile.syr
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Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.33 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.33 secs
--> Reading design: RegFile.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "RegFile.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "RegFile"
Output Format : NGC
Target Device : xc7a100t-3-csg324
---- Source Options
Top Module Name : RegFile
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "\\vboxsvr\sharedwithvm\Memari_Project\MemariProject\RegFile.v" into library work
Parsing module <RegFile>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating module <RegFile>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <RegFile>.
Related source file is "\\vboxsvr\sharedwithvm\Memari_Project\MemariProject\RegFile.v".
Found 32x32-bit dual-port RAM <Mram_regData> for signal <regData>.
Summary:
inferred 2 RAM(s).
Unit <RegFile> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 2
32x32-bit dual-port RAM : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <RegFile>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_regData> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 32-word x 32-bit | |
| clkA | connected to signal <CLK> | rise |
| weA | connected to signal <wEnable> | high |
| addrA | connected to signal <dR> | |
| diA | connected to signal <wData> | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 32-word x 32-bit | |
| addrB | connected to signal <rA> | |
| doB | connected to signal <aData> | |
-----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_regData1> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 32-word x 32-bit | |
| clkA | connected to signal <CLK> | rise |
| weA | connected to signal <wEnable> | high |
| addrA | connected to signal <dR> | |
| diA | connected to signal <wData> | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 32-word x 32-bit | |
| addrB | connected to signal <rB> | |
| doB | connected to signal <bData> | |
-----------------------------------------------------------------------
Unit <RegFile> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 2
32x32-bit dual-port distributed RAM : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <RegFile> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block RegFile, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : RegFile.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1
# GND : 1
# RAMS : 14
# RAM32M : 10
# RAM32X1D : 4
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 112
# IBUF : 48
# OBUF : 64
Device utilization summary:
---------------------------
Selected Device : 7a100tcsg324-3
Slice Logic Utilization:
Number of Slice LUTs: 48 out of 63400 0%
Number used as Memory: 48 out of 19000 0%
Number used as RAM: 48
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 48
Number with an unused Flip Flop: 48 out of 48 100%
Number with an unused LUT: 0 out of 48 0%
Number of fully used LUT-FF pairs: 0 out of 48 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 113
Number of bonded IOBs: 113 out of 210 53%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP | 14 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: 0.748ns
Maximum output required time after clock: 1.648ns
Maximum combinational path delay: 0.933ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Total number of paths / destination ports: 168 / 168
-------------------------------------------------------------------------
Offset: 0.748ns (Levels of Logic = 1)
Source: wEnable (PAD)
Destination: Mram_regData4 (RAM)
Destination Clock: CLK rising
Data Path: wEnable to Mram_regData4
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 14 0.001 0.339 wEnable_IBUF (wEnable_IBUF)
RAM32M:WE 0.408 Mram_regData4
----------------------------------------
Total 0.748ns (0.409ns logic, 0.339ns route)
(54.7% logic, 45.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 64 / 64
-------------------------------------------------------------------------
Offset: 1.648ns (Levels of Logic = 1)
Source: Mram_regData6 (RAM)
Destination: aData<29> (PAD)
Source Clock: CLK rising
Data Path: Mram_regData6 to aData<29>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
RAM32M:WCLK->DOC1 1 1.369 0.279 Mram_regData6 (aData_29_OBUF)
OBUF:I->O 0.000 aData_29_OBUF (aData<29>)
----------------------------------------
Total 1.648ns (1.369ns logic, 0.279ns route)
(83.1% logic, 16.9% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 320 / 64
-------------------------------------------------------------------------
Delay: 0.933ns (Levels of Logic = 3)
Source: rA<4> (PAD)
Destination: aData<29> (PAD)
Data Path: rA<4> to aData<29>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 17 0.001 0.354 rA_4_IBUF (rA_4_IBUF)
RAM32M:ADDRA4->DOA1 1 0.299 0.279 Mram_regData4 (aData_13_OBUF)
OBUF:I->O 0.000 aData_13_OBUF (aData<13>)
----------------------------------------
Total 0.933ns (0.300ns logic, 0.633ns route)
(32.2% logic, 67.8% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
=========================================================================
Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.33 secs
-->
Total memory usage is 227940 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 2 ( 0 filtered)