From 3ed532aa1600a2bf78924832e3a5239ceeca0b81 Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Sun, 28 Jan 2024 20:46:34 -0600 Subject: [PATCH 01/22] Add support for Tronxy V10 with TFT_TRONXY_X5SA Add fixes for TFT_TRONXY_X5SA with Tronxy V10 boards. Add definitions in stm32f4.ini for build options with and without USB flash drive support. Rename pin file for clarity. Define proper pins and options for board. --- Marlin/src/HAL/STM32/tft/tft_fsmc.cpp | 119 ++++-- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 259 ++++++++---- Marlin/src/core/boards.h | 2 +- Marlin/src/pins/pins.h | 4 +- .../pins/stm32f4/pins_TRONXY_CXY_446_V10.h | 372 ++++++++++++++++++ Marlin/src/pins/stm32f4/pins_TRONXY_V10.h | 257 ------------ ini/stm32f4.ini | 40 +- 7 files changed, 665 insertions(+), 388 deletions(-) create mode 100644 Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h delete mode 100644 Marlin/src/pins/stm32f4/pins_TRONXY_V10.h diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp index 8e4f97d0a32e..ce891705abf6 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp @@ -37,30 +37,60 @@ LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; void TFT_FSMC::init() { uint32_t controllerAddress; - FSMC_NORSRAM_TimingTypeDef timing, extTiming; - - uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); - - // Perform the SRAM1 memory initialization sequence - SRAMx.Instance = FSMC_NORSRAM_DEVICE; - SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; - // SRAMx.Init - SRAMx.Init.NSBank = nsBank; - SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; - SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; - #ifdef STM32F4xx - SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; + uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), PINMAP_TFT_CS); + + #if defined(FMC_NORSRAM_DEVICE) + FMC_NORSRAM_TimingTypeDef timing, extTiming; + + // Perform the SRAM1 memory initialization sequence + SRAMx.Instance = FMC_NORSRAM_DEVICE; + SRAMx.Extended = FMC_NORSRAM_EXTENDED_DEVICE; + // SRAMx.Init + SRAMx.Init.NSBank = nsBank; + SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; + SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; + + SRAMx.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; + SRAMx.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE; + + SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; + SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; + #elif defined(FSMC_NORSRAM_DEVICE) + FSMC_NORSRAM_TimingTypeDef timing, extTiming; + + // Perform the SRAM1 memory initialization sequence + SRAMx.Instance = FSMC_NORSRAM_DEVICE; + SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + // SRAMx.Init + SRAMx.Init.NSBank = nsBank; + SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + #ifdef STM32F4xx + SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; + #endif + #else + #error "Selected MCU does not support FSMC/FMC" #endif + // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss timing.AddressSetupTime = 15; @@ -69,7 +99,7 @@ void TFT_FSMC::init() { timing.BusTurnAroundDuration = 0; timing.CLKDivision = 16; timing.DataLatency = 17; - timing.AccessMode = FSMC_ACCESS_MODE_A; + // Write Timing // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss extTiming.AddressSetupTime = 8; @@ -78,25 +108,40 @@ void TFT_FSMC::init() { extTiming.BusTurnAroundDuration = 0; extTiming.CLKDivision = 16; extTiming.DataLatency = 17; - extTiming.AccessMode = FSMC_ACCESS_MODE_A; - - __HAL_RCC_FSMC_CLK_ENABLE(); + + #if defined(FMC_NORSRAM_DEVICE) + timing.AccessMode = FMC_ACCESS_MODE_A; + extTiming.AccessMode = FMC_ACCESS_MODE_A; + __HAL_RCC_FMC_CLK_ENABLE(); + controllerAddress = FMC_BANK1_1; + #else + timing.AccessMode = FSMC_ACCESS_MODE_A; + extTiming.AccessMode = FSMC_ACCESS_MODE_A; + __HAL_RCC_FSMC_CLK_ENABLE(); + controllerAddress = FSMC_BANK1_1; + #endif - for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++) - pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC); - pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); - pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); + for (uint16_t i = 0; PINMAP_TFT_IO[i].pin != NC; i++) + pinmap_pinout(PINMAP_TFT_IO[i].pin, PINMAP_TFT_IO); + pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), PINMAP_TFT_CS); + pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), PINMAP_TFT_RS); - controllerAddress = FSMC_BANK1_1; + // Note: Code below assume that MCU in LQFP-100 package has only one NE pin. STM32H743 has two - NE1 and NE2. #ifdef PF0 switch (nsBank) { - case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; - case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; - case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + #if defined(FMC_NORSRAM_DEVICE) + case FMC_NORSRAM_BANK2: controllerAddress = FMC_BANK1_2 ; break; + case FMC_NORSRAM_BANK3: controllerAddress = FMC_BANK1_3 ; break; + case FMC_NORSRAM_BANK4: controllerAddress = FMC_BANK1_4 ; break; + #else + case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; + case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; + case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + #endif } #endif - controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); + controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), PINMAP_TFT_RS); HAL_SRAM_Init(&SRAMx, &timing, &extTiming); @@ -188,4 +233,4 @@ void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) } #endif // HAS_FSMC_TFT -#endif // HAL_STM32 +#endif // HAL_STM32 \ No newline at end of file diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index 1776cbdb0f65..d6eeb8a02bb8 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -28,7 +28,7 @@ #elif defined(STM32F4xx) #include "stm32f4xx_hal.h" #else - #error "FSMC TFT is currently only supported on STM32F1 and STM32F4 hardware." + #error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware." #endif #ifndef HAL_SRAM_MODULE_ENABLED @@ -47,8 +47,13 @@ #define TFT_IO_DRIVER TFT_FSMC #define DMA_MAX_WORDS 0xFFFF -#define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT) -typedef TERN(TFT_INTERFACE_FSMC_8BIT, uint8_t, uint16_t) tft_data_t; +#if ANY(TFT_INTERFACE_FSMC_8BIT, TFT_INTERFACE_FMC_8BIT) + #define TFT_DATASIZE DATASIZE_8BIT + typedef uint8_t tft_data_t; +#else + #define TFT_DATASIZE DATASIZE_16BIT + typedef uint16_t tft_data_t; +#endif typedef struct { __IO tft_data_t REG; @@ -91,88 +96,184 @@ class TFT_FSMC { } }; -#ifdef STM32F1xx - #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) -#elif defined(STM32F4xx) - #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC) - #define FSMC_BANK1_1 0x60000000U - #define FSMC_BANK1_2 0x64000000U - #define FSMC_BANK1_3 0x68000000U - #define FSMC_BANK1_4 0x6C000000U -#else - #error No configuration for this MCU -#endif - -const PinMap pinMap_FSMC[] = { - {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 - {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 - {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 - {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 - {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 - {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 - {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 - {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 - #if DISABLED(TFT_INTERFACE_FSMC_8BIT) - {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 - {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 - {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 - {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 - {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 - {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 - {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 - {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 +#if defined(FMC_NORSRAM_DEVICE) // Flexible Memory Controller on STM32F446 + #if defined(STM32F4xx) + #define FMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC) + #define FMC_BANK1_1 0x60000000U + #define FMC_BANK1_2 0x64000000U + #define FMC_BANK1_3 0x68000000U + #define FMC_BANK1_4 0x6C000000U + #else + #error "No configuration for this MCU" #endif - {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE - {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE - {NC, NP, 0} -}; -const PinMap pinMap_FSMC_CS[] = { - {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 + #define PINMAP_TFT_IO pinMap_FMC + #define PINMAP_TFT_CS pinMap_FMC_CS + #define PINMAP_TFT_RS pinMap_FMC_RS + + const PinMap pinMap_FMC[] = { + {PD_14, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D00 + {PD_15, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D01 + {PD_0, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D02 + {PD_1, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D03 + {PE_7, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D04 + {PE_8, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D05 + {PE_9, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D06 + {PE_10, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D07 + #if DISABLED(TFT_INTERFACE_FMC_8BIT) + {PE_11, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D08 + {PE_12, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D09 + {PE_13, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D10 + {PE_14, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D11 + {PE_15, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D12 + {PD_8, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D13 + {PD_9, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D14 + {PD_10, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D15 + #endif + {PD_4, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_NOE + {PD_5, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_NWE + {NC, NP, 0} + }; + + const PinMap pinMap_FMC_CS[] = { + {PD_7, (void *)FMC_NORSRAM_BANK1, FMC_PIN_DATA}, // FMC_NE1 #ifdef PF0 - {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 - {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 - {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 + {PG_9, (void *)FMC_NORSRAM_BANK2, FMC_PIN_DATA}, // FMC_NE2 + {PG_10, (void *)FMC_NORSRAM_BANK3, FMC_PIN_DATA}, // FMC_NE3 + {PG_12, (void *)FMC_NORSRAM_BANK4, FMC_PIN_DATA}, // FMC_NE4 #endif {NC, NP, 0} -}; + }; -#if ENABLED(TFT_INTERFACE_FSMC_8BIT) - #define FSMC_RS(A) (void *)((2 << (A-1)) - 1) -#else - #define FSMC_RS(A) (void *)((2 << A) - 2) -#endif + #if ENABLED(TFT_INTERFACE_FMC_8BIT) + #define FMC_RS(A) (void *)((2 << (A-1)) - 1) + #else + #define FMC_RS(A) (void *)((2 << A) - 2) + #endif -const PinMap pinMap_FSMC_RS[] = { - #ifdef PF0 - {PF_0, FSMC_RS( 0), FSMC_PIN_DATA}, // FSMC_A0 - {PF_1, FSMC_RS( 1), FSMC_PIN_DATA}, // FSMC_A1 - {PF_2, FSMC_RS( 2), FSMC_PIN_DATA}, // FSMC_A2 - {PF_3, FSMC_RS( 3), FSMC_PIN_DATA}, // FSMC_A3 - {PF_4, FSMC_RS( 4), FSMC_PIN_DATA}, // FSMC_A4 - {PF_5, FSMC_RS( 5), FSMC_PIN_DATA}, // FSMC_A5 - {PF_12, FSMC_RS( 6), FSMC_PIN_DATA}, // FSMC_A6 - {PF_13, FSMC_RS( 7), FSMC_PIN_DATA}, // FSMC_A7 - {PF_14, FSMC_RS( 8), FSMC_PIN_DATA}, // FSMC_A8 - {PF_15, FSMC_RS( 9), FSMC_PIN_DATA}, // FSMC_A9 - {PG_0, FSMC_RS(10), FSMC_PIN_DATA}, // FSMC_A10 - {PG_1, FSMC_RS(11), FSMC_PIN_DATA}, // FSMC_A11 - {PG_2, FSMC_RS(12), FSMC_PIN_DATA}, // FSMC_A12 - {PG_3, FSMC_RS(13), FSMC_PIN_DATA}, // FSMC_A13 - {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14 - {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15 + const PinMap pinMap_FMC_RS[] = { + #ifdef PF0 + {PF_0, FMC_RS( 0), FMC_PIN_DATA}, // FMC_A0 + {PF_1, FMC_RS( 1), FMC_PIN_DATA}, // FMC_A1 + {PF_2, FMC_RS( 2), FMC_PIN_DATA}, // FMC_A2 + {PF_3, FMC_RS( 3), FMC_PIN_DATA}, // FMC_A3 + {PF_4, FMC_RS( 4), FMC_PIN_DATA}, // FMC_A4 + {PF_5, FMC_RS( 5), FMC_PIN_DATA}, // FMC_A5 + {PF_12, FMC_RS( 6), FMC_PIN_DATA}, // FMC_A6 + {PF_13, FMC_RS( 7), FMC_PIN_DATA}, // FMC_A7 + {PF_14, FMC_RS( 8), FMC_PIN_DATA}, // FMC_A8 + {PF_15, FMC_RS( 9), FMC_PIN_DATA}, // FMC_A9 + {PG_0, FMC_RS(10), FMC_PIN_DATA}, // FMC_A10 + {PG_1, FMC_RS(11), FMC_PIN_DATA}, // FMC_A11 + {PG_2, FMC_RS(12), FMC_PIN_DATA}, // FMC_A12 + {PG_3, FMC_RS(13), FMC_PIN_DATA}, // FMC_A13 + {PG_4, FMC_RS(14), FMC_PIN_DATA}, // FMC_A14 + {PG_5, FMC_RS(15), FMC_PIN_DATA}, // FMC_A15 + #endif + {PD_11, FMC_RS(16), FMC_PIN_DATA}, // FMC_A16 + {PD_12, FMC_RS(17), FMC_PIN_DATA}, // FMC_A17 + {PD_13, FMC_RS(18), FMC_PIN_DATA}, // FMC_A18 + {PE_3, FMC_RS(19), FMC_PIN_DATA}, // FMC_A19 + {PE_4, FMC_RS(20), FMC_PIN_DATA}, // FMC_A20 + {PE_5, FMC_RS(21), FMC_PIN_DATA}, // FMC_A21 + {PE_6, FMC_RS(22), FMC_PIN_DATA}, // FMC_A22 + {PE_2, FMC_RS(23), FMC_PIN_DATA}, // FMC_A23 + #ifdef PF0 + {PG_13, FMC_RS(24), FMC_PIN_DATA}, // FMC_A24 + {PG_14, FMC_RS(25), FMC_PIN_DATA}, // FMC_A25 + #endif + {NC, NP, 0} + }; +#elif defined(FSMC_NORSRAM_DEVICE) // Flexible Static Memory Controller on STM32F103 and STM32F407 + #ifdef STM32F1xx + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) + #elif defined(STM32F4xx) + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC) + #define FSMC_BANK1_1 0x60000000U + #define FSMC_BANK1_2 0x64000000U + #define FSMC_BANK1_3 0x68000000U + #define FSMC_BANK1_4 0x6C000000U + #else + #error "No configuration for this MCU" #endif - {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 - {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 - {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18 - {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 - {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 - {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 - {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 - {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 - #ifdef PF0 - {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24 - {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 + + #define PINMAP_TFT_IO pinMap_FSMC + #define PINMAP_TFT_CS pinMap_FSMC_CS + #define PINMAP_TFT_RS pinMap_FSMC_RS + + const PinMap pinMap_FSMC[] = { + {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 + {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 + {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 + {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 + {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 + {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 + {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 + {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 + #if DISABLED(TFT_INTERFACE_FSMC_8BIT) + {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 + {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 + {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 + {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 + {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 + {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 + {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 + {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 + #endif + {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE + {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE + {NC, NP, 0} + }; + + const PinMap pinMap_FSMC_CS[] = { + {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 + #ifdef PF0 + {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 + {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 + {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 + #endif + {NC, NP, 0} + }; + + #if ENABLED(TFT_INTERFACE_FSMC_8BIT) + #define FSMC_RS(A) (void *)((2 << (A-1)) - 1) + #else + #define FSMC_RS(A) (void *)((2 << A) - 2) #endif - {NC, NP, 0} -}; + + const PinMap pinMap_FSMC_RS[] = { + #ifdef PF0 + {PF_0, FSMC_RS( 0), FSMC_PIN_DATA}, // FSMC_A0 + {PF_1, FSMC_RS( 1), FSMC_PIN_DATA}, // FSMC_A1 + {PF_2, FSMC_RS( 2), FSMC_PIN_DATA}, // FSMC_A2 + {PF_3, FSMC_RS( 3), FSMC_PIN_DATA}, // FSMC_A3 + {PF_4, FSMC_RS( 4), FSMC_PIN_DATA}, // FSMC_A4 + {PF_5, FSMC_RS( 5), FSMC_PIN_DATA}, // FSMC_A5 + {PF_12, FSMC_RS( 6), FSMC_PIN_DATA}, // FSMC_A6 + {PF_13, FSMC_RS( 7), FSMC_PIN_DATA}, // FSMC_A7 + {PF_14, FSMC_RS( 8), FSMC_PIN_DATA}, // FSMC_A8 + {PF_15, FSMC_RS( 9), FSMC_PIN_DATA}, // FSMC_A9 + {PG_0, FSMC_RS(10), FSMC_PIN_DATA}, // FSMC_A10 + {PG_1, FSMC_RS(11), FSMC_PIN_DATA}, // FSMC_A11 + {PG_2, FSMC_RS(12), FSMC_PIN_DATA}, // FSMC_A12 + {PG_3, FSMC_RS(13), FSMC_PIN_DATA}, // FSMC_A13 + {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14 + {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15 + #endif + {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 + {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 + {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18 + {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 + {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 + {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 + {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 + {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 + #ifdef PF0 + {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24 + {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 + #endif + {NC, NP, 0} + }; +#else + #error "Selected MCU does not support FSMC/FMC" +#endif \ No newline at end of file diff --git a/Marlin/src/core/boards.h b/Marlin/src/core/boards.h index 0895bb46a08f..1dfcabdefb86 100644 --- a/Marlin/src/core/boards.h +++ b/Marlin/src/core/boards.h @@ -459,7 +459,7 @@ #define BOARD_OPULO_LUMEN_REV4 5242 // Opulo Lumen PnP Controller REV4 (STM32F407VE / STM32F407VG) #define BOARD_FYSETC_SPIDER_KING407 5243 // FYSETC Spider King407 (STM32F407ZG) #define BOARD_MKS_SKIPR_V1 5244 // MKS SKIPR v1.0 all-in-one board (STM32F407VE) -#define BOARD_TRONXY_V10 5245 // TRONXY V10 (STM32F446ZE) +#define BOARD_TRONXY_CXY_446_V10 5245 // TRONXY CXY-446-V10-220413/CXY-V6-191121 (STM32F446ZE) #define BOARD_CREALITY_F401RE 5246 // Creality CR4NS200141C13 (STM32F401RE) as found in the Ender-5 S1 #define BOARD_BLACKPILL_CUSTOM 5247 // Custom board based on STM32F401CDU6. #define BOARD_I3DBEEZ9_V1 5248 // I3DBEEZ9 V1 (STM32F407ZG) diff --git a/Marlin/src/pins/pins.h b/Marlin/src/pins/pins.h index af32d8c11968..9f5ead671237 100644 --- a/Marlin/src/pins/pins.h +++ b/Marlin/src/pins/pins.h @@ -806,8 +806,8 @@ #include "stm32f4/pins_FYSETC_SPIDER_KING407.h" // STM32F4 env:FYSETC_SPIDER_KING407 #elif MB(MKS_SKIPR_V1) #include "stm32f4/pins_MKS_SKIPR_V1_0.h" // STM32F4 env:mks_skipr_v1 env:mks_skipr_v1_nobootloader -#elif MB(TRONXY_V10) - #include "stm32f4/pins_TRONXY_V10.h" // STM32F4 env:STM32F446_tronxy +#elif MB(TRONXY_CXY_446_V10) + #include "stm32f4/pins_TRONXY_CXY_446_V10.h" // STM32F4 env:TRONXY_CXY_446_V10 env:TRONXY_CXY_446_V10_usb_flash_drive #elif MB(CREALITY_F401RE) #include "stm32f4/pins_CREALITY_F401.h" // STM32F4 env:STM32F401RE_creality #elif MB(BLACKPILL_CUSTOM) diff --git a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h new file mode 100644 index 000000000000..e32f2b52cfc8 --- /dev/null +++ b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h @@ -0,0 +1,372 @@ +/** + * Marlin 3D Printer Firmware + * Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin] + * + * Based on Sprinter and grbl. + * Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +/** + * BOARD_TRONXY_CXY_446_V10 + * + * CXY-V6-191121 / CXY-446-V10-220413 + */ + +#pragma once + +#include "env_validate.h" + +#if HOTENDS > 2 || E_STEPPERS > 2 || NUM_RUNOUT_SENSORS > 2 + #error "Only 2 Hotends / E steppers / Filament Runout sensors are currently supported!" +#endif + +#define BOARD_INFO_NAME "BOARD_TRONXY_CXY_446_V10" +#define DEFAULT_MACHINE_NAME BOARD_INFO_NAME + +#define STEP_TIMER 6 +#define TEMP_TIMER 14 + +// +// EEPROM +// + +// Onboard I2C EEPROM +#if NO_EEPROM_SELECTED + #undef NO_EEPROM_SELECTED + #define I2C_EEPROM + #define MARLIN_EEPROM_SIZE 0x800 // 2K (FT24C16A) +#endif + +// +// SPI Flash +// +#define SPI_FLASH // W25Q16 + +#if ENABLED(SPI_FLASH) + #define SPI_DEVICE 1 + #define SPI_FLASH_SIZE 0x1000000 // 16MB + // SPI1/SPI3 + #define SPI_FLASH_CS_PIN PG15 // W25Q16 CS - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT + #define SPI_FLASH_MOSI_PIN PB5 // W25Q16 DIN - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, FMC_SDCKE1, DCMI_D10, EVENTOUT + #define SPI_FLASH_MISO_PIN PB4 // W25Q16 DOUT - NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, EVENTOUT + #define SPI_FLASH_SCK_PIN PB3 // W25Q16 DCLK - JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, EVENTOUT +#endif + +// +// Limit Switches +// +#define X_STOP_PIN PC15 // X STOP SW - EVENTOUT, OSC32_OUT + +#define X_MIN_PIN X_STOP_PIN +#define X_MAX_PIN PB0 // E0 TMC UART candidate - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUT, ADC12_IN8 + +#define Y_STOP_PIN PC14 // Y STOP SW - EVENTOUT, OSC32_IN + +#if ENABLED(Z_MULTI_ENDSTOPS) + #if X_HOME_DIR > 0 // Swap Z1/Z2 for dual Z with max homing + #define Z_MIN_PIN PF11 // Z2 STOP SW - SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT + #define Z_MAX_PIN PC13 // Z STOP SW - EVENTOUT, TAMP_1/WKUP1 + #else + #define Z_MIN_PIN PC13 // Z STOP SW + #define Z_MAX_PIN PF11 // Z2 STOP SW + #endif + // PE3 is usually connected to Probe + #if ENABLED(FIX_MOUNTED_PROBE) + #define Z_MIN_PROBE_PIN PE3 // BED PROBE - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT + #endif +#elif ENABLED(FIX_MOUNTED_PROBE) + #define Z_STOP_PIN PE3 // BED PROBE +#else + #define Z_STOP_PIN PC13 // Z STOP SW +#endif + +// +// Filament Sensors +// +#if ENABLED(FILAMENT_RUNOUT_SENSOR) + #define FIL_RUNOUT_PIN PE6 // E0 STOP SW - TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, EVENTOUT + + #if NUM_RUNOUT_SENSORS == 2 + #define FIL_RUNOUT2_PIN PF12 // E1 STOP SW - FMC_A6, EVENTOUT + #endif +#endif + +// +// Steppers +// +#define X_ENABLE_PIN PF0 // X TMC2225 EN - I2C2_SDA, FMC_A0, EVENTOUT +#define X_STEP_PIN PE5 // X TMC2225 STEP - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, EVENTOUT +#define X_DIR_PIN PF1 // X TMC2225 DIR - I2C2_SCL, FMC_A1, EVENTOUT + +#define Y_ENABLE_PIN PF5 // Y TMC2225 EN - FMC_A5, EVENTOUT, ADC3_IN15 +#define Y_STEP_PIN PF9 // Y TMC2225 STEP - SAI1_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT, ADC3_IN7 +#define Y_DIR_PIN PF3 // Y TMC2225 DIR - FMC_A3, EVENTOUT, ADC3_IN9 + +#define Z_ENABLE_PIN PA5 // Z TMC2225 EN - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT, ADC12_IN5, DAC_OUT2 +#define Z_STEP_PIN PA6 // Z TMC2225 STEP - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, DCMI_PIXCLK, EVENTOUT, ADC12_IN6 +#define Z_DIR_PIN PF15 // Z TMC2225 DIR - FMPI2C1_SDA, FMC_A9, EVENTOUT + +#ifdef Z2_DRIVER_TYPE + #define Z2_ENABLE_PIN PF7 // Z2 TMC2225 EN - TIM11_CH1, SAI1_MCLK_B, QUADSPI_BK1_IO2, EVENTOUT, ADC3_IN5 + #define Z2_STEP_PIN PF6 // Z2 TMC2225 STEP - TIM10_CH1, SAI1_SD_B, QUADSPI_BK1_IO3, EVENTOUT, ADC3_IN4 + #define Z2_DIR_PIN PF4 // Z2 TMC2225 DIR - FMC_A4, EVENTOUT, ADC3_IN14 +#endif + +#define E0_ENABLE_PIN PF14 // E0 TMC2225 EN - FMPI2C1_SCL, FMC_A8, EVENTOUT +#define E0_STEP_PIN PB1 // E0 TMC2225 STEP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, SDIO_D2, EVENTOUT, ADC12_IN9 +#define E0_DIR_PIN PF13 // E0 TMC2225 DIR - FMPI2C1_SMBA, FMC_A7, EVENTOUT + +#if (EXTRUDERS == 2) + #ifndef E1_DRIVER_TYPE + #error "E1_DRIVER_TYPE must be defined in Configuration.h to use 2 extruders!" + #else + #define E1_ENABLE_PIN PG5 // E1 TMC2225 EN - FMC_A15/FMC_BA1, EVENTOUT + #define E1_STEP_PIN PD12 // E1 TMC2225 STEP - TIM4_CH1, FMPI2C1_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, EVENTOUT + #define E1_DIR_PIN PG4 // E1 TMC2225 DIR - FMC_A14/FMC_BA0, EVENTOUT + #endif +#endif + +#if HAS_TMC_UART + /** + * TMC2208/TMC2209 Software Serial + * + * Only uses 1 pin for UART + * Modification to board required. + * + * Use at your own risk!!! + * + * Instructions: https://zenn.dev/marbocub/articles/tronxy-stm32f4-mainboard-tmc-serial-wiring + */ + // Comment out error line below once pins have been configured to continue. + #error "TMC UART not supported by default on this board. Modification to board required. See pins_TRONXY_CXY_446_V10.h for details." + /* + #define X_SERIAL_TX_PIN PE4 // TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, EVENTOUT + #define X_SERIAL_RX_PIN X_SERIAL_TX_PIN + + #define Y_SERIAL_TX_PIN PF2 // I2C2_SMBA, FMC_A2, EVENTOUT + #define Y_SERIAL_RX_PIN Y_SERIAL_TX_PIN + + #define Z_SERIAL_TX_PIN PA4 // SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, EVENTOUTADC12_IN4, DAC_OUT1 + #define Z_SERIAL_RX_PIN Z_SERIAL_TX_PIN + + #ifdef Z2_DRIVER_TYPE + #define Z2_SERIAL_TX_PIN PF8 // SAI1_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT + #define Z2_SERIAL_RX_PIN Z2_SERIAL_TX_PIN + #endif + + #define E0_SERIAL_TX_PIN PB0 // TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUTADC12_IN8 + #define E0_SERIAL_RX_PIN E0_SERIAL_TX_PIN + + // Unsure on this pin assignment + //#define E1_SERIAL_TX_PIN PD5 // USART2_TX, FMC_NWE, EVENTOUT + //#define E1_SERIAL_RX_PIN E1_SERIAL_TX_PIN + */ +#endif + +// +// Temperature Sensors +// +#define TEMP_0_PIN PC3 // Hotend #1 Therm - SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT, ADC123_IN13 + +#if EXTRUDERS == 2 + #define TEMP_1_PIN PC0 // Hotend #2 Therm - SAI1_MCLK_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT, ADC123_IN10 +#endif + +#define TEMP_BED_PIN PC2 // Bed Therm - SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT, ADC123_IN12 + +// +// Heaters +// +#define HEATER_0_PIN PG7 // Hotend #1 Heater - USART6_CK, FMC_INT, DCMI_D13, EVENTOUT + +#if EXTRUDERS == 2 + #define HEATER_1_PIN PA15 // Hotend #2 Heater - JTDI, TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT +#endif + +#define HEATER_BED_PIN PE2 // Bed Heater - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT + +// +// Fans +// +#define FAN0_PIN PG0 // Part Cooling Fan #1 - FMC_A10, EVENTOUT + +#if EXTRUDERS == 2 + #define FAN1_PIN PB6 // Part Cooling Fan #2 - TIM4_CH1, HDMI_CEC, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, FMC_SDNE1, DCMI_D5, EVENTOUT + #define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT + #define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan - DCMI_D11, EVENTOUT, ADC3_IN8 +#else + #define FAN1_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT +#endif + +#define CONTROLLER_FAN_PIN PD7 // USART2_CK, SPDIFRX_IN0, FMC_NE1, EVENTOUT + +// Define so that hotend heatsink fans automatically start when hotends reach 50 degrees. +#if EXTRUDERS == 2 + #undef E0_AUTO_FAN_PIN + #undef E1_AUTO_FAN_PIN + #define E0_AUTO_FAN_PIN FAN2_PIN + #define E1_AUTO_FAN_PIN FAN3_PIN +#else + #undef E0_AUTO_FAN_PIN + #define E0_AUTO_FAN_PIN FAN1_PIN +#endif + +#define FAN_SOFT_PWM_REQUIRED + +// +// Laser / Servos +// +// NOTE: SPINDLE_LASER_PWM_PIN and SERVO0_PIN are the same pin. +// Only one feature can be enabled at a time. +// +#if ENABLED(LASER_FEATURE) + #if NUM_SERVOS > 0 + #error "NUM_SERVOS must equal 0 to enable LASER_FEATURE" + #else + #define SPINDLE_LASER_ENA_PIN PB11 // WiFi TXD (Pin5) - TIM2_CH4, I2C2_SDA, USART3_RX, SAI2_SD_A, EVENTOUT + #if ENABLED(SPINDLE_LASER_USE_PWM) + #define SPINDLE_LASER_PWM_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT + /** + * NOTE: The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be compounded here. + * See PWM_PIN(x) definition for details. + */ + #endif + #endif +#endif + +#if NUM_SERVOS > 0 + #if ENABLED(LASER_FEATURE) + #error "LASER_FEATURE must be disabled to set NUM_SERVOS greater than 0" + #elif NUM_SERVOS > 1 + #error "Only one servo is currently supported" + #else + #define SERVO0_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT + /** + * Enabled after enabling NUM_SERVOS > 0. + * + * NOTE: Shares PB10 pin with laser. Features cannot be enabled at the same time. + */ + #endif +#endif + +// +// TFT with FSMC interface +// +#if ANY(TFT_TRONXY_X5SA, MKS_ROBIN_TFT43) + + //SPI2 + #define TOUCH_CS_PIN PD11 // TOUCH SCREEN HR2046 CS - FMPI2C1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT + #define TOUCH_SCK_PIN PB13 // TOUCH SCREEN HR2046 DCLK - TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, EVENTOUT + #define TOUCH_MISO_PIN PB14 // TOUCH SCREEN HR2046 DOUT - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT + #define TOUCH_MOSI_PIN PB15 // TOUCH SCREEN HR2046 DIN - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, EVENTOUT + + #define TFT_RESET_PIN PB12 // TOUCH SCREEN HR2046 CS - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SAI1_SCK_B, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT + #define TFT_BACKLIGHT_PIN PG8 // LCD MODULE BACKLIGHT - SPDIFRX_IN2, USART6_RTS, FMC_SDCLK, EVENTOUT + + #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT + #define FSMC_DMA_DEV DMA2 + #define FSMC_DMA_CHANNEL DMA_CH5 + + #define TFT_CS_PIN PG12 // SPI4_MISO, SPDIFRX_IN1, USART6_RTS, FMC_NE4, EVENTOUT + #define TFT_RS_PIN PG2 // FMC_A12, EVENTOUT + + #define FSMC_CS_PIN TFT_CS_PIN + #define FSMC_RS_PIN TFT_RS_PIN + + #if ENABLED(TFT_LVGL_UI) + #define HAS_SPI_FLASH_FONT 1 + #define HAS_GCODE_PREVIEW 1 + #define HAS_GCODE_DEFAULT_VIEW_IN_FLASH 0 + #define HAS_LANG_SELECT_SCREEN 1 + #define HAS_BAK_VIEW_IN_FLASH 0 + #define HAS_LOGO_IN_FLASH 0 + #elif ENABLED(TFT_COLOR_UI) + #define TFT_DRIVER ILI9488 + #define TFT_BUFFER_SIZE 14400 + #endif + + //Touch Screen calibration + #if ANY(TFT_LVGL_UI, TFT_COLOR_UI, TFT_CLASSIC_UI) + #if DISABLED(TOUCH_SCREEN_CALIBRATION) + #error "TFT screen requires TOUCH_SCREEN_CALIBRATION" + #elif ANY(TOUCH_CALIBRATION_X, TOUCH_CALIBRATION_Y, TOUCH_OFFSET_X, TOUCH_OFFSET_Y) + #undef TOUCH_CALIBRATION_X + #undef TOUCH_CALIBRATION_Y + #undef TOUCH_OFFSET_X + #undef TOUCH_OFFSET_Y + #endif + #if ENABLED(TFT_TRONXY_X5SA) + #define TOUCH_CALIBRATION_X -17181 + #define TOUCH_CALIBRATION_Y 11434 + #define TOUCH_OFFSET_X 501 + #define TOUCH_OFFSET_Y -9 + #elif ENABLED(MKS_ROBIN_TFT43) + #define XPT2046_X_CALIBRATION 17184 + #define XPT2046_Y_CALIBRATION 10604 + #define XPT2046_X_OFFSET -31 + #define XPT2046_Y_OFFSET -29 + #endif + #endif +#else + #error "Only TFT_TRONXY_X5SA and MKS_ROBIN_TFT43 are currently supported with this board." +#endif + +// +// SD Card / Flash Drive +// + +// USB Flash Drive Support +#if ENABLED(USBHOST_HS_EN) + #define HAS_OTG_USB_HOST_SUPPORT +#endif + +// SD Card +#define ONBOARD_SDIO +#define SD_DETECT_PIN -1 +#define SDIO_CLOCK 4500000 +#define SDIO_READ_RETRIES 16 + +#define SDIO_D0_PIN PC8 // TRACED0, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT +#define SDIO_D1_PIN PC9 // MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDIO_D1, DCMI_D3, EVENTOUT +#define SDIO_D2_PIN PC10 // SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDIO_D2, DCMI_D8, EVENTOUT +#define SDIO_D3_PIN PC11 // SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDIO_D3, DCMI_D4, EVENTOUT +#define SDIO_CK_PIN PC12 // I2C2_SDA, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, EVENTOUT +#define SDIO_CMD_PIN PD2 // TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT + +// +// Power Loss / Power Supply Control +// +// NOTE: PS_ON_PIN and LED_PIN are the same pin. +// + +#if ENABLED(PSU_CONTROL) + // LED - Temporarily switch the machine with LED simulation + #define PS_ON_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT + // 24V DET - Output of LM393 comparator, configured as pullup + #define POWER_LOSS_PIN PE1 // FMC_NBL1, DCMI_D3, EVENTOUT + // +V for the LM393 comparator, configured as output high + #define POWER_LM393_PIN PE0 // TIM4_ETR, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT +#endif + +// +// Misc +// +#ifndef PS_ON_PIN + #define LED_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT +#endif + +#define BEEPER_PIN PA8 // MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT \ No newline at end of file diff --git a/Marlin/src/pins/stm32f4/pins_TRONXY_V10.h b/Marlin/src/pins/stm32f4/pins_TRONXY_V10.h deleted file mode 100644 index 97580bf618f9..000000000000 --- a/Marlin/src/pins/stm32f4/pins_TRONXY_V10.h +++ /dev/null @@ -1,257 +0,0 @@ -/** - * Marlin 3D Printer Firmware - * Copyright (c) 2022 MarlinFirmware [https://github.com/MarlinFirmware/Marlin] - * - * Based on Sprinter and grbl. - * Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - */ -#pragma once - -#include "env_validate.h" - -#if HOTENDS > 3 || E_STEPPERS > 3 - #error "Tronxy V10 supports up to 3 hotends / E steppers." -#endif - -#define BOARD_INFO_NAME "Tronxy V10" -#define DEFAULT_MACHINE_NAME BOARD_INFO_NAME - -#define STEP_TIMER 6 -#define TEMP_TIMER 14 - -// -// Servos -// -//#define SERVO0_PIN PB10 - -// -// EEPROM -// -#if NO_EEPROM_SELECTED - #undef NO_EEPROM_SELECTED - #if TRONXY_UI > 0 - #define EEPROM_AT24CXX - #else - #define FLASH_EEPROM_EMULATION - #endif -#endif - -#if ENABLED(FLASH_EEPROM_EMULATION) - // SoC Flash (framework-arduinoststm32-maple/STM32F1/libraries/EEPROM/EEPROM.h) - #define EEPROM_START_ADDRESS (0x8000000UL + (512 * 1024) - 2 * EEPROM_PAGE_SIZE) - #define EEPROM_PAGE_SIZE (0x800U) // 2KB, but will use 2x more (4KB) - #define MARLIN_EEPROM_SIZE EEPROM_PAGE_SIZE -#else - #if ENABLED(EEPROM_AT24CXX) - #define AT24CXX_SCL PB8 - #define AT24CXX_SDA PB9 - #define AT24CXX_WP PB7 - #else - #define I2C_EEPROM // AT24C32 - #endif - #define MARLIN_EEPROM_SIZE 0x1000 // 4K -#endif - -// -// SPI Flash -// -//#define SPI_FLASH -#if ENABLED(SPI_FLASH) - #define SPI_FLASH_SIZE 0x200000 // 2MB - #define SPI_FLASH_CS_PIN PG15 // SPI2 - #define SPI_FLASH_SCK_PIN PB3 - #define SPI_FLASH_MISO_PIN PB4 - #define SPI_FLASH_MOSI_PIN PB5 -#endif - -// -// Limit Switches -// -#define X_MIN_PIN PC15 -#define X_MAX_PIN PB0 -#define Y_STOP_PIN PC14 - -#ifndef Z_MIN_PROBE_PIN - #define Z_MIN_PROBE_PIN PE3 -#endif - -#if ENABLED(DUAL_Z_ENDSTOP_PROBE) - #if NUM_Z_STEPPERS > 1 && Z_HOME_TO_MAX // Swap Z1/Z2 for dual Z with max homing - #define Z_MIN_PIN PF11 - #define Z_MAX_PIN PC13 - #else - #define Z_MIN_PIN PC13 - #define Z_MAX_PIN PF11 - #endif -#else - #ifndef Z_STOP_PIN - #define Z_STOP_PIN PC13 - #endif -#endif -// -// Filament Sensors -// -#ifndef FIL_RUNOUT_PIN - #define FIL_RUNOUT_PIN PE6 // MT_DET -#endif -#ifndef FIL_RUNOUT2_PIN - #define FIL_RUNOUT2_PIN PF12 -#endif - -// -// Steppers -// -#define X_ENABLE_PIN PF0 -#define X_STEP_PIN PE5 -#define X_DIR_PIN PF1 - -#define Y_ENABLE_PIN PF5 -#define Y_STEP_PIN PF9 -#define Y_DIR_PIN PF3 - -#define Z_ENABLE_PIN PA5 -#define Z_STEP_PIN PA6 -#define Z_DIR_PIN PF15 - -#define E0_ENABLE_PIN PF14 -#define E0_STEP_PIN PB1 -#define E0_DIR_PIN PF13 - -#define E1_ENABLE_PIN PG5 -#define E1_STEP_PIN PD12 -#define E1_DIR_PIN PG4 - -#define E2_ENABLE_PIN PF7 -#define E2_STEP_PIN PF6 -#define E2_DIR_PIN PF4 - -// -// Temperature Sensors -// -#define TEMP_0_PIN PC3 // TH1 -#define TEMP_BED_PIN PC2 // TB1 - -// -// Heaters / Fans -// -#define HEATER_0_PIN PG7 // HEATER1 -#define HEATER_BED_PIN PE2 // HOT BED -//#define HEATER_BED_INVERTING true - -#define FAN0_PIN PG0 // FAN0 -#define FAN1_PIN PB6 // FAN1 -#define FAN2_PIN PG9 // FAN2 -#define FAN3_PIN PF10 // FAN3 -#define CONTROLLER_FAN_PIN PD7 // BOARD FAN -#define FAN_SOFT_PWM_REQUIRED - -// -// Laser / Spindle -// -#if HAS_CUTTER - #define SPINDLE_LASER_ENA_PIN PB11 // wifi:TX - #if ENABLED(SPINDLE_LASER_USE_PWM) - #define SPINDLE_LASER_PWM_PIN PB10 // wifi:RX-TIM2_CH3 - // The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be compounded here - // See PWM_PIN(x) definition for details - #endif -#endif - -// -// Misc -// -#define BEEPER_PIN PA8 - -//#define LED_PIN PG10 -#define PS_ON_PIN PG10 // Temporarily switch the machine with LED simulation - -#if ENABLED(TRONXY_BACKUP_POWER) - #define POWER_LOSS_PIN PF11 // Configure as drop-down input -#else - #define POWER_LOSS_PIN PE1 // Output of LM393 comparator, configured as pullup -#endif -//#define POWER_LM393_PIN PE0 // +V for the LM393 comparator, configured as output high - -#if ENABLED(TFT_TRONXY_X5SA) - #error "TFT_TRONXY_X5SA is not yet supported." -#endif - -#if 0 - -// -// TFT with FSMC interface -// -#if HAS_FSMC_TFT - #define TFT_RESET_PIN PB12 - #define TFT_BACKLIGHT_PIN PG8 - - #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT - - #define TFT_CS_PIN PG12 - #define TFT_RS_PIN PG2 - - //#define TFT_WIDTH 480 - //#define TFT_HEIGHT 320 - //#define TFT_PIXEL_OFFSET_X 48 - //#define TFT_PIXEL_OFFSET_Y 32 - //#define TFT_DRIVER ILI9488 - //#define TFT_BUFFER_WORDS 14400 - - #if NEED_TOUCH_PINS - #define TOUCH_CS_PIN PD11 // SPI1_NSS - #define TOUCH_SCK_PIN PB13 // SPI1_SCK - #define TOUCH_MISO_PIN PB14 // SPI1_MISO - #define TOUCH_MOSI_PIN PB15 // SPI1_MOSI - #endif - - #if (LCD_CHIP_INDEX == 1 && (TRONXY_UI == 1 || TRONXY_UI == 2)) || LCD_CHIP_INDEX == 3 - #define TOUCH_CALIBRATION_X -17181 - #define TOUCH_CALIBRATION_Y 11434 - #define TOUCH_OFFSET_X 501 - #define TOUCH_OFFSET_Y -9 - #elif LCD_CHIP_INDEX == 1 && TRONXY_UI == 4 - #define TOUCH_CALIBRATION_X 11166 - #define TOUCH_CALIBRATION_Y 17162 - #define TOUCH_OFFSET_X -10 - #define TOUCH_OFFSET_Y -16 - #elif LCD_CHIP_INDEX == 4 && TRONXY_UI == 3 - //#define TOUCH_CALIBRATION_X 8781 - //#define TOUCH_CALIBRATION_Y 11773 - //#define TOUCH_OFFSET_X -17 - //#define TOUCH_OFFSET_Y -16 - // Upside-down - #define TOUCH_CALIBRATION_X -8553 - #define TOUCH_CALIBRATION_Y -11667 - #define TOUCH_OFFSET_X 253 - #define TOUCH_OFFSET_Y 331 - #elif LCD_CHIP_INDEX == 2 - #define TOUCH_CALIBRATION_X 17184 - #define TOUCH_CALIBRATION_Y 10604 - #define TOUCH_OFFSET_X -31 - #define TOUCH_OFFSET_Y -29 - #endif -#endif - -#endif - -// -// SD Card -// -#define ONBOARD_SDIO -#define SD_DETECT_PIN -1 // PF0, but not connected -#define SDIO_CLOCK 4500000 -#define SDIO_READ_RETRIES 16 diff --git a/ini/stm32f4.ini b/ini/stm32f4.ini index 2ba5742f4fec..eda59c7b45a2 100644 --- a/ini/stm32f4.ini +++ b/ini/stm32f4.ini @@ -812,18 +812,34 @@ upload_protocol = dfu upload_command = dfu-util -a 0 -s 0x08000000:leave -D "$SOURCE" # -# STM32F446ZET6 ARM Cortex-M4 -# -[env:STM32F446_tronxy] -extends = stm32_variant -board = marlin_STM32F446ZET_tronxy -board_build.offset = 0x10000 -board_build.rename = fmw_tronxy.bin -build_flags = ${stm32_variant.build_flags} - -DSTM32F4xx -build_unflags = ${stm32_variant.build_unflags} -fno-rtti - -DUSBCON -DUSBD_USE_CDC - +# TRONXY_CXY_446_V10 (STM32F446ZET6 ARM Cortex-M4) +# +[env:TRONXY_CXY_446_V10] +extends = stm32_variant +board = marlin_STM32F446ZET_tronxy +board_build.offset = 0x10000 +board_build.ldscript = buildroot/share/PlatformIO/variants/MARLIN_F446Zx_TRONXY/ldscript.ld +build_src_filter = ${common_stm32.build_src_filter} +board_build.rename = fmw_tronxy.bin +build_flags = ${stm32_variant.build_flags} + -DSTM32F4xx -DUSE_USBHOST_FS +build_unflags = ${stm32_variant.build_unflags} -fno-rtti + -fno-threadsafe-statics -fno-exceptions + -DUSBD_USE_CDC -DUSBCON +extra_scripts = ${stm32_variant.extra_scripts} + buildroot/share/PlatformIO/scripts/tronxy_script.py + +# +# TRONXY_CXY_446_V10 (STM32F446ZET6 ARM Cortex-M4) with USB Flash Drive Support +# +[env:TRONXY_CXY_446_V10_usb_flash_drive] +extends = env:TRONXY_CXY_446_V10 +platform_packages = ${stm_flash_drive.platform_packages} +build_flags = ${common_stm32.build_flags} + -DHAL_PCD_MODULE_ENABLED -DUSBHOST + -DUSBH_IRQ_PRIO=3 -DUSBH_IRQ_SUBPRIO=4 + -DUSBHOST_HS_EN=1 + # # Blackpill # From a56985698136bc586fbb322a6bf1931bd6befc68 Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Sun, 28 Jan 2024 21:22:06 -0600 Subject: [PATCH 02/22] Create tronxy_script.py Creates compiled fmw_tronxy.bin and fmw_tronxy.hex firmware files and places them in a folder labeled "update" in the root of the Marlin project folder for easy access for the user. The Tronxy V10 board requires the firmware to be named in this manner and inside the folder "update" on the SD card for flashing. This saves the user a few steps. --- .../share/PlatformIO/scripts/tronxy_script.py | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 buildroot/share/PlatformIO/scripts/tronxy_script.py diff --git a/buildroot/share/PlatformIO/scripts/tronxy_script.py b/buildroot/share/PlatformIO/scripts/tronxy_script.py new file mode 100644 index 000000000000..5483fd37cfb1 --- /dev/null +++ b/buildroot/share/PlatformIO/scripts/tronxy_script.py @@ -0,0 +1,42 @@ + +import marlin +import os + +from SCons.Script import DefaultEnvironment + +env = DefaultEnvironment() +board = env.BoardConfig() +if 'offset' in board.get("build").keys(): + marlin.relocate_vtab(board.get('build.offset')) + +path = "update" +# Check whether the "update" folder exists +isExist = os.path.exists(path) +if not isExist: + # Create the "update" folder + os.makedirs(path) + +#build "fmw_tronxy.hex" and place in "update" folder +def output_target_hex(): + tar_hex = "update/fmw_tronxy.hex" + env.AddPostAction( + "$BUILD_DIR/${PROGNAME}.elf", + env.VerboseAction(" ".join([ + "$OBJCOPY", "-O", "ihex", "-R", ".eeprom", + "$BUILD_DIR/${PROGNAME}.elf", tar_hex + ]), "Building %s" % tar_hex) + ) + +#build "fmw_tronxy.bin" and place in "update" folder +def output_target_bin(): + tar_bin = "update/fmw_tronxy.bin" + env.AddPostAction( + "$BUILD_DIR/${PROGNAME}.elf", + env.VerboseAction(" ".join([ + "$OBJCOPY", "-O", "binary", "-R", ".eeprom", + "$BUILD_DIR/${PROGNAME}.elf", tar_bin + ]), "Building %s" % tar_bin) + ) + +output_target_hex() +output_target_bin() From 6adc27d312bf1ddf7b9506060d8b5e0dae9bd255 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Mon, 29 Jan 2024 16:41:15 -0600 Subject: [PATCH 03/22] misc cleanup --- Marlin/src/HAL/STM32/tft/tft_fsmc.cpp | 20 +- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 27 ++- .../pins/stm32f4/pins_TRONXY_CXY_446_V10.h | 218 +++++++++--------- .../share/PlatformIO/scripts/tronxy_script.py | 85 +++---- ini/renamed.ini | 3 + ini/stm32f4.ini | 11 +- 6 files changed, 186 insertions(+), 178 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp index ce891705abf6..036840919e7d 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp @@ -38,8 +38,8 @@ LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; void TFT_FSMC::init() { uint32_t controllerAddress; uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), PINMAP_TFT_CS); - - #if defined(FMC_NORSRAM_DEVICE) + + #ifdef FMC_NORSRAM_DEVICE FMC_NORSRAM_TimingTypeDef timing, extTiming; // Perform the SRAM1 memory initialization sequence @@ -58,7 +58,7 @@ void TFT_FSMC::init() { SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; - + SRAMx.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; SRAMx.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE; @@ -66,7 +66,7 @@ void TFT_FSMC::init() { SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; #elif defined(FSMC_NORSRAM_DEVICE) FSMC_NORSRAM_TimingTypeDef timing, extTiming; - + // Perform the SRAM1 memory initialization sequence SRAMx.Instance = FSMC_NORSRAM_DEVICE; SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; @@ -90,7 +90,7 @@ void TFT_FSMC::init() { #else #error "Selected MCU does not support FSMC/FMC" #endif - + // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss timing.AddressSetupTime = 15; @@ -99,7 +99,7 @@ void TFT_FSMC::init() { timing.BusTurnAroundDuration = 0; timing.CLKDivision = 16; timing.DataLatency = 17; - + // Write Timing // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss extTiming.AddressSetupTime = 8; @@ -108,8 +108,8 @@ void TFT_FSMC::init() { extTiming.BusTurnAroundDuration = 0; extTiming.CLKDivision = 16; extTiming.DataLatency = 17; - - #if defined(FMC_NORSRAM_DEVICE) + + #ifdef FMC_NORSRAM_DEVICE timing.AccessMode = FMC_ACCESS_MODE_A; extTiming.AccessMode = FMC_ACCESS_MODE_A; __HAL_RCC_FMC_CLK_ENABLE(); @@ -129,7 +129,7 @@ void TFT_FSMC::init() { // Note: Code below assume that MCU in LQFP-100 package has only one NE pin. STM32H743 has two - NE1 and NE2. #ifdef PF0 switch (nsBank) { - #if defined(FMC_NORSRAM_DEVICE) + #ifdef FMC_NORSRAM_DEVICE case FMC_NORSRAM_BANK2: controllerAddress = FMC_BANK1_2 ; break; case FMC_NORSRAM_BANK3: controllerAddress = FMC_BANK1_3 ; break; case FMC_NORSRAM_BANK4: controllerAddress = FMC_BANK1_4 ; break; @@ -233,4 +233,4 @@ void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) } #endif // HAS_FSMC_TFT -#endif // HAL_STM32 \ No newline at end of file +#endif // HAL_STM32 diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index d6eeb8a02bb8..b34454d628d6 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -96,8 +96,9 @@ class TFT_FSMC { } }; -#if defined(FMC_NORSRAM_DEVICE) // Flexible Memory Controller on STM32F446 - #if defined(STM32F4xx) +#ifdef FMC_NORSRAM_DEVICE // Flexible Memory Controller on STM32F446 + + #ifdef STM32F4xx #define FMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC) #define FMC_BANK1_1 0x60000000U #define FMC_BANK1_2 0x64000000U @@ -136,19 +137,19 @@ class TFT_FSMC { }; const PinMap pinMap_FMC_CS[] = { - {PD_7, (void *)FMC_NORSRAM_BANK1, FMC_PIN_DATA}, // FMC_NE1 - #ifdef PF0 - {PG_9, (void *)FMC_NORSRAM_BANK2, FMC_PIN_DATA}, // FMC_NE2 - {PG_10, (void *)FMC_NORSRAM_BANK3, FMC_PIN_DATA}, // FMC_NE3 - {PG_12, (void *)FMC_NORSRAM_BANK4, FMC_PIN_DATA}, // FMC_NE4 - #endif - {NC, NP, 0} + {PD_7, (void *)FMC_NORSRAM_BANK1, FMC_PIN_DATA}, // FMC_NE1 + #ifdef PF0 + {PG_9, (void *)FMC_NORSRAM_BANK2, FMC_PIN_DATA}, // FMC_NE2 + {PG_10, (void *)FMC_NORSRAM_BANK3, FMC_PIN_DATA}, // FMC_NE3 + {PG_12, (void *)FMC_NORSRAM_BANK4, FMC_PIN_DATA}, // FMC_NE4 + #endif + {NC, NP, 0} }; #if ENABLED(TFT_INTERFACE_FMC_8BIT) - #define FMC_RS(A) (void *)((2 << (A-1)) - 1) + #define FMC_RS(A) (void *)((2 << (A - 1)) - 1) #else - #define FMC_RS(A) (void *)((2 << A) - 2) + #define FMC_RS(A) (void *)((2 << A) - 2) #endif const PinMap pinMap_FMC_RS[] = { @@ -184,7 +185,9 @@ class TFT_FSMC { #endif {NC, NP, 0} }; + #elif defined(FSMC_NORSRAM_DEVICE) // Flexible Static Memory Controller on STM32F103 and STM32F407 + #ifdef STM32F1xx #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) #elif defined(STM32F4xx) @@ -276,4 +279,4 @@ class TFT_FSMC { }; #else #error "Selected MCU does not support FSMC/FMC" -#endif \ No newline at end of file +#endif diff --git a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h index e32f2b52cfc8..fe671fc903a6 100644 --- a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h +++ b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h @@ -22,7 +22,7 @@ /** * BOARD_TRONXY_CXY_446_V10 - * + * * CXY-V6-191121 / CXY-446-V10-220413 */ @@ -54,125 +54,125 @@ // // SPI Flash // -#define SPI_FLASH // W25Q16 +#define SPI_FLASH // W25Q16 #if ENABLED(SPI_FLASH) - #define SPI_DEVICE 1 + #define SPI_DEVICE 1 #define SPI_FLASH_SIZE 0x1000000 // 16MB // SPI1/SPI3 - #define SPI_FLASH_CS_PIN PG15 // W25Q16 CS - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT - #define SPI_FLASH_MOSI_PIN PB5 // W25Q16 DIN - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, FMC_SDCKE1, DCMI_D10, EVENTOUT - #define SPI_FLASH_MISO_PIN PB4 // W25Q16 DOUT - NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, EVENTOUT - #define SPI_FLASH_SCK_PIN PB3 // W25Q16 DCLK - JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, EVENTOUT + #define SPI_FLASH_CS_PIN PG15 // W25Q16 CS - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT + #define SPI_FLASH_MOSI_PIN PB5 // W25Q16 DIN - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, FMC_SDCKE1, DCMI_D10, EVENTOUT + #define SPI_FLASH_MISO_PIN PB4 // W25Q16 DOUT - NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, EVENTOUT + #define SPI_FLASH_SCK_PIN PB3 // W25Q16 DCLK - JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, EVENTOUT #endif // // Limit Switches // -#define X_STOP_PIN PC15 // X STOP SW - EVENTOUT, OSC32_OUT +#define X_STOP_PIN PC15 // X STOP SW - EVENTOUT, OSC32_OUT -#define X_MIN_PIN X_STOP_PIN -#define X_MAX_PIN PB0 // E0 TMC UART candidate - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUT, ADC12_IN8 +#define X_MIN_PIN X_STOP_PIN +#define X_MAX_PIN PB0 // E0 TMC UART candidate - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUT, ADC12_IN8 -#define Y_STOP_PIN PC14 // Y STOP SW - EVENTOUT, OSC32_IN +#define Y_STOP_PIN PC14 // Y STOP SW - EVENTOUT, OSC32_IN #if ENABLED(Z_MULTI_ENDSTOPS) - #if X_HOME_DIR > 0 // Swap Z1/Z2 for dual Z with max homing - #define Z_MIN_PIN PF11 // Z2 STOP SW - SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT - #define Z_MAX_PIN PC13 // Z STOP SW - EVENTOUT, TAMP_1/WKUP1 + #if X_HOME_DIR > 0 // Swap Z1/Z2 for dual Z with max homing + #define Z_MIN_PIN PF11 // Z2 STOP SW - SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT + #define Z_MAX_PIN PC13 // Z STOP SW - EVENTOUT, TAMP_1/WKUP1 #else - #define Z_MIN_PIN PC13 // Z STOP SW - #define Z_MAX_PIN PF11 // Z2 STOP SW + #define Z_MIN_PIN PC13 // Z STOP SW + #define Z_MAX_PIN PF11 // Z2 STOP SW #endif // PE3 is usually connected to Probe #if ENABLED(FIX_MOUNTED_PROBE) - #define Z_MIN_PROBE_PIN PE3 // BED PROBE - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT + #define Z_MIN_PROBE_PIN PE3 // BED PROBE - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT #endif #elif ENABLED(FIX_MOUNTED_PROBE) - #define Z_STOP_PIN PE3 // BED PROBE + #define Z_STOP_PIN PE3 // BED PROBE #else - #define Z_STOP_PIN PC13 // Z STOP SW + #define Z_STOP_PIN PC13 // Z STOP SW #endif // // Filament Sensors // #if ENABLED(FILAMENT_RUNOUT_SENSOR) - #define FIL_RUNOUT_PIN PE6 // E0 STOP SW - TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, EVENTOUT + #define FIL_RUNOUT_PIN PE6 // E0 STOP SW - TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, EVENTOUT #if NUM_RUNOUT_SENSORS == 2 - #define FIL_RUNOUT2_PIN PF12 // E1 STOP SW - FMC_A6, EVENTOUT + #define FIL_RUNOUT2_PIN PF12 // E1 STOP SW - FMC_A6, EVENTOUT #endif #endif // // Steppers // -#define X_ENABLE_PIN PF0 // X TMC2225 EN - I2C2_SDA, FMC_A0, EVENTOUT -#define X_STEP_PIN PE5 // X TMC2225 STEP - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, EVENTOUT -#define X_DIR_PIN PF1 // X TMC2225 DIR - I2C2_SCL, FMC_A1, EVENTOUT +#define X_ENABLE_PIN PF0 // X TMC2225 EN - I2C2_SDA, FMC_A0, EVENTOUT +#define X_STEP_PIN PE5 // X TMC2225 STEP - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, EVENTOUT +#define X_DIR_PIN PF1 // X TMC2225 DIR - I2C2_SCL, FMC_A1, EVENTOUT -#define Y_ENABLE_PIN PF5 // Y TMC2225 EN - FMC_A5, EVENTOUT, ADC3_IN15 -#define Y_STEP_PIN PF9 // Y TMC2225 STEP - SAI1_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT, ADC3_IN7 -#define Y_DIR_PIN PF3 // Y TMC2225 DIR - FMC_A3, EVENTOUT, ADC3_IN9 +#define Y_ENABLE_PIN PF5 // Y TMC2225 EN - FMC_A5, EVENTOUT, ADC3_IN15 +#define Y_STEP_PIN PF9 // Y TMC2225 STEP - SAI1_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT, ADC3_IN7 +#define Y_DIR_PIN PF3 // Y TMC2225 DIR - FMC_A3, EVENTOUT, ADC3_IN9 -#define Z_ENABLE_PIN PA5 // Z TMC2225 EN - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT, ADC12_IN5, DAC_OUT2 -#define Z_STEP_PIN PA6 // Z TMC2225 STEP - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, DCMI_PIXCLK, EVENTOUT, ADC12_IN6 -#define Z_DIR_PIN PF15 // Z TMC2225 DIR - FMPI2C1_SDA, FMC_A9, EVENTOUT +#define Z_ENABLE_PIN PA5 // Z TMC2225 EN - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT, ADC12_IN5, DAC_OUT2 +#define Z_STEP_PIN PA6 // Z TMC2225 STEP - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, DCMI_PIXCLK, EVENTOUT, ADC12_IN6 +#define Z_DIR_PIN PF15 // Z TMC2225 DIR - FMPI2C1_SDA, FMC_A9, EVENTOUT #ifdef Z2_DRIVER_TYPE - #define Z2_ENABLE_PIN PF7 // Z2 TMC2225 EN - TIM11_CH1, SAI1_MCLK_B, QUADSPI_BK1_IO2, EVENTOUT, ADC3_IN5 - #define Z2_STEP_PIN PF6 // Z2 TMC2225 STEP - TIM10_CH1, SAI1_SD_B, QUADSPI_BK1_IO3, EVENTOUT, ADC3_IN4 - #define Z2_DIR_PIN PF4 // Z2 TMC2225 DIR - FMC_A4, EVENTOUT, ADC3_IN14 + #define Z2_ENABLE_PIN PF7 // Z2 TMC2225 EN - TIM11_CH1, SAI1_MCLK_B, QUADSPI_BK1_IO2, EVENTOUT, ADC3_IN5 + #define Z2_STEP_PIN PF6 // Z2 TMC2225 STEP - TIM10_CH1, SAI1_SD_B, QUADSPI_BK1_IO3, EVENTOUT, ADC3_IN4 + #define Z2_DIR_PIN PF4 // Z2 TMC2225 DIR - FMC_A4, EVENTOUT, ADC3_IN14 #endif -#define E0_ENABLE_PIN PF14 // E0 TMC2225 EN - FMPI2C1_SCL, FMC_A8, EVENTOUT -#define E0_STEP_PIN PB1 // E0 TMC2225 STEP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, SDIO_D2, EVENTOUT, ADC12_IN9 -#define E0_DIR_PIN PF13 // E0 TMC2225 DIR - FMPI2C1_SMBA, FMC_A7, EVENTOUT +#define E0_ENABLE_PIN PF14 // E0 TMC2225 EN - FMPI2C1_SCL, FMC_A8, EVENTOUT +#define E0_STEP_PIN PB1 // E0 TMC2225 STEP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, SDIO_D2, EVENTOUT, ADC12_IN9 +#define E0_DIR_PIN PF13 // E0 TMC2225 DIR - FMPI2C1_SMBA, FMC_A7, EVENTOUT #if (EXTRUDERS == 2) #ifndef E1_DRIVER_TYPE #error "E1_DRIVER_TYPE must be defined in Configuration.h to use 2 extruders!" #else - #define E1_ENABLE_PIN PG5 // E1 TMC2225 EN - FMC_A15/FMC_BA1, EVENTOUT - #define E1_STEP_PIN PD12 // E1 TMC2225 STEP - TIM4_CH1, FMPI2C1_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, EVENTOUT - #define E1_DIR_PIN PG4 // E1 TMC2225 DIR - FMC_A14/FMC_BA0, EVENTOUT + #define E1_ENABLE_PIN PG5 // E1 TMC2225 EN - FMC_A15/FMC_BA1, EVENTOUT + #define E1_STEP_PIN PD12 // E1 TMC2225 STEP - TIM4_CH1, FMPI2C1_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, EVENTOUT + #define E1_DIR_PIN PG4 // E1 TMC2225 DIR - FMC_A14/FMC_BA0, EVENTOUT #endif #endif #if HAS_TMC_UART /** * TMC2208/TMC2209 Software Serial - * + * * Only uses 1 pin for UART * Modification to board required. - * + * * Use at your own risk!!! - * + * * Instructions: https://zenn.dev/marbocub/articles/tronxy-stm32f4-mainboard-tmc-serial-wiring */ // Comment out error line below once pins have been configured to continue. #error "TMC UART not supported by default on this board. Modification to board required. See pins_TRONXY_CXY_446_V10.h for details." /* - #define X_SERIAL_TX_PIN PE4 // TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, EVENTOUT + #define X_SERIAL_TX_PIN PE4 // TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, EVENTOUT #define X_SERIAL_RX_PIN X_SERIAL_TX_PIN - #define Y_SERIAL_TX_PIN PF2 // I2C2_SMBA, FMC_A2, EVENTOUT + #define Y_SERIAL_TX_PIN PF2 // I2C2_SMBA, FMC_A2, EVENTOUT #define Y_SERIAL_RX_PIN Y_SERIAL_TX_PIN - #define Z_SERIAL_TX_PIN PA4 // SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, EVENTOUTADC12_IN4, DAC_OUT1 + #define Z_SERIAL_TX_PIN PA4 // SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, EVENTOUTADC12_IN4, DAC_OUT1 #define Z_SERIAL_RX_PIN Z_SERIAL_TX_PIN - + #ifdef Z2_DRIVER_TYPE - #define Z2_SERIAL_TX_PIN PF8 // SAI1_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT + #define Z2_SERIAL_TX_PIN PF8 // SAI1_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT #define Z2_SERIAL_RX_PIN Z2_SERIAL_TX_PIN #endif - #define E0_SERIAL_TX_PIN PB0 // TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUTADC12_IN8 + #define E0_SERIAL_TX_PIN PB0 // TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUTADC12_IN8 #define E0_SERIAL_RX_PIN E0_SERIAL_TX_PIN // Unsure on this pin assignment - //#define E1_SERIAL_TX_PIN PD5 // USART2_TX, FMC_NWE, EVENTOUT + //#define E1_SERIAL_TX_PIN PD5 // USART2_TX, FMC_NWE, EVENTOUT //#define E1_SERIAL_RX_PIN E1_SERIAL_TX_PIN */ #endif @@ -180,56 +180,56 @@ // // Temperature Sensors // -#define TEMP_0_PIN PC3 // Hotend #1 Therm - SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT, ADC123_IN13 +#define TEMP_0_PIN PC3 // Hotend #1 Therm - SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT, ADC123_IN13 #if EXTRUDERS == 2 - #define TEMP_1_PIN PC0 // Hotend #2 Therm - SAI1_MCLK_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT, ADC123_IN10 + #define TEMP_1_PIN PC0 // Hotend #2 Therm - SAI1_MCLK_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT, ADC123_IN10 #endif -#define TEMP_BED_PIN PC2 // Bed Therm - SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT, ADC123_IN12 +#define TEMP_BED_PIN PC2 // Bed Therm - SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT, ADC123_IN12 // // Heaters -// -#define HEATER_0_PIN PG7 // Hotend #1 Heater - USART6_CK, FMC_INT, DCMI_D13, EVENTOUT +// +#define HEATER_0_PIN PG7 // Hotend #1 Heater - USART6_CK, FMC_INT, DCMI_D13, EVENTOUT #if EXTRUDERS == 2 - #define HEATER_1_PIN PA15 // Hotend #2 Heater - JTDI, TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT + #define HEATER_1_PIN PA15 // Hotend #2 Heater - JTDI, TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT #endif -#define HEATER_BED_PIN PE2 // Bed Heater - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT +#define HEATER_BED_PIN PE2 // Bed Heater - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT // // Fans // -#define FAN0_PIN PG0 // Part Cooling Fan #1 - FMC_A10, EVENTOUT +#define FAN0_PIN PG0 // Part Cooling Fan #1 - FMC_A10, EVENTOUT #if EXTRUDERS == 2 - #define FAN1_PIN PB6 // Part Cooling Fan #2 - TIM4_CH1, HDMI_CEC, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, FMC_SDNE1, DCMI_D5, EVENTOUT - #define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT - #define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan - DCMI_D11, EVENTOUT, ADC3_IN8 + #define FAN1_PIN PB6 // Part Cooling Fan #2 - TIM4_CH1, HDMI_CEC, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, FMC_SDNE1, DCMI_D5, EVENTOUT + #define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT + #define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan - DCMI_D11, EVENTOUT, ADC3_IN8 #else - #define FAN1_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT + #define FAN1_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT #endif -#define CONTROLLER_FAN_PIN PD7 // USART2_CK, SPDIFRX_IN0, FMC_NE1, EVENTOUT +#define CONTROLLER_FAN_PIN PD7 // USART2_CK, SPDIFRX_IN0, FMC_NE1, EVENTOUT // Define so that hotend heatsink fans automatically start when hotends reach 50 degrees. #if EXTRUDERS == 2 #undef E0_AUTO_FAN_PIN #undef E1_AUTO_FAN_PIN - #define E0_AUTO_FAN_PIN FAN2_PIN - #define E1_AUTO_FAN_PIN FAN3_PIN + #define E0_AUTO_FAN_PIN FAN2_PIN + #define E1_AUTO_FAN_PIN FAN3_PIN #else #undef E0_AUTO_FAN_PIN - #define E0_AUTO_FAN_PIN FAN1_PIN + #define E0_AUTO_FAN_PIN FAN1_PIN #endif -#define FAN_SOFT_PWM_REQUIRED +#define FAN_SOFT_PWM_REQUIRED // -// Laser / Servos -// +// Laser / Servos +// // NOTE: SPINDLE_LASER_PWM_PIN and SERVO0_PIN are the same pin. // Only one feature can be enabled at a time. // @@ -237,9 +237,9 @@ #if NUM_SERVOS > 0 #error "NUM_SERVOS must equal 0 to enable LASER_FEATURE" #else - #define SPINDLE_LASER_ENA_PIN PB11 // WiFi TXD (Pin5) - TIM2_CH4, I2C2_SDA, USART3_RX, SAI2_SD_A, EVENTOUT + #define SPINDLE_LASER_ENA_PIN PB11 // WiFi TXD (Pin5) - TIM2_CH4, I2C2_SDA, USART3_RX, SAI2_SD_A, EVENTOUT #if ENABLED(SPINDLE_LASER_USE_PWM) - #define SPINDLE_LASER_PWM_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT + #define SPINDLE_LASER_PWM_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT /** * NOTE: The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be compounded here. * See PWM_PIN(x) definition for details. @@ -248,16 +248,16 @@ #endif #endif -#if NUM_SERVOS > 0 +#if NUM_SERVOS > 0 #if ENABLED(LASER_FEATURE) #error "LASER_FEATURE must be disabled to set NUM_SERVOS greater than 0" #elif NUM_SERVOS > 1 #error "Only one servo is currently supported" #else - #define SERVO0_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT - /** + #define SERVO0_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT + /** * Enabled after enabling NUM_SERVOS > 0. - * + * * NOTE: Shares PB10 pin with laser. Features cannot be enabled at the same time. */ #endif @@ -269,24 +269,24 @@ #if ANY(TFT_TRONXY_X5SA, MKS_ROBIN_TFT43) //SPI2 - #define TOUCH_CS_PIN PD11 // TOUCH SCREEN HR2046 CS - FMPI2C1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT - #define TOUCH_SCK_PIN PB13 // TOUCH SCREEN HR2046 DCLK - TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, EVENTOUT - #define TOUCH_MISO_PIN PB14 // TOUCH SCREEN HR2046 DOUT - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT - #define TOUCH_MOSI_PIN PB15 // TOUCH SCREEN HR2046 DIN - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, EVENTOUT + #define TOUCH_CS_PIN PD11 // TOUCH SCREEN HR2046 CS - FMPI2C1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT + #define TOUCH_SCK_PIN PB13 // TOUCH SCREEN HR2046 DCLK - TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, EVENTOUT + #define TOUCH_MISO_PIN PB14 // TOUCH SCREEN HR2046 DOUT - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT + #define TOUCH_MOSI_PIN PB15 // TOUCH SCREEN HR2046 DIN - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, EVENTOUT - #define TFT_RESET_PIN PB12 // TOUCH SCREEN HR2046 CS - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SAI1_SCK_B, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT - #define TFT_BACKLIGHT_PIN PG8 // LCD MODULE BACKLIGHT - SPDIFRX_IN2, USART6_RTS, FMC_SDCLK, EVENTOUT + #define TFT_RESET_PIN PB12 // TOUCH SCREEN HR2046 CS - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SAI1_SCK_B, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT + #define TFT_BACKLIGHT_PIN PG8 // LCD MODULE BACKLIGHT - SPDIFRX_IN2, USART6_RTS, FMC_SDCLK, EVENTOUT #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT #define FSMC_DMA_DEV DMA2 - #define FSMC_DMA_CHANNEL DMA_CH5 + #define FSMC_DMA_CHANNEL DMA_CH5 + + #define TFT_CS_PIN PG12 // SPI4_MISO, SPDIFRX_IN1, USART6_RTS, FMC_NE4, EVENTOUT + #define TFT_RS_PIN PG2 // FMC_A12, EVENTOUT - #define TFT_CS_PIN PG12 // SPI4_MISO, SPDIFRX_IN1, USART6_RTS, FMC_NE4, EVENTOUT - #define TFT_RS_PIN PG2 // FMC_A12, EVENTOUT + #define FSMC_CS_PIN TFT_CS_PIN + #define FSMC_RS_PIN TFT_RS_PIN - #define FSMC_CS_PIN TFT_CS_PIN - #define FSMC_RS_PIN TFT_RS_PIN - #if ENABLED(TFT_LVGL_UI) #define HAS_SPI_FLASH_FONT 1 #define HAS_GCODE_PREVIEW 1 @@ -295,7 +295,7 @@ #define HAS_BAK_VIEW_IN_FLASH 0 #define HAS_LOGO_IN_FLASH 0 #elif ENABLED(TFT_COLOR_UI) - #define TFT_DRIVER ILI9488 + #define TFT_DRIVER ILI9488 #define TFT_BUFFER_SIZE 14400 #endif @@ -310,15 +310,15 @@ #undef TOUCH_OFFSET_Y #endif #if ENABLED(TFT_TRONXY_X5SA) - #define TOUCH_CALIBRATION_X -17181 - #define TOUCH_CALIBRATION_Y 11434 - #define TOUCH_OFFSET_X 501 - #define TOUCH_OFFSET_Y -9 + #define TOUCH_CALIBRATION_X -17181 + #define TOUCH_CALIBRATION_Y 11434 + #define TOUCH_OFFSET_X 501 + #define TOUCH_OFFSET_Y -9 #elif ENABLED(MKS_ROBIN_TFT43) - #define XPT2046_X_CALIBRATION 17184 - #define XPT2046_Y_CALIBRATION 10604 - #define XPT2046_X_OFFSET -31 - #define XPT2046_Y_OFFSET -29 + #define XPT2046_X_CALIBRATION 17184 + #define XPT2046_Y_CALIBRATION 10604 + #define XPT2046_X_OFFSET -31 + #define XPT2046_Y_OFFSET -29 #endif #endif #else @@ -336,37 +336,37 @@ // SD Card #define ONBOARD_SDIO -#define SD_DETECT_PIN -1 +#define SD_DETECT_PIN -1 #define SDIO_CLOCK 4500000 -#define SDIO_READ_RETRIES 16 +#define SDIO_READ_RETRIES 16 -#define SDIO_D0_PIN PC8 // TRACED0, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT -#define SDIO_D1_PIN PC9 // MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDIO_D1, DCMI_D3, EVENTOUT -#define SDIO_D2_PIN PC10 // SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDIO_D2, DCMI_D8, EVENTOUT -#define SDIO_D3_PIN PC11 // SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDIO_D3, DCMI_D4, EVENTOUT -#define SDIO_CK_PIN PC12 // I2C2_SDA, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, EVENTOUT -#define SDIO_CMD_PIN PD2 // TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT +#define SDIO_D0_PIN PC8 // TRACED0, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT +#define SDIO_D1_PIN PC9 // MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDIO_D1, DCMI_D3, EVENTOUT +#define SDIO_D2_PIN PC10 // SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDIO_D2, DCMI_D8, EVENTOUT +#define SDIO_D3_PIN PC11 // SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDIO_D3, DCMI_D4, EVENTOUT +#define SDIO_CK_PIN PC12 // I2C2_SDA, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, EVENTOUT +#define SDIO_CMD_PIN PD2 // TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT // // Power Loss / Power Supply Control -// +// // NOTE: PS_ON_PIN and LED_PIN are the same pin. // #if ENABLED(PSU_CONTROL) // LED - Temporarily switch the machine with LED simulation - #define PS_ON_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT + #define PS_ON_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT // 24V DET - Output of LM393 comparator, configured as pullup - #define POWER_LOSS_PIN PE1 // FMC_NBL1, DCMI_D3, EVENTOUT + #define POWER_LOSS_PIN PE1 // FMC_NBL1, DCMI_D3, EVENTOUT // +V for the LM393 comparator, configured as output high - #define POWER_LM393_PIN PE0 // TIM4_ETR, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT + #define POWER_LM393_PIN PE0 // TIM4_ETR, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT #endif // // Misc // #ifndef PS_ON_PIN - #define LED_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT + #define LED_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT #endif -#define BEEPER_PIN PA8 // MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT \ No newline at end of file +#define BEEPER_PIN PA8 // MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT diff --git a/buildroot/share/PlatformIO/scripts/tronxy_script.py b/buildroot/share/PlatformIO/scripts/tronxy_script.py index 5483fd37cfb1..b414f24c6016 100644 --- a/buildroot/share/PlatformIO/scripts/tronxy_script.py +++ b/buildroot/share/PlatformIO/scripts/tronxy_script.py @@ -1,42 +1,45 @@ +# +# tronxy_script.py +# +import pioutil +if pioutil.is_pio_build(): -import marlin -import os - -from SCons.Script import DefaultEnvironment - -env = DefaultEnvironment() -board = env.BoardConfig() -if 'offset' in board.get("build").keys(): - marlin.relocate_vtab(board.get('build.offset')) - -path = "update" -# Check whether the "update" folder exists -isExist = os.path.exists(path) -if not isExist: - # Create the "update" folder - os.makedirs(path) - -#build "fmw_tronxy.hex" and place in "update" folder -def output_target_hex(): - tar_hex = "update/fmw_tronxy.hex" - env.AddPostAction( - "$BUILD_DIR/${PROGNAME}.elf", - env.VerboseAction(" ".join([ - "$OBJCOPY", "-O", "ihex", "-R", ".eeprom", - "$BUILD_DIR/${PROGNAME}.elf", tar_hex - ]), "Building %s" % tar_hex) - ) - -#build "fmw_tronxy.bin" and place in "update" folder -def output_target_bin(): - tar_bin = "update/fmw_tronxy.bin" - env.AddPostAction( - "$BUILD_DIR/${PROGNAME}.elf", - env.VerboseAction(" ".join([ - "$OBJCOPY", "-O", "binary", "-R", ".eeprom", - "$BUILD_DIR/${PROGNAME}.elf", tar_bin - ]), "Building %s" % tar_bin) - ) - -output_target_hex() -output_target_bin() + import marlin, os + + from SCons.Script import DefaultEnvironment + + env = DefaultEnvironment() + + # Already handled by offset_and_rename.py + #board = env.BoardConfig() + #if 'offset' in board.get("build").keys(): + # marlin.relocate_vtab(board.get('build.offset')) + + # Check whether the "update" folder exists + outpath = "update" + if not os.path.exists(outpath): os.makedirs(outpath) + + # Build "fmw_tronxy.hex" and place in "update" folder + def output_target_hex(): + tar_hex = f"{outpath}/fmw_tronxy.hex" + env.AddPostAction( + "$BUILD_DIR/${PROGNAME}.elf", + env.VerboseAction(" ".join([ + "$OBJCOPY", "-O", "ihex", "-R", ".eeprom", + "$BUILD_DIR/${PROGNAME}.elf", tar_hex + ]), "Building %s" % tar_hex) + ) + + # Build "fmw_tronxy.bin" and place in "update" folder + def output_target_bin(): + tar_bin = f"{outpath}/fmw_tronxy.bin" + env.AddPostAction( + "$BUILD_DIR/${PROGNAME}.elf", + env.VerboseAction(" ".join([ + "$OBJCOPY", "-O", "binary", "-R", ".eeprom", + "$BUILD_DIR/${PROGNAME}.elf", tar_bin + ]), "Building %s" % tar_bin) + ) + + output_target_hex() + output_target_bin() diff --git a/ini/renamed.ini b/ini/renamed.ini index 84f6acd7fab9..85f2df286273 100644 --- a/ini/renamed.ini +++ b/ini/renamed.ini @@ -95,3 +95,6 @@ extends = renamed [env:STM32F407ZE_btt_USB] ;=> STM32F407ZE_btt_usb_flash_drive extends = renamed + +[env:STM32F446_tronxy] ;=> TRONXY_CXY_446_V10 +extends = renamed diff --git a/ini/stm32f4.ini b/ini/stm32f4.ini index eda59c7b45a2..5b28edbf18ac 100644 --- a/ini/stm32f4.ini +++ b/ini/stm32f4.ini @@ -817,9 +817,8 @@ upload_command = dfu-util -a 0 -s 0x08000000:leave -D "$SOURCE" [env:TRONXY_CXY_446_V10] extends = stm32_variant board = marlin_STM32F446ZET_tronxy -board_build.offset = 0x10000 board_build.ldscript = buildroot/share/PlatformIO/variants/MARLIN_F446Zx_TRONXY/ldscript.ld -build_src_filter = ${common_stm32.build_src_filter} +board_build.offset = 0x10000 board_build.rename = fmw_tronxy.bin build_flags = ${stm32_variant.build_flags} -DSTM32F4xx -DUSE_USBHOST_FS @@ -834,12 +833,12 @@ extra_scripts = ${stm32_variant.extra_scripts} # [env:TRONXY_CXY_446_V10_usb_flash_drive] extends = env:TRONXY_CXY_446_V10 -platform_packages = ${stm_flash_drive.platform_packages} -build_flags = ${common_stm32.build_flags} - -DHAL_PCD_MODULE_ENABLED -DUSBHOST +platform_packages = ${stm_flash_drive.platform_packages} +build_flags = ${env:TRONXY_CXY_446_V10.build_flags} + -DHAL_PCD_MODULE_ENABLED -DUSBHOST -DUSBH_IRQ_PRIO=3 -DUSBH_IRQ_SUBPRIO=4 -DUSBHOST_HS_EN=1 - + # # Blackpill # From 96d54839821721e771f731149891ba9d90416446 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Mon, 29 Jan 2024 16:49:01 -0600 Subject: [PATCH 04/22] rename script --- .../scripts/{tronxy_script.py => tronxy_cxy_446_v10.py} | 3 ++- ini/stm32f4.ini | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) rename buildroot/share/PlatformIO/scripts/{tronxy_script.py => tronxy_cxy_446_v10.py} (94%) diff --git a/buildroot/share/PlatformIO/scripts/tronxy_script.py b/buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py similarity index 94% rename from buildroot/share/PlatformIO/scripts/tronxy_script.py rename to buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py index b414f24c6016..eb89791e561f 100644 --- a/buildroot/share/PlatformIO/scripts/tronxy_script.py +++ b/buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py @@ -1,5 +1,6 @@ # -# tronxy_script.py +# tronxy_cxy_446_v10.py +# Build customizations for env:TRONXY_CXY_446_V10 # import pioutil if pioutil.is_pio_build(): diff --git a/ini/stm32f4.ini b/ini/stm32f4.ini index 5b28edbf18ac..99ccf30d329a 100644 --- a/ini/stm32f4.ini +++ b/ini/stm32f4.ini @@ -826,7 +826,7 @@ build_unflags = ${stm32_variant.build_unflags} -fno-rtti -fno-threadsafe-statics -fno-exceptions -DUSBD_USE_CDC -DUSBCON extra_scripts = ${stm32_variant.extra_scripts} - buildroot/share/PlatformIO/scripts/tronxy_script.py + buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py # # TRONXY_CXY_446_V10 (STM32F446ZET6 ARM Cortex-M4) with USB Flash Drive Support From c0fb654a97bc1f3fffe214fd1cd672cf636d70af Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Mon, 29 Jan 2024 16:54:54 -0600 Subject: [PATCH 05/22] etc --- .../pins/stm32f4/pins_TRONXY_CXY_446_V10.h | 38 ++++++++++--------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h index fe671fc903a6..5c5080259f9a 100644 --- a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h +++ b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h @@ -1,6 +1,6 @@ /** * Marlin 3D Printer Firmware - * Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin] + * Copyright (c) 2024 MarlinFirmware [https://github.com/MarlinFirmware/Marlin] * * Based on Sprinter and grbl. * Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm @@ -37,8 +37,8 @@ #define BOARD_INFO_NAME "BOARD_TRONXY_CXY_446_V10" #define DEFAULT_MACHINE_NAME BOARD_INFO_NAME -#define STEP_TIMER 6 -#define TEMP_TIMER 14 +#define STEP_TIMER 6 +#define TEMP_TIMER 14 // // EEPROM @@ -48,17 +48,17 @@ #if NO_EEPROM_SELECTED #undef NO_EEPROM_SELECTED #define I2C_EEPROM - #define MARLIN_EEPROM_SIZE 0x800 // 2K (FT24C16A) + #define MARLIN_EEPROM_SIZE 0x800 // 2K (FT24C16A) #endif // -// SPI Flash +// SPI Flash // #define SPI_FLASH // W25Q16 #if ENABLED(SPI_FLASH) #define SPI_DEVICE 1 - #define SPI_FLASH_SIZE 0x1000000 // 16MB + #define SPI_FLASH_SIZE 0x1000000 // 16MB // SPI1/SPI3 #define SPI_FLASH_CS_PIN PG15 // W25Q16 CS - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT #define SPI_FLASH_MOSI_PIN PB5 // W25Q16 DIN - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, FMC_SDCKE1, DCMI_D10, EVENTOUT @@ -152,7 +152,7 @@ * Instructions: https://zenn.dev/marbocub/articles/tronxy-stm32f4-mainboard-tmc-serial-wiring */ // Comment out error line below once pins have been configured to continue. - #error "TMC UART not supported by default on this board. Modification to board required. See pins_TRONXY_CXY_446_V10.h for details." + #error "TMC UART not supported by default on this board. Board modification required. See pins_TRONXY_CXY_446_V10.h for details." /* #define X_SERIAL_TX_PIN PE4 // TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, EVENTOUT #define X_SERIAL_RX_PIN X_SERIAL_TX_PIN @@ -205,11 +205,11 @@ #define FAN0_PIN PG0 // Part Cooling Fan #1 - FMC_A10, EVENTOUT #if EXTRUDERS == 2 - #define FAN1_PIN PB6 // Part Cooling Fan #2 - TIM4_CH1, HDMI_CEC, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, FMC_SDNE1, DCMI_D5, EVENTOUT - #define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT - #define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan - DCMI_D11, EVENTOUT, ADC3_IN8 + #define FAN1_PIN PB6 // Part Cooling Fan #2 - TIM4_CH1, HDMI_CEC, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, FMC_SDNE1, DCMI_D5, EVENTOUT + #define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT + #define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan - DCMI_D11, EVENTOUT, ADC3_IN8 #else - #define FAN1_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT + #define FAN1_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT #endif #define CONTROLLER_FAN_PIN PD7 // USART2_CK, SPDIFRX_IN0, FMC_NE1, EVENTOUT @@ -268,7 +268,7 @@ // #if ANY(TFT_TRONXY_X5SA, MKS_ROBIN_TFT43) - //SPI2 + // SPI2 #define TOUCH_CS_PIN PD11 // TOUCH SCREEN HR2046 CS - FMPI2C1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT #define TOUCH_SCK_PIN PB13 // TOUCH SCREEN HR2046 DCLK - TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, EVENTOUT #define TOUCH_MISO_PIN PB14 // TOUCH SCREEN HR2046 DOUT - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT @@ -277,7 +277,7 @@ #define TFT_RESET_PIN PB12 // TOUCH SCREEN HR2046 CS - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SAI1_SCK_B, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT #define TFT_BACKLIGHT_PIN PG8 // LCD MODULE BACKLIGHT - SPDIFRX_IN2, USART6_RTS, FMC_SDCLK, EVENTOUT - #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT + #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT #define FSMC_DMA_DEV DMA2 #define FSMC_DMA_CHANNEL DMA_CH5 @@ -295,11 +295,11 @@ #define HAS_BAK_VIEW_IN_FLASH 0 #define HAS_LOGO_IN_FLASH 0 #elif ENABLED(TFT_COLOR_UI) - #define TFT_DRIVER ILI9488 + #define TFT_DRIVER ILI9488 #define TFT_BUFFER_SIZE 14400 #endif - //Touch Screen calibration + // Touch Screen calibration #if ANY(TFT_LVGL_UI, TFT_COLOR_UI, TFT_CLASSIC_UI) #if DISABLED(TOUCH_SCREEN_CALIBRATION) #error "TFT screen requires TOUCH_SCREEN_CALIBRATION" @@ -334,10 +334,12 @@ #define HAS_OTG_USB_HOST_SUPPORT #endif +// // SD Card +// #define ONBOARD_SDIO -#define SD_DETECT_PIN -1 -#define SDIO_CLOCK 4500000 +#define SD_DETECT_PIN -1 // PF0, but not connected +#define SDIO_CLOCK 4500000 #define SDIO_READ_RETRIES 16 #define SDIO_D0_PIN PC8 // TRACED0, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT @@ -363,7 +365,7 @@ #endif // -// Misc +// Misc. Functions // #ifndef PS_ON_PIN #define LED_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT From bc288bbc2d9327b5b0f661b92302e168ec2c5bd8 Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Tue, 30 Jan 2024 12:57:05 -0600 Subject: [PATCH 06/22] Update tft_fsmc.h Rework code to fix broken build on Lerdge boards. --- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 422 ++++++++++++---------------- 1 file changed, 186 insertions(+), 236 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index b34454d628d6..02324c2694a0 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -19,264 +19,214 @@ * along with this program. If not, see . * */ -#pragma once -#include "../../../inc/MarlinConfig.h" - -#ifdef STM32F1xx - #include "stm32f1xx_hal.h" -#elif defined(STM32F4xx) - #include "stm32f4xx_hal.h" -#else - #error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware." -#endif - -#ifndef HAL_SRAM_MODULE_ENABLED - #error "SRAM module disabled for the STM32 framework (HAL_SRAM_MODULE_ENABLED)! Please consult the development team." -#endif - -#ifndef LCD_READ_ID - #define LCD_READ_ID 0x04 // Read display identification information (0xD3 on ILI9341) -#endif -#ifndef LCD_READ_ID4 - #define LCD_READ_ID4 0xD3 // Read display identification information (0xD3 on ILI9341) -#endif - -#define DATASIZE_8BIT SPI_DATASIZE_8BIT -#define DATASIZE_16BIT SPI_DATASIZE_16BIT -#define TFT_IO_DRIVER TFT_FSMC -#define DMA_MAX_WORDS 0xFFFF - -#if ANY(TFT_INTERFACE_FSMC_8BIT, TFT_INTERFACE_FMC_8BIT) - #define TFT_DATASIZE DATASIZE_8BIT - typedef uint8_t tft_data_t; -#else - #define TFT_DATASIZE DATASIZE_16BIT - typedef uint16_t tft_data_t; -#endif - -typedef struct { - __IO tft_data_t REG; - __IO tft_data_t RAM; -} LCD_CONTROLLER_TypeDef; - -class TFT_FSMC { - private: - static SRAM_HandleTypeDef SRAMx; - static DMA_HandleTypeDef DMAtx; - - static LCD_CONTROLLER_TypeDef *LCD; - - static uint32_t readID(const tft_data_t reg); - static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); } - static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count); - static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count); - - public: - static void init(); - static uint32_t getID(); - static bool isBusy(); - static void abort(); +#include "../../platforms.h" - static void dataTransferBegin(uint16_t dataWidth=TFT_DATASIZE) {} - static void dataTransferEnd() {} +#ifdef HAL_STM32 - static void writeData(uint16_t data) { transmit(tft_data_t(data)); } - static void writeReg(const uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } +#include "../../../inc/MarlinConfig.h" - static void writeSequence_DMA(uint16_t *data, uint16_t count) { transmitDMA(DMA_PINC_ENABLE, data, count); } - static void writeMultiple_DMA(uint16_t color, uint16_t count) { static uint16_t data; data = color; transmitDMA(DMA_PINC_DISABLE, &data, count); } +#if HAS_FSMC_TFT - static void writeSequence(uint16_t *data, uint16_t count) { transmit(DMA_PINC_ENABLE, data, count); } - static void writeMultiple(uint16_t color, uint32_t count) { - while (count > 0) { - transmit(DMA_MINC_DISABLE, &color, count > DMA_MAX_WORDS ? DMA_MAX_WORDS : count); - count = count > DMA_MAX_WORDS ? count - DMA_MAX_WORDS : 0; - } - } -}; +#include "tft_fsmc.h" +#include "pinconfig.h" -#ifdef FMC_NORSRAM_DEVICE // Flexible Memory Controller on STM32F446 +SRAM_HandleTypeDef TFT_FSMC::SRAMx; +DMA_HandleTypeDef TFT_FSMC::DMAtx; +LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; - #ifdef STM32F4xx - #define FMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC) - #define FMC_BANK1_1 0x60000000U - #define FMC_BANK1_2 0x64000000U - #define FMC_BANK1_3 0x68000000U - #define FMC_BANK1_4 0x6C000000U +void TFT_FSMC::init() { + uint32_t controllerAddress; + #if defined(STM32F446xx) + FMC_NORSRAM_TimingTypeDef Timing, ExtTiming; #else - #error "No configuration for this MCU" + FSMC_NORSRAM_TimingTypeDef timing, extTiming; #endif - #define PINMAP_TFT_IO pinMap_FMC - #define PINMAP_TFT_CS pinMap_FMC_CS - #define PINMAP_TFT_RS pinMap_FMC_RS + uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); - const PinMap pinMap_FMC[] = { - {PD_14, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D00 - {PD_15, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D01 - {PD_0, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D02 - {PD_1, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D03 - {PE_7, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D04 - {PE_8, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D05 - {PE_9, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D06 - {PE_10, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D07 - #if DISABLED(TFT_INTERFACE_FMC_8BIT) - {PE_11, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D08 - {PE_12, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D09 - {PE_13, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D10 - {PE_14, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D11 - {PE_15, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D12 - {PD_8, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D13 - {PD_9, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D14 - {PD_10, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_D15 + // Perform the SRAM1 memory initialization sequence + #if defined(STM32F446xx) + SRAMx.Instance = FMC_NORSRAM_DEVICE; + SRAMx.Extended = FMC_NORSRAM_EXTENDED_DEVICE; + #else + SRAMx.Instance = FSMC_NORSRAM_DEVICE; + SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + #endif + // SRAMx.Init + SRAMx.Init.NSBank = nsBank; + #if defined(STM32F446xx) + SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; + SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; + SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; + SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; + #else + SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + #ifdef STM32F4xx + SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; #endif - {PD_4, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_NOE - {PD_5, FMC_NORSRAM_DEVICE, FMC_PIN_DATA}, // FMC_NWE - {NC, NP, 0} - }; + #endif + // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller + // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss + timing.AddressSetupTime = 15; + timing.AddressHoldTime = 15; + timing.DataSetupTime = 24; + timing.BusTurnAroundDuration = 0; + timing.CLKDivision = 16; + timing.DataLatency = 17; + #if defined(STM32F446xx) + Timing.AccessMode = FMC_ACCESS_MODE_A; + #else + timing.AccessMode = FSMC_ACCESS_MODE_A; + #endif + // Write Timing + // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss + extTiming.AddressSetupTime = 8; + extTiming.AddressHoldTime = 15; + extTiming.DataSetupTime = 8; + extTiming.BusTurnAroundDuration = 0; + extTiming.CLKDivision = 16; + extTiming.DataLatency = 17; + #if defined(STM32F446xx) + ExtTiming.AccessMode = FMC_ACCESS_MODE_A; + + __HAL_RCC_FMC_CLK_ENABLE(); + #else + extTiming.AccessMode = FSMC_ACCESS_MODE_A; - const PinMap pinMap_FMC_CS[] = { - {PD_7, (void *)FMC_NORSRAM_BANK1, FMC_PIN_DATA}, // FMC_NE1 - #ifdef PF0 - {PG_9, (void *)FMC_NORSRAM_BANK2, FMC_PIN_DATA}, // FMC_NE2 - {PG_10, (void *)FMC_NORSRAM_BANK3, FMC_PIN_DATA}, // FMC_NE3 - {PG_12, (void *)FMC_NORSRAM_BANK4, FMC_PIN_DATA}, // FMC_NE4 - #endif - {NC, NP, 0} - }; + __HAL_RCC_FSMC_CLK_ENABLE(); + #endif - #if ENABLED(TFT_INTERFACE_FMC_8BIT) - #define FMC_RS(A) (void *)((2 << (A - 1)) - 1) - #else - #define FMC_RS(A) (void *)((2 << A) - 2) + for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++) + pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC); + pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); + pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); + + controllerAddress = FSMC_BANK1_1; + #ifdef PF0 + switch (nsBank) { + #if defined(STM32F446xx) + case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; + case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; + case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + #else + case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; + case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; + case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + #endif + } #endif - const PinMap pinMap_FMC_RS[] = { - #ifdef PF0 - {PF_0, FMC_RS( 0), FMC_PIN_DATA}, // FMC_A0 - {PF_1, FMC_RS( 1), FMC_PIN_DATA}, // FMC_A1 - {PF_2, FMC_RS( 2), FMC_PIN_DATA}, // FMC_A2 - {PF_3, FMC_RS( 3), FMC_PIN_DATA}, // FMC_A3 - {PF_4, FMC_RS( 4), FMC_PIN_DATA}, // FMC_A4 - {PF_5, FMC_RS( 5), FMC_PIN_DATA}, // FMC_A5 - {PF_12, FMC_RS( 6), FMC_PIN_DATA}, // FMC_A6 - {PF_13, FMC_RS( 7), FMC_PIN_DATA}, // FMC_A7 - {PF_14, FMC_RS( 8), FMC_PIN_DATA}, // FMC_A8 - {PF_15, FMC_RS( 9), FMC_PIN_DATA}, // FMC_A9 - {PG_0, FMC_RS(10), FMC_PIN_DATA}, // FMC_A10 - {PG_1, FMC_RS(11), FMC_PIN_DATA}, // FMC_A11 - {PG_2, FMC_RS(12), FMC_PIN_DATA}, // FMC_A12 - {PG_3, FMC_RS(13), FMC_PIN_DATA}, // FMC_A13 - {PG_4, FMC_RS(14), FMC_PIN_DATA}, // FMC_A14 - {PG_5, FMC_RS(15), FMC_PIN_DATA}, // FMC_A15 - #endif - {PD_11, FMC_RS(16), FMC_PIN_DATA}, // FMC_A16 - {PD_12, FMC_RS(17), FMC_PIN_DATA}, // FMC_A17 - {PD_13, FMC_RS(18), FMC_PIN_DATA}, // FMC_A18 - {PE_3, FMC_RS(19), FMC_PIN_DATA}, // FMC_A19 - {PE_4, FMC_RS(20), FMC_PIN_DATA}, // FMC_A20 - {PE_5, FMC_RS(21), FMC_PIN_DATA}, // FMC_A21 - {PE_6, FMC_RS(22), FMC_PIN_DATA}, // FMC_A22 - {PE_2, FMC_RS(23), FMC_PIN_DATA}, // FMC_A23 - #ifdef PF0 - {PG_13, FMC_RS(24), FMC_PIN_DATA}, // FMC_A24 - {PG_14, FMC_RS(25), FMC_PIN_DATA}, // FMC_A25 - #endif - {NC, NP, 0} - }; + controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); -#elif defined(FSMC_NORSRAM_DEVICE) // Flexible Static Memory Controller on STM32F103 and STM32F407 + HAL_SRAM_Init(&SRAMx, &timing, &extTiming); #ifdef STM32F1xx - #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) + __HAL_RCC_DMA1_CLK_ENABLE(); + DMAtx.Instance = DMA1_Channel1; #elif defined(STM32F4xx) - #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC) - #define FSMC_BANK1_1 0x60000000U - #define FSMC_BANK1_2 0x64000000U - #define FSMC_BANK1_3 0x68000000U - #define FSMC_BANK1_4 0x6C000000U - #else - #error "No configuration for this MCU" + __HAL_RCC_DMA2_CLK_ENABLE(); + DMAtx.Instance = DMA2_Stream0; + DMAtx.Init.Channel = DMA_CHANNEL_0; + DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; + DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; #endif - - #define PINMAP_TFT_IO pinMap_FSMC - #define PINMAP_TFT_CS pinMap_FSMC_CS - #define PINMAP_TFT_RS pinMap_FSMC_RS - const PinMap pinMap_FSMC[] = { - {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 - {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 - {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 - {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 - {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 - {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 - {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 - {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 - #if DISABLED(TFT_INTERFACE_FSMC_8BIT) - {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 - {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 - {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 - {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 - {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 - {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 - {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 - {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 - #endif - {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE - {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE - {NC, NP, 0} - }; + DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; + DMAtx.Init.MemInc = DMA_MINC_DISABLE; + DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + DMAtx.Init.Mode = DMA_NORMAL; + DMAtx.Init.Priority = DMA_PRIORITY_HIGH; + + LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; +} + +uint32_t TFT_FSMC::getID() { + uint32_t id; + writeReg(0); + id = LCD->RAM; + + if (id == 0) + id = readID(LCD_READ_ID); + if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) + id = readID(LCD_READ_ID4); + return id; +} + +uint32_t TFT_FSMC::readID(const tft_data_t inReg) { + uint32_t id; + writeReg(inReg); + id = LCD->RAM; // dummy read + id = inReg << 24; + id |= (LCD->RAM & 0x00FF) << 16; + id |= (LCD->RAM & 0x00FF) << 8; + id |= LCD->RAM & 0x00FF; + return id; +} + +bool TFT_FSMC::isBusy() { + #ifdef STM32F1xx + #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CCR & DMA_CCR_EN) + #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->CPAR != 0) + #elif defined(STM32F4xx) + #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR & DMA_SxCR_EN) + #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->PAR != 0) + #endif - const PinMap pinMap_FSMC_CS[] = { - {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 - #ifdef PF0 - {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 - {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 - {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 - #endif - {NC, NP, 0} - }; + if (!__IS_DMA_CONFIGURED(&DMAtx)) return false; - #if ENABLED(TFT_INTERFACE_FSMC_8BIT) - #define FSMC_RS(A) (void *)((2 << (A-1)) - 1) - #else - #define FSMC_RS(A) (void *)((2 << A) - 2) - #endif + // Check if DMA transfer error or transfer complete flags are set + if ((__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) == 0) && (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) == 0)) return true; - const PinMap pinMap_FSMC_RS[] = { - #ifdef PF0 - {PF_0, FSMC_RS( 0), FSMC_PIN_DATA}, // FSMC_A0 - {PF_1, FSMC_RS( 1), FSMC_PIN_DATA}, // FSMC_A1 - {PF_2, FSMC_RS( 2), FSMC_PIN_DATA}, // FSMC_A2 - {PF_3, FSMC_RS( 3), FSMC_PIN_DATA}, // FSMC_A3 - {PF_4, FSMC_RS( 4), FSMC_PIN_DATA}, // FSMC_A4 - {PF_5, FSMC_RS( 5), FSMC_PIN_DATA}, // FSMC_A5 - {PF_12, FSMC_RS( 6), FSMC_PIN_DATA}, // FSMC_A6 - {PF_13, FSMC_RS( 7), FSMC_PIN_DATA}, // FSMC_A7 - {PF_14, FSMC_RS( 8), FSMC_PIN_DATA}, // FSMC_A8 - {PF_15, FSMC_RS( 9), FSMC_PIN_DATA}, // FSMC_A9 - {PG_0, FSMC_RS(10), FSMC_PIN_DATA}, // FSMC_A10 - {PG_1, FSMC_RS(11), FSMC_PIN_DATA}, // FSMC_A11 - {PG_2, FSMC_RS(12), FSMC_PIN_DATA}, // FSMC_A12 - {PG_3, FSMC_RS(13), FSMC_PIN_DATA}, // FSMC_A13 - {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14 - {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15 - #endif - {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 - {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 - {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18 - {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 - {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 - {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 - {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 - {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 - #ifdef PF0 - {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24 - {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 - #endif - {NC, NP, 0} - }; -#else - #error "Selected MCU does not support FSMC/FMC" -#endif + __DSB(); + abort(); + return false; +} + +void TFT_FSMC::abort() { + HAL_DMA_Abort(&DMAtx); // Abort DMA transfer if any + HAL_DMA_DeInit(&DMAtx); // Deconfigure DMA +} + +void TFT_FSMC::transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { + DMAtx.Init.PeriphInc = memoryIncrease; + HAL_DMA_Init(&DMAtx); + HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); + + TERN_(TFT_SHARED_IO, while (isBusy())); +} + +void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { + DMAtx.Init.PeriphInc = memoryIncrease; + HAL_DMA_Init(&DMAtx); + dataTransferBegin(); + HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); + HAL_DMA_PollForTransfer(&DMAtx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY); + abort(); +} + +#endif // HAS_FSMC_TFT +#endif // HAL_STM32 From 422a188c205c6430bdafa8c4dd32213a6f94000b Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Tue, 30 Jan 2024 12:58:35 -0600 Subject: [PATCH 07/22] Update tft_fsmc.h --- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 372 +++++++++++++--------------- 1 file changed, 178 insertions(+), 194 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index 02324c2694a0..c076fbdde58c 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -19,214 +19,198 @@ * along with this program. If not, see . * */ - -#include "../../platforms.h" - -#ifdef HAL_STM32 +#pragma once #include "../../../inc/MarlinConfig.h" -#if HAS_FSMC_TFT - -#include "tft_fsmc.h" -#include "pinconfig.h" - -SRAM_HandleTypeDef TFT_FSMC::SRAMx; -DMA_HandleTypeDef TFT_FSMC::DMAtx; -LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; - -void TFT_FSMC::init() { - uint32_t controllerAddress; - #if defined(STM32F446xx) - FMC_NORSRAM_TimingTypeDef Timing, ExtTiming; - #else - FSMC_NORSRAM_TimingTypeDef timing, extTiming; - #endif - - uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); +#ifdef STM32F1xx + #include "stm32f1xx_hal.h" +#elif defined(STM32F4xx) + #include "stm32f4xx_hal.h" +#else + #error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware." +#endif + +#ifndef HAL_SRAM_MODULE_ENABLED + #error "SRAM module disabled for the STM32 framework (HAL_SRAM_MODULE_ENABLED)! Please consult the development team." +#endif + +#ifndef LCD_READ_ID + #define LCD_READ_ID 0x04 // Read display identification information (0xD3 on ILI9341) +#endif +#ifndef LCD_READ_ID4 + #define LCD_READ_ID4 0xD3 // Read display identification information (0xD3 on ILI9341) +#endif + +#define DATASIZE_8BIT SPI_DATASIZE_8BIT +#define DATASIZE_16BIT SPI_DATASIZE_16BIT +#define TFT_IO_DRIVER TFT_FSMC +#define DMA_MAX_WORDS 0xFFFF + +#define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT) +typedef TERN(TFT_INTERFACE_FSMC_8BIT, uint8_t, uint16_t) tft_data_t; + +typedef struct { + __IO tft_data_t REG; + __IO tft_data_t RAM; +} LCD_CONTROLLER_TypeDef; + +class TFT_FSMC { + private: + static SRAM_HandleTypeDef SRAMx; + static DMA_HandleTypeDef DMAtx; + + static LCD_CONTROLLER_TypeDef *LCD; + + static uint32_t readID(const tft_data_t reg); + static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); } + static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count); + static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count); + + public: + static void init(); + static uint32_t getID(); + static bool isBusy(); + static void abort(); + + static void dataTransferBegin(uint16_t dataWidth=TFT_DATASIZE) {} + static void dataTransferEnd() {} + + static void writeData(uint16_t data) { transmit(tft_data_t(data)); } + static void writeReg(const uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } + + static void writeSequence_DMA(uint16_t *data, uint16_t count) { transmitDMA(DMA_PINC_ENABLE, data, count); } + static void writeMultiple_DMA(uint16_t color, uint16_t count) { static uint16_t data; data = color; transmitDMA(DMA_PINC_DISABLE, &data, count); } + + static void writeSequence(uint16_t *data, uint16_t count) { transmit(DMA_PINC_ENABLE, data, count); } + static void writeMultiple(uint16_t color, uint32_t count) { + while (count > 0) { + transmit(DMA_MINC_DISABLE, &color, count > DMA_MAX_WORDS ? DMA_MAX_WORDS : count); + count = count > DMA_MAX_WORDS ? count - DMA_MAX_WORDS : 0; + } + } +}; - // Perform the SRAM1 memory initialization sequence +#ifdef STM32F1xx + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) +#elif defined(STM32F4xx) #if defined(STM32F446xx) - SRAMx.Instance = FMC_NORSRAM_DEVICE; - SRAMx.Extended = FMC_NORSRAM_EXTENDED_DEVICE; + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC) #else - SRAMx.Instance = FSMC_NORSRAM_DEVICE; - SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC) #endif - // SRAMx.Init - SRAMx.Init.NSBank = nsBank; - #if defined(STM32F446xx) - SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; - SRAMx.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; - SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; - #else - SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; - SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; - #ifdef STM32F4xx - SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; + #define FSMC_BANK1_1 0x60000000U + #define FSMC_BANK1_2 0x64000000U + #define FSMC_BANK1_3 0x68000000U + #define FSMC_BANK1_4 0x6C000000U +#else + #error No configuration for this MCU +#endif + +const PinMap pinMap_FSMC[] = { + #if defined(STM32F446xx) // + {PD_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 + {PD_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 + {PD_0, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 + {PD_1, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 + {PE_7, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 + {PE_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 + {PE_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 + {PE_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 + #if DISABLED(TFT_INTERFACE_FSMC_8BIT) + {PE_11, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 + {PE_12, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 + {PE_13, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 + {PE_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 + {PE_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 + {PD_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 + {PD_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 + {PD_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 #endif - #endif - // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller - // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss - timing.AddressSetupTime = 15; - timing.AddressHoldTime = 15; - timing.DataSetupTime = 24; - timing.BusTurnAroundDuration = 0; - timing.CLKDivision = 16; - timing.DataLatency = 17; - #if defined(STM32F446xx) - Timing.AccessMode = FMC_ACCESS_MODE_A; + {PD_4, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE + {PD_5, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE + {NC, NP, 0} #else - timing.AccessMode = FSMC_ACCESS_MODE_A; + {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 + {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 + {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 + {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 + {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 + {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 + {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 + {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 + #if DISABLED(TFT_INTERFACE_FSMC_8BIT) + {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 + {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 + {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 + {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 + {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 + {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 + {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 + {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 + #endif + {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE + {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE + {NC, NP, 0} #endif - // Write Timing - // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss - extTiming.AddressSetupTime = 8; - extTiming.AddressHoldTime = 15; - extTiming.DataSetupTime = 8; - extTiming.BusTurnAroundDuration = 0; - extTiming.CLKDivision = 16; - extTiming.DataLatency = 17; - #if defined(STM32F446xx) - ExtTiming.AccessMode = FMC_ACCESS_MODE_A; - - __HAL_RCC_FMC_CLK_ENABLE(); +}; + +const PinMap pinMap_FSMC_CS[] = { + #if defined(STM32F446xx) // + {PD_7, (void *)FMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 + #ifdef PF0 + {PG_9, (void *)FMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 + {PG_10, (void *)FMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 + {PG_12, (void *)FMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 + #endif + {NC, NP, 0} #else - extTiming.AccessMode = FSMC_ACCESS_MODE_A; - - __HAL_RCC_FSMC_CLK_ENABLE(); + {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 + #ifdef PF0 + {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 + {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 + {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 + #endif + {NC, NP, 0} #endif +}; - for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++) - pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC); - pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); - pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); +#if ENABLED(TFT_INTERFACE_FSMC_8BIT) + #define FSMC_RS(A) (void *)((2 << (A-1)) - 1) +#else + #define FSMC_RS(A) (void *)((2 << A) - 2) +#endif - controllerAddress = FSMC_BANK1_1; +const PinMap pinMap_FSMC_RS[] = { #ifdef PF0 - switch (nsBank) { - #if defined(STM32F446xx) - case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; - case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; - case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; - #else - case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; - case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; - case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; - #endif - } + {PF_0, FSMC_RS( 0), FSMC_PIN_DATA}, // FSMC_A0 + {PF_1, FSMC_RS( 1), FSMC_PIN_DATA}, // FSMC_A1 + {PF_2, FSMC_RS( 2), FSMC_PIN_DATA}, // FSMC_A2 + {PF_3, FSMC_RS( 3), FSMC_PIN_DATA}, // FSMC_A3 + {PF_4, FSMC_RS( 4), FSMC_PIN_DATA}, // FSMC_A4 + {PF_5, FSMC_RS( 5), FSMC_PIN_DATA}, // FSMC_A5 + {PF_12, FSMC_RS( 6), FSMC_PIN_DATA}, // FSMC_A6 + {PF_13, FSMC_RS( 7), FSMC_PIN_DATA}, // FSMC_A7 + {PF_14, FSMC_RS( 8), FSMC_PIN_DATA}, // FSMC_A8 + {PF_15, FSMC_RS( 9), FSMC_PIN_DATA}, // FSMC_A9 + {PG_0, FSMC_RS(10), FSMC_PIN_DATA}, // FSMC_A10 + {PG_1, FSMC_RS(11), FSMC_PIN_DATA}, // FSMC_A11 + {PG_2, FSMC_RS(12), FSMC_PIN_DATA}, // FSMC_A12 + {PG_3, FSMC_RS(13), FSMC_PIN_DATA}, // FSMC_A13 + {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14 + {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15 #endif - - controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); - - HAL_SRAM_Init(&SRAMx, &timing, &extTiming); - - #ifdef STM32F1xx - __HAL_RCC_DMA1_CLK_ENABLE(); - DMAtx.Instance = DMA1_Channel1; - #elif defined(STM32F4xx) - __HAL_RCC_DMA2_CLK_ENABLE(); - DMAtx.Instance = DMA2_Stream0; - DMAtx.Init.Channel = DMA_CHANNEL_0; - DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; - DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; - #endif - - DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; - DMAtx.Init.MemInc = DMA_MINC_DISABLE; - DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - DMAtx.Init.Mode = DMA_NORMAL; - DMAtx.Init.Priority = DMA_PRIORITY_HIGH; - - LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; -} - -uint32_t TFT_FSMC::getID() { - uint32_t id; - writeReg(0); - id = LCD->RAM; - - if (id == 0) - id = readID(LCD_READ_ID); - if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) - id = readID(LCD_READ_ID4); - return id; -} - -uint32_t TFT_FSMC::readID(const tft_data_t inReg) { - uint32_t id; - writeReg(inReg); - id = LCD->RAM; // dummy read - id = inReg << 24; - id |= (LCD->RAM & 0x00FF) << 16; - id |= (LCD->RAM & 0x00FF) << 8; - id |= LCD->RAM & 0x00FF; - return id; -} - -bool TFT_FSMC::isBusy() { - #ifdef STM32F1xx - #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CCR & DMA_CCR_EN) - #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->CPAR != 0) - #elif defined(STM32F4xx) - #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR & DMA_SxCR_EN) - #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->PAR != 0) + {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 + {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 + {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18 + {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 + {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 + {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 + {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 + {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 + #ifdef PF0 + {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24 + {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 #endif - - if (!__IS_DMA_CONFIGURED(&DMAtx)) return false; - - // Check if DMA transfer error or transfer complete flags are set - if ((__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) == 0) && (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) == 0)) return true; - - __DSB(); - abort(); - return false; -} - -void TFT_FSMC::abort() { - HAL_DMA_Abort(&DMAtx); // Abort DMA transfer if any - HAL_DMA_DeInit(&DMAtx); // Deconfigure DMA -} - -void TFT_FSMC::transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { - DMAtx.Init.PeriphInc = memoryIncrease; - HAL_DMA_Init(&DMAtx); - HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); - - TERN_(TFT_SHARED_IO, while (isBusy())); -} - -void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { - DMAtx.Init.PeriphInc = memoryIncrease; - HAL_DMA_Init(&DMAtx); - dataTransferBegin(); - HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); - HAL_DMA_PollForTransfer(&DMAtx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY); - abort(); -} - -#endif // HAS_FSMC_TFT -#endif // HAL_STM32 + {NC, NP, 0} +}; From ec7b9d1ea77c538eca60aee236dc6ef997a1e0e0 Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Tue, 30 Jan 2024 12:59:23 -0600 Subject: [PATCH 08/22] Update tft_fsmc.h Rework code to fix broken build on Lerdge boards. --- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 368 +++++++++++++++------------- 1 file changed, 192 insertions(+), 176 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index c076fbdde58c..e3d932cb9c10 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -19,198 +19,214 @@ * along with this program. If not, see . * */ -#pragma once + +#include "../../platforms.h" + +#ifdef HAL_STM32 #include "../../../inc/MarlinConfig.h" -#ifdef STM32F1xx - #include "stm32f1xx_hal.h" -#elif defined(STM32F4xx) - #include "stm32f4xx_hal.h" -#else - #error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware." -#endif - -#ifndef HAL_SRAM_MODULE_ENABLED - #error "SRAM module disabled for the STM32 framework (HAL_SRAM_MODULE_ENABLED)! Please consult the development team." -#endif - -#ifndef LCD_READ_ID - #define LCD_READ_ID 0x04 // Read display identification information (0xD3 on ILI9341) -#endif -#ifndef LCD_READ_ID4 - #define LCD_READ_ID4 0xD3 // Read display identification information (0xD3 on ILI9341) -#endif - -#define DATASIZE_8BIT SPI_DATASIZE_8BIT -#define DATASIZE_16BIT SPI_DATASIZE_16BIT -#define TFT_IO_DRIVER TFT_FSMC -#define DMA_MAX_WORDS 0xFFFF - -#define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT) -typedef TERN(TFT_INTERFACE_FSMC_8BIT, uint8_t, uint16_t) tft_data_t; - -typedef struct { - __IO tft_data_t REG; - __IO tft_data_t RAM; -} LCD_CONTROLLER_TypeDef; - -class TFT_FSMC { - private: - static SRAM_HandleTypeDef SRAMx; - static DMA_HandleTypeDef DMAtx; - - static LCD_CONTROLLER_TypeDef *LCD; - - static uint32_t readID(const tft_data_t reg); - static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); } - static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count); - static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count); - - public: - static void init(); - static uint32_t getID(); - static bool isBusy(); - static void abort(); - - static void dataTransferBegin(uint16_t dataWidth=TFT_DATASIZE) {} - static void dataTransferEnd() {} - - static void writeData(uint16_t data) { transmit(tft_data_t(data)); } - static void writeReg(const uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } - - static void writeSequence_DMA(uint16_t *data, uint16_t count) { transmitDMA(DMA_PINC_ENABLE, data, count); } - static void writeMultiple_DMA(uint16_t color, uint16_t count) { static uint16_t data; data = color; transmitDMA(DMA_PINC_DISABLE, &data, count); } - - static void writeSequence(uint16_t *data, uint16_t count) { transmit(DMA_PINC_ENABLE, data, count); } - static void writeMultiple(uint16_t color, uint32_t count) { - while (count > 0) { - transmit(DMA_MINC_DISABLE, &color, count > DMA_MAX_WORDS ? DMA_MAX_WORDS : count); - count = count > DMA_MAX_WORDS ? count - DMA_MAX_WORDS : 0; - } - } -}; +#if HAS_FSMC_TFT + +#include "tft_fsmc.h" +#include "pinconfig.h" + +SRAM_HandleTypeDef TFT_FSMC::SRAMx; +DMA_HandleTypeDef TFT_FSMC::DMAtx; +LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; + +void TFT_FSMC::init() { + uint32_t controllerAddress; + #if defined(STM32F446xx) + FMC_NORSRAM_TimingTypeDef Timing, ExtTiming; + #else + FSMC_NORSRAM_TimingTypeDef timing, extTiming; + #endif + + uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); -#ifdef STM32F1xx - #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) -#elif defined(STM32F4xx) + // Perform the SRAM1 memory initialization sequence #if defined(STM32F446xx) - #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC) + SRAMx.Instance = FMC_NORSRAM_DEVICE; + SRAMx.Extended = FMC_NORSRAM_EXTENDED_DEVICE; #else - #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC) + SRAMx.Instance = FSMC_NORSRAM_DEVICE; + SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; #endif - #define FSMC_BANK1_1 0x60000000U - #define FSMC_BANK1_2 0x64000000U - #define FSMC_BANK1_3 0x68000000U - #define FSMC_BANK1_4 0x6C000000U -#else - #error No configuration for this MCU -#endif - -const PinMap pinMap_FSMC[] = { + // SRAMx.Init + SRAMx.Init.NSBank = nsBank; #if defined(STM32F446xx) // - {PD_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 - {PD_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 - {PD_0, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 - {PD_1, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 - {PE_7, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 - {PE_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 - {PE_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 - {PE_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 - #if DISABLED(TFT_INTERFACE_FSMC_8BIT) - {PE_11, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 - {PE_12, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 - {PE_13, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 - {PE_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 - {PE_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 - {PD_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 - {PD_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 - {PD_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 - #endif - {PD_4, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE - {PD_5, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE - {NC, NP, 0} + SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; + SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; + SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; + SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; #else - {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 - {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 - {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 - {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 - {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 - {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 - {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 - {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 - #if DISABLED(TFT_INTERFACE_FSMC_8BIT) - {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 - {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 - {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 - {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 - {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 - {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 - {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 - {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 + SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + #ifdef STM32F4xx + SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; #endif - {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE - {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE - {NC, NP, 0} #endif -}; - -const PinMap pinMap_FSMC_CS[] = { + // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller + // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss + timing.AddressSetupTime = 15; + timing.AddressHoldTime = 15; + timing.DataSetupTime = 24; + timing.BusTurnAroundDuration = 0; + timing.CLKDivision = 16; + timing.DataLatency = 17; #if defined(STM32F446xx) // - {PD_7, (void *)FMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 - #ifdef PF0 - {PG_9, (void *)FMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 - {PG_10, (void *)FMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 - {PG_12, (void *)FMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 - #endif - {NC, NP, 0} + Timing.AccessMode = FMC_ACCESS_MODE_A; #else - {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 - #ifdef PF0 - {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 - {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 - {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 - #endif - {NC, NP, 0} + timing.AccessMode = FSMC_ACCESS_MODE_A; + #endif + // Write Timing + // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss + extTiming.AddressSetupTime = 8; + extTiming.AddressHoldTime = 15; + extTiming.DataSetupTime = 8; + extTiming.BusTurnAroundDuration = 0; + extTiming.CLKDivision = 16; + extTiming.DataLatency = 17; + #if defined(STM32F446xx) // + ExtTiming.AccessMode = FMC_ACCESS_MODE_A; + + __HAL_RCC_FMC_CLK_ENABLE(); + #else + extTiming.AccessMode = FSMC_ACCESS_MODE_A; + + __HAL_RCC_FSMC_CLK_ENABLE(); #endif -}; -#if ENABLED(TFT_INTERFACE_FSMC_8BIT) - #define FSMC_RS(A) (void *)((2 << (A-1)) - 1) -#else - #define FSMC_RS(A) (void *)((2 << A) - 2) -#endif + for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++) + pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC); + pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); + pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); -const PinMap pinMap_FSMC_RS[] = { + controllerAddress = FSMC_BANK1_1; #ifdef PF0 - {PF_0, FSMC_RS( 0), FSMC_PIN_DATA}, // FSMC_A0 - {PF_1, FSMC_RS( 1), FSMC_PIN_DATA}, // FSMC_A1 - {PF_2, FSMC_RS( 2), FSMC_PIN_DATA}, // FSMC_A2 - {PF_3, FSMC_RS( 3), FSMC_PIN_DATA}, // FSMC_A3 - {PF_4, FSMC_RS( 4), FSMC_PIN_DATA}, // FSMC_A4 - {PF_5, FSMC_RS( 5), FSMC_PIN_DATA}, // FSMC_A5 - {PF_12, FSMC_RS( 6), FSMC_PIN_DATA}, // FSMC_A6 - {PF_13, FSMC_RS( 7), FSMC_PIN_DATA}, // FSMC_A7 - {PF_14, FSMC_RS( 8), FSMC_PIN_DATA}, // FSMC_A8 - {PF_15, FSMC_RS( 9), FSMC_PIN_DATA}, // FSMC_A9 - {PG_0, FSMC_RS(10), FSMC_PIN_DATA}, // FSMC_A10 - {PG_1, FSMC_RS(11), FSMC_PIN_DATA}, // FSMC_A11 - {PG_2, FSMC_RS(12), FSMC_PIN_DATA}, // FSMC_A12 - {PG_3, FSMC_RS(13), FSMC_PIN_DATA}, // FSMC_A13 - {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14 - {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15 + switch (nsBank) { + #if defined(STM32F446xx) // + case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; + case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; + case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + #else + case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; + case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; + case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + #endif + } #endif - {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 - {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 - {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18 - {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 - {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 - {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 - {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 - {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 - #ifdef PF0 - {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24 - {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 + + controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); + + HAL_SRAM_Init(&SRAMx, &timing, &extTiming); + + #ifdef STM32F1xx + __HAL_RCC_DMA1_CLK_ENABLE(); + DMAtx.Instance = DMA1_Channel1; + #elif defined(STM32F4xx) + __HAL_RCC_DMA2_CLK_ENABLE(); + DMAtx.Instance = DMA2_Stream0; + DMAtx.Init.Channel = DMA_CHANNEL_0; + DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; + DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; + #endif + + DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; + DMAtx.Init.MemInc = DMA_MINC_DISABLE; + DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + DMAtx.Init.Mode = DMA_NORMAL; + DMAtx.Init.Priority = DMA_PRIORITY_HIGH; + + LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; +} + +uint32_t TFT_FSMC::getID() { + uint32_t id; + writeReg(0); + id = LCD->RAM; + + if (id == 0) + id = readID(LCD_READ_ID); + if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) + id = readID(LCD_READ_ID4); + return id; +} + +uint32_t TFT_FSMC::readID(const tft_data_t inReg) { + uint32_t id; + writeReg(inReg); + id = LCD->RAM; // dummy read + id = inReg << 24; + id |= (LCD->RAM & 0x00FF) << 16; + id |= (LCD->RAM & 0x00FF) << 8; + id |= LCD->RAM & 0x00FF; + return id; +} + +bool TFT_FSMC::isBusy() { + #ifdef STM32F1xx + #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CCR & DMA_CCR_EN) + #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->CPAR != 0) + #elif defined(STM32F4xx) + #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR & DMA_SxCR_EN) + #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->PAR != 0) #endif - {NC, NP, 0} -}; + + if (!__IS_DMA_CONFIGURED(&DMAtx)) return false; + + // Check if DMA transfer error or transfer complete flags are set + if ((__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) == 0) && (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) == 0)) return true; + + __DSB(); + abort(); + return false; +} + +void TFT_FSMC::abort() { + HAL_DMA_Abort(&DMAtx); // Abort DMA transfer if any + HAL_DMA_DeInit(&DMAtx); // Deconfigure DMA +} + +void TFT_FSMC::transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { + DMAtx.Init.PeriphInc = memoryIncrease; + HAL_DMA_Init(&DMAtx); + HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); + + TERN_(TFT_SHARED_IO, while (isBusy())); +} + +void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { + DMAtx.Init.PeriphInc = memoryIncrease; + HAL_DMA_Init(&DMAtx); + dataTransferBegin(); + HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); + HAL_DMA_PollForTransfer(&DMAtx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY); + abort(); +} + +#endif // HAS_FSMC_TFT +#endif // HAL_STM32 From a3f5f5c180fd70489056584c14774b638a9417c5 Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Tue, 30 Jan 2024 13:01:31 -0600 Subject: [PATCH 09/22] Update tft_fsmc.h --- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 368 +++++++++++++--------------- 1 file changed, 176 insertions(+), 192 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index e3d932cb9c10..c076fbdde58c 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -19,214 +19,198 @@ * along with this program. If not, see . * */ - -#include "../../platforms.h" - -#ifdef HAL_STM32 +#pragma once #include "../../../inc/MarlinConfig.h" -#if HAS_FSMC_TFT - -#include "tft_fsmc.h" -#include "pinconfig.h" - -SRAM_HandleTypeDef TFT_FSMC::SRAMx; -DMA_HandleTypeDef TFT_FSMC::DMAtx; -LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; - -void TFT_FSMC::init() { - uint32_t controllerAddress; - #if defined(STM32F446xx) - FMC_NORSRAM_TimingTypeDef Timing, ExtTiming; - #else - FSMC_NORSRAM_TimingTypeDef timing, extTiming; - #endif - - uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); +#ifdef STM32F1xx + #include "stm32f1xx_hal.h" +#elif defined(STM32F4xx) + #include "stm32f4xx_hal.h" +#else + #error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware." +#endif + +#ifndef HAL_SRAM_MODULE_ENABLED + #error "SRAM module disabled for the STM32 framework (HAL_SRAM_MODULE_ENABLED)! Please consult the development team." +#endif + +#ifndef LCD_READ_ID + #define LCD_READ_ID 0x04 // Read display identification information (0xD3 on ILI9341) +#endif +#ifndef LCD_READ_ID4 + #define LCD_READ_ID4 0xD3 // Read display identification information (0xD3 on ILI9341) +#endif + +#define DATASIZE_8BIT SPI_DATASIZE_8BIT +#define DATASIZE_16BIT SPI_DATASIZE_16BIT +#define TFT_IO_DRIVER TFT_FSMC +#define DMA_MAX_WORDS 0xFFFF + +#define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT) +typedef TERN(TFT_INTERFACE_FSMC_8BIT, uint8_t, uint16_t) tft_data_t; + +typedef struct { + __IO tft_data_t REG; + __IO tft_data_t RAM; +} LCD_CONTROLLER_TypeDef; + +class TFT_FSMC { + private: + static SRAM_HandleTypeDef SRAMx; + static DMA_HandleTypeDef DMAtx; + + static LCD_CONTROLLER_TypeDef *LCD; + + static uint32_t readID(const tft_data_t reg); + static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); } + static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count); + static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count); + + public: + static void init(); + static uint32_t getID(); + static bool isBusy(); + static void abort(); + + static void dataTransferBegin(uint16_t dataWidth=TFT_DATASIZE) {} + static void dataTransferEnd() {} + + static void writeData(uint16_t data) { transmit(tft_data_t(data)); } + static void writeReg(const uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } + + static void writeSequence_DMA(uint16_t *data, uint16_t count) { transmitDMA(DMA_PINC_ENABLE, data, count); } + static void writeMultiple_DMA(uint16_t color, uint16_t count) { static uint16_t data; data = color; transmitDMA(DMA_PINC_DISABLE, &data, count); } + + static void writeSequence(uint16_t *data, uint16_t count) { transmit(DMA_PINC_ENABLE, data, count); } + static void writeMultiple(uint16_t color, uint32_t count) { + while (count > 0) { + transmit(DMA_MINC_DISABLE, &color, count > DMA_MAX_WORDS ? DMA_MAX_WORDS : count); + count = count > DMA_MAX_WORDS ? count - DMA_MAX_WORDS : 0; + } + } +}; - // Perform the SRAM1 memory initialization sequence +#ifdef STM32F1xx + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) +#elif defined(STM32F4xx) #if defined(STM32F446xx) - SRAMx.Instance = FMC_NORSRAM_DEVICE; - SRAMx.Extended = FMC_NORSRAM_EXTENDED_DEVICE; + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC) #else - SRAMx.Instance = FSMC_NORSRAM_DEVICE; - SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC) #endif - // SRAMx.Init - SRAMx.Init.NSBank = nsBank; + #define FSMC_BANK1_1 0x60000000U + #define FSMC_BANK1_2 0x64000000U + #define FSMC_BANK1_3 0x68000000U + #define FSMC_BANK1_4 0x6C000000U +#else + #error No configuration for this MCU +#endif + +const PinMap pinMap_FSMC[] = { #if defined(STM32F446xx) // - SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; - SRAMx.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; - SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; - #else - SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; - SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; - #ifdef STM32F4xx - SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; + {PD_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 + {PD_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 + {PD_0, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 + {PD_1, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 + {PE_7, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 + {PE_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 + {PE_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 + {PE_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 + #if DISABLED(TFT_INTERFACE_FSMC_8BIT) + {PE_11, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 + {PE_12, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 + {PE_13, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 + {PE_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 + {PE_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 + {PD_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 + {PD_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 + {PD_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 #endif - #endif - // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller - // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss - timing.AddressSetupTime = 15; - timing.AddressHoldTime = 15; - timing.DataSetupTime = 24; - timing.BusTurnAroundDuration = 0; - timing.CLKDivision = 16; - timing.DataLatency = 17; - #if defined(STM32F446xx) // - Timing.AccessMode = FMC_ACCESS_MODE_A; + {PD_4, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE + {PD_5, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE + {NC, NP, 0} #else - timing.AccessMode = FSMC_ACCESS_MODE_A; + {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 + {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 + {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 + {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 + {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 + {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 + {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 + {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 + #if DISABLED(TFT_INTERFACE_FSMC_8BIT) + {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 + {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 + {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 + {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 + {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 + {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 + {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 + {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 + #endif + {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE + {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE + {NC, NP, 0} #endif - // Write Timing - // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss - extTiming.AddressSetupTime = 8; - extTiming.AddressHoldTime = 15; - extTiming.DataSetupTime = 8; - extTiming.BusTurnAroundDuration = 0; - extTiming.CLKDivision = 16; - extTiming.DataLatency = 17; - #if defined(STM32F446xx) // - ExtTiming.AccessMode = FMC_ACCESS_MODE_A; +}; - __HAL_RCC_FMC_CLK_ENABLE(); +const PinMap pinMap_FSMC_CS[] = { + #if defined(STM32F446xx) // + {PD_7, (void *)FMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 + #ifdef PF0 + {PG_9, (void *)FMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 + {PG_10, (void *)FMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 + {PG_12, (void *)FMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 + #endif + {NC, NP, 0} #else - extTiming.AccessMode = FSMC_ACCESS_MODE_A; - - __HAL_RCC_FSMC_CLK_ENABLE(); + {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 + #ifdef PF0 + {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 + {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 + {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 + #endif + {NC, NP, 0} #endif +}; - for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++) - pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC); - pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); - pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); +#if ENABLED(TFT_INTERFACE_FSMC_8BIT) + #define FSMC_RS(A) (void *)((2 << (A-1)) - 1) +#else + #define FSMC_RS(A) (void *)((2 << A) - 2) +#endif - controllerAddress = FSMC_BANK1_1; +const PinMap pinMap_FSMC_RS[] = { #ifdef PF0 - switch (nsBank) { - #if defined(STM32F446xx) // - case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; - case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; - case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; - #else - case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; - case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; - case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; - #endif - } + {PF_0, FSMC_RS( 0), FSMC_PIN_DATA}, // FSMC_A0 + {PF_1, FSMC_RS( 1), FSMC_PIN_DATA}, // FSMC_A1 + {PF_2, FSMC_RS( 2), FSMC_PIN_DATA}, // FSMC_A2 + {PF_3, FSMC_RS( 3), FSMC_PIN_DATA}, // FSMC_A3 + {PF_4, FSMC_RS( 4), FSMC_PIN_DATA}, // FSMC_A4 + {PF_5, FSMC_RS( 5), FSMC_PIN_DATA}, // FSMC_A5 + {PF_12, FSMC_RS( 6), FSMC_PIN_DATA}, // FSMC_A6 + {PF_13, FSMC_RS( 7), FSMC_PIN_DATA}, // FSMC_A7 + {PF_14, FSMC_RS( 8), FSMC_PIN_DATA}, // FSMC_A8 + {PF_15, FSMC_RS( 9), FSMC_PIN_DATA}, // FSMC_A9 + {PG_0, FSMC_RS(10), FSMC_PIN_DATA}, // FSMC_A10 + {PG_1, FSMC_RS(11), FSMC_PIN_DATA}, // FSMC_A11 + {PG_2, FSMC_RS(12), FSMC_PIN_DATA}, // FSMC_A12 + {PG_3, FSMC_RS(13), FSMC_PIN_DATA}, // FSMC_A13 + {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14 + {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15 #endif - - controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); - - HAL_SRAM_Init(&SRAMx, &timing, &extTiming); - - #ifdef STM32F1xx - __HAL_RCC_DMA1_CLK_ENABLE(); - DMAtx.Instance = DMA1_Channel1; - #elif defined(STM32F4xx) - __HAL_RCC_DMA2_CLK_ENABLE(); - DMAtx.Instance = DMA2_Stream0; - DMAtx.Init.Channel = DMA_CHANNEL_0; - DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; - DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; - #endif - - DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; - DMAtx.Init.MemInc = DMA_MINC_DISABLE; - DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - DMAtx.Init.Mode = DMA_NORMAL; - DMAtx.Init.Priority = DMA_PRIORITY_HIGH; - - LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; -} - -uint32_t TFT_FSMC::getID() { - uint32_t id; - writeReg(0); - id = LCD->RAM; - - if (id == 0) - id = readID(LCD_READ_ID); - if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) - id = readID(LCD_READ_ID4); - return id; -} - -uint32_t TFT_FSMC::readID(const tft_data_t inReg) { - uint32_t id; - writeReg(inReg); - id = LCD->RAM; // dummy read - id = inReg << 24; - id |= (LCD->RAM & 0x00FF) << 16; - id |= (LCD->RAM & 0x00FF) << 8; - id |= LCD->RAM & 0x00FF; - return id; -} - -bool TFT_FSMC::isBusy() { - #ifdef STM32F1xx - #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CCR & DMA_CCR_EN) - #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->CPAR != 0) - #elif defined(STM32F4xx) - #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR & DMA_SxCR_EN) - #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->PAR != 0) + {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 + {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 + {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18 + {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 + {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 + {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 + {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 + {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 + #ifdef PF0 + {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24 + {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 #endif - - if (!__IS_DMA_CONFIGURED(&DMAtx)) return false; - - // Check if DMA transfer error or transfer complete flags are set - if ((__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) == 0) && (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) == 0)) return true; - - __DSB(); - abort(); - return false; -} - -void TFT_FSMC::abort() { - HAL_DMA_Abort(&DMAtx); // Abort DMA transfer if any - HAL_DMA_DeInit(&DMAtx); // Deconfigure DMA -} - -void TFT_FSMC::transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { - DMAtx.Init.PeriphInc = memoryIncrease; - HAL_DMA_Init(&DMAtx); - HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); - - TERN_(TFT_SHARED_IO, while (isBusy())); -} - -void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { - DMAtx.Init.PeriphInc = memoryIncrease; - HAL_DMA_Init(&DMAtx); - dataTransferBegin(); - HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); - HAL_DMA_PollForTransfer(&DMAtx, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY); - abort(); -} - -#endif // HAS_FSMC_TFT -#endif // HAL_STM32 + {NC, NP, 0} +}; From b5730551e00c3783b4e39fcb6e3c052024ac9f98 Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Tue, 30 Jan 2024 13:27:08 -0600 Subject: [PATCH 10/22] Update tft_fsmc.h Cleanup --- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index c076fbdde58c..1b3e761fbec4 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -94,7 +94,7 @@ class TFT_FSMC { #ifdef STM32F1xx #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE) #elif defined(STM32F4xx) - #if defined(STM32F446xx) + #ifdef STM32F446xx #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC) #else #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC) @@ -108,7 +108,7 @@ class TFT_FSMC { #endif const PinMap pinMap_FSMC[] = { - #if defined(STM32F446xx) // + #ifdef STM32F446xx {PD_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 {PD_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 {PD_0, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 @@ -156,7 +156,7 @@ const PinMap pinMap_FSMC[] = { }; const PinMap pinMap_FSMC_CS[] = { - #if defined(STM32F446xx) // + #ifdef STM32F446xx {PD_7, (void *)FMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 #ifdef PF0 {PG_9, (void *)FMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 From 34cf78aef3a92a6469440b57a76e36f978b06eab Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Tue, 30 Jan 2024 21:12:24 -0600 Subject: [PATCH 11/22] Update tft_fsmc.h and tft_fsmc.cpp --- Marlin/src/HAL/STM32/tft/tft_fsmc.cpp | 86 +++++++++++++-------------- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 16 ++--- 2 files changed, 46 insertions(+), 56 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp index 036840919e7d..242085ee59bb 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp @@ -37,16 +37,25 @@ LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; void TFT_FSMC::init() { uint32_t controllerAddress; - uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), PINMAP_TFT_CS); - - #ifdef FMC_NORSRAM_DEVICE + #ifdef STM32F446xx FMC_NORSRAM_TimingTypeDef timing, extTiming; + #else + FSMC_NORSRAM_TimingTypeDef timing, extTiming; + #endif - // Perform the SRAM1 memory initialization sequence + uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); + + // Perform the SRAM1 memory initialization sequence + #ifdef STM32F446xx SRAMx.Instance = FMC_NORSRAM_DEVICE; SRAMx.Extended = FMC_NORSRAM_EXTENDED_DEVICE; - // SRAMx.Init - SRAMx.Init.NSBank = nsBank; + #else + SRAMx.Instance = FSMC_NORSRAM_DEVICE; + SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + #endif + // SRAMx.Init + SRAMx.Init.NSBank = nsBank; + #ifdef STM32F446xx SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); @@ -58,20 +67,9 @@ void TFT_FSMC::init() { SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; - - SRAMx.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; - SRAMx.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE; - SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; - #elif defined(FSMC_NORSRAM_DEVICE) - FSMC_NORSRAM_TimingTypeDef timing, extTiming; - - // Perform the SRAM1 memory initialization sequence - SRAMx.Instance = FSMC_NORSRAM_DEVICE; - SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; - // SRAMx.Init - SRAMx.Init.NSBank = nsBank; + #else SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); @@ -87,10 +85,7 @@ void TFT_FSMC::init() { #ifdef STM32F4xx SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; #endif - #else - #error "Selected MCU does not support FSMC/FMC" #endif - // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss timing.AddressSetupTime = 15; @@ -99,40 +94,41 @@ void TFT_FSMC::init() { timing.BusTurnAroundDuration = 0; timing.CLKDivision = 16; timing.DataLatency = 17; - + #ifdef STM32F446xx + timing.AccessMode = FMC_ACCESS_MODE_A; + #else + timing.AccessMode = FSMC_ACCESS_MODE_A; + #endif // Write Timing - // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss + // Can be decreases from 8-15-8 to 0-0-1 with risk of stability loss extTiming.AddressSetupTime = 8; extTiming.AddressHoldTime = 15; extTiming.DataSetupTime = 8; extTiming.BusTurnAroundDuration = 0; extTiming.CLKDivision = 16; extTiming.DataLatency = 17; - - #ifdef FMC_NORSRAM_DEVICE - timing.AccessMode = FMC_ACCESS_MODE_A; + #ifdef STM32F446xx extTiming.AccessMode = FMC_ACCESS_MODE_A; + __HAL_RCC_FMC_CLK_ENABLE(); - controllerAddress = FMC_BANK1_1; #else - timing.AccessMode = FSMC_ACCESS_MODE_A; extTiming.AccessMode = FSMC_ACCESS_MODE_A; + __HAL_RCC_FSMC_CLK_ENABLE(); - controllerAddress = FSMC_BANK1_1; #endif - for (uint16_t i = 0; PINMAP_TFT_IO[i].pin != NC; i++) - pinmap_pinout(PINMAP_TFT_IO[i].pin, PINMAP_TFT_IO); - pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), PINMAP_TFT_CS); - pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), PINMAP_TFT_RS); + for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++) + pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC); + pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); + pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); - // Note: Code below assume that MCU in LQFP-100 package has only one NE pin. STM32H743 has two - NE1 and NE2. + controllerAddress = FSMC_BANK1_1; #ifdef PF0 switch (nsBank) { - #ifdef FMC_NORSRAM_DEVICE - case FMC_NORSRAM_BANK2: controllerAddress = FMC_BANK1_2 ; break; - case FMC_NORSRAM_BANK3: controllerAddress = FMC_BANK1_3 ; break; - case FMC_NORSRAM_BANK4: controllerAddress = FMC_BANK1_4 ; break; + #ifdef STM32F446xx + case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; + case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; + case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; #else case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; @@ -141,15 +137,15 @@ void TFT_FSMC::init() { } #endif - controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), PINMAP_TFT_RS); + controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS); HAL_SRAM_Init(&SRAMx, &timing, &extTiming); + __HAL_RCC_DMA2_CLK_ENABLE(); + #ifdef STM32F1xx - __HAL_RCC_DMA1_CLK_ENABLE(); - DMAtx.Instance = DMA1_Channel1; + DMAtx.Instance = DMA2_Channel1; #elif defined(STM32F4xx) - __HAL_RCC_DMA2_CLK_ENABLE(); DMAtx.Instance = DMA2_Stream0; DMAtx.Init.Channel = DMA_CHANNEL_0; DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; @@ -180,7 +176,7 @@ uint32_t TFT_FSMC::getID() { return id; } -uint32_t TFT_FSMC::readID(const tft_data_t inReg) { +uint32_t TFT_FSMC::readID(tft_data_t inReg) { uint32_t id; writeReg(inReg); id = LCD->RAM; // dummy read @@ -219,8 +215,6 @@ void TFT_FSMC::transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t cou DMAtx.Init.PeriphInc = memoryIncrease; HAL_DMA_Init(&DMAtx); HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count); - - TERN_(TFT_SHARED_IO, while (isBusy())); } void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) { @@ -233,4 +227,4 @@ void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) } #endif // HAS_FSMC_TFT -#endif // HAL_STM32 +#endif // HAL_STM32 \ No newline at end of file diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index 1b3e761fbec4..819d9effecb8 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -31,10 +31,6 @@ #error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware." #endif -#ifndef HAL_SRAM_MODULE_ENABLED - #error "SRAM module disabled for the STM32 framework (HAL_SRAM_MODULE_ENABLED)! Please consult the development team." -#endif - #ifndef LCD_READ_ID #define LCD_READ_ID 0x04 // Read display identification information (0xD3 on ILI9341) #endif @@ -45,7 +41,7 @@ #define DATASIZE_8BIT SPI_DATASIZE_8BIT #define DATASIZE_16BIT SPI_DATASIZE_16BIT #define TFT_IO_DRIVER TFT_FSMC -#define DMA_MAX_WORDS 0xFFFF +#define DMA_MAX_WORDS 0xFFFF #define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT) typedef TERN(TFT_INTERFACE_FSMC_8BIT, uint8_t, uint16_t) tft_data_t; @@ -62,7 +58,7 @@ class TFT_FSMC { static LCD_CONTROLLER_TypeDef *LCD; - static uint32_t readID(const tft_data_t reg); + static uint32_t readID(tft_data_t reg); static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); } static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count); static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count); @@ -73,11 +69,11 @@ class TFT_FSMC { static bool isBusy(); static void abort(); - static void dataTransferBegin(uint16_t dataWidth=TFT_DATASIZE) {} - static void dataTransferEnd() {} + static void dataTransferBegin(uint16_t dataWidth = TFT_DATASIZE) {} + static void dataTransferEnd() {}; static void writeData(uint16_t data) { transmit(tft_data_t(data)); } - static void writeReg(const uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } + static void writeReg(uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } static void writeSequence_DMA(uint16_t *data, uint16_t count) { transmitDMA(DMA_PINC_ENABLE, data, count); } static void writeMultiple_DMA(uint16_t color, uint16_t count) { static uint16_t data; data = color; transmitDMA(DMA_PINC_DISABLE, &data, count); } @@ -213,4 +209,4 @@ const PinMap pinMap_FSMC_RS[] = { {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 #endif {NC, NP, 0} -}; +}; \ No newline at end of file From 8a050731ac3da1abbb6b229aecff34020599ce84 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Wed, 31 Jan 2024 20:22:17 -0600 Subject: [PATCH 12/22] format --- Marlin/src/HAL/STM32/tft/tft_fsmc.cpp | 125 +++++++++++++------------- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 10 +-- 2 files changed, 65 insertions(+), 70 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp index 242085ee59bb..d29e207b7dca 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp @@ -56,64 +56,64 @@ void TFT_FSMC::init() { // SRAMx.Init SRAMx.Init.NSBank = nsBank; #ifdef STM32F446xx - SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; SRAMx.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; - SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; + SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; + SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; + SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; #else - SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); + SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; #ifdef STM32F4xx SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; #endif #endif + // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller - // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss - timing.AddressSetupTime = 15; - timing.AddressHoldTime = 15; - timing.DataSetupTime = 24; - timing.BusTurnAroundDuration = 0; - timing.CLKDivision = 16; - timing.DataLatency = 17; + // Can be decreased from 15-15-24 to 4-4-8 with risk of stability loss + timing.AddressSetupTime = 15; + timing.AddressHoldTime = 15; + timing.DataSetupTime = 24; + timing.BusTurnAroundDuration = 0; + timing.CLKDivision = 16; + timing.DataLatency = 17; #ifdef STM32F446xx timing.AccessMode = FMC_ACCESS_MODE_A; #else timing.AccessMode = FSMC_ACCESS_MODE_A; #endif + // Write Timing - // Can be decreases from 8-15-8 to 0-0-1 with risk of stability loss - extTiming.AddressSetupTime = 8; - extTiming.AddressHoldTime = 15; - extTiming.DataSetupTime = 8; - extTiming.BusTurnAroundDuration = 0; - extTiming.CLKDivision = 16; - extTiming.DataLatency = 17; + // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss + extTiming.AddressSetupTime = 8; + extTiming.AddressHoldTime = 15; + extTiming.DataSetupTime = 8; + extTiming.BusTurnAroundDuration = 0; + extTiming.CLKDivision = 16; + extTiming.DataLatency = 17; #ifdef STM32F446xx extTiming.AccessMode = FMC_ACCESS_MODE_A; - __HAL_RCC_FMC_CLK_ENABLE(); #else extTiming.AccessMode = FSMC_ACCESS_MODE_A; - __HAL_RCC_FSMC_CLK_ENABLE(); #endif @@ -126,13 +126,13 @@ void TFT_FSMC::init() { #ifdef PF0 switch (nsBank) { #ifdef STM32F446xx - case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; - case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; - case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2; break; + case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3; break; + case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4; break; #else - case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; - case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break; - case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break; + case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2; break; + case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3; break; + case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4; break; #endif } #endif @@ -146,40 +146,35 @@ void TFT_FSMC::init() { #ifdef STM32F1xx DMAtx.Instance = DMA2_Channel1; #elif defined(STM32F4xx) - DMAtx.Instance = DMA2_Stream0; - DMAtx.Init.Channel = DMA_CHANNEL_0; - DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + DMAtx.Instance = DMA2_Stream0; + DMAtx.Init.Channel = DMA_CHANNEL_0; + DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; - DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; + DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; + DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; #endif - DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; - DMAtx.Init.MemInc = DMA_MINC_DISABLE; + DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; + DMAtx.Init.MemInc = DMA_MINC_DISABLE; DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - DMAtx.Init.Mode = DMA_NORMAL; - DMAtx.Init.Priority = DMA_PRIORITY_HIGH; + DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + DMAtx.Init.Mode = DMA_NORMAL; + DMAtx.Init.Priority = DMA_PRIORITY_HIGH; LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; } uint32_t TFT_FSMC::getID() { - uint32_t id; writeReg(0); - id = LCD->RAM; - - if (id == 0) - id = readID(LCD_READ_ID); - if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) - id = readID(LCD_READ_ID4); + uint32_t id = LCD->RAM; + if (id == 0) id = readID(LCD_READ_ID); + if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) id = readID(LCD_READ_ID4); return id; } uint32_t TFT_FSMC::readID(tft_data_t inReg) { - uint32_t id; writeReg(inReg); - id = LCD->RAM; // dummy read + uint32_t id = LCD->RAM; // dummy read id = inReg << 24; id |= (LCD->RAM & 0x00FF) << 16; id |= (LCD->RAM & 0x00FF) << 8; @@ -227,4 +222,4 @@ void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) } #endif // HAS_FSMC_TFT -#endif // HAL_STM32 \ No newline at end of file +#endif // HAL_STM32 diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index 819d9effecb8..9917890e7fb5 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -38,9 +38,9 @@ #define LCD_READ_ID4 0xD3 // Read display identification information (0xD3 on ILI9341) #endif -#define DATASIZE_8BIT SPI_DATASIZE_8BIT -#define DATASIZE_16BIT SPI_DATASIZE_16BIT -#define TFT_IO_DRIVER TFT_FSMC +#define DATASIZE_8BIT SPI_DATASIZE_8BIT +#define DATASIZE_16BIT SPI_DATASIZE_16BIT +#define TFT_IO_DRIVER TFT_FSMC #define DMA_MAX_WORDS 0xFFFF #define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT) @@ -69,7 +69,7 @@ class TFT_FSMC { static bool isBusy(); static void abort(); - static void dataTransferBegin(uint16_t dataWidth = TFT_DATASIZE) {} + static void dataTransferBegin(uint16_t dataWidth=TFT_DATASIZE) {} static void dataTransferEnd() {}; static void writeData(uint16_t data) { transmit(tft_data_t(data)); } @@ -209,4 +209,4 @@ const PinMap pinMap_FSMC_RS[] = { {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25 #endif {NC, NP, 0} -}; \ No newline at end of file +}; From 97cc2db8bf3492dab19e6d2afe7eb18dc75a6e6d Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Wed, 31 Jan 2024 20:41:04 -0600 Subject: [PATCH 13/22] add FMC_OR_FSMC macro --- Marlin/src/HAL/STM32/tft/tft_fsmc.cpp | 126 ++++++++++---------------- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 92 +++++++------------ 2 files changed, 81 insertions(+), 137 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp index d29e207b7dca..4dffe8b4fcc4 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp @@ -37,69 +37,45 @@ LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; void TFT_FSMC::init() { uint32_t controllerAddress; - #ifdef STM32F446xx - FMC_NORSRAM_TimingTypeDef timing, extTiming; - #else - FSMC_NORSRAM_TimingTypeDef timing, extTiming; - #endif + FMC_OR_FSMC(NORSRAM_TimingTypeDef) timing, extTiming; uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS); // Perform the SRAM1 memory initialization sequence - #ifdef STM32F446xx - SRAMx.Instance = FMC_NORSRAM_DEVICE; - SRAMx.Extended = FMC_NORSRAM_EXTENDED_DEVICE; - #else - SRAMx.Instance = FSMC_NORSRAM_DEVICE; - SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; - #endif + SRAMx.Instance = FMC_OR_FSMC(NORSRAM_DEVICE); + SRAMx.Extended = FMC_OR_FSMC(NORSRAM_EXTENDED_DEVICE); + // SRAMx.Init SRAMx.Init.NSBank = nsBank; + SRAMx.Init.DataAddressMux = FMC_OR_FSMC(DATA_ADDRESS_MUX_DISABLE); + SRAMx.Init.MemoryType = FMC_OR_FSMC(MEMORY_TYPE_SRAM); #ifdef STM32F446xx - SRAMx.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; - SRAMx.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; - SRAMx.Init.PageSize = FMC_PAGE_SIZE_NONE; + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16); #else - SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; - SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); - SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; - SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; - SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; - SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; - SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; - SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; - SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; - SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; - #ifdef STM32F4xx - SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE; - #endif + SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); + #endif + SRAMx.Init.BurstAccessMode = FMC_OR_FSMC(BURST_ACCESS_MODE_DISABLE); + SRAMx.Init.WaitSignalPolarity = FMC_OR_FSMC(WAIT_SIGNAL_POLARITY_LOW); + SRAMx.Init.WrapMode = FMC_OR_FSMC(WRAP_MODE_DISABLE); + SRAMx.Init.WaitSignalActive = FMC_OR_FSMC(WAIT_TIMING_BEFORE_WS); + SRAMx.Init.WriteOperation = FMC_OR_FSMC(WRITE_OPERATION_ENABLE); + SRAMx.Init.WaitSignal = FMC_OR_FSMC(WAIT_SIGNAL_DISABLE); + SRAMx.Init.ExtendedMode = FMC_OR_FSMC(EXTENDED_MODE_ENABLE); + SRAMx.Init.AsynchronousWait = FMC_OR_FSMC(ASYNCHRONOUS_WAIT_DISABLE); + SRAMx.Init.WriteBurst = FMC_OR_FSMC(WRITE_BURST_DISABLE); + #if defined(STM32F446xx) || defined(STM32F4xx) + SRAMx.Init.PageSize = FMC_OR_FSMC(PAGE_SIZE_NONE); #endif // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller // Can be decreased from 15-15-24 to 4-4-8 with risk of stability loss - timing.AddressSetupTime = 15; - timing.AddressHoldTime = 15; - timing.DataSetupTime = 24; - timing.BusTurnAroundDuration = 0; - timing.CLKDivision = 16; - timing.DataLatency = 17; - #ifdef STM32F446xx - timing.AccessMode = FMC_ACCESS_MODE_A; - #else - timing.AccessMode = FSMC_ACCESS_MODE_A; - #endif + timing.AddressSetupTime = 15; + timing.AddressHoldTime = 15; + timing.DataSetupTime = 24; + timing.BusTurnAroundDuration = 0; + timing.CLKDivision = 16; + timing.DataLatency = 17; + timing.AccessMode = FMC_OR_FSMC(ACCESS_MODE_A); // Write Timing // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss @@ -109,11 +85,11 @@ void TFT_FSMC::init() { extTiming.BusTurnAroundDuration = 0; extTiming.CLKDivision = 16; extTiming.DataLatency = 17; + extTiming.AccessMode = FMC_OR_FSMC(ACCESS_MODE_A); + #ifdef STM32F446xx - extTiming.AccessMode = FMC_ACCESS_MODE_A; __HAL_RCC_FMC_CLK_ENABLE(); #else - extTiming.AccessMode = FSMC_ACCESS_MODE_A; __HAL_RCC_FSMC_CLK_ENABLE(); #endif @@ -125,15 +101,9 @@ void TFT_FSMC::init() { controllerAddress = FSMC_BANK1_1; #ifdef PF0 switch (nsBank) { - #ifdef STM32F446xx - case FMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2; break; - case FMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3; break; - case FMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4; break; - #else - case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2; break; - case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3; break; - case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4; break; - #endif + case FMC_OR_FSMC(NORSRAM_BANK2): controllerAddress = FSMC_BANK1_2; break; + case FMC_OR_FSMC(NORSRAM_BANK3): controllerAddress = FSMC_BANK1_3; break; + case FMC_OR_FSMC(NORSRAM_BANK4): controllerAddress = FSMC_BANK1_4; break; } #endif @@ -144,22 +114,22 @@ void TFT_FSMC::init() { __HAL_RCC_DMA2_CLK_ENABLE(); #ifdef STM32F1xx - DMAtx.Instance = DMA2_Channel1; + DMAtx.Instance = DMA2_Channel1; #elif defined(STM32F4xx) - DMAtx.Instance = DMA2_Stream0; - DMAtx.Init.Channel = DMA_CHANNEL_0; - DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; - DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; + DMAtx.Instance = DMA2_Stream0; + DMAtx.Init.Channel = DMA_CHANNEL_0; + DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + DMAtx.Init.MemBurst = DMA_MBURST_SINGLE; + DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE; #endif - DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; - DMAtx.Init.MemInc = DMA_MINC_DISABLE; - DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - DMAtx.Init.Mode = DMA_NORMAL; - DMAtx.Init.Priority = DMA_PRIORITY_HIGH; + DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY; + DMAtx.Init.MemInc = DMA_MINC_DISABLE; + DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + DMAtx.Init.Mode = DMA_NORMAL; + DMAtx.Init.Priority = DMA_PRIORITY_HIGH; LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; } @@ -178,7 +148,7 @@ uint32_t TFT_FSMC::readID(tft_data_t inReg) { id = inReg << 24; id |= (LCD->RAM & 0x00FF) << 16; id |= (LCD->RAM & 0x00FF) << 8; - id |= LCD->RAM & 0x00FF; + id |= (LCD->RAM & 0x00FF); return id; } @@ -191,7 +161,9 @@ bool TFT_FSMC::isBusy() { #define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->PAR != 0) #endif - if (!__IS_DMA_CONFIGURED(&DMAtx)) return false; + #ifdef __IS_DMA_CONFIGURED + if (!__IS_DMA_CONFIGURED(&DMAtx)) return false; + #endif // Check if DMA transfer error or transfer complete flags are set if ((__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) == 0) && (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) == 0)) return true; diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index 9917890e7fb5..adf41329ccc5 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -51,6 +51,12 @@ typedef struct { __IO tft_data_t RAM; } LCD_CONTROLLER_TypeDef; +#ifdef STM32F446xx + #define FMC_OR_FSMC(N) _CAT(FMC_, N) +#else + #define FMC_OR_FSMC(N) _CAT(FSMC_, N) +#endif + class TFT_FSMC { private: static SRAM_HandleTypeDef SRAMx; @@ -104,71 +110,37 @@ class TFT_FSMC { #endif const PinMap pinMap_FSMC[] = { - #ifdef STM32F446xx - {PD_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 - {PD_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 - {PD_0, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 - {PD_1, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 - {PE_7, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 - {PE_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 - {PE_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 - {PE_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 - #if DISABLED(TFT_INTERFACE_FSMC_8BIT) - {PE_11, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 - {PE_12, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 - {PE_13, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 - {PE_14, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 - {PE_15, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 - {PD_8, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 - {PD_9, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 - {PD_10, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 - #endif - {PD_4, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE - {PD_5, FMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE - {NC, NP, 0} - #else - {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00 - {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01 - {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02 - {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03 - {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04 - {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 - {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 - {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 - #if DISABLED(TFT_INTERFACE_FSMC_8BIT) - {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 - {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 - {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 - {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 - {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 - {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 - {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 - {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 - #endif - {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE - {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE - {NC, NP, 0} + {PD_14, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D00 + {PD_15, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D01 + {PD_0, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D02 + {PD_1, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D03 + {PE_7, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D04 + {PE_8, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D05 + {PE_9, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D06 + {PE_10, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D07 + #if DISABLED(TFT_INTERFACE_FSMC_8BIT) + {PE_11, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D08 + {PE_12, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D09 + {PE_13, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D10 + {PE_14, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D11 + {PE_15, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D12 + {PD_8, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D13 + {PD_9, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D14 + {PD_10, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D15 #endif + {PD_4, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_NOE + {PD_5, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_NWE + {NC, NP, 0} }; const PinMap pinMap_FSMC_CS[] = { - #ifdef STM32F446xx - {PD_7, (void *)FMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 - #ifdef PF0 - {PG_9, (void *)FMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 - {PG_10, (void *)FMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 - {PG_12, (void *)FMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 - #endif - {NC, NP, 0} - #else - {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1 - #ifdef PF0 - {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2 - {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3 - {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4 - #endif - {NC, NP, 0} + {PD_7, (void *)FMC_OR_FSMC(NORSRAM_BANK1), FSMC_PIN_DATA}, // FSMC_NE1 + #ifdef PF0 + {PG_9, (void *)FMC_OR_FSMC(NORSRAM_BANK2), FSMC_PIN_DATA}, // FSMC_NE2 + {PG_10, (void *)FMC_OR_FSMC(NORSRAM_BANK3), FSMC_PIN_DATA}, // FSMC_NE3 + {PG_12, (void *)FMC_OR_FSMC(NORSRAM_BANK4), FSMC_PIN_DATA}, // FSMC_NE4 #endif + {NC, NP, 0} }; #if ENABLED(TFT_INTERFACE_FSMC_8BIT) From 3cb908f91f0e8c4865ddfdd3072959dbf0b09a18 Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Wed, 31 Jan 2024 22:48:03 -0600 Subject: [PATCH 14/22] Clean up. Clean up pins_TRONXY_CXY_446_V10.h. Clean up stm32f4.ini. --- .../pins/stm32f4/pins_TRONXY_CXY_446_V10.h | 401 ++++++------------ ini/stm32f4.ini | 4 +- 2 files changed, 143 insertions(+), 262 deletions(-) diff --git a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h index 5c5080259f9a..79cbbe59b3e2 100644 --- a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h +++ b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h @@ -30,345 +30,226 @@ #include "env_validate.h" -#if HOTENDS > 2 || E_STEPPERS > 2 || NUM_RUNOUT_SENSORS > 2 - #error "Only 2 Hotends / E steppers / Filament Runout sensors are currently supported!" +#if EXTRUDERS > 2 || E_STEPPERS > 2 || NUM_RUNOUT_SENSORS > 2 + #error "TRONXY CXY 446 V10 only supports 2 Extruders / E steppers / Filament Runout sensors." #endif -#define BOARD_INFO_NAME "BOARD_TRONXY_CXY_446_V10" -#define DEFAULT_MACHINE_NAME BOARD_INFO_NAME +#define BOARD_INFO_NAME "BOARD_TRONXY_CXY_446_V10" +#define DEFAULT_MACHINE_NAME "TRONXY CXY 446 V10" -#define STEP_TIMER 6 +#define STEP_TIMER 6 #define TEMP_TIMER 14 // // EEPROM // - -// Onboard I2C EEPROM #if NO_EEPROM_SELECTED - #undef NO_EEPROM_SELECTED #define I2C_EEPROM - #define MARLIN_EEPROM_SIZE 0x800 // 2K (FT24C16A) + //#define FLASH_EEPROM_EMULATION + #undef NO_EEPROM_SELECTED +#endif + +#if ENABLED(FLASH_EEPROM_EMULATION) + #define EEPROM_START_ADDRESS (0x8000000UL + (512 * 1024) - 2 * EEPROM_PAGE_SIZE) + #define EEPROM_PAGE_SIZE (0x800U) // 2K, but will use 2x more (4K) + #define MARLIN_EEPROM_SIZE EEPROM_PAGE_SIZE +#else + #define MARLIN_EEPROM_SIZE 0x800 // 2K (FT24C16A) #endif // // SPI Flash // -#define SPI_FLASH // W25Q16 - +#define SPI_FLASH // W25Q16 #if ENABLED(SPI_FLASH) - #define SPI_DEVICE 1 - #define SPI_FLASH_SIZE 0x1000000 // 16MB - // SPI1/SPI3 - #define SPI_FLASH_CS_PIN PG15 // W25Q16 CS - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT - #define SPI_FLASH_MOSI_PIN PB5 // W25Q16 DIN - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, FMC_SDCKE1, DCMI_D10, EVENTOUT - #define SPI_FLASH_MISO_PIN PB4 // W25Q16 DOUT - NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, EVENTOUT - #define SPI_FLASH_SCK_PIN PB3 // W25Q16 DCLK - JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, EVENTOUT + #define SPI_FLASH_SIZE 0x1000000 // 16MB + #define SPI_FLASH_CS_PIN PG15 + #define SPI_FLASH_MOSI_PIN PB5 + #define SPI_FLASH_MISO_PIN PB4 + #define SPI_FLASH_SCK_PIN PB3 #endif // -// Limit Switches +// SD Card / Flash Drive +// +#define HAS_OTG_USB_HOST_SUPPORT // USB Flash Drive Support + +// +// SD Card // -#define X_STOP_PIN PC15 // X STOP SW - EVENTOUT, OSC32_OUT +#define ONBOARD_SDIO +#define SD_DETECT_PIN -1 +#define SDIO_CLOCK 4500000 +#define SDIO_READ_RETRIES 16 -#define X_MIN_PIN X_STOP_PIN -#define X_MAX_PIN PB0 // E0 TMC UART candidate - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUT, ADC12_IN8 +#define SDIO_D0_PIN PC8 +#define SDIO_D1_PIN PC9 +#define SDIO_D2_PIN PC10 +#define SDIO_D3_PIN PC11 +#define SDIO_CK_PIN PC12 +#define SDIO_CMD_PIN PD2 -#define Y_STOP_PIN PC14 // Y STOP SW - EVENTOUT, OSC32_IN +// +// Limit Switches +// +#define X_STOP_PIN PC15 +#define Y_STOP_PIN PC14 -#if ENABLED(Z_MULTI_ENDSTOPS) - #if X_HOME_DIR > 0 // Swap Z1/Z2 for dual Z with max homing - #define Z_MIN_PIN PF11 // Z2 STOP SW - SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT - #define Z_MAX_PIN PC13 // Z STOP SW - EVENTOUT, TAMP_1/WKUP1 - #else - #define Z_MIN_PIN PC13 // Z STOP SW - #define Z_MAX_PIN PF11 // Z2 STOP SW - #endif - // PE3 is usually connected to Probe - #if ENABLED(FIX_MOUNTED_PROBE) - #define Z_MIN_PROBE_PIN PE3 // BED PROBE - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT - #endif -#elif ENABLED(FIX_MOUNTED_PROBE) - #define Z_STOP_PIN PE3 // BED PROBE +#if ENABLED(FIX_MOUNTED_PROBE) + #define Z_STOP_PIN PE3 #else - #define Z_STOP_PIN PC13 // Z STOP SW + #define Z_STOP_PIN PC13 #endif // // Filament Sensors // #if ENABLED(FILAMENT_RUNOUT_SENSOR) - #define FIL_RUNOUT_PIN PE6 // E0 STOP SW - TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, EVENTOUT - - #if NUM_RUNOUT_SENSORS == 2 - #define FIL_RUNOUT2_PIN PF12 // E1 STOP SW - FMC_A6, EVENTOUT - #endif + #define FIL_RUNOUT_PIN PE6 + #define FIL_RUNOUT2_PIN PF12 #endif // // Steppers // -#define X_ENABLE_PIN PF0 // X TMC2225 EN - I2C2_SDA, FMC_A0, EVENTOUT -#define X_STEP_PIN PE5 // X TMC2225 STEP - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, EVENTOUT -#define X_DIR_PIN PF1 // X TMC2225 DIR - I2C2_SCL, FMC_A1, EVENTOUT - -#define Y_ENABLE_PIN PF5 // Y TMC2225 EN - FMC_A5, EVENTOUT, ADC3_IN15 -#define Y_STEP_PIN PF9 // Y TMC2225 STEP - SAI1_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT, ADC3_IN7 -#define Y_DIR_PIN PF3 // Y TMC2225 DIR - FMC_A3, EVENTOUT, ADC3_IN9 - -#define Z_ENABLE_PIN PA5 // Z TMC2225 EN - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT, ADC12_IN5, DAC_OUT2 -#define Z_STEP_PIN PA6 // Z TMC2225 STEP - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, DCMI_PIXCLK, EVENTOUT, ADC12_IN6 -#define Z_DIR_PIN PF15 // Z TMC2225 DIR - FMPI2C1_SDA, FMC_A9, EVENTOUT - -#ifdef Z2_DRIVER_TYPE - #define Z2_ENABLE_PIN PF7 // Z2 TMC2225 EN - TIM11_CH1, SAI1_MCLK_B, QUADSPI_BK1_IO2, EVENTOUT, ADC3_IN5 - #define Z2_STEP_PIN PF6 // Z2 TMC2225 STEP - TIM10_CH1, SAI1_SD_B, QUADSPI_BK1_IO3, EVENTOUT, ADC3_IN4 - #define Z2_DIR_PIN PF4 // Z2 TMC2225 DIR - FMC_A4, EVENTOUT, ADC3_IN14 -#endif +#define X_ENABLE_PIN PF0 +#define X_STEP_PIN PE5 +#define X_DIR_PIN PF1 -#define E0_ENABLE_PIN PF14 // E0 TMC2225 EN - FMPI2C1_SCL, FMC_A8, EVENTOUT -#define E0_STEP_PIN PB1 // E0 TMC2225 STEP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, SDIO_D2, EVENTOUT, ADC12_IN9 -#define E0_DIR_PIN PF13 // E0 TMC2225 DIR - FMPI2C1_SMBA, FMC_A7, EVENTOUT - -#if (EXTRUDERS == 2) - #ifndef E1_DRIVER_TYPE - #error "E1_DRIVER_TYPE must be defined in Configuration.h to use 2 extruders!" - #else - #define E1_ENABLE_PIN PG5 // E1 TMC2225 EN - FMC_A15/FMC_BA1, EVENTOUT - #define E1_STEP_PIN PD12 // E1 TMC2225 STEP - TIM4_CH1, FMPI2C1_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, EVENTOUT - #define E1_DIR_PIN PG4 // E1 TMC2225 DIR - FMC_A14/FMC_BA0, EVENTOUT - #endif -#endif +#define Y_ENABLE_PIN PF5 +#define Y_STEP_PIN PF9 +#define Y_DIR_PIN PF3 -#if HAS_TMC_UART - /** - * TMC2208/TMC2209 Software Serial - * - * Only uses 1 pin for UART - * Modification to board required. - * - * Use at your own risk!!! - * - * Instructions: https://zenn.dev/marbocub/articles/tronxy-stm32f4-mainboard-tmc-serial-wiring - */ - // Comment out error line below once pins have been configured to continue. - #error "TMC UART not supported by default on this board. Board modification required. See pins_TRONXY_CXY_446_V10.h for details." - /* - #define X_SERIAL_TX_PIN PE4 // TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, EVENTOUT - #define X_SERIAL_RX_PIN X_SERIAL_TX_PIN - - #define Y_SERIAL_TX_PIN PF2 // I2C2_SMBA, FMC_A2, EVENTOUT - #define Y_SERIAL_RX_PIN Y_SERIAL_TX_PIN - - #define Z_SERIAL_TX_PIN PA4 // SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, EVENTOUTADC12_IN4, DAC_OUT1 - #define Z_SERIAL_RX_PIN Z_SERIAL_TX_PIN - - #ifdef Z2_DRIVER_TYPE - #define Z2_SERIAL_TX_PIN PF8 // SAI1_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT - #define Z2_SERIAL_RX_PIN Z2_SERIAL_TX_PIN - #endif +#define Z_ENABLE_PIN PA5 +#define Z_STEP_PIN PA6 +#define Z_DIR_PIN PF15 - #define E0_SERIAL_TX_PIN PB0 // TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MOSI/I2S3_SD, UART4_CTS, OTG_HS_ULPI_D1, SDIO_D1, EVENTOUTADC12_IN8 - #define E0_SERIAL_RX_PIN E0_SERIAL_TX_PIN +#define E0_ENABLE_PIN PF14 +#define E0_STEP_PIN PB1 +#define E0_DIR_PIN PF13 - // Unsure on this pin assignment - //#define E1_SERIAL_TX_PIN PD5 // USART2_TX, FMC_NWE, EVENTOUT - //#define E1_SERIAL_RX_PIN E1_SERIAL_TX_PIN - */ -#endif +#define E1_ENABLE_PIN PG5 +#define E1_STEP_PIN PD12 +#define E1_DIR_PIN PG4 // // Temperature Sensors // -#define TEMP_0_PIN PC3 // Hotend #1 Therm - SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT, ADC123_IN13 - -#if EXTRUDERS == 2 - #define TEMP_1_PIN PC0 // Hotend #2 Therm - SAI1_MCLK_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT, ADC123_IN10 -#endif - -#define TEMP_BED_PIN PC2 // Bed Therm - SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT, ADC123_IN12 +#define TEMP_0_PIN PC3 +#define TEMP_1_PIN PC0 +#define TEMP_BED_PIN PC2 // // Heaters // -#define HEATER_0_PIN PG7 // Hotend #1 Heater - USART6_CK, FMC_INT, DCMI_D13, EVENTOUT - -#if EXTRUDERS == 2 - #define HEATER_1_PIN PA15 // Hotend #2 Heater - JTDI, TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT -#endif - -#define HEATER_BED_PIN PE2 // Bed Heater - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT +#define HEATER_0_PIN PG7 // Hotend #1 Heater +#define HEATER_1_PIN PA15 // Hotend #2 Heater +#define HEATER_BED_PIN PE2 // // Fans // -#define FAN0_PIN PG0 // Part Cooling Fan #1 - FMC_A10, EVENTOUT - -#if EXTRUDERS == 2 - #define FAN1_PIN PB6 // Part Cooling Fan #2 - TIM4_CH1, HDMI_CEC, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, FMC_SDNE1, DCMI_D5, EVENTOUT - #define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT - #define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan - DCMI_D11, EVENTOUT, ADC3_IN8 -#else - #define FAN1_PIN PG9 // Extruder/Hotend #1 Heatsink Fan - SPDIFRX_IN3, USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE3, DCMI_VSYNC, EVENTOUT -#endif - -#define CONTROLLER_FAN_PIN PD7 // USART2_CK, SPDIFRX_IN0, FMC_NE1, EVENTOUT - -// Define so that hotend heatsink fans automatically start when hotends reach 50 degrees. -#if EXTRUDERS == 2 - #undef E0_AUTO_FAN_PIN - #undef E1_AUTO_FAN_PIN - #define E0_AUTO_FAN_PIN FAN2_PIN - #define E1_AUTO_FAN_PIN FAN3_PIN -#else - #undef E0_AUTO_FAN_PIN - #define E0_AUTO_FAN_PIN FAN1_PIN -#endif - #define FAN_SOFT_PWM_REQUIRED +#define FAN0_PIN PG0 // Part Cooling Fan #1 +#define FAN1_PIN PB6 // Part Cooling Fan #2 +#define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan +#define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan +#define CONTROLLER_FAN_PIN PD7 + // // Laser / Servos // -// NOTE: SPINDLE_LASER_PWM_PIN and SERVO0_PIN are the same pin. -// Only one feature can be enabled at a time. +#define SPINDLE_LASER_ENA_PIN PB11 // WiFi Module TXD (Pin5) +#define SPINDLE_LASER_PWM_PIN PB10 // WiFi Module RXD (Pin4) +// +// NOTE: The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be compounded here. +// See PWM_PIN(x) definition for details. // -#if ENABLED(LASER_FEATURE) - #if NUM_SERVOS > 0 - #error "NUM_SERVOS must equal 0 to enable LASER_FEATURE" - #else - #define SPINDLE_LASER_ENA_PIN PB11 // WiFi TXD (Pin5) - TIM2_CH4, I2C2_SDA, USART3_RX, SAI2_SD_A, EVENTOUT - #if ENABLED(SPINDLE_LASER_USE_PWM) - #define SPINDLE_LASER_PWM_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT - /** - * NOTE: The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be compounded here. - * See PWM_PIN(x) definition for details. - */ - #endif - #endif -#endif - -#if NUM_SERVOS > 0 - #if ENABLED(LASER_FEATURE) - #error "LASER_FEATURE must be disabled to set NUM_SERVOS greater than 0" - #elif NUM_SERVOS > 1 - #error "Only one servo is currently supported" - #else - #define SERVO0_PIN PB10 // WiFi RXD (Pin4) - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, SAI1_SCK_A, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT - /** - * Enabled after enabling NUM_SERVOS > 0. - * - * NOTE: Shares PB10 pin with laser. Features cannot be enabled at the same time. - */ - #endif -#endif // // TFT with FSMC interface // -#if ANY(TFT_TRONXY_X5SA, MKS_ROBIN_TFT43) +#if HAS_FSMC_TFT + #define TOUCH_CS_PIN PD11 + #define TOUCH_SCK_PIN PB13 + #define TOUCH_MISO_PIN PB14 + #define TOUCH_MOSI_PIN PB15 - // SPI2 - #define TOUCH_CS_PIN PD11 // TOUCH SCREEN HR2046 CS - FMPI2C1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT - #define TOUCH_SCK_PIN PB13 // TOUCH SCREEN HR2046 DCLK - TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, EVENTOUT - #define TOUCH_MISO_PIN PB14 // TOUCH SCREEN HR2046 DOUT - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT - #define TOUCH_MOSI_PIN PB15 // TOUCH SCREEN HR2046 DIN - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, EVENTOUT + #define TFT_RESET_PIN PB12 + #define TFT_BACKLIGHT_PIN PG8 - #define TFT_RESET_PIN PB12 // TOUCH SCREEN HR2046 CS - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SAI1_SCK_B, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT - #define TFT_BACKLIGHT_PIN PG8 // LCD MODULE BACKLIGHT - SPDIFRX_IN2, USART6_RTS, FMC_SDCLK, EVENTOUT + #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT + #define FSMC_DMA_DEV DMA2 + #define FSMC_DMA_CHANNEL DMA_CH5 + #define FSMC_CS_PIN PG12 + #define FSMC_RS_PIN PG2 - #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT - #define FSMC_DMA_DEV DMA2 - #define FSMC_DMA_CHANNEL DMA_CH5 - - #define TFT_CS_PIN PG12 // SPI4_MISO, SPDIFRX_IN1, USART6_RTS, FMC_NE4, EVENTOUT - #define TFT_RS_PIN PG2 // FMC_A12, EVENTOUT - - #define FSMC_CS_PIN TFT_CS_PIN - #define FSMC_RS_PIN TFT_RS_PIN + #define TFT_CS_PIN FSMC_CS_PIN + #define TFT_RS_PIN FSMC_RS_PIN #if ENABLED(TFT_LVGL_UI) - #define HAS_SPI_FLASH_FONT 1 - #define HAS_GCODE_PREVIEW 1 - #define HAS_GCODE_DEFAULT_VIEW_IN_FLASH 0 - #define HAS_LANG_SELECT_SCREEN 1 - #define HAS_BAK_VIEW_IN_FLASH 0 - #define HAS_LOGO_IN_FLASH 0 - #elif ENABLED(TFT_COLOR_UI) - #define TFT_DRIVER ILI9488 - #define TFT_BUFFER_SIZE 14400 + #define HAS_SPI_FLASH_FONT 1 + #define HAS_GCODE_PREVIEW 1 + #define HAS_GCODE_DEFAULT_VIEW_IN_FLASH 0 + #define HAS_LANG_SELECT_SCREEN 1 + #define HAS_BAK_VIEW_IN_FLASH 0 + #define HAS_LOGO_IN_FLASH 0 + #elif ANY(TFT_CLASSIC_UI, TFT_COLOR_UI) + //#define TFT_DRIVER ILI9488 + #define TFT_BUFFER_WORDS 14400 #endif // Touch Screen calibration - #if ANY(TFT_LVGL_UI, TFT_COLOR_UI, TFT_CLASSIC_UI) - #if DISABLED(TOUCH_SCREEN_CALIBRATION) - #error "TFT screen requires TOUCH_SCREEN_CALIBRATION" - #elif ANY(TOUCH_CALIBRATION_X, TOUCH_CALIBRATION_Y, TOUCH_OFFSET_X, TOUCH_OFFSET_Y) - #undef TOUCH_CALIBRATION_X - #undef TOUCH_CALIBRATION_Y - #undef TOUCH_OFFSET_X - #undef TOUCH_OFFSET_Y + #if ENABLED(TFT_TRONXY_X5SA) + #ifndef TOUCH_CALIBRATION_X + #define TOUCH_CALIBRATION_X -17181 + #endif + #ifndef TOUCH_CALIBRATION_Y + #define TOUCH_CALIBRATION_Y 11434 + #endif + #ifndef TOUCH_OFFSET_X + #define TOUCH_OFFSET_X 501 + #endif + #ifndef TOUCH_OFFSET_Y + #define TOUCH_OFFSET_Y -9 #endif - #if ENABLED(TFT_TRONXY_X5SA) - #define TOUCH_CALIBRATION_X -17181 - #define TOUCH_CALIBRATION_Y 11434 - #define TOUCH_OFFSET_X 501 - #define TOUCH_OFFSET_Y -9 - #elif ENABLED(MKS_ROBIN_TFT43) - #define XPT2046_X_CALIBRATION 17184 - #define XPT2046_Y_CALIBRATION 10604 - #define XPT2046_X_OFFSET -31 - #define XPT2046_Y_OFFSET -29 + #ifndef TOUCH_ORIENTATION + #define TOUCH_ORIENTATION TOUCH_LANDSCAPE #endif #endif -#else - #error "Only TFT_TRONXY_X5SA and MKS_ROBIN_TFT43 are currently supported with this board." -#endif - -// -// SD Card / Flash Drive -// - -// USB Flash Drive Support -#if ENABLED(USBHOST_HS_EN) - #define HAS_OTG_USB_HOST_SUPPORT + + #if ENABLED(MKS_ROBIN_TFT43) + #ifndef TOUCH_CALIBRATION_X + #define TOUCH_CALIBRATION_X 17184 + #endif + #ifndef TOUCH_CALIBRATION_Y + #define TOUCH_CALIBRATION_Y 10604 + #endif + #ifndef TOUCH_OFFSET_X + #define TOUCH_OFFSET_X -31 + #endif + #ifndef TOUCH_OFFSET_Y + #define TOUCH_OFFSET_Y -29 + #endif + #ifndef TOUCH_ORIENTATION + #define TOUCH_ORIENTATION TOUCH_LANDSCAPE + #endif + #endif +#else + #error "TRONXY CXY 446 V10 only supports TFT with FSMC interface." #endif // -// SD Card +// Power Loss // -#define ONBOARD_SDIO -#define SD_DETECT_PIN -1 // PF0, but not connected -#define SDIO_CLOCK 4500000 -#define SDIO_READ_RETRIES 16 - -#define SDIO_D0_PIN PC8 // TRACED0, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT -#define SDIO_D1_PIN PC9 // MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDIO_D1, DCMI_D3, EVENTOUT -#define SDIO_D2_PIN PC10 // SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDIO_D2, DCMI_D8, EVENTOUT -#define SDIO_D3_PIN PC11 // SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDIO_D3, DCMI_D4, EVENTOUT -#define SDIO_CK_PIN PC12 // I2C2_SDA, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, EVENTOUT -#define SDIO_CMD_PIN PD2 // TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT - -// -// Power Loss / Power Supply Control -// -// NOTE: PS_ON_PIN and LED_PIN are the same pin. -// - #if ENABLED(PSU_CONTROL) - // LED - Temporarily switch the machine with LED simulation - #define PS_ON_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT - // 24V DET - Output of LM393 comparator, configured as pullup - #define POWER_LOSS_PIN PE1 // FMC_NBL1, DCMI_D3, EVENTOUT - // +V for the LM393 comparator, configured as output high - #define POWER_LM393_PIN PE0 // TIM4_ETR, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT + #define PS_ON_PIN PG10 + #define POWER_LOSS_PIN PE1 #endif // // Misc. Functions // -#ifndef PS_ON_PIN - #define LED_PIN PG10 // SAI2_SD_B, FMC_NE3, DCMI_D2, EVENTOUT -#endif - -#define BEEPER_PIN PA8 // MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT +//#define LED_PIN PG10 +#define BEEPER_PIN PA8 diff --git a/ini/stm32f4.ini b/ini/stm32f4.ini index 99ccf30d329a..6fd457c91e3b 100644 --- a/ini/stm32f4.ini +++ b/ini/stm32f4.ini @@ -821,7 +821,7 @@ board_build.ldscript = buildroot/share/PlatformIO/variants/MARLIN_F446Zx_TRONXY/ board_build.offset = 0x10000 board_build.rename = fmw_tronxy.bin build_flags = ${stm32_variant.build_flags} - -DSTM32F4xx -DUSE_USBHOST_FS + -DSTM32F4xx -DUSE_USB_HS_IN_FS build_unflags = ${stm32_variant.build_unflags} -fno-rtti -fno-threadsafe-statics -fno-exceptions -DUSBD_USE_CDC -DUSBCON @@ -837,7 +837,7 @@ platform_packages = ${stm_flash_drive.platform_packages} build_flags = ${env:TRONXY_CXY_446_V10.build_flags} -DHAL_PCD_MODULE_ENABLED -DUSBHOST -DUSBH_IRQ_PRIO=3 -DUSBH_IRQ_SUBPRIO=4 - -DUSBHOST_HS_EN=1 + -DUSBHOST_HS # # Blackpill From a28a97fdd28ba4cf936bf58b5bbd5c0dc2877dde Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Thu, 1 Feb 2024 15:12:06 -0600 Subject: [PATCH 15/22] run pinsformat.js --- .../pins/stm32f4/pins_TRONXY_CXY_446_V10.h | 148 +++++++++--------- 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h index 79cbbe59b3e2..977cae0ab525 100644 --- a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h +++ b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h @@ -60,13 +60,13 @@ // // SPI Flash // -#define SPI_FLASH // W25Q16 +#define SPI_FLASH // W25Q16 #if ENABLED(SPI_FLASH) #define SPI_FLASH_SIZE 0x1000000 // 16MB - #define SPI_FLASH_CS_PIN PG15 - #define SPI_FLASH_MOSI_PIN PB5 - #define SPI_FLASH_MISO_PIN PB4 - #define SPI_FLASH_SCK_PIN PB3 + #define SPI_FLASH_CS_PIN PG15 + #define SPI_FLASH_MOSI_PIN PB5 + #define SPI_FLASH_MISO_PIN PB4 + #define SPI_FLASH_SCK_PIN PB3 #endif // @@ -78,90 +78,90 @@ // SD Card // #define ONBOARD_SDIO -#define SD_DETECT_PIN -1 +#define SD_DETECT_PIN -1 #define SDIO_CLOCK 4500000 #define SDIO_READ_RETRIES 16 -#define SDIO_D0_PIN PC8 -#define SDIO_D1_PIN PC9 -#define SDIO_D2_PIN PC10 -#define SDIO_D3_PIN PC11 -#define SDIO_CK_PIN PC12 -#define SDIO_CMD_PIN PD2 +#define SDIO_D0_PIN PC8 +#define SDIO_D1_PIN PC9 +#define SDIO_D2_PIN PC10 +#define SDIO_D3_PIN PC11 +#define SDIO_CK_PIN PC12 +#define SDIO_CMD_PIN PD2 // // Limit Switches // -#define X_STOP_PIN PC15 -#define Y_STOP_PIN PC14 +#define X_STOP_PIN PC15 +#define Y_STOP_PIN PC14 #if ENABLED(FIX_MOUNTED_PROBE) - #define Z_STOP_PIN PE3 + #define Z_STOP_PIN PE3 #else - #define Z_STOP_PIN PC13 + #define Z_STOP_PIN PC13 #endif // // Filament Sensors // #if ENABLED(FILAMENT_RUNOUT_SENSOR) - #define FIL_RUNOUT_PIN PE6 - #define FIL_RUNOUT2_PIN PF12 + #define FIL_RUNOUT_PIN PE6 + #define FIL_RUNOUT2_PIN PF12 #endif // // Steppers // -#define X_ENABLE_PIN PF0 -#define X_STEP_PIN PE5 -#define X_DIR_PIN PF1 +#define X_ENABLE_PIN PF0 +#define X_STEP_PIN PE5 +#define X_DIR_PIN PF1 -#define Y_ENABLE_PIN PF5 -#define Y_STEP_PIN PF9 -#define Y_DIR_PIN PF3 +#define Y_ENABLE_PIN PF5 +#define Y_STEP_PIN PF9 +#define Y_DIR_PIN PF3 -#define Z_ENABLE_PIN PA5 -#define Z_STEP_PIN PA6 -#define Z_DIR_PIN PF15 +#define Z_ENABLE_PIN PA5 +#define Z_STEP_PIN PA6 +#define Z_DIR_PIN PF15 -#define E0_ENABLE_PIN PF14 -#define E0_STEP_PIN PB1 -#define E0_DIR_PIN PF13 +#define E0_ENABLE_PIN PF14 +#define E0_STEP_PIN PB1 +#define E0_DIR_PIN PF13 -#define E1_ENABLE_PIN PG5 -#define E1_STEP_PIN PD12 -#define E1_DIR_PIN PG4 +#define E1_ENABLE_PIN PG5 +#define E1_STEP_PIN PD12 +#define E1_DIR_PIN PG4 // // Temperature Sensors // -#define TEMP_0_PIN PC3 -#define TEMP_1_PIN PC0 -#define TEMP_BED_PIN PC2 +#define TEMP_0_PIN PC3 +#define TEMP_1_PIN PC0 +#define TEMP_BED_PIN PC2 // // Heaters // -#define HEATER_0_PIN PG7 // Hotend #1 Heater -#define HEATER_1_PIN PA15 // Hotend #2 Heater -#define HEATER_BED_PIN PE2 +#define HEATER_0_PIN PG7 // Hotend #1 Heater +#define HEATER_1_PIN PA15 // Hotend #2 Heater +#define HEATER_BED_PIN PE2 // // Fans // #define FAN_SOFT_PWM_REQUIRED -#define FAN0_PIN PG0 // Part Cooling Fan #1 -#define FAN1_PIN PB6 // Part Cooling Fan #2 -#define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan -#define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan -#define CONTROLLER_FAN_PIN PD7 +#define FAN0_PIN PG0 // Part Cooling Fan #1 +#define FAN1_PIN PB6 // Part Cooling Fan #2 +#define FAN2_PIN PG9 // Extruder/Hotend #1 Heatsink Fan +#define FAN3_PIN PF10 // Extruder/Hotend #2 Heatsink Fan +#define CONTROLLER_FAN_PIN PD7 // // Laser / Servos // -#define SPINDLE_LASER_ENA_PIN PB11 // WiFi Module TXD (Pin5) -#define SPINDLE_LASER_PWM_PIN PB10 // WiFi Module RXD (Pin4) +#define SPINDLE_LASER_ENA_PIN PB11 // WiFi Module TXD (Pin5) +#define SPINDLE_LASER_PWM_PIN PB10 // WiFi Module RXD (Pin4) // // NOTE: The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be compounded here. // See PWM_PIN(x) definition for details. @@ -171,22 +171,22 @@ // TFT with FSMC interface // #if HAS_FSMC_TFT - #define TOUCH_CS_PIN PD11 - #define TOUCH_SCK_PIN PB13 - #define TOUCH_MISO_PIN PB14 - #define TOUCH_MOSI_PIN PB15 + #define TOUCH_CS_PIN PD11 + #define TOUCH_SCK_PIN PB13 + #define TOUCH_MISO_PIN PB14 + #define TOUCH_MOSI_PIN PB15 - #define TFT_RESET_PIN PB12 - #define TFT_BACKLIGHT_PIN PG8 + #define TFT_RESET_PIN PB12 + #define TFT_BACKLIGHT_PIN PG8 #define LCD_USE_DMA_FSMC // Use DMA transfers to send data to the TFT - #define FSMC_DMA_DEV DMA2 - #define FSMC_DMA_CHANNEL DMA_CH5 - #define FSMC_CS_PIN PG12 - #define FSMC_RS_PIN PG2 + #define FSMC_DMA_DEV DMA2 + #define FSMC_DMA_CHANNEL DMA_CH5 + #define FSMC_CS_PIN PG12 + #define FSMC_RS_PIN PG2 - #define TFT_CS_PIN FSMC_CS_PIN - #define TFT_RS_PIN FSMC_RS_PIN + #define TFT_CS_PIN FSMC_CS_PIN + #define TFT_RS_PIN FSMC_RS_PIN #if ENABLED(TFT_LVGL_UI) #define HAS_SPI_FLASH_FONT 1 @@ -196,44 +196,44 @@ #define HAS_BAK_VIEW_IN_FLASH 0 #define HAS_LOGO_IN_FLASH 0 #elif ANY(TFT_CLASSIC_UI, TFT_COLOR_UI) - //#define TFT_DRIVER ILI9488 - #define TFT_BUFFER_WORDS 14400 + //#define TFT_DRIVER ILI9488 + #define TFT_BUFFER_WORDS 14400 #endif // Touch Screen calibration #if ENABLED(TFT_TRONXY_X5SA) #ifndef TOUCH_CALIBRATION_X - #define TOUCH_CALIBRATION_X -17181 + #define TOUCH_CALIBRATION_X -17181 #endif #ifndef TOUCH_CALIBRATION_Y - #define TOUCH_CALIBRATION_Y 11434 + #define TOUCH_CALIBRATION_Y 11434 #endif #ifndef TOUCH_OFFSET_X - #define TOUCH_OFFSET_X 501 + #define TOUCH_OFFSET_X 501 #endif #ifndef TOUCH_OFFSET_Y - #define TOUCH_OFFSET_Y -9 + #define TOUCH_OFFSET_Y -9 #endif #ifndef TOUCH_ORIENTATION - #define TOUCH_ORIENTATION TOUCH_LANDSCAPE + #define TOUCH_ORIENTATION TOUCH_LANDSCAPE #endif #endif #if ENABLED(MKS_ROBIN_TFT43) #ifndef TOUCH_CALIBRATION_X - #define TOUCH_CALIBRATION_X 17184 + #define TOUCH_CALIBRATION_X 17184 #endif #ifndef TOUCH_CALIBRATION_Y - #define TOUCH_CALIBRATION_Y 10604 + #define TOUCH_CALIBRATION_Y 10604 #endif #ifndef TOUCH_OFFSET_X - #define TOUCH_OFFSET_X -31 + #define TOUCH_OFFSET_X -31 #endif #ifndef TOUCH_OFFSET_Y - #define TOUCH_OFFSET_Y -29 + #define TOUCH_OFFSET_Y -29 #endif #ifndef TOUCH_ORIENTATION - #define TOUCH_ORIENTATION TOUCH_LANDSCAPE + #define TOUCH_ORIENTATION TOUCH_LANDSCAPE #endif #endif #else @@ -244,12 +244,12 @@ // Power Loss // #if ENABLED(PSU_CONTROL) - #define PS_ON_PIN PG10 - #define POWER_LOSS_PIN PE1 + #define PS_ON_PIN PG10 + #define POWER_LOSS_PIN PE1 #endif // // Misc. Functions // -//#define LED_PIN PG10 -#define BEEPER_PIN PA8 +//#define LED_PIN PG10 +#define BEEPER_PIN PA8 From 6bc9ec1fddd887069d3416ceaf1991b1cef935f3 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Thu, 1 Feb 2024 15:13:17 -0600 Subject: [PATCH 16/22] etc --- Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h index 977cae0ab525..00bf9de93401 100644 --- a/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h +++ b/Marlin/src/pins/stm32f4/pins_TRONXY_CXY_446_V10.h @@ -162,8 +162,9 @@ // #define SPINDLE_LASER_ENA_PIN PB11 // WiFi Module TXD (Pin5) #define SPINDLE_LASER_PWM_PIN PB10 // WiFi Module RXD (Pin4) + // -// NOTE: The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be compounded here. +// NOTE: The PWM pin definition const PinMap PinMap_PWM[] in PeripheralPins.c must be augmented here. // See PWM_PIN(x) definition for details. // From 0908500e4b7b63099de6c0f387b3e7c4cd775581 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Thu, 1 Feb 2024 15:15:42 -0600 Subject: [PATCH 17/22] dead code --- buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py b/buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py index eb89791e561f..f3cb94a0620e 100644 --- a/buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py +++ b/buildroot/share/PlatformIO/scripts/tronxy_cxy_446_v10.py @@ -11,11 +11,6 @@ env = DefaultEnvironment() - # Already handled by offset_and_rename.py - #board = env.BoardConfig() - #if 'offset' in board.get("build").keys(): - # marlin.relocate_vtab(board.get('build.offset')) - # Check whether the "update" folder exists outpath = "update" if not os.path.exists(outpath): os.makedirs(outpath) From c49ef091dfaff0476ff2355ebeb020ad661584f3 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Thu, 1 Feb 2024 15:19:43 -0600 Subject: [PATCH 18/22] tweaks --- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index adf41329ccc5..2647923e8ee3 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -38,10 +38,10 @@ #define LCD_READ_ID4 0xD3 // Read display identification information (0xD3 on ILI9341) #endif -#define DATASIZE_8BIT SPI_DATASIZE_8BIT -#define DATASIZE_16BIT SPI_DATASIZE_16BIT -#define TFT_IO_DRIVER TFT_FSMC -#define DMA_MAX_WORDS 0xFFFF +#define DATASIZE_8BIT SPI_DATASIZE_8BIT +#define DATASIZE_16BIT SPI_DATASIZE_16BIT +#define TFT_IO_DRIVER TFT_FSMC +#define DMA_MAX_WORDS 0xFFFF #define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT) typedef TERN(TFT_INTERFACE_FSMC_8BIT, uint8_t, uint16_t) tft_data_t; @@ -64,7 +64,7 @@ class TFT_FSMC { static LCD_CONTROLLER_TypeDef *LCD; - static uint32_t readID(tft_data_t reg); + static uint32_t readID(tft_data_t inReg); static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); } static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count); static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count); @@ -76,10 +76,10 @@ class TFT_FSMC { static void abort(); static void dataTransferBegin(uint16_t dataWidth=TFT_DATASIZE) {} - static void dataTransferEnd() {}; + static void dataTransferEnd() {} static void writeData(uint16_t data) { transmit(tft_data_t(data)); } - static void writeReg(uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } + static void writeReg(const uint16_t inReg) { LCD->REG = tft_data_t(inReg); __DSB(); } static void writeSequence_DMA(uint16_t *data, uint16_t count) { transmitDMA(DMA_PINC_ENABLE, data, count); } static void writeMultiple_DMA(uint16_t color, uint16_t count) { static uint16_t data; data = color; transmitDMA(DMA_PINC_DISABLE, &data, count); } From 926a31121bf7f443d6456ea6e9c47f57e89abd6c Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Thu, 1 Feb 2024 15:25:05 -0600 Subject: [PATCH 19/22] board alert --- Marlin/src/pins/pins.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Marlin/src/pins/pins.h b/Marlin/src/pins/pins.h index 9f5ead671237..0a529ad60c3a 100644 --- a/Marlin/src/pins/pins.h +++ b/Marlin/src/pins/pins.h @@ -956,6 +956,7 @@ #define BOARD_LINUX_RAMPS 99926 #define BOARD_BTT_MANTA_M4P_V1_0 99927 #define BOARD_VAKE403D 99928 + #define BOARD_TRONXY_V10 99929 #if MB(MKS_13) #error "BOARD_MKS_13 is now BOARD_MKS_GEN_13. Please update your configuration." @@ -1015,6 +1016,8 @@ #error "BOARD_LINUX_RAMPS is now BOARD_SIMULATED. Please update your configuration." #elif MB(BTT_MANTA_M4P_V1_0) #error "BOARD_BTT_MANTA_M4P_V1_0 is now BOARD_BTT_MANTA_M4P_V2_1. Please update your configuration." + #elif MB(BOARD_TRONXY_V10) + #error "BOARD_TRONXY_V10 is now BOARD_TRONXY_CXY_446_V10. Please update your configuration." #elif MB(VAKE403D) #error "BOARD_VAKE403D is no longer supported in Marlin." #elif defined(MOTHERBOARD) @@ -1053,6 +1056,7 @@ #undef BOARD_LINUX_RAMPS #undef BOARD_BTT_MANTA_M4P_V1_0 #undef BOARD_VAKE403D + #undef BOARD_TRONXY_V10 #endif From 25765f077939f594c0074c5522936e8a9b01660f Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Thu, 1 Feb 2024 21:55:46 -0600 Subject: [PATCH 20/22] Update stm32f4.ini Cleaning up build flags we don't need. --- ini/stm32f4.ini | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/ini/stm32f4.ini b/ini/stm32f4.ini index 6fd457c91e3b..f661d9043cf7 100644 --- a/ini/stm32f4.ini +++ b/ini/stm32f4.ini @@ -820,8 +820,9 @@ board = marlin_STM32F446ZET_tronxy board_build.ldscript = buildroot/share/PlatformIO/variants/MARLIN_F446Zx_TRONXY/ldscript.ld board_build.offset = 0x10000 board_build.rename = fmw_tronxy.bin -build_flags = ${stm32_variant.build_flags} - -DSTM32F4xx -DUSE_USB_HS_IN_FS +build_flags = ${stm32_variant.build_flags} + -DSTM32F4xx -DUSE_USB_HS + -DUSE_USB_HS_IN_FS build_unflags = ${stm32_variant.build_unflags} -fno-rtti -fno-threadsafe-statics -fno-exceptions -DUSBD_USE_CDC -DUSBCON @@ -834,10 +835,6 @@ extra_scripts = ${stm32_variant.extra_scripts} [env:TRONXY_CXY_446_V10_usb_flash_drive] extends = env:TRONXY_CXY_446_V10 platform_packages = ${stm_flash_drive.platform_packages} -build_flags = ${env:TRONXY_CXY_446_V10.build_flags} - -DHAL_PCD_MODULE_ENABLED -DUSBHOST - -DUSBH_IRQ_PRIO=3 -DUSBH_IRQ_SUBPRIO=4 - -DUSBHOST_HS # # Blackpill From 427d2a732a99ef5ffe7c50dab54d4dd573474acd Mon Sep 17 00:00:00 2001 From: Smokey Pell Date: Thu, 1 Feb 2024 22:18:53 -0600 Subject: [PATCH 21/22] Update pins.h --- Marlin/src/pins/pins.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Marlin/src/pins/pins.h b/Marlin/src/pins/pins.h index 0a529ad60c3a..53d31c016819 100644 --- a/Marlin/src/pins/pins.h +++ b/Marlin/src/pins/pins.h @@ -1016,7 +1016,7 @@ #error "BOARD_LINUX_RAMPS is now BOARD_SIMULATED. Please update your configuration." #elif MB(BTT_MANTA_M4P_V1_0) #error "BOARD_BTT_MANTA_M4P_V1_0 is now BOARD_BTT_MANTA_M4P_V2_1. Please update your configuration." - #elif MB(BOARD_TRONXY_V10) + #elif MB(TRONXY_V10) #error "BOARD_TRONXY_V10 is now BOARD_TRONXY_CXY_446_V10. Please update your configuration." #elif MB(VAKE403D) #error "BOARD_VAKE403D is no longer supported in Marlin." From 5165ebeef445fc25bcc8484364b77aa54d38260f Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Sun, 4 Feb 2024 09:12:33 -0600 Subject: [PATCH 22/22] ws --- ini/stm32f4.ini | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ini/stm32f4.ini b/ini/stm32f4.ini index f661d9043cf7..fb8e9109cfd8 100644 --- a/ini/stm32f4.ini +++ b/ini/stm32f4.ini @@ -821,8 +821,8 @@ board_build.ldscript = buildroot/share/PlatformIO/variants/MARLIN_F446Zx_TRONXY/ board_build.offset = 0x10000 board_build.rename = fmw_tronxy.bin build_flags = ${stm32_variant.build_flags} - -DSTM32F4xx -DUSE_USB_HS - -DUSE_USB_HS_IN_FS + -DSTM32F4xx -DUSE_USB_HS + -DUSE_USB_HS_IN_FS build_unflags = ${stm32_variant.build_unflags} -fno-rtti -fno-threadsafe-statics -fno-exceptions -DUSBD_USE_CDC -DUSBCON @@ -833,8 +833,8 @@ extra_scripts = ${stm32_variant.extra_scripts} # TRONXY_CXY_446_V10 (STM32F446ZET6 ARM Cortex-M4) with USB Flash Drive Support # [env:TRONXY_CXY_446_V10_usb_flash_drive] -extends = env:TRONXY_CXY_446_V10 -platform_packages = ${stm_flash_drive.platform_packages} +extends = env:TRONXY_CXY_446_V10 +platform_packages = ${stm_flash_drive.platform_packages} # # Blackpill