[ 48.022851] tegradc 15210000.display: dp: plug event received [ 48.023202] hpd: state 3 (Disabled), hpd 1, pending_hpd_evt 1 [ 48.023358] hpd: switching from state 3 (Disabled) to state 0 (Reset) [ 48.124498] hpd: state 0 (Reset), hpd 1, pending_hpd_evt 0 [ 48.124728] tegradc 15210000.display: blank - powerdown [ 48.124969] extcon-disp-state external-connection:disp-state: cable 44 state 0 already set. [ 48.125251] Extcon DP: HPD disabled [ 48.125351] hpd: switching from state 0 (Reset) to state 1 (Check Plug) [ 48.125528] hpd: state 1 (Check Plug), hpd 1, pending_hpd_evt 0 [ 48.125675] hpd: switching from state 1 (Check Plug) to state 2 (Check EDID) [ 48.129496] tegradc 15210000.display: blank - powerdown [ 48.131250] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x200000 did not specify bpp [ 48.131547] tegradc 15210000.display: unblank [ 48.136381] hpd: state 2 (Check EDID), hpd 1, pending_hpd_evt 0 [ 48.143552] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd [ 48.144228] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd [ 48.144797] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd [ 48.158579] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x200000 did not specify bpp [ 48.169223] dp lt: state 4 (link training fail/disable), pending_lt_evt 1 [ 48.169231] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset) [ 48.169240] dp lt: state 0 (Reset), pending_lt_evt 0 [ 48.170750] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 48.170760] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 48.171012] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 48.171021] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 48.171029] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0 [ 48.171037] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0 [ 48.171045] dp lt: tx_pu: 0x20 [ 48.172021] dp lt: CR not done [ 48.172523] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172537] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172542] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172546] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172550] dp lt: CR retry [ 48.172556] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 48.172564] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 48.172576] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172583] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172591] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172600] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0 [ 48.172607] dp lt: tx_pu: 0x30 [ 48.173609] dp lt: CR not done [ 48.174098] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174103] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174108] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174112] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174122] dp lt: CR retry [ 48.174128] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 48.174136] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 48.174148] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174156] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174164] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174171] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0 [ 48.174178] dp lt: tx_pu: 0x40 [ 48.175159] dp lt: CR done [ 48.175166] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 48.175175] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 48.176855] dp lt: CE not done [ 48.177346] dp lt: new config: lane 0: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177352] dp lt: new config: lane 1: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177357] dp lt: new config: lane 2: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177362] dp lt: new config: lane 3: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177371] dp lt: config: lane 0: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177379] dp lt: config: lane 1: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177386] dp lt: config: lane 2: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177394] dp lt: config: lane 3: vs level: 2, pe level: 1, pc2 level: 0 [ 48.177400] dp lt: tx_pu: 0x60 [ 48.177680] dp lt: CE retry [ 48.177687] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 48.177722] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 48.179846] dp lt: CE done [ 48.179853] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 48.179991] extcon-disp-state external-connection:disp-state: cable 46 state 1 [ 48.179996] Extcon AUX0(DP): enable [ 48.466859] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x200000 did not specify bpp [ 48.467122] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.467364] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.467605] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.467864] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.468106] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.468686] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.468934] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.469176] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.469426] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.469673] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.469916] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.470173] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.470424] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.470666] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.470909] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.471147] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.471386] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 48.471627] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp [ 48.471881] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.472137] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.472781] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.473031] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.473285] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x400000 did not specify bpp [ 48.473553] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.473794] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.474046] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.474309] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 48.474551] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp [ 48.474791] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp [ 48.474799] tegradc 15210000.display: blank - powerdown [ 48.530614] dp lt: state 5 (link training pass), pending_lt_evt 1 [ 48.530622] dp lt: switching from state 5 (link training pass) to state 0 (Reset) [ 48.530628] dp lt: state 0 (Reset), pending_lt_evt 0 [ 48.530636] dp lt: link training force disable [ 48.530640] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable) [ 48.552540] extcon-disp-state external-connection:disp-state: cable 46 state 0 [ 48.552550] Extcon AUX0(DP) disable [ 48.554235] tegra_nvdisp_handle_pd_disable: Powergated Head2 pd [ 48.554411] tegra_nvdisp_handle_pd_disable: Powergated Head1 pd [ 48.555445] tegra_nvdisp_handle_pd_disable: Powergated Head0 pd [ 48.555752] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x200000 did not specify bpp [ 48.555766] tegradc 15210000.display: unblank [ 48.557192] tegra_nvdisp_handle_pd_enable: Unpowergated Head0 pd [ 48.557382] tegra_nvdisp_handle_pd_enable: Unpowergated Head1 pd [ 48.557595] tegra_nvdisp_handle_pd_enable: Unpowergated Head2 pd [ 48.560469] audit: type=1334 audit(1651224759.716:10): prog-id=10 op=UNLOAD [ 48.560483] audit: type=1334 audit(1651224759.716:11): prog-id=9 op=UNLOAD [ 48.562502] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x200000 did not specify bpp [ 48.572614] dp lt: state 4 (link training fail/disable), pending_lt_evt 1 [ 48.572622] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset) [ 48.572631] dp lt: state 0 (Reset), pending_lt_evt 0 [ 48.574127] dp lt: switching from state 0 (Reset) to state 2 (clock recovery) [ 48.574137] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 48.574387] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0 [ 48.574396] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0 [ 48.574403] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0 [ 48.574411] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0 [ 48.574418] dp lt: tx_pu: 0x20 [ 48.575391] dp lt: CR not done [ 48.575878] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575883] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575887] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575890] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575894] dp lt: CR retry [ 48.575899] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 48.575907] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 48.575917] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575925] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575932] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575939] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0 [ 48.575945] dp lt: tx_pu: 0x30 [ 48.576950] dp lt: CR not done [ 48.577455] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577460] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577464] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577467] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577470] dp lt: CR retry [ 48.577475] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery) [ 48.577483] dp lt: state 2 (clock recovery), pending_lt_evt 0 [ 48.577493] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577500] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577507] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577513] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0 [ 48.577520] dp lt: tx_pu: 0x40 [ 48.578514] dp lt: CR done [ 48.578521] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization) [ 48.578529] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 48.580009] dp lt: CE not done [ 48.580492] dp lt: new config: lane 0: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580497] dp lt: new config: lane 1: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580501] dp lt: new config: lane 2: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580504] dp lt: new config: lane 3: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580512] dp lt: config: lane 0: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580518] dp lt: config: lane 1: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580524] dp lt: config: lane 2: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580531] dp lt: config: lane 3: vs level: 2, pe level: 1, pc2 level: 0 [ 48.580538] dp lt: tx_pu: 0x60 [ 48.580813] dp lt: CE retry [ 48.580818] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization) [ 48.580826] dp lt: state 3 (channel equalization), pending_lt_evt 0 [ 48.582908] dp lt: CE done [ 48.582914] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass) [ 48.583019] extcon-disp-state external-connection:disp-state: cable 46 state 1 [ 48.583023] Extcon AUX0(DP): enable [ 49.194946] tegradc 15210000.display: unblank [ 49.199107] tegradc 15200000.display: blank - powerdown [ 49.199271] extcon-disp-state external-connection:disp-state: cable 44 state 1 [ 49.211747] Extcon DP: HPD enabled [ 49.215290] hpd: switching from state 2 (Check EDID) to state 4 (Enabled) [ 49.251656] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x200000 did not specify bpp [ 49.252184] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.252721] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.253208] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.253733] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.261174] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.268922] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.277076] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.284859] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.292481] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.300515] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.308394] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.315990] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.323877] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.332001] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.339918] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.347755] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.355625] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x0 did not specify bpp [ 49.363314] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp [ 49.372232] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 49.380822] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 49.389484] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 49.398151] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x400000 did not specify bpp [ 49.406335] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 49.415240] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 49.423893] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp [ 49.432568] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp [ 49.441040] tegradc 15210000.display: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp [ 49.452243] tegradc 15210000.display: unblank [ 49.453750] tegradc 15200000.display: blank - powerdown