From aedc817164be96e6190d30161ccdf389152e22ab Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Sun, 10 Sep 2023 15:32:10 +0800 Subject: [PATCH] CSR: default mstatus.SXL/UXL to b10 --- src/main/scala/nutcore/backend/fu/CSR.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/nutcore/backend/fu/CSR.scala b/src/main/scala/nutcore/backend/fu/CSR.scala index 51417cd6..7f736b84 100644 --- a/src/main/scala/nutcore/backend/fu/CSR.scala +++ b/src/main/scala/nutcore/backend/fu/CSR.scala @@ -275,13 +275,13 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ val marchid = RegInit(UInt(XLEN.W), 0.U) // return 0 to indicate the field is not implemented val mimpid = RegInit(UInt(XLEN.W), 0.U) // provides a unique encoding of the version of the processor implementation val mhartid = RegInit(UInt(XLEN.W), 0.U) // the hardware thread running the code - val mstatus = RegInit(UInt(XLEN.W), "h00001800".U) + val mstatus = RegInit(UInt(XLEN.W), "ha00001800".U) // val mstatus = RegInit(UInt(XLEN.W), "h8000c0100".U) // mstatus Value Table // | sd | // | pad1 | // | sxl | hardlinked to 10, use 00 to pass xv6 test - // | uxl | hardlinked to 00 + // | uxl | hardlinked to 10 // | pad0 | // | tsr | // | tw |