diff --git a/difftest b/difftest
index 4c1b283b4..b67ce6fda 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 4c1b283b420f09428caed537f16a06af53526ba9
+Subproject commit b67ce6fdaefa17265b06bc4e64eea3a616542c87
diff --git a/src/main/scala/device/AXI4RAM.scala b/src/main/scala/device/AXI4RAM.scala
index b2be09e63..ff6b4e59b 100644
--- a/src/main/scala/device/AXI4RAM.scala
+++ b/src/main/scala/device/AXI4RAM.scala
@@ -23,19 +23,7 @@ import chisel3.util.experimental.loadMemoryFromFile
 import nutcore.HasNutCoreParameter
 import bus.axi4._
 import utils._
-
-class RAMHelper(memByte: Int) extends BlackBox with HasNutCoreParameter {
-  val io = IO(new Bundle {
-    val clk = Input(Clock())
-    val rIdx = Input(UInt(DataBits.W))
-    val rdata = Output(UInt(DataBits.W))
-    val wIdx = Input(UInt(DataBits.W))
-    val wdata = Input(UInt(DataBits.W))
-    val wmask = Input(UInt(DataBits.W))
-    val wen = Input(Bool())
-    val en = Input(Bool())
-  }).suggestName("io")
-}
+import difftest.common.DifftestMem
 
 class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, memByte: Int,
   useBlackBox: Boolean = false) extends AXI4SlaveModule(_type) with HasNutCoreParameter {
@@ -50,23 +38,24 @@ class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, memByte: Int,
   val wen = in.w.fire() && inRange(wIdx)
 
   val rdata = if (useBlackBox) {
-    val mem = Module(new RAMHelper(memByte))
-    mem.io.clk := clock
-    mem.io.rIdx := rIdx
-    mem.io.wIdx := wIdx
-    mem.io.wdata := in.w.bits.data
-    mem.io.wmask := fullMask
-    mem.io.wen := wen
-    mem.io.en := true.B
-    mem.io.rdata
+    val mem = DifftestMem(memByte, 8)
+    when (wen) {
+      mem.write(
+        addr = wIdx,
+        data = in.w.bits.data.asTypeOf(Vec(DataBytes, UInt(8.W))),
+        mask = in.w.bits.strb.asBools
+      )
+    }
+    mem.readAndHold(rIdx, ren).asUInt
   } else {
     val mem = Mem(memByte / DataBytes, Vec(DataBytes, UInt(8.W)))
 
     val wdata = VecInit.tabulate(DataBytes) { i => in.w.bits.data(8*(i+1)-1, 8*i) }
     when (wen) { mem.write(wIdx, wdata, in.w.bits.strb.asBools) }
 
-    Cat(mem.read(rIdx).reverse)
+    RegEnable(Cat(mem.read(rIdx).reverse), ren)
   }
 
-  in.r.bits.data := RegEnable(rdata, ren)
+  in.r.bits.data := rdata
 }
+
diff --git a/src/test/vsrc/ram.v b/src/test/vsrc/ram.v
deleted file mode 100644
index 9f6a1cd5c..000000000
--- a/src/test/vsrc/ram.v
+++ /dev/null
@@ -1,41 +0,0 @@
-`ifdef RV32
-`define RAMWIDTH 32
-import "DPI-C" function void ram_helper
-(
-  input  int    rIdx,
-  output int    rdata,
-  input  int    wIdx,
-  input  int    wdata,
-  input  int    wmask,
-  input  bit    wen
-);
-`else
-`define RAMWIDTH 64
-import "DPI-C" function void ram_helper
-(
-  input  longint    rIdx,
-  output longint    rdata,
-  input  longint    wIdx,
-  input  longint    wdata,
-  input  longint    wmask,
-  input  bit    wen
-);
-`endif
-
-
-module RAMHelper(
-  input         clk,
-  input  [`RAMWIDTH-1:0] rIdx,
-  output [`RAMWIDTH-1:0] rdata,
-  input  [`RAMWIDTH-1:0] wIdx,
-  input  [`RAMWIDTH-1:0] wdata,
-  input  [`RAMWIDTH-1:0] wmask,
-  input         wen
-);
-
-  always @(posedge clk) begin
-    ram_helper(rIdx, rdata, wIdx, wdata, wmask, wen);
-  end
-
-endmodule
-