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submodule(ready-to-run): bump spike ref (#686)
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* spike commit: 5c1faa6b9d7c24cc77cace49c7fce1bf7347ed6c
* spike config: CPU=XIANGSHAN

Including:
    * fix(difftest): correct the bits of timer/external interrupts
    * fix(sstc): do not generate intr when writing CSR stimecmp
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cebarobot authored Nov 27, 2024
1 parent 2f6b69f commit 813ebce
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2 changes: 1 addition & 1 deletion ready-to-run

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