From 86e8dbe8530e3d9514cfbe4db9a2aa18260743d1 Mon Sep 17 00:00:00 2001 From: xuzefan Date: Thu, 27 Jul 2023 14:12:14 +0800 Subject: [PATCH 1/4] fix: compile error when enable NEMU debug --- src/isa/riscv64/include/isa-all-instr.h | 10 +++++----- src/isa/riscv64/instr/priv/exec.h | 6 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/isa/riscv64/include/isa-all-instr.h b/src/isa/riscv64/include/isa-all-instr.h index eda330a34..2852f3722 100644 --- a/src/isa/riscv64/include/isa-all-instr.h +++ b/src/isa/riscv64/include/isa-all-instr.h @@ -33,11 +33,11 @@ #define AMO_INSTR_TERNARY(f) f(atomic) #endif -#ifdef CONFIG_RV_DEBUG - #define RV_D_NULLARY(f) f(ebreak) -#else - #define RV_D_NULLARY(f) -#endif +// #ifdef CONFIG_RV_DEBUG +// #define RV_D_NULLARY(f) f(ebreak) +// #else +// #define RV_D_NULLARY(f) +// #endif #ifdef CONFIG_RVH #ifdef CONFIG_RV_SVINVAL diff --git a/src/isa/riscv64/instr/priv/exec.h b/src/isa/riscv64/instr/priv/exec.h index 4b94f1fe1..98b80e1a5 100644 --- a/src/isa/riscv64/instr/priv/exec.h +++ b/src/isa/riscv64/instr/priv/exec.h @@ -23,9 +23,9 @@ def_EHelper(name) { \ } #ifdef CONFIG_DEBUG -#ifdef CONFIG_RV_DEBUG - def_SYS_EHelper(ebreak) -#endif +// #ifdef CONFIG_RV_DEBUG +// def_SYS_EHelper(ebreak) +// #endif #ifdef CONFIG_RVH #define def_hld_template(name) \ From a66167f098faa69497fb9037a5702938530f3167 Mon Sep 17 00:00:00 2001 From: xuzefan Date: Thu, 27 Jul 2023 14:14:37 +0800 Subject: [PATCH 2/4] fix: ebreak problem when enable Performance optimization --- src/isa/riscv64/instr/decode.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/isa/riscv64/instr/decode.c b/src/isa/riscv64/instr/decode.c index f0f0c019a..53d8c9e61 100644 --- a/src/isa/riscv64/instr/decode.c +++ b/src/isa/riscv64/instr/decode.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "../include/isa-all-instr.h" def_all_THelper(); @@ -130,25 +130,26 @@ int isa_fetch_decode(Decode *s) { s->jnpc = id_dest->imm; s->type = INSTR_TYPE_B; break; case EXEC_ID_p_ret: case EXEC_ID_c_jr: case EXEC_ID_c_jalr: case EXEC_ID_jalr: - IFDEF(CONFIG_DEBUG, case EXEC_ID_mret: case EXEC_ID_sret: case EXEC_ID_ecall:) + IFDEF(CONFIG_DEBUG, case EXEC_ID_mret: case EXEC_ID_sret: case EXEC_ID_ecall: case EXEC_ID_ebreak:) s->type = INSTR_TYPE_I; break; #ifndef CONFIG_DEBUG #ifdef CONFIG_RVH case EXEC_ID_priv: -#else +#else // CONFIG_RVH case EXEC_ID_system: -#endif +#endif // CONFIG_RVH if (s->isa.instr.i.funct3 == 0) { switch (s->isa.instr.csr.csr) { - case 0: // ecall + case 0x0: // ecall + case 0x1: // ebreak case 0x102: // sret case 0x302: // mret s->type = INSTR_TYPE_I; } } break; -#endif +#endif // CONFIG_DEBUG } return idx; From 265f58f38de5f2f78d6418ba2567ab1ed4868b24 Mon Sep 17 00:00:00 2001 From: xuzefan Date: Fri, 28 Jul 2023 10:31:27 +0800 Subject: [PATCH 3/4] fix: flush tcache when changing virtualization mode --- src/isa/riscv64/system/intr.c | 4 +++- src/isa/riscv64/system/priv.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/isa/riscv64/system/intr.c b/src/isa/riscv64/system/intr.c index 793651c1a..2cbdf15e8 100644 --- a/src/isa/riscv64/system/intr.c +++ b/src/isa/riscv64/system/intr.c @@ -15,6 +15,7 @@ ***************************************************************************************/ #include +#include #include "../local-include/csr.h" #include "../local-include/intr.h" @@ -129,6 +130,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) { hstatus->spvp = cpu.mode; } cpu.v = 0; + set_sys_state_flag(SYS_STATE_FLUSH_TCACHE); #else if (delegS) { #endif @@ -162,7 +164,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) { mstatus->gva = (NO == EX_IGPF || NO == EX_LGPF || NO == EX_SGPF || ((v || hld_st_temp) && ((0 <= NO && NO <= 7 && NO != 2) || NO == EX_IPF || NO == EX_LPF || NO == EX_SPF))); mstatus->mpv = cpu.v; - cpu.v = 0; + cpu.v = 0;set_sys_state_flag(SYS_STATE_FLUSH_TCACHE); #endif mcause->val = NO; mepc->val = epc; diff --git a/src/isa/riscv64/system/priv.c b/src/isa/riscv64/system/priv.c index 12d9e4107..426b9e137 100644 --- a/src/isa/riscv64/system/priv.c +++ b/src/isa/riscv64/system/priv.c @@ -640,6 +640,7 @@ static word_t priv_instr(uint32_t op, const rtlreg_t *src) { if (cpu.v == 0){ cpu.v = hstatus->spv; hstatus->spv = 0; + set_sys_state_flag(SYS_STATE_FLUSH_TCACHE); }else if (cpu.v == 1){ if((cpu.mode == MODE_S && hstatus->vtsr) || cpu.mode < MODE_S){ longjmp_exception(EX_VI); @@ -684,6 +685,7 @@ static word_t priv_instr(uint32_t op, const rtlreg_t *src) { #ifdef CONFIG_RVH cpu.v = mstatus->mpv; mstatus->mpv = 0; + set_sys_state_flag(SYS_STATE_FLUSH_TCACHE); #endif // CONFIG_RVH if (mstatus->mpp != MODE_M) { mstatus->mprv = 0; } mstatus->mpp = MODE_U; From 80d4a08cd64f1daa353a7429ed711c3113fa09b5 Mon Sep 17 00:00:00 2001 From: xuzefan Date: Fri, 28 Jul 2023 16:27:58 +0800 Subject: [PATCH 4/4] fix: remove redundant code --- src/isa/riscv64/include/isa-all-instr.h | 6 ------ src/isa/riscv64/instr/priv/exec.h | 3 --- 2 files changed, 9 deletions(-) diff --git a/src/isa/riscv64/include/isa-all-instr.h b/src/isa/riscv64/include/isa-all-instr.h index 2852f3722..c8e87c5c6 100644 --- a/src/isa/riscv64/include/isa-all-instr.h +++ b/src/isa/riscv64/include/isa-all-instr.h @@ -33,12 +33,6 @@ #define AMO_INSTR_TERNARY(f) f(atomic) #endif -// #ifdef CONFIG_RV_DEBUG -// #define RV_D_NULLARY(f) f(ebreak) -// #else -// #define RV_D_NULLARY(f) -// #endif - #ifdef CONFIG_RVH #ifdef CONFIG_RV_SVINVAL #define RVH_INST_BINARY(f) f(hfence_vvma) f(hfence_gvma) f(hinval_vvma) f(hinval_gvma) \ diff --git a/src/isa/riscv64/instr/priv/exec.h b/src/isa/riscv64/instr/priv/exec.h index 98b80e1a5..bf8ba5287 100644 --- a/src/isa/riscv64/instr/priv/exec.h +++ b/src/isa/riscv64/instr/priv/exec.h @@ -23,9 +23,6 @@ def_EHelper(name) { \ } #ifdef CONFIG_DEBUG -// #ifdef CONFIG_RV_DEBUG -// def_SYS_EHelper(ebreak) -// #endif #ifdef CONFIG_RVH #define def_hld_template(name) \