From ee1123792e7aaa3ffdf3d86f883270131403227e Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Mon, 19 Jun 2023 09:35:50 +0800 Subject: [PATCH] Add config for update values of xtval on EX_II --- configs/riscv64-nutshell-ref_defconfig | 7 +++++++ configs/riscv64-xs-ref_defconfig | 7 +++++++ src/cpu/cpu-exec.c | 3 +++ src/isa/riscv64/Kconfig | 4 ++++ src/isa/riscv64/include/isa-def.h | 3 +++ src/isa/riscv64/system/intr.c | 6 ++++++ 6 files changed, 30 insertions(+) diff --git a/configs/riscv64-nutshell-ref_defconfig b/configs/riscv64-nutshell-ref_defconfig index 1b6c51d27..f00f7526d 100644 --- a/configs/riscv64-nutshell-ref_defconfig +++ b/configs/riscv64-nutshell-ref_defconfig @@ -19,13 +19,16 @@ CONFIG_CLINT_MMIO=0x38000000 # CONFIG_RVK is not set # CONFIG_RVV is not set # CONFIG_RV_DEBUG is not set +# CONFIG_RVH is not set CONFIG_RV_PMP_CSR=y CONFIG_RV_PMP_NUM=4 # CONFIG_RV_PMP_CHECK is not set # CONFIG_RV_SVINVAL is not set CONFIG_MISA_UNCHANGEABLE=y CONFIG_XTVEC_VECTORED_MODE=y +# CONFIG_TVAL_EX_II is not set # CONFIG_RV_ARCH_CSRS is not set +# CONFIG_PMPTABLE_EXTENSION is not set # end of ISA-dependent Options for riscv64 CONFIG_ENGINE_INTERPRETER=y @@ -71,6 +74,8 @@ CONFIG_DIFFTEST_REF_NAME="none" CONFIG_MBASE=0x80000000 CONFIG_MSIZE=0x80000000 CONFIG_PADDRBITS=32 +# CONFIG_STORE_LOG is not set +# CONFIG_BR_LOG is not set CONFIG_BBL_OFFSET_WITH_CPT=0xa0000 CONFIG_RESET_FROM_MMIO=y CONFIG_PC_RESET_OFFSET=0x0 @@ -81,6 +86,8 @@ CONFIG_USE_MMAP=y # end of Memory Configuration CONFIG_DEVICE=y +# CONFIG_HAS_UARTLITE is not set +# CONFIG_HAS_VGA is not set # CONFIG_HAS_FLASH is not set # CONFIG_FPU_HOST is not set # CONFIG_FPU_SOFT is not set diff --git a/configs/riscv64-xs-ref_defconfig b/configs/riscv64-xs-ref_defconfig index 5f98e2ab5..8d8e1e1ab 100644 --- a/configs/riscv64-xs-ref_defconfig +++ b/configs/riscv64-xs-ref_defconfig @@ -20,12 +20,15 @@ CONFIG_RVK=y # CONFIG_RVV is not set CONFIG_RV_DEBUG=y # CONFIG_RVH is not set +# CONFIG_RVSDEXT is not set +# CONFIG_RVSDTRIG is not set CONFIG_RV_PMP_CSR=y CONFIG_RV_PMP_NUM=16 CONFIG_RV_PMP_CHECK=y CONFIG_RV_SVINVAL=y CONFIG_MISA_UNCHANGEABLE=y CONFIG_XTVEC_VECTORED_MODE=y +# CONFIG_TVAL_EX_II is not set CONFIG_RV_ARCH_CSRS=y CONFIG_USE_XS_ARCH_CSRS=y # end of ISA-dependent Options for riscv64 @@ -73,6 +76,8 @@ CONFIG_DIFFTEST_REF_NAME="none" CONFIG_MBASE=0x80000000 CONFIG_MSIZE=0x200000000 CONFIG_PADDRBITS=36 +# CONFIG_STORE_LOG is not set +# CONFIG_BR_LOG is not set CONFIG_BBL_OFFSET_WITH_CPT=0xa0000 CONFIG_RESET_FROM_MMIO=y CONFIG_PC_RESET_OFFSET=0x0 @@ -83,6 +88,8 @@ CONFIG_USE_MMAP=y # end of Memory Configuration CONFIG_DEVICE=y +# CONFIG_HAS_UARTLITE is not set +# CONFIG_HAS_VGA is not set CONFIG_HAS_FLASH=y CONFIG_FLASH_PRESET_CONTENT="0x0010029b,0x01f29293,0x00028067" CONFIG_FLASH_START_ADDR=0x10000000 diff --git a/src/cpu/cpu-exec.c b/src/cpu/cpu-exec.c index 49e1e9e09..fdc1db73b 100644 --- a/src/cpu/cpu-exec.c +++ b/src/cpu/cpu-exec.c @@ -447,6 +447,9 @@ static int execute(int n) { fetch_decode(&s, cpu.pc); cpu.debug.current_pc = s.pc; cpu.pc = s.snpc; +#ifdef CONFIG_TVAL_EX_II + cpu.instr = s.isa.instr.val; +#endif #ifdef CONFIG_SHARE if (unlikely(dynamic_config.debug_difftest)) { fprintf(stderr, "(%d) [NEMU] pc = 0x%lx inst %x\n", getpid(), s.pc, s.isa.instr.val); diff --git a/src/isa/riscv64/Kconfig b/src/isa/riscv64/Kconfig index 06b88e193..42a35b0db 100644 --- a/src/isa/riscv64/Kconfig +++ b/src/isa/riscv64/Kconfig @@ -72,6 +72,10 @@ config XTVEC_VECTORED_MODE bool "Support Vectored MODE of mtvec/stvec" default y +config TVAL_EX_II + bool "Update m/stval on illegal instruction exceptions" + default n + config RV_ARCH_CSRS bool "Enable mvendorid, marchid, mimpid CSR" default y diff --git a/src/isa/riscv64/include/isa-def.h b/src/isa/riscv64/include/isa-def.h index 3168d9d67..5024678cd 100644 --- a/src/isa/riscv64/include/isa-def.h +++ b/src/isa/riscv64/include/isa-def.h @@ -102,6 +102,9 @@ typedef struct { bool amo; int mem_exception; +#ifdef CONFIG_TVAL_EX_II + uint32_t instr; +#endif // for LR/SC uint64_t lr_addr; uint64_t lr_valid; diff --git a/src/isa/riscv64/system/intr.c b/src/isa/riscv64/system/intr.c index 2cbdf15e8..2748b5ca7 100644 --- a/src/isa/riscv64/system/intr.c +++ b/src/isa/riscv64/system/intr.c @@ -149,6 +149,9 @@ word_t raise_intr(word_t NO, vaddr_t epc) { case EX_IGPF: case EX_LGPF: case EX_SGPF: #endif break; +#ifdef CONFIG_TVAL_EX_II + case EX_II: stval->val = cpu.instr; break; +#endif default: stval->val = 0; #ifdef CONFIG_RVH htval->val = 0; @@ -181,6 +184,9 @@ word_t raise_intr(word_t NO, vaddr_t epc) { case EX_IGPF: case EX_LGPF: case EX_SGPF: #endif break; +#ifdef CONFIG_TVAL_EX_II + case EX_II: mtval->val = cpu.instr; break; +#endif default: mtval->val = 0; #ifdef CONFIG_RVH mtval2->val = 0;