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fix(watchpoint): support set watchpoint on every 64 bits for vreg. #683

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Nov 26, 2024
+11 −3
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fix(watchpoint): support set watchpoint on every 64 bits for vreg. #683

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13 changes: 10 additions & 3 deletions src/isa/riscv64/reg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,13 @@
* See the Mulan PSL v2 for more details.
***************************************************************************************/

#include <stdlib.h>
#include <isa.h>
//#include <monitor/difftest.h>
#include "local-include/reg.h"
#include "local-include/csr.h"
#include "local-include/trigger.h"
#include "instr/rvv/vreg.h"
//#include "local-include/intr.h"

const char *regsl[] = {
Expand Down Expand Up @@ -146,9 +148,14 @@ rtlreg_t isa_reg_str2val(const char *s, bool *success) {

#ifdef CONFIG_RVV
//vector register
extern const char * vregsl[];
for (i = 0; i < 32; i ++) {
if (strcmp(vregsl[i], s) == 0) return cpu.vr[i]._64[0];
const char *underscore_pos = strchr(s, '_');
if (underscore_pos != NULL) {
size_t prefix_len = underscore_pos - s;
int offset = atoi(underscore_pos + 1);
extern const char * vregsl[];
for (i = 0; i < 32; i ++) {
if (strncmp(vregsl[i], s, prefix_len) == 0) return vreg_l(i, offset);
}
}
#endif // CONFIG_RVV

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1 change: 1 addition & 0 deletions src/utils/expr.c
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Expand Up @@ -44,6 +44,7 @@ static struct rule {
{"==", TK_EQ}, // equal
{"0x[0-9a-fA-F]{1,16}", TK_NUM}, // hex
{"[0-9]{1,10}", TK_NUM}, // dec
{"\\$v[0-9]{1,2}_[0-9]{1,10}", TK_REG}, // vector register, e.g. $v0_0 represents first 64 bits of v0 in RVV
{"\\$[a-z0-9]{1,31}", TK_REG}, // register names
{"\\+", '+'},
{"-", '-'},
Expand Down