From af3eaba07c439e2f4ca4e48465af7da95fefb868 Mon Sep 17 00:00:00 2001
From: Tang Haojin <tanghaojin@outlook.com>
Date: Thu, 17 Oct 2024 09:26:57 +0800
Subject: [PATCH] timing(IMSIC): AXI4 output should be buffered (#3757)

---
 src/main/scala/device/imsic_axi_top.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/device/imsic_axi_top.scala b/src/main/scala/device/imsic_axi_top.scala
index a907495fb6..72de20ac36 100644
--- a/src/main/scala/device/imsic_axi_top.scala
+++ b/src/main/scala/device/imsic_axi_top.scala
@@ -146,7 +146,7 @@ class imsic_bus_top(
     )))
     val xbar = AXI4Xbar(TLArbiter.lowestIndexFirst)
     axi4nodes.foreach { _ := xbar }
-    xbar := node
+    xbar := AXI4Buffer() := node
     node
   }