diff --git a/src/main/scala/yunsuan/vector/VectorALU/VAluBundles.scala b/src/main/scala/yunsuan/vector/VectorALU/VAluBundles.scala
index f0a5d01..4c129f1 100644
--- a/src/main/scala/yunsuan/vector/VectorALU/VAluBundles.scala
+++ b/src/main/scala/yunsuan/vector/VectorALU/VAluBundles.scala
@@ -52,7 +52,7 @@ class VAluOpcode extends Bundle{
   def isIntFixp = op < vredsum || op === vmvsx
   def isVmvsx = op === vmvsx
   def isVmvxs = op === vmvxs
-  def isVmergeMove = op === vmerge || op === vmvsx
+  def isVmergeMove = op === vmerge || op === vmv || op === vmvsx
   // IMac opcode:
   def op3b = op(2, 0)
   def highHalf = op3b === 1.U