From ef718d88098c09b6a6f0d91b485fefbdedaadcb8 Mon Sep 17 00:00:00 2001
From: sinceforYy <1017657683@qq.com>
Date: Thu, 12 Oct 2023 12:33:44 +0800
Subject: [PATCH] fix CVT32 warn&bug & rm useless comment

---
 src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala     | 6 +++---
 .../yunsuan/vector/VectorConvert/util/ShiftRightJam.scala   | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala b/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala
index dac9df3..fcfa05f 100644
--- a/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala
+++ b/src/main/scala/yunsuan/vector/VectorConvert/CVT32.scala
@@ -657,7 +657,7 @@ class CVT32(width: Int = 32) extends CVT(width){
   val exp_delta = VectorFloat.expBias(f32.expWidth) - VectorFloat.expBias(f16.expWidth)
 
   val down_exp_s = fp_in.exp.zext - exp_delta.S
-  val down_exp = Wire(UInt(8.W))
+  val down_exp = Wire(UInt(9.W))
   val down_exp_reg0 = RegNext(down_exp)
   down_exp := down_exp_s.asUInt
 
@@ -668,7 +668,7 @@ class CVT32(width: Int = 32) extends CVT(width){
   nor_signBit := fp_in.sign
 
   // subnormal
-  val shamt = (exp_delta + 1).U(f32.expWidth) - fp_in.exp
+  val shamt = (exp_delta + 1).U(f32.expWidth.W) - fp_in.exp
   val (subnor_sig, shift_sticky) = ShiftRightJam(Cat(fp_in.decode.expNotZero, fp_in.sig.head(f16.precision)), shamt)
   subnor_in := subnor_sig.tail(1).head(f16.precision - 1)
   subnor_roundBit := subnor_sig(0)
@@ -677,7 +677,7 @@ class CVT32(width: Int = 32) extends CVT(width){
 
   val may_be_subnor = Wire(Bool())
   val may_be_subnor_reg0 = RegNext(may_be_subnor)
-  may_be_subnor := down_exp.asSInt < 1.S
+  may_be_subnor := down_exp_s < 1.S
 
   val rmin = is_fp2fp && is_narrow &&  (io.rm === RTZ || (io.rm === RDN & !fp_in.sign) || (io.rm === RUP && fp_in.sign))
 
diff --git a/src/main/scala/yunsuan/vector/VectorConvert/util/ShiftRightJam.scala b/src/main/scala/yunsuan/vector/VectorConvert/util/ShiftRightJam.scala
index 85285d2..0888fe5 100644
--- a/src/main/scala/yunsuan/vector/VectorConvert/util/ShiftRightJam.scala
+++ b/src/main/scala/yunsuan/vector/VectorConvert/util/ShiftRightJam.scala
@@ -7,7 +7,7 @@ import chisel3.util._
  * in => shift | collect sticky bit => {in_shifted, sticky}
  */
 class ShiftRightJam(val len: Int) extends Module {
-  val max_shift_width = log2Up(len + 1) //??
+  val max_shift_width = log2Up(len + 1) 
   val io = IO(new Bundle() {
     val in = Input(UInt(len.W))
     val shamt = Input(UInt())
@@ -17,9 +17,9 @@ class ShiftRightJam(val len: Int) extends Module {
   val exceed_max_shift = io.shamt > len.U
   val shamt = io.shamt(max_shift_width - 1, 0)
   val sticky_mask =
-    ((1.U << shamt).asUInt - 1.U)(len - 1, 0) | Fill(len, exceed_max_shift) //移出去那几位的mask
+    ((1.U << shamt).asUInt - 1.U)(len - 1, 0) | Fill(len, exceed_max_shift)
   io.out := Mux(exceed_max_shift, 0.U, io.in >> io.shamt)
-  io.sticky := (io.in & sticky_mask).orR //看移出去的这几位是否sticky
+  io.sticky := (io.in & sticky_mask).orR 
 }
 
 object ShiftRightJam {