From 568ad9682c47f5ed811f0ca86de5a20e3d301759 Mon Sep 17 00:00:00 2001 From: HeiHuDie <1042519051@qq.com> Date: Thu, 28 Nov 2024 23:38:15 +0800 Subject: [PATCH] fix(FloatAdder): res_is_f32_reg is used before declaration --- src/main/scala/yunsuan/fpu/FloatAdder.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/yunsuan/fpu/FloatAdder.scala b/src/main/scala/yunsuan/fpu/FloatAdder.scala index a33a94a..51300c4 100644 --- a/src/main/scala/yunsuan/fpu/FloatAdder.scala +++ b/src/main/scala/yunsuan/fpu/FloatAdder.scala @@ -202,9 +202,9 @@ private[fpu] class FloatAdderF32F16MixedPipeline(val is_print:Boolean = false,va } val round_to_negative = io.round_mode==="b010".U & EOP val res_negative = fp_a_to32.head(1).asBool & !EOP + val res_is_f32_reg = RegEnable(res_is_f32, fire) val fadd0_result0 = Mux(res_is_f32_reg,Cat(RegEnable(Mux(round_to_negative | res_negative,1.U,0.U), fire),0.U(31.W)),Cat(RegEnable(Mux(round_to_negative | res_negative,Fill(17,1.U),0.U(17.W)), fire),0.U(15.W))) val fadd0_result1 = Mux(res_is_f32_reg,RegEnable(Cat(io.is_sub ^ io.fp_b(31),io.fp_b(30,0)), fire),RegEnable(Cat(0.U(16.W),Cat(io.is_sub ^ io.fp_b(15),io.fp_b(14,0))), fire)) - val res_is_f32_reg = RegEnable(res_is_f32, fire) val out_NAN_reg = Mux(res_is_f32_reg, Cat(0.U,Fill(8,1.U),1.U,0.U(22.W)), Cat(0.U(17.W),Fill(5,1.U),1.U,0.U(9.W))) val out_infinite_sign = Mux(fp_a_is_infinite,fp_a_to32.head(1),io.is_sub^fp_b_to32.head(1)) val out_infinite_sign_reg = RegEnable(out_infinite_sign, fire)